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targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:
mbed_official
Date:
Tue Apr 19 11:15:15 2016 +0100
Revision:
113:b3775bf36a83
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd



Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/



Exporter tool addition for e2 studio

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l073xx.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 113:b3775bf36a83 5 * @version V1.5.0
mbed_official 113:b3775bf36a83 6 * @date 8-January-2016
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
bogdanm 0:9b334a45a8ff 8 * This file contains all the peripheral register's definitions, bits
bogdanm 0:9b334a45a8ff 9 * definitions and memory mapping for stm32l073xx devices.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * This file contains:
bogdanm 0:9b334a45a8ff 12 * - Data structures and the address mapping for all peripherals
bogdanm 0:9b334a45a8ff 13 * - Peripheral's registers declarations and bits definition
bogdanm 0:9b334a45a8ff 14 * - Macros to access peripheral's registers hardware
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 ******************************************************************************
bogdanm 0:9b334a45a8ff 17 * @attention
bogdanm 0:9b334a45a8ff 18 *
mbed_official 113:b3775bf36a83 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 22 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 23 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 26 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 27 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 29 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 30 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 31 *
bogdanm 0:9b334a45a8ff 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 ******************************************************************************
bogdanm 0:9b334a45a8ff 44 */
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @addtogroup stm32l073xx
bogdanm 0:9b334a45a8ff 51 * @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 #ifndef __STM32L073xx_H
bogdanm 0:9b334a45a8ff 55 #define __STM32L073xx_H
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 58 extern "C" {
bogdanm 0:9b334a45a8ff 59 #endif
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 0:9b334a45a8ff 63 * @{
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 /**
bogdanm 0:9b334a45a8ff 66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
bogdanm 0:9b334a45a8ff 69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
bogdanm 0:9b334a45a8ff 70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
bogdanm 0:9b334a45a8ff 71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
bogdanm 0:9b334a45a8ff 72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /**
bogdanm 0:9b334a45a8ff 75 * @}
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 0:9b334a45a8ff 79 * @{
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /**
bogdanm 0:9b334a45a8ff 83 * @brief stm32l073xx Interrupt Number Definition, according to the selected device
bogdanm 0:9b334a45a8ff 84 * in @ref Library_configuration_section
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /*!< Interrupt Number Definition */
bogdanm 0:9b334a45a8ff 88 typedef enum
bogdanm 0:9b334a45a8ff 89 {
bogdanm 0:9b334a45a8ff 90 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
bogdanm 0:9b334a45a8ff 91 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 92 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 93 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
bogdanm 0:9b334a45a8ff 94 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 95 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
bogdanm 0:9b334a45a8ff 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 0:9b334a45a8ff 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
bogdanm 0:9b334a45a8ff 100 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
bogdanm 0:9b334a45a8ff 101 FLASH_IRQn = 3, /*!< FLASH Interrupt */
bogdanm 0:9b334a45a8ff 102 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
bogdanm 0:9b334a45a8ff 103 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
bogdanm 0:9b334a45a8ff 104 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
bogdanm 0:9b334a45a8ff 105 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
bogdanm 0:9b334a45a8ff 106 TSC_IRQn = 8, /*!< TSC Interrupt */
bogdanm 0:9b334a45a8ff 107 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
bogdanm 0:9b334a45a8ff 108 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
bogdanm 0:9b334a45a8ff 109 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
bogdanm 0:9b334a45a8ff 110 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
bogdanm 0:9b334a45a8ff 111 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
bogdanm 0:9b334a45a8ff 112 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
bogdanm 0:9b334a45a8ff 113 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
bogdanm 0:9b334a45a8ff 114 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
bogdanm 0:9b334a45a8ff 115 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
bogdanm 0:9b334a45a8ff 116 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
bogdanm 0:9b334a45a8ff 117 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
bogdanm 0:9b334a45a8ff 118 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
bogdanm 0:9b334a45a8ff 119 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
bogdanm 0:9b334a45a8ff 120 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
bogdanm 0:9b334a45a8ff 121 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
bogdanm 0:9b334a45a8ff 122 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
bogdanm 0:9b334a45a8ff 123 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
bogdanm 0:9b334a45a8ff 124 USART1_IRQn = 27, /*!< USART1 Interrupt */
bogdanm 0:9b334a45a8ff 125 USART2_IRQn = 28, /*!< USART2 Interrupt */
bogdanm 0:9b334a45a8ff 126 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
bogdanm 0:9b334a45a8ff 127 LCD_IRQn = 30, /*!< LCD Interrupt */
bogdanm 0:9b334a45a8ff 128 USB_IRQn = 31, /*!< USB global Interrupt */
bogdanm 0:9b334a45a8ff 129 } IRQn_Type;
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @}
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 #include "core_cm0plus.h"
bogdanm 0:9b334a45a8ff 136 #include "system_stm32l0xx.h"
bogdanm 0:9b334a45a8ff 137 #include <stdint.h>
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /** @addtogroup Peripheral_registers_structures
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /**
bogdanm 0:9b334a45a8ff 144 * @brief Analog to Digital Converter
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 typedef struct
bogdanm 0:9b334a45a8ff 148 {
bogdanm 0:9b334a45a8ff 149 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
bogdanm 0:9b334a45a8ff 150 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
bogdanm 0:9b334a45a8ff 151 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
bogdanm 0:9b334a45a8ff 152 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
bogdanm 0:9b334a45a8ff 153 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
bogdanm 0:9b334a45a8ff 154 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
bogdanm 0:9b334a45a8ff 155 uint32_t RESERVED1; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 156 uint32_t RESERVED2; /*!< Reserved, 0x1C */
bogdanm 0:9b334a45a8ff 157 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
bogdanm 0:9b334a45a8ff 158 uint32_t RESERVED3; /*!< Reserved, 0x24 */
bogdanm 0:9b334a45a8ff 159 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
bogdanm 0:9b334a45a8ff 160 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
bogdanm 0:9b334a45a8ff 161 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
bogdanm 0:9b334a45a8ff 162 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
bogdanm 0:9b334a45a8ff 163 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
bogdanm 0:9b334a45a8ff 164 } ADC_TypeDef;
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 typedef struct
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 169 } ADC_Common_TypeDef;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /**
bogdanm 0:9b334a45a8ff 173 * @brief Comparator
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 typedef struct
bogdanm 0:9b334a45a8ff 177 {
bogdanm 0:9b334a45a8ff 178 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 179 } COMP_TypeDef;
bogdanm 0:9b334a45a8ff 180
mbed_official 113:b3775bf36a83 181 typedef struct
mbed_official 113:b3775bf36a83 182 {
mbed_official 113:b3775bf36a83 183 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
mbed_official 113:b3775bf36a83 184 } COMP_Common_TypeDef;
mbed_official 113:b3775bf36a83 185
mbed_official 113:b3775bf36a83 186
mbed_official 113:b3775bf36a83 187 /**
mbed_official 113:b3775bf36a83 188 * @brief CRC calculation unit
mbed_official 113:b3775bf36a83 189 */
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 typedef struct
bogdanm 0:9b334a45a8ff 192 {
mbed_official 113:b3775bf36a83 193 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 113:b3775bf36a83 194 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 113:b3775bf36a83 195 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 113:b3775bf36a83 196 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 113:b3775bf36a83 197 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 113:b3775bf36a83 198 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 113:b3775bf36a83 199 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 113:b3775bf36a83 200 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 201 } CRC_TypeDef;
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /**
bogdanm 0:9b334a45a8ff 204 * @brief Clock Recovery System
bogdanm 0:9b334a45a8ff 205 */
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 typedef struct
bogdanm 0:9b334a45a8ff 208 {
bogdanm 0:9b334a45a8ff 209 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 210 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 212 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 213 } CRS_TypeDef;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /**
bogdanm 0:9b334a45a8ff 216 * @brief Digital to Analog Converter
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 typedef struct
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 222 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 223 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 224 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 225 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 226 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 227 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 228 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 229 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 230 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 231 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 232 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 233 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 234 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 235 } DAC_TypeDef;
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /**
bogdanm 0:9b334a45a8ff 238 * @brief Debug MCU
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 typedef struct
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 244 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 245 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 246 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 247 }DBGMCU_TypeDef;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /**
bogdanm 0:9b334a45a8ff 250 * @brief DMA Controller
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 typedef struct
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 0:9b334a45a8ff 256 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 0:9b334a45a8ff 257 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 0:9b334a45a8ff 258 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 0:9b334a45a8ff 259 } DMA_Channel_TypeDef;
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 typedef struct
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 264 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 265 } DMA_TypeDef;
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 typedef struct
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
bogdanm 0:9b334a45a8ff 270 } DMA_Request_TypeDef;
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /**
bogdanm 0:9b334a45a8ff 273 * @brief External Interrupt/Event Controller
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 typedef struct
bogdanm 0:9b334a45a8ff 277 {
bogdanm 0:9b334a45a8ff 278 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 279 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 280 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 281 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 282 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 283 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 284 }EXTI_TypeDef;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /**
bogdanm 0:9b334a45a8ff 287 * @brief FLASH Registers
bogdanm 0:9b334a45a8ff 288 */
bogdanm 0:9b334a45a8ff 289 typedef struct
bogdanm 0:9b334a45a8ff 290 {
bogdanm 0:9b334a45a8ff 291 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 292 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 293 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 294 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
bogdanm 0:9b334a45a8ff 295 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 296 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 297 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 298 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
bogdanm 0:9b334a45a8ff 299 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 300 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 301 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 302 } FLASH_TypeDef;
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /**
bogdanm 0:9b334a45a8ff 306 * @brief Option Bytes Registers
bogdanm 0:9b334a45a8ff 307 */
bogdanm 0:9b334a45a8ff 308 typedef struct
bogdanm 0:9b334a45a8ff 309 {
bogdanm 0:9b334a45a8ff 310 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 311 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 312 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 313 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 314 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 315 } OB_TypeDef;
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief General Purpose IO
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 typedef struct
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 325 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 326 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 327 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 328 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 329 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 330 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 331 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 332 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
bogdanm 0:9b334a45a8ff 333 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 334 }GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /**
bogdanm 0:9b334a45a8ff 337 * @brief LPTIMIMER
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 typedef struct
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 342 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 343 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 344 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 345 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 346 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 347 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 348 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 349 } LPTIM_TypeDef;
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /**
bogdanm 0:9b334a45a8ff 352 * @brief SysTem Configuration
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 typedef struct
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 358 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 359 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
bogdanm 0:9b334a45a8ff 360 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 0:9b334a45a8ff 361 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 362 } SYSCFG_TypeDef;
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @brief Inter-integrated Circuit Interface
bogdanm 0:9b334a45a8ff 368 */
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 typedef struct
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 373 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 374 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 375 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 376 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 377 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 378 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 379 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 380 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 381 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 382 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 383 }I2C_TypeDef;
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /**
bogdanm 0:9b334a45a8ff 387 * @brief Independent WATCHDOG
bogdanm 0:9b334a45a8ff 388 */
bogdanm 0:9b334a45a8ff 389 typedef struct
bogdanm 0:9b334a45a8ff 390 {
bogdanm 0:9b334a45a8ff 391 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 392 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 393 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 394 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 395 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 396 } IWDG_TypeDef;
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /**
bogdanm 0:9b334a45a8ff 399 * @brief LCD
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401 typedef struct
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 404 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 405 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 406 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 407 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 408 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
bogdanm 0:9b334a45a8ff 409 } LCD_TypeDef;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /**
bogdanm 0:9b334a45a8ff 412 * @brief MIFARE Firewall
bogdanm 0:9b334a45a8ff 413 */
bogdanm 0:9b334a45a8ff 414 typedef struct
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 417 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 418 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 419 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 420 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 421 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 422 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 423 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 424 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 425
mbed_official 113:b3775bf36a83 426 } FIREWALL_TypeDef;
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @brief Power Control
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431 typedef struct
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 434 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 435 } PWR_TypeDef;
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /**
bogdanm 0:9b334a45a8ff 438 * @brief Reset and Clock Control
bogdanm 0:9b334a45a8ff 439 */
bogdanm 0:9b334a45a8ff 440 typedef struct
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 443 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 444 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 445 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 446 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 447 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 448 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 449 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 450 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 451 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 452 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 453 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 454 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 455 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 456 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 457 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 458 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 459 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 462 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 463 } RCC_TypeDef;
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /**
bogdanm 0:9b334a45a8ff 466 * @brief Random numbers generator
bogdanm 0:9b334a45a8ff 467 */
bogdanm 0:9b334a45a8ff 468 typedef struct
bogdanm 0:9b334a45a8ff 469 {
bogdanm 0:9b334a45a8ff 470 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 471 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 472 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 473 } RNG_TypeDef;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /**
bogdanm 0:9b334a45a8ff 476 * @brief Real-Time Clock
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478 typedef struct
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 486 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 488 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 495 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 496 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 498 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 499 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
bogdanm 0:9b334a45a8ff 500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 505 } RTC_TypeDef;
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /**
bogdanm 0:9b334a45a8ff 509 * @brief Serial Peripheral Interface
bogdanm 0:9b334a45a8ff 510 */
bogdanm 0:9b334a45a8ff 511 typedef struct
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 514 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 515 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 516 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 517 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 518 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 519 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 520 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 521 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 522 } SPI_TypeDef;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /**
bogdanm 0:9b334a45a8ff 525 * @brief TIM
bogdanm 0:9b334a45a8ff 526 */
bogdanm 0:9b334a45a8ff 527 typedef struct
bogdanm 0:9b334a45a8ff 528 {
mbed_official 113:b3775bf36a83 529 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 113:b3775bf36a83 530 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 113:b3775bf36a83 531 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 113:b3775bf36a83 532 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 113:b3775bf36a83 533 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 113:b3775bf36a83 534 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 113:b3775bf36a83 535 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 113:b3775bf36a83 536 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 113:b3775bf36a83 537 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 113:b3775bf36a83 538 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 113:b3775bf36a83 539 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 113:b3775bf36a83 540 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 113:b3775bf36a83 541 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
mbed_official 113:b3775bf36a83 542 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 113:b3775bf36a83 543 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 113:b3775bf36a83 544 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 113:b3775bf36a83 545 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 113:b3775bf36a83 546 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
mbed_official 113:b3775bf36a83 547 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 113:b3775bf36a83 548 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 113:b3775bf36a83 549 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 550 } TIM_TypeDef;
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /**
bogdanm 0:9b334a45a8ff 553 * @brief Touch Sensing Controller (TSC)
bogdanm 0:9b334a45a8ff 554 */
bogdanm 0:9b334a45a8ff 555 typedef struct
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 558 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 559 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 560 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 561 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 562 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 563 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 564 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 565 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 566 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 567 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 568 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 569 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 570 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 0:9b334a45a8ff 571 } TSC_TypeDef;
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 /**
bogdanm 0:9b334a45a8ff 574 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 0:9b334a45a8ff 575 */
bogdanm 0:9b334a45a8ff 576 typedef struct
bogdanm 0:9b334a45a8ff 577 {
bogdanm 0:9b334a45a8ff 578 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 579 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 580 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 581 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 582 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 583 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 584 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 585 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 586 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 587 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 588 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 589 } USART_TypeDef;
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /**
bogdanm 0:9b334a45a8ff 592 * @brief Window WATCHDOG
bogdanm 0:9b334a45a8ff 593 */
bogdanm 0:9b334a45a8ff 594 typedef struct
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 597 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 598 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 599 } WWDG_TypeDef;
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /**
bogdanm 0:9b334a45a8ff 602 * @brief Universal Serial Bus Full Speed Device
bogdanm 0:9b334a45a8ff 603 */
bogdanm 0:9b334a45a8ff 604 typedef struct
bogdanm 0:9b334a45a8ff 605 {
bogdanm 0:9b334a45a8ff 606 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 607 __IO uint16_t RESERVED0; /*!< Reserved */
bogdanm 0:9b334a45a8ff 608 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 609 __IO uint16_t RESERVED1; /*!< Reserved */
bogdanm 0:9b334a45a8ff 610 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 611 __IO uint16_t RESERVED2; /*!< Reserved */
bogdanm 0:9b334a45a8ff 612 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 613 __IO uint16_t RESERVED3; /*!< Reserved */
bogdanm 0:9b334a45a8ff 614 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 615 __IO uint16_t RESERVED4; /*!< Reserved */
bogdanm 0:9b334a45a8ff 616 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 617 __IO uint16_t RESERVED5; /*!< Reserved */
bogdanm 0:9b334a45a8ff 618 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 619 __IO uint16_t RESERVED6; /*!< Reserved */
bogdanm 0:9b334a45a8ff 620 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 621 __IO uint16_t RESERVED7[17]; /*!< Reserved */
bogdanm 0:9b334a45a8ff 622 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 623 __IO uint16_t RESERVED8; /*!< Reserved */
bogdanm 0:9b334a45a8ff 624 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 625 __IO uint16_t RESERVED9; /*!< Reserved */
bogdanm 0:9b334a45a8ff 626 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 627 __IO uint16_t RESERVEDA; /*!< Reserved */
bogdanm 0:9b334a45a8ff 628 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 629 __IO uint16_t RESERVEDB; /*!< Reserved */
bogdanm 0:9b334a45a8ff 630 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 631 __IO uint16_t RESERVEDC; /*!< Reserved */
bogdanm 0:9b334a45a8ff 632 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 633 __IO uint16_t RESERVEDD; /*!< Reserved */
bogdanm 0:9b334a45a8ff 634 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 635 __IO uint16_t RESERVEDE; /*!< Reserved */
bogdanm 0:9b334a45a8ff 636 } USB_TypeDef;
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /**
bogdanm 0:9b334a45a8ff 639 * @}
bogdanm 0:9b334a45a8ff 640 */
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 /** @addtogroup Peripheral_memory_map
bogdanm 0:9b334a45a8ff 643 * @{
bogdanm 0:9b334a45a8ff 644 */
mbed_official 113:b3775bf36a83 645 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
mbed_official 113:b3775bf36a83 646 #define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
mbed_official 113:b3775bf36a83 647 #define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
mbed_official 113:b3775bf36a83 648 #define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
mbed_official 113:b3775bf36a83 649 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
mbed_official 113:b3775bf36a83 650 #define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
mbed_official 113:b3775bf36a83 651 #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
mbed_official 113:b3775bf36a83 652 #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
mbed_official 113:b3775bf36a83 653 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
mbed_official 113:b3775bf36a83 654 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /*!< Peripheral memory map */
bogdanm 0:9b334a45a8ff 657 #define APBPERIPH_BASE PERIPH_BASE
bogdanm 0:9b334a45a8ff 658 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 0:9b334a45a8ff 659 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 662 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 663 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 664 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
bogdanm 0:9b334a45a8ff 665 #define LCD_BASE (APBPERIPH_BASE + 0x00002400)
bogdanm 0:9b334a45a8ff 666 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
bogdanm 0:9b334a45a8ff 667 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
bogdanm 0:9b334a45a8ff 668 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 669 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
bogdanm 0:9b334a45a8ff 670 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
bogdanm 0:9b334a45a8ff 671 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
bogdanm 0:9b334a45a8ff 672 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
bogdanm 0:9b334a45a8ff 673 #define USART5_BASE (APBPERIPH_BASE + 0x00005000)
bogdanm 0:9b334a45a8ff 674 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
bogdanm 0:9b334a45a8ff 675 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
bogdanm 0:9b334a45a8ff 676 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
bogdanm 0:9b334a45a8ff 677 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
bogdanm 0:9b334a45a8ff 678 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
bogdanm 0:9b334a45a8ff 679 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
bogdanm 0:9b334a45a8ff 680 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800)
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
bogdanm 0:9b334a45a8ff 683 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
bogdanm 0:9b334a45a8ff 684 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official 113:b3775bf36a83 685 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
bogdanm 0:9b334a45a8ff 686 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
bogdanm 0:9b334a45a8ff 687 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
bogdanm 0:9b334a45a8ff 688 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
mbed_official 113:b3775bf36a83 689 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
bogdanm 0:9b334a45a8ff 690 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
bogdanm 0:9b334a45a8ff 691 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
bogdanm 0:9b334a45a8ff 692 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
bogdanm 0:9b334a45a8ff 693 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
bogdanm 0:9b334a45a8ff 694 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 697 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
bogdanm 0:9b334a45a8ff 698 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
bogdanm 0:9b334a45a8ff 699 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
bogdanm 0:9b334a45a8ff 700 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
bogdanm 0:9b334a45a8ff 701 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
bogdanm 0:9b334a45a8ff 702 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
bogdanm 0:9b334a45a8ff 703 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
bogdanm 0:9b334a45a8ff 704 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 708 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 113:b3775bf36a83 709 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
bogdanm 0:9b334a45a8ff 710 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 711 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
bogdanm 0:9b334a45a8ff 712 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 715 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 716 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
bogdanm 0:9b334a45a8ff 717 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
bogdanm 0:9b334a45a8ff 718 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 719 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /**
bogdanm 0:9b334a45a8ff 722 * @}
bogdanm 0:9b334a45a8ff 723 */
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /** @addtogroup Peripheral_declaration
bogdanm 0:9b334a45a8ff 726 * @{
bogdanm 0:9b334a45a8ff 727 */
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 0:9b334a45a8ff 730 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 0:9b334a45a8ff 731 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 0:9b334a45a8ff 732 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 0:9b334a45a8ff 733 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 0:9b334a45a8ff 734 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 0:9b334a45a8ff 735 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 0:9b334a45a8ff 736 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 0:9b334a45a8ff 737 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 0:9b334a45a8ff 738 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
bogdanm 0:9b334a45a8ff 739 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 0:9b334a45a8ff 740 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 0:9b334a45a8ff 741 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 0:9b334a45a8ff 742 #define CRS ((CRS_TypeDef *) CRS_BASE)
bogdanm 0:9b334a45a8ff 743 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 0:9b334a45a8ff 744 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 113:b3775bf36a83 745 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
bogdanm 0:9b334a45a8ff 746 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
bogdanm 0:9b334a45a8ff 747 #define LCD ((LCD_TypeDef *) LCD_BASE)
bogdanm 0:9b334a45a8ff 748 #define USART4 ((USART_TypeDef *) USART4_BASE)
bogdanm 0:9b334a45a8ff 749 #define USART5 ((USART_TypeDef *) USART5_BASE)
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 0:9b334a45a8ff 752 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
bogdanm 0:9b334a45a8ff 753 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm 0:9b334a45a8ff 754 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 0:9b334a45a8ff 755 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
bogdanm 0:9b334a45a8ff 756 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
mbed_official 113:b3775bf36a83 757 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
bogdanm 0:9b334a45a8ff 758 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 113:b3775bf36a83 759 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 113:b3775bf36a83 760 /* Legacy defines */
mbed_official 113:b3775bf36a83 761 #define ADC ADC1_COMMON
bogdanm 0:9b334a45a8ff 762 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 0:9b334a45a8ff 763 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 0:9b334a45a8ff 764 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 0:9b334a45a8ff 767 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 0:9b334a45a8ff 768 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 0:9b334a45a8ff 769 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 0:9b334a45a8ff 770 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 0:9b334a45a8ff 771 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 0:9b334a45a8ff 772 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 0:9b334a45a8ff 773 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 0:9b334a45a8ff 774 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
bogdanm 0:9b334a45a8ff 775
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 0:9b334a45a8ff 778 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 0:9b334a45a8ff 779 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 0:9b334a45a8ff 780 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 0:9b334a45a8ff 781 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 0:9b334a45a8ff 782 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 0:9b334a45a8ff 785 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 0:9b334a45a8ff 786 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 0:9b334a45a8ff 787 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 0:9b334a45a8ff 788 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 0:9b334a45a8ff 789 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 #define USB ((USB_TypeDef *) USB_BASE)
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /**
bogdanm 0:9b334a45a8ff 794 * @}
bogdanm 0:9b334a45a8ff 795 */
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 /** @addtogroup Exported_constants
bogdanm 0:9b334a45a8ff 798 * @{
bogdanm 0:9b334a45a8ff 799 */
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 0:9b334a45a8ff 802 * @{
bogdanm 0:9b334a45a8ff 803 */
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /******************************************************************************/
bogdanm 0:9b334a45a8ff 806 /* Peripheral Registers Bits Definition */
bogdanm 0:9b334a45a8ff 807 /******************************************************************************/
bogdanm 0:9b334a45a8ff 808 /******************************************************************************/
bogdanm 0:9b334a45a8ff 809 /* */
bogdanm 0:9b334a45a8ff 810 /* Analog to Digital Converter (ADC) */
bogdanm 0:9b334a45a8ff 811 /* */
bogdanm 0:9b334a45a8ff 812 /******************************************************************************/
bogdanm 0:9b334a45a8ff 813 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 113:b3775bf36a83 814 #define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */
mbed_official 113:b3775bf36a83 815 #define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */
mbed_official 113:b3775bf36a83 816 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */
mbed_official 113:b3775bf36a83 817 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */
mbed_official 113:b3775bf36a83 818 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */
mbed_official 113:b3775bf36a83 819 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */
mbed_official 113:b3775bf36a83 820 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /* Old EOSEQ bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 823 #define ADC_ISR_EOS ADC_ISR_EOSEQ
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /******************** Bits definition for ADC_IER register ******************/
mbed_official 113:b3775bf36a83 826 #define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */
mbed_official 113:b3775bf36a83 827 #define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */
mbed_official 113:b3775bf36a83 828 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */
mbed_official 113:b3775bf36a83 829 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */
mbed_official 113:b3775bf36a83 830 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */
mbed_official 113:b3775bf36a83 831 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */
mbed_official 113:b3775bf36a83 832 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /* Old EOSEQIE bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 835 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
bogdanm 0:9b334a45a8ff 836
bogdanm 0:9b334a45a8ff 837 /******************** Bits definition for ADC_CR register *******************/
mbed_official 113:b3775bf36a83 838 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
mbed_official 113:b3775bf36a83 839 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */
mbed_official 113:b3775bf36a83 840 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */
mbed_official 113:b3775bf36a83 841 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */
mbed_official 113:b3775bf36a83 842 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */
mbed_official 113:b3775bf36a83 843 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 113:b3775bf36a83 846 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 113:b3775bf36a83 847 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 848 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 849 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 850 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 851 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 852 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */
mbed_official 113:b3775bf36a83 853 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 113:b3775bf36a83 854 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */
mbed_official 113:b3775bf36a83 855 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */
mbed_official 113:b3775bf36a83 856 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */
mbed_official 113:b3775bf36a83 857 #define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */
mbed_official 113:b3775bf36a83 858 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */
mbed_official 113:b3775bf36a83 859 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 113:b3775bf36a83 860 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 861 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 862 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 113:b3775bf36a83 863 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 864 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 865 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 866 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */
mbed_official 113:b3775bf36a83 867 #define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */
mbed_official 113:b3775bf36a83 868 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 869 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 870 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */
mbed_official 113:b3775bf36a83 871 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */
mbed_official 113:b3775bf36a83 872 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /* Old WAIT bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 875 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 113:b3775bf36a83 878 #define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */
mbed_official 113:b3775bf36a83 879 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */
mbed_official 113:b3775bf36a83 880 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 881 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 882 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 883 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 884 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */
mbed_official 113:b3775bf36a83 885 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 886 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 887 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 888 #define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */
mbed_official 113:b3775bf36a83 889 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */
mbed_official 113:b3775bf36a83 890 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 891 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 113:b3775bf36a83 895 #define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */
mbed_official 113:b3775bf36a83 896 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 897 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 898 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 899
mbed_official 113:b3775bf36a83 900 /* Legacy defines */
bogdanm 0:9b334a45a8ff 901 #define ADC_SMPR_SMPR ADC_SMPR_SMP
bogdanm 0:9b334a45a8ff 902 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
bogdanm 0:9b334a45a8ff 903 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
bogdanm 0:9b334a45a8ff 904 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 /******************* Bit definition for ADC_TR register ********************/
mbed_official 113:b3775bf36a83 907 #define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */
mbed_official 113:b3775bf36a83 908 #define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 113:b3775bf36a83 911 #define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */
mbed_official 113:b3775bf36a83 912 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */
mbed_official 113:b3775bf36a83 913 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */
mbed_official 113:b3775bf36a83 914 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */
mbed_official 113:b3775bf36a83 915 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */
mbed_official 113:b3775bf36a83 916 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */
mbed_official 113:b3775bf36a83 917 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */
mbed_official 113:b3775bf36a83 918 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */
mbed_official 113:b3775bf36a83 919 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */
mbed_official 113:b3775bf36a83 920 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */
mbed_official 113:b3775bf36a83 921 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */
mbed_official 113:b3775bf36a83 922 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */
mbed_official 113:b3775bf36a83 923 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */
mbed_official 113:b3775bf36a83 924 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */
mbed_official 113:b3775bf36a83 925 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */
mbed_official 113:b3775bf36a83 926 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */
mbed_official 113:b3775bf36a83 927 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */
mbed_official 113:b3775bf36a83 928 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */
mbed_official 113:b3775bf36a83 929 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */
mbed_official 113:b3775bf36a83 930 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /******************** Bit definition for ADC_DR register ********************/
mbed_official 113:b3775bf36a83 933 #define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /******************** Bit definition for ADC_CALFACT register ********************/
mbed_official 113:b3775bf36a83 936 #define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 113:b3775bf36a83 939 #define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */
mbed_official 113:b3775bf36a83 940 #define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */
mbed_official 113:b3775bf36a83 941 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */
mbed_official 113:b3775bf36a83 942 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */
mbed_official 113:b3775bf36a83 943 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */
mbed_official 113:b3775bf36a83 944 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 945 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 946 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 947 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 /******************************************************************************/
bogdanm 0:9b334a45a8ff 950 /* */
bogdanm 0:9b334a45a8ff 951 /* Analog Comparators (COMP) */
bogdanm 0:9b334a45a8ff 952 /* */
bogdanm 0:9b334a45a8ff 953 /******************************************************************************/
bogdanm 0:9b334a45a8ff 954 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
bogdanm 0:9b334a45a8ff 955 /* COMP1 bits definition */
mbed_official 113:b3775bf36a83 956 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */
mbed_official 113:b3775bf36a83 957 #define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */
mbed_official 113:b3775bf36a83 958 #define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */
mbed_official 113:b3775bf36a83 959 #define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */
mbed_official 113:b3775bf36a83 960 #define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */
mbed_official 113:b3775bf36a83 961 #define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */
mbed_official 113:b3775bf36a83 962 #define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */
mbed_official 113:b3775bf36a83 963 #define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */
mbed_official 113:b3775bf36a83 964 #define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */
bogdanm 0:9b334a45a8ff 965 /* COMP2 bits definition */
mbed_official 113:b3775bf36a83 966 #define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */
mbed_official 113:b3775bf36a83 967 #define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */
mbed_official 113:b3775bf36a83 968 #define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */
mbed_official 113:b3775bf36a83 969 #define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */
mbed_official 113:b3775bf36a83 970 #define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */
mbed_official 113:b3775bf36a83 971 #define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */
mbed_official 113:b3775bf36a83 972 #define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */
mbed_official 113:b3775bf36a83 973 #define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */
mbed_official 113:b3775bf36a83 974 #define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */
mbed_official 113:b3775bf36a83 975 #define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */
mbed_official 113:b3775bf36a83 976 #define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */
mbed_official 113:b3775bf36a83 977 #define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */
mbed_official 113:b3775bf36a83 978 #define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */
mbed_official 113:b3775bf36a83 979 #define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */
mbed_official 113:b3775bf36a83 980 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 /********************** Bit definition for COMP_CSR register common ****************/
mbed_official 113:b3775bf36a83 983 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */
mbed_official 113:b3775bf36a83 984 #define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
mbed_official 113:b3775bf36a83 985 #define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */
mbed_official 113:b3775bf36a83 986 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
mbed_official 113:b3775bf36a83 987
mbed_official 113:b3775bf36a83 988 /* Reference defines */
mbed_official 113:b3775bf36a83 989 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /******************************************************************************/
bogdanm 0:9b334a45a8ff 992 /* */
bogdanm 0:9b334a45a8ff 993 /* CRC calculation unit (CRC) */
bogdanm 0:9b334a45a8ff 994 /* */
bogdanm 0:9b334a45a8ff 995 /******************************************************************************/
bogdanm 0:9b334a45a8ff 996 /******************* Bit definition for CRC_DR register *********************/
mbed_official 113:b3775bf36a83 997 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 113:b3775bf36a83 1000 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 /******************** Bit definition for CRC_CR register ********************/
mbed_official 113:b3775bf36a83 1003 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
mbed_official 113:b3775bf36a83 1004 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
mbed_official 113:b3775bf36a83 1005 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
mbed_official 113:b3775bf36a83 1006 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
mbed_official 113:b3775bf36a83 1007 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
mbed_official 113:b3775bf36a83 1008 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1009 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1010 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 113:b3775bf36a83 1013 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /******************* Bit definition for CRC_POL register ********************/
mbed_official 113:b3775bf36a83 1016 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1019 /* */
bogdanm 0:9b334a45a8ff 1020 /* CRS Clock Recovery System */
bogdanm 0:9b334a45a8ff 1021 /* */
bogdanm 0:9b334a45a8ff 1022 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /******************* Bit definition for CRS_CR register *********************/
mbed_official 113:b3775bf36a83 1025 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
mbed_official 113:b3775bf36a83 1026 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
mbed_official 113:b3775bf36a83 1027 #define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
mbed_official 113:b3775bf36a83 1028 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official 113:b3775bf36a83 1029 #define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
mbed_official 113:b3775bf36a83 1030 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
mbed_official 113:b3775bf36a83 1031 #define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
mbed_official 113:b3775bf36a83 1032 #define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
bogdanm 0:9b334a45a8ff 1033
bogdanm 0:9b334a45a8ff 1034 /******************* Bit definition for CRS_CFGR register *********************/
mbed_official 113:b3775bf36a83 1035 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
mbed_official 113:b3775bf36a83 1036 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
mbed_official 113:b3775bf36a83 1037
mbed_official 113:b3775bf36a83 1038 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
mbed_official 113:b3775bf36a83 1039 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
mbed_official 113:b3775bf36a83 1040 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
mbed_official 113:b3775bf36a83 1041 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
mbed_official 113:b3775bf36a83 1042
mbed_official 113:b3775bf36a83 1043 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
mbed_official 113:b3775bf36a83 1044 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
mbed_official 113:b3775bf36a83 1045 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
mbed_official 113:b3775bf36a83 1046
mbed_official 113:b3775bf36a83 1047 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /******************* Bit definition for CRS_ISR register *********************/
mbed_official 113:b3775bf36a83 1050 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
mbed_official 113:b3775bf36a83 1051 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
mbed_official 113:b3775bf36a83 1052 #define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
mbed_official 113:b3775bf36a83 1053 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
mbed_official 113:b3775bf36a83 1054 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
mbed_official 113:b3775bf36a83 1055 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
mbed_official 113:b3775bf36a83 1056 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
mbed_official 113:b3775bf36a83 1057 #define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
mbed_official 113:b3775bf36a83 1058 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
bogdanm 0:9b334a45a8ff 1059
bogdanm 0:9b334a45a8ff 1060 /******************* Bit definition for CRS_ICR register *********************/
mbed_official 113:b3775bf36a83 1061 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
mbed_official 113:b3775bf36a83 1062 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
mbed_official 113:b3775bf36a83 1063 #define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
mbed_official 113:b3775bf36a83 1064 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1067 /* */
bogdanm 0:9b334a45a8ff 1068 /* Digital to Analog Converter (DAC) */
bogdanm 0:9b334a45a8ff 1069 /* */
bogdanm 0:9b334a45a8ff 1070 /******************************************************************************/
mbed_official 113:b3775bf36a83 1071
mbed_official 113:b3775bf36a83 1072 /*
mbed_official 113:b3775bf36a83 1073 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official 113:b3775bf36a83 1074 */
mbed_official 113:b3775bf36a83 1075 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
mbed_official 113:b3775bf36a83 1076
bogdanm 0:9b334a45a8ff 1077 /******************** Bit definition for DAC_CR register ********************/
mbed_official 113:b3775bf36a83 1078 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */
mbed_official 113:b3775bf36a83 1079 #define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */
mbed_official 113:b3775bf36a83 1080 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */
mbed_official 113:b3775bf36a83 1081
mbed_official 113:b3775bf36a83 1082 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 113:b3775bf36a83 1083 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1084 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1085 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 1086
mbed_official 113:b3775bf36a83 1087 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 113:b3775bf36a83 1088 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1089 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1090
mbed_official 113:b3775bf36a83 1091 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 113:b3775bf36a83 1092 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1093 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1094 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 1095 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 1096
mbed_official 113:b3775bf36a83 1097 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */
mbed_official 113:b3775bf36a83 1098 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */
mbed_official 113:b3775bf36a83 1099
mbed_official 113:b3775bf36a83 1100 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!< DAC channel2 enable */
mbed_official 113:b3775bf36a83 1101 #define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!< DAC channel2 output buffer disable */
mbed_official 113:b3775bf36a83 1102 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!< DAC channel2 Trigger enable */
mbed_official 113:b3775bf36a83 1103
mbed_official 113:b3775bf36a83 1104 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 113:b3775bf36a83 1105 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1106 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1107 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 1108
mbed_official 113:b3775bf36a83 1109 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 113:b3775bf36a83 1110 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1111 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1112
mbed_official 113:b3775bf36a83 1113 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 113:b3775bf36a83 1114 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1115 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1116 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 1117 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 1118
mbed_official 113:b3775bf36a83 1119 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!< DAC channel2 DMA enabled */
mbed_official 113:b3775bf36a83 1120 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!< DAC channel12DMA Underrun interrupt enable */
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 113:b3775bf36a83 1123 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */
mbed_official 113:b3775bf36a83 1124 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!< DAC channel2 software trigger */
bogdanm 0:9b334a45a8ff 1125
bogdanm 0:9b334a45a8ff 1126 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 113:b3775bf36a83 1127 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1128
bogdanm 0:9b334a45a8ff 1129 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 113:b3775bf36a83 1130 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 1131
bogdanm 0:9b334a45a8ff 1132 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 113:b3775bf36a83 1133 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 113:b3775bf36a83 1136 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 113:b3775bf36a83 1139 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 113:b3775bf36a83 1142 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 113:b3775bf36a83 1145 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 113:b3775bf36a83 1146 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 113:b3775bf36a83 1149 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 113:b3775bf36a83 1150 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 113:b3775bf36a83 1153 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 113:b3775bf36a83 1154 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 1155
bogdanm 0:9b334a45a8ff 1156 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 113:b3775bf36a83 1157 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
bogdanm 0:9b334a45a8ff 1158
bogdanm 0:9b334a45a8ff 1159 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 113:b3775bf36a83 1160 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!< DAC channel2 data output */
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 /******************** Bit definition for DAC_SR register ********************/
mbed_official 113:b3775bf36a83 1163 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */
mbed_official 113:b3775bf36a83 1164 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA underrun flag */
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1167 /* */
bogdanm 0:9b334a45a8ff 1168 /* Debug MCU (DBGMCU) */
bogdanm 0:9b334a45a8ff 1169 /* */
bogdanm 0:9b334a45a8ff 1170 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 113:b3775bf36a83 1173 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
mbed_official 113:b3775bf36a83 1174
mbed_official 113:b3775bf36a83 1175 #define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000U) /*!< Division Identifier */
mbed_official 113:b3775bf36a83 1176 #define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000U) /*!< MCD divsion ID is 6 */
mbed_official 113:b3775bf36a83 1177 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 113:b3775bf36a83 1178 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1179 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1180 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 1181 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 1182 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 1183 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
mbed_official 113:b3775bf36a83 1184 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
mbed_official 113:b3775bf36a83 1185 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
mbed_official 113:b3775bf36a83 1186 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
mbed_official 113:b3775bf36a83 1187 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
mbed_official 113:b3775bf36a83 1188 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
mbed_official 113:b3775bf36a83 1189 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
mbed_official 113:b3775bf36a83 1190 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
mbed_official 113:b3775bf36a83 1191 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
mbed_official 113:b3775bf36a83 1192 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
mbed_official 113:b3775bf36a83 1193 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
bogdanm 0:9b334a45a8ff 1194
bogdanm 0:9b334a45a8ff 1195 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 113:b3775bf36a83 1196 #define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */
mbed_official 113:b3775bf36a83 1197 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
mbed_official 113:b3775bf36a83 1198 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
mbed_official 113:b3775bf36a83 1199 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
bogdanm 0:9b334a45a8ff 1200
bogdanm 0:9b334a45a8ff 1201 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 113:b3775bf36a83 1202 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
mbed_official 113:b3775bf36a83 1203 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1204 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
mbed_official 113:b3775bf36a83 1205 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1206 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */
mbed_official 113:b3775bf36a83 1207 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 113:b3775bf36a83 1208 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 113:b3775bf36a83 1209 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 113:b3775bf36a83 1210 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
mbed_official 113:b3775bf36a83 1211 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000U) /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
mbed_official 113:b3775bf36a83 1212 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 1213 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 113:b3775bf36a83 1214 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */
mbed_official 113:b3775bf36a83 1215 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1218 /* */
bogdanm 0:9b334a45a8ff 1219 /* DMA Controller (DMA) */
bogdanm 0:9b334a45a8ff 1220 /* */
bogdanm 0:9b334a45a8ff 1221 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1222
bogdanm 0:9b334a45a8ff 1223 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 113:b3775bf36a83 1224 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
mbed_official 113:b3775bf36a83 1225 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1226 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
mbed_official 113:b3775bf36a83 1227 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
mbed_official 113:b3775bf36a83 1228 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
mbed_official 113:b3775bf36a83 1229 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1230 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
mbed_official 113:b3775bf36a83 1231 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
mbed_official 113:b3775bf36a83 1232 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
mbed_official 113:b3775bf36a83 1233 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1234 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
mbed_official 113:b3775bf36a83 1235 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
mbed_official 113:b3775bf36a83 1236 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
mbed_official 113:b3775bf36a83 1237 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1238 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
mbed_official 113:b3775bf36a83 1239 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
mbed_official 113:b3775bf36a83 1240 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
mbed_official 113:b3775bf36a83 1241 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1242 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
mbed_official 113:b3775bf36a83 1243 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
mbed_official 113:b3775bf36a83 1244 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
mbed_official 113:b3775bf36a83 1245 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1246 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
mbed_official 113:b3775bf36a83 1247 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
mbed_official 113:b3775bf36a83 1248 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
mbed_official 113:b3775bf36a83 1249 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
mbed_official 113:b3775bf36a83 1250 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
mbed_official 113:b3775bf36a83 1251 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
bogdanm 0:9b334a45a8ff 1252
bogdanm 0:9b334a45a8ff 1253 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 113:b3775bf36a83 1254 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
mbed_official 113:b3775bf36a83 1255 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1256 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
mbed_official 113:b3775bf36a83 1257 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
mbed_official 113:b3775bf36a83 1258 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
mbed_official 113:b3775bf36a83 1259 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1260 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
mbed_official 113:b3775bf36a83 1261 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
mbed_official 113:b3775bf36a83 1262 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
mbed_official 113:b3775bf36a83 1263 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1264 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
mbed_official 113:b3775bf36a83 1265 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
mbed_official 113:b3775bf36a83 1266 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
mbed_official 113:b3775bf36a83 1267 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1268 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
mbed_official 113:b3775bf36a83 1269 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
mbed_official 113:b3775bf36a83 1270 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
mbed_official 113:b3775bf36a83 1271 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1272 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
mbed_official 113:b3775bf36a83 1273 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
mbed_official 113:b3775bf36a83 1274 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
mbed_official 113:b3775bf36a83 1275 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1276 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
mbed_official 113:b3775bf36a83 1277 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
mbed_official 113:b3775bf36a83 1278 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
mbed_official 113:b3775bf36a83 1279 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
mbed_official 113:b3775bf36a83 1280 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
mbed_official 113:b3775bf36a83 1281 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
bogdanm 0:9b334a45a8ff 1282
bogdanm 0:9b334a45a8ff 1283 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 113:b3775bf36a83 1284 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
mbed_official 113:b3775bf36a83 1285 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
mbed_official 113:b3775bf36a83 1286 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
mbed_official 113:b3775bf36a83 1287 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
mbed_official 113:b3775bf36a83 1288 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
mbed_official 113:b3775bf36a83 1289 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
mbed_official 113:b3775bf36a83 1290 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
mbed_official 113:b3775bf36a83 1291 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
mbed_official 113:b3775bf36a83 1292
mbed_official 113:b3775bf36a83 1293 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 113:b3775bf36a83 1294 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1295 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1296
mbed_official 113:b3775bf36a83 1297 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 113:b3775bf36a83 1298 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1299 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1300
mbed_official 113:b3775bf36a83 1301 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 113:b3775bf36a83 1302 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 1303 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 1304
mbed_official 113:b3775bf36a83 1305 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
bogdanm 0:9b334a45a8ff 1306
bogdanm 0:9b334a45a8ff 1307 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 113:b3775bf36a83 1308 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
bogdanm 0:9b334a45a8ff 1309
bogdanm 0:9b334a45a8ff 1310 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 113:b3775bf36a83 1311 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
bogdanm 0:9b334a45a8ff 1312
bogdanm 0:9b334a45a8ff 1313 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 113:b3775bf36a83 1314 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
bogdanm 0:9b334a45a8ff 1315
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 /******************* Bit definition for DMA_CSELR register *******************/
mbed_official 113:b3775bf36a83 1318 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
mbed_official 113:b3775bf36a83 1319 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
mbed_official 113:b3775bf36a83 1320 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
mbed_official 113:b3775bf36a83 1321 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
mbed_official 113:b3775bf36a83 1322 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
mbed_official 113:b3775bf36a83 1323 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
mbed_official 113:b3775bf36a83 1324 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
bogdanm 0:9b334a45a8ff 1325
bogdanm 0:9b334a45a8ff 1326
bogdanm 0:9b334a45a8ff 1327 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1328 /* */
bogdanm 0:9b334a45a8ff 1329 /* External Interrupt/Event Controller (EXTI) */
bogdanm 0:9b334a45a8ff 1330 /* */
bogdanm 0:9b334a45a8ff 1331 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1332
bogdanm 0:9b334a45a8ff 1333 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 113:b3775bf36a83 1334 #define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
mbed_official 113:b3775bf36a83 1335 #define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
mbed_official 113:b3775bf36a83 1336 #define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
mbed_official 113:b3775bf36a83 1337 #define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
mbed_official 113:b3775bf36a83 1338 #define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
mbed_official 113:b3775bf36a83 1339 #define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
mbed_official 113:b3775bf36a83 1340 #define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
mbed_official 113:b3775bf36a83 1341 #define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
mbed_official 113:b3775bf36a83 1342 #define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
mbed_official 113:b3775bf36a83 1343 #define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
mbed_official 113:b3775bf36a83 1344 #define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
mbed_official 113:b3775bf36a83 1345 #define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
mbed_official 113:b3775bf36a83 1346 #define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
mbed_official 113:b3775bf36a83 1347 #define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
mbed_official 113:b3775bf36a83 1348 #define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
mbed_official 113:b3775bf36a83 1349 #define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
mbed_official 113:b3775bf36a83 1350 #define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
mbed_official 113:b3775bf36a83 1351 #define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
mbed_official 113:b3775bf36a83 1352 #define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
mbed_official 113:b3775bf36a83 1353 #define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
mbed_official 113:b3775bf36a83 1354 #define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
mbed_official 113:b3775bf36a83 1355 #define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
mbed_official 113:b3775bf36a83 1356 #define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
mbed_official 113:b3775bf36a83 1357 #define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
mbed_official 113:b3775bf36a83 1358 #define EXTI_IMR_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
mbed_official 113:b3775bf36a83 1359 #define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
mbed_official 113:b3775bf36a83 1360 #define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
mbed_official 113:b3775bf36a83 1361 #define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
mbed_official 113:b3775bf36a83 1362 #define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
bogdanm 0:9b334a45a8ff 1363
bogdanm 0:9b334a45a8ff 1364 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 113:b3775bf36a83 1365 #define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
mbed_official 113:b3775bf36a83 1366 #define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
mbed_official 113:b3775bf36a83 1367 #define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
mbed_official 113:b3775bf36a83 1368 #define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
mbed_official 113:b3775bf36a83 1369 #define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
mbed_official 113:b3775bf36a83 1370 #define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
mbed_official 113:b3775bf36a83 1371 #define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
mbed_official 113:b3775bf36a83 1372 #define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
mbed_official 113:b3775bf36a83 1373 #define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
mbed_official 113:b3775bf36a83 1374 #define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
mbed_official 113:b3775bf36a83 1375 #define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
mbed_official 113:b3775bf36a83 1376 #define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
mbed_official 113:b3775bf36a83 1377 #define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
mbed_official 113:b3775bf36a83 1378 #define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
mbed_official 113:b3775bf36a83 1379 #define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
mbed_official 113:b3775bf36a83 1380 #define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
mbed_official 113:b3775bf36a83 1381 #define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
mbed_official 113:b3775bf36a83 1382 #define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
mbed_official 113:b3775bf36a83 1383 #define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
mbed_official 113:b3775bf36a83 1384 #define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
mbed_official 113:b3775bf36a83 1385 #define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
mbed_official 113:b3775bf36a83 1386 #define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
mbed_official 113:b3775bf36a83 1387 #define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
mbed_official 113:b3775bf36a83 1388 #define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
mbed_official 113:b3775bf36a83 1389 #define EXTI_EMR_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
mbed_official 113:b3775bf36a83 1390 #define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
mbed_official 113:b3775bf36a83 1391 #define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
mbed_official 113:b3775bf36a83 1392 #define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
mbed_official 113:b3775bf36a83 1393 #define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
bogdanm 0:9b334a45a8ff 1394
bogdanm 0:9b334a45a8ff 1395 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 113:b3775bf36a83 1396 #define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 113:b3775bf36a83 1397 #define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 113:b3775bf36a83 1398 #define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 113:b3775bf36a83 1399 #define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 113:b3775bf36a83 1400 #define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 113:b3775bf36a83 1401 #define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 113:b3775bf36a83 1402 #define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 113:b3775bf36a83 1403 #define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 113:b3775bf36a83 1404 #define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 113:b3775bf36a83 1405 #define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 113:b3775bf36a83 1406 #define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 113:b3775bf36a83 1407 #define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 113:b3775bf36a83 1408 #define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 113:b3775bf36a83 1409 #define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 113:b3775bf36a83 1410 #define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 113:b3775bf36a83 1411 #define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 113:b3775bf36a83 1412 #define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 113:b3775bf36a83 1413 #define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 113:b3775bf36a83 1414 #define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 113:b3775bf36a83 1415 #define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 113:b3775bf36a83 1416 #define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 113:b3775bf36a83 1417 #define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 113:b3775bf36a83 1418
mbed_official 113:b3775bf36a83 1419 /* Legacy defines */
mbed_official 113:b3775bf36a83 1420 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0
mbed_official 113:b3775bf36a83 1421 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1
mbed_official 113:b3775bf36a83 1422 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2
mbed_official 113:b3775bf36a83 1423 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3
mbed_official 113:b3775bf36a83 1424 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4
mbed_official 113:b3775bf36a83 1425 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5
mbed_official 113:b3775bf36a83 1426 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6
mbed_official 113:b3775bf36a83 1427 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7
mbed_official 113:b3775bf36a83 1428 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8
mbed_official 113:b3775bf36a83 1429 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9
mbed_official 113:b3775bf36a83 1430 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10
mbed_official 113:b3775bf36a83 1431 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11
mbed_official 113:b3775bf36a83 1432 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12
mbed_official 113:b3775bf36a83 1433 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13
mbed_official 113:b3775bf36a83 1434 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14
mbed_official 113:b3775bf36a83 1435 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15
mbed_official 113:b3775bf36a83 1436 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16
mbed_official 113:b3775bf36a83 1437 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17
mbed_official 113:b3775bf36a83 1438 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19
mbed_official 113:b3775bf36a83 1439 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20
mbed_official 113:b3775bf36a83 1440 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21
mbed_official 113:b3775bf36a83 1441 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22
bogdanm 0:9b334a45a8ff 1442
bogdanm 0:9b334a45a8ff 1443 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 113:b3775bf36a83 1444 #define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 113:b3775bf36a83 1445 #define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 113:b3775bf36a83 1446 #define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 113:b3775bf36a83 1447 #define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 113:b3775bf36a83 1448 #define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 113:b3775bf36a83 1449 #define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 113:b3775bf36a83 1450 #define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 113:b3775bf36a83 1451 #define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 113:b3775bf36a83 1452 #define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 113:b3775bf36a83 1453 #define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 113:b3775bf36a83 1454 #define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 113:b3775bf36a83 1455 #define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 113:b3775bf36a83 1456 #define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 113:b3775bf36a83 1457 #define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 113:b3775bf36a83 1458 #define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 113:b3775bf36a83 1459 #define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 113:b3775bf36a83 1460 #define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 113:b3775bf36a83 1461 #define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 113:b3775bf36a83 1462 #define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 113:b3775bf36a83 1463 #define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 113:b3775bf36a83 1464 #define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 113:b3775bf36a83 1465 #define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 113:b3775bf36a83 1466
mbed_official 113:b3775bf36a83 1467 /* Legacy defines */
mbed_official 113:b3775bf36a83 1468 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0
mbed_official 113:b3775bf36a83 1469 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1
mbed_official 113:b3775bf36a83 1470 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2
mbed_official 113:b3775bf36a83 1471 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3
mbed_official 113:b3775bf36a83 1472 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4
mbed_official 113:b3775bf36a83 1473 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5
mbed_official 113:b3775bf36a83 1474 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6
mbed_official 113:b3775bf36a83 1475 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7
mbed_official 113:b3775bf36a83 1476 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8
mbed_official 113:b3775bf36a83 1477 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9
mbed_official 113:b3775bf36a83 1478 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10
mbed_official 113:b3775bf36a83 1479 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11
mbed_official 113:b3775bf36a83 1480 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12
mbed_official 113:b3775bf36a83 1481 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13
mbed_official 113:b3775bf36a83 1482 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14
mbed_official 113:b3775bf36a83 1483 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15
mbed_official 113:b3775bf36a83 1484 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16
mbed_official 113:b3775bf36a83 1485 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17
mbed_official 113:b3775bf36a83 1486 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19
mbed_official 113:b3775bf36a83 1487 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20
mbed_official 113:b3775bf36a83 1488 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21
mbed_official 113:b3775bf36a83 1489 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22
bogdanm 0:9b334a45a8ff 1490
bogdanm 0:9b334a45a8ff 1491 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 113:b3775bf36a83 1492 #define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
mbed_official 113:b3775bf36a83 1493 #define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
mbed_official 113:b3775bf36a83 1494 #define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
mbed_official 113:b3775bf36a83 1495 #define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
mbed_official 113:b3775bf36a83 1496 #define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
mbed_official 113:b3775bf36a83 1497 #define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
mbed_official 113:b3775bf36a83 1498 #define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
mbed_official 113:b3775bf36a83 1499 #define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
mbed_official 113:b3775bf36a83 1500 #define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
mbed_official 113:b3775bf36a83 1501 #define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
mbed_official 113:b3775bf36a83 1502 #define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
mbed_official 113:b3775bf36a83 1503 #define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
mbed_official 113:b3775bf36a83 1504 #define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
mbed_official 113:b3775bf36a83 1505 #define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
mbed_official 113:b3775bf36a83 1506 #define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
mbed_official 113:b3775bf36a83 1507 #define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
mbed_official 113:b3775bf36a83 1508 #define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
mbed_official 113:b3775bf36a83 1509 #define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
mbed_official 113:b3775bf36a83 1510 #define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
mbed_official 113:b3775bf36a83 1511 #define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
mbed_official 113:b3775bf36a83 1512 #define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
mbed_official 113:b3775bf36a83 1513 #define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
mbed_official 113:b3775bf36a83 1514
mbed_official 113:b3775bf36a83 1515 /* Legacy defines */
mbed_official 113:b3775bf36a83 1516 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
mbed_official 113:b3775bf36a83 1517 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
mbed_official 113:b3775bf36a83 1518 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
mbed_official 113:b3775bf36a83 1519 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
mbed_official 113:b3775bf36a83 1520 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
mbed_official 113:b3775bf36a83 1521 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
mbed_official 113:b3775bf36a83 1522 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
mbed_official 113:b3775bf36a83 1523 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
mbed_official 113:b3775bf36a83 1524 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
mbed_official 113:b3775bf36a83 1525 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
mbed_official 113:b3775bf36a83 1526 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
mbed_official 113:b3775bf36a83 1527 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
mbed_official 113:b3775bf36a83 1528 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
mbed_official 113:b3775bf36a83 1529 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
mbed_official 113:b3775bf36a83 1530 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
mbed_official 113:b3775bf36a83 1531 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
mbed_official 113:b3775bf36a83 1532 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
mbed_official 113:b3775bf36a83 1533 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
mbed_official 113:b3775bf36a83 1534 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
mbed_official 113:b3775bf36a83 1535 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
mbed_official 113:b3775bf36a83 1536 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
mbed_official 113:b3775bf36a83 1537 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
bogdanm 0:9b334a45a8ff 1538
bogdanm 0:9b334a45a8ff 1539 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 113:b3775bf36a83 1540 #define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */
mbed_official 113:b3775bf36a83 1541 #define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */
mbed_official 113:b3775bf36a83 1542 #define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */
mbed_official 113:b3775bf36a83 1543 #define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */
mbed_official 113:b3775bf36a83 1544 #define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */
mbed_official 113:b3775bf36a83 1545 #define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */
mbed_official 113:b3775bf36a83 1546 #define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */
mbed_official 113:b3775bf36a83 1547 #define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */
mbed_official 113:b3775bf36a83 1548 #define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */
mbed_official 113:b3775bf36a83 1549 #define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */
mbed_official 113:b3775bf36a83 1550 #define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */
mbed_official 113:b3775bf36a83 1551 #define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */
mbed_official 113:b3775bf36a83 1552 #define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */
mbed_official 113:b3775bf36a83 1553 #define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */
mbed_official 113:b3775bf36a83 1554 #define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */
mbed_official 113:b3775bf36a83 1555 #define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */
mbed_official 113:b3775bf36a83 1556 #define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */
mbed_official 113:b3775bf36a83 1557 #define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */
mbed_official 113:b3775bf36a83 1558 #define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */
mbed_official 113:b3775bf36a83 1559 #define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */
mbed_official 113:b3775bf36a83 1560 #define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */
mbed_official 113:b3775bf36a83 1561 #define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */
mbed_official 113:b3775bf36a83 1562
mbed_official 113:b3775bf36a83 1563 /* Legacy defines */
mbed_official 113:b3775bf36a83 1564 #define EXTI_PR_PR0 EXTI_PR_PIF0
mbed_official 113:b3775bf36a83 1565 #define EXTI_PR_PR1 EXTI_PR_PIF1
mbed_official 113:b3775bf36a83 1566 #define EXTI_PR_PR2 EXTI_PR_PIF2
mbed_official 113:b3775bf36a83 1567 #define EXTI_PR_PR3 EXTI_PR_PIF3
mbed_official 113:b3775bf36a83 1568 #define EXTI_PR_PR4 EXTI_PR_PIF4
mbed_official 113:b3775bf36a83 1569 #define EXTI_PR_PR5 EXTI_PR_PIF5
mbed_official 113:b3775bf36a83 1570 #define EXTI_PR_PR6 EXTI_PR_PIF6
mbed_official 113:b3775bf36a83 1571 #define EXTI_PR_PR7 EXTI_PR_PIF7
mbed_official 113:b3775bf36a83 1572 #define EXTI_PR_PR8 EXTI_PR_PIF8
mbed_official 113:b3775bf36a83 1573 #define EXTI_PR_PR9 EXTI_PR_PIF9
mbed_official 113:b3775bf36a83 1574 #define EXTI_PR_PR10 EXTI_PR_PIF10
mbed_official 113:b3775bf36a83 1575 #define EXTI_PR_PR11 EXTI_PR_PIF11
mbed_official 113:b3775bf36a83 1576 #define EXTI_PR_PR12 EXTI_PR_PIF12
mbed_official 113:b3775bf36a83 1577 #define EXTI_PR_PR13 EXTI_PR_PIF13
mbed_official 113:b3775bf36a83 1578 #define EXTI_PR_PR14 EXTI_PR_PIF14
mbed_official 113:b3775bf36a83 1579 #define EXTI_PR_PR15 EXTI_PR_PIF15
mbed_official 113:b3775bf36a83 1580 #define EXTI_PR_PR16 EXTI_PR_PIF16
mbed_official 113:b3775bf36a83 1581 #define EXTI_PR_PR17 EXTI_PR_PIF17
mbed_official 113:b3775bf36a83 1582 #define EXTI_PR_PR19 EXTI_PR_PIF19
mbed_official 113:b3775bf36a83 1583 #define EXTI_PR_PR20 EXTI_PR_PIF20
mbed_official 113:b3775bf36a83 1584 #define EXTI_PR_PR21 EXTI_PR_PIF21
mbed_official 113:b3775bf36a83 1585 #define EXTI_PR_PR22 EXTI_PR_PIF22
bogdanm 0:9b334a45a8ff 1586
bogdanm 0:9b334a45a8ff 1587 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1588 /* */
bogdanm 0:9b334a45a8ff 1589 /* FLASH and Option Bytes Registers */
bogdanm 0:9b334a45a8ff 1590 /* */
bogdanm 0:9b334a45a8ff 1591 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1592
bogdanm 0:9b334a45a8ff 1593 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 113:b3775bf36a83 1594 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */
mbed_official 113:b3775bf36a83 1595 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
mbed_official 113:b3775bf36a83 1596 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
mbed_official 113:b3775bf36a83 1597 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
mbed_official 113:b3775bf36a83 1598 #define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */
mbed_official 113:b3775bf36a83 1599 #define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */
bogdanm 0:9b334a45a8ff 1600
bogdanm 0:9b334a45a8ff 1601 /******************* Bit definition for FLASH_PECR register ******************/
mbed_official 113:b3775bf36a83 1602 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
mbed_official 113:b3775bf36a83 1603 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
mbed_official 113:b3775bf36a83 1604 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
mbed_official 113:b3775bf36a83 1605 #define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
mbed_official 113:b3775bf36a83 1606 #define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
mbed_official 113:b3775bf36a83 1607 #define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
mbed_official 113:b3775bf36a83 1608 #define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
mbed_official 113:b3775bf36a83 1609 #define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
mbed_official 113:b3775bf36a83 1610 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000U) /*!< Parallel Bank mode */
mbed_official 113:b3775bf36a83 1611 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
mbed_official 113:b3775bf36a83 1612 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
mbed_official 113:b3775bf36a83 1613 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
mbed_official 113:b3775bf36a83 1614 #define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */
mbed_official 113:b3775bf36a83 1615 #define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000U) /*!< Non-Zero check disable */
bogdanm 0:9b334a45a8ff 1616
bogdanm 0:9b334a45a8ff 1617 /****************** Bit definition for FLASH_PDKEYR register ******************/
mbed_official 113:b3775bf36a83 1618 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
bogdanm 0:9b334a45a8ff 1619
bogdanm 0:9b334a45a8ff 1620 /****************** Bit definition for FLASH_PEKEYR register ******************/
mbed_official 113:b3775bf36a83 1621 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
bogdanm 0:9b334a45a8ff 1622
bogdanm 0:9b334a45a8ff 1623 /****************** Bit definition for FLASH_PRGKEYR register ******************/
mbed_official 113:b3775bf36a83 1624 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
bogdanm 0:9b334a45a8ff 1625
bogdanm 0:9b334a45a8ff 1626 /****************** Bit definition for FLASH_OPTKEYR register ******************/
mbed_official 113:b3775bf36a83 1627 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
bogdanm 0:9b334a45a8ff 1628
bogdanm 0:9b334a45a8ff 1629 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 113:b3775bf36a83 1630 #define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
mbed_official 113:b3775bf36a83 1631 #define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
mbed_official 113:b3775bf36a83 1632 #define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */
mbed_official 113:b3775bf36a83 1633 #define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
mbed_official 113:b3775bf36a83 1634
mbed_official 113:b3775bf36a83 1635 #define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */
mbed_official 113:b3775bf36a83 1636 #define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
mbed_official 113:b3775bf36a83 1637 #define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
mbed_official 113:b3775bf36a83 1638 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */
mbed_official 113:b3775bf36a83 1639 #define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
mbed_official 113:b3775bf36a83 1640 #define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */
mbed_official 113:b3775bf36a83 1641 #define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */
mbed_official 113:b3775bf36a83 1642
mbed_official 113:b3775bf36a83 1643 /* Legacy defines */
bogdanm 0:9b334a45a8ff 1644 #define FLASH_SR_FWWER FLASH_SR_FWWERR
bogdanm 0:9b334a45a8ff 1645 #define FLASH_SR_ENHV FLASH_SR_HVOFF
bogdanm 0:9b334a45a8ff 1646 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
bogdanm 0:9b334a45a8ff 1647
bogdanm 0:9b334a45a8ff 1648 /****************** Bit definition for FLASH_OPTR register *******************/
mbed_official 113:b3775bf36a83 1649 #define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */
mbed_official 113:b3775bf36a83 1650 #define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */
mbed_official 113:b3775bf36a83 1651 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
mbed_official 113:b3775bf36a83 1652 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
mbed_official 113:b3775bf36a83 1653 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
mbed_official 113:b3775bf36a83 1654 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
mbed_official 113:b3775bf36a83 1655 #define FLASH_OPTR_BFB2 ((uint32_t)0x00800000U) /*!< BFB2 */
mbed_official 113:b3775bf36a83 1656 #define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
mbed_official 113:b3775bf36a83 1657 #define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */
bogdanm 0:9b334a45a8ff 1658
bogdanm 0:9b334a45a8ff 1659 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 113:b3775bf36a83 1660 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */
bogdanm 0:9b334a45a8ff 1661
bogdanm 0:9b334a45a8ff 1662 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1663 /* */
bogdanm 0:9b334a45a8ff 1664 /* General Purpose IOs (GPIO) */
bogdanm 0:9b334a45a8ff 1665 /* */
bogdanm 0:9b334a45a8ff 1666 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1667 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 113:b3775bf36a83 1668 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
mbed_official 113:b3775bf36a83 1669 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1670 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1671 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
mbed_official 113:b3775bf36a83 1672 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1673 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1674 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
mbed_official 113:b3775bf36a83 1675 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1676 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1677 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
mbed_official 113:b3775bf36a83 1678 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1679 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1680 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
mbed_official 113:b3775bf36a83 1681 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1682 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1683 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
mbed_official 113:b3775bf36a83 1684 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1685 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1686 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
mbed_official 113:b3775bf36a83 1687 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1688 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1689 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
mbed_official 113:b3775bf36a83 1690 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1691 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
mbed_official 113:b3775bf36a83 1692 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
mbed_official 113:b3775bf36a83 1693 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
mbed_official 113:b3775bf36a83 1694 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
mbed_official 113:b3775bf36a83 1695 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
mbed_official 113:b3775bf36a83 1696 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
mbed_official 113:b3775bf36a83 1697 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
mbed_official 113:b3775bf36a83 1698 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
mbed_official 113:b3775bf36a83 1699 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
mbed_official 113:b3775bf36a83 1700 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
mbed_official 113:b3775bf36a83 1701 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
mbed_official 113:b3775bf36a83 1702 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
mbed_official 113:b3775bf36a83 1703 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
mbed_official 113:b3775bf36a83 1704 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
mbed_official 113:b3775bf36a83 1705 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 1706 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 1707 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
mbed_official 113:b3775bf36a83 1708 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 1709 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 1710 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
mbed_official 113:b3775bf36a83 1711 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
mbed_official 113:b3775bf36a83 1712 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
mbed_official 113:b3775bf36a83 1713 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
mbed_official 113:b3775bf36a83 1714 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
mbed_official 113:b3775bf36a83 1715 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
bogdanm 0:9b334a45a8ff 1716
bogdanm 0:9b334a45a8ff 1717 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 113:b3775bf36a83 1718 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1719 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1720 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1721 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1722 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1723 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1724 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1725 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1726 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1727 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1728 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1729 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1730 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1731 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1732 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1733 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
bogdanm 0:9b334a45a8ff 1734
bogdanm 0:9b334a45a8ff 1735 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 113:b3775bf36a83 1736 #define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
mbed_official 113:b3775bf36a83 1737 #define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1738 #define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1739 #define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
mbed_official 113:b3775bf36a83 1740 #define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1741 #define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1742 #define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
mbed_official 113:b3775bf36a83 1743 #define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1744 #define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1745 #define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
mbed_official 113:b3775bf36a83 1746 #define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1747 #define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1748 #define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
mbed_official 113:b3775bf36a83 1749 #define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1750 #define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1751 #define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
mbed_official 113:b3775bf36a83 1752 #define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1753 #define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1754 #define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
mbed_official 113:b3775bf36a83 1755 #define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1756 #define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1757 #define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
mbed_official 113:b3775bf36a83 1758 #define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1759 #define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
mbed_official 113:b3775bf36a83 1760 #define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
mbed_official 113:b3775bf36a83 1761 #define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
mbed_official 113:b3775bf36a83 1762 #define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
mbed_official 113:b3775bf36a83 1763 #define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
mbed_official 113:b3775bf36a83 1764 #define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
mbed_official 113:b3775bf36a83 1765 #define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
mbed_official 113:b3775bf36a83 1766 #define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
mbed_official 113:b3775bf36a83 1767 #define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
mbed_official 113:b3775bf36a83 1768 #define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
mbed_official 113:b3775bf36a83 1769 #define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
mbed_official 113:b3775bf36a83 1770 #define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
mbed_official 113:b3775bf36a83 1771 #define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
mbed_official 113:b3775bf36a83 1772 #define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
mbed_official 113:b3775bf36a83 1773 #define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 1774 #define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 1775 #define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
mbed_official 113:b3775bf36a83 1776 #define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 1777 #define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 1778 #define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
mbed_official 113:b3775bf36a83 1779 #define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
mbed_official 113:b3775bf36a83 1780 #define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
mbed_official 113:b3775bf36a83 1781 #define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
mbed_official 113:b3775bf36a83 1782 #define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
mbed_official 113:b3775bf36a83 1783 #define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
bogdanm 0:9b334a45a8ff 1784
bogdanm 0:9b334a45a8ff 1785 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 113:b3775bf36a83 1786 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
mbed_official 113:b3775bf36a83 1787 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1788 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1789 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
mbed_official 113:b3775bf36a83 1790 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1791 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1792 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
mbed_official 113:b3775bf36a83 1793 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1794 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1795 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
mbed_official 113:b3775bf36a83 1796 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1797 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1798 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
mbed_official 113:b3775bf36a83 1799 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1800 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1801 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
mbed_official 113:b3775bf36a83 1802 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1803 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1804 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
mbed_official 113:b3775bf36a83 1805 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1806 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1807 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
mbed_official 113:b3775bf36a83 1808 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1809 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
mbed_official 113:b3775bf36a83 1810 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
mbed_official 113:b3775bf36a83 1811 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
mbed_official 113:b3775bf36a83 1812 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
mbed_official 113:b3775bf36a83 1813 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
mbed_official 113:b3775bf36a83 1814 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
mbed_official 113:b3775bf36a83 1815 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
mbed_official 113:b3775bf36a83 1816 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
mbed_official 113:b3775bf36a83 1817 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
mbed_official 113:b3775bf36a83 1818 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
mbed_official 113:b3775bf36a83 1819 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
mbed_official 113:b3775bf36a83 1820 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
mbed_official 113:b3775bf36a83 1821 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
mbed_official 113:b3775bf36a83 1822 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
mbed_official 113:b3775bf36a83 1823 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 1824 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 1825 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
mbed_official 113:b3775bf36a83 1826 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 1827 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 1828 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
mbed_official 113:b3775bf36a83 1829 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
mbed_official 113:b3775bf36a83 1830 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
mbed_official 113:b3775bf36a83 1831 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
mbed_official 113:b3775bf36a83 1832 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
mbed_official 113:b3775bf36a83 1833 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
bogdanm 0:9b334a45a8ff 1834
bogdanm 0:9b334a45a8ff 1835 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 113:b3775bf36a83 1836 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1837 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1838 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1839 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1840 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1841 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1842 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1843 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1844 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1845 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1846 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1847 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1848 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1849 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1850 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1851 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
bogdanm 0:9b334a45a8ff 1852
bogdanm 0:9b334a45a8ff 1853 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 113:b3775bf36a83 1854 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1855 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1856 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1857 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1858 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1859 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1860 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1861 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1862 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1863 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1864 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1865 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1866 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1867 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1868 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1869 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
bogdanm 0:9b334a45a8ff 1870
bogdanm 0:9b334a45a8ff 1871 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 113:b3775bf36a83 1872 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1873 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1874 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1875 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1876 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1877 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1878 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1879 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1880 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1881 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1882 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1883 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1884 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1885 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1886 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1887 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
mbed_official 113:b3775bf36a83 1888 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
mbed_official 113:b3775bf36a83 1889 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
mbed_official 113:b3775bf36a83 1890 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
mbed_official 113:b3775bf36a83 1891 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
mbed_official 113:b3775bf36a83 1892 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
mbed_official 113:b3775bf36a83 1893 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
mbed_official 113:b3775bf36a83 1894 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
mbed_official 113:b3775bf36a83 1895 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
mbed_official 113:b3775bf36a83 1896 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 1897 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 1898 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 1899 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 1900 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
mbed_official 113:b3775bf36a83 1901 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
mbed_official 113:b3775bf36a83 1902 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
mbed_official 113:b3775bf36a83 1903 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
bogdanm 0:9b334a45a8ff 1904
bogdanm 0:9b334a45a8ff 1905 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 113:b3775bf36a83 1906 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1907 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1908 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1909 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1910 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1911 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1912 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1913 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1914 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1915 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1916 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1917 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1918 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1919 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1920 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1921 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
mbed_official 113:b3775bf36a83 1922 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
mbed_official 113:b3775bf36a83 1923
mbed_official 113:b3775bf36a83 1924 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 113:b3775bf36a83 1925 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
mbed_official 113:b3775bf36a83 1926 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
mbed_official 113:b3775bf36a83 1927 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
mbed_official 113:b3775bf36a83 1928 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
mbed_official 113:b3775bf36a83 1929 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
mbed_official 113:b3775bf36a83 1930 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
mbed_official 113:b3775bf36a83 1931 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
mbed_official 113:b3775bf36a83 1932 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
mbed_official 113:b3775bf36a83 1933
mbed_official 113:b3775bf36a83 1934 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 113:b3775bf36a83 1935 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
mbed_official 113:b3775bf36a83 1936 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
mbed_official 113:b3775bf36a83 1937 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
mbed_official 113:b3775bf36a83 1938 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
mbed_official 113:b3775bf36a83 1939 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
mbed_official 113:b3775bf36a83 1940 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
mbed_official 113:b3775bf36a83 1941 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
mbed_official 113:b3775bf36a83 1942 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
bogdanm 0:9b334a45a8ff 1943
bogdanm 0:9b334a45a8ff 1944 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 113:b3775bf36a83 1945 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 1946 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 1947 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 1948 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 1949 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 1950 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 1951 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
mbed_official 113:b3775bf36a83 1952 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
mbed_official 113:b3775bf36a83 1953 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
mbed_official 113:b3775bf36a83 1954 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
mbed_official 113:b3775bf36a83 1955 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
mbed_official 113:b3775bf36a83 1956 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
mbed_official 113:b3775bf36a83 1957 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
mbed_official 113:b3775bf36a83 1958 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
mbed_official 113:b3775bf36a83 1959 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
mbed_official 113:b3775bf36a83 1960 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
bogdanm 0:9b334a45a8ff 1961
bogdanm 0:9b334a45a8ff 1962 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1963 /* */
bogdanm 0:9b334a45a8ff 1964 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 0:9b334a45a8ff 1965 /* */
bogdanm 0:9b334a45a8ff 1966 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1967
bogdanm 0:9b334a45a8ff 1968 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 113:b3775bf36a83 1969 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
mbed_official 113:b3775bf36a83 1970 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
mbed_official 113:b3775bf36a83 1971 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
mbed_official 113:b3775bf36a83 1972 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
mbed_official 113:b3775bf36a83 1973 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
mbed_official 113:b3775bf36a83 1974 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
mbed_official 113:b3775bf36a83 1975 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
mbed_official 113:b3775bf36a83 1976 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
mbed_official 113:b3775bf36a83 1977 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
mbed_official 113:b3775bf36a83 1978 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
mbed_official 113:b3775bf36a83 1979 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
mbed_official 113:b3775bf36a83 1980 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
mbed_official 113:b3775bf36a83 1981 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
mbed_official 113:b3775bf36a83 1982 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
mbed_official 113:b3775bf36a83 1983 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
mbed_official 113:b3775bf36a83 1984 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
mbed_official 113:b3775bf36a83 1985 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
mbed_official 113:b3775bf36a83 1986 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
mbed_official 113:b3775bf36a83 1987 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
mbed_official 113:b3775bf36a83 1988 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
bogdanm 0:9b334a45a8ff 1989
bogdanm 0:9b334a45a8ff 1990 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 113:b3775bf36a83 1991 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
mbed_official 113:b3775bf36a83 1992 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
mbed_official 113:b3775bf36a83 1993 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
mbed_official 113:b3775bf36a83 1994 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
mbed_official 113:b3775bf36a83 1995 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
mbed_official 113:b3775bf36a83 1996 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
mbed_official 113:b3775bf36a83 1997 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
mbed_official 113:b3775bf36a83 1998 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
mbed_official 113:b3775bf36a83 1999 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
mbed_official 113:b3775bf36a83 2000 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
mbed_official 113:b3775bf36a83 2001 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
bogdanm 0:9b334a45a8ff 2002
bogdanm 0:9b334a45a8ff 2003 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 113:b3775bf36a83 2004 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
mbed_official 113:b3775bf36a83 2005 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
mbed_official 113:b3775bf36a83 2006 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
bogdanm 0:9b334a45a8ff 2007
bogdanm 0:9b334a45a8ff 2008 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 113:b3775bf36a83 2009 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
mbed_official 113:b3775bf36a83 2010 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
mbed_official 113:b3775bf36a83 2011 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
mbed_official 113:b3775bf36a83 2012 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
mbed_official 113:b3775bf36a83 2013 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
mbed_official 113:b3775bf36a83 2014 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
mbed_official 113:b3775bf36a83 2015 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
mbed_official 113:b3775bf36a83 2016 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
mbed_official 113:b3775bf36a83 2017 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
mbed_official 113:b3775bf36a83 2018 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
mbed_official 113:b3775bf36a83 2019 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
bogdanm 0:9b334a45a8ff 2020
bogdanm 0:9b334a45a8ff 2021 /******************* Bit definition for I2C_TIMINGR register *******************/
mbed_official 113:b3775bf36a83 2022 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
mbed_official 113:b3775bf36a83 2023 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
mbed_official 113:b3775bf36a83 2024 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
mbed_official 113:b3775bf36a83 2025 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
mbed_official 113:b3775bf36a83 2026 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
bogdanm 0:9b334a45a8ff 2027
bogdanm 0:9b334a45a8ff 2028 /******************* Bit definition for I2C_TIMEOUTR register *******************/
mbed_official 113:b3775bf36a83 2029 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
mbed_official 113:b3775bf36a83 2030 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
mbed_official 113:b3775bf36a83 2031 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
mbed_official 113:b3775bf36a83 2032 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/
mbed_official 113:b3775bf36a83 2033 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
bogdanm 0:9b334a45a8ff 2034
bogdanm 0:9b334a45a8ff 2035 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 113:b3775bf36a83 2036 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
mbed_official 113:b3775bf36a83 2037 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
mbed_official 113:b3775bf36a83 2038 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
mbed_official 113:b3775bf36a83 2039 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/
mbed_official 113:b3775bf36a83 2040 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
mbed_official 113:b3775bf36a83 2041 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
mbed_official 113:b3775bf36a83 2042 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
mbed_official 113:b3775bf36a83 2043 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
mbed_official 113:b3775bf36a83 2044 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
mbed_official 113:b3775bf36a83 2045 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
mbed_official 113:b3775bf36a83 2046 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
mbed_official 113:b3775bf36a83 2047 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
mbed_official 113:b3775bf36a83 2048 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
mbed_official 113:b3775bf36a83 2049 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
mbed_official 113:b3775bf36a83 2050 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
mbed_official 113:b3775bf36a83 2051 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
mbed_official 113:b3775bf36a83 2052 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
bogdanm 0:9b334a45a8ff 2053
bogdanm 0:9b334a45a8ff 2054 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 113:b3775bf36a83 2055 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
mbed_official 113:b3775bf36a83 2056 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
mbed_official 113:b3775bf36a83 2057 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
mbed_official 113:b3775bf36a83 2058 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
mbed_official 113:b3775bf36a83 2059 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
mbed_official 113:b3775bf36a83 2060 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
mbed_official 113:b3775bf36a83 2061 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
mbed_official 113:b3775bf36a83 2062 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
mbed_official 113:b3775bf36a83 2063 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
bogdanm 0:9b334a45a8ff 2064
bogdanm 0:9b334a45a8ff 2065 /****************** Bit definition for I2C_PECR register *********************/
mbed_official 113:b3775bf36a83 2066 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
bogdanm 0:9b334a45a8ff 2067
bogdanm 0:9b334a45a8ff 2068 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 113:b3775bf36a83 2069 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
bogdanm 0:9b334a45a8ff 2070
bogdanm 0:9b334a45a8ff 2071 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 113:b3775bf36a83 2072 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
bogdanm 0:9b334a45a8ff 2073
bogdanm 0:9b334a45a8ff 2074 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2075 /* */
bogdanm 0:9b334a45a8ff 2076 /* Independent WATCHDOG (IWDG) */
bogdanm 0:9b334a45a8ff 2077 /* */
bogdanm 0:9b334a45a8ff 2078 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2079 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 113:b3775bf36a83 2080 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
bogdanm 0:9b334a45a8ff 2081
bogdanm 0:9b334a45a8ff 2082 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 113:b3775bf36a83 2083 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
mbed_official 113:b3775bf36a83 2084 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2085 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2086 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2087
bogdanm 0:9b334a45a8ff 2088 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 113:b3775bf36a83 2089 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
bogdanm 0:9b334a45a8ff 2090
bogdanm 0:9b334a45a8ff 2091 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 113:b3775bf36a83 2092 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
mbed_official 113:b3775bf36a83 2093 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
mbed_official 113:b3775bf36a83 2094 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
bogdanm 0:9b334a45a8ff 2095
bogdanm 0:9b334a45a8ff 2096 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 113:b3775bf36a83 2097 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
bogdanm 0:9b334a45a8ff 2098
bogdanm 0:9b334a45a8ff 2099 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2100 /* */
bogdanm 0:9b334a45a8ff 2101 /* LCD Controller (LCD) */
bogdanm 0:9b334a45a8ff 2102 /* */
bogdanm 0:9b334a45a8ff 2103 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2104
bogdanm 0:9b334a45a8ff 2105 /******************* Bit definition for LCD_CR register *********************/
mbed_official 113:b3775bf36a83 2106 #define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
mbed_official 113:b3775bf36a83 2107 #define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
mbed_official 113:b3775bf36a83 2108
mbed_official 113:b3775bf36a83 2109 #define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
mbed_official 113:b3775bf36a83 2110 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
mbed_official 113:b3775bf36a83 2111 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
mbed_official 113:b3775bf36a83 2112 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
mbed_official 113:b3775bf36a83 2113
mbed_official 113:b3775bf36a83 2114 #define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
mbed_official 113:b3775bf36a83 2115 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
mbed_official 113:b3775bf36a83 2116 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
mbed_official 113:b3775bf36a83 2117
mbed_official 113:b3775bf36a83 2118 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
bogdanm 0:9b334a45a8ff 2119
bogdanm 0:9b334a45a8ff 2120 /******************* Bit definition for LCD_FCR register ********************/
mbed_official 113:b3775bf36a83 2121 #define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
mbed_official 113:b3775bf36a83 2122 #define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
mbed_official 113:b3775bf36a83 2123 #define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
mbed_official 113:b3775bf36a83 2124
mbed_official 113:b3775bf36a83 2125 #define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
mbed_official 113:b3775bf36a83 2126 #define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2127 #define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2128 #define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2129
mbed_official 113:b3775bf36a83 2130 #define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
mbed_official 113:b3775bf36a83 2131 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2132 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2133 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2134
mbed_official 113:b3775bf36a83 2135 #define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
mbed_official 113:b3775bf36a83 2136 #define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2137 #define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2138 #define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2139
mbed_official 113:b3775bf36a83 2140 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
mbed_official 113:b3775bf36a83 2141 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2142 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2143 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2144
mbed_official 113:b3775bf36a83 2145 #define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
mbed_official 113:b3775bf36a83 2146 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2147 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2148
mbed_official 113:b3775bf36a83 2149 #define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
mbed_official 113:b3775bf36a83 2150 #define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
bogdanm 0:9b334a45a8ff 2151
bogdanm 0:9b334a45a8ff 2152 /******************* Bit definition for LCD_SR register *********************/
mbed_official 113:b3775bf36a83 2153 #define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
mbed_official 113:b3775bf36a83 2154 #define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
mbed_official 113:b3775bf36a83 2155 #define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
mbed_official 113:b3775bf36a83 2156 #define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
mbed_official 113:b3775bf36a83 2157 #define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
mbed_official 113:b3775bf36a83 2158 #define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
bogdanm 0:9b334a45a8ff 2159
bogdanm 0:9b334a45a8ff 2160 /******************* Bit definition for LCD_CLR register ********************/
mbed_official 113:b3775bf36a83 2161 #define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
mbed_official 113:b3775bf36a83 2162 #define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
bogdanm 0:9b334a45a8ff 2163
bogdanm 0:9b334a45a8ff 2164 /******************* Bit definition for LCD_RAM register ********************/
mbed_official 113:b3775bf36a83 2165 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
bogdanm 0:9b334a45a8ff 2166
bogdanm 0:9b334a45a8ff 2167 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2168 /* */
bogdanm 0:9b334a45a8ff 2169 /* Low Power Timer (LPTTIM) */
bogdanm 0:9b334a45a8ff 2170 /* */
bogdanm 0:9b334a45a8ff 2171 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2172 /****************** Bit definition for LPTIM_ISR register *******************/
mbed_official 113:b3775bf36a83 2173 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
mbed_official 113:b3775bf36a83 2174 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
mbed_official 113:b3775bf36a83 2175 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
mbed_official 113:b3775bf36a83 2176 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
mbed_official 113:b3775bf36a83 2177 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
mbed_official 113:b3775bf36a83 2178 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
mbed_official 113:b3775bf36a83 2179 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
bogdanm 0:9b334a45a8ff 2180
bogdanm 0:9b334a45a8ff 2181 /****************** Bit definition for LPTIM_ICR register *******************/
mbed_official 113:b3775bf36a83 2182 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
mbed_official 113:b3775bf36a83 2183 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
mbed_official 113:b3775bf36a83 2184 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
mbed_official 113:b3775bf36a83 2185 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
mbed_official 113:b3775bf36a83 2186 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
mbed_official 113:b3775bf36a83 2187 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
mbed_official 113:b3775bf36a83 2188 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
bogdanm 0:9b334a45a8ff 2189
bogdanm 0:9b334a45a8ff 2190 /****************** Bit definition for LPTIM_IER register ********************/
mbed_official 113:b3775bf36a83 2191 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
mbed_official 113:b3775bf36a83 2192 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
mbed_official 113:b3775bf36a83 2193 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
mbed_official 113:b3775bf36a83 2194 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
mbed_official 113:b3775bf36a83 2195 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
mbed_official 113:b3775bf36a83 2196 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
mbed_official 113:b3775bf36a83 2197 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
bogdanm 0:9b334a45a8ff 2198
bogdanm 0:9b334a45a8ff 2199 /****************** Bit definition for LPTIM_CFGR register *******************/
mbed_official 113:b3775bf36a83 2200 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
mbed_official 113:b3775bf36a83 2201
mbed_official 113:b3775bf36a83 2202 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
mbed_official 113:b3775bf36a83 2203 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2204 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2205
mbed_official 113:b3775bf36a83 2206 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
mbed_official 113:b3775bf36a83 2207 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2208 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2209
mbed_official 113:b3775bf36a83 2210 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
mbed_official 113:b3775bf36a83 2211 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2212 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2213
mbed_official 113:b3775bf36a83 2214 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
mbed_official 113:b3775bf36a83 2215 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2216 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2217 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2218
mbed_official 113:b3775bf36a83 2219 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
mbed_official 113:b3775bf36a83 2220 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2221 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2222 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2223
mbed_official 113:b3775bf36a83 2224 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
mbed_official 113:b3775bf36a83 2225 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2226 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2227
mbed_official 113:b3775bf36a83 2228 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
mbed_official 113:b3775bf36a83 2229 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
mbed_official 113:b3775bf36a83 2230 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
mbed_official 113:b3775bf36a83 2231 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
mbed_official 113:b3775bf36a83 2232 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
mbed_official 113:b3775bf36a83 2233 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
bogdanm 0:9b334a45a8ff 2234
bogdanm 0:9b334a45a8ff 2235 /****************** Bit definition for LPTIM_CR register ********************/
mbed_official 113:b3775bf36a83 2236 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
mbed_official 113:b3775bf36a83 2237 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
mbed_official 113:b3775bf36a83 2238 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
bogdanm 0:9b334a45a8ff 2239
bogdanm 0:9b334a45a8ff 2240 /****************** Bit definition for LPTIM_CMP register *******************/
mbed_official 113:b3775bf36a83 2241 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
bogdanm 0:9b334a45a8ff 2242
bogdanm 0:9b334a45a8ff 2243 /****************** Bit definition for LPTIM_ARR register *******************/
mbed_official 113:b3775bf36a83 2244 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
bogdanm 0:9b334a45a8ff 2245
bogdanm 0:9b334a45a8ff 2246 /****************** Bit definition for LPTIM_CNT register *******************/
mbed_official 113:b3775bf36a83 2247 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
bogdanm 0:9b334a45a8ff 2248
bogdanm 0:9b334a45a8ff 2249 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2250 /* */
bogdanm 0:9b334a45a8ff 2251 /* MIFARE Firewall */
bogdanm 0:9b334a45a8ff 2252 /* */
bogdanm 0:9b334a45a8ff 2253 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2254
bogdanm 0:9b334a45a8ff 2255 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
mbed_official 113:b3775bf36a83 2256 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
mbed_official 113:b3775bf36a83 2257 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
mbed_official 113:b3775bf36a83 2258 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
mbed_official 113:b3775bf36a83 2259 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
mbed_official 113:b3775bf36a83 2260 #define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */
mbed_official 113:b3775bf36a83 2261 #define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */
bogdanm 0:9b334a45a8ff 2262
bogdanm 0:9b334a45a8ff 2263 /**************************Bit definition for CR register *********************/
mbed_official 113:b3775bf36a83 2264 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
mbed_official 113:b3775bf36a83 2265 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
mbed_official 113:b3775bf36a83 2266 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
bogdanm 0:9b334a45a8ff 2267
bogdanm 0:9b334a45a8ff 2268 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2269 /* */
bogdanm 0:9b334a45a8ff 2270 /* Power Control (PWR) */
bogdanm 0:9b334a45a8ff 2271 /* */
bogdanm 0:9b334a45a8ff 2272 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2273
bogdanm 0:9b334a45a8ff 2274 /******************** Bit definition for PWR_CR register ********************/
mbed_official 113:b3775bf36a83 2275 #define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
mbed_official 113:b3775bf36a83 2276 #define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
mbed_official 113:b3775bf36a83 2277 #define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
mbed_official 113:b3775bf36a83 2278 #define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
mbed_official 113:b3775bf36a83 2279 #define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
mbed_official 113:b3775bf36a83 2280
mbed_official 113:b3775bf36a83 2281 #define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 113:b3775bf36a83 2282 #define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2283 #define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2284 #define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2285
bogdanm 0:9b334a45a8ff 2286 /*!< PVD level configuration */
mbed_official 113:b3775bf36a83 2287 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
mbed_official 113:b3775bf36a83 2288 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
mbed_official 113:b3775bf36a83 2289 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
mbed_official 113:b3775bf36a83 2290 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
mbed_official 113:b3775bf36a83 2291 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
mbed_official 113:b3775bf36a83 2292 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
mbed_official 113:b3775bf36a83 2293 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
mbed_official 113:b3775bf36a83 2294 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
mbed_official 113:b3775bf36a83 2295
mbed_official 113:b3775bf36a83 2296 #define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
mbed_official 113:b3775bf36a83 2297 #define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
mbed_official 113:b3775bf36a83 2298 #define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
mbed_official 113:b3775bf36a83 2299
mbed_official 113:b3775bf36a83 2300 #define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
mbed_official 113:b3775bf36a83 2301 #define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2302 #define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2303 #define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */
mbed_official 113:b3775bf36a83 2304 #define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
bogdanm 0:9b334a45a8ff 2305
bogdanm 0:9b334a45a8ff 2306 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 113:b3775bf36a83 2307 #define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
mbed_official 113:b3775bf36a83 2308 #define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
mbed_official 113:b3775bf36a83 2309 #define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
mbed_official 113:b3775bf36a83 2310 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 113:b3775bf36a83 2311 #define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
mbed_official 113:b3775bf36a83 2312 #define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
mbed_official 113:b3775bf36a83 2313
mbed_official 113:b3775bf36a83 2314 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
mbed_official 113:b3775bf36a83 2315 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
mbed_official 113:b3775bf36a83 2316 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */
bogdanm 0:9b334a45a8ff 2317
bogdanm 0:9b334a45a8ff 2318 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2319 /* */
bogdanm 0:9b334a45a8ff 2320 /* Reset and Clock Control */
bogdanm 0:9b334a45a8ff 2321 /* */
bogdanm 0:9b334a45a8ff 2322 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2323
bogdanm 0:9b334a45a8ff 2324 /******************** Bit definition for RCC_CR register ********************/
mbed_official 113:b3775bf36a83 2325 #define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
mbed_official 113:b3775bf36a83 2326 #define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */
mbed_official 113:b3775bf36a83 2327 #define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */
mbed_official 113:b3775bf36a83 2328 #define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */
mbed_official 113:b3775bf36a83 2329 #define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */
mbed_official 113:b3775bf36a83 2330 #define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /*!< Internal High Speed clock out enable */
mbed_official 113:b3775bf36a83 2331 #define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
mbed_official 113:b3775bf36a83 2332 #define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
mbed_official 113:b3775bf36a83 2333 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
mbed_official 113:b3775bf36a83 2334 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
mbed_official 113:b3775bf36a83 2335 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
mbed_official 113:b3775bf36a83 2336 #define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
mbed_official 113:b3775bf36a83 2337 #define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */
mbed_official 113:b3775bf36a83 2338 #define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */
mbed_official 113:b3775bf36a83 2339 #define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */
mbed_official 113:b3775bf36a83 2340 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
mbed_official 113:b3775bf36a83 2341 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
mbed_official 113:b3775bf36a83 2342
mbed_official 113:b3775bf36a83 2343 /* Reference defines */
mbed_official 113:b3775bf36a83 2344 #define RCC_CR_CSSON RCC_CR_CSSHSEON
bogdanm 0:9b334a45a8ff 2345
bogdanm 0:9b334a45a8ff 2346 /******************** Bit definition for RCC_ICSCR register *****************/
mbed_official 113:b3775bf36a83 2347 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
mbed_official 113:b3775bf36a83 2348 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
mbed_official 113:b3775bf36a83 2349
mbed_official 113:b3775bf36a83 2350 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
mbed_official 113:b3775bf36a83 2351 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
mbed_official 113:b3775bf36a83 2352 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
mbed_official 113:b3775bf36a83 2353 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
mbed_official 113:b3775bf36a83 2354 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
mbed_official 113:b3775bf36a83 2355 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
mbed_official 113:b3775bf36a83 2356 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
mbed_official 113:b3775bf36a83 2357 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
mbed_official 113:b3775bf36a83 2358 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
mbed_official 113:b3775bf36a83 2359 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
bogdanm 0:9b334a45a8ff 2360
bogdanm 0:9b334a45a8ff 2361 /******************** Bit definition for RCC_CRRCR register *****************/
mbed_official 113:b3775bf36a83 2362 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */
mbed_official 113:b3775bf36a83 2363 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */
mbed_official 113:b3775bf36a83 2364 #define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004U) /*!< HSI 48MHz DIV6 out enable */
mbed_official 113:b3775bf36a83 2365 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */
bogdanm 0:9b334a45a8ff 2366
bogdanm 0:9b334a45a8ff 2367 /******************* Bit definition for RCC_CFGR register *******************/
bogdanm 0:9b334a45a8ff 2368 /*!< SW configuration */
mbed_official 113:b3775bf36a83 2369 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 113:b3775bf36a83 2370 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2371 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2372
mbed_official 113:b3775bf36a83 2373 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
mbed_official 113:b3775bf36a83 2374 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
mbed_official 113:b3775bf36a83 2375 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
mbed_official 113:b3775bf36a83 2376 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
bogdanm 0:9b334a45a8ff 2377
bogdanm 0:9b334a45a8ff 2378 /*!< SWS configuration */
mbed_official 113:b3775bf36a83 2379 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 113:b3775bf36a83 2380 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2381 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2382
mbed_official 113:b3775bf36a83 2383 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
mbed_official 113:b3775bf36a83 2384 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
mbed_official 113:b3775bf36a83 2385 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
mbed_official 113:b3775bf36a83 2386 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 2387
bogdanm 0:9b334a45a8ff 2388 /*!< HPRE configuration */
mbed_official 113:b3775bf36a83 2389 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 113:b3775bf36a83 2390 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2391 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2392 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2393 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 2394
mbed_official 113:b3775bf36a83 2395 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
mbed_official 113:b3775bf36a83 2396 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
mbed_official 113:b3775bf36a83 2397 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
mbed_official 113:b3775bf36a83 2398 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
mbed_official 113:b3775bf36a83 2399 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
mbed_official 113:b3775bf36a83 2400 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
mbed_official 113:b3775bf36a83 2401 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
mbed_official 113:b3775bf36a83 2402 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
mbed_official 113:b3775bf36a83 2403 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
bogdanm 0:9b334a45a8ff 2404
bogdanm 0:9b334a45a8ff 2405 /*!< PPRE1 configuration */
mbed_official 113:b3775bf36a83 2406 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 113:b3775bf36a83 2407 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2408 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2409 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2410
mbed_official 113:b3775bf36a83 2411 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
mbed_official 113:b3775bf36a83 2412 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
mbed_official 113:b3775bf36a83 2413 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
mbed_official 113:b3775bf36a83 2414 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
mbed_official 113:b3775bf36a83 2415 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 2416
bogdanm 0:9b334a45a8ff 2417 /*!< PPRE2 configuration */
mbed_official 113:b3775bf36a83 2418 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 113:b3775bf36a83 2419 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2420 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2421 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2422
mbed_official 113:b3775bf36a83 2423 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
mbed_official 113:b3775bf36a83 2424 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
mbed_official 113:b3775bf36a83 2425 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
mbed_official 113:b3775bf36a83 2426 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
mbed_official 113:b3775bf36a83 2427 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
mbed_official 113:b3775bf36a83 2428
mbed_official 113:b3775bf36a83 2429 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */
bogdanm 0:9b334a45a8ff 2430
bogdanm 0:9b334a45a8ff 2431 /*!< PLL entry clock source*/
mbed_official 113:b3775bf36a83 2432 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
mbed_official 113:b3775bf36a83 2433
mbed_official 113:b3775bf36a83 2434 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
mbed_official 113:b3775bf36a83 2435 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
bogdanm 0:9b334a45a8ff 2436
bogdanm 0:9b334a45a8ff 2437
bogdanm 0:9b334a45a8ff 2438 /*!< PLLMUL configuration */
mbed_official 113:b3775bf36a83 2439 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 113:b3775bf36a83 2440 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2441 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2442 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2443 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 2444
mbed_official 113:b3775bf36a83 2445 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
mbed_official 113:b3775bf36a83 2446 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
mbed_official 113:b3775bf36a83 2447 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
mbed_official 113:b3775bf36a83 2448 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
mbed_official 113:b3775bf36a83 2449 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
mbed_official 113:b3775bf36a83 2450 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
mbed_official 113:b3775bf36a83 2451 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
mbed_official 113:b3775bf36a83 2452 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
mbed_official 113:b3775bf36a83 2453 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
bogdanm 0:9b334a45a8ff 2454
bogdanm 0:9b334a45a8ff 2455 /*!< PLLDIV configuration */
mbed_official 113:b3775bf36a83 2456 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
mbed_official 113:b3775bf36a83 2457 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
mbed_official 113:b3775bf36a83 2458 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
mbed_official 113:b3775bf36a83 2459
mbed_official 113:b3775bf36a83 2460 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
mbed_official 113:b3775bf36a83 2461 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
mbed_official 113:b3775bf36a83 2462 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
bogdanm 0:9b334a45a8ff 2463
bogdanm 0:9b334a45a8ff 2464 /*!< MCO configuration */
mbed_official 113:b3775bf36a83 2465 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
mbed_official 113:b3775bf36a83 2466 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2467 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 2468 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 2469 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 2470
mbed_official 113:b3775bf36a83 2471 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
mbed_official 113:b3775bf36a83 2472 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */
mbed_official 113:b3775bf36a83 2473 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
mbed_official 113:b3775bf36a83 2474 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
mbed_official 113:b3775bf36a83 2475 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
mbed_official 113:b3775bf36a83 2476 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
mbed_official 113:b3775bf36a83 2477 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
mbed_official 113:b3775bf36a83 2478 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
mbed_official 113:b3775bf36a83 2479 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */
mbed_official 113:b3775bf36a83 2480
mbed_official 113:b3775bf36a83 2481 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
mbed_official 113:b3775bf36a83 2482 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
mbed_official 113:b3775bf36a83 2483 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
mbed_official 113:b3775bf36a83 2484 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */
mbed_official 113:b3775bf36a83 2485
mbed_official 113:b3775bf36a83 2486 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
mbed_official 113:b3775bf36a83 2487 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
mbed_official 113:b3775bf36a83 2488 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
mbed_official 113:b3775bf36a83 2489 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
mbed_official 113:b3775bf36a83 2490 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
mbed_official 113:b3775bf36a83 2491
mbed_official 113:b3775bf36a83 2492 /* Legacy defines */
mbed_official 113:b3775bf36a83 2493 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
mbed_official 113:b3775bf36a83 2494 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
mbed_official 113:b3775bf36a83 2495 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
mbed_official 113:b3775bf36a83 2496 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
mbed_official 113:b3775bf36a83 2497 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
mbed_official 113:b3775bf36a83 2498 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
bogdanm 0:9b334a45a8ff 2499
bogdanm 0:9b334a45a8ff 2500 /*!<****************** Bit definition for RCC_CIER register ********************/
mbed_official 113:b3775bf36a83 2501 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2502 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2503 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2504 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2505 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2506 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2507 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */
mbed_official 113:b3775bf36a83 2508 #define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */
mbed_official 113:b3775bf36a83 2509
mbed_official 113:b3775bf36a83 2510 /* Reference defines */
mbed_official 113:b3775bf36a83 2511 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
bogdanm 0:9b334a45a8ff 2512
bogdanm 0:9b334a45a8ff 2513 /*!<****************** Bit definition for RCC_CIFR register ********************/
mbed_official 113:b3775bf36a83 2514 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2515 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2516 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2517 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2518 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2519 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2520 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */
mbed_official 113:b3775bf36a83 2521 #define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */
mbed_official 113:b3775bf36a83 2522 #define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */
mbed_official 113:b3775bf36a83 2523
mbed_official 113:b3775bf36a83 2524 /* Reference defines */
mbed_official 113:b3775bf36a83 2525 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
mbed_official 113:b3775bf36a83 2526 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
bogdanm 0:9b334a45a8ff 2527
bogdanm 0:9b334a45a8ff 2528 /*!<****************** Bit definition for RCC_CICR register ********************/
mbed_official 113:b3775bf36a83 2529 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2530 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2531 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2532 #define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2533 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2534 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2535 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */
mbed_official 113:b3775bf36a83 2536 #define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */
mbed_official 113:b3775bf36a83 2537 #define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */
mbed_official 113:b3775bf36a83 2538
mbed_official 113:b3775bf36a83 2539 /* Reference defines */
mbed_official 113:b3775bf36a83 2540 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
mbed_official 113:b3775bf36a83 2541 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC
bogdanm 0:9b334a45a8ff 2542 /***************** Bit definition for RCC_IOPRSTR register ******************/
mbed_official 113:b3775bf36a83 2543 #define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
mbed_official 113:b3775bf36a83 2544 #define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
mbed_official 113:b3775bf36a83 2545 #define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
mbed_official 113:b3775bf36a83 2546 #define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
mbed_official 113:b3775bf36a83 2547 #define RCC_IOPRSTR_IOPERST ((uint32_t)0x00000010U) /*!< GPIO port E reset */
mbed_official 113:b3775bf36a83 2548 #define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */
mbed_official 113:b3775bf36a83 2549
mbed_official 113:b3775bf36a83 2550 /* Reference defines */
mbed_official 113:b3775bf36a83 2551 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
mbed_official 113:b3775bf36a83 2552 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
mbed_official 113:b3775bf36a83 2553 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
mbed_official 113:b3775bf36a83 2554 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
mbed_official 113:b3775bf36a83 2555 #define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
mbed_official 113:b3775bf36a83 2556 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
mbed_official 113:b3775bf36a83 2557
bogdanm 0:9b334a45a8ff 2558
bogdanm 0:9b334a45a8ff 2559 /****************** Bit definition for RCC_AHBRST register ******************/
mbed_official 113:b3775bf36a83 2560 #define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */
mbed_official 113:b3775bf36a83 2561 #define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */
mbed_official 113:b3775bf36a83 2562 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
mbed_official 113:b3775bf36a83 2563 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */
mbed_official 113:b3775bf36a83 2564 #define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */
mbed_official 113:b3775bf36a83 2565
mbed_official 113:b3775bf36a83 2566 /* Reference defines */
mbed_official 113:b3775bf36a83 2567 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
bogdanm 0:9b334a45a8ff 2568
bogdanm 0:9b334a45a8ff 2569 /***************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 113:b3775bf36a83 2570 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */
mbed_official 113:b3775bf36a83 2571 #define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */
mbed_official 113:b3775bf36a83 2572 #define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */
mbed_official 113:b3775bf36a83 2573 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */
mbed_official 113:b3775bf36a83 2574 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */
mbed_official 113:b3775bf36a83 2575 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */
mbed_official 113:b3775bf36a83 2576 #define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */
mbed_official 113:b3775bf36a83 2577
mbed_official 113:b3775bf36a83 2578 /* Reference defines */
mbed_official 113:b3775bf36a83 2579 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
mbed_official 113:b3775bf36a83 2580 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
bogdanm 0:9b334a45a8ff 2581
bogdanm 0:9b334a45a8ff 2582 /***************** Bit definition for RCC_APB1RSTR register *****************/
mbed_official 113:b3775bf36a83 2583 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */
mbed_official 113:b3775bf36a83 2584 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /*!< Timer 3 clock reset */
mbed_official 113:b3775bf36a83 2585 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */
mbed_official 113:b3775bf36a83 2586 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /*!< Timer 7 clock reset */
mbed_official 113:b3775bf36a83 2587 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */
mbed_official 113:b3775bf36a83 2588 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */
mbed_official 113:b3775bf36a83 2589 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */
mbed_official 113:b3775bf36a83 2590 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */
mbed_official 113:b3775bf36a83 2591 #define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */
mbed_official 113:b3775bf36a83 2592 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000U) /*!< USART4 clock reset */
mbed_official 113:b3775bf36a83 2593 #define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000U) /*!< USART5 clock reset */
mbed_official 113:b3775bf36a83 2594 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */
mbed_official 113:b3775bf36a83 2595 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */
mbed_official 113:b3775bf36a83 2596 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */
mbed_official 113:b3775bf36a83 2597 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */
mbed_official 113:b3775bf36a83 2598 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */
mbed_official 113:b3775bf36a83 2599 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */
mbed_official 113:b3775bf36a83 2600 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000U) /*!< I2C 3 clock reset */
mbed_official 113:b3775bf36a83 2601 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */
bogdanm 0:9b334a45a8ff 2602
bogdanm 0:9b334a45a8ff 2603 /***************** Bit definition for RCC_IOPENR register ******************/
mbed_official 113:b3775bf36a83 2604 #define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
mbed_official 113:b3775bf36a83 2605 #define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
mbed_official 113:b3775bf36a83 2606 #define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
mbed_official 113:b3775bf36a83 2607 #define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
mbed_official 113:b3775bf36a83 2608 #define RCC_IOPENR_IOPEEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enable */
mbed_official 113:b3775bf36a83 2609 #define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */
mbed_official 113:b3775bf36a83 2610
mbed_official 113:b3775bf36a83 2611 /* Reference defines */
mbed_official 113:b3775bf36a83 2612 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
mbed_official 113:b3775bf36a83 2613 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
mbed_official 113:b3775bf36a83 2614 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
mbed_official 113:b3775bf36a83 2615 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
mbed_official 113:b3775bf36a83 2616 #define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
mbed_official 113:b3775bf36a83 2617 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
bogdanm 0:9b334a45a8ff 2618
bogdanm 0:9b334a45a8ff 2619 /***************** Bit definition for RCC_AHBENR register ******************/
mbed_official 113:b3775bf36a83 2620 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */
mbed_official 113:b3775bf36a83 2621 #define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */
mbed_official 113:b3775bf36a83 2622 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
mbed_official 113:b3775bf36a83 2623 #define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */
mbed_official 113:b3775bf36a83 2624 #define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */
mbed_official 113:b3775bf36a83 2625
mbed_official 113:b3775bf36a83 2626 /* Reference defines */
mbed_official 113:b3775bf36a83 2627 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
bogdanm 0:9b334a45a8ff 2628
bogdanm 0:9b334a45a8ff 2629 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 113:b3775bf36a83 2630 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */
mbed_official 113:b3775bf36a83 2631 #define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */
mbed_official 113:b3775bf36a83 2632 #define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */
mbed_official 113:b3775bf36a83 2633 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */
mbed_official 113:b3775bf36a83 2634 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
mbed_official 113:b3775bf36a83 2635 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
mbed_official 113:b3775bf36a83 2636 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
mbed_official 113:b3775bf36a83 2637 #define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */
mbed_official 113:b3775bf36a83 2638
mbed_official 113:b3775bf36a83 2639 /* Reference defines */
mbed_official 113:b3775bf36a83 2640
mbed_official 113:b3775bf36a83 2641 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
mbed_official 113:b3775bf36a83 2642 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 113:b3775bf36a83 2643 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
bogdanm 0:9b334a45a8ff 2644
bogdanm 0:9b334a45a8ff 2645 /***************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 113:b3775bf36a83 2646 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */
mbed_official 113:b3775bf36a83 2647 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /*!< Timer 3 clock enable */
mbed_official 113:b3775bf36a83 2648 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
mbed_official 113:b3775bf36a83 2649 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /*!< Timer 7 clock enable */
mbed_official 113:b3775bf36a83 2650 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
mbed_official 113:b3775bf36a83 2651 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
mbed_official 113:b3775bf36a83 2652 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */
mbed_official 113:b3775bf36a83 2653 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */
mbed_official 113:b3775bf36a83 2654 #define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */
mbed_official 113:b3775bf36a83 2655 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000U) /*!< USART4 clock enable */
mbed_official 113:b3775bf36a83 2656 #define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000U) /*!< USART5 clock enable */
mbed_official 113:b3775bf36a83 2657 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */
mbed_official 113:b3775bf36a83 2658 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */
mbed_official 113:b3775bf36a83 2659 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
mbed_official 113:b3775bf36a83 2660 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */
mbed_official 113:b3775bf36a83 2661 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */
mbed_official 113:b3775bf36a83 2662 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */
mbed_official 113:b3775bf36a83 2663 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000U) /*!< I2C3 clock enable */
mbed_official 113:b3775bf36a83 2664 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */
bogdanm 0:9b334a45a8ff 2665
bogdanm 0:9b334a45a8ff 2666 /****************** Bit definition for RCC_IOPSMENR register ****************/
mbed_official 113:b3775bf36a83 2667 #define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2668 #define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2669 #define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2670 #define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2671 #define RCC_IOPSMENR_IOPESMEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2672 #define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2673
mbed_official 113:b3775bf36a83 2674 /* Reference defines */
mbed_official 113:b3775bf36a83 2675 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2676 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2677 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2678 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2679 #define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2680 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
bogdanm 0:9b334a45a8ff 2681
bogdanm 0:9b334a45a8ff 2682 /***************** Bit definition for RCC_AHBSMENR register ******************/
mbed_official 113:b3775bf36a83 2683 #define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2684 #define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */
mbed_official 113:b3775bf36a83 2685 #define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2686 #define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2687 #define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2688 #define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2689
mbed_official 113:b3775bf36a83 2690 /* Reference defines */
mbed_official 113:b3775bf36a83 2691 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
bogdanm 0:9b334a45a8ff 2692
bogdanm 0:9b334a45a8ff 2693 /***************** Bit definition for RCC_APB2SMENR register ******************/
mbed_official 113:b3775bf36a83 2694 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2695 #define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2696 #define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2697 #define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2698 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2699 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2700 #define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2701
mbed_official 113:b3775bf36a83 2702 /* Reference defines */
mbed_official 113:b3775bf36a83 2703 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2704 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
bogdanm 0:9b334a45a8ff 2705
bogdanm 0:9b334a45a8ff 2706 /***************** Bit definition for RCC_APB1SMENR register ******************/
mbed_official 113:b3775bf36a83 2707 #define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2708 #define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002U) /*!< Timer 3 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2709 #define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2710 #define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020U) /*!< Timer 7 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2711 #define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2712 #define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2713 #define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2714 #define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2715 #define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2716 #define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000U) /*!< USART4 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2717 #define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000U) /*!< USART5 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2718 #define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2719 #define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2720 #define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2721 #define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2722 #define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2723 #define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2724 #define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000U) /*!< I2C3 clock enabled in sleep mode */
mbed_official 113:b3775bf36a83 2725 #define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */
bogdanm 0:9b334a45a8ff 2726
bogdanm 0:9b334a45a8ff 2727 /******************* Bit definition for RCC_CCIPR register *******************/
bogdanm 0:9b334a45a8ff 2728 /*!< USART1 Clock source selection */
mbed_official 113:b3775bf36a83 2729 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */
mbed_official 113:b3775bf36a83 2730 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2731 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2732
bogdanm 0:9b334a45a8ff 2733 /*!< USART2 Clock source selection */
mbed_official 113:b3775bf36a83 2734 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */
mbed_official 113:b3775bf36a83 2735 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2736 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2737
bogdanm 0:9b334a45a8ff 2738 /*!< LPUART1 Clock source selection */
bogdanm 0:9b334a45a8ff 2739 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
bogdanm 0:9b334a45a8ff 2740 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2741 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2742
bogdanm 0:9b334a45a8ff 2743 /*!< I2C1 Clock source selection */
mbed_official 113:b3775bf36a83 2744 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */
mbed_official 113:b3775bf36a83 2745 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2746 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2747
bogdanm 0:9b334a45a8ff 2748 /*!< I2C3 Clock source selection */
mbed_official 113:b3775bf36a83 2749 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U) /*!< I2C3SEL [1:0] bits */
mbed_official 113:b3775bf36a83 2750 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2751 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2752
bogdanm 0:9b334a45a8ff 2753 /*!< LPTIM1 Clock source selection */
mbed_official 113:b3775bf36a83 2754 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */
mbed_official 113:b3775bf36a83 2755 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2756 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2757
bogdanm 0:9b334a45a8ff 2758 /*!< HSI48 Clock source selection */
mbed_official 113:b3775bf36a83 2759 #define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/
mbed_official 113:b3775bf36a83 2760
mbed_official 113:b3775bf36a83 2761 /* Legacy defines */
bogdanm 0:9b334a45a8ff 2762 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
bogdanm 0:9b334a45a8ff 2763
bogdanm 0:9b334a45a8ff 2764 /******************* Bit definition for RCC_CSR register *******************/
mbed_official 113:b3775bf36a83 2765 #define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
mbed_official 113:b3775bf36a83 2766 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
mbed_official 113:b3775bf36a83 2767
mbed_official 113:b3775bf36a83 2768 #define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
mbed_official 113:b3775bf36a83 2769 #define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
mbed_official 113:b3775bf36a83 2770 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
bogdanm 0:9b334a45a8ff 2771
mbed_official 113:b3775bf36a83 2772 #define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 113:b3775bf36a83 2773 #define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2774 #define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2775
mbed_official 113:b3775bf36a83 2776 #define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */
mbed_official 113:b3775bf36a83 2777 #define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */
bogdanm 0:9b334a45a8ff 2778
bogdanm 0:9b334a45a8ff 2779 /*!< RTC congiguration */
mbed_official 113:b3775bf36a83 2780 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 113:b3775bf36a83 2781 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 2782 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2783
mbed_official 113:b3775bf36a83 2784 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
mbed_official 113:b3775bf36a83 2785 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
mbed_official 113:b3775bf36a83 2786 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
mbed_official 113:b3775bf36a83 2787 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */
bogdanm 0:9b334a45a8ff 2788
mbed_official 113:b3775bf36a83 2789 #define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */
mbed_official 113:b3775bf36a83 2790 #define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */
mbed_official 113:b3775bf36a83 2791
mbed_official 113:b3775bf36a83 2792 #define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */
mbed_official 113:b3775bf36a83 2793 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */
mbed_official 113:b3775bf36a83 2794 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */
mbed_official 113:b3775bf36a83 2795 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
mbed_official 113:b3775bf36a83 2796 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
mbed_official 113:b3775bf36a83 2797 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
mbed_official 113:b3775bf36a83 2798 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
mbed_official 113:b3775bf36a83 2799 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
mbed_official 113:b3775bf36a83 2800 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
mbed_official 113:b3775bf36a83 2801
mbed_official 113:b3775bf36a83 2802 /* Reference defines */
mbed_official 113:b3775bf36a83 2803 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 113:b3775bf36a83 2804
bogdanm 0:9b334a45a8ff 2805
bogdanm 0:9b334a45a8ff 2806 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2807 /* */
bogdanm 0:9b334a45a8ff 2808 /* RNG */
bogdanm 0:9b334a45a8ff 2809 /* */
bogdanm 0:9b334a45a8ff 2810 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2811 /******************** Bits definition for RNG_CR register *******************/
mbed_official 113:b3775bf36a83 2812 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 2813 #define RNG_CR_IE ((uint32_t)0x00000008U)
bogdanm 0:9b334a45a8ff 2814
bogdanm 0:9b334a45a8ff 2815 /******************** Bits definition for RNG_SR register *******************/
mbed_official 113:b3775bf36a83 2816 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
mbed_official 113:b3775bf36a83 2817 #define RNG_SR_CECS ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 2818 #define RNG_SR_SECS ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 2819 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 2820 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
bogdanm 0:9b334a45a8ff 2821
bogdanm 0:9b334a45a8ff 2822 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2823 /* */
bogdanm 0:9b334a45a8ff 2824 /* Real-Time Clock (RTC) */
bogdanm 0:9b334a45a8ff 2825 /* */
bogdanm 0:9b334a45a8ff 2826 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2827 /******************** Bits definition for RTC_TR register *******************/
mbed_official 113:b3775bf36a83 2828 #define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 2829 #define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */
mbed_official 113:b3775bf36a83 2830 #define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 2831 #define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 2832 #define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */
mbed_official 113:b3775bf36a83 2833 #define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2834 #define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 2835 #define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 2836 #define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 2837 #define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */
mbed_official 113:b3775bf36a83 2838 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 2839 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 2840 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 2841 #define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 2842 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 2843 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 2844 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 2845 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 2846 #define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */
mbed_official 113:b3775bf36a83 2847 #define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 2848 #define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 2849 #define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 2850 #define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 2851 #define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 2852 #define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 2853 #define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 2854 #define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 2855
bogdanm 0:9b334a45a8ff 2856 /******************** Bits definition for RTC_DR register *******************/
mbed_official 113:b3775bf36a83 2857 #define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */
mbed_official 113:b3775bf36a83 2858 #define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 2859 #define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 2860 #define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 2861 #define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */
mbed_official 113:b3775bf36a83 2862 #define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */
mbed_official 113:b3775bf36a83 2863 #define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2864 #define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 2865 #define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 2866 #define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 2867 #define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */
mbed_official 113:b3775bf36a83 2868 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 2869 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 2870 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 2871 #define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 2872 #define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 2873 #define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 2874 #define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 2875 #define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 2876 #define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 2877 #define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */
mbed_official 113:b3775bf36a83 2878 #define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 2879 #define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 2880 #define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 2881 #define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 2882 #define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 2883 #define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 2884 #define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 2885
bogdanm 0:9b334a45a8ff 2886 /******************** Bits definition for RTC_CR register *******************/
mbed_official 113:b3775bf36a83 2887 #define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */
mbed_official 113:b3775bf36a83 2888 #define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */
mbed_official 113:b3775bf36a83 2889 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 2890 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 2891 #define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 2892 #define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 2893 #define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 2894 #define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 2895 #define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2896 #define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 2897 #define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 2898 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 2899 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 2900 #define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 2901 #define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 2902 #define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 2903 #define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 2904 #define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 2905 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 2906 #define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 2907 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */
mbed_official 113:b3775bf36a83 2908 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */
mbed_official 113:b3775bf36a83 2909 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 2910 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 2911 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */
bogdanm 0:9b334a45a8ff 2912
bogdanm 0:9b334a45a8ff 2913 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 113:b3775bf36a83 2914 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2915 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 2916 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 2917 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 2918 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 2919 #define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 2920 #define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 2921 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 2922 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 2923 #define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */
mbed_official 113:b3775bf36a83 2924 #define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 2925 #define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 2926 #define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 2927 #define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */
mbed_official 113:b3775bf36a83 2928 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 2929 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 2930 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */
bogdanm 0:9b334a45a8ff 2931
bogdanm 0:9b334a45a8ff 2932 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 113:b3775bf36a83 2933 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */
mbed_official 113:b3775bf36a83 2934 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */
bogdanm 0:9b334a45a8ff 2935
bogdanm 0:9b334a45a8ff 2936 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 113:b3775bf36a83 2937 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
bogdanm 0:9b334a45a8ff 2938
bogdanm 0:9b334a45a8ff 2939 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 113:b3775bf36a83 2940 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */
mbed_official 113:b3775bf36a83 2941 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */
mbed_official 113:b3775bf36a83 2942 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */
mbed_official 113:b3775bf36a83 2943 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */
mbed_official 113:b3775bf36a83 2944 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */
mbed_official 113:b3775bf36a83 2945 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */
mbed_official 113:b3775bf36a83 2946 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */
mbed_official 113:b3775bf36a83 2947 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */
mbed_official 113:b3775bf36a83 2948 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */
mbed_official 113:b3775bf36a83 2949 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */
mbed_official 113:b3775bf36a83 2950 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */
mbed_official 113:b3775bf36a83 2951 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 2952 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */
mbed_official 113:b3775bf36a83 2953 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 2954 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 2955 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */
mbed_official 113:b3775bf36a83 2956 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2957 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 2958 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 2959 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 2960 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 2961 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */
mbed_official 113:b3775bf36a83 2962 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 2963 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 2964 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 2965 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 2966 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 2967 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 2968 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 2969 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 2970 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */
mbed_official 113:b3775bf36a83 2971 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */
mbed_official 113:b3775bf36a83 2972 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 2973 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 2974 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 2975 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 2976 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 2977 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 2978 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 2979 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 2980
bogdanm 0:9b334a45a8ff 2981 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 113:b3775bf36a83 2982 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */
mbed_official 113:b3775bf36a83 2983 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */
mbed_official 113:b3775bf36a83 2984 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */
mbed_official 113:b3775bf36a83 2985 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */
mbed_official 113:b3775bf36a83 2986 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */
mbed_official 113:b3775bf36a83 2987 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */
mbed_official 113:b3775bf36a83 2988 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */
mbed_official 113:b3775bf36a83 2989 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */
mbed_official 113:b3775bf36a83 2990 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */
mbed_official 113:b3775bf36a83 2991 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */
mbed_official 113:b3775bf36a83 2992 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */
mbed_official 113:b3775bf36a83 2993 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 2994 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */
mbed_official 113:b3775bf36a83 2995 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 2996 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 2997 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */
mbed_official 113:b3775bf36a83 2998 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 2999 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 3000 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 3001 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 3002 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 3003 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */
mbed_official 113:b3775bf36a83 3004 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 3005 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 3006 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 3007 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 3008 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 3009 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 3010 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 3011 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 3012 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */
mbed_official 113:b3775bf36a83 3013 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */
mbed_official 113:b3775bf36a83 3014 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 3015 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 3016 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 3017 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 3018 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 3019 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3020 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 3021 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 3022
bogdanm 0:9b334a45a8ff 3023 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 113:b3775bf36a83 3024 #define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */
bogdanm 0:9b334a45a8ff 3025
bogdanm 0:9b334a45a8ff 3026 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 113:b3775bf36a83 3027 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */
bogdanm 0:9b334a45a8ff 3028
bogdanm 0:9b334a45a8ff 3029 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 113:b3775bf36a83 3030 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */
mbed_official 113:b3775bf36a83 3031 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */
bogdanm 0:9b334a45a8ff 3032
bogdanm 0:9b334a45a8ff 3033 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 113:b3775bf36a83 3034 #define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 3035 #define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */
mbed_official 113:b3775bf36a83 3036 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 3037 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 3038 #define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */
mbed_official 113:b3775bf36a83 3039 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 3040 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 3041 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 3042 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 3043 #define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */
mbed_official 113:b3775bf36a83 3044 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 3045 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 3046 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 3047 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 3048 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 3049 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 3050 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 3051 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 3052 #define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */
mbed_official 113:b3775bf36a83 3053 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 3054 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 3055 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 3056 #define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 3057 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 3058 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3059 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 3060 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 3061
bogdanm 0:9b334a45a8ff 3062 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 113:b3775bf36a83 3063 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */
mbed_official 113:b3775bf36a83 3064 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 3065 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 3066 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 3067 #define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 3068 #define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */
mbed_official 113:b3775bf36a83 3069 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 3070 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 3071 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 3072 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 3073 #define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */
mbed_official 113:b3775bf36a83 3074 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 3075 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 3076 #define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */
mbed_official 113:b3775bf36a83 3077 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 3078 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3079 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 3080 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */
bogdanm 0:9b334a45a8ff 3081
bogdanm 0:9b334a45a8ff 3082 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 113:b3775bf36a83 3083 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
mbed_official 113:b3775bf36a83 3084
mbed_official 113:b3775bf36a83 3085 /******************** Bits definition for RTC_CALR register *****************/
mbed_official 113:b3775bf36a83 3086 #define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 3087 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 3088 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 3089 #define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */
mbed_official 113:b3775bf36a83 3090 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 3091 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3092 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 3093 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */
mbed_official 113:b3775bf36a83 3094 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 3095 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 3096 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 3097 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */
mbed_official 113:b3775bf36a83 3098 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 3099
mbed_official 113:b3775bf36a83 3100 /* Legacy defines */
mbed_official 113:b3775bf36a83 3101 #define RTC_CAL_CALP RTC_CALR_CALP
mbed_official 113:b3775bf36a83 3102 #define RTC_CAL_CALW8 RTC_CALR_CALW8
mbed_official 113:b3775bf36a83 3103 #define RTC_CAL_CALW16 RTC_CALR_CALW16
mbed_official 113:b3775bf36a83 3104 #define RTC_CAL_CALM RTC_CALR_CALM
mbed_official 113:b3775bf36a83 3105 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
mbed_official 113:b3775bf36a83 3106 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
mbed_official 113:b3775bf36a83 3107 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
mbed_official 113:b3775bf36a83 3108 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
mbed_official 113:b3775bf36a83 3109 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
mbed_official 113:b3775bf36a83 3110 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
mbed_official 113:b3775bf36a83 3111 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
mbed_official 113:b3775bf36a83 3112 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
mbed_official 113:b3775bf36a83 3113 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
bogdanm 0:9b334a45a8ff 3114
bogdanm 0:9b334a45a8ff 3115 /******************** Bits definition for RTC_TAMPCR register ****************/
mbed_official 113:b3775bf36a83 3116 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /*!< */
mbed_official 113:b3775bf36a83 3117 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /*!< */
mbed_official 113:b3775bf36a83 3118 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /*!< */
mbed_official 113:b3775bf36a83 3119 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */
mbed_official 113:b3775bf36a83 3120 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */
mbed_official 113:b3775bf36a83 3121 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */
mbed_official 113:b3775bf36a83 3122 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */
mbed_official 113:b3775bf36a83 3123 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */
mbed_official 113:b3775bf36a83 3124 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */
mbed_official 113:b3775bf36a83 3125 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */
mbed_official 113:b3775bf36a83 3126 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */
mbed_official 113:b3775bf36a83 3127 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */
mbed_official 113:b3775bf36a83 3128 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */
mbed_official 113:b3775bf36a83 3129 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */
mbed_official 113:b3775bf36a83 3130 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */
mbed_official 113:b3775bf36a83 3131 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */
mbed_official 113:b3775bf36a83 3132 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */
mbed_official 113:b3775bf36a83 3133 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */
mbed_official 113:b3775bf36a83 3134 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */
mbed_official 113:b3775bf36a83 3135 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */
mbed_official 113:b3775bf36a83 3136 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */
mbed_official 113:b3775bf36a83 3137 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /*!< */
mbed_official 113:b3775bf36a83 3138 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /*!< */
mbed_official 113:b3775bf36a83 3139 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */
mbed_official 113:b3775bf36a83 3140 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */
mbed_official 113:b3775bf36a83 3141 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */
mbed_official 113:b3775bf36a83 3142 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3143 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */
bogdanm 0:9b334a45a8ff 3144
bogdanm 0:9b334a45a8ff 3145 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 113:b3775bf36a83 3146 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
mbed_official 113:b3775bf36a83 3147 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 3148 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 3149 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 3150 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 3151 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
bogdanm 0:9b334a45a8ff 3152
bogdanm 0:9b334a45a8ff 3153 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 113:b3775bf36a83 3154 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
mbed_official 113:b3775bf36a83 3155 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
mbed_official 113:b3775bf36a83 3156 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
mbed_official 113:b3775bf36a83 3157 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
mbed_official 113:b3775bf36a83 3158 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
mbed_official 113:b3775bf36a83 3159 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
bogdanm 0:9b334a45a8ff 3160
bogdanm 0:9b334a45a8ff 3161 /******************** Bits definition for RTC_OR register ****************/
mbed_official 113:b3775bf36a83 3162 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */
mbed_official 113:b3775bf36a83 3163 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */
mbed_official 113:b3775bf36a83 3164
mbed_official 113:b3775bf36a83 3165 /* Legacy defines */
bogdanm 0:9b334a45a8ff 3166 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
bogdanm 0:9b334a45a8ff 3167
bogdanm 0:9b334a45a8ff 3168 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 113:b3775bf36a83 3169 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */
bogdanm 0:9b334a45a8ff 3170
bogdanm 0:9b334a45a8ff 3171 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 113:b3775bf36a83 3172 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */
bogdanm 0:9b334a45a8ff 3173
bogdanm 0:9b334a45a8ff 3174 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 113:b3775bf36a83 3175 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */
bogdanm 0:9b334a45a8ff 3176
bogdanm 0:9b334a45a8ff 3177 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 113:b3775bf36a83 3178 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */
bogdanm 0:9b334a45a8ff 3179
bogdanm 0:9b334a45a8ff 3180 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 113:b3775bf36a83 3181 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */
mbed_official 113:b3775bf36a83 3182
mbed_official 113:b3775bf36a83 3183 /******************** Number of backup registers ******************************/
mbed_official 113:b3775bf36a83 3184 #define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */
bogdanm 0:9b334a45a8ff 3185
bogdanm 0:9b334a45a8ff 3186 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3187 /* */
bogdanm 0:9b334a45a8ff 3188 /* Serial Peripheral Interface (SPI) */
bogdanm 0:9b334a45a8ff 3189 /* */
bogdanm 0:9b334a45a8ff 3190 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3191 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 113:b3775bf36a83 3192 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
mbed_official 113:b3775bf36a83 3193 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
mbed_official 113:b3775bf36a83 3194 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
mbed_official 113:b3775bf36a83 3195 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 113:b3775bf36a83 3196 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 3197 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 3198 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 3199 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
mbed_official 113:b3775bf36a83 3200 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
mbed_official 113:b3775bf36a83 3201 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
mbed_official 113:b3775bf36a83 3202 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
mbed_official 113:b3775bf36a83 3203 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
mbed_official 113:b3775bf36a83 3204 #define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
mbed_official 113:b3775bf36a83 3205 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
mbed_official 113:b3775bf36a83 3206 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
mbed_official 113:b3775bf36a83 3207 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
mbed_official 113:b3775bf36a83 3208 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
bogdanm 0:9b334a45a8ff 3209
bogdanm 0:9b334a45a8ff 3210 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 113:b3775bf36a83 3211 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
mbed_official 113:b3775bf36a83 3212 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
mbed_official 113:b3775bf36a83 3213 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
mbed_official 113:b3775bf36a83 3214 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
mbed_official 113:b3775bf36a83 3215 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
mbed_official 113:b3775bf36a83 3216 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 113:b3775bf36a83 3217 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 3218
bogdanm 0:9b334a45a8ff 3219 /******************** Bit definition for SPI_SR register ********************/
mbed_official 113:b3775bf36a83 3220 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
mbed_official 113:b3775bf36a83 3221 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
mbed_official 113:b3775bf36a83 3222 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
mbed_official 113:b3775bf36a83 3223 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
mbed_official 113:b3775bf36a83 3224 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
mbed_official 113:b3775bf36a83 3225 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
mbed_official 113:b3775bf36a83 3226 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
mbed_official 113:b3775bf36a83 3227 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
mbed_official 113:b3775bf36a83 3228 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
bogdanm 0:9b334a45a8ff 3229
bogdanm 0:9b334a45a8ff 3230 /******************** Bit definition for SPI_DR register ********************/
mbed_official 113:b3775bf36a83 3231 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
bogdanm 0:9b334a45a8ff 3232
bogdanm 0:9b334a45a8ff 3233 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 113:b3775bf36a83 3234 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
bogdanm 0:9b334a45a8ff 3235
bogdanm 0:9b334a45a8ff 3236 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 113:b3775bf36a83 3237 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
bogdanm 0:9b334a45a8ff 3238
bogdanm 0:9b334a45a8ff 3239 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 113:b3775bf36a83 3240 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
bogdanm 0:9b334a45a8ff 3241
bogdanm 0:9b334a45a8ff 3242 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 113:b3775bf36a83 3243 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
mbed_official 113:b3775bf36a83 3244 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 113:b3775bf36a83 3245 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3246 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3247 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
mbed_official 113:b3775bf36a83 3248 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 113:b3775bf36a83 3249 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3250 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3251 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
mbed_official 113:b3775bf36a83 3252 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 113:b3775bf36a83 3253 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3254 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3255 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
mbed_official 113:b3775bf36a83 3256 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
mbed_official 113:b3775bf36a83 3257 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000U) /*!<Asynchronous start enable */
bogdanm 0:9b334a45a8ff 3258 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 113:b3775bf36a83 3259 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
mbed_official 113:b3775bf36a83 3260 #define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
mbed_official 113:b3775bf36a83 3261 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
bogdanm 0:9b334a45a8ff 3262
bogdanm 0:9b334a45a8ff 3263 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3264 /* */
bogdanm 0:9b334a45a8ff 3265 /* System Configuration (SYSCFG) */
bogdanm 0:9b334a45a8ff 3266 /* */
bogdanm 0:9b334a45a8ff 3267 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3268 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 113:b3775bf36a83 3269 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
mbed_official 113:b3775bf36a83 3270 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 113:b3775bf36a83 3271 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 113:b3775bf36a83 3272 #define SYSCFG_CFGR1_UFB ((uint32_t)0x00000008U) /*!< User bank swapping */
mbed_official 113:b3775bf36a83 3273 #define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */
mbed_official 113:b3775bf36a83 3274 #define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */
mbed_official 113:b3775bf36a83 3275 #define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */
bogdanm 0:9b334a45a8ff 3276
bogdanm 0:9b334a45a8ff 3277 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 113:b3775bf36a83 3278 #define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */
mbed_official 113:b3775bf36a83 3279 #define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000003EU) /*!< Connection of internal Vlcd rail to external capacitors */
mbed_official 113:b3775bf36a83 3280 #define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
mbed_official 113:b3775bf36a83 3281 #define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
mbed_official 113:b3775bf36a83 3282 #define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
mbed_official 113:b3775bf36a83 3283 #define SYSCFG_CFGR2_CAPA_3 ((uint32_t)0x00000010U)
mbed_official 113:b3775bf36a83 3284 #define SYSCFG_CFGR2_CAPA_4 ((uint32_t)0x00000020U)
mbed_official 113:b3775bf36a83 3285 #define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */
mbed_official 113:b3775bf36a83 3286 #define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */
mbed_official 113:b3775bf36a83 3287 #define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */
mbed_official 113:b3775bf36a83 3288 #define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */
mbed_official 113:b3775bf36a83 3289 #define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */
mbed_official 113:b3775bf36a83 3290 #define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /*!< I2C2 Fast mode plus */
mbed_official 113:b3775bf36a83 3291 #define SYSCFG_CFGR2_I2C3_FMP ((uint32_t)0x00004000U) /*!< I2C3 Fast mode plus */
bogdanm 0:9b334a45a8ff 3292
bogdanm 0:9b334a45a8ff 3293 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 113:b3775bf36a83 3294 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
mbed_official 113:b3775bf36a83 3295 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
mbed_official 113:b3775bf36a83 3296 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
mbed_official 113:b3775bf36a83 3297 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
bogdanm 0:9b334a45a8ff 3298
bogdanm 0:9b334a45a8ff 3299 /**
bogdanm 0:9b334a45a8ff 3300 * @brief EXTI0 configuration
bogdanm 0:9b334a45a8ff 3301 */
mbed_official 113:b3775bf36a83 3302 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
mbed_official 113:b3775bf36a83 3303 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
mbed_official 113:b3775bf36a83 3304 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
mbed_official 113:b3775bf36a83 3305 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!< PD[0] pin */
mbed_official 113:b3775bf36a83 3306 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!< PE[0] pin */
mbed_official 113:b3775bf36a83 3307 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
bogdanm 0:9b334a45a8ff 3308
bogdanm 0:9b334a45a8ff 3309 /**
bogdanm 0:9b334a45a8ff 3310 * @brief EXTI1 configuration
bogdanm 0:9b334a45a8ff 3311 */
mbed_official 113:b3775bf36a83 3312 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
mbed_official 113:b3775bf36a83 3313 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
mbed_official 113:b3775bf36a83 3314 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
mbed_official 113:b3775bf36a83 3315 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!< PD[1] pin */
mbed_official 113:b3775bf36a83 3316 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!< PE[1] pin */
mbed_official 113:b3775bf36a83 3317 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
bogdanm 0:9b334a45a8ff 3318
bogdanm 0:9b334a45a8ff 3319 /**
bogdanm 0:9b334a45a8ff 3320 * @brief EXTI2 configuration
bogdanm 0:9b334a45a8ff 3321 */
mbed_official 113:b3775bf36a83 3322 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
mbed_official 113:b3775bf36a83 3323 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
mbed_official 113:b3775bf36a83 3324 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
mbed_official 113:b3775bf36a83 3325 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
mbed_official 113:b3775bf36a83 3326 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!< PE[2] pin */
bogdanm 0:9b334a45a8ff 3327
bogdanm 0:9b334a45a8ff 3328 /**
bogdanm 0:9b334a45a8ff 3329 * @brief EXTI3 configuration
bogdanm 0:9b334a45a8ff 3330 */
mbed_official 113:b3775bf36a83 3331 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
mbed_official 113:b3775bf36a83 3332 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
mbed_official 113:b3775bf36a83 3333 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
mbed_official 113:b3775bf36a83 3334 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!< PD[3] pin */
mbed_official 113:b3775bf36a83 3335 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!< PE[3] pin */
bogdanm 0:9b334a45a8ff 3336
bogdanm 0:9b334a45a8ff 3337 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
mbed_official 113:b3775bf36a83 3338 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
mbed_official 113:b3775bf36a83 3339 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
mbed_official 113:b3775bf36a83 3340 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
mbed_official 113:b3775bf36a83 3341 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
bogdanm 0:9b334a45a8ff 3342
bogdanm 0:9b334a45a8ff 3343 /**
bogdanm 0:9b334a45a8ff 3344 * @brief EXTI4 configuration
bogdanm 0:9b334a45a8ff 3345 */
mbed_official 113:b3775bf36a83 3346 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
mbed_official 113:b3775bf36a83 3347 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
mbed_official 113:b3775bf36a83 3348 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
mbed_official 113:b3775bf36a83 3349 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!< PD[4] pin */
mbed_official 113:b3775bf36a83 3350 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!< PE[4] pin */
bogdanm 0:9b334a45a8ff 3351
bogdanm 0:9b334a45a8ff 3352 /**
bogdanm 0:9b334a45a8ff 3353 * @brief EXTI5 configuration
bogdanm 0:9b334a45a8ff 3354 */
mbed_official 113:b3775bf36a83 3355 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
mbed_official 113:b3775bf36a83 3356 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
mbed_official 113:b3775bf36a83 3357 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
mbed_official 113:b3775bf36a83 3358 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!< PD[5] pin */
mbed_official 113:b3775bf36a83 3359 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!< PE[5] pin */
bogdanm 0:9b334a45a8ff 3360
bogdanm 0:9b334a45a8ff 3361 /**
bogdanm 0:9b334a45a8ff 3362 * @brief EXTI6 configuration
bogdanm 0:9b334a45a8ff 3363 */
mbed_official 113:b3775bf36a83 3364 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
mbed_official 113:b3775bf36a83 3365 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
mbed_official 113:b3775bf36a83 3366 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
mbed_official 113:b3775bf36a83 3367 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!< PD[6] pin */
mbed_official 113:b3775bf36a83 3368 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!< PE[6] pin */
bogdanm 0:9b334a45a8ff 3369
bogdanm 0:9b334a45a8ff 3370 /**
bogdanm 0:9b334a45a8ff 3371 * @brief EXTI7 configuration
bogdanm 0:9b334a45a8ff 3372 */
mbed_official 113:b3775bf36a83 3373 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
mbed_official 113:b3775bf36a83 3374 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
mbed_official 113:b3775bf36a83 3375 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
mbed_official 113:b3775bf36a83 3376 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!< PD[7] pin */
mbed_official 113:b3775bf36a83 3377 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!< PE[7] pin */
bogdanm 0:9b334a45a8ff 3378
bogdanm 0:9b334a45a8ff 3379 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
mbed_official 113:b3775bf36a83 3380 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
mbed_official 113:b3775bf36a83 3381 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
mbed_official 113:b3775bf36a83 3382 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
mbed_official 113:b3775bf36a83 3383 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
bogdanm 0:9b334a45a8ff 3384
bogdanm 0:9b334a45a8ff 3385 /**
bogdanm 0:9b334a45a8ff 3386 * @brief EXTI8 configuration
bogdanm 0:9b334a45a8ff 3387 */
mbed_official 113:b3775bf36a83 3388 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
mbed_official 113:b3775bf36a83 3389 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
mbed_official 113:b3775bf36a83 3390 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
mbed_official 113:b3775bf36a83 3391 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!< PD[8] pin */
mbed_official 113:b3775bf36a83 3392 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!< PE[8] pin */
bogdanm 0:9b334a45a8ff 3393
bogdanm 0:9b334a45a8ff 3394 /**
bogdanm 0:9b334a45a8ff 3395 * @brief EXTI9 configuration
bogdanm 0:9b334a45a8ff 3396 */
mbed_official 113:b3775bf36a83 3397 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
mbed_official 113:b3775bf36a83 3398 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
mbed_official 113:b3775bf36a83 3399 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
mbed_official 113:b3775bf36a83 3400 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!< PD[9] pin */
mbed_official 113:b3775bf36a83 3401 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!< PE[9] pin */
mbed_official 113:b3775bf36a83 3402 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000050U) /*!< PH[9] pin */
bogdanm 0:9b334a45a8ff 3403
bogdanm 0:9b334a45a8ff 3404 /**
bogdanm 0:9b334a45a8ff 3405 * @brief EXTI10 configuration
bogdanm 0:9b334a45a8ff 3406 */
mbed_official 113:b3775bf36a83 3407 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
mbed_official 113:b3775bf36a83 3408 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
mbed_official 113:b3775bf36a83 3409 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
mbed_official 113:b3775bf36a83 3410 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!< PD[10] pin */
mbed_official 113:b3775bf36a83 3411 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!< PE[10] pin */
mbed_official 113:b3775bf36a83 3412 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000500U) /*!< PH[10] pin */
bogdanm 0:9b334a45a8ff 3413
bogdanm 0:9b334a45a8ff 3414 /**
bogdanm 0:9b334a45a8ff 3415 * @brief EXTI11 configuration
bogdanm 0:9b334a45a8ff 3416 */
mbed_official 113:b3775bf36a83 3417 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
mbed_official 113:b3775bf36a83 3418 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
mbed_official 113:b3775bf36a83 3419 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
mbed_official 113:b3775bf36a83 3420 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!< PD[11] pin */
mbed_official 113:b3775bf36a83 3421 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!< PE[11] pin */
bogdanm 0:9b334a45a8ff 3422
bogdanm 0:9b334a45a8ff 3423 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 113:b3775bf36a83 3424 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
mbed_official 113:b3775bf36a83 3425 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
mbed_official 113:b3775bf36a83 3426 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
mbed_official 113:b3775bf36a83 3427 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
bogdanm 0:9b334a45a8ff 3428
bogdanm 0:9b334a45a8ff 3429 /**
bogdanm 0:9b334a45a8ff 3430 * @brief EXTI12 configuration
bogdanm 0:9b334a45a8ff 3431 */
mbed_official 113:b3775bf36a83 3432 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
mbed_official 113:b3775bf36a83 3433 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
mbed_official 113:b3775bf36a83 3434 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
mbed_official 113:b3775bf36a83 3435 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!< PD[12] pin */
mbed_official 113:b3775bf36a83 3436 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!< PE[12] pin */
bogdanm 0:9b334a45a8ff 3437
bogdanm 0:9b334a45a8ff 3438 /**
bogdanm 0:9b334a45a8ff 3439 * @brief EXTI13 configuration
bogdanm 0:9b334a45a8ff 3440 */
mbed_official 113:b3775bf36a83 3441 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
mbed_official 113:b3775bf36a83 3442 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
mbed_official 113:b3775bf36a83 3443 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
mbed_official 113:b3775bf36a83 3444 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!< PD[13] pin */
mbed_official 113:b3775bf36a83 3445 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!< PE[13] pin */
bogdanm 0:9b334a45a8ff 3446
bogdanm 0:9b334a45a8ff 3447 /**
bogdanm 0:9b334a45a8ff 3448 * @brief EXTI14 configuration
bogdanm 0:9b334a45a8ff 3449 */
mbed_official 113:b3775bf36a83 3450 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
mbed_official 113:b3775bf36a83 3451 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
mbed_official 113:b3775bf36a83 3452 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
mbed_official 113:b3775bf36a83 3453 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!< PD[14] pin */
mbed_official 113:b3775bf36a83 3454 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!< PE[14] pin */
bogdanm 0:9b334a45a8ff 3455
bogdanm 0:9b334a45a8ff 3456 /**
bogdanm 0:9b334a45a8ff 3457 * @brief EXTI15 configuration
bogdanm 0:9b334a45a8ff 3458 */
mbed_official 113:b3775bf36a83 3459 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
mbed_official 113:b3775bf36a83 3460 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
mbed_official 113:b3775bf36a83 3461 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
mbed_official 113:b3775bf36a83 3462 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!< PD[15] pin */
mbed_official 113:b3775bf36a83 3463 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!< PE[15] pin */
bogdanm 0:9b334a45a8ff 3464
bogdanm 0:9b334a45a8ff 3465
bogdanm 0:9b334a45a8ff 3466 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
mbed_official 113:b3775bf36a83 3467 #define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/
mbed_official 113:b3775bf36a83 3468 #define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */
mbed_official 113:b3775bf36a83 3469 #define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 3470 #define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 3471 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */
mbed_official 113:b3775bf36a83 3472 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */
mbed_official 113:b3775bf36a83 3473 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */
mbed_official 113:b3775bf36a83 3474 #define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
mbed_official 113:b3775bf36a83 3475 #define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /*!< VREFINT for 48 MHz RC oscillator ready flag */
mbed_official 113:b3775bf36a83 3476 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */
mbed_official 113:b3775bf36a83 3477 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */
mbed_official 113:b3775bf36a83 3478 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */
mbed_official 113:b3775bf36a83 3479 #define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */
mbed_official 113:b3775bf36a83 3480 #define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */
mbed_official 113:b3775bf36a83 3481
mbed_official 113:b3775bf36a83 3482 /* Legacy defines */
bogdanm 0:9b334a45a8ff 3483
bogdanm 0:9b334a45a8ff 3484 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
bogdanm 0:9b334a45a8ff 3485 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
bogdanm 0:9b334a45a8ff 3486 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
bogdanm 0:9b334a45a8ff 3487 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
bogdanm 0:9b334a45a8ff 3488 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
bogdanm 0:9b334a45a8ff 3489 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
bogdanm 0:9b334a45a8ff 3490
bogdanm 0:9b334a45a8ff 3491 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3492 /* */
bogdanm 0:9b334a45a8ff 3493 /* Timers (TIM) */
bogdanm 0:9b334a45a8ff 3494 /* */
bogdanm 0:9b334a45a8ff 3495 /******************************************************************************/
mbed_official 113:b3775bf36a83 3496 /*
mbed_official 113:b3775bf36a83 3497 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official 113:b3775bf36a83 3498 */
mbed_official 113:b3775bf36a83 3499 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
mbed_official 113:b3775bf36a83 3500 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
mbed_official 113:b3775bf36a83 3501 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
mbed_official 113:b3775bf36a83 3502 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
mbed_official 113:b3775bf36a83 3503 #else
mbed_official 113:b3775bf36a83 3504 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
mbed_official 113:b3775bf36a83 3505 #endif
mbed_official 113:b3775bf36a83 3506
bogdanm 0:9b334a45a8ff 3507 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 113:b3775bf36a83 3508 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
mbed_official 113:b3775bf36a83 3509 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
mbed_official 113:b3775bf36a83 3510 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
mbed_official 113:b3775bf36a83 3511 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
mbed_official 113:b3775bf36a83 3512 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
mbed_official 113:b3775bf36a83 3513
mbed_official 113:b3775bf36a83 3514 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 113:b3775bf36a83 3515 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3516 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3517
mbed_official 113:b3775bf36a83 3518 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
mbed_official 113:b3775bf36a83 3519
mbed_official 113:b3775bf36a83 3520 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
mbed_official 113:b3775bf36a83 3521 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3522 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3523
bogdanm 0:9b334a45a8ff 3524 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 113:b3775bf36a83 3525 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
mbed_official 113:b3775bf36a83 3526
mbed_official 113:b3775bf36a83 3527 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 113:b3775bf36a83 3528 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3529 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3530 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3531
mbed_official 113:b3775bf36a83 3532 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
bogdanm 0:9b334a45a8ff 3533
bogdanm 0:9b334a45a8ff 3534 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 113:b3775bf36a83 3535 #define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 113:b3775bf36a83 3536 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3537 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3538 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3539
mbed_official 113:b3775bf36a83 3540 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
mbed_official 113:b3775bf36a83 3541
mbed_official 113:b3775bf36a83 3542 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 113:b3775bf36a83 3543 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3544 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3545 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3546
mbed_official 113:b3775bf36a83 3547 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
mbed_official 113:b3775bf36a83 3548
mbed_official 113:b3775bf36a83 3549 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 113:b3775bf36a83 3550 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3551 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3552 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3553 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3554
mbed_official 113:b3775bf36a83 3555 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 113:b3775bf36a83 3556 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3557 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3558
mbed_official 113:b3775bf36a83 3559 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
mbed_official 113:b3775bf36a83 3560 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
bogdanm 0:9b334a45a8ff 3561
bogdanm 0:9b334a45a8ff 3562 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 113:b3775bf36a83 3563 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
mbed_official 113:b3775bf36a83 3564 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
mbed_official 113:b3775bf36a83 3565 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
mbed_official 113:b3775bf36a83 3566 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
mbed_official 113:b3775bf36a83 3567 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
mbed_official 113:b3775bf36a83 3568 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
mbed_official 113:b3775bf36a83 3569 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
mbed_official 113:b3775bf36a83 3570 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
mbed_official 113:b3775bf36a83 3571 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
mbed_official 113:b3775bf36a83 3572 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
mbed_official 113:b3775bf36a83 3573 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
mbed_official 113:b3775bf36a83 3574 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
bogdanm 0:9b334a45a8ff 3575
bogdanm 0:9b334a45a8ff 3576 /******************** Bit definition for TIM_SR register ********************/
mbed_official 113:b3775bf36a83 3577 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
mbed_official 113:b3775bf36a83 3578 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 113:b3775bf36a83 3579 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 113:b3775bf36a83 3580 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 113:b3775bf36a83 3581 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 113:b3775bf36a83 3582 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
mbed_official 113:b3775bf36a83 3583 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 113:b3775bf36a83 3584 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 113:b3775bf36a83 3585 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 113:b3775bf36a83 3586 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 0:9b334a45a8ff 3587
bogdanm 0:9b334a45a8ff 3588 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 113:b3775bf36a83 3589 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
mbed_official 113:b3775bf36a83 3590 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
mbed_official 113:b3775bf36a83 3591 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
mbed_official 113:b3775bf36a83 3592 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
mbed_official 113:b3775bf36a83 3593 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
mbed_official 113:b3775bf36a83 3594 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
bogdanm 0:9b334a45a8ff 3595
bogdanm 0:9b334a45a8ff 3596 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 113:b3775bf36a83 3597 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 113:b3775bf36a83 3598 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3599 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3600
mbed_official 113:b3775bf36a83 3601 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
mbed_official 113:b3775bf36a83 3602 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
mbed_official 113:b3775bf36a83 3603
mbed_official 113:b3775bf36a83 3604 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 113:b3775bf36a83 3605 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3606 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3607 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3608
mbed_official 113:b3775bf36a83 3609 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
mbed_official 113:b3775bf36a83 3610
mbed_official 113:b3775bf36a83 3611 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 113:b3775bf36a83 3612 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3613 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3614
mbed_official 113:b3775bf36a83 3615 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
mbed_official 113:b3775bf36a83 3616 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
mbed_official 113:b3775bf36a83 3617
mbed_official 113:b3775bf36a83 3618 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 113:b3775bf36a83 3619 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3620 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3621 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3622
mbed_official 113:b3775bf36a83 3623 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
bogdanm 0:9b334a45a8ff 3624
bogdanm 0:9b334a45a8ff 3625 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 3626
mbed_official 113:b3775bf36a83 3627 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 113:b3775bf36a83 3628 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3629 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3630
mbed_official 113:b3775bf36a83 3631 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 113:b3775bf36a83 3632 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3633 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3634 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3635 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3636
mbed_official 113:b3775bf36a83 3637 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 113:b3775bf36a83 3638 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3639 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3640
mbed_official 113:b3775bf36a83 3641 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 113:b3775bf36a83 3642 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3643 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3644 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3645 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3646
bogdanm 0:9b334a45a8ff 3647 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 113:b3775bf36a83 3648 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 113:b3775bf36a83 3649 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3650 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3651
mbed_official 113:b3775bf36a83 3652 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
mbed_official 113:b3775bf36a83 3653 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
mbed_official 113:b3775bf36a83 3654
mbed_official 113:b3775bf36a83 3655 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 113:b3775bf36a83 3656 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3657 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3658 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3659
mbed_official 113:b3775bf36a83 3660 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
mbed_official 113:b3775bf36a83 3661
mbed_official 113:b3775bf36a83 3662 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 113:b3775bf36a83 3663 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3664 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3665
mbed_official 113:b3775bf36a83 3666 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
mbed_official 113:b3775bf36a83 3667 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
mbed_official 113:b3775bf36a83 3668
mbed_official 113:b3775bf36a83 3669 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 113:b3775bf36a83 3670 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3671 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3672 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3673
mbed_official 113:b3775bf36a83 3674 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
bogdanm 0:9b334a45a8ff 3675
bogdanm 0:9b334a45a8ff 3676 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 3677
mbed_official 113:b3775bf36a83 3678 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 113:b3775bf36a83 3679 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3680 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3681
mbed_official 113:b3775bf36a83 3682 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 113:b3775bf36a83 3683 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3684 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3685 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3686 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3687
mbed_official 113:b3775bf36a83 3688 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 113:b3775bf36a83 3689 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3690 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3691
mbed_official 113:b3775bf36a83 3692 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 113:b3775bf36a83 3693 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3694 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3695 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3696 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3697
bogdanm 0:9b334a45a8ff 3698 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 113:b3775bf36a83 3699 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
mbed_official 113:b3775bf36a83 3700 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
mbed_official 113:b3775bf36a83 3701 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 113:b3775bf36a83 3702 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
mbed_official 113:b3775bf36a83 3703 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
mbed_official 113:b3775bf36a83 3704 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 113:b3775bf36a83 3705 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
mbed_official 113:b3775bf36a83 3706 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
mbed_official 113:b3775bf36a83 3707 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 113:b3775bf36a83 3708 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
mbed_official 113:b3775bf36a83 3709 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
mbed_official 113:b3775bf36a83 3710 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 3711
bogdanm 0:9b334a45a8ff 3712 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 113:b3775bf36a83 3713 #define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
bogdanm 0:9b334a45a8ff 3714
bogdanm 0:9b334a45a8ff 3715 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 113:b3775bf36a83 3716 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
bogdanm 0:9b334a45a8ff 3717
bogdanm 0:9b334a45a8ff 3718 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 113:b3775bf36a83 3719 #define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
bogdanm 0:9b334a45a8ff 3720
bogdanm 0:9b334a45a8ff 3721 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 113:b3775bf36a83 3722 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
bogdanm 0:9b334a45a8ff 3723
bogdanm 0:9b334a45a8ff 3724 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 113:b3775bf36a83 3725 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
bogdanm 0:9b334a45a8ff 3726
bogdanm 0:9b334a45a8ff 3727 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 113:b3775bf36a83 3728 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
bogdanm 0:9b334a45a8ff 3729
bogdanm 0:9b334a45a8ff 3730 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 113:b3775bf36a83 3731 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
bogdanm 0:9b334a45a8ff 3732
bogdanm 0:9b334a45a8ff 3733 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 113:b3775bf36a83 3734 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 113:b3775bf36a83 3735 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3736 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3737 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3738 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3739 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
mbed_official 113:b3775bf36a83 3740
mbed_official 113:b3775bf36a83 3741 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 113:b3775bf36a83 3742 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3743 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3744 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3745 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3746 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 3747
bogdanm 0:9b334a45a8ff 3748 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 113:b3775bf36a83 3749 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
bogdanm 0:9b334a45a8ff 3750
bogdanm 0:9b334a45a8ff 3751 /******************* Bit definition for TIM_OR register *********************/
mbed_official 113:b3775bf36a83 3752 #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
mbed_official 113:b3775bf36a83 3753 #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3754 #define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3755 #define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3756 #define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
mbed_official 113:b3775bf36a83 3757 #define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3758 #define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3759
mbed_official 113:b3775bf36a83 3760 #define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
mbed_official 113:b3775bf36a83 3761 #define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3762 #define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3763 #define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
mbed_official 113:b3775bf36a83 3764 #define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3765 #define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3766 #define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3767 #define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
mbed_official 113:b3775bf36a83 3768
mbed_official 113:b3775bf36a83 3769 #define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
mbed_official 113:b3775bf36a83 3770 #define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3771 #define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3772 #define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
mbed_official 113:b3775bf36a83 3773 #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3774 #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3775
mbed_official 113:b3775bf36a83 3776 #define TIM3_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
mbed_official 113:b3775bf36a83 3777 #define TIM3_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3778 #define TIM3_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3779 #define TIM3_OR_TI1_RMP ((uint32_t)0x00000004U) /*!<TI1_RMP[2] bit */
mbed_official 113:b3775bf36a83 3780 #define TIM3_OR_TI2_RMP ((uint32_t)0x00000008U) /*!<TI2_RMP[3] bit */
mbed_official 113:b3775bf36a83 3781 #define TIM3_OR_TI4_RMP ((uint32_t)0x00000010U) /*!<TI4_RMP[4] bit */
bogdanm 0:9b334a45a8ff 3782
bogdanm 0:9b334a45a8ff 3783
bogdanm 0:9b334a45a8ff 3784 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3785 /* */
bogdanm 0:9b334a45a8ff 3786 /* Touch Sensing Controller (TSC) */
bogdanm 0:9b334a45a8ff 3787 /* */
bogdanm 0:9b334a45a8ff 3788 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3789 /******************* Bit definition for TSC_CR register *********************/
mbed_official 113:b3775bf36a83 3790 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
mbed_official 113:b3775bf36a83 3791 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
mbed_official 113:b3775bf36a83 3792 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
mbed_official 113:b3775bf36a83 3793 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
mbed_official 113:b3775bf36a83 3794 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
mbed_official 113:b3775bf36a83 3795
mbed_official 113:b3775bf36a83 3796 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 113:b3775bf36a83 3797 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3798 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3799 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3800
mbed_official 113:b3775bf36a83 3801 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 113:b3775bf36a83 3802 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3803 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3804 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3805
mbed_official 113:b3775bf36a83 3806 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
mbed_official 113:b3775bf36a83 3807 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
mbed_official 113:b3775bf36a83 3808
mbed_official 113:b3775bf36a83 3809 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 113:b3775bf36a83 3810 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3811 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3812 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3813 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3814 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
mbed_official 113:b3775bf36a83 3815 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
mbed_official 113:b3775bf36a83 3816 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
mbed_official 113:b3775bf36a83 3817
mbed_official 113:b3775bf36a83 3818 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 113:b3775bf36a83 3819 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3820 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3821 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3822 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
mbed_official 113:b3775bf36a83 3823
mbed_official 113:b3775bf36a83 3824 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 113:b3775bf36a83 3825 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
mbed_official 113:b3775bf36a83 3826 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
mbed_official 113:b3775bf36a83 3827 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
mbed_official 113:b3775bf36a83 3828 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3829
bogdanm 0:9b334a45a8ff 3830 /******************* Bit definition for TSC_IER register ********************/
mbed_official 113:b3775bf36a83 3831 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
mbed_official 113:b3775bf36a83 3832 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
bogdanm 0:9b334a45a8ff 3833
bogdanm 0:9b334a45a8ff 3834 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 113:b3775bf36a83 3835 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
mbed_official 113:b3775bf36a83 3836 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
bogdanm 0:9b334a45a8ff 3837
bogdanm 0:9b334a45a8ff 3838 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 113:b3775bf36a83 3839 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
mbed_official 113:b3775bf36a83 3840 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
bogdanm 0:9b334a45a8ff 3841
bogdanm 0:9b334a45a8ff 3842 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 113:b3775bf36a83 3843 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3844 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3845 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3846 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3847 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3848 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3849 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3850 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3851 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3852 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3853 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3854 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3855 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3856 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3857 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3858 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3859 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3860 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3861 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3862 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3863 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3864 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3865 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3866 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3867 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3868 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3869 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3870 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3871 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3872 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3873 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 113:b3775bf36a83 3874 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 3875
bogdanm 0:9b334a45a8ff 3876 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 113:b3775bf36a83 3877 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3878 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3879 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3880 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3881 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3882 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3883 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3884 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3885 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3886 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3887 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3888 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3889 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3890 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3891 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3892 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3893 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3894 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3895 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3896 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3897 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3898 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3899 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3900 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3901 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3902 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3903 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3904 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
mbed_official 113:b3775bf36a83 3905 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
mbed_official 113:b3775bf36a83 3906 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
mbed_official 113:b3775bf36a83 3907 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
mbed_official 113:b3775bf36a83 3908 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 3909
bogdanm 0:9b334a45a8ff 3910 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 113:b3775bf36a83 3911 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3912 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3913 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3914 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3915 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3916 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3917 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3918 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3919 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3920 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3921 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3922 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3923 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3924 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3925 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3926 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3927 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3928 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3929 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3930 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3931 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3932 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3933 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3934 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3935 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3936 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3937 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3938 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
mbed_official 113:b3775bf36a83 3939 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
mbed_official 113:b3775bf36a83 3940 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
mbed_official 113:b3775bf36a83 3941 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
mbed_official 113:b3775bf36a83 3942 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 3943
bogdanm 0:9b334a45a8ff 3944 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 113:b3775bf36a83 3945 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
mbed_official 113:b3775bf36a83 3946 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
mbed_official 113:b3775bf36a83 3947 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
mbed_official 113:b3775bf36a83 3948 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
mbed_official 113:b3775bf36a83 3949 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
mbed_official 113:b3775bf36a83 3950 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
mbed_official 113:b3775bf36a83 3951 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
mbed_official 113:b3775bf36a83 3952 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
mbed_official 113:b3775bf36a83 3953 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
mbed_official 113:b3775bf36a83 3954 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
mbed_official 113:b3775bf36a83 3955 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
mbed_official 113:b3775bf36a83 3956 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
mbed_official 113:b3775bf36a83 3957 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
mbed_official 113:b3775bf36a83 3958 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
mbed_official 113:b3775bf36a83 3959 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
mbed_official 113:b3775bf36a83 3960 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
mbed_official 113:b3775bf36a83 3961 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
mbed_official 113:b3775bf36a83 3962 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
mbed_official 113:b3775bf36a83 3963 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
mbed_official 113:b3775bf36a83 3964 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
mbed_official 113:b3775bf36a83 3965 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
mbed_official 113:b3775bf36a83 3966 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
mbed_official 113:b3775bf36a83 3967 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
mbed_official 113:b3775bf36a83 3968 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
mbed_official 113:b3775bf36a83 3969 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
mbed_official 113:b3775bf36a83 3970 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
mbed_official 113:b3775bf36a83 3971 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
mbed_official 113:b3775bf36a83 3972 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
mbed_official 113:b3775bf36a83 3973 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
mbed_official 113:b3775bf36a83 3974 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
mbed_official 113:b3775bf36a83 3975 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
mbed_official 113:b3775bf36a83 3976 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
bogdanm 0:9b334a45a8ff 3977
bogdanm 0:9b334a45a8ff 3978 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 113:b3775bf36a83 3979 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
mbed_official 113:b3775bf36a83 3980 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
mbed_official 113:b3775bf36a83 3981 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
mbed_official 113:b3775bf36a83 3982 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
mbed_official 113:b3775bf36a83 3983 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
mbed_official 113:b3775bf36a83 3984 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
mbed_official 113:b3775bf36a83 3985 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
mbed_official 113:b3775bf36a83 3986 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
mbed_official 113:b3775bf36a83 3987 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
mbed_official 113:b3775bf36a83 3988 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
mbed_official 113:b3775bf36a83 3989 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
mbed_official 113:b3775bf36a83 3990 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
mbed_official 113:b3775bf36a83 3991 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
mbed_official 113:b3775bf36a83 3992 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
mbed_official 113:b3775bf36a83 3993 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
mbed_official 113:b3775bf36a83 3994 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
bogdanm 0:9b334a45a8ff 3995
bogdanm 0:9b334a45a8ff 3996 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 113:b3775bf36a83 3997 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
bogdanm 0:9b334a45a8ff 3998
bogdanm 0:9b334a45a8ff 3999 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4000 /* */
bogdanm 0:9b334a45a8ff 4001 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 0:9b334a45a8ff 4002 /* */
bogdanm 0:9b334a45a8ff 4003 /******************************************************************************/
mbed_official 113:b3775bf36a83 4004
mbed_official 113:b3775bf36a83 4005 /*
mbed_official 113:b3775bf36a83 4006 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official 113:b3775bf36a83 4007 */
mbed_official 113:b3775bf36a83 4008 /* Note: No specific macro feature on this device */
mbed_official 113:b3775bf36a83 4009
bogdanm 0:9b334a45a8ff 4010 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 113:b3775bf36a83 4011 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
mbed_official 113:b3775bf36a83 4012 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
mbed_official 113:b3775bf36a83 4013 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
mbed_official 113:b3775bf36a83 4014 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
mbed_official 113:b3775bf36a83 4015 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
mbed_official 113:b3775bf36a83 4016 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
mbed_official 113:b3775bf36a83 4017 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
mbed_official 113:b3775bf36a83 4018 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
mbed_official 113:b3775bf36a83 4019 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
mbed_official 113:b3775bf36a83 4020 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
mbed_official 113:b3775bf36a83 4021 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
mbed_official 113:b3775bf36a83 4022 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
mbed_official 113:b3775bf36a83 4023 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
mbed_official 113:b3775bf36a83 4024 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
mbed_official 113:b3775bf36a83 4025 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
mbed_official 113:b3775bf36a83 4026 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
mbed_official 113:b3775bf36a83 4027 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 113:b3775bf36a83 4028 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 113:b3775bf36a83 4029 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4030 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4031 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 4032 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 4033 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 4034 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 113:b3775bf36a83 4035 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4036 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4037 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 4038 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 4039 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 4040 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
mbed_official 113:b3775bf36a83 4041 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
mbed_official 113:b3775bf36a83 4042 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
bogdanm 0:9b334a45a8ff 4043 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 113:b3775bf36a83 4044 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
mbed_official 113:b3775bf36a83 4045 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
mbed_official 113:b3775bf36a83 4046 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
mbed_official 113:b3775bf36a83 4047 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
mbed_official 113:b3775bf36a83 4048 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
mbed_official 113:b3775bf36a83 4049 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
mbed_official 113:b3775bf36a83 4050 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
mbed_official 113:b3775bf36a83 4051 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 113:b3775bf36a83 4052 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4053 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4054 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
mbed_official 113:b3775bf36a83 4055 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
mbed_official 113:b3775bf36a83 4056 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
mbed_official 113:b3775bf36a83 4057 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
mbed_official 113:b3775bf36a83 4058 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
mbed_official 113:b3775bf36a83 4059 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
mbed_official 113:b3775bf36a83 4060 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
mbed_official 113:b3775bf36a83 4061 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 113:b3775bf36a83 4062 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4063 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4064 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
mbed_official 113:b3775bf36a83 4065 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
bogdanm 0:9b334a45a8ff 4066
bogdanm 0:9b334a45a8ff 4067 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 113:b3775bf36a83 4068 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
mbed_official 113:b3775bf36a83 4069 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
mbed_official 113:b3775bf36a83 4070 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
mbed_official 113:b3775bf36a83 4071 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
mbed_official 113:b3775bf36a83 4072 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
mbed_official 113:b3775bf36a83 4073 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
mbed_official 113:b3775bf36a83 4074 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
mbed_official 113:b3775bf36a83 4075 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
mbed_official 113:b3775bf36a83 4076 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
mbed_official 113:b3775bf36a83 4077 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
mbed_official 113:b3775bf36a83 4078 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
mbed_official 113:b3775bf36a83 4079 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
mbed_official 113:b3775bf36a83 4080 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
mbed_official 113:b3775bf36a83 4081 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
mbed_official 113:b3775bf36a83 4082 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
mbed_official 113:b3775bf36a83 4083 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
mbed_official 113:b3775bf36a83 4084 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 113:b3775bf36a83 4085 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4086 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4087 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 4088 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 113:b3775bf36a83 4089 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4090 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4091 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
mbed_official 113:b3775bf36a83 4092 #define USART_CR3_UCESM ((uint32_t)0x00800000U) /*!< Clock Enable in Stop mode */
bogdanm 0:9b334a45a8ff 4093
bogdanm 0:9b334a45a8ff 4094 /****************** Bit definition for USART_BRR register *******************/
mbed_official 113:b3775bf36a83 4095 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
mbed_official 113:b3775bf36a83 4096 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
bogdanm 0:9b334a45a8ff 4097
bogdanm 0:9b334a45a8ff 4098 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 113:b3775bf36a83 4099 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 113:b3775bf36a83 4100 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
bogdanm 0:9b334a45a8ff 4101
bogdanm 0:9b334a45a8ff 4102
bogdanm 0:9b334a45a8ff 4103 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 113:b3775bf36a83 4104 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
mbed_official 113:b3775bf36a83 4105 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
bogdanm 0:9b334a45a8ff 4106
bogdanm 0:9b334a45a8ff 4107 /******************* Bit definition for USART_RQR register ******************/
mbed_official 113:b3775bf36a83 4108 #define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /*!< Auto-Baud Rate Request */
mbed_official 113:b3775bf36a83 4109 #define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /*!< Send Break Request */
mbed_official 113:b3775bf36a83 4110 #define USART_RQR_MMRQ ((uint32_t)0x00000004U) /*!< Mute Mode Request */
mbed_official 113:b3775bf36a83 4111 #define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /*!< Receive Data flush Request */
mbed_official 113:b3775bf36a83 4112 #define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /*!< Transmit data flush Request */
bogdanm 0:9b334a45a8ff 4113
bogdanm 0:9b334a45a8ff 4114 /******************* Bit definition for USART_ISR register ******************/
mbed_official 113:b3775bf36a83 4115 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
mbed_official 113:b3775bf36a83 4116 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
mbed_official 113:b3775bf36a83 4117 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
mbed_official 113:b3775bf36a83 4118 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
mbed_official 113:b3775bf36a83 4119 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
mbed_official 113:b3775bf36a83 4120 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
mbed_official 113:b3775bf36a83 4121 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
mbed_official 113:b3775bf36a83 4122 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
mbed_official 113:b3775bf36a83 4123 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
mbed_official 113:b3775bf36a83 4124 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
mbed_official 113:b3775bf36a83 4125 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
mbed_official 113:b3775bf36a83 4126 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
mbed_official 113:b3775bf36a83 4127 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
mbed_official 113:b3775bf36a83 4128 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
mbed_official 113:b3775bf36a83 4129 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
mbed_official 113:b3775bf36a83 4130 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
mbed_official 113:b3775bf36a83 4131 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
mbed_official 113:b3775bf36a83 4132 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
mbed_official 113:b3775bf36a83 4133 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
mbed_official 113:b3775bf36a83 4134 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
mbed_official 113:b3775bf36a83 4135 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
mbed_official 113:b3775bf36a83 4136 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
bogdanm 0:9b334a45a8ff 4137
bogdanm 0:9b334a45a8ff 4138 /******************* Bit definition for USART_ICR register ******************/
mbed_official 113:b3775bf36a83 4139 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
mbed_official 113:b3775bf36a83 4140 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
mbed_official 113:b3775bf36a83 4141 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
mbed_official 113:b3775bf36a83 4142 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
mbed_official 113:b3775bf36a83 4143 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
mbed_official 113:b3775bf36a83 4144 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
mbed_official 113:b3775bf36a83 4145 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
mbed_official 113:b3775bf36a83 4146 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
mbed_official 113:b3775bf36a83 4147 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
mbed_official 113:b3775bf36a83 4148 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
mbed_official 113:b3775bf36a83 4149 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
mbed_official 113:b3775bf36a83 4150 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
bogdanm 0:9b334a45a8ff 4151
bogdanm 0:9b334a45a8ff 4152 /******************* Bit definition for USART_RDR register ******************/
mbed_official 113:b3775bf36a83 4153 #define USART_RDR_RDR ((uint32_t)0x000001FFU) /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 0:9b334a45a8ff 4154
bogdanm 0:9b334a45a8ff 4155 /******************* Bit definition for USART_TDR register ******************/
mbed_official 113:b3775bf36a83 4156 #define USART_TDR_TDR ((uint32_t)0x000001FFU) /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 0:9b334a45a8ff 4157
bogdanm 0:9b334a45a8ff 4158 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4159 /* */
bogdanm 0:9b334a45a8ff 4160 /* USB Device General registers */
bogdanm 0:9b334a45a8ff 4161 /* */
bogdanm 0:9b334a45a8ff 4162 /******************************************************************************/
mbed_official 113:b3775bf36a83 4163 #define USB_BASE ((uint32_t)0x40005C00U) /*!< USB_IP Peripheral Registers base address */
mbed_official 113:b3775bf36a83 4164 #define USB_PMAADDR ((uint32_t)0x40006000U) /*!< USB_IP Packet Memory Area base address */
bogdanm 0:9b334a45a8ff 4165
bogdanm 0:9b334a45a8ff 4166 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
bogdanm 0:9b334a45a8ff 4167 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
bogdanm 0:9b334a45a8ff 4168 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
bogdanm 0:9b334a45a8ff 4169 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
bogdanm 0:9b334a45a8ff 4170 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
bogdanm 0:9b334a45a8ff 4171 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
bogdanm 0:9b334a45a8ff 4172 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
bogdanm 0:9b334a45a8ff 4173
bogdanm 0:9b334a45a8ff 4174 /**************************** ISTR interrupt events *************************/
mbed_official 113:b3775bf36a83 4175 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
mbed_official 113:b3775bf36a83 4176 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
mbed_official 113:b3775bf36a83 4177 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
mbed_official 113:b3775bf36a83 4178 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
mbed_official 113:b3775bf36a83 4179 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
mbed_official 113:b3775bf36a83 4180 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
mbed_official 113:b3775bf36a83 4181 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
mbed_official 113:b3775bf36a83 4182 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
mbed_official 113:b3775bf36a83 4183 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
mbed_official 113:b3775bf36a83 4184 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
mbed_official 113:b3775bf36a83 4185 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
bogdanm 0:9b334a45a8ff 4186
bogdanm 0:9b334a45a8ff 4187 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
bogdanm 0:9b334a45a8ff 4188 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
bogdanm 0:9b334a45a8ff 4189 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
bogdanm 0:9b334a45a8ff 4190 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
bogdanm 0:9b334a45a8ff 4191 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
bogdanm 0:9b334a45a8ff 4192 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
bogdanm 0:9b334a45a8ff 4193 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
bogdanm 0:9b334a45a8ff 4194 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
bogdanm 0:9b334a45a8ff 4195 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
bogdanm 0:9b334a45a8ff 4196 /************************* CNTR control register bits definitions ***********/
mbed_official 113:b3775bf36a83 4197 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
mbed_official 113:b3775bf36a83 4198 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
mbed_official 113:b3775bf36a83 4199 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
mbed_official 113:b3775bf36a83 4200 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
mbed_official 113:b3775bf36a83 4201 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
mbed_official 113:b3775bf36a83 4202 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
mbed_official 113:b3775bf36a83 4203 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
mbed_official 113:b3775bf36a83 4204 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
mbed_official 113:b3775bf36a83 4205 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
mbed_official 113:b3775bf36a83 4206 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
mbed_official 113:b3775bf36a83 4207 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
mbed_official 113:b3775bf36a83 4208 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
mbed_official 113:b3775bf36a83 4209 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
mbed_official 113:b3775bf36a83 4210 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
mbed_official 113:b3775bf36a83 4211 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
bogdanm 0:9b334a45a8ff 4212 /************************* BCDR control register bits definitions ***********/
mbed_official 113:b3775bf36a83 4213 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
mbed_official 113:b3775bf36a83 4214 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
mbed_official 113:b3775bf36a83 4215 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
mbed_official 113:b3775bf36a83 4216 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
mbed_official 113:b3775bf36a83 4217 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
mbed_official 113:b3775bf36a83 4218 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
mbed_official 113:b3775bf36a83 4219 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
mbed_official 113:b3775bf36a83 4220 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
mbed_official 113:b3775bf36a83 4221 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
bogdanm 0:9b334a45a8ff 4222 /*************************** LPM register bits definitions ******************/
mbed_official 113:b3775bf36a83 4223 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
mbed_official 113:b3775bf36a83 4224 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 113:b3775bf36a83 4225 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
mbed_official 113:b3775bf36a83 4226 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
bogdanm 0:9b334a45a8ff 4227 /******************** FNR Frame Number Register bit definitions ************/
mbed_official 113:b3775bf36a83 4228 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
mbed_official 113:b3775bf36a83 4229 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
mbed_official 113:b3775bf36a83 4230 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
mbed_official 113:b3775bf36a83 4231 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
mbed_official 113:b3775bf36a83 4232 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
bogdanm 0:9b334a45a8ff 4233 /******************** DADDR Device ADDRess bit definitions ****************/
mbed_official 113:b3775bf36a83 4234 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
mbed_official 113:b3775bf36a83 4235 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
bogdanm 0:9b334a45a8ff 4236 /****************************** Endpoint register *************************/
bogdanm 0:9b334a45a8ff 4237 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
bogdanm 0:9b334a45a8ff 4238 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
bogdanm 0:9b334a45a8ff 4239 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
bogdanm 0:9b334a45a8ff 4240 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
bogdanm 0:9b334a45a8ff 4241 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
bogdanm 0:9b334a45a8ff 4242 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
bogdanm 0:9b334a45a8ff 4243 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
bogdanm 0:9b334a45a8ff 4244 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
bogdanm 0:9b334a45a8ff 4245 /* bit positions */
mbed_official 113:b3775bf36a83 4246 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
mbed_official 113:b3775bf36a83 4247 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
mbed_official 113:b3775bf36a83 4248 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
mbed_official 113:b3775bf36a83 4249 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
mbed_official 113:b3775bf36a83 4250 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
mbed_official 113:b3775bf36a83 4251 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
mbed_official 113:b3775bf36a83 4252 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
mbed_official 113:b3775bf36a83 4253 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
mbed_official 113:b3775bf36a83 4254 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
mbed_official 113:b3775bf36a83 4255 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
bogdanm 0:9b334a45a8ff 4256
bogdanm 0:9b334a45a8ff 4257 /* EndPoint REGister MASK (no toggle fields) */
bogdanm 0:9b334a45a8ff 4258 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
bogdanm 0:9b334a45a8ff 4259 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 113:b3775bf36a83 4260 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
mbed_official 113:b3775bf36a83 4261 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
mbed_official 113:b3775bf36a83 4262 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
mbed_official 113:b3775bf36a83 4263 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
mbed_official 113:b3775bf36a83 4264 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
mbed_official 113:b3775bf36a83 4265 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 4266
mbed_official 113:b3775bf36a83 4267 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
bogdanm 0:9b334a45a8ff 4268 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 113:b3775bf36a83 4269 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
mbed_official 113:b3775bf36a83 4270 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
mbed_official 113:b3775bf36a83 4271 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
mbed_official 113:b3775bf36a83 4272 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
mbed_official 113:b3775bf36a83 4273 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 113:b3775bf36a83 4274 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
bogdanm 0:9b334a45a8ff 4275 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 4276 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 113:b3775bf36a83 4277 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
mbed_official 113:b3775bf36a83 4278 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
mbed_official 113:b3775bf36a83 4279 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
mbed_official 113:b3775bf36a83 4280 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
mbed_official 113:b3775bf36a83 4281 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 113:b3775bf36a83 4282 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
bogdanm 0:9b334a45a8ff 4283 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 4284
bogdanm 0:9b334a45a8ff 4285 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4286 /* */
bogdanm 0:9b334a45a8ff 4287 /* Window WATCHDOG (WWDG) */
bogdanm 0:9b334a45a8ff 4288 /* */
bogdanm 0:9b334a45a8ff 4289 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4290
bogdanm 0:9b334a45a8ff 4291 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 113:b3775bf36a83 4292 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 113:b3775bf36a83 4293 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4294 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4295 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 4296 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 4297 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 4298 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
mbed_official 113:b3775bf36a83 4299 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
mbed_official 113:b3775bf36a83 4300
mbed_official 113:b3775bf36a83 4301 /* Legacy defines */
mbed_official 113:b3775bf36a83 4302 #define WWDG_CR_T0 WWDG_CR_T_0
mbed_official 113:b3775bf36a83 4303 #define WWDG_CR_T1 WWDG_CR_T_1
mbed_official 113:b3775bf36a83 4304 #define WWDG_CR_T2 WWDG_CR_T_2
mbed_official 113:b3775bf36a83 4305 #define WWDG_CR_T3 WWDG_CR_T_3
mbed_official 113:b3775bf36a83 4306 #define WWDG_CR_T4 WWDG_CR_T_4
mbed_official 113:b3775bf36a83 4307 #define WWDG_CR_T5 WWDG_CR_T_5
mbed_official 113:b3775bf36a83 4308 #define WWDG_CR_T6 WWDG_CR_T_6
mbed_official 113:b3775bf36a83 4309
mbed_official 113:b3775bf36a83 4310 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
bogdanm 0:9b334a45a8ff 4311
bogdanm 0:9b334a45a8ff 4312 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 113:b3775bf36a83 4313 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
mbed_official 113:b3775bf36a83 4314 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4315 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4316 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
mbed_official 113:b3775bf36a83 4317 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
mbed_official 113:b3775bf36a83 4318 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
mbed_official 113:b3775bf36a83 4319 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
mbed_official 113:b3775bf36a83 4320 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
mbed_official 113:b3775bf36a83 4321
mbed_official 113:b3775bf36a83 4322 /* Legacy defines */
mbed_official 113:b3775bf36a83 4323 #define WWDG_CFR_W0 WWDG_CFR_W_0
mbed_official 113:b3775bf36a83 4324 #define WWDG_CFR_W1 WWDG_CFR_W_1
mbed_official 113:b3775bf36a83 4325 #define WWDG_CFR_W2 WWDG_CFR_W_2
mbed_official 113:b3775bf36a83 4326 #define WWDG_CFR_W3 WWDG_CFR_W_3
mbed_official 113:b3775bf36a83 4327 #define WWDG_CFR_W4 WWDG_CFR_W_4
mbed_official 113:b3775bf36a83 4328 #define WWDG_CFR_W5 WWDG_CFR_W_5
mbed_official 113:b3775bf36a83 4329 #define WWDG_CFR_W6 WWDG_CFR_W_6
mbed_official 113:b3775bf36a83 4330
mbed_official 113:b3775bf36a83 4331 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
mbed_official 113:b3775bf36a83 4332 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
mbed_official 113:b3775bf36a83 4333 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
mbed_official 113:b3775bf36a83 4334
mbed_official 113:b3775bf36a83 4335 /* Legacy defines */
mbed_official 113:b3775bf36a83 4336 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
mbed_official 113:b3775bf36a83 4337 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
mbed_official 113:b3775bf36a83 4338
mbed_official 113:b3775bf36a83 4339 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 4340
bogdanm 0:9b334a45a8ff 4341 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 113:b3775bf36a83 4342 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
bogdanm 0:9b334a45a8ff 4343
bogdanm 0:9b334a45a8ff 4344 /**
bogdanm 0:9b334a45a8ff 4345 * @}
bogdanm 0:9b334a45a8ff 4346 */
bogdanm 0:9b334a45a8ff 4347
bogdanm 0:9b334a45a8ff 4348 /**
bogdanm 0:9b334a45a8ff 4349 * @}
bogdanm 0:9b334a45a8ff 4350 */
bogdanm 0:9b334a45a8ff 4351
bogdanm 0:9b334a45a8ff 4352 /** @addtogroup Exported_macros
bogdanm 0:9b334a45a8ff 4353 * @{
bogdanm 0:9b334a45a8ff 4354 */
bogdanm 0:9b334a45a8ff 4355
bogdanm 0:9b334a45a8ff 4356 /******************************* ADC Instances ********************************/
bogdanm 0:9b334a45a8ff 4357 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm 0:9b334a45a8ff 4358
bogdanm 0:9b334a45a8ff 4359 /******************************* COMP Instances *******************************/
bogdanm 0:9b334a45a8ff 4360 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
bogdanm 0:9b334a45a8ff 4361 ((INSTANCE) == COMP2))
bogdanm 0:9b334a45a8ff 4362
mbed_official 113:b3775bf36a83 4363 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
mbed_official 113:b3775bf36a83 4364
bogdanm 0:9b334a45a8ff 4365 /******************************* CRC Instances ********************************/
bogdanm 0:9b334a45a8ff 4366 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 0:9b334a45a8ff 4367
bogdanm 0:9b334a45a8ff 4368 /******************************* DAC Instances *********************************/
bogdanm 0:9b334a45a8ff 4369 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 0:9b334a45a8ff 4370
bogdanm 0:9b334a45a8ff 4371 /******************************* DMA Instances *********************************/
bogdanm 0:9b334a45a8ff 4372 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 0:9b334a45a8ff 4373 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 0:9b334a45a8ff 4374 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 0:9b334a45a8ff 4375 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 0:9b334a45a8ff 4376 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 0:9b334a45a8ff 4377 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 0:9b334a45a8ff 4378 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 0:9b334a45a8ff 4379 ((INSTANCE) == DMA1_Stream7))
bogdanm 0:9b334a45a8ff 4380
bogdanm 0:9b334a45a8ff 4381 /******************************* GPIO Instances *******************************/
bogdanm 0:9b334a45a8ff 4382 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 0:9b334a45a8ff 4383 ((INSTANCE) == GPIOB) || \
bogdanm 0:9b334a45a8ff 4384 ((INSTANCE) == GPIOC) || \
bogdanm 0:9b334a45a8ff 4385 ((INSTANCE) == GPIOD) || \
bogdanm 0:9b334a45a8ff 4386 ((INSTANCE) == GPIOE) || \
bogdanm 0:9b334a45a8ff 4387 ((INSTANCE) == GPIOH))
bogdanm 0:9b334a45a8ff 4388
mbed_official 113:b3775bf36a83 4389 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 113:b3775bf36a83 4390 ((INSTANCE) == GPIOB) || \
mbed_official 113:b3775bf36a83 4391 ((INSTANCE) == GPIOC) || \
mbed_official 113:b3775bf36a83 4392 ((INSTANCE) == GPIOD) || \
mbed_official 113:b3775bf36a83 4393 ((INSTANCE) == GPIOE) || \
mbed_official 113:b3775bf36a83 4394 ((INSTANCE) == GPIOH))
mbed_official 113:b3775bf36a83 4395
bogdanm 0:9b334a45a8ff 4396 /******************************** I2C Instances *******************************/
bogdanm 0:9b334a45a8ff 4397 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 0:9b334a45a8ff 4398 ((INSTANCE) == I2C2) || \
bogdanm 0:9b334a45a8ff 4399 ((INSTANCE) == I2C3))
bogdanm 0:9b334a45a8ff 4400
bogdanm 0:9b334a45a8ff 4401 /******************************** I2S Instances *******************************/
bogdanm 0:9b334a45a8ff 4402 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
bogdanm 0:9b334a45a8ff 4403
bogdanm 0:9b334a45a8ff 4404 /******************************* RNG Instances ********************************/
bogdanm 0:9b334a45a8ff 4405 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm 0:9b334a45a8ff 4406
bogdanm 0:9b334a45a8ff 4407 /****************************** RTC Instances *********************************/
bogdanm 0:9b334a45a8ff 4408 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 0:9b334a45a8ff 4409
bogdanm 0:9b334a45a8ff 4410 /******************************** SMBUS Instances *****************************/
bogdanm 0:9b334a45a8ff 4411 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 0:9b334a45a8ff 4412 ((INSTANCE) == I2C3))
bogdanm 0:9b334a45a8ff 4413
bogdanm 0:9b334a45a8ff 4414 /******************************** SPI Instances *******************************/
bogdanm 0:9b334a45a8ff 4415 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 0:9b334a45a8ff 4416 ((INSTANCE) == SPI2))
bogdanm 0:9b334a45a8ff 4417
bogdanm 0:9b334a45a8ff 4418 /****************** LPTIM Instances : All supported instances *****************/
bogdanm 0:9b334a45a8ff 4419 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
bogdanm 0:9b334a45a8ff 4420
bogdanm 0:9b334a45a8ff 4421 /****************** TIM Instances : All supported instances *******************/
bogdanm 0:9b334a45a8ff 4422 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4423 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4424 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 4425 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 4426 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4427 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4428
mbed_official 113:b3775bf36a83 4429 /****************** TIM Instances : supporting counting mode selection ********/
mbed_official 113:b3775bf36a83 4430 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4431 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4432 ((INSTANCE) == TIM21) || \
mbed_official 113:b3775bf36a83 4433 ((INSTANCE) == TIM22))
mbed_official 113:b3775bf36a83 4434
mbed_official 113:b3775bf36a83 4435 /****************** TIM Instances : supporting clock division *****************/
mbed_official 113:b3775bf36a83 4436 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4437 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4438 ((INSTANCE) == TIM21) || \
mbed_official 113:b3775bf36a83 4439 ((INSTANCE) == TIM22))
mbed_official 113:b3775bf36a83 4440
mbed_official 113:b3775bf36a83 4441 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
mbed_official 113:b3775bf36a83 4442 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4443 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4444 ((INSTANCE) == TIM21))
mbed_official 113:b3775bf36a83 4445
mbed_official 113:b3775bf36a83 4446 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
mbed_official 113:b3775bf36a83 4447 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4448 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4449 ((INSTANCE) == TIM21) || \
mbed_official 113:b3775bf36a83 4450 ((INSTANCE) == TIM22))
mbed_official 113:b3775bf36a83 4451
mbed_official 113:b3775bf36a83 4452 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 113:b3775bf36a83 4453 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4454 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4455 ((INSTANCE) == TIM21))
mbed_official 113:b3775bf36a83 4456
mbed_official 113:b3775bf36a83 4457 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 113:b3775bf36a83 4458 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4459 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4460 ((INSTANCE) == TIM21) || \
mbed_official 113:b3775bf36a83 4461 ((INSTANCE) == TIM22))
mbed_official 113:b3775bf36a83 4462
bogdanm 0:9b334a45a8ff 4463 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 0:9b334a45a8ff 4464 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4465 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4466 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4467 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4468
bogdanm 0:9b334a45a8ff 4469 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 0:9b334a45a8ff 4470 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4471 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4472 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4473 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4474
bogdanm 0:9b334a45a8ff 4475 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 0:9b334a45a8ff 4476 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4477 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4478
bogdanm 0:9b334a45a8ff 4479 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 0:9b334a45a8ff 4480 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4481 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4482
bogdanm 0:9b334a45a8ff 4483 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 0:9b334a45a8ff 4484
bogdanm 0:9b334a45a8ff 4485 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 0:9b334a45a8ff 4486 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4487 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4488
bogdanm 0:9b334a45a8ff 4489 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 0:9b334a45a8ff 4490 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4491 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4492 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 4493 ((INSTANCE) == TIM7))
bogdanm 0:9b334a45a8ff 4494
bogdanm 0:9b334a45a8ff 4495 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 0:9b334a45a8ff 4496 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4497 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4498
bogdanm 0:9b334a45a8ff 4499 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 0:9b334a45a8ff 4500 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4501 (INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4502
bogdanm 0:9b334a45a8ff 4503 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 0:9b334a45a8ff 4504 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4505 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 4506
bogdanm 0:9b334a45a8ff 4507 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 0:9b334a45a8ff 4508 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4509 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4510 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 4511 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 4512 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4513 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4514
bogdanm 0:9b334a45a8ff 4515 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 0:9b334a45a8ff 4516 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4517 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4518 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4519 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4520
bogdanm 0:9b334a45a8ff 4521 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 0:9b334a45a8ff 4522
bogdanm 0:9b334a45a8ff 4523 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 0:9b334a45a8ff 4524 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4525 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4526 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4527 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4528
bogdanm 0:9b334a45a8ff 4529 /****************** TIM Instances : remapping capability **********************/
bogdanm 0:9b334a45a8ff 4530 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4531 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 4532 ((INSTANCE) == TIM21) || \
bogdanm 0:9b334a45a8ff 4533 ((INSTANCE) == TIM22))
bogdanm 0:9b334a45a8ff 4534
mbed_official 113:b3775bf36a83 4535 /****************** TIM Instances : supporting encoder interface **************/
mbed_official 113:b3775bf36a83 4536 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4537 ((INSTANCE) == TIM3) || \
mbed_official 113:b3775bf36a83 4538 ((INSTANCE) == TIM21) || \
mbed_official 113:b3775bf36a83 4539 ((INSTANCE) == TIM22))
mbed_official 113:b3775bf36a83 4540
mbed_official 113:b3775bf36a83 4541 /******************* TIM Instances : output(s) OCXEC register *****************/
mbed_official 113:b3775bf36a83 4542 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 113:b3775bf36a83 4543 ((INSTANCE) == TIM3))
mbed_official 113:b3775bf36a83 4544
bogdanm 0:9b334a45a8ff 4545 /******************* TIM Instances : output(s) available **********************/
bogdanm 0:9b334a45a8ff 4546 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 4547 (((((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 4548 ((INSTANCE) == TIM3)) \
bogdanm 0:9b334a45a8ff 4549 && \
bogdanm 0:9b334a45a8ff 4550 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 4551 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 4552 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 4553 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 4554 || \
bogdanm 0:9b334a45a8ff 4555 (((INSTANCE) == TIM21) && \
bogdanm 0:9b334a45a8ff 4556 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 4557 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 0:9b334a45a8ff 4558 || \
bogdanm 0:9b334a45a8ff 4559 (((INSTANCE) == TIM22) && \
bogdanm 0:9b334a45a8ff 4560 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 4561 ((CHANNEL) == TIM_CHANNEL_2))))
bogdanm 0:9b334a45a8ff 4562
bogdanm 0:9b334a45a8ff 4563 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 0:9b334a45a8ff 4564 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4565 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 4566 ((INSTANCE) == USART4) || \
bogdanm 0:9b334a45a8ff 4567 ((INSTANCE) == USART5) || \
bogdanm 0:9b334a45a8ff 4568 ((INSTANCE) == LPUART1))
bogdanm 0:9b334a45a8ff 4569
bogdanm 0:9b334a45a8ff 4570 /******************** USART Instances : Synchronous mode **********************/
bogdanm 0:9b334a45a8ff 4571 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4572 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 4573 ((INSTANCE) == USART4) || \
bogdanm 0:9b334a45a8ff 4574 ((INSTANCE) == USART5))
bogdanm 0:9b334a45a8ff 4575
bogdanm 0:9b334a45a8ff 4576 /****************** USART Instances : Auto Baud Rate detection ****************/
bogdanm 0:9b334a45a8ff 4577
bogdanm 0:9b334a45a8ff 4578 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4579 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 4580
bogdanm 0:9b334a45a8ff 4581 /******************** UART Instances : Half-Duplex mode **********************/
bogdanm 0:9b334a45a8ff 4582 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4583 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 4584 ((INSTANCE) == USART4) || \
bogdanm 0:9b334a45a8ff 4585 ((INSTANCE) == USART5) || \
bogdanm 0:9b334a45a8ff 4586 ((INSTANCE) == LPUART1))
bogdanm 0:9b334a45a8ff 4587
bogdanm 0:9b334a45a8ff 4588 /******************** UART Instances : LIN mode **********************/
bogdanm 0:9b334a45a8ff 4589 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4590 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 4591
bogdanm 0:9b334a45a8ff 4592 /******************** UART Instances : Wake-up from Stop mode **********************/
bogdanm 0:9b334a45a8ff 4593 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4594 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 4595 ((INSTANCE) == LPUART1))
bogdanm 0:9b334a45a8ff 4596 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 0:9b334a45a8ff 4597 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4598 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 4599 ((INSTANCE) == USART4) || \
bogdanm 0:9b334a45a8ff 4600 ((INSTANCE) == USART5) || \
bogdanm 0:9b334a45a8ff 4601 ((INSTANCE) == LPUART1))
bogdanm 0:9b334a45a8ff 4602
bogdanm 0:9b334a45a8ff 4603 /********************* UART Instances : Smard card mode ***********************/
bogdanm 0:9b334a45a8ff 4604 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4605 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 4606
bogdanm 0:9b334a45a8ff 4607 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 0:9b334a45a8ff 4608 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 4609 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 4610
bogdanm 0:9b334a45a8ff 4611 /****************************** IWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 4612 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 0:9b334a45a8ff 4613
bogdanm 0:9b334a45a8ff 4614 /****************************** USB Instances ********************************/
bogdanm 0:9b334a45a8ff 4615 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
bogdanm 0:9b334a45a8ff 4616
bogdanm 0:9b334a45a8ff 4617 /****************************** WWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 4618 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 0:9b334a45a8ff 4619
bogdanm 0:9b334a45a8ff 4620 /****************************** LCD Instances ********************************/
bogdanm 0:9b334a45a8ff 4621 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
bogdanm 0:9b334a45a8ff 4622
bogdanm 0:9b334a45a8ff 4623 /**
bogdanm 0:9b334a45a8ff 4624 * @}
bogdanm 0:9b334a45a8ff 4625 */
bogdanm 0:9b334a45a8ff 4626
bogdanm 0:9b334a45a8ff 4627 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4628 /* For a painless codes migration between the STM32L0xx device product */
bogdanm 0:9b334a45a8ff 4629 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 0:9b334a45a8ff 4630 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 0:9b334a45a8ff 4631 /* No need to update developed interrupt code when moving across */
bogdanm 0:9b334a45a8ff 4632 /* product lines within the same STM32L0 Family */
bogdanm 0:9b334a45a8ff 4633 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4634
bogdanm 0:9b334a45a8ff 4635 /* Aliases for __IRQn */
bogdanm 0:9b334a45a8ff 4636
bogdanm 0:9b334a45a8ff 4637 #define LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 0:9b334a45a8ff 4638 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 0:9b334a45a8ff 4639 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 0:9b334a45a8ff 4640 #define TIM6_IRQn TIM6_DAC_IRQn
bogdanm 0:9b334a45a8ff 4641 #define RCC_IRQn RCC_CRS_IRQn
bogdanm 0:9b334a45a8ff 4642
bogdanm 0:9b334a45a8ff 4643 /* Aliases for __IRQHandler */
bogdanm 0:9b334a45a8ff 4644 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 0:9b334a45a8ff 4645 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 0:9b334a45a8ff 4646 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 0:9b334a45a8ff 4647 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
bogdanm 0:9b334a45a8ff 4648 #define RCC_IRQHandler RCC_CRS_IRQHandler
bogdanm 0:9b334a45a8ff 4649
bogdanm 0:9b334a45a8ff 4650 /**
bogdanm 0:9b334a45a8ff 4651 * @}
bogdanm 0:9b334a45a8ff 4652 */
bogdanm 0:9b334a45a8ff 4653
bogdanm 0:9b334a45a8ff 4654 /**
bogdanm 0:9b334a45a8ff 4655 * @}
bogdanm 0:9b334a45a8ff 4656 */
bogdanm 0:9b334a45a8ff 4657
bogdanm 0:9b334a45a8ff 4658 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 4659 }
bogdanm 0:9b334a45a8ff 4660 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 4661
bogdanm 0:9b334a45a8ff 4662 #endif /* __STM32L073xx_H */
bogdanm 0:9b334a45a8ff 4663
bogdanm 0:9b334a45a8ff 4664
bogdanm 0:9b334a45a8ff 4665
bogdanm 0:9b334a45a8ff 4666 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/