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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_ll_fmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief FMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FMC peripheral features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
<> 144:ef7eb2e8f9f7 20 (+) The NOR/PSRAM memory controller
<> 144:ef7eb2e8f9f7 21 (+) The NAND memory controller
<> 144:ef7eb2e8f9f7 22 (+) The Synchronous DRAM (SDRAM) controller
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
<> 144:ef7eb2e8f9f7 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
<> 144:ef7eb2e8f9f7 26 (+) to translate AHB transactions into the appropriate external device protocol
<> 144:ef7eb2e8f9f7 27 (+) to meet the access time requirements of the external memory devices
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 [..] All external memories share the addresses, data and control signals with the controller.
<> 144:ef7eb2e8f9f7 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
<> 144:ef7eb2e8f9f7 31 only one access at a time to an external device.
<> 144:ef7eb2e8f9f7 32 The main features of the FMC controller are the following:
<> 144:ef7eb2e8f9f7 33 (+) Interface with static-memory mapped devices including:
<> 144:ef7eb2e8f9f7 34 (++) Static random access memory (SRAM)
<> 144:ef7eb2e8f9f7 35 (++) Read-only memory (ROM)
<> 144:ef7eb2e8f9f7 36 (++) NOR Flash memory/OneNAND Flash memory
<> 144:ef7eb2e8f9f7 37 (++) PSRAM (4 memory banks)
<> 144:ef7eb2e8f9f7 38 (++) 16-bit PC Card compatible devices
<> 144:ef7eb2e8f9f7 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
<> 144:ef7eb2e8f9f7 40 data
<> 144:ef7eb2e8f9f7 41 (+) Interface with synchronous DRAM (SDRAM) memories
<> 144:ef7eb2e8f9f7 42 (+) Independent Chip Select control for each memory bank
<> 144:ef7eb2e8f9f7 43 (+) Independent configuration for each memory bank
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 @endverbatim
<> 144:ef7eb2e8f9f7 46 ******************************************************************************
<> 144:ef7eb2e8f9f7 47 * @attention
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 50 *
<> 144:ef7eb2e8f9f7 51 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 52 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 53 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 56 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 57 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 59 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 60 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 ******************************************************************************
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 80 * @{
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @defgroup FMC_LL FMC Low Layer
<> 144:ef7eb2e8f9f7 84 * @brief FMC driver modules
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 91 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 92 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
<> 144:ef7eb2e8f9f7 102 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 @verbatim
<> 144:ef7eb2e8f9f7 105 ==============================================================================
<> 144:ef7eb2e8f9f7 106 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 107 ==============================================================================
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 [..]
<> 144:ef7eb2e8f9f7 110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 111 to run the NORSRAM external devices.
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 116 (+) FMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 117 FMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 118 (+) FMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 @endverbatim
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 135 (+) Initialize and configure the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 136 (+) De-initialize the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 137 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 @endverbatim
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @brief Initialize the FMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 145 * control parameters in the FMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 146 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 147 * @param Init: Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 148 * @retval HAL status
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Check the parameters */
<> 144:ef7eb2e8f9f7 155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 163 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 164 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 165 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 166 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 167 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 173 tmpr = Device->BTCR[Init->NSBank];
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
<> 144:ef7eb2e8f9f7 176 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
<> 144:ef7eb2e8f9f7 177 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
<> 144:ef7eb2e8f9f7 178 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
<> 144:ef7eb2e8f9f7 179 FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \
<> 144:ef7eb2e8f9f7 180 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
<> 144:ef7eb2e8f9f7 181 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 184 tmpr |= (uint32_t)(Init->DataAddressMux |\
<> 144:ef7eb2e8f9f7 185 Init->MemoryType |\
<> 144:ef7eb2e8f9f7 186 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 187 Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 188 Init->WaitSignalPolarity |\
<> 144:ef7eb2e8f9f7 189 Init->WaitSignalActive |\
<> 144:ef7eb2e8f9f7 190 Init->WriteOperation |\
<> 144:ef7eb2e8f9f7 191 Init->WaitSignal |\
<> 144:ef7eb2e8f9f7 192 Init->ExtendedMode |\
<> 144:ef7eb2e8f9f7 193 Init->AsynchronousWait |\
<> 144:ef7eb2e8f9f7 194 Init->WriteBurst |\
<> 144:ef7eb2e8f9f7 195 Init->ContinuousClock |\
<> 144:ef7eb2e8f9f7 196 Init->PageSize |\
<> 144:ef7eb2e8f9f7 197 Init->WriteFifo);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 Device->BTCR[Init->NSBank] = tmpr;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
<> 144:ef7eb2e8f9f7 207 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 if(Init->NSBank != FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 return HAL_OK;
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @brief DeInitialize the FMC_NORSRAM peripheral
<> 144:ef7eb2e8f9f7 222 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 223 * @param ExDevice: Pointer to NORSRAM extended mode device instance
<> 144:ef7eb2e8f9f7 224 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 225 * @retval HAL status
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Check the parameters */
<> 144:ef7eb2e8f9f7 230 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Disable the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 235 __FMC_NORSRAM_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* De-initialize the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 238 /* FMC_NORSRAM_BANK1 */
<> 144:ef7eb2e8f9f7 239 if(Bank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 Device->BTCR[Bank] = 0x000030DB;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 244 else
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 Device->BTCR[Bank] = 0x000030D2;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 250 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 return HAL_OK;
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief Initialize the FMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 258 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 259 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 260 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 261 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 262 * @retval HAL status
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Check the parameters */
<> 144:ef7eb2e8f9f7 269 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 270 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 271 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 272 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 273 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 274 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 275 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 276 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 277 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 280 tmpr = Device->BTCR[Bank + 1];
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
<> 144:ef7eb2e8f9f7 283 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
<> 144:ef7eb2e8f9f7 284 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
<> 144:ef7eb2e8f9f7 285 FMC_BTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Set FMC_NORSRAM device timing parameters */
<> 144:ef7eb2e8f9f7 288 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 289 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 290 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 291 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 292 (((Timing->CLKDivision)-1) << 20) |\
<> 144:ef7eb2e8f9f7 293 (((Timing->DataLatency)-2) << 24) |\
<> 144:ef7eb2e8f9f7 294 (Timing->AccessMode)
<> 144:ef7eb2e8f9f7 295 );
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 Device->BTCR[Bank + 1] = tmpr;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
<> 144:ef7eb2e8f9f7 300 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
<> 144:ef7eb2e8f9f7 303 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
<> 144:ef7eb2e8f9f7 304 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 return HAL_OK;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 312 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 313 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 314 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 315 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 316 * @retval HAL status
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Check the parameters */
<> 144:ef7eb2e8f9f7 323 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 144:ef7eb2e8f9f7 326 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check the parameters */
<> 144:ef7eb2e8f9f7 329 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 144:ef7eb2e8f9f7 330 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 331 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 332 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 333 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 334 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 335 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 336 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 337 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Get the BWTR register value */
<> 144:ef7eb2e8f9f7 340 tmpr = Device->BWTR[Bank];
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
<> 144:ef7eb2e8f9f7 343 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
<> 144:ef7eb2e8f9f7 344 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 347 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 348 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 349 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 350 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 Device->BWTR[Bank] = tmpr;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 else
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 Device->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 return HAL_OK;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
<> 144:ef7eb2e8f9f7 366 * @brief management functions
<> 144:ef7eb2e8f9f7 367 *
<> 144:ef7eb2e8f9f7 368 @verbatim
<> 144:ef7eb2e8f9f7 369 ==============================================================================
<> 144:ef7eb2e8f9f7 370 ##### FMC_NORSRAM Control functions #####
<> 144:ef7eb2e8f9f7 371 ==============================================================================
<> 144:ef7eb2e8f9f7 372 [..]
<> 144:ef7eb2e8f9f7 373 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 374 the FMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 @endverbatim
<> 144:ef7eb2e8f9f7 377 * @{
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief Enables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 382 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 383 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 384 * @retval HAL status
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Check the parameters */
<> 144:ef7eb2e8f9f7 389 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 390 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Enable write operation */
<> 144:ef7eb2e8f9f7 393 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 return HAL_OK;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /**
<> 144:ef7eb2e8f9f7 399 * @brief Disables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 400 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 401 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 402 * @retval HAL status
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 /* Check the parameters */
<> 144:ef7eb2e8f9f7 407 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 408 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Disable write operation */
<> 144:ef7eb2e8f9f7 411 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 return HAL_OK;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @}
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
<> 144:ef7eb2e8f9f7 425 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 426 *
<> 144:ef7eb2e8f9f7 427 @verbatim
<> 144:ef7eb2e8f9f7 428 ==============================================================================
<> 144:ef7eb2e8f9f7 429 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 430 ==============================================================================
<> 144:ef7eb2e8f9f7 431 [..]
<> 144:ef7eb2e8f9f7 432 This driver contains a set of APIs to interface with the FMC NAND banks in order
<> 144:ef7eb2e8f9f7 433 to run the NAND external devices.
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 436 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
<> 144:ef7eb2e8f9f7 437 (+) FMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 438 FMC_NAND_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 439 (+) FMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 440 FMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 441 (+) FMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 442 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
<> 144:ef7eb2e8f9f7 443 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 @endverbatim
<> 144:ef7eb2e8f9f7 446 * @{
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 450 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 451 *
<> 144:ef7eb2e8f9f7 452 @verbatim
<> 144:ef7eb2e8f9f7 453 ==============================================================================
<> 144:ef7eb2e8f9f7 454 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 455 ==============================================================================
<> 144:ef7eb2e8f9f7 456 [..]
<> 144:ef7eb2e8f9f7 457 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 458 (+) Initialize and configure the FMC NAND interface
<> 144:ef7eb2e8f9f7 459 (+) De-initialize the FMC NAND interface
<> 144:ef7eb2e8f9f7 460 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 @endverbatim
<> 144:ef7eb2e8f9f7 463 * @{
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief Initializes the FMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 468 * control parameters in the FMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 469 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 470 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 471 * @retval HAL status
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Check the parameters */
<> 144:ef7eb2e8f9f7 478 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 479 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 480 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 481 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 482 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 483 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 484 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 485 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 488 tmpr = Device->PCR;
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
<> 144:ef7eb2e8f9f7 491 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
<> 144:ef7eb2e8f9f7 492 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
<> 144:ef7eb2e8f9f7 493 FMC_PCR_TAR | FMC_PCR_ECCPS));
<> 144:ef7eb2e8f9f7 494 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 495 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 496 FMC_PCR_MEMORY_TYPE_NAND |\
<> 144:ef7eb2e8f9f7 497 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 498 Init->EccComputation |\
<> 144:ef7eb2e8f9f7 499 Init->ECCPageSize |\
<> 144:ef7eb2e8f9f7 500 ((Init->TCLRSetupTime) << 9) |\
<> 144:ef7eb2e8f9f7 501 ((Init->TARSetupTime) << 13));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 504 Device->PCR = tmpr;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 return HAL_OK;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /**
<> 144:ef7eb2e8f9f7 511 * @brief Initializes the FMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 512 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 513 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 514 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 515 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 516 * @retval HAL status
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Check the parameters */
<> 144:ef7eb2e8f9f7 523 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 524 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 525 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 526 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 527 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 528 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 531 tmpr = Device->PMEM;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 534 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
<> 144:ef7eb2e8f9f7 535 FMC_PMEM_MEMHIZ3));
<> 144:ef7eb2e8f9f7 536 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 537 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 538 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 539 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 540 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 541 );
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 544 Device->PMEM = tmpr;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 return HAL_OK;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 551 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 552 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 553 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 554 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 555 * @retval HAL status
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Check the parameters */
<> 144:ef7eb2e8f9f7 562 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 563 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 564 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 565 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 566 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 567 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 570 tmpr = Device->PATT;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 573 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
<> 144:ef7eb2e8f9f7 574 FMC_PATT_ATTHIZ3));
<> 144:ef7eb2e8f9f7 575 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 576 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 577 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 578 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 579 ((Timing->HiZSetupTime) << 24));
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 582 Device->PATT = tmpr;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 return HAL_OK;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @brief DeInitializes the FMC_NAND device
<> 144:ef7eb2e8f9f7 589 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 590 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 591 * @retval HAL status
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 /* Check the parameters */
<> 144:ef7eb2e8f9f7 596 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 597 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 600 __FMC_NAND_DISABLE(Device);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Set the FMC_NAND_BANK3 registers to their reset values */
<> 144:ef7eb2e8f9f7 603 Device->PCR = 0x00000018U;
<> 144:ef7eb2e8f9f7 604 Device->SR = 0x00000040U;
<> 144:ef7eb2e8f9f7 605 Device->PMEM = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 606 Device->PATT = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 return HAL_OK;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @}
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /** @defgroup HAL_FMC_NAND_Group3 Control functions
<> 144:ef7eb2e8f9f7 616 * @brief management functions
<> 144:ef7eb2e8f9f7 617 *
<> 144:ef7eb2e8f9f7 618 @verbatim
<> 144:ef7eb2e8f9f7 619 ==============================================================================
<> 144:ef7eb2e8f9f7 620 ##### FMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 621 ==============================================================================
<> 144:ef7eb2e8f9f7 622 [..]
<> 144:ef7eb2e8f9f7 623 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 624 the FMC NAND interface.
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 @endverbatim
<> 144:ef7eb2e8f9f7 627 * @{
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @brief Enables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 633 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 634 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 635 * @retval HAL status
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Check the parameters */
<> 144:ef7eb2e8f9f7 640 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 641 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 644 Device->PCR |= FMC_PCR_ECCEN;
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 return HAL_OK;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 652 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 653 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 654 * @retval HAL status
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Check the parameters */
<> 144:ef7eb2e8f9f7 659 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 660 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 663 Device->PCR &= ~FMC_PCR_ECCEN;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 return HAL_OK;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 670 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 671 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 672 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 673 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 674 * @retval HAL status
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Check the parameters */
<> 144:ef7eb2e8f9f7 681 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 682 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Get tick */
<> 144:ef7eb2e8f9f7 685 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Wait until FIFO is empty */
<> 144:ef7eb2e8f9f7 688 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 691 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 692 {
<> 144:ef7eb2e8f9f7 693 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Get the ECCR register value */
<> 144:ef7eb2e8f9f7 701 *ECCval = (uint32_t)Device->ECCR;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 return HAL_OK;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @}
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @}
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /** @defgroup FMC_LL_SDRAM
<> 144:ef7eb2e8f9f7 715 * @brief SDRAM Controller functions
<> 144:ef7eb2e8f9f7 716 *
<> 144:ef7eb2e8f9f7 717 @verbatim
<> 144:ef7eb2e8f9f7 718 ==============================================================================
<> 144:ef7eb2e8f9f7 719 ##### How to use SDRAM device driver #####
<> 144:ef7eb2e8f9f7 720 ==============================================================================
<> 144:ef7eb2e8f9f7 721 [..]
<> 144:ef7eb2e8f9f7 722 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
<> 144:ef7eb2e8f9f7 723 to run the SDRAM external devices.
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
<> 144:ef7eb2e8f9f7 726 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
<> 144:ef7eb2e8f9f7 727 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 728 (+) FMC SDRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 729 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 730 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 @endverbatim
<> 144:ef7eb2e8f9f7 733 * @{
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 737 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 738 *
<> 144:ef7eb2e8f9f7 739 @verbatim
<> 144:ef7eb2e8f9f7 740 ==============================================================================
<> 144:ef7eb2e8f9f7 741 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 742 ==============================================================================
<> 144:ef7eb2e8f9f7 743 [..]
<> 144:ef7eb2e8f9f7 744 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 745 (+) Initialize and configure the FMC SDRAM interface
<> 144:ef7eb2e8f9f7 746 (+) De-initialize the FMC SDRAM interface
<> 144:ef7eb2e8f9f7 747 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 @endverbatim
<> 144:ef7eb2e8f9f7 750 * @{
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @brief Initializes the FMC_SDRAM device according to the specified
<> 144:ef7eb2e8f9f7 755 * control parameters in the FMC_SDRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 756 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 757 * @param Init: Pointer to SDRAM Initialization structure
<> 144:ef7eb2e8f9f7 758 * @retval HAL status
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 uint32_t tmpr1 = 0;
<> 144:ef7eb2e8f9f7 763 uint32_t tmpr2 = 0;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Check the parameters */
<> 144:ef7eb2e8f9f7 766 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 767 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
<> 144:ef7eb2e8f9f7 768 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
<> 144:ef7eb2e8f9f7 769 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
<> 144:ef7eb2e8f9f7 770 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 771 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
<> 144:ef7eb2e8f9f7 772 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
<> 144:ef7eb2e8f9f7 773 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
<> 144:ef7eb2e8f9f7 774 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
<> 144:ef7eb2e8f9f7 775 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
<> 144:ef7eb2e8f9f7 776 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Set SDRAM bank configuration parameters */
<> 144:ef7eb2e8f9f7 779 if (Init->SDBank != FMC_SDRAM_BANK2)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 784 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
<> 144:ef7eb2e8f9f7 785 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
<> 144:ef7eb2e8f9f7 786 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
<> 144:ef7eb2e8f9f7 789 Init->RowBitsNumber |\
<> 144:ef7eb2e8f9f7 790 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 791 Init->InternalBankNumber |\
<> 144:ef7eb2e8f9f7 792 Init->CASLatency |\
<> 144:ef7eb2e8f9f7 793 Init->WriteProtection |\
<> 144:ef7eb2e8f9f7 794 Init->SDClockPeriod |\
<> 144:ef7eb2e8f9f7 795 Init->ReadBurst |\
<> 144:ef7eb2e8f9f7 796 Init->ReadPipeDelay
<> 144:ef7eb2e8f9f7 797 );
<> 144:ef7eb2e8f9f7 798 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 else /* FMC_Bank2_SDRAM */
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Clear SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 805 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
<> 144:ef7eb2e8f9f7 808 Init->ReadBurst |\
<> 144:ef7eb2e8f9f7 809 Init->ReadPipeDelay);
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 814 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
<> 144:ef7eb2e8f9f7 815 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
<> 144:ef7eb2e8f9f7 816 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
<> 144:ef7eb2e8f9f7 819 Init->RowBitsNumber |\
<> 144:ef7eb2e8f9f7 820 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 821 Init->InternalBankNumber |\
<> 144:ef7eb2e8f9f7 822 Init->CASLatency |\
<> 144:ef7eb2e8f9f7 823 Init->WriteProtection);
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 826 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 return HAL_OK;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /**
<> 144:ef7eb2e8f9f7 834 * @brief Initializes the FMC_SDRAM device timing according to the specified
<> 144:ef7eb2e8f9f7 835 * parameters in the FMC_SDRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 836 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 837 * @param Timing: Pointer to SDRAM Timing structure
<> 144:ef7eb2e8f9f7 838 * @param Bank: SDRAM bank number
<> 144:ef7eb2e8f9f7 839 * @retval HAL status
<> 144:ef7eb2e8f9f7 840 */
<> 144:ef7eb2e8f9f7 841 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 uint32_t tmpr1 = 0;
<> 144:ef7eb2e8f9f7 844 uint32_t tmpr2 = 0;
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Check the parameters */
<> 144:ef7eb2e8f9f7 847 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 848 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
<> 144:ef7eb2e8f9f7 849 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
<> 144:ef7eb2e8f9f7 850 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
<> 144:ef7eb2e8f9f7 851 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
<> 144:ef7eb2e8f9f7 852 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
<> 144:ef7eb2e8f9f7 853 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
<> 144:ef7eb2e8f9f7 854 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
<> 144:ef7eb2e8f9f7 855 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Set SDRAM device timing parameters */
<> 144:ef7eb2e8f9f7 858 if (Bank != FMC_SDRAM_BANK2)
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
<> 144:ef7eb2e8f9f7 863 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
<> 144:ef7eb2e8f9f7 864 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
<> 144:ef7eb2e8f9f7 865 FMC_SDTR1_TRCD));
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
<> 144:ef7eb2e8f9f7 868 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
<> 144:ef7eb2e8f9f7 869 (((Timing->SelfRefreshTime)-1) << 8) |\
<> 144:ef7eb2e8f9f7 870 (((Timing->RowCycleDelay)-1) << 12) |\
<> 144:ef7eb2e8f9f7 871 (((Timing->WriteRecoveryTime)-1) <<16) |\
<> 144:ef7eb2e8f9f7 872 (((Timing->RPDelay)-1) << 20) |\
<> 144:ef7eb2e8f9f7 873 (((Timing->RCDDelay)-1) << 24));
<> 144:ef7eb2e8f9f7 874 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876 else /* FMC_Bank2_SDRAM */
<> 144:ef7eb2e8f9f7 877 {
<> 144:ef7eb2e8f9f7 878 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Clear TRC and TRP bits */
<> 144:ef7eb2e8f9f7 881 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
<> 144:ef7eb2e8f9f7 884 (((Timing->RPDelay)-1) << 20));
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
<> 144:ef7eb2e8f9f7 889 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
<> 144:ef7eb2e8f9f7 890 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
<> 144:ef7eb2e8f9f7 891 FMC_SDTR1_TRCD));
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
<> 144:ef7eb2e8f9f7 894 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
<> 144:ef7eb2e8f9f7 895 (((Timing->SelfRefreshTime)-1) << 8) |\
<> 144:ef7eb2e8f9f7 896 (((Timing->WriteRecoveryTime)-1) <<16) |\
<> 144:ef7eb2e8f9f7 897 (((Timing->RCDDelay)-1) << 24));
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 900 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 return HAL_OK;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @brief DeInitializes the FMC_SDRAM peripheral
<> 144:ef7eb2e8f9f7 908 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 909 * @retval HAL status
<> 144:ef7eb2e8f9f7 910 */
<> 144:ef7eb2e8f9f7 911 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 /* Check the parameters */
<> 144:ef7eb2e8f9f7 914 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 915 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* De-initialize the SDRAM device */
<> 144:ef7eb2e8f9f7 918 Device->SDCR[Bank] = 0x000002D0;
<> 144:ef7eb2e8f9f7 919 Device->SDTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 920 Device->SDCMR = 0x00000000;
<> 144:ef7eb2e8f9f7 921 Device->SDRTR = 0x00000000;
<> 144:ef7eb2e8f9f7 922 Device->SDSR = 0x00000000;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 return HAL_OK;
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @}
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
<> 144:ef7eb2e8f9f7 932 * @brief management functions
<> 144:ef7eb2e8f9f7 933 *
<> 144:ef7eb2e8f9f7 934 @verbatim
<> 144:ef7eb2e8f9f7 935 ==============================================================================
<> 144:ef7eb2e8f9f7 936 ##### FMC_SDRAM Control functions #####
<> 144:ef7eb2e8f9f7 937 ==============================================================================
<> 144:ef7eb2e8f9f7 938 [..]
<> 144:ef7eb2e8f9f7 939 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 940 the FMC SDRAM interface.
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 @endverbatim
<> 144:ef7eb2e8f9f7 943 * @{
<> 144:ef7eb2e8f9f7 944 */
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /**
<> 144:ef7eb2e8f9f7 947 * @brief Enables dynamically FMC_SDRAM write protection.
<> 144:ef7eb2e8f9f7 948 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 949 * @param Bank: SDRAM bank number
<> 144:ef7eb2e8f9f7 950 * @retval HAL status
<> 144:ef7eb2e8f9f7 951 */
<> 144:ef7eb2e8f9f7 952 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* Check the parameters */
<> 144:ef7eb2e8f9f7 955 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 956 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Enable write protection */
<> 144:ef7eb2e8f9f7 959 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 return HAL_OK;
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @brief Disables dynamically FMC_SDRAM write protection.
<> 144:ef7eb2e8f9f7 966 * @param hsdram: FMC_SDRAM handle
<> 144:ef7eb2e8f9f7 967 * @retval HAL status
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Check the parameters */
<> 144:ef7eb2e8f9f7 972 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 973 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Disable write protection */
<> 144:ef7eb2e8f9f7 976 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 return HAL_OK;
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /**
<> 144:ef7eb2e8f9f7 982 * @brief Send Command to the FMC SDRAM bank
<> 144:ef7eb2e8f9f7 983 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 984 * @param Command: Pointer to SDRAM command structure
<> 144:ef7eb2e8f9f7 985 * @param Timing: Pointer to SDRAM Timing structure
<> 144:ef7eb2e8f9f7 986 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 987 * @retval HAL state
<> 144:ef7eb2e8f9f7 988 */
<> 144:ef7eb2e8f9f7 989 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 __IO uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 992 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Check the parameters */
<> 144:ef7eb2e8f9f7 995 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 996 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
<> 144:ef7eb2e8f9f7 997 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
<> 144:ef7eb2e8f9f7 998 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
<> 144:ef7eb2e8f9f7 999 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Set command register */
<> 144:ef7eb2e8f9f7 1002 tmpr = (uint32_t)((Command->CommandMode) |\
<> 144:ef7eb2e8f9f7 1003 (Command->CommandTarget) |\
<> 144:ef7eb2e8f9f7 1004 (((Command->AutoRefreshNumber)-1) << 5) |\
<> 144:ef7eb2e8f9f7 1005 ((Command->ModeRegisterDefinition) << 9)
<> 144:ef7eb2e8f9f7 1006 );
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 Device->SDCMR = tmpr;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Get tick */
<> 144:ef7eb2e8f9f7 1011 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* wait until command is send */
<> 144:ef7eb2e8f9f7 1014 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1017 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 return HAL_OK;
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /**
<> 144:ef7eb2e8f9f7 1030 * @brief Program the SDRAM Memory Refresh rate.
<> 144:ef7eb2e8f9f7 1031 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1032 * @param RefreshRate: The SDRAM refresh rate value.
<> 144:ef7eb2e8f9f7 1033 * @retval HAL state
<> 144:ef7eb2e8f9f7 1034 */
<> 144:ef7eb2e8f9f7 1035 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
<> 144:ef7eb2e8f9f7 1036 {
<> 144:ef7eb2e8f9f7 1037 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1038 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1039 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /* Set the refresh rate in command register */
<> 144:ef7eb2e8f9f7 1042 Device->SDRTR |= (RefreshRate<<1);
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 return HAL_OK;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
<> 144:ef7eb2e8f9f7 1049 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1050 * @param AutoRefreshNumber: Specifies the auto Refresh number.
<> 144:ef7eb2e8f9f7 1051 * @retval None
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /* Set the Auto-refresh number in command register */
<> 144:ef7eb2e8f9f7 1060 Device->SDCMR |= (AutoRefreshNumber << 5);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 return HAL_OK;
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /**
<> 144:ef7eb2e8f9f7 1066 * @brief Returns the indicated FMC SDRAM bank mode status.
<> 144:ef7eb2e8f9f7 1067 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1068 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
<> 144:ef7eb2e8f9f7 1069 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
<> 144:ef7eb2e8f9f7 1070 * @retval The FMC SDRAM bank mode status, could be on of the following values:
<> 144:ef7eb2e8f9f7 1071 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
<> 144:ef7eb2e8f9f7 1072 * FMC_SDRAM_POWER_DOWN_MODE.
<> 144:ef7eb2e8f9f7 1073 */
<> 144:ef7eb2e8f9f7 1074 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1075 {
<> 144:ef7eb2e8f9f7 1076 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1079 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1080 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* Get the corresponding bank mode */
<> 144:ef7eb2e8f9f7 1083 if(Bank == FMC_SDRAM_BANK1)
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 else
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Return the mode status */
<> 144:ef7eb2e8f9f7 1093 return tmpreg;
<> 144:ef7eb2e8f9f7 1094 }
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /**
<> 144:ef7eb2e8f9f7 1097 * @}
<> 144:ef7eb2e8f9f7 1098 */
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /**
<> 144:ef7eb2e8f9f7 1101 * @}
<> 144:ef7eb2e8f9f7 1102 */
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @}
<> 144:ef7eb2e8f9f7 1106 */
<> 144:ef7eb2e8f9f7 1107 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /**
<> 144:ef7eb2e8f9f7 1110 * @}
<> 144:ef7eb2e8f9f7 1111 */
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @}
<> 144:ef7eb2e8f9f7 1115 */
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/