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targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL05Z32FK4
<> 144:ef7eb2e8f9f7 4 ** MKL05Z32LC4
<> 144:ef7eb2e8f9f7 5 ** MKL05Z32VLF4
<> 144:ef7eb2e8f9f7 6 **
<> 144:ef7eb2e8f9f7 7 ** Compilers: ARM Compiler
<> 144:ef7eb2e8f9f7 8 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 9 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 10 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 11 **
<> 144:ef7eb2e8f9f7 12 ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
<> 144:ef7eb2e8f9f7 13 ** Version: rev. 1.6, 2013-04-11
<> 144:ef7eb2e8f9f7 14 **
<> 144:ef7eb2e8f9f7 15 ** Abstract:
<> 144:ef7eb2e8f9f7 16 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 17 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 18 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Copyright: 2013 Freescale, Inc. All Rights Reserved.
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 23 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 24 **
<> 144:ef7eb2e8f9f7 25 ** Revisions:
<> 144:ef7eb2e8f9f7 26 ** - rev. 1.0 (2012-06-08)
<> 144:ef7eb2e8f9f7 27 ** Initial version.
<> 144:ef7eb2e8f9f7 28 ** - rev. 1.1 (2012-06-21)
<> 144:ef7eb2e8f9f7 29 ** Update according to reference manual rev. 1.
<> 144:ef7eb2e8f9f7 30 ** - rev. 1.2 (2012-08-01)
<> 144:ef7eb2e8f9f7 31 ** Device type UARTLP changed to UART0.
<> 144:ef7eb2e8f9f7 32 ** Missing PORTB_IRQn interrupt number definition added.
<> 144:ef7eb2e8f9f7 33 ** - rev. 1.3 (2012-10-04)
<> 144:ef7eb2e8f9f7 34 ** Update according to reference manual rev. 3.
<> 144:ef7eb2e8f9f7 35 ** - rev. 1.4 (2012-11-22)
<> 144:ef7eb2e8f9f7 36 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
<> 144:ef7eb2e8f9f7 37 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
<> 144:ef7eb2e8f9f7 38 ** - rev. 1.5 (2013-04-05)
<> 144:ef7eb2e8f9f7 39 ** Changed start of doxygen comment.
<> 144:ef7eb2e8f9f7 40 ** - rev. 1.6 (2013-04-11)
<> 144:ef7eb2e8f9f7 41 ** SystemInit methods updated with predefined initialization sequence.
<> 144:ef7eb2e8f9f7 42 **
<> 144:ef7eb2e8f9f7 43 ** ###################################################################
<> 144:ef7eb2e8f9f7 44 */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*!
<> 144:ef7eb2e8f9f7 47 * @file MKL05Z4
<> 144:ef7eb2e8f9f7 48 * @version 1.6
<> 144:ef7eb2e8f9f7 49 * @date 2013-04-11
<> 144:ef7eb2e8f9f7 50 * @brief Device specific configuration file for MKL05Z4 (implementation file)
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 53 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 54 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #include <stdint.h>
<> 144:ef7eb2e8f9f7 58 #include "MKL05Z4.h"
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 #define DISABLE_WDOG 1
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 63 /* Predefined clock setups
<> 144:ef7eb2e8f9f7 64 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
<> 144:ef7eb2e8f9f7 65 Reference clock source for MCG module is the slow internal clock source 32.768kHz
<> 144:ef7eb2e8f9f7 66 Core clock = 41.94MHz, BusClock = 20.97MHz
<> 144:ef7eb2e8f9f7 67 1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
<> 144:ef7eb2e8f9f7 68 Reference clock source for MCG module is an external crystal 32.768kHz
<> 144:ef7eb2e8f9f7 69 Core clock = 47.97MHz, BusClock = 23.98MHz
<> 144:ef7eb2e8f9f7 70 2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
<> 144:ef7eb2e8f9f7 71 Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
<> 144:ef7eb2e8f9f7 72 Core clock = 4MHz, BusClock = 4MHz
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 76 Define clock source values
<> 144:ef7eb2e8f9f7 77 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 79 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 80 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 81 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 82 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
<> 144:ef7eb2e8f9f7 83 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 84 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 85 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 86 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 87 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
<> 144:ef7eb2e8f9f7 88 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 89 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 90 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 91 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 92 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 93 #endif /* (CLOCK_SETUP == 2) */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 97 -- Core clock
<> 144:ef7eb2e8f9f7 98 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 103 -- SystemInit()
<> 144:ef7eb2e8f9f7 104 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 static void busy_delay(uint32_t delay) {
<> 144:ef7eb2e8f9f7 107 volatile uint32_t i = delay;
<> 144:ef7eb2e8f9f7 108 while (i--);
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 112 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 113 /* Disable the WDOG module */
<> 144:ef7eb2e8f9f7 114 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
<> 144:ef7eb2e8f9f7 115 SIM->COPC = (uint32_t)0x00u;
<> 144:ef7eb2e8f9f7 116 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 117 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 118 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 119 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
<> 144:ef7eb2e8f9f7 120 /* Switch to FEI Mode */
<> 144:ef7eb2e8f9f7 121 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 122 MCG->C1 = MCG_C1_CLKS(0x00) |
<> 144:ef7eb2e8f9f7 123 MCG_C1_FRDIV(0x00) |
<> 144:ef7eb2e8f9f7 124 MCG_C1_IREFS_MASK |
<> 144:ef7eb2e8f9f7 125 MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 126 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 127 MCG->C2 = MCG_C2_RANGE0(0x00);
<> 144:ef7eb2e8f9f7 128 /* MCG_C4: DMX32=0,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 129 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
<> 144:ef7eb2e8f9f7 130 MCG_C4_DMX32_MASK |
<> 144:ef7eb2e8f9f7 131 MCG_C4_DRST_DRS(0x02)
<> 144:ef7eb2e8f9f7 132 )) | (uint8_t)(
<> 144:ef7eb2e8f9f7 133 MCG_C4_DRST_DRS(0x01)
<> 144:ef7eb2e8f9f7 134 ));
<> 144:ef7eb2e8f9f7 135 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 136 OSC0->CR = OSC_CR_ERCLKEN_MASK;
<> 144:ef7eb2e8f9f7 137 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 142 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 143 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 144 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 145 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
<> 144:ef7eb2e8f9f7 146 /* PORTA->PCR[3]: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 147 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 148 /* PORTA->PCR[4]: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 149 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 150 /* Switch to FEE Mode */
<> 144:ef7eb2e8f9f7 151 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 152 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
<> 144:ef7eb2e8f9f7 153 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
<> 144:ef7eb2e8f9f7 154 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC4P_MASK;
<> 144:ef7eb2e8f9f7 155 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 156 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
<> 144:ef7eb2e8f9f7 157 /* MCG->C4: DMX32=1,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 158 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
<> 144:ef7eb2e8f9f7 159 MCG_C4_DRST_DRS(0x02)
<> 144:ef7eb2e8f9f7 160 )) | (uint8_t)(
<> 144:ef7eb2e8f9f7 161 MCG_C4_DMX32_MASK |
<> 144:ef7eb2e8f9f7 162 MCG_C4_DRST_DRS(0x01)
<> 144:ef7eb2e8f9f7 163 ));
<> 144:ef7eb2e8f9f7 164 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 169 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 170 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
<> 144:ef7eb2e8f9f7 171 /* MCG->SC: FCRDIV=0 */
<> 144:ef7eb2e8f9f7 172 MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
<> 144:ef7eb2e8f9f7 173 /* Switch to FBI Mode */
<> 144:ef7eb2e8f9f7 174 /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 175 MCG->C1 = MCG_C1_CLKS(0x01) |
<> 144:ef7eb2e8f9f7 176 MCG_C1_FRDIV(0x00) |
<> 144:ef7eb2e8f9f7 177 MCG_C1_IREFS_MASK |
<> 144:ef7eb2e8f9f7 178 MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 179 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
<> 144:ef7eb2e8f9f7 180 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
<> 144:ef7eb2e8f9f7 181 /* MCG->C4: DMX32=0,DRST_DRS=0 */
<> 144:ef7eb2e8f9f7 182 MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
<> 144:ef7eb2e8f9f7 183 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 184 OSC0->CR = OSC_CR_ERCLKEN_MASK;
<> 144:ef7eb2e8f9f7 185 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 /* Switch to BLPI Mode */
<> 144:ef7eb2e8f9f7 190 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
<> 144:ef7eb2e8f9f7 191 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
<> 144:ef7eb2e8f9f7 192 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194 while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196 #endif /* (CLOCK_SETUP == 2) */
<> 144:ef7eb2e8f9f7 197 // Give the FLL time to stabilize
<> 144:ef7eb2e8f9f7 198 // This can take up to 1ms according to the KL05 datasheet
<> 144:ef7eb2e8f9f7 199 // Note: Without this delay the UART's baud can be wrong for the
<> 144:ef7eb2e8f9f7 200 // first byte sent in some cases. A delay of 1000 fixes this
<> 144:ef7eb2e8f9f7 201 // problem even under optimizations. The delay of 10,000 is used
<> 144:ef7eb2e8f9f7 202 // to add a saftey margin.
<> 144:ef7eb2e8f9f7 203 busy_delay(10000);
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 207 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 208 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 211 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 212 uint8_t Divider;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 215 /* Output of FLL is selected */
<> 144:ef7eb2e8f9f7 216 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 217 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 218 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 219 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 220 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 221 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 222 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 223 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 224 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 225 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 226 case 0x0u:
<> 144:ef7eb2e8f9f7 227 MCGOUTClock *= 640u;
<> 144:ef7eb2e8f9f7 228 break;
<> 144:ef7eb2e8f9f7 229 case 0x20u:
<> 144:ef7eb2e8f9f7 230 MCGOUTClock *= 1280u;
<> 144:ef7eb2e8f9f7 231 break;
<> 144:ef7eb2e8f9f7 232 case 0x40u:
<> 144:ef7eb2e8f9f7 233 MCGOUTClock *= 1920u;
<> 144:ef7eb2e8f9f7 234 break;
<> 144:ef7eb2e8f9f7 235 case 0x60u:
<> 144:ef7eb2e8f9f7 236 MCGOUTClock *= 2560u;
<> 144:ef7eb2e8f9f7 237 break;
<> 144:ef7eb2e8f9f7 238 case 0x80u:
<> 144:ef7eb2e8f9f7 239 MCGOUTClock *= 732u;
<> 144:ef7eb2e8f9f7 240 break;
<> 144:ef7eb2e8f9f7 241 case 0xA0u:
<> 144:ef7eb2e8f9f7 242 MCGOUTClock *= 1464u;
<> 144:ef7eb2e8f9f7 243 break;
<> 144:ef7eb2e8f9f7 244 case 0xC0u:
<> 144:ef7eb2e8f9f7 245 MCGOUTClock *= 2197u;
<> 144:ef7eb2e8f9f7 246 break;
<> 144:ef7eb2e8f9f7 247 case 0xE0u:
<> 144:ef7eb2e8f9f7 248 MCGOUTClock *= 2929u;
<> 144:ef7eb2e8f9f7 249 break;
<> 144:ef7eb2e8f9f7 250 default:
<> 144:ef7eb2e8f9f7 251 break;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
<> 144:ef7eb2e8f9f7 254 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 255 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 256 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 257 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 258 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 259 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 260 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
<> 144:ef7eb2e8f9f7 261 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 262 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 263 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 264 /* Reserved value */
<> 144:ef7eb2e8f9f7 265 return;
<> 144:ef7eb2e8f9f7 266 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 267 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 268 }