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targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Compilers: ARM Compiler
<> 144:ef7eb2e8f9f7 4 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 5 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 6 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 7 **
<> 144:ef7eb2e8f9f7 8 **
<> 144:ef7eb2e8f9f7 9 **
<> 144:ef7eb2e8f9f7 10 ** Version: rev. 1.0, 2011-12-15
<> 144:ef7eb2e8f9f7 11 **
<> 144:ef7eb2e8f9f7 12 ** Abstract:
<> 144:ef7eb2e8f9f7 13 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 14 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 15 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
<> 144:ef7eb2e8f9f7 18 **
<> 144:ef7eb2e8f9f7 19 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 20 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** Revisions:
<> 144:ef7eb2e8f9f7 23 ** - rev. 1.0 (2011-12-15)
<> 144:ef7eb2e8f9f7 24 ** Initial version
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** ###################################################################
<> 144:ef7eb2e8f9f7 27 */
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /**
<> 144:ef7eb2e8f9f7 30 * @file MK20DX256
<> 144:ef7eb2e8f9f7 31 * @version 1.0
<> 144:ef7eb2e8f9f7 32 * @date 2011-12-15
<> 144:ef7eb2e8f9f7 33 * @brief Device specific configuration file for MK20DX256 (implementation file)
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 36 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 37 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #include <stdint.h>
<> 144:ef7eb2e8f9f7 41 #include "MK20DX256.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #define DISABLE_WDOG 1
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 46 /* Predefined clock setups
<> 144:ef7eb2e8f9f7 47 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
<> 144:ef7eb2e8f9f7 48 Reference clock source for MCG module is the slow internal clock source 32.768kHz
<> 144:ef7eb2e8f9f7 49 Core clock = 41.94MHz, BusClock = 41.94MHz
<> 144:ef7eb2e8f9f7 50 Works on Teensy3.1 but no USB support
<> 144:ef7eb2e8f9f7 51 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
<> 144:ef7eb2e8f9f7 52 Reference clock source for MCG module is an external crystal 16MHz
<> 144:ef7eb2e8f9f7 53 Core clock = 96MHz, BusClock = 48MHz
<> 144:ef7eb2e8f9f7 54 Default high speed Teensy3.1 96Mhz set up
<> 144:ef7eb2e8f9f7 55 2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
<> 144:ef7eb2e8f9f7 56 Reference clock source for MCG module is an external crystal 16MHz
<> 144:ef7eb2e8f9f7 57 Core clock = 72MHz, BusClock = 36MHz
<> 144:ef7eb2e8f9f7 58 Alternative standard 'slower' Teensy3.1 72Mhz set up
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 62 Define clock source values
<> 144:ef7eb2e8f9f7 63 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 64 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 65 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 66 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 67 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 68 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 69 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
<> 144:ef7eb2e8f9f7 70 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 71 #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 72 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 73 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 74 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 75 #define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 76 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 77 #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 78 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 79 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 80 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 81 #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 82 #endif /* (CLOCK_SETUP == 2) */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 86 -- Core clock
<> 144:ef7eb2e8f9f7 87 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 92 -- SystemInit()
<> 144:ef7eb2e8f9f7 93 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 94 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 95 /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 98 /* Disable the WDOG module */
<> 144:ef7eb2e8f9f7 99 /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
<> 144:ef7eb2e8f9f7 100 WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
<> 144:ef7eb2e8f9f7 101 /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
<> 144:ef7eb2e8f9f7 102 WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
<> 144:ef7eb2e8f9f7 103 /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
<> 144:ef7eb2e8f9f7 104 WDOG->STCTRLH = (uint16_t)0x01D2u;
<> 144:ef7eb2e8f9f7 105 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 108 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
<> 144:ef7eb2e8f9f7 109 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
<> 144:ef7eb2e8f9f7 110 /* Switch to FEI Mode */
<> 144:ef7eb2e8f9f7 111 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 112 MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 113 /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 114 MCG->C2 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 115 /* MCG_C4: DMX32=0,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 116 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
<> 144:ef7eb2e8f9f7 117 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 118 MCG->C5 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 119 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 120 MCG->C6 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 121 while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 122 while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 125 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/
<> 144:ef7eb2e8f9f7 126 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
<> 144:ef7eb2e8f9f7 127 /* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */
<> 144:ef7eb2e8f9f7 128 SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
<> 144:ef7eb2e8f9f7 129 /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
<> 144:ef7eb2e8f9f7 130 OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
<> 144:ef7eb2e8f9f7 131 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 132 /* MCG->C7: OSCSEL=0 */
<> 144:ef7eb2e8f9f7 133 MCG->C7 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 134 /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 135 MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
<> 144:ef7eb2e8f9f7 136 //MCG->C2 = (uint8_t)0x24u;
<> 144:ef7eb2e8f9f7 137 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 138 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 139 /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 140 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
<> 144:ef7eb2e8f9f7 141 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
<> 144:ef7eb2e8f9f7 142 MCG->C5 = MCG_C5_PRDIV0(7);
<> 144:ef7eb2e8f9f7 143 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 144 MCG->C6 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 145 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
<> 144:ef7eb2e8f9f7 146 while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 147 /* Switch to PBE Mode */
<> 144:ef7eb2e8f9f7 148 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
<> 144:ef7eb2e8f9f7 149 MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz
<> 144:ef7eb2e8f9f7 150 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
<> 144:ef7eb2e8f9f7 151 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output
<> 144:ef7eb2e8f9f7 152 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
<> 144:ef7eb2e8f9f7 153 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
<> 144:ef7eb2e8f9f7 154 /* Switch to PEE Mode */
<> 144:ef7eb2e8f9f7 155 /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 156 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 157 while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
<> 144:ef7eb2e8f9f7 158 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 161 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/
<> 144:ef7eb2e8f9f7 162 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
<> 144:ef7eb2e8f9f7 163 /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
<> 144:ef7eb2e8f9f7 164 SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
<> 144:ef7eb2e8f9f7 165 /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
<> 144:ef7eb2e8f9f7 166 OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
<> 144:ef7eb2e8f9f7 167 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 168 /* MCG->C7: OSCSEL=0 */
<> 144:ef7eb2e8f9f7 169 MCG->C7 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 170 /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 171 MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
<> 144:ef7eb2e8f9f7 172 //MCG->C2 = (uint8_t)0x24u;
<> 144:ef7eb2e8f9f7 173 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 174 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 175 /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 176 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
<> 144:ef7eb2e8f9f7 177 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
<> 144:ef7eb2e8f9f7 178 MCG->C5 = MCG_C5_PRDIV0(7);
<> 144:ef7eb2e8f9f7 179 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 180 MCG->C6 = (uint8_t)0x00u;
<> 144:ef7eb2e8f9f7 181 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
<> 144:ef7eb2e8f9f7 182 while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 183 /* Switch to PBE Mode */
<> 144:ef7eb2e8f9f7 184 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
<> 144:ef7eb2e8f9f7 185 MCG->C5 = MCG_C5_PRDIV0(5);
<> 144:ef7eb2e8f9f7 186 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
<> 144:ef7eb2e8f9f7 187 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
<> 144:ef7eb2e8f9f7 188 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
<> 144:ef7eb2e8f9f7 189 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
<> 144:ef7eb2e8f9f7 190 /* Switch to PEE Mode */
<> 144:ef7eb2e8f9f7 191 /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 192 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 193 while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
<> 144:ef7eb2e8f9f7 194 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
<> 144:ef7eb2e8f9f7 195 #endif /* (CLOCK_SETUP) */
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 199 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 200 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 203 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 204 uint8_t Divider;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 207 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 208 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 209 /* FLL is selected */
<> 144:ef7eb2e8f9f7 210 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 211 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 212 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 213 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 214 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 215 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 216 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 217 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 218 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 219 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
<> 144:ef7eb2e8f9f7 220 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
<> 144:ef7eb2e8f9f7 221 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
<> 144:ef7eb2e8f9f7 222 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 223 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 224 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 225 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 226 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 227 case 0x0u:
<> 144:ef7eb2e8f9f7 228 MCGOUTClock *= 640u;
<> 144:ef7eb2e8f9f7 229 break;
<> 144:ef7eb2e8f9f7 230 case 0x20u:
<> 144:ef7eb2e8f9f7 231 MCGOUTClock *= 1280u;
<> 144:ef7eb2e8f9f7 232 break;
<> 144:ef7eb2e8f9f7 233 case 0x40u:
<> 144:ef7eb2e8f9f7 234 MCGOUTClock *= 1920u;
<> 144:ef7eb2e8f9f7 235 break;
<> 144:ef7eb2e8f9f7 236 case 0x60u:
<> 144:ef7eb2e8f9f7 237 MCGOUTClock *= 2560u;
<> 144:ef7eb2e8f9f7 238 break;
<> 144:ef7eb2e8f9f7 239 case 0x80u:
<> 144:ef7eb2e8f9f7 240 MCGOUTClock *= 732u;
<> 144:ef7eb2e8f9f7 241 break;
<> 144:ef7eb2e8f9f7 242 case 0xA0u:
<> 144:ef7eb2e8f9f7 243 MCGOUTClock *= 1464u;
<> 144:ef7eb2e8f9f7 244 break;
<> 144:ef7eb2e8f9f7 245 case 0xC0u:
<> 144:ef7eb2e8f9f7 246 MCGOUTClock *= 2197u;
<> 144:ef7eb2e8f9f7 247 break;
<> 144:ef7eb2e8f9f7 248 case 0xE0u:
<> 144:ef7eb2e8f9f7 249 MCGOUTClock *= 2929u;
<> 144:ef7eb2e8f9f7 250 break;
<> 144:ef7eb2e8f9f7 251 default:
<> 144:ef7eb2e8f9f7 252 break;
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 255 /* PLL is selected */
<> 144:ef7eb2e8f9f7 256 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
<> 144:ef7eb2e8f9f7 257 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 258 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
<> 144:ef7eb2e8f9f7 259 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 260 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 261 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
<> 144:ef7eb2e8f9f7 262 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 263 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 264 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 265 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 266 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 267 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 268 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
<> 144:ef7eb2e8f9f7 269 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 270 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 271 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 272 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 273 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 274 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 275 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 276 /* Reserved value */
<> 144:ef7eb2e8f9f7 277 return;
<> 144:ef7eb2e8f9f7 278 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 279 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 280 }