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mbed library sources. Supersedes mbed-src.

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@71:a5b1c83f05dc, 2016-02-25 (annotated)

Committer:: mbed_official
Date:: Thu Feb 25 09:45:11 2016 +0000
Revision:: 71:a5b1c83f05dc
Parent:: 34:bb6061527455
Child:: 98:f043b034eb5d

Synchronized with git revision 8577dc9680abc50885f129a77852579c5a5bc527



Full URL: https://github.com/mbedmicro/mbed/commit/8577dc9680abc50885f129a77852579c5a5bc527/



l476rg rtc

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L4xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L4xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	68	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm	0:9b334a45a8ff	74	This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
bogdanm	0:9b334a45a8ff	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
bogdanm	0:9b334a45a8ff	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
bogdanm	0:9b334a45a8ff	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
bogdanm	0:9b334a45a8ff	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
bogdanm	0:9b334a45a8ff	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	}RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	/**
bogdanm	0:9b334a45a8ff	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
bogdanm	0:9b334a45a8ff	93	*/
bogdanm	0:9b334a45a8ff	94	typedef struct
bogdanm	0:9b334a45a8ff	95	{
bogdanm	0:9b334a45a8ff	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	0:9b334a45a8ff	97	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	0:9b334a45a8ff	100	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	0:9b334a45a8ff	106	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	0:9b334a45a8ff	112	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	uint32_t MSIState; /*!< The new state of the MSI.
bogdanm	0:9b334a45a8ff	115	This parameter can be a value of @ref RCC_MSI_Config */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	118	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	uint32_t MSIClockRange; /*!< The MSI frequency range.
bogdanm	0:9b334a45a8ff	121	This parameter can be a value of @ref RCC_MSI_Clock_Range */
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	}RCC_OscInitTypeDef;
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/**
bogdanm	0:9b334a45a8ff	128	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	129	*/
bogdanm	0:9b334a45a8ff	130	typedef struct
bogdanm	0:9b334a45a8ff	131	{
bogdanm	0:9b334a45a8ff	132	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	133	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	136	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	137
bogdanm	0:9b334a45a8ff	138	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	139	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	142	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	145	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	}RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	/**
bogdanm	0:9b334a45a8ff	150	* @}
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	154	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	155	* @{
bogdanm	0:9b334a45a8ff	156	*/
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/** @defgroup RCC_Timeout_Value Timeout Values
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	71:a5b1c83f05dc	162	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
bogdanm	0:9b334a45a8ff	163	/**
bogdanm	0:9b334a45a8ff	164	* @}
bogdanm	0:9b334a45a8ff	165	*/
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	0:9b334a45a8ff	168	* @{
bogdanm	0:9b334a45a8ff	169	*/
bogdanm	0:9b334a45a8ff	170	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
bogdanm	0:9b334a45a8ff	171	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
bogdanm	0:9b334a45a8ff	172	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
bogdanm	0:9b334a45a8ff	173	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
bogdanm	0:9b334a45a8ff	174	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
bogdanm	0:9b334a45a8ff	175	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
bogdanm	0:9b334a45a8ff	176	/**
bogdanm	0:9b334a45a8ff	177	* @}
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/** @defgroup RCC_HSE_Config HSE Config
bogdanm	0:9b334a45a8ff	181	* @{
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
bogdanm	0:9b334a45a8ff	184	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
bogdanm	0:9b334a45a8ff	185	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @}
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	/** @defgroup RCC_LSE_Config LSE Config
bogdanm	0:9b334a45a8ff	191	* @{
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
bogdanm	0:9b334a45a8ff	194	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
bogdanm	0:9b334a45a8ff	195	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
bogdanm	0:9b334a45a8ff	196	/**
bogdanm	0:9b334a45a8ff	197	* @}
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/** @defgroup RCC_HSI_Config HSI Config
bogdanm	0:9b334a45a8ff	201	* @{
bogdanm	0:9b334a45a8ff	202	*/
bogdanm	0:9b334a45a8ff	203	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
bogdanm	0:9b334a45a8ff	204	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /!< Default HSI calibration trimming value /
bogdanm	0:9b334a45a8ff	207	/**
bogdanm	0:9b334a45a8ff	208	* @}
bogdanm	0:9b334a45a8ff	209	*/
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/** @defgroup RCC_LSI_Config LSI Config
bogdanm	0:9b334a45a8ff	212	* @{
bogdanm	0:9b334a45a8ff	213	*/
bogdanm	0:9b334a45a8ff	214	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
bogdanm	0:9b334a45a8ff	215	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
bogdanm	0:9b334a45a8ff	216	/**
bogdanm	0:9b334a45a8ff	217	* @}
bogdanm	0:9b334a45a8ff	218	*/
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/** @defgroup RCC_MSI_Config MSI Config
bogdanm	0:9b334a45a8ff	221	* @{
bogdanm	0:9b334a45a8ff	222	*/
bogdanm	0:9b334a45a8ff	223	#define RCC_MSI_OFF ((uint32_t)0x00000000) /!< MSI clock deactivation /
bogdanm	0:9b334a45a8ff	224	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
bogdanm	0:9b334a45a8ff	227	/**
bogdanm	0:9b334a45a8ff	228	* @}
bogdanm	0:9b334a45a8ff	229	*/
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/** @defgroup RCC_PLL_Config PLL Config
bogdanm	0:9b334a45a8ff	232	* @{
bogdanm	0:9b334a45a8ff	233	*/
bogdanm	0:9b334a45a8ff	234	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL configuration unchanged /
bogdanm	0:9b334a45a8ff	235	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
bogdanm	0:9b334a45a8ff	236	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
bogdanm	0:9b334a45a8ff	237	/**
bogdanm	0:9b334a45a8ff	238	* @}
bogdanm	0:9b334a45a8ff	239	*/
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
bogdanm	0:9b334a45a8ff	242	* @{
bogdanm	0:9b334a45a8ff	243	*/
bogdanm	0:9b334a45a8ff	244	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007) /!< PLLP division factor = 7 /
bogdanm	0:9b334a45a8ff	245	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011) /!< PLLP division factor = 17 /
bogdanm	0:9b334a45a8ff	246	/**
bogdanm	0:9b334a45a8ff	247	* @}
bogdanm	0:9b334a45a8ff	248	*/
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
bogdanm	0:9b334a45a8ff	251	* @{
bogdanm	0:9b334a45a8ff	252	*/
bogdanm	0:9b334a45a8ff	253	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002) /!< PLLQ division factor = 2 /
bogdanm	0:9b334a45a8ff	254	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004) /!< PLLQ division factor = 4 /
bogdanm	0:9b334a45a8ff	255	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006) /!< PLLQ division factor = 6 /
bogdanm	0:9b334a45a8ff	256	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008) /!< PLLQ division factor = 8 /
bogdanm	0:9b334a45a8ff	257	/**
bogdanm	0:9b334a45a8ff	258	* @}
bogdanm	0:9b334a45a8ff	259	*/
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
bogdanm	0:9b334a45a8ff	262	* @{
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002) /!< PLLR division factor = 2 /
bogdanm	0:9b334a45a8ff	265	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004) /!< PLLR division factor = 4 /
bogdanm	0:9b334a45a8ff	266	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006) /!< PLLR division factor = 6 /
bogdanm	0:9b334a45a8ff	267	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008) /!< PLLR division factor = 8 /
bogdanm	0:9b334a45a8ff	268	/**
bogdanm	0:9b334a45a8ff	269	* @}
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	0:9b334a45a8ff	273	* @{
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000) /!< No clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	276	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	277	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	278	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	279	/**
bogdanm	0:9b334a45a8ff	280	* @}
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
bogdanm	0:9b334a45a8ff	284	* @{
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL /
bogdanm	0:9b334a45a8ff	287	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
bogdanm	0:9b334a45a8ff	288	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
bogdanm	0:9b334a45a8ff	289	/**
bogdanm	0:9b334a45a8ff	290	* @}
bogdanm	0:9b334a45a8ff	291	*/
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
bogdanm	0:9b334a45a8ff	294	* @{
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
bogdanm	0:9b334a45a8ff	297	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
bogdanm	0:9b334a45a8ff	298	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
bogdanm	0:9b334a45a8ff	299	/**
bogdanm	0:9b334a45a8ff	300	* @}
bogdanm	0:9b334a45a8ff	301	*/
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
bogdanm	0:9b334a45a8ff	304	* @{
bogdanm	0:9b334a45a8ff	305	*/
bogdanm	0:9b334a45a8ff	306	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
bogdanm	0:9b334a45a8ff	307	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
bogdanm	0:9b334a45a8ff	308	/**
bogdanm	0:9b334a45a8ff	309	* @}
bogdanm	0:9b334a45a8ff	310	*/
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
bogdanm	0:9b334a45a8ff	313	* @{
bogdanm	0:9b334a45a8ff	314	*/
bogdanm	0:9b334a45a8ff	315	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
bogdanm	0:9b334a45a8ff	316	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
bogdanm	0:9b334a45a8ff	317	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
bogdanm	0:9b334a45a8ff	318	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
bogdanm	0:9b334a45a8ff	319	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
bogdanm	0:9b334a45a8ff	320	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
bogdanm	0:9b334a45a8ff	321	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
bogdanm	0:9b334a45a8ff	322	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
bogdanm	0:9b334a45a8ff	323	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
bogdanm	0:9b334a45a8ff	324	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
bogdanm	0:9b334a45a8ff	325	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
bogdanm	0:9b334a45a8ff	326	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
bogdanm	0:9b334a45a8ff	327	/**
bogdanm	0:9b334a45a8ff	328	* @}
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm	0:9b334a45a8ff	332	* @{
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
bogdanm	0:9b334a45a8ff	335	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
bogdanm	0:9b334a45a8ff	336	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
bogdanm	0:9b334a45a8ff	337	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
bogdanm	0:9b334a45a8ff	338	/**
bogdanm	0:9b334a45a8ff	339	* @}
bogdanm	0:9b334a45a8ff	340	*/
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	0:9b334a45a8ff	343	* @{
bogdanm	0:9b334a45a8ff	344	*/
bogdanm	0:9b334a45a8ff	345	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
bogdanm	0:9b334a45a8ff	346	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
bogdanm	0:9b334a45a8ff	347	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
bogdanm	0:9b334a45a8ff	348	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
bogdanm	0:9b334a45a8ff	349	/**
bogdanm	0:9b334a45a8ff	350	* @}
bogdanm	0:9b334a45a8ff	351	*/
bogdanm	0:9b334a45a8ff	352
bogdanm	0:9b334a45a8ff	353	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm	0:9b334a45a8ff	354	* @{
bogdanm	0:9b334a45a8ff	355	*/
bogdanm	0:9b334a45a8ff	356	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
bogdanm	0:9b334a45a8ff	357	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
bogdanm	0:9b334a45a8ff	358	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
bogdanm	0:9b334a45a8ff	359	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	360	/**
bogdanm	0:9b334a45a8ff	361	* @}
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm	0:9b334a45a8ff	365	* @{
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	368	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	369	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	370	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	371	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	372	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	373	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	374	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	375	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	376	/**
bogdanm	0:9b334a45a8ff	377	* @}
bogdanm	0:9b334a45a8ff	378	*/
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
bogdanm	0:9b334a45a8ff	381	* @{
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	384	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	385	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	386	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	387	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	388	/**
bogdanm	0:9b334a45a8ff	389	* @}
bogdanm	0:9b334a45a8ff	390	*/
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm	0:9b334a45a8ff	393	* @{
bogdanm	0:9b334a45a8ff	394	*/
bogdanm	0:9b334a45a8ff	395	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	396	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	397	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
bogdanm	0:9b334a45a8ff	398	/**
bogdanm	0:9b334a45a8ff	399	* @}
bogdanm	0:9b334a45a8ff	400	*/
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	0:9b334a45a8ff	403	* @{
bogdanm	0:9b334a45a8ff	404	*/
bogdanm	0:9b334a45a8ff	405	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	406	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	0:9b334a45a8ff	407	/**
bogdanm	0:9b334a45a8ff	408	* @}
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
bogdanm	0:9b334a45a8ff	412	* @{
bogdanm	0:9b334a45a8ff	413	*/
bogdanm	0:9b334a45a8ff	414	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
bogdanm	0:9b334a45a8ff	415	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
bogdanm	0:9b334a45a8ff	416	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
bogdanm	0:9b334a45a8ff	417	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
bogdanm	0:9b334a45a8ff	418	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
bogdanm	0:9b334a45a8ff	419	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
bogdanm	0:9b334a45a8ff	420	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL /!< LSE selection as MCO1 source /
bogdanm	0:9b334a45a8ff	421	/**
bogdanm	0:9b334a45a8ff	422	* @}
bogdanm	0:9b334a45a8ff	423	*/
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
bogdanm	0:9b334a45a8ff	426	* @{
bogdanm	0:9b334a45a8ff	427	*/
bogdanm	0:9b334a45a8ff	428	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 /!< MCO not divided /
bogdanm	0:9b334a45a8ff	429	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 /!< MCO divided by 2 /
bogdanm	0:9b334a45a8ff	430	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 /!< MCO divided by 4 /
bogdanm	0:9b334a45a8ff	431	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 /!< MCO divided by 8 /
bogdanm	0:9b334a45a8ff	432	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 /!< MCO divided by 16 /
bogdanm	0:9b334a45a8ff	433	/**
bogdanm	0:9b334a45a8ff	434	* @}
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/** @defgroup RCC_Interrupt Interrupts
bogdanm	0:9b334a45a8ff	438	* @{
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440	#define RCC_IT_LSIRDY ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	441	#define RCC_IT_LSERDY ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	442	#define RCC_IT_MSIRDY ((uint32_t)0x00000004) /!< MSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	443	#define RCC_IT_HSIRDY ((uint32_t)0x00000008) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	444	#define RCC_IT_HSERDY ((uint32_t)0x00000010) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	445	#define RCC_IT_PLLRDY ((uint32_t)0x00000020) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	446	#define RCC_IT_PLLSAI1RDY ((uint32_t)0x00000040) /!< PLLSAI1 Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	447	#define RCC_IT_PLLSAI2RDY ((uint32_t)0x00000080) /!< PLLSAI2 Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	448	#define RCC_IT_CSS ((uint32_t)0x00000100) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	449	#define RCC_IT_LSECSS ((uint32_t)0x00000200) /!< LSE Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	450	/**
bogdanm	0:9b334a45a8ff	451	* @}
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/** @defgroup RCC_Flag Flags
bogdanm	0:9b334a45a8ff	455	* Elements values convention: 0XXYYYYYb
bogdanm	0:9b334a45a8ff	456	* - YYYYY : Flag position in the register
bogdanm	0:9b334a45a8ff	457	* - 0XX : Register index
bogdanm	0:9b334a45a8ff	458	* - 01: CR register
bogdanm	0:9b334a45a8ff	459	* - 10: BDCR register
bogdanm	0:9b334a45a8ff	460	* - 11: CSR register
bogdanm	0:9b334a45a8ff	461	* @{
bogdanm	0:9b334a45a8ff	462	*/
bogdanm	0:9b334a45a8ff	463	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	464	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
bogdanm	0:9b334a45a8ff	465	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
bogdanm	0:9b334a45a8ff	466	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
bogdanm	0:9b334a45a8ff	467	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
bogdanm	0:9b334a45a8ff	468	#define RCC_FLAG_PLLSAI1RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
bogdanm	0:9b334a45a8ff	469	#define RCC_FLAG_PLLSAI2RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	/* Flags in the BDCR register */
bogdanm	0:9b334a45a8ff	472	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
bogdanm	0:9b334a45a8ff	473	#define RCC_FLAG_LSECSSD ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	476	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
bogdanm	0:9b334a45a8ff	477	#define RCC_FLAG_RMVF ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
bogdanm	0:9b334a45a8ff	478	#define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
bogdanm	0:9b334a45a8ff	479	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
bogdanm	0:9b334a45a8ff	480	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	481	#define RCC_FLAG_BORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
bogdanm	0:9b334a45a8ff	482	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	483	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	484	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	485	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	486	/**
bogdanm	0:9b334a45a8ff	487	* @}
bogdanm	0:9b334a45a8ff	488	*/
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
bogdanm	0:9b334a45a8ff	491	* @{
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< LSE low drive capability /
bogdanm	0:9b334a45a8ff	494	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< LSE medium low drive capability /
bogdanm	0:9b334a45a8ff	495	/* Workaround implementation on medium low */
bogdanm	0:9b334a45a8ff	496	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< LSE medium high drive capability /
bogdanm	0:9b334a45a8ff	497	/* Workaround implementation on medium high */
bogdanm	0:9b334a45a8ff	498	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
bogdanm	0:9b334a45a8ff	499	/**
bogdanm	0:9b334a45a8ff	500	* @}
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
bogdanm	0:9b334a45a8ff	504	* @{
bogdanm	0:9b334a45a8ff	505	*/
bogdanm	0:9b334a45a8ff	506	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
bogdanm	0:9b334a45a8ff	507	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
bogdanm	0:9b334a45a8ff	508	/**
bogdanm	0:9b334a45a8ff	509	* @}
bogdanm	0:9b334a45a8ff	510	*/
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	/**
bogdanm	0:9b334a45a8ff	513	* @}
bogdanm	0:9b334a45a8ff	514	*/
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	519	* @{
bogdanm	0:9b334a45a8ff	520	*/
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	523	* @brief Enable or disable the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	524	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	525	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	526	* using it.
bogdanm	0:9b334a45a8ff	527	* @{
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	531	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	532	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
bogdanm	0:9b334a45a8ff	533	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	534	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
bogdanm	0:9b334a45a8ff	535	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	536	} while(0)
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	539	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	540	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
bogdanm	0:9b334a45a8ff	541	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	542	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
bogdanm	0:9b334a45a8ff	543	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	544	} while(0)
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	547	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
bogdanm	0:9b334a45a8ff	549	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
bogdanm	0:9b334a45a8ff	551	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	552	} while(0)
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	555	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	556	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
bogdanm	0:9b334a45a8ff	557	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	558	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
bogdanm	0:9b334a45a8ff	559	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	560	} while(0)
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	563	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	564	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
bogdanm	0:9b334a45a8ff	565	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	566	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
bogdanm	0:9b334a45a8ff	567	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	568	} while(0)
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
bogdanm	0:9b334a45a8ff	573
bogdanm	0:9b334a45a8ff	574	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/**
bogdanm	0:9b334a45a8ff	581	* @}
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	585	* @brief Enable or disable the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	586	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	587	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	588	* using it.
bogdanm	0:9b334a45a8ff	589	* @{
bogdanm	0:9b334a45a8ff	590	*/
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	593	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	594	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
bogdanm	0:9b334a45a8ff	595	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	596	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
bogdanm	0:9b334a45a8ff	597	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	598	} while(0)
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	601	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	602	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
bogdanm	0:9b334a45a8ff	603	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	604	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
bogdanm	0:9b334a45a8ff	605	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	606	} while(0)
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	609	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	610	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
bogdanm	0:9b334a45a8ff	611	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	612	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
bogdanm	0:9b334a45a8ff	613	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	614	} while(0)
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	617	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	618	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
bogdanm	0:9b334a45a8ff	619	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	620	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
bogdanm	0:9b334a45a8ff	621	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	622	} while(0)
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	625	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	626	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
bogdanm	0:9b334a45a8ff	627	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	628	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
bogdanm	0:9b334a45a8ff	629	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	630	} while(0)
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	633	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	634	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
bogdanm	0:9b334a45a8ff	635	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	636	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
bogdanm	0:9b334a45a8ff	637	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	638	} while(0)
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	641	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	642	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
bogdanm	0:9b334a45a8ff	643	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	644	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
bogdanm	0:9b334a45a8ff	645	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	646	} while(0)
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	649	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	650	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
bogdanm	0:9b334a45a8ff	651	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	652	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
bogdanm	0:9b334a45a8ff	653	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	654	} while(0)
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	657	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	658	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
bogdanm	0:9b334a45a8ff	659	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	660	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
bogdanm	0:9b334a45a8ff	661	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	662	} while(0)
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	665	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	666	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
bogdanm	0:9b334a45a8ff	667	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	668	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
bogdanm	0:9b334a45a8ff	669	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	670	} while(0)
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/**
bogdanm	0:9b334a45a8ff	693	* @}
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	697	* @brief Enable or disable the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	698	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	699	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	700	* using it.
bogdanm	0:9b334a45a8ff	701	* @{
bogdanm	0:9b334a45a8ff	702	*/
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	705	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	706	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
bogdanm	0:9b334a45a8ff	707	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	708	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
bogdanm	0:9b334a45a8ff	709	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	710	} while(0)
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	713	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	714	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
bogdanm	0:9b334a45a8ff	715	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	716	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
bogdanm	0:9b334a45a8ff	717	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	718	} while(0)
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/**
bogdanm	0:9b334a45a8ff	725	* @}
bogdanm	0:9b334a45a8ff	726	*/
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	729	* @brief Enable or disable the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	730	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	731	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	732	* using it.
bogdanm	0:9b334a45a8ff	733	* @{
bogdanm	0:9b334a45a8ff	734	*/
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	737	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	738	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
bogdanm	0:9b334a45a8ff	739	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	740	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
bogdanm	0:9b334a45a8ff	741	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	742	} while(0)
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	745	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	746	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
bogdanm	0:9b334a45a8ff	747	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	748	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
bogdanm	0:9b334a45a8ff	749	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	750	} while(0)
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	753	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	754	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
bogdanm	0:9b334a45a8ff	755	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	756	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
bogdanm	0:9b334a45a8ff	757	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	758	} while(0)
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	761	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	762	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
bogdanm	0:9b334a45a8ff	763	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	764	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
bogdanm	0:9b334a45a8ff	765	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	766	} while(0)
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	769	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	770	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
bogdanm	0:9b334a45a8ff	771	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	772	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
bogdanm	0:9b334a45a8ff	773	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	774	} while(0)
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	777	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	778	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
bogdanm	0:9b334a45a8ff	779	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	780	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
bogdanm	0:9b334a45a8ff	781	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	782	} while(0)
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	785	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	786	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
bogdanm	0:9b334a45a8ff	787	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	788	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
bogdanm	0:9b334a45a8ff	789	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	790	} while(0)
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	793	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	794	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
bogdanm	0:9b334a45a8ff	795	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	796	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
bogdanm	0:9b334a45a8ff	797	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	798	} while(0)
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	801	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	802	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
bogdanm	0:9b334a45a8ff	803	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	804	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
bogdanm	0:9b334a45a8ff	805	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	806	} while(0)
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	809	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	810	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
bogdanm	0:9b334a45a8ff	811	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	812	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
bogdanm	0:9b334a45a8ff	813	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	814	} while(0)
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	817	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	818	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
bogdanm	0:9b334a45a8ff	819	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	820	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
bogdanm	0:9b334a45a8ff	821	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	822	} while(0)
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	825	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	826	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
bogdanm	0:9b334a45a8ff	827	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	828	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
bogdanm	0:9b334a45a8ff	829	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	830	} while(0)
bogdanm	0:9b334a45a8ff	831
bogdanm	0:9b334a45a8ff	832	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	833	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	834	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
bogdanm	0:9b334a45a8ff	835	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	836	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
bogdanm	0:9b334a45a8ff	837	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	838	} while(0)
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	841	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	842	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
bogdanm	0:9b334a45a8ff	843	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	844	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
bogdanm	0:9b334a45a8ff	845	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	846	} while(0)
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	849	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	850	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
bogdanm	0:9b334a45a8ff	851	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	852	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
bogdanm	0:9b334a45a8ff	853	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	854	} while(0)
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	857	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	858	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
bogdanm	0:9b334a45a8ff	859	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	860	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
bogdanm	0:9b334a45a8ff	861	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	862	} while(0)
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	865	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	866	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
bogdanm	0:9b334a45a8ff	867	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	868	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
bogdanm	0:9b334a45a8ff	869	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	870	} while(0)
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	873	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	874	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
bogdanm	0:9b334a45a8ff	875	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	876	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
bogdanm	0:9b334a45a8ff	877	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	878	} while(0)
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	881	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	882	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
bogdanm	0:9b334a45a8ff	883	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	884	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
bogdanm	0:9b334a45a8ff	885	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	886	} while(0)
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	889	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	890	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
bogdanm	0:9b334a45a8ff	891	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	892	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
bogdanm	0:9b334a45a8ff	893	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	894	} while(0)
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	897	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	898	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
bogdanm	0:9b334a45a8ff	899	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	900	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
bogdanm	0:9b334a45a8ff	901	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	902	} while(0)
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	905	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	906	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
bogdanm	0:9b334a45a8ff	907	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	908	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
bogdanm	0:9b334a45a8ff	909	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	910	} while(0)
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	913	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	914	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
bogdanm	0:9b334a45a8ff	915	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	916	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
bogdanm	0:9b334a45a8ff	917	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	918	} while(0)
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	921	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	922	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
bogdanm	0:9b334a45a8ff	923	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	924	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
bogdanm	0:9b334a45a8ff	925	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	926	} while(0)
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
bogdanm	0:9b334a45a8ff	929
bogdanm	0:9b334a45a8ff	930	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
bogdanm	0:9b334a45a8ff	969
bogdanm	0:9b334a45a8ff	970	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	/**
bogdanm	0:9b334a45a8ff	977	* @}
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	981	* @brief Enable or disable the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	982	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	983	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	984	* using it.
bogdanm	0:9b334a45a8ff	985	* @{
bogdanm	0:9b334a45a8ff	986	*/
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	989	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	990	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
bogdanm	0:9b334a45a8ff	991	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	992	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
bogdanm	0:9b334a45a8ff	993	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	994	} while(0)
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	997	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	998	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
bogdanm	0:9b334a45a8ff	999	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1000	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
bogdanm	0:9b334a45a8ff	1001	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1002	} while(0)
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1005	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1006	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
bogdanm	0:9b334a45a8ff	1007	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1008	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
bogdanm	0:9b334a45a8ff	1009	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1010	} while(0)
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1013	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1014	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
bogdanm	0:9b334a45a8ff	1015	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1016	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
bogdanm	0:9b334a45a8ff	1017	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1018	} while(0)
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1021	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1022	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
bogdanm	0:9b334a45a8ff	1023	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1024	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
bogdanm	0:9b334a45a8ff	1025	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1026	} while(0)
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1029	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1030	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
bogdanm	0:9b334a45a8ff	1031	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1032	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
bogdanm	0:9b334a45a8ff	1033	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1034	} while(0)
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1037	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1038	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
bogdanm	0:9b334a45a8ff	1039	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1040	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
bogdanm	0:9b334a45a8ff	1041	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1042	} while(0)
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1046	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1047	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
bogdanm	0:9b334a45a8ff	1048	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1049	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
bogdanm	0:9b334a45a8ff	1050	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1051	} while(0)
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1054	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1055	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
bogdanm	0:9b334a45a8ff	1056	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1057	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
bogdanm	0:9b334a45a8ff	1058	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1059	} while(0)
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1062	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1063	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
bogdanm	0:9b334a45a8ff	1064	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1065	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
bogdanm	0:9b334a45a8ff	1066	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1067	} while(0)
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1070	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1071	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
bogdanm	0:9b334a45a8ff	1072	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1073	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
bogdanm	0:9b334a45a8ff	1074	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1075	} while(0)
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1078	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1079	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
bogdanm	0:9b334a45a8ff	1080	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1081	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
bogdanm	0:9b334a45a8ff	1082	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1083	} while(0)
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	#define __HAL_RCC_DFSDM_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1086	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1087	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
bogdanm	0:9b334a45a8ff	1088	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1089	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
bogdanm	0:9b334a45a8ff	1090	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1091	} while(0)
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	#define __HAL_RCC_DFSDM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN)
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/**
bogdanm	0:9b334a45a8ff	1118	* @}
bogdanm	0:9b334a45a8ff	1119	*/
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1122	* @brief Check whether the AHB1 peripheral clock is enabled or not.
bogdanm	0:9b334a45a8ff	1123	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1124	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1125	* using it.
bogdanm	0:9b334a45a8ff	1126	* @{
bogdanm	0:9b334a45a8ff	1127	*/
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	/**
bogdanm	0:9b334a45a8ff	1150	* @}
bogdanm	0:9b334a45a8ff	1151	*/
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1154	* @brief Check whether the AHB2 peripheral clock is enabled or not.
bogdanm	0:9b334a45a8ff	1155	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1156	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1157	* using it.
bogdanm	0:9b334a45a8ff	1158	* @{
bogdanm	0:9b334a45a8ff	1159	*/
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
bogdanm	0:9b334a45a8ff	1174
bogdanm	0:9b334a45a8ff	1175	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/**
bogdanm	0:9b334a45a8ff	1202	* @}
bogdanm	0:9b334a45a8ff	1203	*/
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1206	* @brief Check whether the AHB3 peripheral clock is enabled or not.
bogdanm	0:9b334a45a8ff	1207	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1208	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1209	* using it.
bogdanm	0:9b334a45a8ff	1210	* @{
bogdanm	0:9b334a45a8ff	1211	*/
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/**
bogdanm	0:9b334a45a8ff	1222	* @}
bogdanm	0:9b334a45a8ff	1223	*/
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1226	* @brief Check whether the APB1 peripheral clock is enabled or not.
bogdanm	0:9b334a45a8ff	1227	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1228	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1229	* using it.
bogdanm	0:9b334a45a8ff	1230	* @{
bogdanm	0:9b334a45a8ff	1231	*/
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/**
bogdanm	0:9b334a45a8ff	1330	* @}
bogdanm	0:9b334a45a8ff	1331	*/
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1334	* @brief Check whether the APB2 peripheral clock is enabled or not.
bogdanm	0:9b334a45a8ff	1335	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1336	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1337	* using it.
bogdanm	0:9b334a45a8ff	1338	* @{
bogdanm	0:9b334a45a8ff	1339	*/
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) != RESET)
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) == RESET)
bogdanm	0:9b334a45a8ff	1390
bogdanm	0:9b334a45a8ff	1391	/**
bogdanm	0:9b334a45a8ff	1392	* @}
bogdanm	0:9b334a45a8ff	1393	*/
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
bogdanm	0:9b334a45a8ff	1396	* @brief Force or release AHB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1397	* @{
bogdanm	0:9b334a45a8ff	1398	*/
bogdanm	0:9b334a45a8ff	1399	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000)
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
bogdanm	0:9b334a45a8ff	1416
bogdanm	0:9b334a45a8ff	1417	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	/**
bogdanm	0:9b334a45a8ff	1424	* @}
bogdanm	0:9b334a45a8ff	1425	*/
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
bogdanm	0:9b334a45a8ff	1428	* @brief Force or release AHB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1429	* @{
bogdanm	0:9b334a45a8ff	1430	*/
bogdanm	0:9b334a45a8ff	1431	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1432
bogdanm	0:9b334a45a8ff	1433	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000)
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
bogdanm	0:9b334a45a8ff	1458
bogdanm	0:9b334a45a8ff	1459	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/**
bogdanm	0:9b334a45a8ff	1476	* @}
bogdanm	0:9b334a45a8ff	1477	*/
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
bogdanm	0:9b334a45a8ff	1480	* @brief Force or release AHB3 peripheral reset.
bogdanm	0:9b334a45a8ff	1481	* @{
bogdanm	0:9b334a45a8ff	1482	*/
bogdanm	0:9b334a45a8ff	1483	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000)
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
bogdanm	0:9b334a45a8ff	1492
bogdanm	0:9b334a45a8ff	1493	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/**
bogdanm	0:9b334a45a8ff	1496	* @}
bogdanm	0:9b334a45a8ff	1497	*/
bogdanm	0:9b334a45a8ff	1498
bogdanm	0:9b334a45a8ff	1499	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
bogdanm	0:9b334a45a8ff	1500	* @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1501	* @{
bogdanm	0:9b334a45a8ff	1502	*/
bogdanm	0:9b334a45a8ff	1503	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
bogdanm	0:9b334a45a8ff	1514
bogdanm	0:9b334a45a8ff	1515	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
bogdanm	0:9b334a45a8ff	1516
bogdanm	0:9b334a45a8ff	1517	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
bogdanm	0:9b334a45a8ff	1520
bogdanm	0:9b334a45a8ff	1521	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000)
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
bogdanm	0:9b334a45a8ff	1576
bogdanm	0:9b334a45a8ff	1577	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
bogdanm	0:9b334a45a8ff	1592
bogdanm	0:9b334a45a8ff	1593	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
bogdanm	0:9b334a45a8ff	1594
bogdanm	0:9b334a45a8ff	1595	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	/**
bogdanm	0:9b334a45a8ff	1600	* @}
bogdanm	0:9b334a45a8ff	1601	*/
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
bogdanm	0:9b334a45a8ff	1604	* @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1605	* @{
bogdanm	0:9b334a45a8ff	1606	*/
bogdanm	0:9b334a45a8ff	1607	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
bogdanm	0:9b334a45a8ff	1620
bogdanm	0:9b334a45a8ff	1621	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
bogdanm	0:9b334a45a8ff	1622
bogdanm	0:9b334a45a8ff	1623	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
bogdanm	0:9b334a45a8ff	1626
bogdanm	0:9b334a45a8ff	1627	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	#define __HAL_RCC_DFSDM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000)
bogdanm	0:9b334a45a8ff	1634
bogdanm	0:9b334a45a8ff	1635	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
bogdanm	0:9b334a45a8ff	1640
bogdanm	0:9b334a45a8ff	1641	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
bogdanm	0:9b334a45a8ff	1642
bogdanm	0:9b334a45a8ff	1643	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
bogdanm	0:9b334a45a8ff	1646
bogdanm	0:9b334a45a8ff	1647	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
bogdanm	0:9b334a45a8ff	1650
bogdanm	0:9b334a45a8ff	1651	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	#define __HAL_RCC_DFSDM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	/**
bogdanm	0:9b334a45a8ff	1660	* @}
bogdanm	0:9b334a45a8ff	1661	*/
bogdanm	0:9b334a45a8ff	1662
bogdanm	0:9b334a45a8ff	1663	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1664	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1665	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1666	* power consumption.
bogdanm	0:9b334a45a8ff	1667	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1668	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1669	* @{
bogdanm	0:9b334a45a8ff	1670	*/
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
bogdanm	0:9b334a45a8ff	1675
bogdanm	0:9b334a45a8ff	1676	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
bogdanm	0:9b334a45a8ff	1683
bogdanm	0:9b334a45a8ff	1684	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
bogdanm	0:9b334a45a8ff	1691
bogdanm	0:9b334a45a8ff	1692	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/**
bogdanm	0:9b334a45a8ff	1697	* @}
bogdanm	0:9b334a45a8ff	1698	*/
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1701	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1702	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1703	* power consumption.
bogdanm	0:9b334a45a8ff	1704	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1705	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1706	* @{
bogdanm	0:9b334a45a8ff	1707	*/
bogdanm	0:9b334a45a8ff	1708
bogdanm	0:9b334a45a8ff	1709	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
bogdanm	0:9b334a45a8ff	1714
bogdanm	0:9b334a45a8ff	1715	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
bogdanm	0:9b334a45a8ff	1726
bogdanm	0:9b334a45a8ff	1727	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
bogdanm	0:9b334a45a8ff	1738
bogdanm	0:9b334a45a8ff	1739	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
bogdanm	0:9b334a45a8ff	1742
bogdanm	0:9b334a45a8ff	1743	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
bogdanm	0:9b334a45a8ff	1746
bogdanm	0:9b334a45a8ff	1747	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	/**
bogdanm	0:9b334a45a8ff	1754	* @}
bogdanm	0:9b334a45a8ff	1755	*/
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1758	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1759	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1760	* power consumption.
bogdanm	0:9b334a45a8ff	1761	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1762	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1763	* @{
bogdanm	0:9b334a45a8ff	1764	*/
bogdanm	0:9b334a45a8ff	1765
bogdanm	0:9b334a45a8ff	1766	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
bogdanm	0:9b334a45a8ff	1767
bogdanm	0:9b334a45a8ff	1768	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
bogdanm	0:9b334a45a8ff	1771
bogdanm	0:9b334a45a8ff	1772	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	/**
bogdanm	0:9b334a45a8ff	1775	* @}
bogdanm	0:9b334a45a8ff	1776	*/
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1779	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1781	* power consumption.
bogdanm	0:9b334a45a8ff	1782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1784	* @{
bogdanm	0:9b334a45a8ff	1785	*/
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
bogdanm	0:9b334a45a8ff	1792
bogdanm	0:9b334a45a8ff	1793	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
bogdanm	0:9b334a45a8ff	1794
bogdanm	0:9b334a45a8ff	1795	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
bogdanm	0:9b334a45a8ff	1798
bogdanm	0:9b334a45a8ff	1799	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
bogdanm	0:9b334a45a8ff	1810
bogdanm	0:9b334a45a8ff	1811	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
bogdanm	0:9b334a45a8ff	1816
bogdanm	0:9b334a45a8ff	1817	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
bogdanm	0:9b334a45a8ff	1818
bogdanm	0:9b334a45a8ff	1819	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
bogdanm	0:9b334a45a8ff	1824
bogdanm	0:9b334a45a8ff	1825	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
bogdanm	0:9b334a45a8ff	1826
bogdanm	0:9b334a45a8ff	1827	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
bogdanm	0:9b334a45a8ff	1828
bogdanm	0:9b334a45a8ff	1829	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
bogdanm	0:9b334a45a8ff	1832
bogdanm	0:9b334a45a8ff	1833	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
bogdanm	0:9b334a45a8ff	1838
bogdanm	0:9b334a45a8ff	1839	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
bogdanm	0:9b334a45a8ff	1842
bogdanm	0:9b334a45a8ff	1843	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
bogdanm	0:9b334a45a8ff	1848
bogdanm	0:9b334a45a8ff	1849	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
bogdanm	0:9b334a45a8ff	1850
bogdanm	0:9b334a45a8ff	1851	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
bogdanm	0:9b334a45a8ff	1854
bogdanm	0:9b334a45a8ff	1855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
bogdanm	0:9b334a45a8ff	1858
bogdanm	0:9b334a45a8ff	1859	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
bogdanm	0:9b334a45a8ff	1860
bogdanm	0:9b334a45a8ff	1861	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
bogdanm	0:9b334a45a8ff	1864
bogdanm	0:9b334a45a8ff	1865	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
bogdanm	0:9b334a45a8ff	1880
bogdanm	0:9b334a45a8ff	1881	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	/**
bogdanm	0:9b334a45a8ff	1884	* @}
bogdanm	0:9b334a45a8ff	1885	*/
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1888	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1889	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1890	* power consumption.
bogdanm	0:9b334a45a8ff	1891	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1892	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1893	* @{
bogdanm	0:9b334a45a8ff	1894	*/
bogdanm	0:9b334a45a8ff	1895
bogdanm	0:9b334a45a8ff	1896	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
bogdanm	0:9b334a45a8ff	1897
bogdanm	0:9b334a45a8ff	1898	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
bogdanm	0:9b334a45a8ff	1899
bogdanm	0:9b334a45a8ff	1900	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
bogdanm	0:9b334a45a8ff	1905
bogdanm	0:9b334a45a8ff	1906	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
bogdanm	0:9b334a45a8ff	1909
bogdanm	0:9b334a45a8ff	1910	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
bogdanm	0:9b334a45a8ff	1915
bogdanm	0:9b334a45a8ff	1916	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
bogdanm	0:9b334a45a8ff	1919
bogdanm	0:9b334a45a8ff	1920	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
bogdanm	0:9b334a45a8ff	1923
bogdanm	0:9b334a45a8ff	1924	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
bogdanm	0:9b334a45a8ff	1927
bogdanm	0:9b334a45a8ff	1928	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
bogdanm	0:9b334a45a8ff	1933
bogdanm	0:9b334a45a8ff	1934	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
bogdanm	0:9b334a45a8ff	1939
bogdanm	0:9b334a45a8ff	1940	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
bogdanm	0:9b334a45a8ff	1943
bogdanm	0:9b334a45a8ff	1944	/**
bogdanm	0:9b334a45a8ff	1945	* @}
bogdanm	0:9b334a45a8ff	1946	*/
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1949	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	1950	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1951	* power consumption.
bogdanm	0:9b334a45a8ff	1952	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1953	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1954	* @{
bogdanm	0:9b334a45a8ff	1955	*/
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	1958
bogdanm	0:9b334a45a8ff	1959	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	1960
bogdanm	0:9b334a45a8ff	1961	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
bogdanm	0:9b334a45a8ff	1962
bogdanm	0:9b334a45a8ff	1963	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	1964
bogdanm	0:9b334a45a8ff	1965	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	1970
bogdanm	0:9b334a45a8ff	1971	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	1972
bogdanm	0:9b334a45a8ff	1973	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
bogdanm	0:9b334a45a8ff	1978
bogdanm	0:9b334a45a8ff	1979	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	/**
bogdanm	0:9b334a45a8ff	1982	* @}
bogdanm	0:9b334a45a8ff	1983	*/
bogdanm	0:9b334a45a8ff	1984
bogdanm	0:9b334a45a8ff	1985	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	1986	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	1987	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1988	* power consumption.
bogdanm	0:9b334a45a8ff	1989	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1990	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1991	* @{
bogdanm	0:9b334a45a8ff	1992	*/
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
bogdanm	0:9b334a45a8ff	1995
bogdanm	0:9b334a45a8ff	1996	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
bogdanm	0:9b334a45a8ff	1997
bogdanm	0:9b334a45a8ff	1998	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
bogdanm	0:9b334a45a8ff	1999
bogdanm	0:9b334a45a8ff	2000	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2001
bogdanm	0:9b334a45a8ff	2002	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2005
bogdanm	0:9b334a45a8ff	2006	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2007
bogdanm	0:9b334a45a8ff	2008	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2009
bogdanm	0:9b334a45a8ff	2010	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2011
bogdanm	0:9b334a45a8ff	2012	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2019
bogdanm	0:9b334a45a8ff	2020	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2021
bogdanm	0:9b334a45a8ff	2022	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
bogdanm	0:9b334a45a8ff	2025
bogdanm	0:9b334a45a8ff	2026	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2031
bogdanm	0:9b334a45a8ff	2032	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2033
bogdanm	0:9b334a45a8ff	2034	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2035
bogdanm	0:9b334a45a8ff	2036	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2037
bogdanm	0:9b334a45a8ff	2038	/**
bogdanm	0:9b334a45a8ff	2039	* @}
bogdanm	0:9b334a45a8ff	2040	*/
bogdanm	0:9b334a45a8ff	2041
bogdanm	0:9b334a45a8ff	2042	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	2043	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	2044	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	2045	* power consumption.
bogdanm	0:9b334a45a8ff	2046	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	2047	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	2048	* @{
bogdanm	0:9b334a45a8ff	2049	*/
bogdanm	0:9b334a45a8ff	2050
bogdanm	0:9b334a45a8ff	2051	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2058
bogdanm	0:9b334a45a8ff	2059	/**
bogdanm	0:9b334a45a8ff	2060	* @}
bogdanm	0:9b334a45a8ff	2061	*/
bogdanm	0:9b334a45a8ff	2062
bogdanm	0:9b334a45a8ff	2063	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	2064	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	2065	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	2066	* power consumption.
bogdanm	0:9b334a45a8ff	2067	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	2068	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	2069	* @{
bogdanm	0:9b334a45a8ff	2070	*/
bogdanm	0:9b334a45a8ff	2071
bogdanm	0:9b334a45a8ff	2072	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2073
bogdanm	0:9b334a45a8ff	2074	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2075
bogdanm	0:9b334a45a8ff	2076	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2077
bogdanm	0:9b334a45a8ff	2078	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2079
bogdanm	0:9b334a45a8ff	2080	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2081
bogdanm	0:9b334a45a8ff	2082	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2085
bogdanm	0:9b334a45a8ff	2086	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2087
bogdanm	0:9b334a45a8ff	2088	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2091
bogdanm	0:9b334a45a8ff	2092	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2095
bogdanm	0:9b334a45a8ff	2096	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2097
bogdanm	0:9b334a45a8ff	2098	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2099
bogdanm	0:9b334a45a8ff	2100	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2101
bogdanm	0:9b334a45a8ff	2102	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2103
bogdanm	0:9b334a45a8ff	2104	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2107
bogdanm	0:9b334a45a8ff	2108	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2109
bogdanm	0:9b334a45a8ff	2110	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2111
bogdanm	0:9b334a45a8ff	2112	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2115
bogdanm	0:9b334a45a8ff	2116	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2117
bogdanm	0:9b334a45a8ff	2118	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2121
bogdanm	0:9b334a45a8ff	2122	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2123
bogdanm	0:9b334a45a8ff	2124	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2125
bogdanm	0:9b334a45a8ff	2126	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2127
bogdanm	0:9b334a45a8ff	2128	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2133
bogdanm	0:9b334a45a8ff	2134	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2137
bogdanm	0:9b334a45a8ff	2138	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2139
bogdanm	0:9b334a45a8ff	2140	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2141
bogdanm	0:9b334a45a8ff	2142	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2143
bogdanm	0:9b334a45a8ff	2144	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2145
bogdanm	0:9b334a45a8ff	2146	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2151
bogdanm	0:9b334a45a8ff	2152	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2159
bogdanm	0:9b334a45a8ff	2160	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2161
bogdanm	0:9b334a45a8ff	2162	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2163
bogdanm	0:9b334a45a8ff	2164	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2167
bogdanm	0:9b334a45a8ff	2168	/**
bogdanm	0:9b334a45a8ff	2169	* @}
bogdanm	0:9b334a45a8ff	2170	*/
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
bogdanm	0:9b334a45a8ff	2173	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	2174	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	2175	* power consumption.
bogdanm	0:9b334a45a8ff	2176	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	2177	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	2178	* @{
bogdanm	0:9b334a45a8ff	2179	*/
bogdanm	0:9b334a45a8ff	2180
bogdanm	0:9b334a45a8ff	2181	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2184
bogdanm	0:9b334a45a8ff	2185	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2186
bogdanm	0:9b334a45a8ff	2187	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2188
bogdanm	0:9b334a45a8ff	2189	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2192
bogdanm	0:9b334a45a8ff	2193	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2194
bogdanm	0:9b334a45a8ff	2195	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2198
bogdanm	0:9b334a45a8ff	2199	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
bogdanm	0:9b334a45a8ff	2202
bogdanm	0:9b334a45a8ff	2203	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) != RESET)
bogdanm	0:9b334a45a8ff	2204
bogdanm	0:9b334a45a8ff	2205	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2206
bogdanm	0:9b334a45a8ff	2207	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2210
bogdanm	0:9b334a45a8ff	2211	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2212
bogdanm	0:9b334a45a8ff	2213	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2214
bogdanm	0:9b334a45a8ff	2215	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2216
bogdanm	0:9b334a45a8ff	2217	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2218
bogdanm	0:9b334a45a8ff	2219	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2222
bogdanm	0:9b334a45a8ff	2223	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2224
bogdanm	0:9b334a45a8ff	2225	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) == RESET)
bogdanm	0:9b334a45a8ff	2228
bogdanm	0:9b334a45a8ff	2229	/**
bogdanm	0:9b334a45a8ff	2230	* @}
bogdanm	0:9b334a45a8ff	2231	*/
bogdanm	0:9b334a45a8ff	2232
bogdanm	0:9b334a45a8ff	2233	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
bogdanm	0:9b334a45a8ff	2234	* @{
bogdanm	0:9b334a45a8ff	2235	*/
bogdanm	0:9b334a45a8ff	2236
bogdanm	0:9b334a45a8ff	2237	/** @brief Macros to force or release the Backup domain reset.
bogdanm	0:9b334a45a8ff	2238	* @note This function resets the RTC peripheral (including the backup registers)
bogdanm	0:9b334a45a8ff	2239	* and the RTC clock source selection in RCC_CSR register.
bogdanm	0:9b334a45a8ff	2240	* @note The BKPSRAM is not affected by this reset.
bogdanm	0:9b334a45a8ff	2241	* @retval None
bogdanm	0:9b334a45a8ff	2242	*/
bogdanm	0:9b334a45a8ff	2243	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/**
bogdanm	0:9b334a45a8ff	2248	* @}
bogdanm	0:9b334a45a8ff	2249	*/
bogdanm	0:9b334a45a8ff	2250
bogdanm	0:9b334a45a8ff	2251	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm	0:9b334a45a8ff	2252	* @{
bogdanm	0:9b334a45a8ff	2253	*/
bogdanm	0:9b334a45a8ff	2254
bogdanm	0:9b334a45a8ff	2255	/** @brief Macros to enable or disable the RTC clock.
bogdanm	0:9b334a45a8ff	2256	* @note As the RTC is in the Backup domain and write access is denied to
bogdanm	0:9b334a45a8ff	2257	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	2258	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
bogdanm	0:9b334a45a8ff	2259	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	2260	* @note These macros must be used after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	2261	* @retval None
bogdanm	0:9b334a45a8ff	2262	*/
bogdanm	0:9b334a45a8ff	2263	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	0:9b334a45a8ff	2266
bogdanm	0:9b334a45a8ff	2267	/**
bogdanm	0:9b334a45a8ff	2268	* @}
bogdanm	0:9b334a45a8ff	2269	*/
bogdanm	0:9b334a45a8ff	2270
bogdanm	0:9b334a45a8ff	2271	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	2272	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2273	* It is used (enabled by hardware) as system clock source after startup
bogdanm	0:9b334a45a8ff	2274	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	0:9b334a45a8ff	2275	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	0:9b334a45a8ff	2276	* Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	2277	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	2278	* you have to select another source of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	2279	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	0:9b334a45a8ff	2280	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	0:9b334a45a8ff	2281	* system clock source.
bogdanm	0:9b334a45a8ff	2282	* This parameter can be: ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	2283	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	2284	* clock cycles.
bogdanm	0:9b334a45a8ff	2285	* @retval None
bogdanm	0:9b334a45a8ff	2286	*/
bogdanm	0:9b334a45a8ff	2287	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	2288
bogdanm	0:9b334a45a8ff	2289	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	2290
bogdanm	0:9b334a45a8ff	2291	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	2292	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	2293	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	0:9b334a45a8ff	2294	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
bogdanm	0:9b334a45a8ff	2295	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	2296	* This parameter must be a number between 0 and 31.
bogdanm	0:9b334a45a8ff	2297	* @retval None
bogdanm	0:9b334a45a8ff	2298	*/
bogdanm	0:9b334a45a8ff	2299	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
bogdanm	0:9b334a45a8ff	2300	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
bogdanm	0:9b334a45a8ff	2301
bogdanm	0:9b334a45a8ff	2302	/**
bogdanm	0:9b334a45a8ff	2303	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
bogdanm	0:9b334a45a8ff	2304	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
bogdanm	0:9b334a45a8ff	2305	* @note The enable of this function has not effect on the HSION bit.
bogdanm	0:9b334a45a8ff	2306	* This parameter can be: ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	2307	* @retval None
bogdanm	0:9b334a45a8ff	2308	*/
bogdanm	0:9b334a45a8ff	2309	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
bogdanm	0:9b334a45a8ff	2312
bogdanm	0:9b334a45a8ff	2313	/**
bogdanm	0:9b334a45a8ff	2314	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
bogdanm	0:9b334a45a8ff	2315	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
bogdanm	0:9b334a45a8ff	2316	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
bogdanm	0:9b334a45a8ff	2317	* speed because of the HSI startup time.
bogdanm	0:9b334a45a8ff	2318	* @note The enable of this function has not effect on the HSION bit.
bogdanm	0:9b334a45a8ff	2319	* This parameter can be: ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	2320	* @retval None
bogdanm	0:9b334a45a8ff	2321	*/
bogdanm	0:9b334a45a8ff	2322	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	2325
bogdanm	0:9b334a45a8ff	2326	/**
bogdanm	0:9b334a45a8ff	2327	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
bogdanm	0:9b334a45a8ff	2328	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2329	* It is used (enabled by hardware) as system clock source after
bogdanm	0:9b334a45a8ff	2330	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
bogdanm	0:9b334a45a8ff	2331	* of failure of the HSE used directly or indirectly as system clock
bogdanm	0:9b334a45a8ff	2332	* (if the Clock Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	2333	* @note MSI can not be stopped if it is used as system clock source.
bogdanm	0:9b334a45a8ff	2334	* In this case, you have to select another source of the system
bogdanm	0:9b334a45a8ff	2335	* clock then stop the MSI.
bogdanm	0:9b334a45a8ff	2336	* @note After enabling the MSI, the application software should wait on
bogdanm	0:9b334a45a8ff	2337	* MSIRDY flag to be set indicating that MSI clock is stable and can
bogdanm	0:9b334a45a8ff	2338	* be used as system clock source.
bogdanm	0:9b334a45a8ff	2339	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
bogdanm	0:9b334a45a8ff	2340	* clock cycles.
bogdanm	0:9b334a45a8ff	2341	* @retval None
bogdanm	0:9b334a45a8ff	2342	*/
bogdanm	0:9b334a45a8ff	2343	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	2344
bogdanm	0:9b334a45a8ff	2345	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	2346
bogdanm	0:9b334a45a8ff	2347	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
bogdanm	0:9b334a45a8ff	2348	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	2349	* and temperature that influence the frequency of the internal MSI RC.
bogdanm	0:9b334a45a8ff	2350	* Refer to the Application Note AN3300 for more details on how to
bogdanm	0:9b334a45a8ff	2351	* calibrate the MSI.
bogdanm	0:9b334a45a8ff	2352	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
bogdanm	0:9b334a45a8ff	2353	* (default is RCC_MSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	2354	* This parameter must be a number between 0 and 255.
bogdanm	0:9b334a45a8ff	2355	* @retval None
bogdanm	0:9b334a45a8ff	2356	*/
bogdanm	0:9b334a45a8ff	2357	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
bogdanm	0:9b334a45a8ff	2358	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
bogdanm	0:9b334a45a8ff	2359
bogdanm	0:9b334a45a8ff	2360	/**
bogdanm	0:9b334a45a8ff	2361	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
bogdanm	0:9b334a45a8ff	2362	* @note After restart from Reset , the MSI clock is around 4 MHz.
bogdanm	0:9b334a45a8ff	2363	* After stop the startup clock can be MSI (at any of its possible
bogdanm	0:9b334a45a8ff	2364	* frequencies, the one that was used before entering stop mode) or HSI.
bogdanm	0:9b334a45a8ff	2365	* After Standby its frequency can be selected between 4 possible values
bogdanm	0:9b334a45a8ff	2366	* (1, 2, 4 or 8 MHz).
bogdanm	0:9b334a45a8ff	2367	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
bogdanm	0:9b334a45a8ff	2368	* (MSIRDY=1).
bogdanm	0:9b334a45a8ff	2369	* @note The MSI clock range after reset can be modified on the fly.
bogdanm	0:9b334a45a8ff	2370	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
bogdanm	0:9b334a45a8ff	2371	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	2372	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
bogdanm	0:9b334a45a8ff	2373	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
bogdanm	0:9b334a45a8ff	2374	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
bogdanm	0:9b334a45a8ff	2375	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
bogdanm	0:9b334a45a8ff	2376	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
bogdanm	0:9b334a45a8ff	2377	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
bogdanm	0:9b334a45a8ff	2378	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
bogdanm	0:9b334a45a8ff	2379	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
bogdanm	0:9b334a45a8ff	2380	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
bogdanm	0:9b334a45a8ff	2381	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
bogdanm	0:9b334a45a8ff	2382	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
bogdanm	0:9b334a45a8ff	2383	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
bogdanm	0:9b334a45a8ff	2384	* @retval None
bogdanm	0:9b334a45a8ff	2385	*/
bogdanm	0:9b334a45a8ff	2386	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
bogdanm	0:9b334a45a8ff	2387	do { \
bogdanm	0:9b334a45a8ff	2388	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
bogdanm	0:9b334a45a8ff	2389	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
bogdanm	0:9b334a45a8ff	2390	} while(0)
bogdanm	0:9b334a45a8ff	2391
bogdanm	0:9b334a45a8ff	2392	/**
bogdanm	0:9b334a45a8ff	2393	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
bogdanm	0:9b334a45a8ff	2394	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
bogdanm	0:9b334a45a8ff	2395	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
bogdanm	0:9b334a45a8ff	2396	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	2397	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
bogdanm	0:9b334a45a8ff	2398	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
bogdanm	0:9b334a45a8ff	2399	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
bogdanm	0:9b334a45a8ff	2400	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
bogdanm	0:9b334a45a8ff	2401	* @retval None
bogdanm	0:9b334a45a8ff	2402	*/
bogdanm	0:9b334a45a8ff	2403	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
bogdanm	0:9b334a45a8ff	2404	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
bogdanm	0:9b334a45a8ff	2405
bogdanm	0:9b334a45a8ff	2406	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
bogdanm	0:9b334a45a8ff	2407	* @retval MSI clock range.
bogdanm	0:9b334a45a8ff	2408	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	2409	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
bogdanm	0:9b334a45a8ff	2410	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
bogdanm	0:9b334a45a8ff	2411	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
bogdanm	0:9b334a45a8ff	2412	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
bogdanm	0:9b334a45a8ff	2413	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
bogdanm	0:9b334a45a8ff	2414	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
bogdanm	0:9b334a45a8ff	2415	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
bogdanm	0:9b334a45a8ff	2416	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
bogdanm	0:9b334a45a8ff	2417	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
bogdanm	0:9b334a45a8ff	2418	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
bogdanm	0:9b334a45a8ff	2419	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
bogdanm	0:9b334a45a8ff	2420	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
bogdanm	0:9b334a45a8ff	2421	*/
bogdanm	0:9b334a45a8ff	2422	#define __HAL_RCC_GET_MSI_RANGE() \
bogdanm	0:9b334a45a8ff	2423	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
bogdanm	0:9b334a45a8ff	2424	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
bogdanm	0:9b334a45a8ff	2425	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
bogdanm	0:9b334a45a8ff	2426
bogdanm	0:9b334a45a8ff	2427	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	2428	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	2429	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	2430	* be used to clock the IWDG and/or the RTC.
bogdanm	0:9b334a45a8ff	2431	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	2432	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	2433	* clock cycles.
bogdanm	0:9b334a45a8ff	2434	* @retval None
bogdanm	0:9b334a45a8ff	2435	*/
bogdanm	0:9b334a45a8ff	2436	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	2437
bogdanm	0:9b334a45a8ff	2438	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	2439
bogdanm	0:9b334a45a8ff	2440	/**
bogdanm	0:9b334a45a8ff	2441	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	0:9b334a45a8ff	2442	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
bogdanm	0:9b334a45a8ff	2443	* supported by this macro. User should request a transition to HSE Off
bogdanm	0:9b334a45a8ff	2444	* first and then HSE On or HSE Bypass.
bogdanm	0:9b334a45a8ff	2445	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	2446	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	2447	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	2448	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	2449	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	2450	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	2451	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2452	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	0:9b334a45a8ff	2453	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	2454	* function.
bogdanm	0:9b334a45a8ff	2455	* @param __STATE__: specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	2456	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2457	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	2458	* 6 HSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	2459	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm	0:9b334a45a8ff	2460	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	2461	* @retval None
bogdanm	0:9b334a45a8ff	2462	*/
bogdanm	0:9b334a45a8ff	2463	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	2464	do { \
bogdanm	0:9b334a45a8ff	2465	if((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	2466	{ \
bogdanm	0:9b334a45a8ff	2467	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	2468	} \
bogdanm	0:9b334a45a8ff	2469	else if((__STATE__) == RCC_HSE_BYPASS) \
bogdanm	0:9b334a45a8ff	2470	{ \
bogdanm	0:9b334a45a8ff	2471	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	2472	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	2473	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	2474	} \
bogdanm	0:9b334a45a8ff	2475	else \
bogdanm	0:9b334a45a8ff	2476	{ \
bogdanm	0:9b334a45a8ff	2477	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	2478	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	2479	} \
bogdanm	0:9b334a45a8ff	2480	} while(0)
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/**
bogdanm	0:9b334a45a8ff	2483	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	0:9b334a45a8ff	2484	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
bogdanm	0:9b334a45a8ff	2485	* supported by this macro. User should request a transition to LSE Off
bogdanm	0:9b334a45a8ff	2486	* first and then LSE On or LSE Bypass.
bogdanm	0:9b334a45a8ff	2487	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	0:9b334a45a8ff	2488	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	2489	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	0:9b334a45a8ff	2490	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	2491	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	0:9b334a45a8ff	2492	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	0:9b334a45a8ff	2493	* is stable and can be used to clock the RTC.
bogdanm	0:9b334a45a8ff	2494	* @param __STATE__: specifies the new state of the LSE.
bogdanm	0:9b334a45a8ff	2495	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2496	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	0:9b334a45a8ff	2497	* 6 LSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	2498	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	0:9b334a45a8ff	2499	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	2500	* @retval None
bogdanm	0:9b334a45a8ff	2501	*/
bogdanm	0:9b334a45a8ff	2502	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	2503	do { \
bogdanm	0:9b334a45a8ff	2504	if((__STATE__) == RCC_LSE_ON) \
bogdanm	0:9b334a45a8ff	2505	{ \
bogdanm	0:9b334a45a8ff	2506	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	2507	} \
bogdanm	0:9b334a45a8ff	2508	else if((__STATE__) == RCC_LSE_OFF) \
bogdanm	0:9b334a45a8ff	2509	{ \
bogdanm	0:9b334a45a8ff	2510	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	2511	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	2512	} \
bogdanm	0:9b334a45a8ff	2513	else if((__STATE__) == RCC_LSE_BYPASS) \
bogdanm	0:9b334a45a8ff	2514	{ \
bogdanm	0:9b334a45a8ff	2515	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	2516	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	2517	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	2518	} \
bogdanm	0:9b334a45a8ff	2519	else \
bogdanm	0:9b334a45a8ff	2520	{ \
bogdanm	0:9b334a45a8ff	2521	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	2522	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	2523	} \
bogdanm	0:9b334a45a8ff	2524	} while(0)
bogdanm	0:9b334a45a8ff	2525
bogdanm	0:9b334a45a8ff	2526	/** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm	0:9b334a45a8ff	2527	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	0:9b334a45a8ff	2528	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	2529	* access using the Power Backup Access macro before to configure
bogdanm	0:9b334a45a8ff	2530	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	2531	* @note Once the RTC clock is configured it cannot be changed unless the
bogdanm	0:9b334a45a8ff	2532	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	0:9b334a45a8ff	2533	* a Power On Reset (POR).
bogdanm	0:9b334a45a8ff	2534	*
bogdanm	0:9b334a45a8ff	2535	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	2536	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2537	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm	0:9b334a45a8ff	2538	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm	0:9b334a45a8ff	2539	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
bogdanm	0:9b334a45a8ff	2540	*
bogdanm	0:9b334a45a8ff	2541	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	2542	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	2543	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	0:9b334a45a8ff	2544	* cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2545	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	0:9b334a45a8ff	2546	* RTC clock source).
bogdanm	0:9b334a45a8ff	2547	* @retval None
bogdanm	0:9b334a45a8ff	2548	*/
bogdanm	0:9b334a45a8ff	2549	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2550	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2551
bogdanm	0:9b334a45a8ff	2552
bogdanm	0:9b334a45a8ff	2553	/** @brief Macro to get the RTC clock source.
bogdanm	0:9b334a45a8ff	2554	* @retval The returned value can be one of the following:
bogdanm	0:9b334a45a8ff	2555	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm	0:9b334a45a8ff	2556	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm	0:9b334a45a8ff	2557	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
bogdanm	0:9b334a45a8ff	2558	*/
bogdanm	0:9b334a45a8ff	2559	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
bogdanm	0:9b334a45a8ff	2560
bogdanm	0:9b334a45a8ff	2561	/** @brief Macros to enable or disable the main PLL.
bogdanm	0:9b334a45a8ff	2562	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	2563	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	2564	* be used as system clock source.
bogdanm	0:9b334a45a8ff	2565	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	2566	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2567	* @retval None
bogdanm	0:9b334a45a8ff	2568	*/
bogdanm	0:9b334a45a8ff	2569	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	2572
bogdanm	0:9b334a45a8ff	2573	/** @brief Macro to configure the PLL clock source.
bogdanm	0:9b334a45a8ff	2574	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	2575	* @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	2576	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2577	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2578	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2579	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2580	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2581	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
bogdanm	0:9b334a45a8ff	2582	* @retval None
bogdanm	0:9b334a45a8ff	2583	*
bogdanm	0:9b334a45a8ff	2584	*/
bogdanm	0:9b334a45a8ff	2585	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
bogdanm	0:9b334a45a8ff	2586	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	/** @brief Macro to configure the PLL multiplication factor.
bogdanm	0:9b334a45a8ff	2589	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	2590	* @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	2591	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
bogdanm	0:9b334a45a8ff	2592	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2593	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2594	* of 16 MHz to limit PLL jitter.
bogdanm	0:9b334a45a8ff	2595	* @retval None
bogdanm	0:9b334a45a8ff	2596	*
bogdanm	0:9b334a45a8ff	2597	*/
bogdanm	0:9b334a45a8ff	2598	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
bogdanm	0:9b334a45a8ff	2599	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
bogdanm	0:9b334a45a8ff	2600
bogdanm	0:9b334a45a8ff	2601	/**
bogdanm	0:9b334a45a8ff	2602	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	2603	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	2604	*
bogdanm	0:9b334a45a8ff	2605	* @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	2606	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2607	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2608	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2609	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2610	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2611	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
bogdanm	0:9b334a45a8ff	2612	*
bogdanm	0:9b334a45a8ff	2613	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
bogdanm	0:9b334a45a8ff	2614	* This parameter must be a number between 1 and 8.
bogdanm	0:9b334a45a8ff	2615	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2616	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2617	* of 16 MHz to limit PLL jitter.
bogdanm	0:9b334a45a8ff	2618	*
bogdanm	0:9b334a45a8ff	2619	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
bogdanm	0:9b334a45a8ff	2620	* This parameter must be a number between 8 and 86.
bogdanm	0:9b334a45a8ff	2621	* @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2622	* output frequency is between 64 and 344 MHz.
bogdanm	0:9b334a45a8ff	2623	*
bogdanm	0:9b334a45a8ff	2624	* @param __PLLP__: specifies the division factor for SAI clock.
bogdanm	0:9b334a45a8ff	2625	* This parameter must be a number in the range (7 or 17).
bogdanm	0:9b334a45a8ff	2626	*
bogdanm	0:9b334a45a8ff	2627	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
bogdanm	0:9b334a45a8ff	2628	* This parameter must be in the range (2, 4, 6 or 8).
bogdanm	0:9b334a45a8ff	2629	* @note If the USB OTG FS is used in your application, you have to set the
bogdanm	0:9b334a45a8ff	2630	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm	0:9b334a45a8ff	2631	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm	0:9b334a45a8ff	2632	* correctly.
bogdanm	0:9b334a45a8ff	2633	* @param __PLLR__: specifies the division factor for the main system clock.
bogdanm	0:9b334a45a8ff	2634	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
bogdanm	0:9b334a45a8ff	2635	* This parameter must be in the range (2, 4, 6 or 8).
bogdanm	0:9b334a45a8ff	2636	* @retval None
bogdanm	0:9b334a45a8ff	2637	*/
bogdanm	0:9b334a45a8ff	2638	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
bogdanm	0:9b334a45a8ff	2639	(RCC->PLLCFGR = (((__PLLM__) - 1) << 4U) \| ((__PLLN__) << 8U) \| (((__PLLP__) >> 4U ) << 17U) \| \
bogdanm	0:9b334a45a8ff	2640	(__PLLSOURCE__) \| ((((__PLLQ__) >> 1U) - 1) << 21U) \| ((((__PLLR__) >> 1U) - 1) << 25U))
bogdanm	0:9b334a45a8ff	2641
bogdanm	0:9b334a45a8ff	2642	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	0:9b334a45a8ff	2643	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	0:9b334a45a8ff	2644	* of the following:
bogdanm	0:9b334a45a8ff	2645	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	2646	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	2647	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	2648	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	2649	*/
bogdanm	0:9b334a45a8ff	2650	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm	0:9b334a45a8ff	2651
bogdanm	0:9b334a45a8ff	2652	/**
bogdanm	0:9b334a45a8ff	2653	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
bogdanm	0:9b334a45a8ff	2654	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
bogdanm	0:9b334a45a8ff	2655	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
bogdanm	0:9b334a45a8ff	2656	* be stopped if used as System Clock.
bogdanm	0:9b334a45a8ff	2657	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
bogdanm	0:9b334a45a8ff	2658	* This parameter can be one or a combination of the following values:
bogdanm	0:9b334a45a8ff	2659	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
bogdanm	0:9b334a45a8ff	2660	* high-quality audio performance on SAI interface in case.
bogdanm	0:9b334a45a8ff	2661	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
bogdanm	0:9b334a45a8ff	2662	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
bogdanm	0:9b334a45a8ff	2663	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
bogdanm	0:9b334a45a8ff	2664	* @retval None
bogdanm	0:9b334a45a8ff	2665	*/
bogdanm	0:9b334a45a8ff	2666	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
bogdanm	0:9b334a45a8ff	2667
bogdanm	0:9b334a45a8ff	2668	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	/**
bogdanm	0:9b334a45a8ff	2671	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
bogdanm	0:9b334a45a8ff	2672	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
bogdanm	0:9b334a45a8ff	2673	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2674	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
bogdanm	0:9b334a45a8ff	2675	* high-quality audio performance on SAI interface in case.
bogdanm	0:9b334a45a8ff	2676	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
bogdanm	0:9b334a45a8ff	2677	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
bogdanm	0:9b334a45a8ff	2678	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
bogdanm	0:9b334a45a8ff	2679	* @retval SET / RESET
bogdanm	0:9b334a45a8ff	2680	*/
bogdanm	0:9b334a45a8ff	2681	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
bogdanm	0:9b334a45a8ff	2682
bogdanm	0:9b334a45a8ff	2683	/**
bogdanm	0:9b334a45a8ff	2684	* @brief Macro to configure the system clock source.
bogdanm	0:9b334a45a8ff	2685	* @param __SYSCLKSOURCE__: specifies the system clock source.
bogdanm	0:9b334a45a8ff	2686	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2687	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	2688	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	2689	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	2690	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
bogdanm	0:9b334a45a8ff	2691	* @retval None
bogdanm	0:9b334a45a8ff	2692	*/
bogdanm	0:9b334a45a8ff	2693	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2694	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
bogdanm	0:9b334a45a8ff	2695
bogdanm	0:9b334a45a8ff	2696	/** @brief Macro to get the clock source used as system clock.
bogdanm	0:9b334a45a8ff	2697	* @retval The clock source used as system clock. The returned value can be one
bogdanm	0:9b334a45a8ff	2698	* of the following:
bogdanm	0:9b334a45a8ff	2699	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
bogdanm	0:9b334a45a8ff	2700	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
bogdanm	0:9b334a45a8ff	2701	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
bogdanm	0:9b334a45a8ff	2702	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
bogdanm	0:9b334a45a8ff	2703	*/
bogdanm	0:9b334a45a8ff	2704	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm	0:9b334a45a8ff	2705
bogdanm	0:9b334a45a8ff	2706	/**
bogdanm	0:9b334a45a8ff	2707	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
bogdanm	0:9b334a45a8ff	2708	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	0:9b334a45a8ff	2709	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	2710	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	0:9b334a45a8ff	2711	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	2712	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
bogdanm	0:9b334a45a8ff	2713	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2714	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm	0:9b334a45a8ff	2715	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm	0:9b334a45a8ff	2716	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm	0:9b334a45a8ff	2717	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm	0:9b334a45a8ff	2718	* @retval None
bogdanm	0:9b334a45a8ff	2719	*/
bogdanm	0:9b334a45a8ff	2720	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
bogdanm	0:9b334a45a8ff	2721	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
bogdanm	0:9b334a45a8ff	2722
bogdanm	0:9b334a45a8ff	2723	/**
bogdanm	0:9b334a45a8ff	2724	* @brief Macro to configures the wake up from stop clock.
bogdanm	0:9b334a45a8ff	2725	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
bogdanm	0:9b334a45a8ff	2726	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2727	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
bogdanm	0:9b334a45a8ff	2728	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
bogdanm	0:9b334a45a8ff	2729	* @retval None
bogdanm	0:9b334a45a8ff	2730	*/
bogdanm	0:9b334a45a8ff	2731	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
bogdanm	0:9b334a45a8ff	2732	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
bogdanm	0:9b334a45a8ff	2733
bogdanm	0:9b334a45a8ff	2734
bogdanm	0:9b334a45a8ff	2735	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	0:9b334a45a8ff	2736	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	2737	* @{
bogdanm	0:9b334a45a8ff	2738	*/
bogdanm	0:9b334a45a8ff	2739
bogdanm	0:9b334a45a8ff	2740	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm	0:9b334a45a8ff	2741	* the selected interrupts).
bogdanm	0:9b334a45a8ff	2742	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	2743	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2744	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	2745	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	2746	* @arg RCC_IT_MSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2747	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2748	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	2749	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	2750	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
bogdanm	0:9b334a45a8ff	2751	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
bogdanm	0:9b334a45a8ff	2752	* @arg RCC_IT_LSECSS: Clock security system interrupt
bogdanm	0:9b334a45a8ff	2753	* @retval None
bogdanm	0:9b334a45a8ff	2754	*/
bogdanm	0:9b334a45a8ff	2755	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2756
bogdanm	0:9b334a45a8ff	2757	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm	0:9b334a45a8ff	2758	* the selected interrupts).
bogdanm	0:9b334a45a8ff	2759	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	2760	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2761	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	2762	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	2763	* @arg RCC_IT_MSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2764	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2765	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	2766	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	2767	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
bogdanm	0:9b334a45a8ff	2768	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
bogdanm	0:9b334a45a8ff	2769	* @arg RCC_IT_LSECSS: Clock security system interrupt
bogdanm	0:9b334a45a8ff	2770	* @retval None
bogdanm	0:9b334a45a8ff	2771	*/
bogdanm	0:9b334a45a8ff	2772	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2773
bogdanm	0:9b334a45a8ff	2774	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm	0:9b334a45a8ff	2775	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	2776	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	2777	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2778	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	2779	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	2780	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	2781	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2782	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	2783	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	2784	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
bogdanm	0:9b334a45a8ff	2785	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
bogdanm	0:9b334a45a8ff	2786	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
bogdanm	0:9b334a45a8ff	2787	* @arg RCC_IT_LSECSS: Clock security system interrupt
bogdanm	0:9b334a45a8ff	2788	* @retval None
bogdanm	0:9b334a45a8ff	2789	*/
bogdanm	0:9b334a45a8ff	2790	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2791
bogdanm	0:9b334a45a8ff	2792	/** @brief Check whether the RCC interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	2793	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	2794	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2795	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	2796	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	2797	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	2798	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	2799	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	2800	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	2801	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
bogdanm	0:9b334a45a8ff	2802	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
bogdanm	0:9b334a45a8ff	2803	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
bogdanm	0:9b334a45a8ff	2804	* @arg RCC_IT_LSECSS: Clock security system interrupt
bogdanm	0:9b334a45a8ff	2805	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2806	*/
bogdanm	0:9b334a45a8ff	2807	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2808
bogdanm	0:9b334a45a8ff	2809	/** @brief Set RMVF bit to clear the reset flags.
bogdanm	0:9b334a45a8ff	2810	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
bogdanm	0:9b334a45a8ff	2811	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm	0:9b334a45a8ff	2812	* @retval None
bogdanm	0:9b334a45a8ff	2813	*/
bogdanm	0:9b334a45a8ff	2814	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	0:9b334a45a8ff	2815
bogdanm	0:9b334a45a8ff	2816	/** @brief Check whether the selected RCC flag is set or not.
bogdanm	0:9b334a45a8ff	2817	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	2818	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2819	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
bogdanm	0:9b334a45a8ff	2820	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm	0:9b334a45a8ff	2821	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm	0:9b334a45a8ff	2822	* @arg RCC_FLAG_PLLRDY: main PLL clock ready
bogdanm	0:9b334a45a8ff	2823	* @arg RCC_FLAG_PLLSAI2RDY: PLLSAI2 clock ready
bogdanm	0:9b334a45a8ff	2824	* @arg RCC_FLAG_PLLSAI1RDY: PLLSAI1 clock ready
bogdanm	0:9b334a45a8ff	2825	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm	0:9b334a45a8ff	2826	* @arg RCC_FLAG_LSECSSD: Clock security system failure on LSE oscillator detection
bogdanm	0:9b334a45a8ff	2827	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm	0:9b334a45a8ff	2828	* @arg RCC_FLAG_BORRST: BOR reset
bogdanm	0:9b334a45a8ff	2829	* @arg RCC_FLAG_OBLRST: OBLRST reset
bogdanm	0:9b334a45a8ff	2830	* @arg RCC_FLAG_PINRST: Pin reset
bogdanm	0:9b334a45a8ff	2831	* @arg RCC_FLAG_FWRST: FIREWALL reset
bogdanm	0:9b334a45a8ff	2832	* @arg RCC_FLAG_RMVF: Remove reset Flag
bogdanm	0:9b334a45a8ff	2833	* @arg RCC_FLAG_SFTRST: Software reset
bogdanm	0:9b334a45a8ff	2834	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm	0:9b334a45a8ff	2835	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm	0:9b334a45a8ff	2836	* @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm	0:9b334a45a8ff	2837	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2838	*/
bogdanm	0:9b334a45a8ff	2839	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
bogdanm	0:9b334a45a8ff	2840	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
bogdanm	0:9b334a45a8ff	2841	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
bogdanm	0:9b334a45a8ff	2842	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0) \
bogdanm	0:9b334a45a8ff	2843	? 1 : 0)
bogdanm	0:9b334a45a8ff	2844
bogdanm	0:9b334a45a8ff	2845	/**
bogdanm	0:9b334a45a8ff	2846	* @}
bogdanm	0:9b334a45a8ff	2847	*/
bogdanm	0:9b334a45a8ff	2848
bogdanm	0:9b334a45a8ff	2849	/**
bogdanm	0:9b334a45a8ff	2850	* @}
bogdanm	0:9b334a45a8ff	2851	*/
bogdanm	0:9b334a45a8ff	2852
bogdanm	0:9b334a45a8ff	2853	/* Private constants ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2854	/** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm	0:9b334a45a8ff	2855	* @{
bogdanm	0:9b334a45a8ff	2856	*/
bogdanm	0:9b334a45a8ff	2857	/* Defines used for Flags */
bogdanm	0:9b334a45a8ff	2858	#define CR_REG_INDEX ((uint8_t)1)
bogdanm	0:9b334a45a8ff	2859	#define BDCR_REG_INDEX ((uint8_t)2)
bogdanm	0:9b334a45a8ff	2860	#define CSR_REG_INDEX ((uint8_t)3)
bogdanm	0:9b334a45a8ff	2861
bogdanm	0:9b334a45a8ff	2862	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	0:9b334a45a8ff	2863	/**
bogdanm	0:9b334a45a8ff	2864	* @}
bogdanm	0:9b334a45a8ff	2865	*/
bogdanm	0:9b334a45a8ff	2866
bogdanm	0:9b334a45a8ff	2867	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2868	/** @addtogroup RCC_Private_Macros
bogdanm	0:9b334a45a8ff	2869	* @{
bogdanm	0:9b334a45a8ff	2870	*/
bogdanm	0:9b334a45a8ff	2871
bogdanm	0:9b334a45a8ff	2872	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	2873	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	2874	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2875	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	2876	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	2877	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
bogdanm	0:9b334a45a8ff	2878
bogdanm	0:9b334a45a8ff	2879	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	2880	((__HSE__) == RCC_HSE_BYPASS))
bogdanm	0:9b334a45a8ff	2881
bogdanm	0:9b334a45a8ff	2882	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	2883	((__LSE__) == RCC_LSE_BYPASS))
bogdanm	0:9b334a45a8ff	2884
bogdanm	0:9b334a45a8ff	2885	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	2886
bogdanm	0:9b334a45a8ff	2887	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31)
bogdanm	0:9b334a45a8ff	2888
bogdanm	0:9b334a45a8ff	2889	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
bogdanm	0:9b334a45a8ff	2890
bogdanm	0:9b334a45a8ff	2891	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
bogdanm	0:9b334a45a8ff	2892
bogdanm	0:9b334a45a8ff	2893	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255)
bogdanm	0:9b334a45a8ff	2894
bogdanm	0:9b334a45a8ff	2895	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	2896	((__PLL__) == RCC_PLL_ON))
bogdanm	0:9b334a45a8ff	2897
bogdanm	0:9b334a45a8ff	2898	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	2899	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	2900	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2901	((__SOURCE__) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	2902
bogdanm	0:9b334a45a8ff	2903	#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= 8)
bogdanm	0:9b334a45a8ff	2904
bogdanm	0:9b334a45a8ff	2905	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
bogdanm	0:9b334a45a8ff	2906
bogdanm	0:9b334a45a8ff	2907	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17) )
bogdanm	0:9b334a45a8ff	2908
bogdanm	0:9b334a45a8ff	2909	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
bogdanm	0:9b334a45a8ff	2910	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
bogdanm	0:9b334a45a8ff	2911
bogdanm	0:9b334a45a8ff	2912	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
bogdanm	0:9b334a45a8ff	2913	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
bogdanm	0:9b334a45a8ff	2914
bogdanm	0:9b334a45a8ff	2915	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
bogdanm	0:9b334a45a8ff	2916	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
bogdanm	0:9b334a45a8ff	2917	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
bogdanm	0:9b334a45a8ff	2918	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0))
bogdanm	0:9b334a45a8ff	2919
bogdanm	0:9b334a45a8ff	2920	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK ) \|\| \
bogdanm	0:9b334a45a8ff	2921	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
bogdanm	0:9b334a45a8ff	2922	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0))
bogdanm	0:9b334a45a8ff	2923
bogdanm	0:9b334a45a8ff	2924	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
bogdanm	0:9b334a45a8ff	2925	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
bogdanm	0:9b334a45a8ff	2926	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
bogdanm	0:9b334a45a8ff	2927	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
bogdanm	0:9b334a45a8ff	2928	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
bogdanm	0:9b334a45a8ff	2929	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
bogdanm	0:9b334a45a8ff	2930	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
bogdanm	0:9b334a45a8ff	2931	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
bogdanm	0:9b334a45a8ff	2932	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
bogdanm	0:9b334a45a8ff	2933	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
bogdanm	0:9b334a45a8ff	2934	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
bogdanm	0:9b334a45a8ff	2935	((__RANGE__) == RCC_MSIRANGE_11))
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
bogdanm	0:9b334a45a8ff	2938	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
bogdanm	0:9b334a45a8ff	2939	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
bogdanm	0:9b334a45a8ff	2940	((__RANGE__) == RCC_MSIRANGE_7))
bogdanm	0:9b334a45a8ff	2941
bogdanm	0:9b334a45a8ff	2942	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
bogdanm	0:9b334a45a8ff	2943
bogdanm	0:9b334a45a8ff	2944	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	2945	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2946	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	2947	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	2948
bogdanm	0:9b334a45a8ff	2949	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	2950	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	2951	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	2952	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	2953	((__HCLK__) == RCC_SYSCLK_DIV512))
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	2956	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	2957	((__PCLK__) == RCC_HCLK_DIV16))
bogdanm	0:9b334a45a8ff	2958
bogdanm	0:9b334a45a8ff	2959	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2960	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	2961	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm	0:9b334a45a8ff	2962
bogdanm	0:9b334a45a8ff	2963	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
bogdanm	0:9b334a45a8ff	2964
bogdanm	0:9b334a45a8ff	2965	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2966	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	2967	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2968	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	2969	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
bogdanm	0:9b334a45a8ff	2970	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	2971	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
bogdanm	0:9b334a45a8ff	2972
bogdanm	0:9b334a45a8ff	2973	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
bogdanm	0:9b334a45a8ff	2974	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
bogdanm	0:9b334a45a8ff	2975	((__DIV__) == RCC_MCODIV_16))
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
bogdanm	0:9b334a45a8ff	2978	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
bogdanm	0:9b334a45a8ff	2979	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
bogdanm	0:9b334a45a8ff	2980	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
bogdanm	0:9b334a45a8ff	2981
bogdanm	0:9b334a45a8ff	2982	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
bogdanm	0:9b334a45a8ff	2983	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
bogdanm	0:9b334a45a8ff	2984	/**
bogdanm	0:9b334a45a8ff	2985	* @}
bogdanm	0:9b334a45a8ff	2986	*/
bogdanm	0:9b334a45a8ff	2987
bogdanm	0:9b334a45a8ff	2988	/* Include RCC HAL Extended module */
bogdanm	0:9b334a45a8ff	2989	#include "stm32l4xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	2990
bogdanm	0:9b334a45a8ff	2991	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2992	/** @addtogroup RCC_Exported_Functions
bogdanm	0:9b334a45a8ff	2993	* @{
bogdanm	0:9b334a45a8ff	2994	*/
bogdanm	0:9b334a45a8ff	2995
bogdanm	0:9b334a45a8ff	2996
bogdanm	0:9b334a45a8ff	2997	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	2998	* @{
bogdanm	0:9b334a45a8ff	2999	*/
bogdanm	0:9b334a45a8ff	3000
bogdanm	0:9b334a45a8ff	3001	/* Initialization and de-initialization functions ******************************/
bogdanm	0:9b334a45a8ff	3002	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	3003	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	3004	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	3005
bogdanm	0:9b334a45a8ff	3006	/**
bogdanm	0:9b334a45a8ff	3007	* @}
bogdanm	0:9b334a45a8ff	3008	*/
bogdanm	0:9b334a45a8ff	3009
bogdanm	0:9b334a45a8ff	3010	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	3011	* @{
bogdanm	0:9b334a45a8ff	3012	*/
bogdanm	0:9b334a45a8ff	3013
bogdanm	0:9b334a45a8ff	3014	/* Peripheral Control functions ************************************************/
bogdanm	0:9b334a45a8ff	3015	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	0:9b334a45a8ff	3016	void HAL_RCC_EnableCSS(void);
bogdanm	0:9b334a45a8ff	3017	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	3018	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	3019	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	3020	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	0:9b334a45a8ff	3021	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	3022	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	3023	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	3024	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	3025	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	3026	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	3027
bogdanm	0:9b334a45a8ff	3028	/**
bogdanm	0:9b334a45a8ff	3029	* @}
bogdanm	0:9b334a45a8ff	3030	*/
bogdanm	0:9b334a45a8ff	3031
bogdanm	0:9b334a45a8ff	3032	/**
bogdanm	0:9b334a45a8ff	3033	* @}
bogdanm	0:9b334a45a8ff	3034	*/
bogdanm	0:9b334a45a8ff	3035
bogdanm	0:9b334a45a8ff	3036	/**
bogdanm	0:9b334a45a8ff	3037	* @}
bogdanm	0:9b334a45a8ff	3038	*/
bogdanm	0:9b334a45a8ff	3039
bogdanm	0:9b334a45a8ff	3040	/**
bogdanm	0:9b334a45a8ff	3041	* @}
bogdanm	0:9b334a45a8ff	3042	*/
bogdanm	0:9b334a45a8ff	3043
bogdanm	0:9b334a45a8ff	3044	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	3045	}
bogdanm	0:9b334a45a8ff	3046	#endif
bogdanm	0:9b334a45a8ff	3047
bogdanm	0:9b334a45a8ff	3048	#endif /* __STM32L4xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	3049
bogdanm	0:9b334a45a8ff	3050	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	17 Oct 2016
Imports:	2
Forks:	0
Commits:	149
Dependents:	0
Dependencies:	0
Followers:	4

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@71:a5b1c83f05dc, 2016-02-25 (annotated)

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