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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:: rodriguise
Date:: Mon Oct 17 18:47:01 2016 +0000
Revision:: 148:4802eb17e82b
Parent:: 144:ef7eb2e8f9f7

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User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup RCC
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t PLLState; /*!< The new state of the PLL.
<>	144:ef7eb2e8f9f7	68	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
<>	144:ef7eb2e8f9f7	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
<>	144:ef7eb2e8f9f7	74	This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
<>	144:ef7eb2e8f9f7	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
<>	144:ef7eb2e8f9f7	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
<>	144:ef7eb2e8f9f7	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
<>	144:ef7eb2e8f9f7	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
<>	144:ef7eb2e8f9f7	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	}RCC_PLLInitTypeDef;
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	/**
<>	144:ef7eb2e8f9f7	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	93	*/
<>	144:ef7eb2e8f9f7	94	typedef struct
<>	144:ef7eb2e8f9f7	95	{
<>	144:ef7eb2e8f9f7	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
<>	144:ef7eb2e8f9f7	97	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	uint32_t HSEState; /*!< The new state of the HSE.
<>	144:ef7eb2e8f9f7	100	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	uint32_t LSEState; /*!< The new state of the LSE.
<>	144:ef7eb2e8f9f7	103	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	uint32_t HSIState; /*!< The new state of the HSI.
<>	144:ef7eb2e8f9f7	106	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L47x/STM32L48x devices.
<>	144:ef7eb2e8f9f7	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on STM32L43x/STM32L44x/STM32L49x/STM32L4Ax/ devices */
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	uint32_t LSIState; /*!< The new state of the LSI.
<>	144:ef7eb2e8f9f7	113	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	uint32_t MSIState; /*!< The new state of the MSI.
<>	144:ef7eb2e8f9f7	116	This parameter can be a value of @ref RCC_MSI_Config */
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	uint32_t MSIClockRange; /*!< The MSI frequency range.
<>	144:ef7eb2e8f9f7	122	This parameter can be a value of @ref RCC_MSI_Clock_Range */
<>	144:ef7eb2e8f9f7	123
<>	144:ef7eb2e8f9f7	124	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
<>	144:ef7eb2e8f9f7	125	This parameter can be a value of @ref RCC_HSI48_Config */
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	}RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/**
<>	144:ef7eb2e8f9f7	132	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134	typedef struct
<>	144:ef7eb2e8f9f7	135	{
<>	144:ef7eb2e8f9f7	136	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	137	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	143	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	146	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	149	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	}RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/**
<>	144:ef7eb2e8f9f7	154	* @}
<>	144:ef7eb2e8f9f7	155	*/
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	158	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	159	* @{
<>	144:ef7eb2e8f9f7	160	*/
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/** @defgroup RCC_Timeout_Value Timeout Values
<>	144:ef7eb2e8f9f7	163	* @{
<>	144:ef7eb2e8f9f7	164	*/
<>	144:ef7eb2e8f9f7	165	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
rodriguise	148:4802eb17e82b	166	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) // LSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	167	/**
<>	144:ef7eb2e8f9f7	168	* @}
<>	144:ef7eb2e8f9f7	169	*/
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	172	* @{
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /!< Oscillator configuration unchanged /
<>	144:ef7eb2e8f9f7	175	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /!< HSE to configure /
<>	144:ef7eb2e8f9f7	176	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /!< HSI to configure /
<>	144:ef7eb2e8f9f7	177	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /!< LSE to configure /
<>	144:ef7eb2e8f9f7	178	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /!< LSI to configure /
<>	144:ef7eb2e8f9f7	179	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /!< MSI to configure /
<>	144:ef7eb2e8f9f7	180	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	181	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /!< HSI48 to configure /
<>	144:ef7eb2e8f9f7	182	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	183	/**
<>	144:ef7eb2e8f9f7	184	* @}
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	/** @defgroup RCC_HSE_Config HSE Config
<>	144:ef7eb2e8f9f7	188	* @{
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190	#define RCC_HSE_OFF ((uint32_t)0x00000000U) /!< HSE clock deactivation /
<>	144:ef7eb2e8f9f7	191	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
<>	144:ef7eb2e8f9f7	192	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
<>	144:ef7eb2e8f9f7	193	/**
<>	144:ef7eb2e8f9f7	194	* @}
<>	144:ef7eb2e8f9f7	195	*/
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	/** @defgroup RCC_LSE_Config LSE Config
<>	144:ef7eb2e8f9f7	198	* @{
<>	144:ef7eb2e8f9f7	199	*/
<>	144:ef7eb2e8f9f7	200	#define RCC_LSE_OFF ((uint32_t)0x00000000U) /!< LSE clock deactivation /
<>	144:ef7eb2e8f9f7	201	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
<>	144:ef7eb2e8f9f7	202	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	* @}
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/** @defgroup RCC_HSI_Config HSI Config
<>	144:ef7eb2e8f9f7	208	* @{
<>	144:ef7eb2e8f9f7	209	*/
<>	144:ef7eb2e8f9f7	210	#define RCC_HSI_OFF ((uint32_t)0x00000000U) /!< HSI clock deactivation /
<>	144:ef7eb2e8f9f7	211	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /!< Default HSI calibration trimming value /
<>	144:ef7eb2e8f9f7	214	/**
<>	144:ef7eb2e8f9f7	215	* @}
<>	144:ef7eb2e8f9f7	216	*/
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/** @defgroup RCC_LSI_Config LSI Config
<>	144:ef7eb2e8f9f7	219	* @{
<>	144:ef7eb2e8f9f7	220	*/
<>	144:ef7eb2e8f9f7	221	#define RCC_LSI_OFF ((uint32_t)0x00000000U) /!< LSI clock deactivation /
<>	144:ef7eb2e8f9f7	222	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
<>	144:ef7eb2e8f9f7	223	/**
<>	144:ef7eb2e8f9f7	224	* @}
<>	144:ef7eb2e8f9f7	225	*/
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/** @defgroup RCC_MSI_Config MSI Config
<>	144:ef7eb2e8f9f7	228	* @{
<>	144:ef7eb2e8f9f7	229	*/
<>	144:ef7eb2e8f9f7	230	#define RCC_MSI_OFF ((uint32_t)0x00000000U) /!< MSI clock deactivation /
<>	144:ef7eb2e8f9f7	231	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
<>	144:ef7eb2e8f9f7	234	/**
<>	144:ef7eb2e8f9f7	235	* @}
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	239	/** @defgroup RCC_HSI48_Config HSI48 Config
<>	144:ef7eb2e8f9f7	240	* @{
<>	144:ef7eb2e8f9f7	241	*/
<>	144:ef7eb2e8f9f7	242	#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /!< HSI48 clock deactivation /
<>	144:ef7eb2e8f9f7	243	#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /!< HSI48 clock activation /
<>	144:ef7eb2e8f9f7	244	/**
<>	144:ef7eb2e8f9f7	245	* @}
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247	#else
<>	144:ef7eb2e8f9f7	248	/** @defgroup RCC_HSI48_Config HSI48 Config
<>	144:ef7eb2e8f9f7	249	* @{
<>	144:ef7eb2e8f9f7	250	*/
<>	144:ef7eb2e8f9f7	251	#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /!< HSI48 clock deactivation /
<>	144:ef7eb2e8f9f7	252	/**
<>	144:ef7eb2e8f9f7	253	* @}
<>	144:ef7eb2e8f9f7	254	*/
<>	144:ef7eb2e8f9f7	255	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/** @defgroup RCC_PLL_Config PLL Config
<>	144:ef7eb2e8f9f7	258	* @{
<>	144:ef7eb2e8f9f7	259	*/
<>	144:ef7eb2e8f9f7	260	#define RCC_PLL_NONE ((uint32_t)0x00000000U) /!< PLL configuration unchanged /
<>	144:ef7eb2e8f9f7	261	#define RCC_PLL_OFF ((uint32_t)0x00000001U) /!< PLL deactivation /
<>	144:ef7eb2e8f9f7	262	#define RCC_PLL_ON ((uint32_t)0x00000002U) /!< PLL activation /
<>	144:ef7eb2e8f9f7	263	/**
<>	144:ef7eb2e8f9f7	264	* @}
<>	144:ef7eb2e8f9f7	265	*/
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
<>	144:ef7eb2e8f9f7	268	* @{
<>	144:ef7eb2e8f9f7	269	*/
<>	144:ef7eb2e8f9f7	270	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	271	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /!< PLLP division factor = 2 /
<>	144:ef7eb2e8f9f7	272	#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /!< PLLP division factor = 3 /
<>	144:ef7eb2e8f9f7	273	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /!< PLLP division factor = 4 /
<>	144:ef7eb2e8f9f7	274	#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /!< PLLP division factor = 5 /
<>	144:ef7eb2e8f9f7	275	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /!< PLLP division factor = 6 /
<>	144:ef7eb2e8f9f7	276	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /!< PLLP division factor = 7 /
<>	144:ef7eb2e8f9f7	277	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /!< PLLP division factor = 8 /
<>	144:ef7eb2e8f9f7	278	#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /!< PLLP division factor = 9 /
<>	144:ef7eb2e8f9f7	279	#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /!< PLLP division factor = 10 /
<>	144:ef7eb2e8f9f7	280	#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /!< PLLP division factor = 11 /
<>	144:ef7eb2e8f9f7	281	#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /!< PLLP division factor = 12 /
<>	144:ef7eb2e8f9f7	282	#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /!< PLLP division factor = 13 /
<>	144:ef7eb2e8f9f7	283	#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /!< PLLP division factor = 14 /
<>	144:ef7eb2e8f9f7	284	#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /!< PLLP division factor = 15 /
<>	144:ef7eb2e8f9f7	285	#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /!< PLLP division factor = 16 /
<>	144:ef7eb2e8f9f7	286	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /!< PLLP division factor = 17 /
<>	144:ef7eb2e8f9f7	287	#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /!< PLLP division factor = 18 /
<>	144:ef7eb2e8f9f7	288	#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /!< PLLP division factor = 19 /
<>	144:ef7eb2e8f9f7	289	#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /!< PLLP division factor = 20 /
<>	144:ef7eb2e8f9f7	290	#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /!< PLLP division factor = 21 /
<>	144:ef7eb2e8f9f7	291	#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /!< PLLP division factor = 22 /
<>	144:ef7eb2e8f9f7	292	#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /!< PLLP division factor = 23 /
<>	144:ef7eb2e8f9f7	293	#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /!< PLLP division factor = 24 /
<>	144:ef7eb2e8f9f7	294	#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /!< PLLP division factor = 25 /
<>	144:ef7eb2e8f9f7	295	#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /!< PLLP division factor = 26 /
<>	144:ef7eb2e8f9f7	296	#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /!< PLLP division factor = 27 /
<>	144:ef7eb2e8f9f7	297	#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /!< PLLP division factor = 28 /
<>	144:ef7eb2e8f9f7	298	#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /!< PLLP division factor = 29 /
<>	144:ef7eb2e8f9f7	299	#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /!< PLLP division factor = 30 /
<>	144:ef7eb2e8f9f7	300	#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /!< PLLP division factor = 31 /
<>	144:ef7eb2e8f9f7	301	#else
<>	144:ef7eb2e8f9f7	302	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /!< PLLP division factor = 7 /
<>	144:ef7eb2e8f9f7	303	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /!< PLLP division factor = 17 /
<>	144:ef7eb2e8f9f7	304	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	305	/**
<>	144:ef7eb2e8f9f7	306	* @}
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
<>	144:ef7eb2e8f9f7	310	* @{
<>	144:ef7eb2e8f9f7	311	*/
<>	144:ef7eb2e8f9f7	312	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /!< PLLQ division factor = 2 /
<>	144:ef7eb2e8f9f7	313	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /!< PLLQ division factor = 4 /
<>	144:ef7eb2e8f9f7	314	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /!< PLLQ division factor = 6 /
<>	144:ef7eb2e8f9f7	315	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /!< PLLQ division factor = 8 /
<>	144:ef7eb2e8f9f7	316	/**
<>	144:ef7eb2e8f9f7	317	* @}
<>	144:ef7eb2e8f9f7	318	*/
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
<>	144:ef7eb2e8f9f7	321	* @{
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /!< PLLR division factor = 2 /
<>	144:ef7eb2e8f9f7	324	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /!< PLLR division factor = 4 /
<>	144:ef7eb2e8f9f7	325	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /!< PLLR division factor = 6 /
<>	144:ef7eb2e8f9f7	326	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /!< PLLR division factor = 8 /
<>	144:ef7eb2e8f9f7	327	/**
<>	144:ef7eb2e8f9f7	328	* @}
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	332	* @{
<>	144:ef7eb2e8f9f7	333	*/
<>	144:ef7eb2e8f9f7	334	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /!< No clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	335	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	336	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	337	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @}
<>	144:ef7eb2e8f9f7	340	*/
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
<>	144:ef7eb2e8f9f7	343	* @{
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	346	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) /
<>	144:ef7eb2e8f9f7	347	#else
<>	144:ef7eb2e8f9f7	348	#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) /
<>	144:ef7eb2e8f9f7	349	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	350	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
<>	144:ef7eb2e8f9f7	351	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
<>	144:ef7eb2e8f9f7	352	/**
<>	144:ef7eb2e8f9f7	353	* @}
<>	144:ef7eb2e8f9f7	354	*/
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
<>	144:ef7eb2e8f9f7	357	* @{
<>	144:ef7eb2e8f9f7	358	*/
<>	144:ef7eb2e8f9f7	359	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
<>	144:ef7eb2e8f9f7	360	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
<>	144:ef7eb2e8f9f7	361	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
<>	144:ef7eb2e8f9f7	362	/**
<>	144:ef7eb2e8f9f7	363	* @}
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
<>	144:ef7eb2e8f9f7	369	* @{
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
<>	144:ef7eb2e8f9f7	372	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
<>	144:ef7eb2e8f9f7	373	/**
<>	144:ef7eb2e8f9f7	374	* @}
<>	144:ef7eb2e8f9f7	375	*/
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
<>	144:ef7eb2e8f9f7	380	* @{
<>	144:ef7eb2e8f9f7	381	*/
<>	144:ef7eb2e8f9f7	382	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
<>	144:ef7eb2e8f9f7	383	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
<>	144:ef7eb2e8f9f7	384	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
<>	144:ef7eb2e8f9f7	385	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
<>	144:ef7eb2e8f9f7	386	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
<>	144:ef7eb2e8f9f7	387	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
<>	144:ef7eb2e8f9f7	388	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
<>	144:ef7eb2e8f9f7	389	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
<>	144:ef7eb2e8f9f7	390	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
<>	144:ef7eb2e8f9f7	391	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
<>	144:ef7eb2e8f9f7	392	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
<>	144:ef7eb2e8f9f7	393	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
<>	144:ef7eb2e8f9f7	394	/**
<>	144:ef7eb2e8f9f7	395	* @}
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup RCC_System_Clock_Type System Clock Type
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /!< SYSCLK to configure /
<>	144:ef7eb2e8f9f7	402	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /!< HCLK to configure /
<>	144:ef7eb2e8f9f7	403	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /!< PCLK1 to configure /
<>	144:ef7eb2e8f9f7	404	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /!< PCLK2 to configure /
<>	144:ef7eb2e8f9f7	405	/**
<>	144:ef7eb2e8f9f7	406	* @}
<>	144:ef7eb2e8f9f7	407	*/
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/** @defgroup RCC_System_Clock_Source System Clock Source
<>	144:ef7eb2e8f9f7	410	* @{
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
<>	144:ef7eb2e8f9f7	413	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	144:ef7eb2e8f9f7	414	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	144:ef7eb2e8f9f7	415	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	144:ef7eb2e8f9f7	416	/**
<>	144:ef7eb2e8f9f7	417	* @}
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<>	144:ef7eb2e8f9f7	421	* @{
<>	144:ef7eb2e8f9f7	422	*/
<>	144:ef7eb2e8f9f7	423	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
<>	144:ef7eb2e8f9f7	424	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	425	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	426	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	427	/**
<>	144:ef7eb2e8f9f7	428	* @}
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<>	144:ef7eb2e8f9f7	432	* @{
<>	144:ef7eb2e8f9f7	433	*/
<>	144:ef7eb2e8f9f7	434	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	144:ef7eb2e8f9f7	435	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	144:ef7eb2e8f9f7	436	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	144:ef7eb2e8f9f7	437	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	144:ef7eb2e8f9f7	438	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	144:ef7eb2e8f9f7	439	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	144:ef7eb2e8f9f7	440	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	144:ef7eb2e8f9f7	441	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	144:ef7eb2e8f9f7	442	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	443	/**
<>	144:ef7eb2e8f9f7	444	* @}
<>	144:ef7eb2e8f9f7	445	*/
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
<>	144:ef7eb2e8f9f7	448	* @{
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	451	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	452	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	453	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	454	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	455	/**
<>	144:ef7eb2e8f9f7	456	* @}
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
<>	144:ef7eb2e8f9f7	460	* @{
<>	144:ef7eb2e8f9f7	461	*/
<>	144:ef7eb2e8f9f7	462	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /!< No clock used as RTC clock /
<>	144:ef7eb2e8f9f7	463	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	464	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	465	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
<>	144:ef7eb2e8f9f7	466	/**
<>	144:ef7eb2e8f9f7	467	* @}
<>	144:ef7eb2e8f9f7	468	*/
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/** @defgroup RCC_MCO_Index MCO Index
<>	144:ef7eb2e8f9f7	471	* @{
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473	#define RCC_MCO1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	474	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
<>	144:ef7eb2e8f9f7	475	/**
<>	144:ef7eb2e8f9f7	476	* @}
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478
<>	144:ef7eb2e8f9f7	479	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
<>	144:ef7eb2e8f9f7	480	* @{
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /!< MCO1 output disabled, no clock on MCO1 /
<>	144:ef7eb2e8f9f7	483	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
<>	144:ef7eb2e8f9f7	484	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
<>	144:ef7eb2e8f9f7	485	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
<>	144:ef7eb2e8f9f7	486	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
<>	144:ef7eb2e8f9f7	487	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
<>	144:ef7eb2e8f9f7	488	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
<>	144:ef7eb2e8f9f7	489	#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
<>	144:ef7eb2e8f9f7	490	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	491	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) /
<>	144:ef7eb2e8f9f7	492	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	493	/**
<>	144:ef7eb2e8f9f7	494	* @}
<>	144:ef7eb2e8f9f7	495	*/
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
<>	144:ef7eb2e8f9f7	498	* @{
<>	144:ef7eb2e8f9f7	499	*/
<>	144:ef7eb2e8f9f7	500	#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
<>	144:ef7eb2e8f9f7	501	#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
<>	144:ef7eb2e8f9f7	502	#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
<>	144:ef7eb2e8f9f7	503	#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
<>	144:ef7eb2e8f9f7	504	#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
<>	144:ef7eb2e8f9f7	505	/**
<>	144:ef7eb2e8f9f7	506	* @}
<>	144:ef7eb2e8f9f7	507	*/
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	/** @defgroup RCC_Interrupt Interrupts
<>	144:ef7eb2e8f9f7	510	* @{
<>	144:ef7eb2e8f9f7	511	*/
<>	144:ef7eb2e8f9f7	512	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	513	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	514	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	515	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI16 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	516	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	517	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	518	#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	519	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	520	#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	521	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	522	#define RCC_IT_CSS RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	523	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	524	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	525	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	526	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	527	/**
<>	144:ef7eb2e8f9f7	528	* @}
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/** @defgroup RCC_Flag Flags
<>	144:ef7eb2e8f9f7	532	* Elements values convention: XXXYYYYYb
<>	144:ef7eb2e8f9f7	533	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	534	* - XXX : Register index
<>	144:ef7eb2e8f9f7	535	* - 001: CR register
<>	144:ef7eb2e8f9f7	536	* - 010: BDCR register
<>	144:ef7eb2e8f9f7	537	* - 011: CSR register
<>	144:ef7eb2e8f9f7	538	* - 100: CRRCR register
<>	144:ef7eb2e8f9f7	539	* @{
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541	/* Flags in the CR register */
<>	144:ef7eb2e8f9f7	542	#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
<>	144:ef7eb2e8f9f7	543	#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
<>	144:ef7eb2e8f9f7	544	#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
<>	144:ef7eb2e8f9f7	545	#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
<>	144:ef7eb2e8f9f7	546	#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
<>	144:ef7eb2e8f9f7	547	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	548	#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
<>	144:ef7eb2e8f9f7	549	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/* Flags in the BDCR register */
<>	144:ef7eb2e8f9f7	552	#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
<>	144:ef7eb2e8f9f7	553	#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/* Flags in the CSR register */
<>	144:ef7eb2e8f9f7	556	#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
<>	144:ef7eb2e8f9f7	557	#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
<>	144:ef7eb2e8f9f7	558	#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
<>	144:ef7eb2e8f9f7	559	#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
<>	144:ef7eb2e8f9f7	560	#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
<>	144:ef7eb2e8f9f7	561	#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
<>	144:ef7eb2e8f9f7	562	#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
<>	144:ef7eb2e8f9f7	563	#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
<>	144:ef7eb2e8f9f7	564	#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
<>	144:ef7eb2e8f9f7	565	#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	568	/* Flags in the CRRCR register */
<>	144:ef7eb2e8f9f7	569	#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CRRCR_HSI48RDY))) /!< HSI48 Ready flag /
<>	144:ef7eb2e8f9f7	570	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	571	/**
<>	144:ef7eb2e8f9f7	572	* @}
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
<>	144:ef7eb2e8f9f7	576	* @{
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /!< LSE low drive capability /
<>	144:ef7eb2e8f9f7	579	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< LSE medium low drive capability /
<>	144:ef7eb2e8f9f7	580	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< LSE medium high drive capability /
<>	144:ef7eb2e8f9f7	581	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
<>	144:ef7eb2e8f9f7	582	/**
<>	144:ef7eb2e8f9f7	583	* @}
<>	144:ef7eb2e8f9f7	584	*/
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
<>	144:ef7eb2e8f9f7	587	* @{
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /!< MSI selection after wake-up from STOP /
<>	144:ef7eb2e8f9f7	590	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
<>	144:ef7eb2e8f9f7	591	/**
<>	144:ef7eb2e8f9f7	592	* @}
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/**
<>	144:ef7eb2e8f9f7	596	* @}
<>	144:ef7eb2e8f9f7	597	*/
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	602	* @{
<>	144:ef7eb2e8f9f7	603	*/
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	606	* @brief Enable or disable the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	607	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	608	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	609	* using it.
<>	144:ef7eb2e8f9f7	610	* @{
<>	144:ef7eb2e8f9f7	611	*/
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	614	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	615	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
<>	144:ef7eb2e8f9f7	616	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	617	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
<>	144:ef7eb2e8f9f7	618	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	619	} while(0)
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	622	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	623	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
<>	144:ef7eb2e8f9f7	624	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	625	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
<>	144:ef7eb2e8f9f7	626	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	627	} while(0)
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	630	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	631	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
<>	144:ef7eb2e8f9f7	632	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	633	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
<>	144:ef7eb2e8f9f7	634	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	635	} while(0)
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	638	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	639	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
<>	144:ef7eb2e8f9f7	640	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	641	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
<>	144:ef7eb2e8f9f7	642	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	643	} while(0)
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	646	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	647	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
<>	144:ef7eb2e8f9f7	648	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	649	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
<>	144:ef7eb2e8f9f7	650	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	651	} while(0)
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
<>	144:ef7eb2e8f9f7	659
<>	144:ef7eb2e8f9f7	660	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/**
<>	144:ef7eb2e8f9f7	665	* @}
<>	144:ef7eb2e8f9f7	666	*/
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	669	* @brief Enable or disable the AHB2 peripheral clock.
<>	144:ef7eb2e8f9f7	670	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	671	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	672	* using it.
<>	144:ef7eb2e8f9f7	673	* @{
<>	144:ef7eb2e8f9f7	674	*/
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	677	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	678	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
<>	144:ef7eb2e8f9f7	679	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	680	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
<>	144:ef7eb2e8f9f7	681	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	682	} while(0)
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	685	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	686	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
<>	144:ef7eb2e8f9f7	687	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	688	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
<>	144:ef7eb2e8f9f7	689	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	690	} while(0)
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	693	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	694	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
<>	144:ef7eb2e8f9f7	695	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	696	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
<>	144:ef7eb2e8f9f7	697	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	698	} while(0)
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	701	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	702	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	703	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
<>	144:ef7eb2e8f9f7	704	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	705	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
<>	144:ef7eb2e8f9f7	706	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	707	} while(0)
<>	144:ef7eb2e8f9f7	708	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	711	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	712	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	713	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
<>	144:ef7eb2e8f9f7	714	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	715	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
<>	144:ef7eb2e8f9f7	716	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	717	} while(0)
<>	144:ef7eb2e8f9f7	718	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	721	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	722	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	723	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
<>	144:ef7eb2e8f9f7	724	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	725	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
<>	144:ef7eb2e8f9f7	726	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	727	} while(0)
<>	144:ef7eb2e8f9f7	728	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	729
<>	144:ef7eb2e8f9f7	730	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	731	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	732	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	733	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
<>	144:ef7eb2e8f9f7	734	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	735	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
<>	144:ef7eb2e8f9f7	736	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	737	} while(0)
<>	144:ef7eb2e8f9f7	738	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	741	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	742	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
<>	144:ef7eb2e8f9f7	743	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	744	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
<>	144:ef7eb2e8f9f7	745	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	746	} while(0)
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	749	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	750	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	751	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
<>	144:ef7eb2e8f9f7	752	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	753	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
<>	144:ef7eb2e8f9f7	754	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	755	} while(0)
<>	144:ef7eb2e8f9f7	756	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	759	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	760	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
<>	144:ef7eb2e8f9f7	761	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	762	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
<>	144:ef7eb2e8f9f7	763	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	764	} while(0)
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	#if defined(AES)
<>	144:ef7eb2e8f9f7	767	#define __HAL_RCC_AES_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	768	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	769	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
<>	144:ef7eb2e8f9f7	770	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	771	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
<>	144:ef7eb2e8f9f7	772	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	773	} while(0)
<>	144:ef7eb2e8f9f7	774	#endif /* AES */
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	777	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	778	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
<>	144:ef7eb2e8f9f7	779	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	780	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
<>	144:ef7eb2e8f9f7	781	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	782	} while(0)
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	792	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
<>	144:ef7eb2e8f9f7	793	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	794
<>	144:ef7eb2e8f9f7	795	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	796	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
<>	144:ef7eb2e8f9f7	797	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	800	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
<>	144:ef7eb2e8f9f7	801	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	802
<>	144:ef7eb2e8f9f7	803	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	804	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
<>	144:ef7eb2e8f9f7	805	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	810	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
<>	144:ef7eb2e8f9f7	811	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	812
<>	144:ef7eb2e8f9f7	813	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
<>	144:ef7eb2e8f9f7	814
<>	144:ef7eb2e8f9f7	815	#if defined(AES)
<>	144:ef7eb2e8f9f7	816	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
<>	144:ef7eb2e8f9f7	817	#endif /* AES */
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	/**
<>	144:ef7eb2e8f9f7	822	* @}
<>	144:ef7eb2e8f9f7	823	*/
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	826	* @brief Enable or disable the AHB3 peripheral clock.
<>	144:ef7eb2e8f9f7	827	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	828	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	829	* using it.
<>	144:ef7eb2e8f9f7	830	* @{
<>	144:ef7eb2e8f9f7	831	*/
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	834	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	835	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	836	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
<>	144:ef7eb2e8f9f7	837	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	838	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
<>	144:ef7eb2e8f9f7	839	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	840	} while(0)
<>	144:ef7eb2e8f9f7	841	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	844	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	845	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	846	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
<>	144:ef7eb2e8f9f7	847	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	848	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
<>	144:ef7eb2e8f9f7	849	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	850	} while(0)
<>	144:ef7eb2e8f9f7	851	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	855	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
<>	144:ef7eb2e8f9f7	856	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	859	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
<>	144:ef7eb2e8f9f7	860	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/**
<>	144:ef7eb2e8f9f7	863	* @}
<>	144:ef7eb2e8f9f7	864	*/
<>	144:ef7eb2e8f9f7	865
<>	144:ef7eb2e8f9f7	866	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	867	* @brief Enable or disable the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	868	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	869	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	870	* using it.
<>	144:ef7eb2e8f9f7	871	* @{
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	875	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	876	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
<>	144:ef7eb2e8f9f7	877	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	878	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
<>	144:ef7eb2e8f9f7	879	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	880	} while(0)
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	883	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	884	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	885	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
<>	144:ef7eb2e8f9f7	886	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	887	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
<>	144:ef7eb2e8f9f7	888	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	889	} while(0)
<>	144:ef7eb2e8f9f7	890	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	893	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	894	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	895	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
<>	144:ef7eb2e8f9f7	896	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	897	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
<>	144:ef7eb2e8f9f7	898	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	899	} while(0)
<>	144:ef7eb2e8f9f7	900	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	903	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	904	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	905	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
<>	144:ef7eb2e8f9f7	906	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	907	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
<>	144:ef7eb2e8f9f7	908	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	909	} while(0)
<>	144:ef7eb2e8f9f7	910	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	911
<>	144:ef7eb2e8f9f7	912	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	913	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	914	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
<>	144:ef7eb2e8f9f7	915	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	916	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
<>	144:ef7eb2e8f9f7	917	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	918	} while(0)
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	921	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	922	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
<>	144:ef7eb2e8f9f7	923	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	924	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
<>	144:ef7eb2e8f9f7	925	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	926	} while(0)
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	#if defined(LCD)
<>	144:ef7eb2e8f9f7	929	#define __HAL_RCC_LCD_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	930	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	931	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
<>	144:ef7eb2e8f9f7	932	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	933	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
<>	144:ef7eb2e8f9f7	934	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	935	} while(0)
<>	144:ef7eb2e8f9f7	936	#endif /* LCD */
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	#if defined(RCC_APB1ENR1_RTCAPBEN)
<>	144:ef7eb2e8f9f7	939	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	940	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	941	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
<>	144:ef7eb2e8f9f7	942	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	943	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
<>	144:ef7eb2e8f9f7	944	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	945	} while(0)
<>	144:ef7eb2e8f9f7	946	#endif /* RCC_APB1ENR1_RTCAPBEN */
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	949	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	950	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
<>	144:ef7eb2e8f9f7	951	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	952	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
<>	144:ef7eb2e8f9f7	953	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	954	} while(0)
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	957	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	958	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	959	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
<>	144:ef7eb2e8f9f7	960	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	961	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
<>	144:ef7eb2e8f9f7	962	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	963	} while(0)
<>	144:ef7eb2e8f9f7	964	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	967	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	968	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
<>	144:ef7eb2e8f9f7	969	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	970	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
<>	144:ef7eb2e8f9f7	971	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	972	} while(0)
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	975	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	976	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
<>	144:ef7eb2e8f9f7	977	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	978	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
<>	144:ef7eb2e8f9f7	979	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	980	} while(0)
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	#if defined(USART3)
<>	144:ef7eb2e8f9f7	983	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	984	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	985	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
<>	144:ef7eb2e8f9f7	986	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	987	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
<>	144:ef7eb2e8f9f7	988	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	989	} while(0)
<>	144:ef7eb2e8f9f7	990	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	#if defined(UART4)
<>	144:ef7eb2e8f9f7	993	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	994	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	995	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
<>	144:ef7eb2e8f9f7	996	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	997	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
<>	144:ef7eb2e8f9f7	998	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	999	} while(0)
<>	144:ef7eb2e8f9f7	1000	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	#if defined(UART5)
<>	144:ef7eb2e8f9f7	1003	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1004	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1005	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
<>	144:ef7eb2e8f9f7	1006	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1007	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
<>	144:ef7eb2e8f9f7	1008	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1009	} while(0)
<>	144:ef7eb2e8f9f7	1010	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1013	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1014	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
<>	144:ef7eb2e8f9f7	1015	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1016	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
<>	144:ef7eb2e8f9f7	1017	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1018	} while(0)
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	1021	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1022	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1023	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
<>	144:ef7eb2e8f9f7	1024	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1025	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
<>	144:ef7eb2e8f9f7	1026	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1027	} while(0)
<>	144:ef7eb2e8f9f7	1028	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1031	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1032	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
<>	144:ef7eb2e8f9f7	1033	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1034	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
<>	144:ef7eb2e8f9f7	1035	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1036	} while(0)
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1039	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1040	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1041	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
<>	144:ef7eb2e8f9f7	1042	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1043	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
<>	144:ef7eb2e8f9f7	1044	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1045	} while(0)
<>	144:ef7eb2e8f9f7	1046	#endif /* CRS */
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1049	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1050	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
<>	144:ef7eb2e8f9f7	1051	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1052	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
<>	144:ef7eb2e8f9f7	1053	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1054	} while(0)
<>	144:ef7eb2e8f9f7	1055
<>	144:ef7eb2e8f9f7	1056	#if defined(USB)
<>	144:ef7eb2e8f9f7	1057	#define __HAL_RCC_USB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1058	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1059	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
<>	144:ef7eb2e8f9f7	1060	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1061	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
<>	144:ef7eb2e8f9f7	1062	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1063	} while(0)
<>	144:ef7eb2e8f9f7	1064	#endif /* USB */
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1067	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1068	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
<>	144:ef7eb2e8f9f7	1069	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1070	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
<>	144:ef7eb2e8f9f7	1071	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1072	} while(0)
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1075	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1076	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
<>	144:ef7eb2e8f9f7	1077	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1078	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
<>	144:ef7eb2e8f9f7	1079	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1080	} while(0)
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1083	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1084	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
<>	144:ef7eb2e8f9f7	1085	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1086	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
<>	144:ef7eb2e8f9f7	1087	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1088	} while(0)
<>	144:ef7eb2e8f9f7	1089
<>	144:ef7eb2e8f9f7	1090	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1091	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1092	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
<>	144:ef7eb2e8f9f7	1093	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1094	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
<>	144:ef7eb2e8f9f7	1095	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1096	} while(0)
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1099	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1100	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
<>	144:ef7eb2e8f9f7	1101	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1102	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
<>	144:ef7eb2e8f9f7	1103	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1104	} while(0)
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1107	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1108	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
<>	144:ef7eb2e8f9f7	1109	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1110	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
<>	144:ef7eb2e8f9f7	1111	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1112	} while(0)
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1115	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1116	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
<>	144:ef7eb2e8f9f7	1117	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1118	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
<>	144:ef7eb2e8f9f7	1119	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1120	} while(0)
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	1126	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
<>	144:ef7eb2e8f9f7	1127	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	1130	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
<>	144:ef7eb2e8f9f7	1131	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	1132
<>	144:ef7eb2e8f9f7	1133	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	1134	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
<>	144:ef7eb2e8f9f7	1135	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	1136
<>	144:ef7eb2e8f9f7	1137	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
<>	144:ef7eb2e8f9f7	1140
<>	144:ef7eb2e8f9f7	1141	#if defined(LCD)
<>	144:ef7eb2e8f9f7	1142	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
<>	144:ef7eb2e8f9f7	1143	#endif /* LCD */
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	#if defined(RCC_APB1ENR1_RTCAPBEN)
<>	144:ef7eb2e8f9f7	1146	#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
<>	144:ef7eb2e8f9f7	1147	#endif /* RCC_APB1ENR1_RTCAPBEN */
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	1150	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
<>	144:ef7eb2e8f9f7	1151	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	#if defined(USART3)
<>	144:ef7eb2e8f9f7	1158	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
<>	144:ef7eb2e8f9f7	1159	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	#if defined(UART4)
<>	144:ef7eb2e8f9f7	1162	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
<>	144:ef7eb2e8f9f7	1163	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	1164
<>	144:ef7eb2e8f9f7	1165	#if defined(UART5)
<>	144:ef7eb2e8f9f7	1166	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
<>	144:ef7eb2e8f9f7	1167	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
<>	144:ef7eb2e8f9f7	1170
<>	144:ef7eb2e8f9f7	1171	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	1172	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
<>	144:ef7eb2e8f9f7	1173	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1178	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
<>	144:ef7eb2e8f9f7	1179	#endif /* CRS */
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	#if defined(USB)
<>	144:ef7eb2e8f9f7	1184	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
<>	144:ef7eb2e8f9f7	1185	#endif /* USB */
<>	144:ef7eb2e8f9f7	1186
<>	144:ef7eb2e8f9f7	1187	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/**
<>	144:ef7eb2e8f9f7	1202	* @}
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	1206	* @brief Enable or disable the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	1207	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1208	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1209	* using it.
<>	144:ef7eb2e8f9f7	1210	* @{
<>	144:ef7eb2e8f9f7	1211	*/
<>	144:ef7eb2e8f9f7	1212
<>	144:ef7eb2e8f9f7	1213	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1214	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1215	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
<>	144:ef7eb2e8f9f7	1216	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1217	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
<>	144:ef7eb2e8f9f7	1218	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1219	} while(0)
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1222	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1223	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
<>	144:ef7eb2e8f9f7	1224	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1225	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
<>	144:ef7eb2e8f9f7	1226	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1227	} while(0)
<>	144:ef7eb2e8f9f7	1228
<>	144:ef7eb2e8f9f7	1229	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
<>	144:ef7eb2e8f9f7	1230	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1231	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1232	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
<>	144:ef7eb2e8f9f7	1233	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1234	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
<>	144:ef7eb2e8f9f7	1235	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1236	} while(0)
<>	144:ef7eb2e8f9f7	1237	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
<>	144:ef7eb2e8f9f7	1238
<>	144:ef7eb2e8f9f7	1239	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1240	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1241	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
<>	144:ef7eb2e8f9f7	1242	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1243	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
<>	144:ef7eb2e8f9f7	1244	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1245	} while(0)
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1248	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1249	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
<>	144:ef7eb2e8f9f7	1250	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1251	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
<>	144:ef7eb2e8f9f7	1252	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1253	} while(0)
<>	144:ef7eb2e8f9f7	1254
<>	144:ef7eb2e8f9f7	1255	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	1256	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1257	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1258	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
<>	144:ef7eb2e8f9f7	1259	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1260	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
<>	144:ef7eb2e8f9f7	1261	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1262	} while(0)
<>	144:ef7eb2e8f9f7	1263	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1266	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1267	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
<>	144:ef7eb2e8f9f7	1268	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1269	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
<>	144:ef7eb2e8f9f7	1270	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1271	} while(0)
<>	144:ef7eb2e8f9f7	1272
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1275	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1276	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
<>	144:ef7eb2e8f9f7	1277	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1278	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
<>	144:ef7eb2e8f9f7	1279	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1280	} while(0)
<>	144:ef7eb2e8f9f7	1281
<>	144:ef7eb2e8f9f7	1282	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1283	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1284	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
<>	144:ef7eb2e8f9f7	1285	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1286	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
<>	144:ef7eb2e8f9f7	1287	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1288	} while(0)
<>	144:ef7eb2e8f9f7	1289
<>	144:ef7eb2e8f9f7	1290	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	1291	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1292	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1293	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
<>	144:ef7eb2e8f9f7	1294	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1295	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
<>	144:ef7eb2e8f9f7	1296	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1297	} while(0)
<>	144:ef7eb2e8f9f7	1298	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1301	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1302	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
<>	144:ef7eb2e8f9f7	1303	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1304	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
<>	144:ef7eb2e8f9f7	1305	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1306	} while(0)
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	1309	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1310	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1311	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
<>	144:ef7eb2e8f9f7	1312	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1313	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
<>	144:ef7eb2e8f9f7	1314	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1315	} while(0)
<>	144:ef7eb2e8f9f7	1316	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	1319	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1320	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1321	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
<>	144:ef7eb2e8f9f7	1322	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1323	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
<>	144:ef7eb2e8f9f7	1324	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1325	} while(0)
<>	144:ef7eb2e8f9f7	1326	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
<>	144:ef7eb2e8f9f7	1332	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
<>	144:ef7eb2e8f9f7	1333	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	1340	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
<>	144:ef7eb2e8f9f7	1341	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
<>	144:ef7eb2e8f9f7	1346
<>	144:ef7eb2e8f9f7	1347	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
<>	144:ef7eb2e8f9f7	1348
<>	144:ef7eb2e8f9f7	1349	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	1350	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
<>	144:ef7eb2e8f9f7	1351	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	1356	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
<>	144:ef7eb2e8f9f7	1357	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	1360	#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
<>	144:ef7eb2e8f9f7	1361	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363	/**
<>	144:ef7eb2e8f9f7	1364	* @}
<>	144:ef7eb2e8f9f7	1365	*/
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1368	* @brief Check whether the AHB1 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	1369	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1370	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1371	* using it.
<>	144:ef7eb2e8f9f7	1372	* @{
<>	144:ef7eb2e8f9f7	1373	*/
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
<>	144:ef7eb2e8f9f7	1384
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/**
<>	144:ef7eb2e8f9f7	1397	* @}
<>	144:ef7eb2e8f9f7	1398	*/
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1401	* @brief Check whether the AHB2 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	1402	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1403	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1404	* using it.
<>	144:ef7eb2e8f9f7	1405	* @{
<>	144:ef7eb2e8f9f7	1406	*/
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	1415	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
<>	144:ef7eb2e8f9f7	1416	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	1419	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
<>	144:ef7eb2e8f9f7	1420	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	1423	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
<>	144:ef7eb2e8f9f7	1424	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	1425
<>	144:ef7eb2e8f9f7	1426	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	1427	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
<>	144:ef7eb2e8f9f7	1428	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	1433	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
<>	144:ef7eb2e8f9f7	1434	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	1435
<>	144:ef7eb2e8f9f7	1436	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	#if defined(AES)
<>	144:ef7eb2e8f9f7	1439	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
<>	144:ef7eb2e8f9f7	1440	#endif /* AES */
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
<>	144:ef7eb2e8f9f7	1450
<>	144:ef7eb2e8f9f7	1451	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	1452	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
<>	144:ef7eb2e8f9f7	1453	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	1456	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
<>	144:ef7eb2e8f9f7	1457	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	1460	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
<>	144:ef7eb2e8f9f7	1461	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	1464	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
<>	144:ef7eb2e8f9f7	1465	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	1466
<>	144:ef7eb2e8f9f7	1467	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
<>	144:ef7eb2e8f9f7	1468
<>	144:ef7eb2e8f9f7	1469	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	1470	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
<>	144:ef7eb2e8f9f7	1471	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	#if defined(AES)
<>	144:ef7eb2e8f9f7	1476	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
<>	144:ef7eb2e8f9f7	1477	#endif /* AES */
<>	144:ef7eb2e8f9f7	1478
<>	144:ef7eb2e8f9f7	1479	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	/**
<>	144:ef7eb2e8f9f7	1482	* @}
<>	144:ef7eb2e8f9f7	1483	*/
<>	144:ef7eb2e8f9f7	1484
<>	144:ef7eb2e8f9f7	1485	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1486	* @brief Check whether the AHB3 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	1487	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1488	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1489	* using it.
<>	144:ef7eb2e8f9f7	1490	* @{
<>	144:ef7eb2e8f9f7	1491	*/
<>	144:ef7eb2e8f9f7	1492
<>	144:ef7eb2e8f9f7	1493	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	1494	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
<>	144:ef7eb2e8f9f7	1495	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	1496
<>	144:ef7eb2e8f9f7	1497	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	1498	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
<>	144:ef7eb2e8f9f7	1499	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	1502	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
<>	144:ef7eb2e8f9f7	1503	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	1506	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
<>	144:ef7eb2e8f9f7	1507	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	1508
<>	144:ef7eb2e8f9f7	1509	/**
<>	144:ef7eb2e8f9f7	1510	* @}
<>	144:ef7eb2e8f9f7	1511	*/
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1514	* @brief Check whether the APB1 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	1515	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1516	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1517	* using it.
<>	144:ef7eb2e8f9f7	1518	* @{
<>	144:ef7eb2e8f9f7	1519	*/
<>	144:ef7eb2e8f9f7	1520
<>	144:ef7eb2e8f9f7	1521	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	1524	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
<>	144:ef7eb2e8f9f7	1525	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	1528	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
<>	144:ef7eb2e8f9f7	1529	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	1532	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
<>	144:ef7eb2e8f9f7	1533	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	1534
<>	144:ef7eb2e8f9f7	1535	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
<>	144:ef7eb2e8f9f7	1536
<>	144:ef7eb2e8f9f7	1537	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
<>	144:ef7eb2e8f9f7	1538
<>	144:ef7eb2e8f9f7	1539	#if defined(LCD)
<>	144:ef7eb2e8f9f7	1540	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
<>	144:ef7eb2e8f9f7	1541	#endif /* LCD */
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	#if defined(RCC_APB1ENR1_RTCAPBEN)
<>	144:ef7eb2e8f9f7	1544	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
<>	144:ef7eb2e8f9f7	1545	#endif /* RCC_APB1ENR1_RTCAPBEN */
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	1550	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
<>	144:ef7eb2e8f9f7	1551	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	#if defined(USART3)
<>	144:ef7eb2e8f9f7	1558	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
<>	144:ef7eb2e8f9f7	1559	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	#if defined(UART4)
<>	144:ef7eb2e8f9f7	1562	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
<>	144:ef7eb2e8f9f7	1563	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	1564
<>	144:ef7eb2e8f9f7	1565	#if defined(UART5)
<>	144:ef7eb2e8f9f7	1566	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
<>	144:ef7eb2e8f9f7	1567	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	1572	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
<>	144:ef7eb2e8f9f7	1573	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	1574
<>	144:ef7eb2e8f9f7	1575	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
<>	144:ef7eb2e8f9f7	1576
<>	144:ef7eb2e8f9f7	1577	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1578	#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
<>	144:ef7eb2e8f9f7	1579	#endif /* CRS */
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	#if defined(USB)
<>	144:ef7eb2e8f9f7	1584	#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
<>	144:ef7eb2e8f9f7	1585	#endif /* USB */
<>	144:ef7eb2e8f9f7	1586
<>	144:ef7eb2e8f9f7	1587	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
<>	144:ef7eb2e8f9f7	1588
<>	144:ef7eb2e8f9f7	1589	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
<>	144:ef7eb2e8f9f7	1590
<>	144:ef7eb2e8f9f7	1591	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
<>	144:ef7eb2e8f9f7	1596
<>	144:ef7eb2e8f9f7	1597	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
<>	144:ef7eb2e8f9f7	1600
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
<>	144:ef7eb2e8f9f7	1603
<>	144:ef7eb2e8f9f7	1604	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	1605	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
<>	144:ef7eb2e8f9f7	1606	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	1607
<>	144:ef7eb2e8f9f7	1608	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	1609	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
<>	144:ef7eb2e8f9f7	1610	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	1611
<>	144:ef7eb2e8f9f7	1612	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	1613	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
<>	144:ef7eb2e8f9f7	1614	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
<>	144:ef7eb2e8f9f7	1619
<>	144:ef7eb2e8f9f7	1620	#if defined(LCD)
<>	144:ef7eb2e8f9f7	1621	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
<>	144:ef7eb2e8f9f7	1622	#endif /* LCD */
<>	144:ef7eb2e8f9f7	1623
<>	144:ef7eb2e8f9f7	1624	#if defined(RCC_APB1ENR1_RTCAPBEN)
<>	144:ef7eb2e8f9f7	1625	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
<>	144:ef7eb2e8f9f7	1626	#endif /* RCC_APB1ENR1_RTCAPBEN */
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
<>	144:ef7eb2e8f9f7	1629
<>	144:ef7eb2e8f9f7	1630	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	1631	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
<>	144:ef7eb2e8f9f7	1632	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	1633
<>	144:ef7eb2e8f9f7	1634	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
<>	144:ef7eb2e8f9f7	1635
<>	144:ef7eb2e8f9f7	1636	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	#if defined(USART3)
<>	144:ef7eb2e8f9f7	1639	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
<>	144:ef7eb2e8f9f7	1640	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	1641
<>	144:ef7eb2e8f9f7	1642	#if defined(UART4)
<>	144:ef7eb2e8f9f7	1643	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
<>	144:ef7eb2e8f9f7	1644	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	1645
<>	144:ef7eb2e8f9f7	1646	#if defined(UART5)
<>	144:ef7eb2e8f9f7	1647	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
<>	144:ef7eb2e8f9f7	1648	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
<>	144:ef7eb2e8f9f7	1651
<>	144:ef7eb2e8f9f7	1652	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	1653	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
<>	144:ef7eb2e8f9f7	1654	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
<>	144:ef7eb2e8f9f7	1657
<>	144:ef7eb2e8f9f7	1658	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1659	#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
<>	144:ef7eb2e8f9f7	1660	#endif /* CRS */
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	#if defined(USB)
<>	144:ef7eb2e8f9f7	1665	#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
<>	144:ef7eb2e8f9f7	1666	#endif /* USB */
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
<>	144:ef7eb2e8f9f7	1669
<>	144:ef7eb2e8f9f7	1670	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
<>	144:ef7eb2e8f9f7	1673
<>	144:ef7eb2e8f9f7	1674	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
<>	144:ef7eb2e8f9f7	1677
<>	144:ef7eb2e8f9f7	1678	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
<>	144:ef7eb2e8f9f7	1679
<>	144:ef7eb2e8f9f7	1680	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/**
<>	144:ef7eb2e8f9f7	1683	* @}
<>	144:ef7eb2e8f9f7	1684	*/
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1687	* @brief Check whether the APB2 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	1688	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1689	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1690	* using it.
<>	144:ef7eb2e8f9f7	1691	* @{
<>	144:ef7eb2e8f9f7	1692	*/
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
<>	144:ef7eb2e8f9f7	1695
<>	144:ef7eb2e8f9f7	1696	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
<>	144:ef7eb2e8f9f7	1699	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
<>	144:ef7eb2e8f9f7	1700	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
<>	144:ef7eb2e8f9f7	1701
<>	144:ef7eb2e8f9f7	1702	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
<>	144:ef7eb2e8f9f7	1705
<>	144:ef7eb2e8f9f7	1706	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	1707	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
<>	144:ef7eb2e8f9f7	1708	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	1709
<>	144:ef7eb2e8f9f7	1710	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
<>	144:ef7eb2e8f9f7	1711
<>	144:ef7eb2e8f9f7	1712	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
<>	144:ef7eb2e8f9f7	1713
<>	144:ef7eb2e8f9f7	1714	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
<>	144:ef7eb2e8f9f7	1715
<>	144:ef7eb2e8f9f7	1716	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	1717	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
<>	144:ef7eb2e8f9f7	1718	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
<>	144:ef7eb2e8f9f7	1721
<>	144:ef7eb2e8f9f7	1722	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	1723	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
<>	144:ef7eb2e8f9f7	1724	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	1725
<>	144:ef7eb2e8f9f7	1726	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	1727	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
<>	144:ef7eb2e8f9f7	1728	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
<>	144:ef7eb2e8f9f7	1732
<>	144:ef7eb2e8f9f7	1733	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
<>	144:ef7eb2e8f9f7	1734	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
<>	144:ef7eb2e8f9f7	1735	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
<>	144:ef7eb2e8f9f7	1736
<>	144:ef7eb2e8f9f7	1737	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
<>	144:ef7eb2e8f9f7	1738
<>	144:ef7eb2e8f9f7	1739	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	1742	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
<>	144:ef7eb2e8f9f7	1743	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
<>	144:ef7eb2e8f9f7	1746
<>	144:ef7eb2e8f9f7	1747	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
<>	144:ef7eb2e8f9f7	1750
<>	144:ef7eb2e8f9f7	1751	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	1752	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
<>	144:ef7eb2e8f9f7	1753	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	1754
<>	144:ef7eb2e8f9f7	1755	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	1758	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
<>	144:ef7eb2e8f9f7	1759	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	1762	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
<>	144:ef7eb2e8f9f7	1763	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	1764
<>	144:ef7eb2e8f9f7	1765	/**
<>	144:ef7eb2e8f9f7	1766	* @}
<>	144:ef7eb2e8f9f7	1767	*/
<>	144:ef7eb2e8f9f7	1768
<>	144:ef7eb2e8f9f7	1769	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	1770	* @brief Force or release AHB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1771	* @{
<>	144:ef7eb2e8f9f7	1772	*/
<>	144:ef7eb2e8f9f7	1773	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785
<>	144:ef7eb2e8f9f7	1786	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
<>	144:ef7eb2e8f9f7	1787
<>	144:ef7eb2e8f9f7	1788	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
<>	144:ef7eb2e8f9f7	1789
<>	144:ef7eb2e8f9f7	1790	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
<>	144:ef7eb2e8f9f7	1791
<>	144:ef7eb2e8f9f7	1792	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/**
<>	144:ef7eb2e8f9f7	1799	* @}
<>	144:ef7eb2e8f9f7	1800	*/
<>	144:ef7eb2e8f9f7	1801
<>	144:ef7eb2e8f9f7	1802	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	1803	* @brief Force or release AHB2 peripheral reset.
<>	144:ef7eb2e8f9f7	1804	* @{
<>	144:ef7eb2e8f9f7	1805	*/
<>	144:ef7eb2e8f9f7	1806	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1807
<>	144:ef7eb2e8f9f7	1808	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
<>	144:ef7eb2e8f9f7	1809
<>	144:ef7eb2e8f9f7	1810	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
<>	144:ef7eb2e8f9f7	1813
<>	144:ef7eb2e8f9f7	1814	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	1815	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
<>	144:ef7eb2e8f9f7	1816	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	1817
<>	144:ef7eb2e8f9f7	1818	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	1819	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
<>	144:ef7eb2e8f9f7	1820	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	1821
<>	144:ef7eb2e8f9f7	1822	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	1823	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
<>	144:ef7eb2e8f9f7	1824	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	1825
<>	144:ef7eb2e8f9f7	1826	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	1827	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
<>	144:ef7eb2e8f9f7	1828	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
<>	144:ef7eb2e8f9f7	1831
<>	144:ef7eb2e8f9f7	1832	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	1833	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
<>	144:ef7eb2e8f9f7	1834	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
<>	144:ef7eb2e8f9f7	1837
<>	144:ef7eb2e8f9f7	1838	#if defined(AES)
<>	144:ef7eb2e8f9f7	1839	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
<>	144:ef7eb2e8f9f7	1840	#endif /* AES */
<>	144:ef7eb2e8f9f7	1841
<>	144:ef7eb2e8f9f7	1842	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
<>	144:ef7eb2e8f9f7	1843
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
<>	144:ef7eb2e8f9f7	1846
<>	144:ef7eb2e8f9f7	1847	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
<>	144:ef7eb2e8f9f7	1850
<>	144:ef7eb2e8f9f7	1851	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
<>	144:ef7eb2e8f9f7	1852
<>	144:ef7eb2e8f9f7	1853	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	1854	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
<>	144:ef7eb2e8f9f7	1855	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	1856
<>	144:ef7eb2e8f9f7	1857	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	1858	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
<>	144:ef7eb2e8f9f7	1859	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	1860
<>	144:ef7eb2e8f9f7	1861	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	1862	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
<>	144:ef7eb2e8f9f7	1863	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	1866	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
<>	144:ef7eb2e8f9f7	1867	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	1868
<>	144:ef7eb2e8f9f7	1869	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	1872	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
<>	144:ef7eb2e8f9f7	1873	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	1874
<>	144:ef7eb2e8f9f7	1875	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	#if defined(AES)
<>	144:ef7eb2e8f9f7	1878	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
<>	144:ef7eb2e8f9f7	1879	#endif /* AES */
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
<>	144:ef7eb2e8f9f7	1882
<>	144:ef7eb2e8f9f7	1883	/**
<>	144:ef7eb2e8f9f7	1884	* @}
<>	144:ef7eb2e8f9f7	1885	*/
<>	144:ef7eb2e8f9f7	1886
<>	144:ef7eb2e8f9f7	1887	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	1888	* @brief Force or release AHB3 peripheral reset.
<>	144:ef7eb2e8f9f7	1889	* @{
<>	144:ef7eb2e8f9f7	1890	*/
<>	144:ef7eb2e8f9f7	1891	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1892
<>	144:ef7eb2e8f9f7	1893	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	1894	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
<>	144:ef7eb2e8f9f7	1895	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	1898	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
<>	144:ef7eb2e8f9f7	1899	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	1900
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
<>	144:ef7eb2e8f9f7	1903
<>	144:ef7eb2e8f9f7	1904	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	1905	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
<>	144:ef7eb2e8f9f7	1906	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	1907
<>	144:ef7eb2e8f9f7	1908	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	1909	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
<>	144:ef7eb2e8f9f7	1910	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	1911
<>	144:ef7eb2e8f9f7	1912	/**
<>	144:ef7eb2e8f9f7	1913	* @}
<>	144:ef7eb2e8f9f7	1914	*/
<>	144:ef7eb2e8f9f7	1915
<>	144:ef7eb2e8f9f7	1916	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	1917	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1918	* @{
<>	144:ef7eb2e8f9f7	1919	*/
<>	144:ef7eb2e8f9f7	1920	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1921
<>	144:ef7eb2e8f9f7	1922	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	1925	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
<>	144:ef7eb2e8f9f7	1926	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	1927
<>	144:ef7eb2e8f9f7	1928	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	1929	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
<>	144:ef7eb2e8f9f7	1930	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	1931
<>	144:ef7eb2e8f9f7	1932	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	1933	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
<>	144:ef7eb2e8f9f7	1934	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	1935
<>	144:ef7eb2e8f9f7	1936	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
<>	144:ef7eb2e8f9f7	1937
<>	144:ef7eb2e8f9f7	1938	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
<>	144:ef7eb2e8f9f7	1939
<>	144:ef7eb2e8f9f7	1940	#if defined(LCD)
<>	144:ef7eb2e8f9f7	1941	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
<>	144:ef7eb2e8f9f7	1942	#endif /* LCD */
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	1945	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
<>	144:ef7eb2e8f9f7	1946	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	1947
<>	144:ef7eb2e8f9f7	1948	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
<>	144:ef7eb2e8f9f7	1949
<>	144:ef7eb2e8f9f7	1950	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
<>	144:ef7eb2e8f9f7	1951
<>	144:ef7eb2e8f9f7	1952	#if defined(USART3)
<>	144:ef7eb2e8f9f7	1953	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
<>	144:ef7eb2e8f9f7	1954	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	1955
<>	144:ef7eb2e8f9f7	1956	#if defined(UART4)
<>	144:ef7eb2e8f9f7	1957	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
<>	144:ef7eb2e8f9f7	1958	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	#if defined(UART5)
<>	144:ef7eb2e8f9f7	1961	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
<>	144:ef7eb2e8f9f7	1962	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	1963
<>	144:ef7eb2e8f9f7	1964	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	1967	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
<>	144:ef7eb2e8f9f7	1968	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	1969
<>	144:ef7eb2e8f9f7	1970	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1973	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
<>	144:ef7eb2e8f9f7	1974	#endif /* CRS */
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
<>	144:ef7eb2e8f9f7	1977
<>	144:ef7eb2e8f9f7	1978	#if defined(USB)
<>	144:ef7eb2e8f9f7	1979	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
<>	144:ef7eb2e8f9f7	1980	#endif /* USB */
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
<>	144:ef7eb2e8f9f7	1987
<>	144:ef7eb2e8f9f7	1988	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
<>	144:ef7eb2e8f9f7	1991
<>	144:ef7eb2e8f9f7	1992	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
<>	144:ef7eb2e8f9f7	1995
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
<>	144:ef7eb2e8f9f7	1998
<>	144:ef7eb2e8f9f7	1999	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
<>	144:ef7eb2e8f9f7	2000
<>	144:ef7eb2e8f9f7	2001	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	2002	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
<>	144:ef7eb2e8f9f7	2003	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	2004
<>	144:ef7eb2e8f9f7	2005	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	2006	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
<>	144:ef7eb2e8f9f7	2007	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	2008
<>	144:ef7eb2e8f9f7	2009	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	2010	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
<>	144:ef7eb2e8f9f7	2011	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	2012
<>	144:ef7eb2e8f9f7	2013	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
<>	144:ef7eb2e8f9f7	2014
<>	144:ef7eb2e8f9f7	2015	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	#if defined(LCD)
<>	144:ef7eb2e8f9f7	2018	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
<>	144:ef7eb2e8f9f7	2019	#endif /* LCD */
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	2022	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
<>	144:ef7eb2e8f9f7	2023	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	2024
<>	144:ef7eb2e8f9f7	2025	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
<>	144:ef7eb2e8f9f7	2026
<>	144:ef7eb2e8f9f7	2027	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	#if defined(USART3)
<>	144:ef7eb2e8f9f7	2030	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
<>	144:ef7eb2e8f9f7	2031	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	2032
<>	144:ef7eb2e8f9f7	2033	#if defined(UART4)
<>	144:ef7eb2e8f9f7	2034	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
<>	144:ef7eb2e8f9f7	2035	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	2036
<>	144:ef7eb2e8f9f7	2037	#if defined(UART5)
<>	144:ef7eb2e8f9f7	2038	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
<>	144:ef7eb2e8f9f7	2039	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	2040
<>	144:ef7eb2e8f9f7	2041	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
<>	144:ef7eb2e8f9f7	2042
<>	144:ef7eb2e8f9f7	2043	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	2044	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
<>	144:ef7eb2e8f9f7	2045	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	2046
<>	144:ef7eb2e8f9f7	2047	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
<>	144:ef7eb2e8f9f7	2048
<>	144:ef7eb2e8f9f7	2049	#if defined(CRS)
<>	144:ef7eb2e8f9f7	2050	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
<>	144:ef7eb2e8f9f7	2051	#endif /* CRS */
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	#if defined(USB)
<>	144:ef7eb2e8f9f7	2056	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
<>	144:ef7eb2e8f9f7	2057	#endif /* USB */
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
<>	144:ef7eb2e8f9f7	2060
<>	144:ef7eb2e8f9f7	2061	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
<>	144:ef7eb2e8f9f7	2072
<>	144:ef7eb2e8f9f7	2073	/**
<>	144:ef7eb2e8f9f7	2074	* @}
<>	144:ef7eb2e8f9f7	2075	*/
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	2078	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	2079	* @{
<>	144:ef7eb2e8f9f7	2080	*/
<>	144:ef7eb2e8f9f7	2081	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	2082
<>	144:ef7eb2e8f9f7	2083	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
<>	144:ef7eb2e8f9f7	2084
<>	144:ef7eb2e8f9f7	2085	#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
<>	144:ef7eb2e8f9f7	2086	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
<>	144:ef7eb2e8f9f7	2087	#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
<>	144:ef7eb2e8f9f7	2088
<>	144:ef7eb2e8f9f7	2089	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
<>	144:ef7eb2e8f9f7	2090
<>	144:ef7eb2e8f9f7	2091	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
<>	144:ef7eb2e8f9f7	2092
<>	144:ef7eb2e8f9f7	2093	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2094	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
<>	144:ef7eb2e8f9f7	2095	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2096
<>	144:ef7eb2e8f9f7	2097	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2104	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
<>	144:ef7eb2e8f9f7	2105	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2110	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
<>	144:ef7eb2e8f9f7	2111	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2114	#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
<>	144:ef7eb2e8f9f7	2115	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2116
<>	144:ef7eb2e8f9f7	2117
<>	144:ef7eb2e8f9f7	2118	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
<>	144:ef7eb2e8f9f7	2121
<>	144:ef7eb2e8f9f7	2122	#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
<>	144:ef7eb2e8f9f7	2123	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
<>	144:ef7eb2e8f9f7	2124	#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
<>	144:ef7eb2e8f9f7	2127
<>	144:ef7eb2e8f9f7	2128	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2131	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
<>	144:ef7eb2e8f9f7	2132	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2133
<>	144:ef7eb2e8f9f7	2134	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
<>	144:ef7eb2e8f9f7	2137
<>	144:ef7eb2e8f9f7	2138	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
<>	144:ef7eb2e8f9f7	2139
<>	144:ef7eb2e8f9f7	2140	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2141	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
<>	144:ef7eb2e8f9f7	2142	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2143
<>	144:ef7eb2e8f9f7	2144	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
<>	144:ef7eb2e8f9f7	2145
<>	144:ef7eb2e8f9f7	2146	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2147	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
<>	144:ef7eb2e8f9f7	2148	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2149
<>	144:ef7eb2e8f9f7	2150	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2151	#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
<>	144:ef7eb2e8f9f7	2152	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2153
<>	144:ef7eb2e8f9f7	2154	/**
<>	144:ef7eb2e8f9f7	2155	* @}
<>	144:ef7eb2e8f9f7	2156	*/
<>	144:ef7eb2e8f9f7	2157
<>	144:ef7eb2e8f9f7	2158	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	2159	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2160	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2161	* power consumption.
<>	144:ef7eb2e8f9f7	2162	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2163	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2164	* @{
<>	144:ef7eb2e8f9f7	2165	*/
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
<>	144:ef7eb2e8f9f7	2168
<>	144:ef7eb2e8f9f7	2169	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
<>	144:ef7eb2e8f9f7	2172
<>	144:ef7eb2e8f9f7	2173	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
<>	144:ef7eb2e8f9f7	2174
<>	144:ef7eb2e8f9f7	2175	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
<>	144:ef7eb2e8f9f7	2176
<>	144:ef7eb2e8f9f7	2177	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179
<>	144:ef7eb2e8f9f7	2180	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
<>	144:ef7eb2e8f9f7	2183
<>	144:ef7eb2e8f9f7	2184	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
<>	144:ef7eb2e8f9f7	2185
<>	144:ef7eb2e8f9f7	2186	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
<>	144:ef7eb2e8f9f7	2187
<>	144:ef7eb2e8f9f7	2188	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
<>	144:ef7eb2e8f9f7	2189
<>	144:ef7eb2e8f9f7	2190	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
<>	144:ef7eb2e8f9f7	2191
<>	144:ef7eb2e8f9f7	2192	/**
<>	144:ef7eb2e8f9f7	2193	* @}
<>	144:ef7eb2e8f9f7	2194	*/
<>	144:ef7eb2e8f9f7	2195
<>	144:ef7eb2e8f9f7	2196	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	2197	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2198	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2199	* power consumption.
<>	144:ef7eb2e8f9f7	2200	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2201	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2202	* @{
<>	144:ef7eb2e8f9f7	2203	*/
<>	144:ef7eb2e8f9f7	2204
<>	144:ef7eb2e8f9f7	2205	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
<>	144:ef7eb2e8f9f7	2206
<>	144:ef7eb2e8f9f7	2207	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
<>	144:ef7eb2e8f9f7	2208
<>	144:ef7eb2e8f9f7	2209	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
<>	144:ef7eb2e8f9f7	2210
<>	144:ef7eb2e8f9f7	2211	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	2212	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
<>	144:ef7eb2e8f9f7	2213	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	2214
<>	144:ef7eb2e8f9f7	2215	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	2216	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
<>	144:ef7eb2e8f9f7	2217	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	2220	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
<>	144:ef7eb2e8f9f7	2221	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	2222
<>	144:ef7eb2e8f9f7	2223	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	2224	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
<>	144:ef7eb2e8f9f7	2225	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	2226
<>	144:ef7eb2e8f9f7	2227	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
<>	144:ef7eb2e8f9f7	2228
<>	144:ef7eb2e8f9f7	2229	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	2232	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
<>	144:ef7eb2e8f9f7	2233	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	#if defined(AES)
<>	144:ef7eb2e8f9f7	2238	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
<>	144:ef7eb2e8f9f7	2239	#endif /* AES */
<>	144:ef7eb2e8f9f7	2240
<>	144:ef7eb2e8f9f7	2241	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
<>	144:ef7eb2e8f9f7	2242
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
<>	144:ef7eb2e8f9f7	2245
<>	144:ef7eb2e8f9f7	2246	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
<>	144:ef7eb2e8f9f7	2247
<>	144:ef7eb2e8f9f7	2248	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
<>	144:ef7eb2e8f9f7	2249
<>	144:ef7eb2e8f9f7	2250	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	2251	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
<>	144:ef7eb2e8f9f7	2252	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	2253
<>	144:ef7eb2e8f9f7	2254	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	2255	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
<>	144:ef7eb2e8f9f7	2256	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	2257
<>	144:ef7eb2e8f9f7	2258	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	2259	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
<>	144:ef7eb2e8f9f7	2260	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	2261
<>	144:ef7eb2e8f9f7	2262	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	2263	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
<>	144:ef7eb2e8f9f7	2264	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	2265
<>	144:ef7eb2e8f9f7	2266	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	2271	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
<>	144:ef7eb2e8f9f7	2272	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
<>	144:ef7eb2e8f9f7	2275
<>	144:ef7eb2e8f9f7	2276	#if defined(AES)
<>	144:ef7eb2e8f9f7	2277	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
<>	144:ef7eb2e8f9f7	2278	#endif /* AES */
<>	144:ef7eb2e8f9f7	2279
<>	144:ef7eb2e8f9f7	2280	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	/**
<>	144:ef7eb2e8f9f7	2283	* @}
<>	144:ef7eb2e8f9f7	2284	*/
<>	144:ef7eb2e8f9f7	2285
<>	144:ef7eb2e8f9f7	2286	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	2287	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2288	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2289	* power consumption.
<>	144:ef7eb2e8f9f7	2290	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2291	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2292	* @{
<>	144:ef7eb2e8f9f7	2293	*/
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	2296	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
<>	144:ef7eb2e8f9f7	2297	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	2298
<>	144:ef7eb2e8f9f7	2299	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	2300	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
<>	144:ef7eb2e8f9f7	2301	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	2302
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	2305	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
<>	144:ef7eb2e8f9f7	2306	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	2307
<>	144:ef7eb2e8f9f7	2308	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	2309	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
<>	144:ef7eb2e8f9f7	2310	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	2311
<>	144:ef7eb2e8f9f7	2312	/**
<>	144:ef7eb2e8f9f7	2313	* @}
<>	144:ef7eb2e8f9f7	2314	*/
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	2317	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2318	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2319	* power consumption.
<>	144:ef7eb2e8f9f7	2320	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2321	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2322	* @{
<>	144:ef7eb2e8f9f7	2323	*/
<>	144:ef7eb2e8f9f7	2324
<>	144:ef7eb2e8f9f7	2325	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
<>	144:ef7eb2e8f9f7	2326
<>	144:ef7eb2e8f9f7	2327	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	2328	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
<>	144:ef7eb2e8f9f7	2329	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	2332	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
<>	144:ef7eb2e8f9f7	2333	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	2334
<>	144:ef7eb2e8f9f7	2335	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	2336	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
<>	144:ef7eb2e8f9f7	2337	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	2338
<>	144:ef7eb2e8f9f7	2339	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
<>	144:ef7eb2e8f9f7	2340
<>	144:ef7eb2e8f9f7	2341	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
<>	144:ef7eb2e8f9f7	2342
<>	144:ef7eb2e8f9f7	2343	#if defined(LCD)
<>	144:ef7eb2e8f9f7	2344	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
<>	144:ef7eb2e8f9f7	2345	#endif /* LCD */
<>	144:ef7eb2e8f9f7	2346
<>	144:ef7eb2e8f9f7	2347	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2348	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2349	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
<>	144:ef7eb2e8f9f7	2350
<>	144:ef7eb2e8f9f7	2351	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	2354	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
<>	144:ef7eb2e8f9f7	2355	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	2356
<>	144:ef7eb2e8f9f7	2357	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
<>	144:ef7eb2e8f9f7	2360
<>	144:ef7eb2e8f9f7	2361	#if defined(USART3)
<>	144:ef7eb2e8f9f7	2362	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
<>	144:ef7eb2e8f9f7	2363	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	2364
<>	144:ef7eb2e8f9f7	2365	#if defined(UART4)
<>	144:ef7eb2e8f9f7	2366	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
<>	144:ef7eb2e8f9f7	2367	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	2368
<>	144:ef7eb2e8f9f7	2369	#if defined(UART5)
<>	144:ef7eb2e8f9f7	2370	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
<>	144:ef7eb2e8f9f7	2371	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	2372
<>	144:ef7eb2e8f9f7	2373	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
<>	144:ef7eb2e8f9f7	2374
<>	144:ef7eb2e8f9f7	2375	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	2376	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
<>	144:ef7eb2e8f9f7	2377	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	2378
<>	144:ef7eb2e8f9f7	2379	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	#if defined(CRS)
<>	144:ef7eb2e8f9f7	2382	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
<>	144:ef7eb2e8f9f7	2383	#endif /* CRS */
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	#if defined(USB)
<>	144:ef7eb2e8f9f7	2388	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
<>	144:ef7eb2e8f9f7	2389	#endif /* USB */
<>	144:ef7eb2e8f9f7	2390
<>	144:ef7eb2e8f9f7	2391	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
<>	144:ef7eb2e8f9f7	2394
<>	144:ef7eb2e8f9f7	2395	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
<>	144:ef7eb2e8f9f7	2396
<>	144:ef7eb2e8f9f7	2397	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
<>	144:ef7eb2e8f9f7	2398
<>	144:ef7eb2e8f9f7	2399	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
<>	144:ef7eb2e8f9f7	2402
<>	144:ef7eb2e8f9f7	2403	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
<>	144:ef7eb2e8f9f7	2407
<>	144:ef7eb2e8f9f7	2408	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	2409	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
<>	144:ef7eb2e8f9f7	2410	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	2411
<>	144:ef7eb2e8f9f7	2412	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	2413	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
<>	144:ef7eb2e8f9f7	2414	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	2415
<>	144:ef7eb2e8f9f7	2416	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	2417	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
<>	144:ef7eb2e8f9f7	2418	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	2419
<>	144:ef7eb2e8f9f7	2420	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
<>	144:ef7eb2e8f9f7	2421
<>	144:ef7eb2e8f9f7	2422	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
<>	144:ef7eb2e8f9f7	2423
<>	144:ef7eb2e8f9f7	2424	#if defined(LCD)
<>	144:ef7eb2e8f9f7	2425	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
<>	144:ef7eb2e8f9f7	2426	#endif /* LCD */
<>	144:ef7eb2e8f9f7	2427
<>	144:ef7eb2e8f9f7	2428	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2429	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2430	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
<>	144:ef7eb2e8f9f7	2431
<>	144:ef7eb2e8f9f7	2432	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
<>	144:ef7eb2e8f9f7	2433
<>	144:ef7eb2e8f9f7	2434	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	2435	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
<>	144:ef7eb2e8f9f7	2436	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
<>	144:ef7eb2e8f9f7	2439
<>	144:ef7eb2e8f9f7	2440	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
<>	144:ef7eb2e8f9f7	2441
<>	144:ef7eb2e8f9f7	2442	#if defined(USART3)
<>	144:ef7eb2e8f9f7	2443	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
<>	144:ef7eb2e8f9f7	2444	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	2445
<>	144:ef7eb2e8f9f7	2446	#if defined(UART4)
<>	144:ef7eb2e8f9f7	2447	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
<>	144:ef7eb2e8f9f7	2448	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	2449
<>	144:ef7eb2e8f9f7	2450	#if defined(UART5)
<>	144:ef7eb2e8f9f7	2451	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
<>	144:ef7eb2e8f9f7	2452	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	2453
<>	144:ef7eb2e8f9f7	2454	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
<>	144:ef7eb2e8f9f7	2455
<>	144:ef7eb2e8f9f7	2456	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	2457	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
<>	144:ef7eb2e8f9f7	2458	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
<>	144:ef7eb2e8f9f7	2461
<>	144:ef7eb2e8f9f7	2462	#if defined(CRS)
<>	144:ef7eb2e8f9f7	2463	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
<>	144:ef7eb2e8f9f7	2464	#endif /* CRS */
<>	144:ef7eb2e8f9f7	2465
<>	144:ef7eb2e8f9f7	2466	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
<>	144:ef7eb2e8f9f7	2467
<>	144:ef7eb2e8f9f7	2468	#if defined(USB)
<>	144:ef7eb2e8f9f7	2469	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
<>	144:ef7eb2e8f9f7	2470	#endif /* USB */
<>	144:ef7eb2e8f9f7	2471
<>	144:ef7eb2e8f9f7	2472	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
<>	144:ef7eb2e8f9f7	2473
<>	144:ef7eb2e8f9f7	2474	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
<>	144:ef7eb2e8f9f7	2475
<>	144:ef7eb2e8f9f7	2476	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
<>	144:ef7eb2e8f9f7	2477
<>	144:ef7eb2e8f9f7	2478	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
<>	144:ef7eb2e8f9f7	2481
<>	144:ef7eb2e8f9f7	2482	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
<>	144:ef7eb2e8f9f7	2483
<>	144:ef7eb2e8f9f7	2484	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
<>	144:ef7eb2e8f9f7	2485
<>	144:ef7eb2e8f9f7	2486	/**
<>	144:ef7eb2e8f9f7	2487	* @}
<>	144:ef7eb2e8f9f7	2488	*/
<>	144:ef7eb2e8f9f7	2489
<>	144:ef7eb2e8f9f7	2490	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	2491	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2492	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2493	* power consumption.
<>	144:ef7eb2e8f9f7	2494	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2495	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2496	* @{
<>	144:ef7eb2e8f9f7	2497	*/
<>	144:ef7eb2e8f9f7	2498
<>	144:ef7eb2e8f9f7	2499	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
<>	144:ef7eb2e8f9f7	2500
<>	144:ef7eb2e8f9f7	2501	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2502	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2503	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
<>	144:ef7eb2e8f9f7	2504
<>	144:ef7eb2e8f9f7	2505	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
<>	144:ef7eb2e8f9f7	2506
<>	144:ef7eb2e8f9f7	2507	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
<>	144:ef7eb2e8f9f7	2508
<>	144:ef7eb2e8f9f7	2509	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2510	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
<>	144:ef7eb2e8f9f7	2511	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
<>	144:ef7eb2e8f9f7	2514
<>	144:ef7eb2e8f9f7	2515	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
<>	144:ef7eb2e8f9f7	2516
<>	144:ef7eb2e8f9f7	2517	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
<>	144:ef7eb2e8f9f7	2518
<>	144:ef7eb2e8f9f7	2519	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2520	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
<>	144:ef7eb2e8f9f7	2521	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2522
<>	144:ef7eb2e8f9f7	2523	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
<>	144:ef7eb2e8f9f7	2524
<>	144:ef7eb2e8f9f7	2525	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2526	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
<>	144:ef7eb2e8f9f7	2527	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2528
<>	144:ef7eb2e8f9f7	2529	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2530	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
<>	144:ef7eb2e8f9f7	2531	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2532
<>	144:ef7eb2e8f9f7	2533
<>	144:ef7eb2e8f9f7	2534	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
<>	144:ef7eb2e8f9f7	2535
<>	144:ef7eb2e8f9f7	2536	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2537	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2538	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
<>	144:ef7eb2e8f9f7	2541
<>	144:ef7eb2e8f9f7	2542	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
<>	144:ef7eb2e8f9f7	2543
<>	144:ef7eb2e8f9f7	2544	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2545	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
<>	144:ef7eb2e8f9f7	2546	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2547
<>	144:ef7eb2e8f9f7	2548	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
<>	144:ef7eb2e8f9f7	2549
<>	144:ef7eb2e8f9f7	2550	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
<>	144:ef7eb2e8f9f7	2551
<>	144:ef7eb2e8f9f7	2552	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
<>	144:ef7eb2e8f9f7	2553
<>	144:ef7eb2e8f9f7	2554	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2555	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
<>	144:ef7eb2e8f9f7	2556	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2557
<>	144:ef7eb2e8f9f7	2558	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
<>	144:ef7eb2e8f9f7	2559
<>	144:ef7eb2e8f9f7	2560	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2561	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
<>	144:ef7eb2e8f9f7	2562	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2563
<>	144:ef7eb2e8f9f7	2564	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2565	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
<>	144:ef7eb2e8f9f7	2566	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	/**
<>	144:ef7eb2e8f9f7	2569	* @}
<>	144:ef7eb2e8f9f7	2570	*/
<>	144:ef7eb2e8f9f7	2571
<>	144:ef7eb2e8f9f7	2572	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	2573	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	2574	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2575	* power consumption.
<>	144:ef7eb2e8f9f7	2576	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2577	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2578	* @{
<>	144:ef7eb2e8f9f7	2579	*/
<>	144:ef7eb2e8f9f7	2580
<>	144:ef7eb2e8f9f7	2581	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2582
<>	144:ef7eb2e8f9f7	2583	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2584
<>	144:ef7eb2e8f9f7	2585	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2586
<>	144:ef7eb2e8f9f7	2587	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2588
<>	144:ef7eb2e8f9f7	2589	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2590
<>	144:ef7eb2e8f9f7	2591	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2592
<>	144:ef7eb2e8f9f7	2593
<>	144:ef7eb2e8f9f7	2594	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2595
<>	144:ef7eb2e8f9f7	2596	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2597
<>	144:ef7eb2e8f9f7	2598	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2599
<>	144:ef7eb2e8f9f7	2600	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2601
<>	144:ef7eb2e8f9f7	2602	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2603
<>	144:ef7eb2e8f9f7	2604	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2605
<>	144:ef7eb2e8f9f7	2606	/**
<>	144:ef7eb2e8f9f7	2607	* @}
<>	144:ef7eb2e8f9f7	2608	*/
<>	144:ef7eb2e8f9f7	2609
<>	144:ef7eb2e8f9f7	2610	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	2611	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	2612	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2613	* power consumption.
<>	144:ef7eb2e8f9f7	2614	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2615	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2616	* @{
<>	144:ef7eb2e8f9f7	2617	*/
<>	144:ef7eb2e8f9f7	2618
<>	144:ef7eb2e8f9f7	2619	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
<>	144:ef7eb2e8f9f7	2620
<>	144:ef7eb2e8f9f7	2621	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2622
<>	144:ef7eb2e8f9f7	2623	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2624
<>	144:ef7eb2e8f9f7	2625	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	2626	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2627	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	2628
<>	144:ef7eb2e8f9f7	2629	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	2630	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
<>	144:ef7eb2e8f9f7	2631	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	2632
<>	144:ef7eb2e8f9f7	2633	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	2634	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2635	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	2636
<>	144:ef7eb2e8f9f7	2637	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	2638	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2639	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	2640
<>	144:ef7eb2e8f9f7	2641	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2642
<>	144:ef7eb2e8f9f7	2643	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2644
<>	144:ef7eb2e8f9f7	2645	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	2646	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2647	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	2648
<>	144:ef7eb2e8f9f7	2649	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	#if defined(AES)
<>	144:ef7eb2e8f9f7	2652	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2653	#endif /* AES */
<>	144:ef7eb2e8f9f7	2654
<>	144:ef7eb2e8f9f7	2655	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2656
<>	144:ef7eb2e8f9f7	2657
<>	144:ef7eb2e8f9f7	2658	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
<>	144:ef7eb2e8f9f7	2659
<>	144:ef7eb2e8f9f7	2660	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2661
<>	144:ef7eb2e8f9f7	2662	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	#if defined(GPIOD)
<>	144:ef7eb2e8f9f7	2665	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2666	#endif /* GPIOD */
<>	144:ef7eb2e8f9f7	2667
<>	144:ef7eb2e8f9f7	2668	#if defined(GPIOE)
<>	144:ef7eb2e8f9f7	2669	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
<>	144:ef7eb2e8f9f7	2670	#endif /* GPIOE */
<>	144:ef7eb2e8f9f7	2671
<>	144:ef7eb2e8f9f7	2672	#if defined(GPIOF)
<>	144:ef7eb2e8f9f7	2673	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2674	#endif /* GPIOF */
<>	144:ef7eb2e8f9f7	2675
<>	144:ef7eb2e8f9f7	2676	#if defined(GPIOG)
<>	144:ef7eb2e8f9f7	2677	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2678	#endif /* GPIOG */
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2681
<>	144:ef7eb2e8f9f7	2682	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2683
<>	144:ef7eb2e8f9f7	2684	#if defined(USB_OTG_FS)
<>	144:ef7eb2e8f9f7	2685	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2686	#endif /* USB_OTG_FS */
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2689
<>	144:ef7eb2e8f9f7	2690	#if defined(AES)
<>	144:ef7eb2e8f9f7	2691	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2692	#endif /* AES */
<>	144:ef7eb2e8f9f7	2693
<>	144:ef7eb2e8f9f7	2694	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2695
<>	144:ef7eb2e8f9f7	2696	/**
<>	144:ef7eb2e8f9f7	2697	* @}
<>	144:ef7eb2e8f9f7	2698	*/
<>	144:ef7eb2e8f9f7	2699
<>	144:ef7eb2e8f9f7	2700	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	2701	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	2702	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2703	* power consumption.
<>	144:ef7eb2e8f9f7	2704	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2705	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2706	* @{
<>	144:ef7eb2e8f9f7	2707	*/
<>	144:ef7eb2e8f9f7	2708
<>	144:ef7eb2e8f9f7	2709	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	2710	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
<>	144:ef7eb2e8f9f7	2711	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	2712
<>	144:ef7eb2e8f9f7	2713	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	2714	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2715	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	2716
<>	144:ef7eb2e8f9f7	2717	#if defined(QUADSPI)
<>	144:ef7eb2e8f9f7	2718	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
<>	144:ef7eb2e8f9f7	2719	#endif /* QUADSPI */
<>	144:ef7eb2e8f9f7	2720
<>	144:ef7eb2e8f9f7	2721	#if defined(FMC_BANK1)
<>	144:ef7eb2e8f9f7	2722	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2723	#endif /* FMC_BANK1 */
<>	144:ef7eb2e8f9f7	2724
<>	144:ef7eb2e8f9f7	2725	/**
<>	144:ef7eb2e8f9f7	2726	* @}
<>	144:ef7eb2e8f9f7	2727	*/
<>	144:ef7eb2e8f9f7	2728
<>	144:ef7eb2e8f9f7	2729	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	2730	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	2731	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2732	* power consumption.
<>	144:ef7eb2e8f9f7	2733	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2734	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2735	* @{
<>	144:ef7eb2e8f9f7	2736	*/
<>	144:ef7eb2e8f9f7	2737
<>	144:ef7eb2e8f9f7	2738	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2739
<>	144:ef7eb2e8f9f7	2740	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	2741	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2742	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	2743
<>	144:ef7eb2e8f9f7	2744	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	2745	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2746	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	2747
<>	144:ef7eb2e8f9f7	2748	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	2749	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2750	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	2751
<>	144:ef7eb2e8f9f7	2752	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2753
<>	144:ef7eb2e8f9f7	2754	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2755
<>	144:ef7eb2e8f9f7	2756	#if defined(LCD)
<>	144:ef7eb2e8f9f7	2757	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2758	#endif /* LCD */
<>	144:ef7eb2e8f9f7	2759
<>	144:ef7eb2e8f9f7	2760	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2761	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2762	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
<>	144:ef7eb2e8f9f7	2763
<>	144:ef7eb2e8f9f7	2764	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2765
<>	144:ef7eb2e8f9f7	2766	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	2767	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2768	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	2769
<>	144:ef7eb2e8f9f7	2770	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2771
<>	144:ef7eb2e8f9f7	2772	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2773
<>	144:ef7eb2e8f9f7	2774	#if defined(USART3)
<>	144:ef7eb2e8f9f7	2775	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2776	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	2777
<>	144:ef7eb2e8f9f7	2778	#if defined(UART4)
<>	144:ef7eb2e8f9f7	2779	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2780	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	2781
<>	144:ef7eb2e8f9f7	2782	#if defined(UART5)
<>	144:ef7eb2e8f9f7	2783	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2784	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	2785
<>	144:ef7eb2e8f9f7	2786	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2787
<>	144:ef7eb2e8f9f7	2788	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	2789	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2790	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	2791
<>	144:ef7eb2e8f9f7	2792	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2793
<>	144:ef7eb2e8f9f7	2794	#if defined(CRS)
<>	144:ef7eb2e8f9f7	2795	#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2796	#endif /* CRS */
<>	144:ef7eb2e8f9f7	2797
<>	144:ef7eb2e8f9f7	2798	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2799
<>	144:ef7eb2e8f9f7	2800	#if defined(USB)
<>	144:ef7eb2e8f9f7	2801	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2802	#endif /* USB */
<>	144:ef7eb2e8f9f7	2803
<>	144:ef7eb2e8f9f7	2804	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2807
<>	144:ef7eb2e8f9f7	2808	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2809
<>	144:ef7eb2e8f9f7	2810	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2811
<>	144:ef7eb2e8f9f7	2812	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2813
<>	144:ef7eb2e8f9f7	2814	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2815
<>	144:ef7eb2e8f9f7	2816	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2817
<>	144:ef7eb2e8f9f7	2818
<>	144:ef7eb2e8f9f7	2819	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2820
<>	144:ef7eb2e8f9f7	2821	#if defined(TIM3)
<>	144:ef7eb2e8f9f7	2822	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2823	#endif /* TIM3 */
<>	144:ef7eb2e8f9f7	2824
<>	144:ef7eb2e8f9f7	2825	#if defined(TIM4)
<>	144:ef7eb2e8f9f7	2826	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2827	#endif /* TIM4 */
<>	144:ef7eb2e8f9f7	2828
<>	144:ef7eb2e8f9f7	2829	#if defined(TIM5)
<>	144:ef7eb2e8f9f7	2830	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2831	#endif /* TIM5 */
<>	144:ef7eb2e8f9f7	2832
<>	144:ef7eb2e8f9f7	2833	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2834
<>	144:ef7eb2e8f9f7	2835	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2836
<>	144:ef7eb2e8f9f7	2837	#if defined(LCD)
<>	144:ef7eb2e8f9f7	2838	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2839	#endif /* LCD */
<>	144:ef7eb2e8f9f7	2840
<>	144:ef7eb2e8f9f7	2841	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
<>	144:ef7eb2e8f9f7	2842	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2843	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
<>	144:ef7eb2e8f9f7	2844
<>	144:ef7eb2e8f9f7	2845	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2846
<>	144:ef7eb2e8f9f7	2847	#if defined(SPI2)
<>	144:ef7eb2e8f9f7	2848	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2849	#endif /* SPI2 */
<>	144:ef7eb2e8f9f7	2850
<>	144:ef7eb2e8f9f7	2851	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2852
<>	144:ef7eb2e8f9f7	2853	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2854
<>	144:ef7eb2e8f9f7	2855	#if defined(USART3)
<>	144:ef7eb2e8f9f7	2856	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2857	#endif /* USART3 */
<>	144:ef7eb2e8f9f7	2858
<>	144:ef7eb2e8f9f7	2859	#if defined(UART4)
<>	144:ef7eb2e8f9f7	2860	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2861	#endif /* UART4 */
<>	144:ef7eb2e8f9f7	2862
<>	144:ef7eb2e8f9f7	2863	#if defined(UART5)
<>	144:ef7eb2e8f9f7	2864	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2865	#endif /* UART5 */
<>	144:ef7eb2e8f9f7	2866
<>	144:ef7eb2e8f9f7	2867	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2868
<>	144:ef7eb2e8f9f7	2869	#if defined(I2C2)
<>	144:ef7eb2e8f9f7	2870	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2871	#endif /* I2C2 */
<>	144:ef7eb2e8f9f7	2872
<>	144:ef7eb2e8f9f7	2873	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2874
<>	144:ef7eb2e8f9f7	2875	#if defined(CRS)
<>	144:ef7eb2e8f9f7	2876	#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2877	#endif /* CRS */
<>	144:ef7eb2e8f9f7	2878
<>	144:ef7eb2e8f9f7	2879	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2880
<>	144:ef7eb2e8f9f7	2881	#if defined(USB)
<>	144:ef7eb2e8f9f7	2882	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2883	#endif /* USB */
<>	144:ef7eb2e8f9f7	2884
<>	144:ef7eb2e8f9f7	2885	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2886
<>	144:ef7eb2e8f9f7	2887	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2888
<>	144:ef7eb2e8f9f7	2889	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2890
<>	144:ef7eb2e8f9f7	2891	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2892
<>	144:ef7eb2e8f9f7	2893	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2894
<>	144:ef7eb2e8f9f7	2895	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2896
<>	144:ef7eb2e8f9f7	2897	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2898
<>	144:ef7eb2e8f9f7	2899	/**
<>	144:ef7eb2e8f9f7	2900	* @}
<>	144:ef7eb2e8f9f7	2901	*/
<>	144:ef7eb2e8f9f7	2902
<>	144:ef7eb2e8f9f7	2903	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	2904	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	2905	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2906	* power consumption.
<>	144:ef7eb2e8f9f7	2907	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2908	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2909	* @{
<>	144:ef7eb2e8f9f7	2910	*/
<>	144:ef7eb2e8f9f7	2911
<>	144:ef7eb2e8f9f7	2912	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	2913
<>	144:ef7eb2e8f9f7	2914	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2915	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2916	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
<>	144:ef7eb2e8f9f7	2917
<>	144:ef7eb2e8f9f7	2918	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2921
<>	144:ef7eb2e8f9f7	2922	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2923	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2924	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2925
<>	144:ef7eb2e8f9f7	2926	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2927
<>	144:ef7eb2e8f9f7	2928	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2929
<>	144:ef7eb2e8f9f7	2930	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2933	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2934	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2935
<>	144:ef7eb2e8f9f7	2936	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2937
<>	144:ef7eb2e8f9f7	2938	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2939	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2940	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2941
<>	144:ef7eb2e8f9f7	2942	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2943	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	2944	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2945
<>	144:ef7eb2e8f9f7	2946
<>	144:ef7eb2e8f9f7	2947	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
<>	144:ef7eb2e8f9f7	2948
<>	144:ef7eb2e8f9f7	2949	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
<>	144:ef7eb2e8f9f7	2950	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2951	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
<>	144:ef7eb2e8f9f7	2952
<>	144:ef7eb2e8f9f7	2953	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2954
<>	144:ef7eb2e8f9f7	2955	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2956
<>	144:ef7eb2e8f9f7	2957	#if defined(TIM8)
<>	144:ef7eb2e8f9f7	2958	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2959	#endif /* TIM8 */
<>	144:ef7eb2e8f9f7	2960
<>	144:ef7eb2e8f9f7	2961	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2962
<>	144:ef7eb2e8f9f7	2963	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2966
<>	144:ef7eb2e8f9f7	2967	#if defined(TIM17)
<>	144:ef7eb2e8f9f7	2968	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2969	#endif /* TIM17 */
<>	144:ef7eb2e8f9f7	2970
<>	144:ef7eb2e8f9f7	2971	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2972
<>	144:ef7eb2e8f9f7	2973	#if defined(SAI2)
<>	144:ef7eb2e8f9f7	2974	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2975	#endif /* SAI2 */
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977	#if defined(DFSDM1_Filter0)
<>	144:ef7eb2e8f9f7	2978	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	2979	#endif /* DFSDM1_Filter0 */
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	/**
<>	144:ef7eb2e8f9f7	2982	* @}
<>	144:ef7eb2e8f9f7	2983	*/
<>	144:ef7eb2e8f9f7	2984
<>	144:ef7eb2e8f9f7	2985	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
<>	144:ef7eb2e8f9f7	2986	* @{
<>	144:ef7eb2e8f9f7	2987	*/
<>	144:ef7eb2e8f9f7	2988
<>	144:ef7eb2e8f9f7	2989	/** @brief Macros to force or release the Backup domain reset.
<>	144:ef7eb2e8f9f7	2990	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	2991	* and the RTC clock source selection in RCC_CSR register.
<>	144:ef7eb2e8f9f7	2992	* @note The BKPSRAM is not affected by this reset.
<>	144:ef7eb2e8f9f7	2993	* @retval None
<>	144:ef7eb2e8f9f7	2994	*/
<>	144:ef7eb2e8f9f7	2995	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
<>	144:ef7eb2e8f9f7	2996
<>	144:ef7eb2e8f9f7	2997	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
<>	144:ef7eb2e8f9f7	2998
<>	144:ef7eb2e8f9f7	2999	/**
<>	144:ef7eb2e8f9f7	3000	* @}
<>	144:ef7eb2e8f9f7	3001	*/
<>	144:ef7eb2e8f9f7	3002
<>	144:ef7eb2e8f9f7	3003	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
<>	144:ef7eb2e8f9f7	3004	* @{
<>	144:ef7eb2e8f9f7	3005	*/
<>	144:ef7eb2e8f9f7	3006
<>	144:ef7eb2e8f9f7	3007	/** @brief Macros to enable or disable the RTC clock.
<>	144:ef7eb2e8f9f7	3008	* @note As the RTC is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	3009	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	3010	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
<>	144:ef7eb2e8f9f7	3011	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	3012	* @note These macros must be used after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	3013	* @retval None
<>	144:ef7eb2e8f9f7	3014	*/
<>	144:ef7eb2e8f9f7	3015	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
<>	144:ef7eb2e8f9f7	3016
<>	144:ef7eb2e8f9f7	3017	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
<>	144:ef7eb2e8f9f7	3018
<>	144:ef7eb2e8f9f7	3019	/**
<>	144:ef7eb2e8f9f7	3020	* @}
<>	144:ef7eb2e8f9f7	3021	*/
<>	144:ef7eb2e8f9f7	3022
<>	144:ef7eb2e8f9f7	3023	/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
<>	144:ef7eb2e8f9f7	3024	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3025	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	3026	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	3027	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	3028	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	3029	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	3030	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	3031	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	3032	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	3033	* system clock source.
<>	144:ef7eb2e8f9f7	3034	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	3035	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	3036	* clock cycles.
<>	144:ef7eb2e8f9f7	3037	* @retval None
<>	144:ef7eb2e8f9f7	3038	*/
<>	144:ef7eb2e8f9f7	3039	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	3040
<>	144:ef7eb2e8f9f7	3041	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	3042
<>	144:ef7eb2e8f9f7	3043	/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	3044	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	3045	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	3046	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
<>	144:ef7eb2e8f9f7	3047	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	3048	* This parameter must be a number between 0 and 31.
<>	144:ef7eb2e8f9f7	3049	* @retval None
<>	144:ef7eb2e8f9f7	3050	*/
<>	144:ef7eb2e8f9f7	3051	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
<>	144:ef7eb2e8f9f7	3052	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
<>	144:ef7eb2e8f9f7	3053
<>	144:ef7eb2e8f9f7	3054	/**
<>	144:ef7eb2e8f9f7	3055	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
<>	144:ef7eb2e8f9f7	3056	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
<>	144:ef7eb2e8f9f7	3057	* @note The enable of this function has not effect on the HSION bit.
<>	144:ef7eb2e8f9f7	3058	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	3059	* @retval None
<>	144:ef7eb2e8f9f7	3060	*/
<>	144:ef7eb2e8f9f7	3061	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
<>	144:ef7eb2e8f9f7	3062
<>	144:ef7eb2e8f9f7	3063	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
<>	144:ef7eb2e8f9f7	3064
<>	144:ef7eb2e8f9f7	3065	/**
<>	144:ef7eb2e8f9f7	3066	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
<>	144:ef7eb2e8f9f7	3067	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
<>	144:ef7eb2e8f9f7	3068	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
<>	144:ef7eb2e8f9f7	3069	* speed because of the HSI startup time.
<>	144:ef7eb2e8f9f7	3070	* @note The enable of this function has not effect on the HSION bit.
<>	144:ef7eb2e8f9f7	3071	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	3072	* @retval None
<>	144:ef7eb2e8f9f7	3073	*/
<>	144:ef7eb2e8f9f7	3074	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
<>	144:ef7eb2e8f9f7	3075
<>	144:ef7eb2e8f9f7	3076	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
<>	144:ef7eb2e8f9f7	3077
<>	144:ef7eb2e8f9f7	3078	/**
<>	144:ef7eb2e8f9f7	3079	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
<>	144:ef7eb2e8f9f7	3080	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3081	* It is used (enabled by hardware) as system clock source after
<>	144:ef7eb2e8f9f7	3082	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
<>	144:ef7eb2e8f9f7	3083	* of failure of the HSE used directly or indirectly as system clock
<>	144:ef7eb2e8f9f7	3084	* (if the Clock Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	3085	* @note MSI can not be stopped if it is used as system clock source.
<>	144:ef7eb2e8f9f7	3086	* In this case, you have to select another source of the system
<>	144:ef7eb2e8f9f7	3087	* clock then stop the MSI.
<>	144:ef7eb2e8f9f7	3088	* @note After enabling the MSI, the application software should wait on
<>	144:ef7eb2e8f9f7	3089	* MSIRDY flag to be set indicating that MSI clock is stable and can
<>	144:ef7eb2e8f9f7	3090	* be used as system clock source.
<>	144:ef7eb2e8f9f7	3091	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
<>	144:ef7eb2e8f9f7	3092	* clock cycles.
<>	144:ef7eb2e8f9f7	3093	* @retval None
<>	144:ef7eb2e8f9f7	3094	*/
<>	144:ef7eb2e8f9f7	3095	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
<>	144:ef7eb2e8f9f7	3096
<>	144:ef7eb2e8f9f7	3097	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
<>	144:ef7eb2e8f9f7	3098
<>	144:ef7eb2e8f9f7	3099	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
<>	144:ef7eb2e8f9f7	3100	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	3101	* and temperature that influence the frequency of the internal MSI RC.
<>	144:ef7eb2e8f9f7	3102	* Refer to the Application Note AN3300 for more details on how to
<>	144:ef7eb2e8f9f7	3103	* calibrate the MSI.
<>	144:ef7eb2e8f9f7	3104	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
<>	144:ef7eb2e8f9f7	3105	* (default is RCC_MSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	3106	* This parameter must be a number between 0 and 255.
<>	144:ef7eb2e8f9f7	3107	* @retval None
<>	144:ef7eb2e8f9f7	3108	*/
<>	144:ef7eb2e8f9f7	3109	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
<>	144:ef7eb2e8f9f7	3110	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
<>	144:ef7eb2e8f9f7	3111
<>	144:ef7eb2e8f9f7	3112	/**
<>	144:ef7eb2e8f9f7	3113	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
<>	144:ef7eb2e8f9f7	3114	* @note After restart from Reset , the MSI clock is around 4 MHz.
<>	144:ef7eb2e8f9f7	3115	* After stop the startup clock can be MSI (at any of its possible
<>	144:ef7eb2e8f9f7	3116	* frequencies, the one that was used before entering stop mode) or HSI.
<>	144:ef7eb2e8f9f7	3117	* After Standby its frequency can be selected between 4 possible values
<>	144:ef7eb2e8f9f7	3118	* (1, 2, 4 or 8 MHz).
<>	144:ef7eb2e8f9f7	3119	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
<>	144:ef7eb2e8f9f7	3120	* (MSIRDY=1).
<>	144:ef7eb2e8f9f7	3121	* @note The MSI clock range after reset can be modified on the fly.
<>	144:ef7eb2e8f9f7	3122	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
<>	144:ef7eb2e8f9f7	3123	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	3124	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
<>	144:ef7eb2e8f9f7	3125	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
<>	144:ef7eb2e8f9f7	3126	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
<>	144:ef7eb2e8f9f7	3127	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
<>	144:ef7eb2e8f9f7	3128	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
<>	144:ef7eb2e8f9f7	3129	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
<>	144:ef7eb2e8f9f7	3130	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
<>	144:ef7eb2e8f9f7	3131	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
<>	144:ef7eb2e8f9f7	3132	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
<>	144:ef7eb2e8f9f7	3133	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
<>	144:ef7eb2e8f9f7	3134	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
<>	144:ef7eb2e8f9f7	3135	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
<>	144:ef7eb2e8f9f7	3136	* @retval None
<>	144:ef7eb2e8f9f7	3137	*/
<>	144:ef7eb2e8f9f7	3138	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
<>	144:ef7eb2e8f9f7	3139	do { \
<>	144:ef7eb2e8f9f7	3140	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
<>	144:ef7eb2e8f9f7	3141	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
<>	144:ef7eb2e8f9f7	3142	} while(0)
<>	144:ef7eb2e8f9f7	3143
<>	144:ef7eb2e8f9f7	3144	/**
<>	144:ef7eb2e8f9f7	3145	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
<>	144:ef7eb2e8f9f7	3146	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
<>	144:ef7eb2e8f9f7	3147	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
<>	144:ef7eb2e8f9f7	3148	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	3149	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
<>	144:ef7eb2e8f9f7	3150	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
<>	144:ef7eb2e8f9f7	3151	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
<>	144:ef7eb2e8f9f7	3152	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
<>	144:ef7eb2e8f9f7	3153	* @retval None
<>	144:ef7eb2e8f9f7	3154	*/
<>	144:ef7eb2e8f9f7	3155	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
<>	144:ef7eb2e8f9f7	3156	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
<>	144:ef7eb2e8f9f7	3157
<>	144:ef7eb2e8f9f7	3158	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
<>	144:ef7eb2e8f9f7	3159	* @retval MSI clock range.
<>	144:ef7eb2e8f9f7	3160	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	3161	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
<>	144:ef7eb2e8f9f7	3162	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
<>	144:ef7eb2e8f9f7	3163	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
<>	144:ef7eb2e8f9f7	3164	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
<>	144:ef7eb2e8f9f7	3165	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
<>	144:ef7eb2e8f9f7	3166	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
<>	144:ef7eb2e8f9f7	3167	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
<>	144:ef7eb2e8f9f7	3168	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
<>	144:ef7eb2e8f9f7	3169	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
<>	144:ef7eb2e8f9f7	3170	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
<>	144:ef7eb2e8f9f7	3171	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
<>	144:ef7eb2e8f9f7	3172	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
<>	144:ef7eb2e8f9f7	3173	*/
<>	144:ef7eb2e8f9f7	3174	#define __HAL_RCC_GET_MSI_RANGE() \
<>	144:ef7eb2e8f9f7	3175	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
<>	144:ef7eb2e8f9f7	3176	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
<>	144:ef7eb2e8f9f7	3177	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
<>	144:ef7eb2e8f9f7	3178
<>	144:ef7eb2e8f9f7	3179	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	3180	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	3181	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	3182	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	3183	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	3184	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	3185	* clock cycles.
<>	144:ef7eb2e8f9f7	3186	* @retval None
<>	144:ef7eb2e8f9f7	3187	*/
<>	144:ef7eb2e8f9f7	3188	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	3189
<>	144:ef7eb2e8f9f7	3190	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	3191
<>	144:ef7eb2e8f9f7	3192	/**
<>	144:ef7eb2e8f9f7	3193	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	3194	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	3195	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	3196	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	3197	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	3198	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	3199	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	3200	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	3201	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	3202	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	3203	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3204	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	3205	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	3206	* function.
<>	144:ef7eb2e8f9f7	3207	* @param __STATE__: specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	3208	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3209	* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	3210	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	3211	* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
<>	144:ef7eb2e8f9f7	3212	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	3213	* @retval None
<>	144:ef7eb2e8f9f7	3214	*/
<>	144:ef7eb2e8f9f7	3215	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	3216	do { \
<>	144:ef7eb2e8f9f7	3217	if((__STATE__) == RCC_HSE_ON) \
<>	144:ef7eb2e8f9f7	3218	{ \
<>	144:ef7eb2e8f9f7	3219	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	3220	} \
<>	144:ef7eb2e8f9f7	3221	else if((__STATE__) == RCC_HSE_BYPASS) \
<>	144:ef7eb2e8f9f7	3222	{ \
<>	144:ef7eb2e8f9f7	3223	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	3224	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	3225	} \
<>	144:ef7eb2e8f9f7	3226	else \
<>	144:ef7eb2e8f9f7	3227	{ \
<>	144:ef7eb2e8f9f7	3228	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	3229	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	3230	} \
<>	144:ef7eb2e8f9f7	3231	} while(0)
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	/**
<>	144:ef7eb2e8f9f7	3234	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	3235	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<>	144:ef7eb2e8f9f7	3236	* supported by this macro. User should request a transition to LSE Off
<>	144:ef7eb2e8f9f7	3237	* first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	3238	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	3239	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	3240	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	3241	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	3242	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	3243	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	3244	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	3245	* @param __STATE__: specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	3246	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3247	* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	3248	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	3249	* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	3250	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	3251	* @retval None
<>	144:ef7eb2e8f9f7	3252	*/
<>	144:ef7eb2e8f9f7	3253	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	3254	do { \
<>	144:ef7eb2e8f9f7	3255	if((__STATE__) == RCC_LSE_ON) \
<>	144:ef7eb2e8f9f7	3256	{ \
<>	144:ef7eb2e8f9f7	3257	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	3258	} \
<>	144:ef7eb2e8f9f7	3259	else if((__STATE__) == RCC_LSE_BYPASS) \
<>	144:ef7eb2e8f9f7	3260	{ \
<>	144:ef7eb2e8f9f7	3261	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	3262	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	3263	} \
<>	144:ef7eb2e8f9f7	3264	else \
<>	144:ef7eb2e8f9f7	3265	{ \
<>	144:ef7eb2e8f9f7	3266	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	3267	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	3268	} \
<>	144:ef7eb2e8f9f7	3269	} while(0)
<>	144:ef7eb2e8f9f7	3270
<>	144:ef7eb2e8f9f7	3271	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3272
<>	144:ef7eb2e8f9f7	3273	/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
<>	144:ef7eb2e8f9f7	3274	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3275	* @note After enabling the HSI48, the application software should wait on HSI48RDY
<>	144:ef7eb2e8f9f7	3276	* flag to be set indicating that HSI48 clock is stable.
<>	144:ef7eb2e8f9f7	3277	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	3278	* @retval None
<>	144:ef7eb2e8f9f7	3279	*/
<>	144:ef7eb2e8f9f7	3280	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
<>	144:ef7eb2e8f9f7	3281
<>	144:ef7eb2e8f9f7	3282	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
<>	144:ef7eb2e8f9f7	3283
<>	144:ef7eb2e8f9f7	3284	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3285
<>	144:ef7eb2e8f9f7	3286	/** @brief Macros to configure the RTC clock (RTCCLK).
<>	144:ef7eb2e8f9f7	3287	* @note As the RTC clock configuration bits are in the Backup domain and write
<>	144:ef7eb2e8f9f7	3288	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	3289	* access using the Power Backup Access macro before to configure
<>	144:ef7eb2e8f9f7	3290	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	3291	* @note Once the RTC clock is configured it cannot be changed unless the
<>	144:ef7eb2e8f9f7	3292	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
<>	144:ef7eb2e8f9f7	3293	* a Power On Reset (POR).
<>	144:ef7eb2e8f9f7	3294	*
<>	144:ef7eb2e8f9f7	3295	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	3296	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3297	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
<>	144:ef7eb2e8f9f7	3298	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
<>	144:ef7eb2e8f9f7	3299	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
<>	144:ef7eb2e8f9f7	3300	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
<>	144:ef7eb2e8f9f7	3301	*
<>	144:ef7eb2e8f9f7	3302	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	3303	* work in STOP and STANDBY modes, and can be used as wakeup source.
<>	144:ef7eb2e8f9f7	3304	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	3305	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3306	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	3307	* RTC clock source).
<>	144:ef7eb2e8f9f7	3308	* @retval None
<>	144:ef7eb2e8f9f7	3309	*/
<>	144:ef7eb2e8f9f7	3310	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	3311	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	3312
<>	144:ef7eb2e8f9f7	3313
<>	144:ef7eb2e8f9f7	3314	/** @brief Macro to get the RTC clock source.
<>	144:ef7eb2e8f9f7	3315	* @retval The returned value can be one of the following:
<>	144:ef7eb2e8f9f7	3316	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
<>	144:ef7eb2e8f9f7	3317	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
<>	144:ef7eb2e8f9f7	3318	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
<>	144:ef7eb2e8f9f7	3319	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
<>	144:ef7eb2e8f9f7	3320	*/
<>	144:ef7eb2e8f9f7	3321	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
<>	144:ef7eb2e8f9f7	3322
<>	144:ef7eb2e8f9f7	3323	/** @brief Macros to enable or disable the main PLL.
<>	144:ef7eb2e8f9f7	3324	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	3325	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	3326	* be used as system clock source.
<>	144:ef7eb2e8f9f7	3327	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	3328	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	3329	* @retval None
<>	144:ef7eb2e8f9f7	3330	*/
<>	144:ef7eb2e8f9f7	3331	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	3332
<>	144:ef7eb2e8f9f7	3333	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	3334
<>	144:ef7eb2e8f9f7	3335	/** @brief Macro to configure the PLL clock source.
<>	144:ef7eb2e8f9f7	3336	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	3337	* @param __PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	3338	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3339	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3340	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3341	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3342	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3343	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
<>	144:ef7eb2e8f9f7	3344	* @retval None
<>	144:ef7eb2e8f9f7	3345	*
<>	144:ef7eb2e8f9f7	3346	*/
<>	144:ef7eb2e8f9f7	3347	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
<>	144:ef7eb2e8f9f7	3348	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
<>	144:ef7eb2e8f9f7	3349
<>	144:ef7eb2e8f9f7	3350	/** @brief Macro to configure the PLL source division factor M.
<>	144:ef7eb2e8f9f7	3351	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	3352	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	3353	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
<>	144:ef7eb2e8f9f7	3354	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	3355	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	3356	* of 16 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	3357	* @retval None
<>	144:ef7eb2e8f9f7	3358	*
<>	144:ef7eb2e8f9f7	3359	*/
<>	144:ef7eb2e8f9f7	3360	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
<>	144:ef7eb2e8f9f7	3361	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
<>	144:ef7eb2e8f9f7	3362
<>	144:ef7eb2e8f9f7	3363	/**
<>	144:ef7eb2e8f9f7	3364	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	3365	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	3366	*
<>	144:ef7eb2e8f9f7	3367	* @param __PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	3368	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3369	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3370	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3371	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3372	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	3373	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
<>	144:ef7eb2e8f9f7	3374	*
<>	144:ef7eb2e8f9f7	3375	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
<>	144:ef7eb2e8f9f7	3376	* This parameter must be a number between 1 and 8.
<>	144:ef7eb2e8f9f7	3377	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	3378	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	3379	* of 16 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	3380	*
<>	144:ef7eb2e8f9f7	3381	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
<>	144:ef7eb2e8f9f7	3382	* This parameter must be a number between 8 and 86.
<>	144:ef7eb2e8f9f7	3383	* @note You have to set the PLLN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	3384	* output frequency is between 64 and 344 MHz.
<>	144:ef7eb2e8f9f7	3385	*
<>	144:ef7eb2e8f9f7	3386	* @param __PLLP__: specifies the division factor for SAI clock.
<>	144:ef7eb2e8f9f7	3387	* This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
<>	144:ef7eb2e8f9f7	3388	* else (2 to 31).
<>	144:ef7eb2e8f9f7	3389	*
<>	144:ef7eb2e8f9f7	3390	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
<>	144:ef7eb2e8f9f7	3391	* This parameter must be in the range (2, 4, 6 or 8).
<>	144:ef7eb2e8f9f7	3392	* @note If the USB OTG FS is used in your application, you have to set the
<>	144:ef7eb2e8f9f7	3393	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<>	144:ef7eb2e8f9f7	3394	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
<>	144:ef7eb2e8f9f7	3395	* correctly.
<>	144:ef7eb2e8f9f7	3396	* @param __PLLR__: specifies the division factor for the main system clock.
<>	144:ef7eb2e8f9f7	3397	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
<>	144:ef7eb2e8f9f7	3398	* This parameter must be in the range (2, 4, 6 or 8).
<>	144:ef7eb2e8f9f7	3399	* @retval None
<>	144:ef7eb2e8f9f7	3400	*/
<>	144:ef7eb2e8f9f7	3401	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	3402
<>	144:ef7eb2e8f9f7	3403	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
<>	144:ef7eb2e8f9f7	3404	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| \
<>	144:ef7eb2e8f9f7	3405	(uint32_t)(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) \| \
<>	144:ef7eb2e8f9f7	3406	(uint32_t)((__PLLP__) << 27U))
<>	144:ef7eb2e8f9f7	3407
<>	144:ef7eb2e8f9f7	3408	#else
<>	144:ef7eb2e8f9f7	3409
<>	144:ef7eb2e8f9f7	3410	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
<>	144:ef7eb2e8f9f7	3411	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| (uint32_t)(((__PLLP__) >> 4U ) << 17U) \| \
<>	144:ef7eb2e8f9f7	3412	(uint32_t)(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
<>	144:ef7eb2e8f9f7	3413
<>	144:ef7eb2e8f9f7	3414	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	3415
<>	144:ef7eb2e8f9f7	3416	/** @brief Macro to get the oscillator used as PLL clock source.
<>	144:ef7eb2e8f9f7	3417	* @retval The oscillator used as PLL clock source. The returned value can be one
<>	144:ef7eb2e8f9f7	3418	* of the following:
<>	144:ef7eb2e8f9f7	3419	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	3420	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	3421	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	3422	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	3423	*/
<>	144:ef7eb2e8f9f7	3424	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	3425
<>	144:ef7eb2e8f9f7	3426	/**
<>	144:ef7eb2e8f9f7	3427	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
<>	144:ef7eb2e8f9f7	3428	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
<>	144:ef7eb2e8f9f7	3429	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
<>	144:ef7eb2e8f9f7	3430	* be stopped if used as System Clock.
<>	144:ef7eb2e8f9f7	3431	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
<>	144:ef7eb2e8f9f7	3432	* This parameter can be one or a combination of the following values:
<>	144:ef7eb2e8f9f7	3433	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
<>	144:ef7eb2e8f9f7	3434	* high-quality audio performance on SAI interface in case.
<>	144:ef7eb2e8f9f7	3435	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
<>	144:ef7eb2e8f9f7	3436	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
<>	144:ef7eb2e8f9f7	3437	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
<>	144:ef7eb2e8f9f7	3438	* @retval None
<>	144:ef7eb2e8f9f7	3439	*/
<>	144:ef7eb2e8f9f7	3440	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
<>	144:ef7eb2e8f9f7	3441
<>	144:ef7eb2e8f9f7	3442	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
<>	144:ef7eb2e8f9f7	3443
<>	144:ef7eb2e8f9f7	3444	/**
<>	144:ef7eb2e8f9f7	3445	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
<>	144:ef7eb2e8f9f7	3446	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
<>	144:ef7eb2e8f9f7	3447	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3448	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
<>	144:ef7eb2e8f9f7	3449	* high-quality audio performance on SAI interface in case.
<>	144:ef7eb2e8f9f7	3450	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
<>	144:ef7eb2e8f9f7	3451	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
<>	144:ef7eb2e8f9f7	3452	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
<>	144:ef7eb2e8f9f7	3453	* @retval SET / RESET
<>	144:ef7eb2e8f9f7	3454	*/
<>	144:ef7eb2e8f9f7	3455	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
<>	144:ef7eb2e8f9f7	3456
<>	144:ef7eb2e8f9f7	3457	/**
<>	144:ef7eb2e8f9f7	3458	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	3459	* @param __SYSCLKSOURCE__: specifies the system clock source.
<>	144:ef7eb2e8f9f7	3460	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3461	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	3462	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	3463	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	3464	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	3465	* @retval None
<>	144:ef7eb2e8f9f7	3466	*/
<>	144:ef7eb2e8f9f7	3467	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<>	144:ef7eb2e8f9f7	3468	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	3469
<>	144:ef7eb2e8f9f7	3470	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	3471	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	3472	* of the following:
<>	144:ef7eb2e8f9f7	3473	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
<>	144:ef7eb2e8f9f7	3474	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
<>	144:ef7eb2e8f9f7	3475	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
<>	144:ef7eb2e8f9f7	3476	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
<>	144:ef7eb2e8f9f7	3477	*/
<>	144:ef7eb2e8f9f7	3478	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
<>	144:ef7eb2e8f9f7	3479
<>	144:ef7eb2e8f9f7	3480	/**
<>	144:ef7eb2e8f9f7	3481	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
<>	144:ef7eb2e8f9f7	3482	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	3483	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	3484	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	3485	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	3486	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
<>	144:ef7eb2e8f9f7	3487	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3488	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
<>	144:ef7eb2e8f9f7	3489	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
<>	144:ef7eb2e8f9f7	3490	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
<>	144:ef7eb2e8f9f7	3491	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
<>	144:ef7eb2e8f9f7	3492	* @retval None
<>	144:ef7eb2e8f9f7	3493	*/
<>	144:ef7eb2e8f9f7	3494	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
<>	144:ef7eb2e8f9f7	3495	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
<>	144:ef7eb2e8f9f7	3496
<>	144:ef7eb2e8f9f7	3497	/**
<>	144:ef7eb2e8f9f7	3498	* @brief Macro to configure the wake up from stop clock.
<>	144:ef7eb2e8f9f7	3499	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
<>	144:ef7eb2e8f9f7	3500	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3501	* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
<>	144:ef7eb2e8f9f7	3502	* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
<>	144:ef7eb2e8f9f7	3503	* @retval None
<>	144:ef7eb2e8f9f7	3504	*/
<>	144:ef7eb2e8f9f7	3505	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
<>	144:ef7eb2e8f9f7	3506	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
<>	144:ef7eb2e8f9f7	3507
<>	144:ef7eb2e8f9f7	3508
<>	144:ef7eb2e8f9f7	3509	/** @brief Macro to configure the MCO clock.
<>	144:ef7eb2e8f9f7	3510	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	3511	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3512	* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
<>	144:ef7eb2e8f9f7	3513	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
<>	144:ef7eb2e8f9f7	3514	* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	3515	* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	3516	* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
<>	144:ef7eb2e8f9f7	3517	* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
<>	144:ef7eb2e8f9f7	3518	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	3519	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
<>	144:ef7eb2e8f9f7	3520	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3521	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
<>	144:ef7eb2e8f9f7	3522	@endif
<>	144:ef7eb2e8f9f7	3523	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	3524	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3525	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
<>	144:ef7eb2e8f9f7	3526	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
<>	144:ef7eb2e8f9f7	3527	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
<>	144:ef7eb2e8f9f7	3528	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
<>	144:ef7eb2e8f9f7	3529	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
<>	144:ef7eb2e8f9f7	3530	*/
<>	144:ef7eb2e8f9f7	3531	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	3532	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	3533
<>	144:ef7eb2e8f9f7	3534	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	3535	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	3536	* @{
<>	144:ef7eb2e8f9f7	3537	*/
<>	144:ef7eb2e8f9f7	3538
<>	144:ef7eb2e8f9f7	3539	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
<>	144:ef7eb2e8f9f7	3540	* the selected interrupts).
<>	144:ef7eb2e8f9f7	3541	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	3542	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	3543	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	3544	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	3545	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3546	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3547	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	3548	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
<>	144:ef7eb2e8f9f7	3549	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	3550	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
<>	144:ef7eb2e8f9f7	3551	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3552	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3553	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
<>	144:ef7eb2e8f9f7	3554	@endif
<>	144:ef7eb2e8f9f7	3555	* @retval None
<>	144:ef7eb2e8f9f7	3556	*/
<>	144:ef7eb2e8f9f7	3557	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	3558
<>	144:ef7eb2e8f9f7	3559	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
<>	144:ef7eb2e8f9f7	3560	* the selected interrupts).
<>	144:ef7eb2e8f9f7	3561	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	3562	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	3563	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	3564	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	3565	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3566	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3567	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	3568	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
<>	144:ef7eb2e8f9f7	3569	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	3570	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
<>	144:ef7eb2e8f9f7	3571	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3572	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3573	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
<>	144:ef7eb2e8f9f7	3574	@endif
<>	144:ef7eb2e8f9f7	3575	* @retval None
<>	144:ef7eb2e8f9f7	3576	*/
<>	144:ef7eb2e8f9f7	3577	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	3578
<>	144:ef7eb2e8f9f7	3579	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
<>	144:ef7eb2e8f9f7	3580	* bits to clear the selected interrupt pending bits.
<>	144:ef7eb2e8f9f7	3581	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	3582	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	3583	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	3584	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	3585	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<>	144:ef7eb2e8f9f7	3586	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3587	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	3588	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
<>	144:ef7eb2e8f9f7	3589	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	3590	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
<>	144:ef7eb2e8f9f7	3591	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3592	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3593	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3594	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
<>	144:ef7eb2e8f9f7	3595	@endif
<>	144:ef7eb2e8f9f7	3596	* @retval None
<>	144:ef7eb2e8f9f7	3597	*/
<>	144:ef7eb2e8f9f7	3598	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600	/** @brief Check whether the RCC interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	3601	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	3602	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3603	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	3604	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	3605	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<>	144:ef7eb2e8f9f7	3606	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	3607	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	3608	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
<>	144:ef7eb2e8f9f7	3609	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	3610	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
<>	144:ef7eb2e8f9f7	3611	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3612	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
<>	144:ef7eb2e8f9f7	3613	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3614	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
<>	144:ef7eb2e8f9f7	3615	@endif
<>	144:ef7eb2e8f9f7	3616	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	3617	*/
<>	144:ef7eb2e8f9f7	3618	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	3619
<>	144:ef7eb2e8f9f7	3620	/** @brief Set RMVF bit to clear the reset flags.
<>	144:ef7eb2e8f9f7	3621	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
<>	144:ef7eb2e8f9f7	3622	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
<>	144:ef7eb2e8f9f7	3623	* @retval None
<>	144:ef7eb2e8f9f7	3624	*/
<>	144:ef7eb2e8f9f7	3625	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	3626
<>	144:ef7eb2e8f9f7	3627	/** @brief Check whether the selected RCC flag is set or not.
<>	144:ef7eb2e8f9f7	3628	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	3629	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3630	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
<>	144:ef7eb2e8f9f7	3631	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
<>	144:ef7eb2e8f9f7	3632	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
<>	144:ef7eb2e8f9f7	3633	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
<>	144:ef7eb2e8f9f7	3634	* @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
<>	144:ef7eb2e8f9f7	3635	* @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
<>	144:ef7eb2e8f9f7	3636	@if STM32L443xx
<>	144:ef7eb2e8f9f7	3637	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
<>	144:ef7eb2e8f9f7	3638	@endif
<>	144:ef7eb2e8f9f7	3639	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
<>	144:ef7eb2e8f9f7	3640	* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
<>	144:ef7eb2e8f9f7	3641	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
<>	144:ef7eb2e8f9f7	3642	* @arg @ref RCC_FLAG_BORRST BOR reset
<>	144:ef7eb2e8f9f7	3643	* @arg @ref RCC_FLAG_OBLRST OBLRST reset
<>	144:ef7eb2e8f9f7	3644	* @arg @ref RCC_FLAG_PINRST Pin reset
<>	144:ef7eb2e8f9f7	3645	* @arg @ref RCC_FLAG_FWRST FIREWALL reset
<>	144:ef7eb2e8f9f7	3646	* @arg @ref RCC_FLAG_RMVF Remove reset Flag
<>	144:ef7eb2e8f9f7	3647	* @arg @ref RCC_FLAG_SFTRST Software reset
<>	144:ef7eb2e8f9f7	3648	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
<>	144:ef7eb2e8f9f7	3649	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
<>	144:ef7eb2e8f9f7	3650	* @arg @ref RCC_FLAG_LPWRRST Low Power reset
<>	144:ef7eb2e8f9f7	3651	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	3652	*/
<>	144:ef7eb2e8f9f7	3653	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3654	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
<>	144:ef7eb2e8f9f7	3655	((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
<>	144:ef7eb2e8f9f7	3656	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
<>	144:ef7eb2e8f9f7	3657	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
<>	144:ef7eb2e8f9f7	3658	((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
<>	144:ef7eb2e8f9f7	3659	? 1U : 0U)
<>	144:ef7eb2e8f9f7	3660	#else
<>	144:ef7eb2e8f9f7	3661	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
<>	144:ef7eb2e8f9f7	3662	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
<>	144:ef7eb2e8f9f7	3663	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
<>	144:ef7eb2e8f9f7	3664	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
<>	144:ef7eb2e8f9f7	3665	? 1U : 0U)
<>	144:ef7eb2e8f9f7	3666	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3667
<>	144:ef7eb2e8f9f7	3668	/**
<>	144:ef7eb2e8f9f7	3669	* @}
<>	144:ef7eb2e8f9f7	3670	*/
<>	144:ef7eb2e8f9f7	3671
<>	144:ef7eb2e8f9f7	3672	/**
<>	144:ef7eb2e8f9f7	3673	* @}
<>	144:ef7eb2e8f9f7	3674	*/
<>	144:ef7eb2e8f9f7	3675
<>	144:ef7eb2e8f9f7	3676	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3677	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	3678	* @{
<>	144:ef7eb2e8f9f7	3679	*/
<>	144:ef7eb2e8f9f7	3680	/* Defines used for Flags */
<>	144:ef7eb2e8f9f7	3681	#define CR_REG_INDEX ((uint32_t)1U)
<>	144:ef7eb2e8f9f7	3682	#define BDCR_REG_INDEX ((uint32_t)2U)
<>	144:ef7eb2e8f9f7	3683	#define CSR_REG_INDEX ((uint32_t)3U)
<>	144:ef7eb2e8f9f7	3684	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3685	#define CRRCR_REG_INDEX ((uint32_t)4U)
<>	144:ef7eb2e8f9f7	3686	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3687
<>	144:ef7eb2e8f9f7	3688	#define RCC_FLAG_MASK ((uint32_t)0x1FU)
<>	144:ef7eb2e8f9f7	3689	/**
<>	144:ef7eb2e8f9f7	3690	* @}
<>	144:ef7eb2e8f9f7	3691	*/
<>	144:ef7eb2e8f9f7	3692
<>	144:ef7eb2e8f9f7	3693	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3694	/** @addtogroup RCC_Private_Macros
<>	144:ef7eb2e8f9f7	3695	* @{
<>	144:ef7eb2e8f9f7	3696	*/
<>	144:ef7eb2e8f9f7	3697
<>	144:ef7eb2e8f9f7	3698	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3699	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3700	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	3701	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3702	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) \|\| \
<>	144:ef7eb2e8f9f7	3703	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3704	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3705	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
<>	144:ef7eb2e8f9f7	3706	#else
<>	144:ef7eb2e8f9f7	3707	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3708	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	3709	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3710	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3711	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3712	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
<>	144:ef7eb2e8f9f7	3713	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3714
<>	144:ef7eb2e8f9f7	3715	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	3716	((__HSE__) == RCC_HSE_BYPASS))
<>	144:ef7eb2e8f9f7	3717
<>	144:ef7eb2e8f9f7	3718	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	3719	((__LSE__) == RCC_LSE_BYPASS))
<>	144:ef7eb2e8f9f7	3720
<>	144:ef7eb2e8f9f7	3721	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	3722
<>	144:ef7eb2e8f9f7	3723	#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
<>	144:ef7eb2e8f9f7	3724
<>	144:ef7eb2e8f9f7	3725	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
<>	144:ef7eb2e8f9f7	3726
<>	144:ef7eb2e8f9f7	3727	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
<>	144:ef7eb2e8f9f7	3728
<>	144:ef7eb2e8f9f7	3729	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
<>	144:ef7eb2e8f9f7	3730
<>	144:ef7eb2e8f9f7	3731	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3732	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
<>	144:ef7eb2e8f9f7	3733	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3734
<>	144:ef7eb2e8f9f7	3735	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
<>	144:ef7eb2e8f9f7	3736	((__PLL__) == RCC_PLL_ON))
<>	144:ef7eb2e8f9f7	3737
<>	144:ef7eb2e8f9f7	3738	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3739	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3740	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3741	((__SOURCE__) == RCC_PLLSOURCE_HSE))
<>	144:ef7eb2e8f9f7	3742
<>	144:ef7eb2e8f9f7	3743	#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
<>	144:ef7eb2e8f9f7	3744
<>	144:ef7eb2e8f9f7	3745	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
<>	144:ef7eb2e8f9f7	3746
<>	144:ef7eb2e8f9f7	3747	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	3748	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
<>	144:ef7eb2e8f9f7	3749	#else
<>	144:ef7eb2e8f9f7	3750	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
<>	144:ef7eb2e8f9f7	3751	#endif /RCC_PLLP_DIV_2_31_SUPPORT /
<>	144:ef7eb2e8f9f7	3752
<>	144:ef7eb2e8f9f7	3753	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
<>	144:ef7eb2e8f9f7	3754	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
<>	144:ef7eb2e8f9f7	3755
<>	144:ef7eb2e8f9f7	3756	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
<>	144:ef7eb2e8f9f7	3757	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
<>	144:ef7eb2e8f9f7	3758
<>	144:ef7eb2e8f9f7	3759	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
<>	144:ef7eb2e8f9f7	3760	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
<>	144:ef7eb2e8f9f7	3761	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
<>	144:ef7eb2e8f9f7	3762	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0U))
<>	144:ef7eb2e8f9f7	3763
<>	144:ef7eb2e8f9f7	3764	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	3765	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) \|\| \
<>	144:ef7eb2e8f9f7	3766	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
<>	144:ef7eb2e8f9f7	3767	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0U))
<>	144:ef7eb2e8f9f7	3768	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	3769
<>	144:ef7eb2e8f9f7	3770	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
<>	144:ef7eb2e8f9f7	3771	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
<>	144:ef7eb2e8f9f7	3772	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
<>	144:ef7eb2e8f9f7	3773	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
<>	144:ef7eb2e8f9f7	3774	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
<>	144:ef7eb2e8f9f7	3775	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
<>	144:ef7eb2e8f9f7	3776	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
<>	144:ef7eb2e8f9f7	3777	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
<>	144:ef7eb2e8f9f7	3778	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
<>	144:ef7eb2e8f9f7	3779	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
<>	144:ef7eb2e8f9f7	3780	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
<>	144:ef7eb2e8f9f7	3781	((__RANGE__) == RCC_MSIRANGE_11))
<>	144:ef7eb2e8f9f7	3782
<>	144:ef7eb2e8f9f7	3783	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
<>	144:ef7eb2e8f9f7	3784	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
<>	144:ef7eb2e8f9f7	3785	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
<>	144:ef7eb2e8f9f7	3786	((__RANGE__) == RCC_MSIRANGE_7))
<>	144:ef7eb2e8f9f7	3787
<>	144:ef7eb2e8f9f7	3788	#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3791	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3792	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	3793	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	3794
<>	144:ef7eb2e8f9f7	3795	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	3796	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	3797	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	3798	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	3799	((__HCLK__) == RCC_SYSCLK_DIV512))
<>	144:ef7eb2e8f9f7	3800
<>	144:ef7eb2e8f9f7	3801	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	3802	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	3803	((__PCLK__) == RCC_HCLK_DIV16))
<>	144:ef7eb2e8f9f7	3804
<>	144:ef7eb2e8f9f7	3805	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
<>	144:ef7eb2e8f9f7	3806	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3807	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3808	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
<>	144:ef7eb2e8f9f7	3809
<>	144:ef7eb2e8f9f7	3810	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
<>	144:ef7eb2e8f9f7	3811
<>	144:ef7eb2e8f9f7	3812	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	3813	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
<>	144:ef7eb2e8f9f7	3814	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3815	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3816	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3817	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	3818	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
<>	144:ef7eb2e8f9f7	3819	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3820	((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3821	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
<>	144:ef7eb2e8f9f7	3822	#else
<>	144:ef7eb2e8f9f7	3823	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
<>	144:ef7eb2e8f9f7	3824	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3825	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3826	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3827	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	3828	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
<>	144:ef7eb2e8f9f7	3829	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3830	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
<>	144:ef7eb2e8f9f7	3831	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	3832
<>	144:ef7eb2e8f9f7	3833	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
<>	144:ef7eb2e8f9f7	3834	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
<>	144:ef7eb2e8f9f7	3835	((__DIV__) == RCC_MCODIV_16))
<>	144:ef7eb2e8f9f7	3836
<>	144:ef7eb2e8f9f7	3837	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
<>	144:ef7eb2e8f9f7	3838	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
<>	144:ef7eb2e8f9f7	3839	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
<>	144:ef7eb2e8f9f7	3840	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
<>	144:ef7eb2e8f9f7	3841
<>	144:ef7eb2e8f9f7	3842	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
<>	144:ef7eb2e8f9f7	3843	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
<>	144:ef7eb2e8f9f7	3844	/**
<>	144:ef7eb2e8f9f7	3845	* @}
<>	144:ef7eb2e8f9f7	3846	*/
<>	144:ef7eb2e8f9f7	3847
<>	144:ef7eb2e8f9f7	3848	/* Include RCC HAL Extended module */
<>	144:ef7eb2e8f9f7	3849	#include "stm32l4xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	3850
<>	144:ef7eb2e8f9f7	3851	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3852	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	3853	* @{
<>	144:ef7eb2e8f9f7	3854	*/
<>	144:ef7eb2e8f9f7	3855
<>	144:ef7eb2e8f9f7	3856
<>	144:ef7eb2e8f9f7	3857	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	3858	* @{
<>	144:ef7eb2e8f9f7	3859	*/
<>	144:ef7eb2e8f9f7	3860
<>	144:ef7eb2e8f9f7	3861	/* Initialization and de-initialization functions ******************************/
<>	144:ef7eb2e8f9f7	3862	void HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	3863	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	3864	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	3865
<>	144:ef7eb2e8f9f7	3866	/**
<>	144:ef7eb2e8f9f7	3867	* @}
<>	144:ef7eb2e8f9f7	3868	*/
<>	144:ef7eb2e8f9f7	3869
<>	144:ef7eb2e8f9f7	3870	/** @addtogroup RCC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	3871	* @{
<>	144:ef7eb2e8f9f7	3872	*/
<>	144:ef7eb2e8f9f7	3873
<>	144:ef7eb2e8f9f7	3874	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	3875	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	3876	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	3877	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	3878	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	3879	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	3880	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	3881	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	3882	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	3883	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	3884	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	3885	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	3886	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	3887
<>	144:ef7eb2e8f9f7	3888	/**
<>	144:ef7eb2e8f9f7	3889	* @}
<>	144:ef7eb2e8f9f7	3890	*/
<>	144:ef7eb2e8f9f7	3891
<>	144:ef7eb2e8f9f7	3892	/**
<>	144:ef7eb2e8f9f7	3893	* @}
<>	144:ef7eb2e8f9f7	3894	*/
<>	144:ef7eb2e8f9f7	3895
<>	144:ef7eb2e8f9f7	3896	/**
<>	144:ef7eb2e8f9f7	3897	* @}
<>	144:ef7eb2e8f9f7	3898	*/
<>	144:ef7eb2e8f9f7	3899
<>	144:ef7eb2e8f9f7	3900	/**
<>	144:ef7eb2e8f9f7	3901	* @}
<>	144:ef7eb2e8f9f7	3902	*/
<>	144:ef7eb2e8f9f7	3903
<>	144:ef7eb2e8f9f7	3904	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	3905	}
<>	144:ef7eb2e8f9f7	3906	#endif
<>	144:ef7eb2e8f9f7	3907
<>	144:ef7eb2e8f9f7	3908	#endif /* __STM32L4xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	3909
<>	144:ef7eb2e8f9f7	3910	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	17 Oct 2016
Imports:	2
Forks:	0
Commits:	149
Dependents:	0
Dependencies:	0
Followers:	4

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@148:4802eb17e82b, 2016-10-17 (annotated)

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