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mbed-os/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device/system_MK20D5.c@1:b36bbc1c6d27, 2020-04-11 (annotated)

Committer:
demayer
Date:
Sat Apr 11 08:15:48 2020 +0000
Revision:
1:b36bbc1c6d27
Parent:
0:6bf0743ece18 
IMU-library in .h und .cpp file aufgeteilt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
demayer 0:6bf0743ece18 1 /*
demayer 0:6bf0743ece18 2 ** ###################################################################
demayer 0:6bf0743ece18 3 ** Compilers: ARM Compiler
demayer 0:6bf0743ece18 4 ** Freescale C/C++ for Embedded ARM
demayer 0:6bf0743ece18 5 ** GNU C Compiler
demayer 0:6bf0743ece18 6 ** IAR ANSI C/C++ Compiler for ARM
demayer 0:6bf0743ece18 7 **
demayer 0:6bf0743ece18 8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
demayer 0:6bf0743ece18 9 ** K20P32M50SF0RM Rev. 1, Oct 2011
demayer 0:6bf0743ece18 10 ** K20P48M50SF0RM Rev. 1, Oct 2011
demayer 0:6bf0743ece18 11 **
demayer 0:6bf0743ece18 12 ** Version: rev. 1.0, 2011-12-15
demayer 0:6bf0743ece18 13 **
demayer 0:6bf0743ece18 14 ** Abstract:
demayer 0:6bf0743ece18 15 ** Provides a system configuration function and a global variable that
demayer 0:6bf0743ece18 16 ** contains the system frequency. It configures the device and initializes
demayer 0:6bf0743ece18 17 ** the oscillator (PLL) that is part of the microcontroller device.
demayer 0:6bf0743ece18 18 **
demayer 0:6bf0743ece18 19 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
demayer 0:6bf0743ece18 20 **
demayer 0:6bf0743ece18 21 ** http: www.freescale.com
demayer 0:6bf0743ece18 22 ** mail: support@freescale.com
demayer 0:6bf0743ece18 23 **
demayer 0:6bf0743ece18 24 ** Revisions:
demayer 0:6bf0743ece18 25 ** - rev. 1.0 (2011-12-15)
demayer 0:6bf0743ece18 26 ** Initial version
demayer 0:6bf0743ece18 27 **
demayer 0:6bf0743ece18 28 ** ###################################################################
demayer 0:6bf0743ece18 29 */
demayer 0:6bf0743ece18 30
demayer 0:6bf0743ece18 31 /**
demayer 0:6bf0743ece18 32 * @file MK20D5
demayer 0:6bf0743ece18 33 * @version 1.0
demayer 0:6bf0743ece18 34 * @date 2011-12-15
demayer 0:6bf0743ece18 35 * @brief Device specific configuration file for MK20D5 (implementation file)
demayer 0:6bf0743ece18 36 *
demayer 0:6bf0743ece18 37 * Provides a system configuration function and a global variable that contains
demayer 0:6bf0743ece18 38 * the system frequency. It configures the device and initializes the oscillator
demayer 0:6bf0743ece18 39 * (PLL) that is part of the microcontroller device.
demayer 0:6bf0743ece18 40 */
demayer 0:6bf0743ece18 41
demayer 0:6bf0743ece18 42 #include <stdint.h>
demayer 0:6bf0743ece18 43 #include "MK20D5.h"
demayer 0:6bf0743ece18 44
demayer 0:6bf0743ece18 45 #define DISABLE_WDOG 1
demayer 0:6bf0743ece18 46
demayer 0:6bf0743ece18 47 #define CLOCK_SETUP 1
demayer 0:6bf0743ece18 48 /* Predefined clock setups
demayer 0:6bf0743ece18 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
demayer 0:6bf0743ece18 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
demayer 0:6bf0743ece18 51 Core clock = 41.94MHz, BusClock = 41.94MHz
demayer 0:6bf0743ece18 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
demayer 0:6bf0743ece18 53 Reference clock source for MCG module is an external crystal 8MHz
demayer 0:6bf0743ece18 54 Core clock = 48MHz, BusClock = 48MHz
demayer 0:6bf0743ece18 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
demayer 0:6bf0743ece18 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
demayer 0:6bf0743ece18 57 Core clock = 8MHz, BusClock = 8MHz
demayer 0:6bf0743ece18 58 */
demayer 0:6bf0743ece18 59
demayer 0:6bf0743ece18 60 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 61 Define clock source values
demayer 0:6bf0743ece18 62 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 63 #if (CLOCK_SETUP == 0)
demayer 0:6bf0743ece18 64 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 65 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 66 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 67 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 68 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
demayer 0:6bf0743ece18 69 #elif (CLOCK_SETUP == 1)
demayer 0:6bf0743ece18 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 71 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 72 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 73 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 74 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
demayer 0:6bf0743ece18 75 #elif (CLOCK_SETUP == 2)
demayer 0:6bf0743ece18 76 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 77 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
demayer 0:6bf0743ece18 80 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
demayer 0:6bf0743ece18 81 #endif /* (CLOCK_SETUP == 2) */
demayer 0:6bf0743ece18 82
demayer 0:6bf0743ece18 83
demayer 0:6bf0743ece18 84 /* ----------------------------------------------------------------------------
demayer 0:6bf0743ece18 85 -- Core clock
demayer 0:6bf0743ece18 86 ---------------------------------------------------------------------------- */
demayer 0:6bf0743ece18 87
demayer 0:6bf0743ece18 88 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
demayer 0:6bf0743ece18 89
demayer 0:6bf0743ece18 90 /* ----------------------------------------------------------------------------
demayer 0:6bf0743ece18 91 -- SystemInit()
demayer 0:6bf0743ece18 92 ---------------------------------------------------------------------------- */
demayer 0:6bf0743ece18 93
demayer 0:6bf0743ece18 94 void SystemInit (void) {
demayer 0:6bf0743ece18 95 #if (DISABLE_WDOG)
demayer 0:6bf0743ece18 96 /* Disable the WDOG module */
demayer 0:6bf0743ece18 97 /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
demayer 0:6bf0743ece18 98 WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
demayer 0:6bf0743ece18 99 /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
demayer 0:6bf0743ece18 100 WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
demayer 0:6bf0743ece18 101 /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
demayer 0:6bf0743ece18 102 WDOG->STCTRLH = (uint16_t)0x01D2u;
demayer 0:6bf0743ece18 103 #endif /* (DISABLE_WDOG) */
demayer 0:6bf0743ece18 104 #if (CLOCK_SETUP == 0)
demayer 0:6bf0743ece18 105 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
demayer 0:6bf0743ece18 106 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
demayer 0:6bf0743ece18 107 /* Switch to FEI Mode */
demayer 0:6bf0743ece18 108 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
demayer 0:6bf0743ece18 109 MCG->C1 = (uint8_t)0x06u;
demayer 0:6bf0743ece18 110 /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
demayer 0:6bf0743ece18 111 MCG->C2 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 112 /* MCG_C4: DMX32=0,DRST_DRS=1 */
demayer 0:6bf0743ece18 113 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
demayer 0:6bf0743ece18 114 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
demayer 0:6bf0743ece18 115 MCG->C5 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 116 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
demayer 0:6bf0743ece18 117 MCG->C6 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 118 while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
demayer 0:6bf0743ece18 119 }
demayer 0:6bf0743ece18 120 while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
demayer 0:6bf0743ece18 121 }
demayer 0:6bf0743ece18 122 #elif (CLOCK_SETUP == 1)
demayer 0:6bf0743ece18 123 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
demayer 0:6bf0743ece18 124 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
demayer 0:6bf0743ece18 125 /* Switch to FBE Mode */
demayer 0:6bf0743ece18 126 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
demayer 0:6bf0743ece18 127 OSC0->CR = (uint8_t)0x00u;
demayer 0:6bf0743ece18 128 /* MCG->C7: OSCSEL=0 */
demayer 0:6bf0743ece18 129 MCG->C7 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 130 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
demayer 0:6bf0743ece18 131 MCG->C2 = (uint8_t)0x24u;
demayer 0:6bf0743ece18 132 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
demayer 0:6bf0743ece18 133 MCG->C1 = (uint8_t)0x9Au;
demayer 0:6bf0743ece18 134 /* MCG->C4: DMX32=0,DRST_DRS=0 */
demayer 0:6bf0743ece18 135 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
demayer 0:6bf0743ece18 136 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
demayer 0:6bf0743ece18 137 MCG->C5 = (uint8_t)0x03u;
demayer 0:6bf0743ece18 138 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
demayer 0:6bf0743ece18 139 MCG->C6 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 140 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
demayer 0:6bf0743ece18 141 }
demayer 0:6bf0743ece18 142 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
demayer 0:6bf0743ece18 143 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
demayer 0:6bf0743ece18 144 }
demayer 0:6bf0743ece18 145 #endif
demayer 0:6bf0743ece18 146 while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
demayer 0:6bf0743ece18 147 }
demayer 0:6bf0743ece18 148 /* Switch to PBE Mode */
demayer 0:6bf0743ece18 149 /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
demayer 0:6bf0743ece18 150 MCG->C5 = (uint8_t)0x03u;
demayer 0:6bf0743ece18 151 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
demayer 0:6bf0743ece18 152 MCG->C6 = (uint8_t)0x40u;
demayer 0:6bf0743ece18 153 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
demayer 0:6bf0743ece18 154 }
demayer 0:6bf0743ece18 155 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
demayer 0:6bf0743ece18 156 }
demayer 0:6bf0743ece18 157 /* Switch to PEE Mode */
demayer 0:6bf0743ece18 158 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
demayer 0:6bf0743ece18 159 MCG->C1 = (uint8_t)0x1Au;
demayer 0:6bf0743ece18 160 while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
demayer 0:6bf0743ece18 161 }
demayer 0:6bf0743ece18 162 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
demayer 0:6bf0743ece18 163 }
demayer 0:6bf0743ece18 164 #elif (CLOCK_SETUP == 2)
demayer 0:6bf0743ece18 165 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
demayer 0:6bf0743ece18 166 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
demayer 0:6bf0743ece18 167 /* Switch to FBE Mode */
demayer 0:6bf0743ece18 168 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
demayer 0:6bf0743ece18 169 OSC0->CR = (uint8_t)0x00u;
demayer 0:6bf0743ece18 170 /* MCG->C7: OSCSEL=0 */
demayer 0:6bf0743ece18 171 MCG->C7 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 172 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
demayer 0:6bf0743ece18 173 MCG->C2 = (uint8_t)0x24u;
demayer 0:6bf0743ece18 174 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
demayer 0:6bf0743ece18 175 MCG->C1 = (uint8_t)0x9Au;
demayer 0:6bf0743ece18 176 /* MCG->C4: DMX32=0,DRST_DRS=0 */
demayer 0:6bf0743ece18 177 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
demayer 0:6bf0743ece18 178 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
demayer 0:6bf0743ece18 179 MCG->C5 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 180 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
demayer 0:6bf0743ece18 181 MCG->C6 = (uint8_t)0x00u;
demayer 0:6bf0743ece18 182 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
demayer 0:6bf0743ece18 183 }
demayer 0:6bf0743ece18 184 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
demayer 0:6bf0743ece18 185 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
demayer 0:6bf0743ece18 186 }
demayer 0:6bf0743ece18 187 #endif
demayer 0:6bf0743ece18 188 while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
demayer 0:6bf0743ece18 189 }
demayer 0:6bf0743ece18 190 /* Switch to BLPE Mode */
demayer 0:6bf0743ece18 191 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
demayer 0:6bf0743ece18 192 MCG->C2 = (uint8_t)0x24u;
demayer 0:6bf0743ece18 193 #endif /* (CLOCK_SETUP == 2) */
demayer 0:6bf0743ece18 194 }
demayer 0:6bf0743ece18 195
demayer 0:6bf0743ece18 196 /* ----------------------------------------------------------------------------
demayer 0:6bf0743ece18 197 -- SystemCoreClockUpdate()
demayer 0:6bf0743ece18 198 ---------------------------------------------------------------------------- */
demayer 0:6bf0743ece18 199
demayer 0:6bf0743ece18 200 void SystemCoreClockUpdate (void) {
demayer 0:6bf0743ece18 201 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
demayer 0:6bf0743ece18 202 uint8_t Divider;
demayer 0:6bf0743ece18 203
demayer 0:6bf0743ece18 204 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
demayer 0:6bf0743ece18 205 /* Output of FLL or PLL is selected */
demayer 0:6bf0743ece18 206 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
demayer 0:6bf0743ece18 207 /* FLL is selected */
demayer 0:6bf0743ece18 208 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
demayer 0:6bf0743ece18 209 /* External reference clock is selected */
demayer 0:6bf0743ece18 210 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
demayer 0:6bf0743ece18 211 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
demayer 0:6bf0743ece18 212 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 213 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
demayer 0:6bf0743ece18 214 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 215 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
demayer 0:6bf0743ece18 216 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
demayer 0:6bf0743ece18 217 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
demayer 0:6bf0743ece18 218 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
demayer 0:6bf0743ece18 219 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
demayer 0:6bf0743ece18 220 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 221 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
demayer 0:6bf0743ece18 222 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 223 /* Select correct multiplier to calculate the MCG output clock */
demayer 0:6bf0743ece18 224 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
demayer 0:6bf0743ece18 225 case 0x0u:
demayer 0:6bf0743ece18 226 MCGOUTClock *= 640u;
demayer 0:6bf0743ece18 227 break;
demayer 0:6bf0743ece18 228 case 0x20u:
demayer 0:6bf0743ece18 229 MCGOUTClock *= 1280u;
demayer 0:6bf0743ece18 230 break;
demayer 0:6bf0743ece18 231 case 0x40u:
demayer 0:6bf0743ece18 232 MCGOUTClock *= 1920u;
demayer 0:6bf0743ece18 233 break;
demayer 0:6bf0743ece18 234 case 0x60u:
demayer 0:6bf0743ece18 235 MCGOUTClock *= 2560u;
demayer 0:6bf0743ece18 236 break;
demayer 0:6bf0743ece18 237 case 0x80u:
demayer 0:6bf0743ece18 238 MCGOUTClock *= 732u;
demayer 0:6bf0743ece18 239 break;
demayer 0:6bf0743ece18 240 case 0xA0u:
demayer 0:6bf0743ece18 241 MCGOUTClock *= 1464u;
demayer 0:6bf0743ece18 242 break;
demayer 0:6bf0743ece18 243 case 0xC0u:
demayer 0:6bf0743ece18 244 MCGOUTClock *= 2197u;
demayer 0:6bf0743ece18 245 break;
demayer 0:6bf0743ece18 246 case 0xE0u:
demayer 0:6bf0743ece18 247 MCGOUTClock *= 2929u;
demayer 0:6bf0743ece18 248 break;
demayer 0:6bf0743ece18 249 default:
demayer 0:6bf0743ece18 250 break;
demayer 0:6bf0743ece18 251 }
demayer 0:6bf0743ece18 252 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 253 /* PLL is selected */
demayer 0:6bf0743ece18 254 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
demayer 0:6bf0743ece18 255 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
demayer 0:6bf0743ece18 256 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
demayer 0:6bf0743ece18 257 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
demayer 0:6bf0743ece18 258 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 259 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
demayer 0:6bf0743ece18 260 /* Internal reference clock is selected */
demayer 0:6bf0743ece18 261 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
demayer 0:6bf0743ece18 262 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
demayer 0:6bf0743ece18 263 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 264 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
demayer 0:6bf0743ece18 265 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 266 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
demayer 0:6bf0743ece18 267 /* External reference clock is selected */
demayer 0:6bf0743ece18 268 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
demayer 0:6bf0743ece18 269 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
demayer 0:6bf0743ece18 270 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 271 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
demayer 0:6bf0743ece18 272 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
demayer 0:6bf0743ece18 273 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
demayer 0:6bf0743ece18 274 /* Reserved value */
demayer 0:6bf0743ece18 275 return;
demayer 0:6bf0743ece18 276 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
demayer 0:6bf0743ece18 277 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
demayer 0:6bf0743ece18 278 }