PES2_R2D2.0 / Mbed 2 deprecated MicroMouse_MASTER_FOUR

Pathfinding nach rechts funktioniert noch nicht...der rest schon

Dependencies:   mbed

Fork of MicroMouse_MASTER_THREE by PES2_R2D2.0

EncoderCounter.cpp@0:a9fe4ef404bf, 2018-03-07 (annotated)

Committer:
ruesipat
Date:
Wed Mar 07 14:06:19 2018 +0000
Revision:
0:a9fe4ef404bf
Child:
1:d9e840c48b1e
hallo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ruesipat 0:a9fe4ef404bf 1 /*
ruesipat 0:a9fe4ef404bf 2 * EncoderCounter.cpp
ruesipat 0:a9fe4ef404bf 3 * Copyright (c) 2018, ZHAW
ruesipat 0:a9fe4ef404bf 4 * All rights reserved.
ruesipat 0:a9fe4ef404bf 5 */
ruesipat 0:a9fe4ef404bf 6
ruesipat 0:a9fe4ef404bf 7 #include "EncoderCounter.h"
ruesipat 0:a9fe4ef404bf 8
ruesipat 0:a9fe4ef404bf 9 using namespace std;
ruesipat 0:a9fe4ef404bf 10
ruesipat 0:a9fe4ef404bf 11 /**
ruesipat 0:a9fe4ef404bf 12 * Creates and initializes the driver to read the quadrature
ruesipat 0:a9fe4ef404bf 13 * encoder counter of the STM32 microcontroller.
ruesipat 0:a9fe4ef404bf 14 * @param a the input pin for the channel A.
ruesipat 0:a9fe4ef404bf 15 * @param b the input pin for the channel B.
ruesipat 0:a9fe4ef404bf 16 */
ruesipat 0:a9fe4ef404bf 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
ruesipat 0:a9fe4ef404bf 18
ruesipat 0:a9fe4ef404bf 19 // check pins
ruesipat 0:a9fe4ef404bf 20
ruesipat 0:a9fe4ef404bf 21 if ((a == PA_0) && (b == PA_1)) {
ruesipat 0:a9fe4ef404bf 22
ruesipat 0:a9fe4ef404bf 23 // pinmap OK for TIM2 CH1 and CH2
ruesipat 0:a9fe4ef404bf 24
ruesipat 0:a9fe4ef404bf 25 TIM = TIM2;
ruesipat 0:a9fe4ef404bf 26
ruesipat 0:a9fe4ef404bf 27 // configure general purpose I/O registers
ruesipat 0:a9fe4ef404bf 28
ruesipat 0:a9fe4ef404bf 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
ruesipat 0:a9fe4ef404bf 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
ruesipat 0:a9fe4ef404bf 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
ruesipat 0:a9fe4ef404bf 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
ruesipat 0:a9fe4ef404bf 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
ruesipat 0:a9fe4ef404bf 35
ruesipat 0:a9fe4ef404bf 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
ruesipat 0:a9fe4ef404bf 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
ruesipat 0:a9fe4ef404bf 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
ruesipat 0:a9fe4ef404bf 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
ruesipat 0:a9fe4ef404bf 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
ruesipat 0:a9fe4ef404bf 42
ruesipat 0:a9fe4ef404bf 43 // configure reset and clock control registers
ruesipat 0:a9fe4ef404bf 44
ruesipat 0:a9fe4ef404bf 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
ruesipat 0:a9fe4ef404bf 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
ruesipat 0:a9fe4ef404bf 47
ruesipat 0:a9fe4ef404bf 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
ruesipat 0:a9fe4ef404bf 49
ruesipat 0:a9fe4ef404bf 50 } else if ((a == PA_6) && (b == PC_7)) {
ruesipat 0:a9fe4ef404bf 51
ruesipat 0:a9fe4ef404bf 52 // pinmap OK for TIM3 CH1 and CH2
ruesipat 0:a9fe4ef404bf 53
ruesipat 0:a9fe4ef404bf 54 TIM = TIM3;
ruesipat 0:a9fe4ef404bf 55
ruesipat 0:a9fe4ef404bf 56 // configure reset and clock control registers
ruesipat 0:a9fe4ef404bf 57
ruesipat 0:a9fe4ef404bf 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
ruesipat 0:a9fe4ef404bf 59
ruesipat 0:a9fe4ef404bf 60 // configure general purpose I/O registers
ruesipat 0:a9fe4ef404bf 61
ruesipat 0:a9fe4ef404bf 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
ruesipat 0:a9fe4ef404bf 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
ruesipat 0:a9fe4ef404bf 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
ruesipat 0:a9fe4ef404bf 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
ruesipat 0:a9fe4ef404bf 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
ruesipat 0:a9fe4ef404bf 68
ruesipat 0:a9fe4ef404bf 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
ruesipat 0:a9fe4ef404bf 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
ruesipat 0:a9fe4ef404bf 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
ruesipat 0:a9fe4ef404bf 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
ruesipat 0:a9fe4ef404bf 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
ruesipat 0:a9fe4ef404bf 75
ruesipat 0:a9fe4ef404bf 76 // configure reset and clock control registers
ruesipat 0:a9fe4ef404bf 77
ruesipat 0:a9fe4ef404bf 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
ruesipat 0:a9fe4ef404bf 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
ruesipat 0:a9fe4ef404bf 80
ruesipat 0:a9fe4ef404bf 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
ruesipat 0:a9fe4ef404bf 82
ruesipat 0:a9fe4ef404bf 83 } else if ((a == PB_6) && (b == PB_7)) {
ruesipat 0:a9fe4ef404bf 84
ruesipat 0:a9fe4ef404bf 85 // pinmap OK for TIM4 CH1 and CH2
ruesipat 0:a9fe4ef404bf 86
ruesipat 0:a9fe4ef404bf 87 TIM = TIM4;
ruesipat 0:a9fe4ef404bf 88
ruesipat 0:a9fe4ef404bf 89 // configure reset and clock control registers
ruesipat 0:a9fe4ef404bf 90
ruesipat 0:a9fe4ef404bf 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
ruesipat 0:a9fe4ef404bf 92
ruesipat 0:a9fe4ef404bf 93 // configure general purpose I/O registers
ruesipat 0:a9fe4ef404bf 94
ruesipat 0:a9fe4ef404bf 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
ruesipat 0:a9fe4ef404bf 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
ruesipat 0:a9fe4ef404bf 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
ruesipat 0:a9fe4ef404bf 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
ruesipat 0:a9fe4ef404bf 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
ruesipat 0:a9fe4ef404bf 101
ruesipat 0:a9fe4ef404bf 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
ruesipat 0:a9fe4ef404bf 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
ruesipat 0:a9fe4ef404bf 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
ruesipat 0:a9fe4ef404bf 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
ruesipat 0:a9fe4ef404bf 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
ruesipat 0:a9fe4ef404bf 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
ruesipat 0:a9fe4ef404bf 108
ruesipat 0:a9fe4ef404bf 109 // configure reset and clock control registers
ruesipat 0:a9fe4ef404bf 110
ruesipat 0:a9fe4ef404bf 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
ruesipat 0:a9fe4ef404bf 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
ruesipat 0:a9fe4ef404bf 113
ruesipat 0:a9fe4ef404bf 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
ruesipat 0:a9fe4ef404bf 115
ruesipat 0:a9fe4ef404bf 116 } else {
ruesipat 0:a9fe4ef404bf 117
ruesipat 0:a9fe4ef404bf 118 printf("pinmap not found for peripheral\n");
ruesipat 0:a9fe4ef404bf 119 }
ruesipat 0:a9fe4ef404bf 120
ruesipat 0:a9fe4ef404bf 121 // configure general purpose timer 3 or 4
ruesipat 0:a9fe4ef404bf 122
ruesipat 0:a9fe4ef404bf 123 TIM->CR1 = 0x0000; // counter disable
ruesipat 0:a9fe4ef404bf 124 TIM->CR2 = 0x0000; // reset master mode selection
ruesipat 0:a9fe4ef404bf 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
ruesipat 0:a9fe4ef404bf 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
ruesipat 0:a9fe4ef404bf 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
ruesipat 0:a9fe4ef404bf 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
ruesipat 0:a9fe4ef404bf 129 TIM->CNT = 0x0000; // reset counter value
ruesipat 0:a9fe4ef404bf 130 TIM->ARR = 0xFFFF; // auto reload register
ruesipat 0:a9fe4ef404bf 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
ruesipat 0:a9fe4ef404bf 132 }
ruesipat 0:a9fe4ef404bf 133
ruesipat 0:a9fe4ef404bf 134 EncoderCounter::~EncoderCounter() {}
ruesipat 0:a9fe4ef404bf 135
ruesipat 0:a9fe4ef404bf 136 /**
ruesipat 0:a9fe4ef404bf 137 * Resets the counter value to zero.
ruesipat 0:a9fe4ef404bf 138 */
ruesipat 0:a9fe4ef404bf 139 void EncoderCounter::reset() {
ruesipat 0:a9fe4ef404bf 140
ruesipat 0:a9fe4ef404bf 141 TIM->CNT = 0x0000;
ruesipat 0:a9fe4ef404bf 142 }
ruesipat 0:a9fe4ef404bf 143
ruesipat 0:a9fe4ef404bf 144 /**
ruesipat 0:a9fe4ef404bf 145 * Resets the counter value to a given offset value.
ruesipat 0:a9fe4ef404bf 146 * @param offset the offset value to reset the counter to.
ruesipat 0:a9fe4ef404bf 147 */
ruesipat 0:a9fe4ef404bf 148 void EncoderCounter::reset(short offset) {
ruesipat 0:a9fe4ef404bf 149
ruesipat 0:a9fe4ef404bf 150 TIM->CNT = -offset;
ruesipat 0:a9fe4ef404bf 151 }
ruesipat 0:a9fe4ef404bf 152
ruesipat 0:a9fe4ef404bf 153 /**
ruesipat 0:a9fe4ef404bf 154 * Reads the quadrature encoder counter value.
ruesipat 0:a9fe4ef404bf 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
ruesipat 0:a9fe4ef404bf 156 */
ruesipat 0:a9fe4ef404bf 157 short EncoderCounter::read() {
ruesipat 0:a9fe4ef404bf 158
ruesipat 0:a9fe4ef404bf 159 return (short)(-TIM->CNT);
ruesipat 0:a9fe4ef404bf 160 }
ruesipat 0:a9fe4ef404bf 161
ruesipat 0:a9fe4ef404bf 162 /**
ruesipat 0:a9fe4ef404bf 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
ruesipat 0:a9fe4ef404bf 164 */
ruesipat 0:a9fe4ef404bf 165 EncoderCounter::operator short() {
ruesipat 0:a9fe4ef404bf 166
ruesipat 0:a9fe4ef404bf 167 return read();
ruesipat 0:a9fe4ef404bf 168 }