NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

Files at this revision

API Documentation at this revision

Revision 21:8a238b2c42d0, committed 2015-04-24

Comitter:
FSL\B36402
Date:
Fri Apr 24 17:44:59 2015 -0500
Parent:
20:933513bba8a1
Child:
22:7703e6571f21
Commit message:
Fixed __disable_irq and __enable_irq issue in IAR

Changed in this revision

FSL_IEEE802_15_4_PHY/EmbeddedTypes.h Show annotated file Show diff for this revision Revisions of this file
FSL_IEEE802_15_4_PHY/MCR20Drv/MCR20Drv.c Show annotated file Show diff for this revision Revisions of this file
FSL_IEEE802_15_4_PHY/PhyStateMachine.c Show annotated file Show diff for this revision Revisions of this file
FSL_IEEE802_15_4_PHY/PhyTime.c Show annotated file Show diff for this revision Revisions of this file 
--- a/FSL_IEEE802_15_4_PHY/EmbeddedTypes.h	Sat Apr 04 22:28:34 2015 +0000
+++ b/FSL_IEEE802_15_4_PHY/EmbeddedTypes.h	Fri Apr 24 17:44:59 2015 -0500
@@ -47,7 +47,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
-
+#include <intrinsics.h>
 
 /************************************************************************************
 *
@@ -105,5 +105,9 @@
 #define FLib_MemCpy(pDst, pSrc, size)       memcpy(pDst, pSrc, size)
 #define FLib_MemSet(pDst, value, size)      memset(pDst, value, size)
 
+#define OSA_EnterCritical(kCriticalDisableInt)  __disable_interrupt()
+#define OSA_ExitCritical(kCriticalDisableInt)   __enable_interrupt()
+
+
 #endif /* _EMBEDDEDTYPES_H_ */
 

--- a/FSL_IEEE802_15_4_PHY/MCR20Drv/MCR20Drv.c	Sat Apr 04 22:28:34 2015 +0000
+++ b/FSL_IEEE802_15_4_PHY/MCR20Drv/MCR20Drv.c	Fri Apr 24 17:44:59 2015 -0500
@@ -542,7 +542,7 @@
 void
 )
 {
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
 
     if( mPhyIrqDisableCnt == 0 )
     {
@@ -551,7 +551,7 @@
 
     mPhyIrqDisableCnt++;
 
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*---------------------------------------------------------------------------
@@ -565,7 +565,7 @@
 void
 )
 {
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
 
     if( mPhyIrqDisableCnt )
     {
@@ -577,7 +577,7 @@
         }
     }
 
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*---------------------------------------------------------------------------

--- a/FSL_IEEE802_15_4_PHY/PhyStateMachine.c	Sat Apr 04 22:28:34 2015 +0000
+++ b/FSL_IEEE802_15_4_PHY/PhyStateMachine.c	Fri Apr 24 17:44:59 2015 -0500
@@ -473,13 +473,13 @@
 
   if( pMsg->msgData.dataReq.txDuration != gPhySeqStartAsap_c )
   {
-      __disable_irq();
+      OSA_EnterCritical(kCriticalDisableInt);
       PhyTimeReadClock( &time );
       time += pMsg->msgData.dataReq.txDuration;
       /* Compensate PHY overhead, including WU time */
       time += 54;
       PhyTimeSetEventTimeout( &time );
-      __enable_irq();
+      OSA_ExitCritical(kCriticalDisableInt);
   }
 
   UnprotectFromXcvrInterrupt();
@@ -506,7 +506,7 @@
 {
     uint32_t endTime;
 
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
 
     if( gPhySeqStartAsap_c == startTime )
     {
@@ -526,7 +526,7 @@
         PhyTimeSetEventTimeout( &(endTime) );
     }
 
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -772,7 +772,7 @@
         uint32_t currentTime;
         uint32_t time;
 
-        __disable_irq();
+        OSA_EnterCritical(kCriticalDisableInt);
 
         //Read currentTime and Timeout values [sym]
         PhyTimeReadClock(&currentTime);
@@ -794,7 +794,7 @@
             MCR20Drv_DirectAccessSPIMultiByteWrite( T3CMP_LSB, (uint8_t *)&mPhySeqTimeout, 3);
         }
 
-        __enable_irq();
+        OSA_ExitCritical(kCriticalDisableInt);
     }
 
 #ifdef MAC_PHY_DEBUG

--- a/FSL_IEEE802_15_4_PHY/PhyTime.c	Sat Apr 04 22:28:34 2015 +0000
+++ b/FSL_IEEE802_15_4_PHY/PhyTime.c	Fri Apr 24 17:44:59 2015 -0500
@@ -96,7 +96,7 @@
 {
   uint8_t phyReg, phyCtrl3Reg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
   phyReg |= cPHY_CTRL1_TMRTRIGEN;    // enable autosequence start by TC2 match
@@ -118,7 +118,7 @@
   phyCtrl3Reg |= cPHY_CTRL3_TMR2CMP_EN;   // enable TMR2 compare
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -134,7 +134,7 @@
 {
   uint8_t phyReg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
   phyReg &= ~(cPHY_CTRL1_TMRTRIGEN); // disable autosequence start by TC2 match
@@ -150,7 +150,7 @@
   phyReg |= (cIRQSTS3_TMR2IRQ);      // aknowledge TMR2 IRQ
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -175,7 +175,7 @@
   }
 #endif // PHY_PARAMETERS_VALIDATION
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
   phyCtrl3Reg &= ~(cPHY_CTRL3_TMR3CMP_EN);// disable TMR3 compare
@@ -197,7 +197,7 @@
   phyCtrl3Reg |= cPHY_CTRL3_TMR3CMP_EN;   // enable TMR3 compare
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -222,7 +222,7 @@
 {
   uint8_t phyReg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
   phyReg &= ~(cPHY_CTRL4_TC3TMOUT);  // disable autosequence stop by TC3 match
@@ -237,7 +237,7 @@
   phyReg |= cIRQSTS3_TMR3IRQ;         // aknowledge TMR3 IRQ
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -258,12 +258,12 @@
   }
 #endif // PHY_PARAMETERS_VALIDATION
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) EVENT_TMR_LSB, (uint8_t *) pRetClk, 3);
   *(((uint8_t *)pRetClk) + 3) = 0;
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 
 }
 
@@ -287,7 +287,7 @@
   }
 #endif // PHY_PARAMETERS_VALIDATION
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
   phyCtrl4Reg |= cPHY_CTRL4_TMRLOAD; // self clearing bit
@@ -295,7 +295,7 @@
   MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T1CMP_LSB, (uint8_t *) pAbsTime, 3);
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyCtrl4Reg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -311,7 +311,7 @@
 {
   uint8_t phyCtrl3Reg, irqSts3Reg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
   phyCtrl3Reg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare
@@ -328,7 +328,7 @@
   phyCtrl3Reg |= cPHY_CTRL3_TMR1CMP_EN;   // enable TMR1 compare
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 
 }
 
@@ -343,7 +343,7 @@
 {
   uint8_t phyReg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
   phyReg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare
@@ -354,7 +354,7 @@
   phyReg |= cIRQSTS3_TMR1IRQ;         // aknowledge TMR1 IRQ
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -370,7 +370,7 @@
 {
   uint8_t phyCtrl3Reg, irqSts3Reg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
 //  phyCtrl3Reg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare
@@ -387,7 +387,7 @@
   phyCtrl3Reg |= cPHY_CTRL3_TMR4CMP_EN;   // enable TMR4 compare
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 }
 
 /*! *********************************************************************************
@@ -404,7 +404,7 @@
   bool_t wakeUpIrq = FALSE;
   uint8_t phyReg;
 
-  __disable_irq();
+  OSA_EnterCritical(kCriticalDisableInt);
 
   phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
   phyReg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare
@@ -423,7 +423,7 @@
 
   MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
 
-  __enable_irq();
+  OSA_ExitCritical(kCriticalDisableInt);
 
   return wakeUpIrq;
 }
@@ -485,10 +485,10 @@
 {
     phyTimeTimestamp_t time = 0;
 
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
     PhyTimeReadClock( (uint32_t*)&time );
     time |= (gPhyTimerOverflow << gPhyTimeShift_c);
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 
     return time;
 }
@@ -512,7 +512,7 @@
     }
 
     /* Search for a free slot (slot 0 is reserved for the Overflow calback) */
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
     for( tmr=1; tmr<gMaxPhyTimers_c; tmr++ )
     {
         if( mPhyTimers[tmr].callback == NULL )
@@ -521,7 +521,7 @@
             break;
         }
     }
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 
     if( tmr >= gMaxPhyTimers_c )
         return gInvalidTimerId_c;
@@ -551,12 +551,12 @@
         return gPhyTimeNotFound_c;
     }
 
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
     if( pNextEvent == &mPhyTimers[timerId] )
         pNextEvent = NULL;
 
     mPhyTimers[timerId].callback = NULL;
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 
     return gPhyTimeOk_c;
 }
@@ -574,7 +574,7 @@
     uint32_t i;
     phyTimeStatus_t status = gPhyTimeNotFound_c;
 
-    __disable_irq();
+    OSA_EnterCritical(kCriticalDisableInt);
     for( i=1; i<gMaxPhyTimers_c; i++ )
     {
         if( mPhyTimers[i].callback && (param == mPhyTimers[i].parameter) )
@@ -585,7 +585,7 @@
                 pNextEvent = NULL;
         }
     }
-    __enable_irq();
+    OSA_ExitCritical(kCriticalDisableInt);
 
     return status;
 }
@@ -601,14 +601,14 @@
 
     if( pNextEvent )
     {
-        __disable_irq();
+        OSA_EnterCritical(kCriticalDisableInt);
 
         param = pNextEvent->parameter;
         cb = pNextEvent->callback;
         pNextEvent->callback = NULL;
         pNextEvent = NULL;
 
-        __enable_irq();
+        OSA_ExitCritical(kCriticalDisableInt);
 
         cb(param);
     }
@@ -628,7 +628,7 @@
 
     while(1)
     {
-        __disable_irq();
+        OSA_EnterCritical(kCriticalDisableInt);
         
         pEv = PhyTime_GetNextEvent();
         currentTime = PhyTime_GetTimestamp();
@@ -645,7 +645,7 @@
             }
         }
 
-        __enable_irq();
+        OSA_ExitCritical(kCriticalDisableInt);
 
         if( !pEv )
             break;