NXP
The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.
Dependencies: fsl_phy_mcr20a fsl_smac mbed-rtos mbed
Fork of
mcr20_wireless_uart
by 
Freescale
By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.
- Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
- The code must be downloaded on the platforms via CMSIS-DAP (or other means).
- After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
- To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.
Documentation
SMAC Demo Applications User Guide
Revision 5:69f1634cd40b, committed 2015-03-05
- Comitter:
- FSL\B36402
- Date:
- Thu Mar 05 14:32:32 2015 -0600
- Parent:
- 3:a38ad504a18c
- Child:
- 6:01d070bc1c26
- Commit message:
- Adding new files for MCR20
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/MCR20Drv.c Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,802 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* \file MCR20Drv.c
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+/*****************************************************************************
+* INCLUDED HEADERS *
+*---------------------------------------------------------------------------*
+* Add to this section all the headers that this module needs to include. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+#include "MCR20Drv.h"
+#include "MCR20Reg.h"
+
+//#include "EmbeddedTypes.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include "low_level_RF.h"
+//#include "arm_hal_interrupt.h"
+//#include "arm_hal_phy.h"
+//#include "driverRFPhy.h"
+//#include "driverAtmelRFInterface.h"
+//#include "low_level_RF.h"
+
+//#include "SPI.h"
+//#include "fsl_gpio_driver.h"
+//#include "fsl_os_abstraction.h"
+
+
+/*****************************************************************************
+* PRIVATE VARIABLES *
+*---------------------------------------------------------------------------*
+* Add to this section all the variables and constants that have local *
+* (file) scope. *
+* Each of this declarations shall be preceded by the 'static' keyword. *
+* These variables / constants cannot be accessed outside this module. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+uint8_t gXcvrSpiInstance_c = 0;
+
+static uint32_t mPhyIrqDisableCnt = 1;
+
+void spi_master_init(uint32_t instance)
+{
+}
+
+void spi_master_configure_speed(uint32_t instance, uint32_t freq)
+{
+ spi.frequency(freq);
+}
+
+void gXcvrAssertCS_d(void) {
+ RF_CS_Set(0);
+}
+
+void gXcvrDeassertCS_d(void) {
+ RF_CS_Set(1);
+}
+
+#if 0
+/* GPIO configuration */
+const gpio_output_pin_user_config_t mXcvrSpiCsCfg = {
+ .pinName = kGpioXcvrSpiCsPin,
+ .config.outputLogic = 1,
+ .config.slewRate = kPortFastSlewRate,
+ #if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+ .config.isOpenDrainEnabled = false,
+ #endif
+ .config.driveStrength = kPortLowDriveStrength,
+};
+
+const gpio_input_pin_user_config_t mXcvrIrqPinCfg = {
+ .pinName = kGpioXcvrIrqPin,
+ .config.isPullEnable = false,
+ .config.pullSelect = kPortPullDown,
+ .config.isPassiveFilterEnabled = false,
+ .config.interrupt = kPortIntDisabled
+};
+#endif
+
+/*****************************************************************************
+* PUBLIC VARIABLES *
+*---------------------------------------------------------------------------*
+* Add to this section all the variables and constants that have global *
+* (project) scope. *
+* These variables / constants can be accessed outside this module. *
+* These variables / constants shall be preceded by the 'extern' keyword in *
+* the interface header. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+/*****************************************************************************
+* PRIVATE FUNCTIONS PROTOTYPES *
+*---------------------------------------------------------------------------*
+* Add to this section all the functions prototypes that have local (file) *
+* scope. *
+* These functions cannot be accessed outside this module. *
+* These declarations shall be preceded by the 'static' keyword. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+/*****************************************************************************
+* PRIVATE FUNCTIONS *
+*---------------------------------------------------------------------------*
+* Add to this section all the functions that have local (file) scope. *
+* These functions cannot be accessed outside this module. *
+* These definitions shall be preceded by the 'static' keyword. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+
+/*****************************************************************************
+* PUBLIC FUNCTIONS *
+*---------------------------------------------------------------------------*
+* Add to this section all the functions that have global (project) scope. *
+* These functions can be accessed outside this module. *
+* These functions shall have their declarations (prototypes) within the *
+* interface header file and shall be preceded by the 'extern' keyword. *
+*---------------------------------------------------------------------------*
+*****************************************************************************/
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_Init
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_Init
+(
+void
+)
+{
+#if 0
+ spi_master_init(gXcvrSpiInstance_c);
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ /* Override SPI CS pin function. Set pin as GPIO */
+ PORT_HAL_SetMuxMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrSpiCsPin)],
+ GPIO_EXTRACT_PIN(kGpioXcvrSpiCsPin),
+ kPortMuxAsGpio);
+ GPIO_DRV_OutputPinInit(&mXcvrSpiCsCfg);
+ gXcvrDeassertCS_d();
+#endif
+
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_DirectAccessSPIWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_DirectAccessSPIWrite
+(
+uint8_t address,
+uint8_t value
+)
+{
+ uint16_t txData;
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = (address & TransceiverSPI_DirectRegisterAddressMask);
+ txData |= value << 8;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, NULL, sizeof(txData));
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_DirectAccessSPIMultiByteWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_DirectAccessSPIMultiByteWrite
+(
+uint8_t startAddress,
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint8_t txData;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
+
+ spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_PB_SPIByteWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_PB_SPIByteWrite
+(
+uint8_t address,
+uint8_t value
+)
+{
+ uint32_t txData;
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_WriteSelect |
+ TransceiverSPI_PacketBuffAccessSelect |
+ TransceiverSPI_PacketBuffByteModeSelect;
+ txData |= (address) << 8;
+ txData |= (value) << 16;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_PB_SPIBurstWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_PB_SPIBurstWrite
+(
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint8_t txData;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_WriteSelect |
+ TransceiverSPI_PacketBuffAccessSelect |
+ TransceiverSPI_PacketBuffBurstModeSelect;
+
+ spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, 1);
+ spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_DirectAccessSPIRead
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+
+uint8_t MCR20Drv_DirectAccessSPIRead
+(
+uint8_t address
+)
+{
+ uint8_t txData;
+ uint8_t rxData;
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ gXcvrAssertCS_d();
+
+ txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
+ TransceiverSPI_ReadSelect;
+
+ spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData));
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+
+ return rxData;
+
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_DirectAccessSPIMultyByteRead
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
+(
+uint8_t startAddress,
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint8_t txData;
+ uint8_t phyIRQSTS1;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return 0;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ gXcvrAssertCS_d();
+
+ txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
+ TransceiverSPI_ReadSelect;
+
+ spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+
+ return phyIRQSTS1;
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_PB_SPIBurstRead
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_PB_SPIBurstRead
+(
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint8_t txData;
+ uint8_t phyIRQSTS1;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return 0;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_ReadSelect |
+ TransceiverSPI_PacketBuffAccessSelect |
+ TransceiverSPI_PacketBuffBurstModeSelect;
+
+ spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+
+ return phyIRQSTS1;
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IndirectAccessSPIWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIWrite
+(
+uint8_t address,
+uint8_t value
+)
+{
+ uint32_t txData;
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_IARIndexReg;
+ txData |= (address) << 8;
+ txData |= (value) << 16;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIMultiByteWrite
+(
+uint8_t startAddress,
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint16_t txData;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_IARIndexReg;
+ txData |= (startAddress) << 8;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, NULL, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IndirectAccessSPIRead
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_IndirectAccessSPIRead
+(
+uint8_t address
+)
+{
+ uint16_t txData;
+ uint8_t rxData;
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ gXcvrAssertCS_d();
+
+ txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
+ txData |= (address) << 8;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData));
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+
+ return rxData;
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IndirectAccessSPIMultiByteRead
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIMultiByteRead
+(
+uint8_t startAddress,
+uint8_t * byteArray,
+uint8_t numOfBytes
+)
+{
+ uint16_t txData;
+
+ if( (numOfBytes == 0) || (byteArray == NULL) )
+ {
+ return;
+ }
+
+ ProtectFromMCR20Interrupt();
+
+ spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
+
+ gXcvrAssertCS_d();
+
+ txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
+ txData |= (startAddress) << 8;
+
+ spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
+ spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
+
+ gXcvrDeassertCS_d();
+ UnprotectFromMCR20Interrupt();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IRQ_PortConfig
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_PortConfig
+(
+void
+)
+{
+#if 0
+ PORT_HAL_SetMuxMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
+ GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
+ kPortMuxAsGpio);
+ GPIO_DRV_InputPinInit(&mXcvrIrqPinCfg);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IsIrqPending
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+uint32_t MCR20Drv_IsIrqPending
+(
+void
+)
+{
+#if 0
+ if( GPIO_DRV_ReadPinInput(kGpioXcvrIrqPin) )
+ {
+ return FALSE;
+ }
+ return TRUE;
+#endif
+ return TRUE;
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IRQ_Disable
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Disable // TODO
+(
+void
+)
+{
+ arm_enter_critical();
+
+ if( mPhyIrqDisableCnt == 0 )
+ {
+// PORT_HAL_SetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
+// GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
+// kPortIntDisabled);
+ }
+
+ mPhyIrqDisableCnt++;
+
+ arm_exit_critical();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IRQ_Enable
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Enable // TODO
+(
+void
+)
+{
+ arm_enter_critical();
+
+ if( mPhyIrqDisableCnt )
+ {
+ mPhyIrqDisableCnt--;
+
+ if( mPhyIrqDisableCnt == 0 )
+ {
+// PORT_HAL_SetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
+// GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
+// kPortIntLogicZero);
+ }
+ }
+
+ arm_exit_critical();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IRQ_IsEnabled
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+uint32_t MCR20Drv_IRQ_IsEnabled
+(
+void
+)
+{
+#if 0
+ port_interrupt_config_t mode;
+
+ mode = PORT_HAL_GetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
+ GPIO_EXTRACT_PIN(kGpioXcvrIrqPin));
+ return (mode != kPortIntDisabled);
+#endif
+ return 0;
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_IRQ_Clear
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Clear
+(
+void
+)
+{
+ // GPIO_DRV_ClearPinIntFlag(kGpioXcvrIrqPin);
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_RST_Assert
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_RST_B_Assert
+(
+void
+)
+{
+ //GPIO_DRV_ClearPinOutput(kGpioXcvrResetPin);
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_RST_Deassert
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_RST_B_Deassert
+(
+void
+)
+{
+ //GPIO_DRV_SetPinOutput(kGpioXcvrResetPin);
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_SoftRST_Assert
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_SoftRST_Assert
+(
+void
+)
+{
+ MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_SoftRST_Deassert
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_SoftRST_Deassert
+(
+void
+)
+{
+ MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_Soft_RESET
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_Soft_RESET
+(
+void
+)
+{
+ //assert SOG_RST
+ MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
+
+ //deassert SOG_RST
+ MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_RESET
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_RESET
+(
+void
+)
+{
+ volatile uint32_t delay = 1000;
+ //assert RST_B
+ MCR20Drv_RST_B_Assert();
+
+ // TODO
+ while(delay--);
+
+ //deassert RST_B
+ MCR20Drv_RST_B_Deassert();
+}
+
+/*---------------------------------------------------------------------------
+* Name: MCR20Drv_Set_CLK_OUT_Freq
+* Description: -
+* Parameters: -
+* Return: -
+*---------------------------------------------------------------------------*/
+void MCR20Drv_Set_CLK_OUT_Freq
+(
+uint8_t freqDiv
+)
+{
+ uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
+
+ if(freqDiv == gCLK_OUT_FREQ_DISABLE)
+ {
+ clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
+ }
+
+ MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/MCR20Drv.h Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,413 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* \file MCR20Drv.h
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef __MCR20_DRV_H__
+#define __MCR20_DRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+ * INCLUDED HEADERS *
+ *---------------------------------------------------------------------------*
+ * Add to this section all the headers that this module needs to include. *
+ * Note that it is not a good practice to include header files into header *
+ * files, so use this section only if there is no other better solution. *
+ *---------------------------------------------------------------------------*
+ *****************************************************************************/
+
+//#include "EmbeddedTypes.h"
+#include <stdint.h>
+
+/*****************************************************************************
+ * PRIVATE MACROS *
+ *---------------------------------------------------------------------------*
+ * Add to this section all the access macros, registers mappings, bit access *
+ * macros, masks, flags etc ...
+ *---------------------------------------------------------------------------*
+ *****************************************************************************/
+#ifndef gMCR20_ClkOutFreq_d
+#define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_4_MHz
+#endif
+
+/*****************************************************************************
+ * PUBLIC FUNCTIONS *
+ *---------------------------------------------------------------------------*
+ * Add to this section all the global functions prototype preceded (as a *
+ * good practice) by the keyword 'extern' *
+ *---------------------------------------------------------------------------*
+ *****************************************************************************/
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_Init
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+extern void MCR20Drv_Init
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_SPI_DMA_Init
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_SPI_DMA_Init
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_Start_PB_DMA_SPI_Write
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_Start_PB_DMA_SPI_Write
+(
+ uint8_t * srcAddress,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_Start_PB_DMA_SPI_Read
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_Start_PB_DMA_SPI_Read
+(
+ uint8_t * dstAddress,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_DirectAccessSPIWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_DirectAccessSPIWrite
+(
+ uint8_t address,
+ uint8_t value
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_DirectAccessSPIMultiByteWrite
+(
+ uint8_t startAddress,
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_PB_SPIBurstWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_PB_SPIBurstWrite
+(
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_DirectAccessSPIRead
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_DirectAccessSPIRead
+(
+ uint8_t address
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_DirectAccessSPIMultyByteRead
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+
+uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
+(
+ uint8_t startAddress,
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_PB_SPIByteWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_PB_SPIByteWrite
+(
+ uint8_t address,
+ uint8_t value
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_PB_SPIBurstRead
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_PB_SPIBurstRead
+(
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IndirectAccessSPIWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIWrite
+(
+ uint8_t address,
+ uint8_t value
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIMultiByteWrite
+(
+ uint8_t startAddress,
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IndirectAccessSPIRead
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+uint8_t MCR20Drv_IndirectAccessSPIRead
+(
+ uint8_t address
+);
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IndirectAccessSPIMultiByteRead
+(
+ uint8_t startAddress,
+ uint8_t * byteArray,
+ uint8_t numOfBytes
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IRQ_PortConfig
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_PortConfig
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IsIrqPending
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+uint32_t MCR20Drv_IsIrqPending
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IRQ_Disable
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Disable
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IRQ_Enable
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Enable
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IRQ_IsEnabled
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+uint32_t MCR20Drv_IRQ_IsEnabled
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_IRQ_Clear
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_IRQ_Clear
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_RST_PortConfig
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_RST_B_PortConfig
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_RST_Assert
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_RST_B_Assert
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_RST_Deassert
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_RST_B_Deassert
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_SoftRST_Assert
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_SoftRST_Assert
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_SoftRST_Deassert
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_SoftRST_Deassert
+(
+ void
+);
+
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_RESET
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_RESET
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_Soft_RESET
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_Soft_RESET
+(
+ void
+);
+
+/*---------------------------------------------------------------------------
+ * Name: MCR20Drv_Set_CLK_OUT_Freq
+ * Description: -
+ * Parameters: -
+ * Return: -
+ *---------------------------------------------------------------------------*/
+void MCR20Drv_Set_CLK_OUT_Freq
+(
+ uint8_t freqDiv
+);
+
+#define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable()
+#define UnprotectFromMCR20Interrupt() MCR20Drv_IRQ_Enable()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCR20_DRV_H__ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/MCR20Overwrites.h Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,309 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* \file MCR20Overwrites.h
+* Description: Overwrites header file for MCR20 Register values
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef OVERWRITES_H_
+#define OVERWRITES_H_
+
+typedef struct overwrites_tag {
+ char address;
+ char data;
+}overwrites_t;
+
+
+/*****************************************************************************************************************/
+// This file is created exclusively for use with the transceiver 2.0 silicon
+// and is provided for the world to use. It contains a list of all
+// known overwrite values. Overwrite values are non-default register
+// values that configure the transceiver device to a more optimally performing
+// posture. It is expected that low level software (i.e. PHY) will
+// consume this file as a #include, and transfer the contents to the
+// the indicated addresses in the transceiver's memory space. This file has
+// at least one required entry, that being its own version current version
+// number, to be stored at transceiver's location 0x3B the
+// OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
+// the transceiver address space to assist in future debug efforts. The
+// analyst may read this location (once device has been booted with
+// mysterious software) and have a good indication of what register
+// overwrites were performed (with all versions of the overwrites.h file
+// being archived forever at the Compass location shown above.
+//
+// The transceiver has an indirect register (IAR) space. Write access to this space
+// requires 3 or more writes:
+// 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
+// 2nd) IAR Register #0x00 - 0xFF.
+// 3rd) The data to write
+// nth) Burst mode additional data if required.
+//
+// Write access to direct space requires only a single address, data pair.
+
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
+{0x23, 0x17} //PA_PWR new default Power Step is "23"
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
+{0x52, 0x55}, //AGC_THR1 RSSI tune up
+{0x53, 0x2D}, //AGC_THR2 RSSI tune up
+{0x66, 0x5F}, //ATT_RSSI1 tune up
+{0x67, 0x8F}, //ATT_RSSI2 tune up
+{0x68, 0x61}, //RSSI_OFFSET
+{0x78, 0x03}, //CHF_PMAGAIN
+{0x22, 0x50}, //CCA1_THRESH
+{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
+{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
+};
+
+
+/* begin of deprecated versions
+
+==VERSION 1==
+(version 1 is empty)
+
+==VERSION 2==
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+};
+
+==VERSION 3==
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
+{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+};
+
+==VERSION 4==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
+{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+};
+
+==VERSION 5==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+};
+
+==VERSION 6==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x06} //version 06: disable PA calibration
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
+};
+
+==VERSION 7==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x07} //version 07: updated registers for ED/RSSI
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
+{0x52, 0x73}, //AGC_THR1 RSSI tune up
+{0x53, 0x2D}, //AGC_THR2 RSSI tune up
+{0x66, 0x5F}, //ATT_RSSI1 tune up
+{0x67, 0x8F}, //ATT_RSSI2 tune up
+{0x68, 0x60}, //RSSI_OFFSET
+{0x69, 0x65} //RSSI_SLOPE
+};
+
+
+==VERSION 8==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x08} //version 08: updated registers for ED/RSSI
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
+{0x52, 0x73}, //AGC_THR1 RSSI tune up
+{0x53, 0x2D}, //AGC_THR2 RSSI tune up
+{0x66, 0x5F}, //ATT_RSSI1 tune up
+{0x67, 0x8F}, //ATT_RSSI2 tune up
+{0x69, 0x65} //RSSI_SLOPE
+{0x68, 0x61}, //RSSI_OFFSET
+{0x78, 0x03} //CHF_PMAGAIN
+};
+
+
+==VERSION 9==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
+{0x23, 0x17} //PA_PWR new default value
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
+{0x52, 0x55}, //AGC_THR1 RSSI tune up
+{0x53, 0x2D}, //AGC_THR2 RSSI tune up
+{0x66, 0x5F}, //ATT_RSSI1 tune up
+{0x67, 0x8F}, //ATT_RSSI2 tune up
+{0x68, 0x61}, //RSSI_OFFSET
+{0x78, 0x03} //CHF_PMAGAIN
+};
+
+==VERSION A==
+overwrites_t const overwrites_direct[] ={
+{0x3B, 0x0A} //version 0A: updated registers for CCA
+{0x23, 0x17} //PA_PWR new default Power Step is "23"
+};
+
+overwrites_t const overwrites_indirect[] ={
+{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
+{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
+{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
+{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
+{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
+{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
+{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
+{0x52, 0x55}, //AGC_THR1 RSSI tune up
+{0x53, 0x2D}, //AGC_THR2 RSSI tune up
+{0x66, 0x5F}, //ATT_RSSI1 tune up
+{0x67, 0x8F}, //ATT_RSSI2 tune up
+{0x68, 0x61}, //RSSI_OFFSET
+{0x78, 0x03} //CHF_PMAGAIN
+{0x22, 0x50} //CCA1_THRESH
+};
+
+end of deprecated versions */
+
+
+#endif //OVERWRITES_H_
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/MCR20Reg.h Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,730 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* \file MCR20reg.h
+* MCR20 Registers
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef __MCR20_REG_H__
+#define __MCR20_REG_H__
+/*****************************************************************************
+ * INCLUDED HEADERS *
+ *---------------------------------------------------------------------------*
+ * Add to this section all the headers that this module needs to include. *
+ * Note that it is not a good practice to include header files into header *
+ * files, so use this section only if there is no other better solution. *
+ *---------------------------------------------------------------------------*
+ *****************************************************************************/
+
+/****************************************************************************/
+/* Transceiver SPI Registers */
+/****************************************************************************/
+
+#define TransceiverSPI_IARIndexReg (0x3E)
+
+#define TransceiverSPI_ReadSelect (1<<7)
+#define TransceiverSPI_WriteSelect (0<<7)
+#define TransceiverSPI_RegisterAccessSelect (0<<6)
+#define TransceiverSPI_PacketBuffAccessSelect (1<<6)
+#define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
+#define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
+
+#define TransceiverSPI_DirectRegisterAddressMask (0x3F)
+
+#define IRQSTS1 0x00
+#define IRQSTS2 0x01
+#define IRQSTS3 0x02
+#define PHY_CTRL1 0x03
+#define PHY_CTRL2 0x04
+#define PHY_CTRL3 0x05
+#define RX_FRM_LEN 0x06
+#define PHY_CTRL4 0x07
+#define SRC_CTRL 0x08
+#define SRC_ADDRS_SUM_LSB 0x09
+#define SRC_ADDRS_SUM_MSB 0x0A
+#define CCA1_ED_FNL 0x0B
+#define EVENT_TMR_LSB 0x0C
+#define EVENT_TMR_MSB 0x0D
+#define EVENT_TMR_USB 0x0E
+#define TIMESTAMP_LSB 0x0F
+#define TIMESTAMP_MSB 0x10
+#define TIMESTAMP_USB 0x11
+#define T3CMP_LSB 0x12
+#define T3CMP_MSB 0x13
+#define T3CMP_USB 0x14
+#define T2PRIMECMP_LSB 0x15
+#define T2PRIMECMP_MSB 0x16
+#define T1CMP_LSB 0x17
+#define T1CMP_MSB 0x18
+#define T1CMP_USB 0x19
+#define T2CMP_LSB 0x1A
+#define T2CMP_MSB 0x1B
+#define T2CMP_USB 0x1C
+#define T4CMP_LSB 0x1D
+#define T4CMP_MSB 0x1E
+#define T4CMP_USB 0x1F
+#define PLL_INT0 0x20
+#define PLL_FRAC0_LSB 0x21
+#define PLL_FRAC0_MSB 0x22
+#define PA_PWR 0x23
+#define SEQ_STATE 0x24
+#define LQI_VALUE 0x25
+#define RSSI_CCA_CONT 0x26
+//-------------- 0x27
+#define ASM_CTRL1 0x28
+#define ASM_CTRL2 0x29
+#define ASM_DATA_0 0x2A
+#define ASM_DATA_1 0x2B
+#define ASM_DATA_2 0x2C
+#define ASM_DATA_3 0x2D
+#define ASM_DATA_4 0x2E
+#define ASM_DATA_5 0x2F
+#define ASM_DATA_6 0x30
+#define ASM_DATA_7 0x31
+#define ASM_DATA_8 0x32
+#define ASM_DATA_9 0x33
+#define ASM_DATA_A 0x34
+#define ASM_DATA_B 0x35
+#define ASM_DATA_C 0x36
+#define ASM_DATA_D 0x37
+#define ASM_DATA_E 0x38
+#define ASM_DATA_F 0x39
+//------------------- 0x3A
+#define OVERWRITE_VER 0x3B
+#define CLK_OUT_CTRL 0x3C
+#define PWR_MODES 0x3D
+#define IAR_INDEX 0x3E
+#define IAR_DATA 0x3F
+
+
+#define PART_ID 0x00
+#define XTAL_TRIM 0x01
+#define PMC_LP_TRIM 0x02
+#define MACPANID0_LSB 0x03
+#define MACPANID0_MSB 0x04
+#define MACSHORTADDRS0_LSB 0x05
+#define MACSHORTADDRS0_MSB 0x06
+#define MACLONGADDRS0_0 0x07
+#define MACLONGADDRS0_8 0x08
+#define MACLONGADDRS0_16 0x09
+#define MACLONGADDRS0_24 0x0A
+#define MACLONGADDRS0_32 0x0B
+#define MACLONGADDRS0_40 0x0C
+#define MACLONGADDRS0_48 0x0D
+#define MACLONGADDRS0_56 0x0E
+#define RX_FRAME_FILTER 0x0F
+#define PLL_INT1 0x10
+#define PLL_FRAC1_LSB 0x11
+#define PLL_FRAC1_MSB 0x12
+#define MACPANID1_LSB 0x13
+#define MACPANID1_MSB 0x14
+#define MACSHORTADDRS1_LSB 0x15
+#define MACSHORTADDRS1_MSB 0x16
+#define MACLONGADDRS1_0 0x17
+#define MACLONGADDRS1_8 0x18
+#define MACLONGADDRS1_16 0x19
+#define MACLONGADDRS1_24 0x1A
+#define MACLONGADDRS1_32 0x1B
+#define MACLONGADDRS1_40 0x1C
+#define MACLONGADDRS1_48 0x1D
+#define MACLONGADDRS1_56 0x1E
+#define DUAL_PAN_CTRL 0x1F
+#define DUAL_PAN_DWELL 0x20
+#define DUAL_PAN_STS 0x21
+#define CCA1_THRESH 0x22
+#define CCA1_ED_OFFSET_COMP 0x23
+#define LQI_OFFSET_COMP 0x24
+#define CCA_CTRL 0x25
+#define CCA2_CORR_PEAKS 0x26
+#define CCA2_CORR_THRESH 0x27
+#define TMR_PRESCALE 0x28
+//---------------- 0x29
+#define GPIO_DATA 0x2A
+#define GPIO_DIR 0x2B
+#define GPIO_PUL_EN 0x2C
+#define GPIO_PUL_SEL 0x2D
+#define GPIO_DS 0x2E
+//-------------- 0x2F
+#define ANT_PAD_CTRL 0x30
+#define MISC_PAD_CTRL 0x31
+#define BSM_CTRL 0x32
+//--------------- 0x33
+#define _RNG 0x34
+#define RX_BYTE_COUNT 0x35
+#define RX_WTR_MARK 0x36
+#define SOFT_RESET 0x37
+#define TXDELAY 0x38
+#define ACKDELAY 0x39
+#define SEQ_MGR_CTRL 0x3A
+#define SEQ_MGR_STS 0x3B
+#define SEQ_T_STS 0x3C
+#define ABORT_STS 0x3D
+#define CCCA_BUSY_CNT 0x3E
+#define SRC_ADDR_CHECKSUM1 0x3F
+#define SRC_ADDR_CHECKSUM2 0x40
+#define SRC_TBL_VALID1 0x41
+#define SRC_TBL_VALID2 0x42
+#define FILTERFAIL_CODE1 0x43
+#define FILTERFAIL_CODE2 0x44
+#define SLOT_PRELOAD 0x45
+//---------------- 0x46
+#define CORR_VT 0x47
+#define SYNC_CTRL 0x48
+#define PN_LSB_0 0x49
+#define PN_LSB_1 0x4A
+#define PN_MSB_0 0x4B
+#define PN_MSB_1 0x4C
+#define CORR_NVAL 0x4D
+#define TX_MODE_CTRL 0x4E
+#define SNF_THR 0x4F
+#define FAD_THR 0x50
+#define ANT_AGC_CTRL 0x51
+#define AGC_THR1 0x52
+#define AGC_THR2 0x53
+#define AGC_HYS 0x54
+#define AFC 0x55
+//--------------- 0x56
+//--------------- 0x57
+#define PHY_STS 0x58
+#define RX_MAX_CORR 0x59
+#define RX_MAX_PREAMBLE 0x5A
+#define RSSI 0x5B
+//--------------- 0x5C
+//--------------- 0x5D
+#define PLL_DIG_CTRL 0x5E
+#define VCO_CAL 0x5F
+#define VCO_BEST_DIFF 0x60
+#define VCO_BIAS 0x61
+#define KMOD_CTRL 0x62
+#define KMOD_CAL 0x63
+#define PA_CAL 0x64
+#define PA_PWRCAL 0x65
+#define ATT_RSSI1 0x66
+#define ATT_RSSI2 0x67
+#define RSSI_OFFSET 0x68
+#define RSSI_SLOPE 0x69
+#define RSSI_CAL1 0x6A
+#define RSSI_CAL2 0x6B
+//--------------- 0x6C
+//--------------- 0x6D
+#define XTAL_CTRL 0x6E
+#define XTAL_COMP_MIN 0x6F
+#define XTAL_COMP_MAX 0x70
+#define XTAL_GM 0x71
+//--------------- 0x72
+//--------------- 0x73
+#define LNA_TUNE 0x74
+#define LNA_AGCGAIN 0x75
+//--------------- 0x76
+//--------------- 0x77
+#define CHF_PMA_GAIN 0x78
+#define CHF_IBUF 0x79
+#define CHF_QBUF 0x7A
+#define CHF_IRIN 0x7B
+#define CHF_QRIN 0x7C
+#define CHF_IL 0x7D
+#define CHF_QL 0x7E
+#define CHF_CC1 0x7F
+#define CHF_CCL 0x80
+#define CHF_CC2 0x81
+#define CHF_IROUT 0x82
+#define CHF_QROUT 0x83
+//--------------- 0x84
+//--------------- 0x85
+#define RSSI_CTRL 0x86
+//--------------- 0x87
+//--------------- 0x88
+#define PA_BIAS 0x89
+#define PA_TUNING 0x8A
+//--------------- 0x8B
+//--------------- 0x8C
+#define PMC_HP_TRIM 0x8D
+#define VREGA_TRIM 0x8E
+//--------------- 0x8F
+//--------------- 0x90
+#define VCO_CTRL1 0x91
+#define VCO_CTRL2 0x92
+//--------------- 0x93
+//--------------- 0x94
+#define ANA_SPARE_OUT1 0x95
+#define ANA_SPARE_OUT2 0x96
+#define ANA_SPARE_IN 0x97
+#define MISCELLANEOUS 0x98
+//--------------- 0x99
+#define SEQ_MGR_OVRD0 0x9A
+#define SEQ_MGR_OVRD1 0x9B
+#define SEQ_MGR_OVRD2 0x9C
+#define SEQ_MGR_OVRD3 0x9D
+#define SEQ_MGR_OVRD4 0x9E
+#define SEQ_MGR_OVRD5 0x9F
+#define SEQ_MGR_OVRD6 0xA0
+#define SEQ_MGR_OVRD7 0xA1
+//--------------- 0xA2
+#define TESTMODE_CTRL 0xA3
+#define DTM_CTRL1 0xA4
+#define DTM_CTRL2 0xA5
+#define ATM_CTRL1 0xA6
+#define ATM_CTRL2 0xA7
+#define ATM_CTRL3 0xA8
+//--------------- 0xA9
+#define LIM_FE_TEST_CTRL 0xAA
+#define CHF_TEST_CTRL 0xAB
+#define VCO_TEST_CTRL 0xAC
+#define PLL_TEST_CTRL 0xAD
+#define PA_TEST_CTRL 0xAE
+#define PMC_TEST_CTRL 0xAF
+#define SCAN_DTM_PROTECT_1 0xFE
+#define SCAN_DTM_PROTECT_0 0xFF
+
+// IRQSTS1 bits
+#define cIRQSTS1_RX_FRM_PEND (1<<7)
+#define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
+#define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
+#define cIRQSTS1_RXWTRMRKIRQ (1<<4)
+#define cIRQSTS1_CCAIRQ (1<<3)
+#define cIRQSTS1_RXIRQ (1<<2)
+#define cIRQSTS1_TXIRQ (1<<1)
+#define cIRQSTS1_SEQIRQ (1<<0)
+
+typedef union regIRQSTS1_tag{
+ uint8_t byte;
+ struct{
+ uint8_t SEQIRQ:1;
+ uint8_t TXIRQ:1;
+ uint8_t RXIRQ:1;
+ uint8_t CCAIRQ:1;
+ uint8_t RXWTRMRKIRQ:1;
+ uint8_t FILTERFAIL_IRQ:1;
+ uint8_t PLL_UNLOCK_IRQ:1;
+ uint8_t RX_FRM_PEND:1;
+ }bit;
+} regIRQSTS1_t;
+
+// IRQSTS2 bits
+#define cIRQSTS2_CRCVALID (1<<7)
+#define cIRQSTS2_CCA (1<<6)
+#define cIRQSTS2_SRCADDR (1<<5)
+#define cIRQSTS2_PI (1<<4)
+#define cIRQSTS2_TMRSTATUS (1<<3)
+#define cIRQSTS2_ASM_IRQ (1<<2)
+#define cIRQSTS2_PB_ERR_IRQ (1<<1)
+#define cIRQSTS2_WAKE_IRQ (1<<0)
+
+typedef union regIRQSTS2_tag{
+ uint8_t byte;
+ struct{
+ uint8_t WAKE_IRQ:1;
+ uint8_t PB_ERR_IRQ:1;
+ uint8_t ASM_IRQ:1;
+ uint8_t TMRSTATUS:1;
+ uint8_t PI:1;
+ uint8_t SRCADDR:1;
+ uint8_t CCA:1;
+ uint8_t CRCVALID:1;
+ }bit;
+} regIRQSTS2_t;
+
+// IRQSTS3 bits
+#define cIRQSTS3_TMR4MSK (1<<7)
+#define cIRQSTS3_TMR3MSK (1<<6)
+#define cIRQSTS3_TMR2MSK (1<<5)
+#define cIRQSTS3_TMR1MSK (1<<4)
+#define cIRQSTS3_TMR4IRQ (1<<3)
+#define cIRQSTS3_TMR3IRQ (1<<2)
+#define cIRQSTS3_TMR2IRQ (1<<1)
+#define cIRQSTS3_TMR1IRQ (1<<0)
+
+typedef union regIRQSTS3_tag{
+ uint8_t byte;
+ struct{
+ uint8_t TMR1IRQ:1;
+ uint8_t TMR2IRQ:1;
+ uint8_t TMR3IRQ:1;
+ uint8_t TMR4IRQ:1;
+ uint8_t TMR1MSK:1;
+ uint8_t TMR2MSK:1;
+ uint8_t TMR3MSK:1;
+ uint8_t TMR4MSK:1;
+ }bit;
+} regIRQSTS3_t;
+
+// PHY_CTRL1 bits
+#define cPHY_CTRL1_TMRTRIGEN (1<<7)
+#define cPHY_CTRL1_SLOTTED (1<<6)
+#define cPHY_CTRL1_CCABFRTX (1<<5)
+#define cPHY_CTRL1_RXACKRQD (1<<4)
+#define cPHY_CTRL1_AUTOACK (1<<3)
+#define cPHY_CTRL1_XCVSEQ (7<<0)
+
+typedef union regPHY_CTRL1_tag{
+ uint8_t byte;
+ struct{
+ uint8_t XCVSEQ:3;
+ uint8_t AUTOACK:1;
+ uint8_t RXACKRQD:1;
+ uint8_t CCABFRTX:1;
+ uint8_t SLOTTED:1;
+ uint8_t TMRTRIGEN:1;
+ }bit;
+} regPHY_CTRL1_t;
+
+// PHY_CTRL2 bits
+#define cPHY_CTRL2_CRC_MSK (1<<7)
+#define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
+#define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
+#define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
+#define cPHY_CTRL2_CCAMSK (1<<3)
+#define cPHY_CTRL2_RXMSK (1<<2)
+#define cPHY_CTRL2_TXMSK (1<<1)
+#define cPHY_CTRL2_SEQMSK (1<<0)
+
+typedef union regPHY_CTRL2_tag{
+ uint8_t byte;
+ struct{
+ uint8_t SEQMSK:1;
+ uint8_t TXMSK:1;
+ uint8_t RXMSK:1;
+ uint8_t CCAMSK:1;
+ uint8_t RX_WMRK_MSK:1;
+ uint8_t FILTERFAIL_MSK:1;
+ uint8_t PLL_UNLOCK_MSK:1;
+ uint8_t CRC_MSK:1;
+ }bit;
+} regPHY_CTRL2_t;
+
+// PHY_CTRL3 bits
+#define cPHY_CTRL3_TMR4CMP_EN (1<<7)
+#define cPHY_CTRL3_TMR3CMP_EN (1<<6)
+#define cPHY_CTRL3_TMR2CMP_EN (1<<5)
+#define cPHY_CTRL3_TMR1CMP_EN (1<<4)
+#define cPHY_CTRL3_ASM_MSK (1<<2)
+#define cPHY_CTRL3_PB_ERR_MSK (1<<1)
+#define cPHY_CTRL3_WAKE_MSK (1<<0)
+
+typedef union regPHY_CTRL3_tag{
+ uint8_t byte;
+ struct{
+ uint8_t WAKE_MSK:1;
+ uint8_t PB_ERR_MSK:1;
+ uint8_t ASM_MSK:1;
+ uint8_t RESERVED:1;
+ uint8_t TMR1CMP_EN:1;
+ uint8_t TMR2CMP_EN:1;
+ uint8_t TMR3CMP_EN:1;
+ uint8_t TMR4CMP_EN:1;
+ }bit;
+} regPHY_CTRL3_t;
+
+// RX_FRM_LEN bits
+#define cRX_FRAME_LENGTH (0x7F)
+
+// PHY_CTRL4 bits
+#define cPHY_CTRL4_TRCV_MSK (1<<7)
+#define cPHY_CTRL4_TC3TMOUT (1<<6)
+#define cPHY_CTRL4_PANCORDNTR0 (1<<5)
+#define cPHY_CTRL4_CCATYPE (3<<0)
+#define cPHY_CTRL4_CCATYPE_Shift_c (3)
+#define cPHY_CTRL4_TMRLOAD (1<<2)
+#define cPHY_CTRL4_PROMISCUOUS (1<<1)
+#define cPHY_CTRL4_TC2PRIME_EN (1<<0)
+
+typedef union regPHY_CTRL4_tag{
+ uint8_t byte;
+ struct{
+ uint8_t TC2PRIME_EN:1;
+ uint8_t PROMISCUOUS:1;
+ uint8_t TMRLOAD:1;
+ uint8_t CCATYPE:2;
+ uint8_t PANCORDNTR0:1;
+ uint8_t TC3TMOUT:1;
+ uint8_t TRCV_MSK:1;
+ }bit;
+} regPHY_CTRL4_t;
+
+// SRC_CTRL bits
+#define cSRC_CTRL_INDEX (0x0F)
+#define cSRC_CTRL_INDEX_Shift_c (4)
+#define cSRC_CTRL_ACK_FRM_PND (1<<3)
+#define cSRC_CTRL_SRCADDR_EN (1<<2)
+#define cSRC_CTRL_INDEX_EN (1<<1)
+#define cSRC_CTRL_INDEX_DISABLE (1<<0)
+
+typedef union regSRC_CTRL_tag{
+ uint8_t byte;
+ struct{
+ uint8_t INDEX_DISABLE:1;
+ uint8_t INDEX_EN:1;
+ uint8_t SRCADDR_EN:1;
+ uint8_t ACK_FRM_PND:1;
+ uint8_t INDEX:4;
+ }bit;
+} regSRC_CTRL_t;
+
+// ASM_CTRL1 bits
+#define cASM_CTRL1_CLEAR (1<<7)
+#define cASM_CTRL1_START (1<<6)
+#define cASM_CTRL1_SELFTST (1<<5)
+#define cASM_CTRL1_CTR (1<<4)
+#define cASM_CTRL1_CBC (1<<3)
+#define cASM_CTRL1_AES (1<<2)
+#define cASM_CTRL1_LOAD_MAC (1<<1)
+
+// ASM_CTRL2 bits
+#define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
+#define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
+#define cASM_CTRL2_TSTPAS (1<<1)
+
+// CLK_OUT_CTRL bits
+#define cCLK_OUT_CTRL_EXTEND (1<<7)
+#define cCLK_OUT_CTRL_HIZ (1<<6)
+#define cCLK_OUT_CTRL_SR (1<<5)
+#define cCLK_OUT_CTRL_DS (1<<4)
+#define cCLK_OUT_CTRL_EN (1<<3)
+#define cCLK_OUT_CTRL_DIV (7)
+
+// PWR_MODES bits
+#define cPWR_MODES_XTAL_READY (1<<5)
+#define cPWR_MODES_XTALEN (1<<4)
+#define cPWR_MODES_ASM_CLK_EN (1<<3)
+#define cPWR_MODES_AUTODOZE (1<<1)
+#define cPWR_MODES_PMC_MODE (1<<0)
+
+// RX_FRAME_FILTER bits
+#define cRX_FRAME_FLT_FRM_VER (0xC0)
+#define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
+#define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
+#define cRX_FRAME_FLT_NS_FT (1<<4)
+#define cRX_FRAME_FLT_CMD_FT (1<<3)
+#define cRX_FRAME_FLT_ACK_FT (1<<2)
+#define cRX_FRAME_FLT_DATA_FT (1<<1)
+#define cRX_FRAME_FLT_BEACON_FT (1<<0)
+
+typedef union regRX_FRAME_FILTER_tag{
+ uint8_t byte;
+ struct{
+ uint8_t FRAME_FLT_BEACON_FT:1;
+ uint8_t FRAME_FLT_DATA_FT:1;
+ uint8_t FRAME_FLT_ACK_FT:1;
+ uint8_t FRAME_FLT_CMD_FT:1;
+ uint8_t FRAME_FLT_NS_FT:1;
+ uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
+ uint8_t FRAME_FLT_FRM_VER:2;
+ }bit;
+} regRX_FRAME_FILTER_t;
+
+// DUAL_PAN_CTRL bits
+#define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
+#define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
+#define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
+#define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
+#define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
+#define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
+
+// DUAL_PAN_STS bits
+#define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
+#define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
+#define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
+
+// CCA_CTRL bits
+#define cCCA_CTRL_AGC_FRZ_EN (1<<6)
+#define cCCA_CTRL_CONT_RSSI_EN (1<<5)
+#define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
+#define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
+#define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
+#define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
+#define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
+
+// GPIO_DATA bits
+#define cGPIO_DATA_7 (1<<7)
+#define cGPIO_DATA_6 (1<<6)
+#define cGPIO_DATA_5 (1<<5)
+#define cGPIO_DATA_4 (1<<4)
+#define cGPIO_DATA_3 (1<<3)
+#define cGPIO_DATA_2 (1<<2)
+#define cGPIO_DATA_1 (1<<1)
+#define cGPIO_DATA_0 (1<<0)
+
+// GPIO_DIR bits
+#define cGPIO_DIR_7 (1<<7)
+#define cGPIO_DIR_6 (1<<6)
+#define cGPIO_DIR_5 (1<<5)
+#define cGPIO_DIR_4 (1<<4)
+#define cGPIO_DIR_3 (1<<3)
+#define cGPIO_DIR_2 (1<<2)
+#define cGPIO_DIR_1 (1<<1)
+#define cGPIO_DIR_0 (1<<0)
+
+// GPIO_PUL_EN bits
+#define cGPIO_PUL_EN_7 (1<<7)
+#define cGPIO_PUL_EN_6 (1<<6)
+#define cGPIO_PUL_EN_5 (1<<5)
+#define cGPIO_PUL_EN_4 (1<<4)
+#define cGPIO_PUL_EN_3 (1<<3)
+#define cGPIO_PUL_EN_2 (1<<2)
+#define cGPIO_PUL_EN_1 (1<<1)
+#define cGPIO_PUL_EN_0 (1<<0)
+
+// GPIO_PUL_SEL bits
+#define cGPIO_PUL_SEL_7 (1<<7)
+#define cGPIO_PUL_SEL_6 (1<<6)
+#define cGPIO_PUL_SEL_5 (1<<5)
+#define cGPIO_PUL_SEL_4 (1<<4)
+#define cGPIO_PUL_SEL_3 (1<<3)
+#define cGPIO_PUL_SEL_2 (1<<2)
+#define cGPIO_PUL_SEL_1 (1<<1)
+#define cGPIO_PUL_SEL_0 (1<<0)
+
+// GPIO_DS bits
+#define cGPIO_DS_7 (1<<7)
+#define cGPIO_DS_6 (1<<6)
+#define cGPIO_DS_5 (1<<5)
+#define cGPIO_DS_4 (1<<4)
+#define cGPIO_DS_3 (1<<3)
+#define cGPIO_DS_2 (1<<2)
+#define cGPIO_DS_1 (1<<1)
+#define cGPIO_DS_0 (1<<0)
+
+// SPI_CTRL bits
+//#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
+//#define cSPI_CTRL_PB_PROTECT (1<<0)
+
+// ANT_PAD_CTRL bits
+#define cANT_PAD_CTRL_ANTX_POL (0x0F)
+#define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
+#define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
+#define cANT_PAD_CTRL_ANTX_HZ (1<<2)
+#define cANT_PAD_CTRL_ANTX_EN (3)
+
+// MISC_PAD_CTRL bits
+#define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
+#define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
+#define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
+#define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
+
+// ANT_AGC_CTRL bits
+#define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
+#define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
+#define cANT_AGC_CTRL_ANTX_Shift_c (1)
+#define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
+
+// BSM_CTRL bits
+#define cBSM_CTRL_BSM_EN (1<<0)
+
+// SOFT_RESET bits
+#define cSOFT_RESET_SOG_RST (1<<7)
+#define cSOFT_RESET_REGS_RST (1<<4)
+#define cSOFT_RESET_PLL_RST (1<<3)
+#define cSOFT_RESET_TX_RST (1<<2)
+#define cSOFT_RESET_RX_RST (1<<1)
+#define cSOFT_RESET_SEQ_MGR_RST (1<<0)
+
+// SEQ_MGR_CTRL bits
+#define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
+#define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
+#define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
+#define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
+#define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
+#define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
+#define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
+#define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
+
+// SEQ_MGR_STS bits
+#define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
+#define cSEQ_MGR_STS_RX_MODE (1<<6)
+#define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
+#define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
+#define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
+#define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
+
+// ABORT_STS bits
+#define cABORT_STS_PLL_ABORTED (1<<2)
+#define cABORT_STS_TC3_ABORTED (1<<1)
+#define cABORT_STS_SW_ABORTED (1<<0)
+
+// FILTERFAIL_CODE2 bits
+#define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
+#define cFILTERFAIL_CODE2_9_8 (3)
+
+// PHY_STS bits
+#define cPHY_STS_PLL_UNLOCK (1<<7)
+#define cPHY_STS_PLL_LOCK_ERR (1<<6)
+#define cPHY_STS_PLL_LOCK (1<<5)
+#define cPHY_STS_CRCVALID (1<<3)
+#define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
+#define cPHY_STS_SFD_DET (1<<1)
+#define cPHY_STS_PREAMBLE_DET (1<<0)
+
+// TESTMODE_CTRL bits
+#define cTEST_MODE_CTRL_HOT_ANT (1<<4)
+#define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
+#define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
+#define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
+#define cTEST_MODE_CTRL_FPGA_EN (1<<0)
+
+// DTM_CTRL1 bits
+#define cDTM_CTRL1_ATM_LOCKED (1<<7)
+#define cDTM_CTRL1_DTM_EN (1<<6)
+#define cDTM_CTRL1_PAGE5 (1<<5)
+#define cDTM_CTRL1_PAGE4 (1<<4)
+#define cDTM_CTRL1_PAGE3 (1<<3)
+#define cDTM_CTRL1_PAGE2 (1<<2)
+#define cDTM_CTRL1_PAGE1 (1<<1)
+#define cDTM_CTRL1_PAGE0 (1<<0)
+
+// TX_MODE_CTRL
+#define cTX_MODE_CTRL_TX_INV (1<<4)
+#define cTX_MODE_CTRL_BT_EN (1<<3)
+#define cTX_MODE_CTRL_DTS2 (1<<2)
+#define cTX_MODE_CTRL_DTS1 (1<<1)
+#define cTX_MODE_CTRL_DTS0 (1<<0)
+
+#define cTX_MODE_CTRL_DTS_MASK (7)
+
+// CLK_OUT_CTRL bits
+#define cCLK_OUT_EXTEND (1<<7)
+#define cCLK_OUT_HIZ (1<<6)
+#define cCLK_OUT_SR (1<<5)
+#define cCLK_OUT_DS (1<<4)
+#define cCLK_OUT_EN (1<<3)
+#define cCLK_OUT_DIV_Mask (7<<0)
+
+#define gCLK_OUT_FREQ_32_MHz (0)
+#define gCLK_OUT_FREQ_16_MHz (1)
+#define gCLK_OUT_FREQ_8_MHz (2)
+#define gCLK_OUT_FREQ_4_MHz (3)
+#define gCLK_OUT_FREQ_1_MHz (4)
+#define gCLK_OUT_FREQ_250_KHz (5)
+#define gCLK_OUT_FREQ_62_5_KHz (6)
+#define gCLK_OUT_FREQ_32_78_KHz (7)
+#define gCLK_OUT_FREQ_DISABLE (8)
+
+
+
+
+#endif /* __MCR20_REG_H__ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/driverRFPhy.c Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,1237 @@
+/*
+ * driverRFPhy.c
+ *
+ * Created on: 14 July 2014
+ * Author: mBed team
+ */
+#include "arm_hal_interrupt.h"
+#include "arm_hal_phy.h"
+#include "driverRFPhy.h"
+#include "driverAtmelRFInterface.h"
+#include <string.h>
+
+#include <stdio.h>
+
+#include "options.h"
+
+/*RF receive buffer*/
+static uint8_t rf_buffer[RF_BUFFER_SIZE];
+/*RF ACK receive buffer*/
+static uint8_t ack_rx_buf[5];
+/*ACK wait duration changes depending on data rate*/
+static uint16_t rf_ack_wait_duration = RF_ACK_WAIT_TIMEOUT;
+
+static uint8_t radio_tx_power = 0x07;
+static uint8_t rf_channel;
+static uint8_t rf_tuned = 1;
+static uint8_t radio_rpc_value = 0xef;
+static uint8_t rf_use_front_end = 0;
+static uint8_t rf_use_antenna_diversity = 0;
+static uint8_t rf_csd_port = 0;
+static uint8_t rf_csd_pin = 0;
+static uint8_t rf_cps_port = 0;
+static uint8_t rf_cps_pin = 0;
+static uint8_t tx_sequence = 0xff;
+static uint8_t need_ack = 0;
+static uint8_t rf_rx_mode = 0;
+static uint8_t rf_flags = 0;
+static uint8_t rf_rnd_rssi = 0;
+static int8_t rf_radio_driver_id = -1;
+static phy_device_driver_s device_driver;
+static uint8_t atmel_MAC[8];
+static phy_device_channel_info_s channel_info;
+static uint8_t mac_tx_handle = 0;
+
+/*
+ * \brief Function sets given RF flag on.
+ *
+ * \param x Given RF flag
+ *
+ * \return none
+ */
+void rf_flags_set(uint8_t x)
+{
+ rf_flags |= x;
+}
+
+/*
+ * \brief Function clears given RF flag on.
+ *
+ * \param x Given RF flag
+ *
+ * \return none
+ */
+void rf_flags_clear(uint8_t x)
+{
+ rf_flags &= ~x;
+}
+
+/*
+ * \brief Function checks if given RF flag is on.
+ *
+ * \param x Given RF flag
+ *
+ * \return states of the given flags
+ */
+uint8_t rf_flags_check(uint8_t x)
+{
+ return (rf_flags & x);
+}
+
+/*
+ * \brief Function clears all RF flags.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_flags_reset(void)
+{
+ rf_flags = 0;
+}
+
+/*
+ * \brief Function sets CPS and CSD pins of the Front end.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_front_end_rx_lna(void)
+{
+ /* not supported in this version */
+}
+
+/*
+ * \brief Function clears CPS and CSD pins of the Front end.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_front_end_sleep(void)
+{
+ /* not supported in this version */
+}
+
+/*
+ * \brief Function initialises and registers the RF driver.
+ *
+ * \param none
+ *
+ * \return rf_radio_driver_id Driver ID given by NET library
+ */
+int8_t rf_device_register(void)
+{
+ rf_init();
+ /*Set pointer to MAC address*/
+ device_driver.PHY_MAC = atmel_MAC;
+ device_driver.driver_description = "ATMEL_MAC";
+#if PHY_LINK_15_4_2_4GHZ_TYPE
+ /*Number of channels in PHY*/
+ channel_info.channel_count = 16;
+ /*Channel mask 26-11*/
+ channel_info.channel_mask = 0x07FFF800;
+ /*Type of RF PHY is SubGHz*/
+ device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
+ device_driver.link_channel_info = &channel_info;
+#else
+ /*Number of channels in PHY*/
+ channel_info.channel_count = 11;
+ /*Channel mask 0-10*/
+ channel_info.channel_mask = 0x000007ff;
+ /*Type of RF PHY is SubGHz*/
+ device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
+ device_driver.link_channel_info = &channel_info;
+#endif
+ /*Maximum size of payload is 127*/
+ device_driver.phy_MTU = 127;
+ /*No header in PHY*/
+ device_driver.phy_header_length = 0;
+ /*No tail in PHY*/
+ device_driver.phy_tail_length = 0;
+ /*Set address write function*/
+ device_driver.phy_xx_address_write = &rf_address_write;
+ /*Set RF extension function*/
+ device_driver.phy_xx_extension = &rf_extension;
+ /*Set RF state control function*/
+ device_driver.phy_xx_state_control = &rf_interface_state_control;
+ /*Set transmit function*/
+ device_driver.phy_xx_tx = &rf_start_cca;
+ printf("RF Device Registration...");
+ /*Register device driver*/
+ rf_radio_driver_id = arm_net_phy_register(&device_driver);
+ printf("OK\r\n");
+ return rf_radio_driver_id;
+}
+
+/*
+ * \brief Function returns the generated 8-bit random value for seeding Pseudo-random generator. This value was generated by reading noise from RF channel in RF initialisation.
+ *
+ * \param none
+ *
+ * \return random RSSI value
+ */
+int8_t rf_read_random(void)
+{
+ return rf_rnd_rssi;
+}
+
+/*
+ * \brief Function is a call back for ACK wait timeout.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_ack_wait_timer_interrupt(void)
+{
+ arm_enter_critical();
+ /*Force PLL state*/
+ rf_if_change_trx_state(FORCE_PLL_ON);
+ rf_poll_trx_state_change(PLL_ON);
+ /*Start receiver in RX_AACK_ON state*/
+ rf_rx_mode = 0;
+ rf_flags_clear(RFF_RX);
+ rf_receive();
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function is a call back for calibration interval timer.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_calibration_timer_interrupt(void)
+{
+ /*Calibrate RF*/
+ rf_calibration_cb();
+ /*Start new calibration timeout*/
+ rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
+}
+
+/*
+ * \brief Function initialises the RF timer for ACK wait and calibration.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_timer_init(void)
+{
+ rf_if_timer_init();
+}
+
+/*
+ * \brief Function starts the ACK wait timeout.
+ *
+ * \param slots Given slots, resolution 50us
+ *
+ * \return none
+ */
+void rf_ack_wait_timer_start(uint16_t slots)
+{
+ rf_if_ack_wait_timer_start(slots);
+}
+
+/*
+ * \brief Function starts the calibration interval.
+ *
+ * \param slots Given slots, resolution 50us
+ *
+ * \return none
+ */
+void rf_calibration_timer_start(uint32_t slots)
+{
+ rf_if_calibration_timer_start(slots);
+}
+
+/*
+ * \brief Function stops the ACK wait timeout.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_ack_wait_timer_stop(void)
+{
+ rf_if_ack_wait_timer_stop();
+}
+
+/*
+ * \brief Function reads the MAC address array.
+ *
+ * \param ptr Pointer to read array
+ *
+ * \return none
+ */
+void rf_read_mac_address(uint8_t *ptr)
+{
+ memcpy(ptr, atmel_MAC, 8);
+}
+
+/*
+ * \brief Function sets the MAC address array.
+ *
+ * \param ptr Pointer to given MAC address array
+ *
+ * \return none
+ */
+void rf_set_mac_address(const uint8_t *ptr)
+{
+ memcpy(atmel_MAC,ptr,8);
+}
+
+/*
+ * \brief Function writes various RF settings in startup.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_write_settings(void)
+{
+ int i, j = 0;
+
+ arm_enter_critical();
+
+ //printf("RF Write Settings: 1\r\n");
+ rf_if_write_rf_settings();
+
+ //printf("RF Write Settings: 2\r\n");
+ /*Set output power*/
+ rf_if_write_set_tx_power_register(radio_tx_power);
+
+ //printf("RF Write Settings: 3\r\n");
+ /*Set RPC register*/
+ rf_if_write_set_trx_rpc_register(radio_rpc_value);
+
+ //printf("RF Write Settings: 4\r\n");
+ /*Initialise Front end*/
+ if(rf_use_front_end)
+ {
+ printf("RF Front End used\r\n");
+ rf_if_enable_pa_ext();
+ /* not supported in this version */
+ }
+
+ //printf("RF Write Settings: 5\r\n");
+ /*Initialise Antenna Diversity*/
+ if(rf_use_antenna_diversity) {
+ printf("RF Antenna diversity\r\n");
+ rf_if_write_antenna_diversity_settings();
+ }
+
+ printf("RF Write Settings: 7\r\n");
+ arm_exit_critical();
+ printf("RF Write Settings End\r\n");
+}
+
+/*
+ * \brief Function writes 16-bit address in RF address filter.
+ *
+ * \param short_address Given short address
+ *
+ * \return none
+ */
+void rf_set_short_adr(uint8_t * short_address)
+{
+ uint8_t rf_off_flag = 0;
+ arm_enter_critical();
+ /*Wake up RF if sleeping*/
+ if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
+ {
+ rf_if_disable_slptr();
+ rf_off_flag = 1;
+ rf_poll_trx_state_change(TRX_OFF);
+ }
+ /*Write address filter registers*/
+ rf_if_write_short_addr_registers(short_address);
+ /*RF back to sleep*/
+ if(rf_off_flag)
+ rf_if_enable_slptr();
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function writes PAN Id in RF PAN Id filter.
+ *
+ * \param pan_id Given PAN Id
+ *
+ * \return none
+ */
+void rf_set_pan_id(uint8_t *pan_id)
+{
+ uint8_t rf_off_flag = 0;
+
+ arm_enter_critical();
+ /*Wake up RF if sleeping*/
+ if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
+ {
+ rf_if_disable_slptr();
+ rf_off_flag = 1;
+ rf_poll_trx_state_change(TRX_OFF);
+ }
+ /*Write address filter registers*/
+ rf_if_write_pan_id_registers(pan_id);
+ /*RF back to sleep*/
+ if(rf_off_flag)
+ rf_if_enable_slptr();
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function writes 64-bit address in RF address filter.
+ *
+ * \param address Given 64-bit address
+ *
+ * \return none
+ */
+void rf_set_address(uint8_t *address)
+{
+ uint8_t rf_off_flag = 0;
+
+ arm_enter_critical();
+ /*Wake up RF if sleeping*/
+ if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
+ {
+ rf_if_disable_slptr();
+ rf_off_flag = 1;
+ rf_poll_trx_state_change(TRX_OFF);
+ }
+ /*Write address filter registers*/
+ rf_if_write_ieee_addr_registers(address);
+ /*RF back to sleep*/
+ if(rf_off_flag)
+ rf_if_enable_slptr();
+
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function sets the RF channel.
+ *
+ * \param ch New channel
+ *
+ * \return none
+ */
+void rf_channel_set(uint8_t ch)
+{
+ arm_enter_critical();
+ rf_channel = ch;
+ if(ch < 0x1f)
+ rf_if_set_channel_register(ch);
+ arm_exit_critical();
+}
+
+
+/*
+ * \brief Function initialises the radio driver and resets the radio.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_init(void)
+{
+ printf("RF Init Start\r\n");
+ /*Initialise timers*/
+ rf_timer_init(); //TODO
+ rf_channel = RF_DEFAULT_CHANNEL;
+ printf("RF Reset\r\n");
+ /*Reset RF module*/
+ rf_if_reset_radio();
+ printf("RF Write Settings\r\n");
+ /*Write RF settings*/
+ rf_write_settings();
+ printf("RF Init PHY Mode\r\n");
+ /*Initialise PHY mode*/
+ rf_init_phy_mode();
+ /*Clear RF flags*/
+ rf_flags_reset();
+ /*Set RF in TRX OFF state*/
+ rf_if_change_trx_state(TRX_OFF);
+ /*Set RF in PLL_ON state*/
+ rf_if_change_trx_state(PLL_ON);
+ /*Start receiver*/
+ rf_receive();
+ /*Read random variable. This will be used when seeding pseudo-random generator*/
+ rf_rnd_rssi = rf_if_read_rnd();
+ /*Start RF calibration timer*/
+ rf_calibration_timer_start(RF_CALIBRATION_INTERVAL); //ACA!
+ printf("RF Init End\r\n");
+}
+
+/**
+ * \brief Function gets called when MAC is setting radio off.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_off(void)
+{
+ if(rf_flags_check(RFF_ON))
+ {
+ rf_cca_abort();
+ uint16_t while_counter = 0;
+ /*Wait while receiving*/
+ while(rf_if_read_trx_state() == BUSY_RX_AACK || rf_if_read_trx_state() == BUSY_RX)
+ {
+ while_counter++;
+ if(while_counter == 0xffff)
+ break;
+ }
+ /*RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP*/
+ if(rf_if_read_trx_state() == RX_AACK_ON)
+ {
+ rf_if_change_trx_state(PLL_ON);
+ }
+ rf_if_change_trx_state(TRX_OFF);
+ rf_if_enable_slptr();
+ rf_flags_clear(~RFF_ON);
+ /*Front end in sleep*/
+ if(rf_use_front_end)
+ {
+ rf_if_disable_pa_ext();
+ rf_front_end_sleep();
+ }
+ /*Disable Antenna Diversity*/
+ if(rf_use_antenna_diversity)
+ rf_if_disable_ant_div();
+ }
+}
+
+/*
+ * \brief Function polls the RF state until it has changed to desired state.
+ *
+ * \param trx_state RF state
+ *
+ * \return none
+ */
+void rf_poll_trx_state_change(rf_trx_states_t trx_state)
+{
+ uint16_t while_counter = 0;
+ arm_enter_critical();
+
+ if(trx_state != RF_TX_START)
+ {
+ if(trx_state == FORCE_PLL_ON)
+ trx_state = PLL_ON;
+ else if(trx_state == FORCE_TRX_OFF)
+ trx_state = TRX_OFF;
+
+ while(rf_if_read_trx_state() != trx_state)
+ {
+ while_counter++;
+ if(while_counter == 0x1ff)
+ break;
+ }
+ }
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
+ *
+ * \param data_ptr Pointer to TX data
+ * \param data_length Length of the TX data
+ * \param tx_handle Handle to transmission
+ * \return 0 Success
+ * \return -1 Busy
+ */
+int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle)
+{
+ /*Check if transmitter is busy*/
+ if((rf_if_read_trx_state() == BUSY_RX_AACK) || (rf_if_read_trx_state() == BUSY_RX))
+ {
+ /*Return busy*/
+ return -1;
+ }
+ else
+ {
+ arm_enter_critical();
+ /*Check if transmitted data needs to be acked*/
+ if(*data_ptr & 0x20)
+ need_ack = 1;
+ else
+ need_ack = 0;
+ /*Store the sequence number for ACK handling*/
+ tx_sequence = *(data_ptr + 2);
+ /*Set radio in RX state to read channel*/
+ rf_receive();
+ /*Write TX FIFO*/
+ rf_if_write_frame_buffer(data_ptr, (uint8_t)data_length);
+ rf_flags_set(RFF_CCA);
+ /*Start CCA process*/
+ rf_if_enable_cca_ed_done_interrupt();
+ rf_if_start_cca_process();
+ /*Store TX handle*/
+ mac_tx_handle = tx_handle;
+ arm_exit_critical();
+ }
+
+ /*Return success*/
+ return 0;
+}
+
+/*
+ * \brief Function aborts CCA process.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_cca_abort(void)
+{
+ /*Clear RFF_CCA RF flag*/
+ rf_flags_clear(RFF_CCA);
+}
+
+
+
+/*
+ * \brief Function starts the transmission of the frame.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_start_tx(void)
+{
+ /*Only start transmitting from RX state*/
+ uint8_t trx_state = rf_if_read_trx_state();
+ if((trx_state != RX_AACK_ON) && (trx_state != RX_ON))
+ {
+ arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
+ }
+ else
+ {
+ /*RF state change: ->PLL_ON->RF_TX_START*/
+ rf_if_change_trx_state(FORCE_PLL_ON);
+ rf_flags_clear(RFF_RX);
+ rf_if_enable_tx_end_interrupt();
+ rf_flags_set(RFF_TX);
+ rf_if_change_trx_state(RF_TX_START);
+ }
+}
+
+/*
+ * \brief Function sets the RF in RX state.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_receive(void)
+{
+ uint16_t while_counter = 0;
+ if(rf_flags_check(RFF_ON) == 0)
+ {
+ rf_on();
+ }
+ /*If not yet in RX state set it*/
+ if(rf_flags_check(RFF_RX) == 0)
+ {
+ arm_enter_critical();
+ /*Wait while receiving data*/
+ while((rf_if_read_trx_state() == BUSY_RX) || (rf_if_read_trx_state() == BUSY_RX_AACK))
+ {
+ while_counter++;
+ if(while_counter == 0xffff)
+ {
+ break;
+ }
+ }
+ /*Wake up from sleep state*/
+ if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1f)
+ {
+ rf_if_disable_slptr();
+ rf_poll_trx_state_change(TRX_OFF);
+ }
+
+ rf_if_change_trx_state(PLL_ON);
+ /*ACK is always received in RX_ON state to bypass address filters*/
+ if(rf_rx_mode)
+ {
+ rf_rx_mode = 0;
+ rf_if_change_trx_state(RX_ON);
+ }
+ else
+ {
+ rf_if_change_trx_state(RX_AACK_ON);
+ /*If calibration timer was unable to calibrate the RF, run calibration now*/
+ if(!rf_tuned)
+ {
+ /*Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state*/
+ rf_if_calibration();
+ /*RF is tuned now*/
+ rf_tuned = 1;
+ }
+ }
+ rf_channel_set(rf_channel);
+ rf_flags_set(RFF_RX);
+ rf_if_enable_rx_end_interrupt();
+ /*Enable LNA if Front end used*/
+ if(rf_use_front_end)
+ rf_front_end_rx_lna();
+ arm_exit_critical();
+ }
+ /*Stop the running CCA process*/
+ if(rf_flags_check(RFF_CCA))
+ rf_cca_abort();
+}
+
+/*
+ * \brief Function calibrates the radio.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_calibration_cb(void)
+{
+ /*clear tuned flag to start tuning in rf_receive*/
+ rf_tuned = 0;
+ /*If RF is in default receive state, start calibration*/
+ if(rf_if_read_trx_state() == RX_AACK_ON)
+ {
+ arm_enter_critical();
+ /*Set RF in PLL_ON state*/
+ rf_if_change_trx_state(PLL_ON);
+ /*Set RF in TRX_OFF state to start PLL tuning*/
+ rf_if_change_trx_state(TRX_OFF);
+ /*Set RF in RX_ON state to calibrate*/
+ rf_if_change_trx_state(RX_ON);
+ /*Calibrate FTN*/
+ rf_if_calibration();
+ /*RF is tuned now*/
+ rf_tuned = 1;
+ /*Back to default receive state*/
+ rf_flags_clear(RFF_RX);
+ rf_receive();
+ arm_exit_critical();
+ }
+}
+
+/*
+ * \brief Function sets RF_ON flag when radio is powered.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_on(void)
+{
+ /*Set RFF_ON flag*/
+ if(rf_flags_check(RFF_ON) == 0)
+ {
+ rf_flags_set(RFF_ON);
+ /*Wake up Front end*/
+ if(rf_use_front_end)
+ {
+ /*Set PA_EXT_EN to enable controlling of external front end*/
+ rf_if_enable_pa_ext();
+ rf_front_end_rx_lna();
+ }
+ /*Enable Antenna diversity*/
+ if(rf_use_antenna_diversity)
+ /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/
+ rf_if_enable_ant_div();
+ }
+}
+
+/*
+ * \brief Function handles the received ACK frame.
+ *
+ * \param seq_number Sequence number of received ACK
+ * \param data_pending Pending bit state in received ACK
+ *
+ * \return none
+ */
+void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
+{
+ phy_link_tx_status_e phy_status;
+ arm_enter_critical();
+ /*Received ACK sequence must be equal with transmitted packet sequence*/
+ if(tx_sequence == seq_number)
+ {
+ rf_ack_wait_timer_stop();
+ /*When data pending bit in ACK frame is set, inform NET library*/
+ if(data_pending)
+ phy_status = PHY_LINK_TX_DONE_PENDING;
+ else
+ phy_status = PHY_LINK_TX_DONE;
+ /*Call PHY TX Done API*/
+ arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle,phy_status, 1, 1);
+ }
+ arm_exit_critical();
+}
+
+/*
+ * \brief Function is a call back for RX end interrupt.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_handle_rx_end(void)
+{
+ uint8_t rf_lqi;
+
+ /*Frame received interrupt*/
+ if(rf_flags_check(RFF_RX))
+ {
+ /*Check CRC_valid bit*/
+ if(rf_if_check_crc())
+ {
+ uint8_t *rf_rx_ptr;
+ uint8_t receiving_ack = 0;
+ /*Read length*/
+ uint8_t len = rf_if_read_received_frame_length();
+ /*Not ACK frame*/
+ if(len > 5)
+ {
+ rf_rx_ptr = rf_buffer;
+ }
+ /*ACK received*/
+ else
+ {
+ /*Read ACK in static ACK buffer*/
+ receiving_ack = 1;
+ rf_rx_ptr = ack_rx_buf;
+ }
+ /*Check the length is valid*/
+ if(len > 1 && len < RF_BUFFER_SIZE)
+ {
+ /*Read received packet*/
+ rf_if_read_packet(rf_rx_ptr, len);
+ /*Get LQI*/
+ rf_lqi = rf_if_read_lqi();
+ /*Handle received ACK*/
+ if(receiving_ack && ((ack_rx_buf[0] & 0x07) == 0x02))
+ {
+ uint8_t pending = 0;
+ /*Check if data is pending*/
+ if ((ack_rx_buf[0] & 0x10))
+ {
+ pending=1;
+ }
+ /*Send sequence number in ACK handler*/
+ rf_handle_ack(ack_rx_buf[2], pending);
+ }
+ /*Handle received data*/
+ else if(rf_if_read_trx_state() != RX_ON && rf_if_read_trx_state() != BUSY_RX)
+ {
+ arm_net_phy_rx(rf_buffer,len - 2, rf_lqi, rf_radio_driver_id);
+ }
+ }
+ }
+ }
+ /*Start receiver*/
+ rf_flags_clear(RFF_RX);
+ rf_receive();
+}
+
+/*
+ * \brief Function is called when MAC is shutting down the radio.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_shutdown(void)
+{
+ /*Call RF OFF*/
+ rf_off();
+ /*Clear RF flags*/
+ rf_flags_reset();
+}
+
+/*
+ * \brief Function is a call back for TX end interrupt.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_handle_tx_end(void)
+{
+ phy_link_tx_status_e phy_status = PHY_LINK_TX_SUCCESS;
+
+ rf_rx_mode = 0;
+ /*If ACK is needed for this transmission*/
+ if(need_ack && rf_flags_check(RFF_TX))
+ {
+ rf_ack_wait_timer_start(rf_ack_wait_duration);
+ rf_rx_mode = 1;
+ }
+ rf_flags_clear(RFF_RX);
+ /*Start receiver*/
+ rf_receive();
+
+ /*Call PHY TX Done API*/
+ arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, phy_status, 1, 1);
+}
+
+/*
+ * \brief Function is a call back for CCA ED done interrupt.
+ *
+ * \param none
+ *
+ * \return none
+ */
+void rf_handle_cca_ed_done(void)
+{
+ rf_flags_clear(RFF_CCA);
+ /*Check the result of CCA process*/
+ if(rf_if_check_cca())
+ {
+ rf_start_tx();
+ }
+ else
+ {
+ /*Send CCA fail notification*/
+ arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
+ }
+}
+
+/*
+ * \brief Function sets the TX power variable.
+ *
+ * \param power TX power setting
+ *
+ * \return 0 Success
+ * \return -1 Fail
+ */
+int8_t rf_tx_power_set(uint8_t power)
+{
+ int8_t ret_val = -1;
+ if(power < 16)
+ {
+ radio_tx_power = power;
+ ret_val = 0;
+ }
+ return ret_val;
+}
+
+/*
+ * \brief Function returns the TX power variable.
+ *
+ * \param none
+ *
+ * \return radio_tx_power TX power variable
+ */
+uint8_t rf_tx_power_get(void)
+{
+ return radio_tx_power;
+}
+
+/*
+ * \brief Function sets the RF RPC variable.
+ *
+ * \param rpc_value RPC setting
+ *
+ * \return 0 Success
+ */
+int8_t rf_rpc_set(uint8_t rpc_value)
+{
+ int8_t ret_val = -1;
+ radio_rpc_value = rpc_value;
+ ret_val = 0;
+ return ret_val;
+}
+
+/*
+ * \brief Function enables the usage of Front end.
+ *
+ * \param none
+ *
+ * \return 0 Success
+ */
+int8_t rf_enable_pa(void)
+{
+ int8_t ret_val = 0;
+ rf_use_front_end = 1;
+ return ret_val;
+}
+
+/*
+ * \brief Function enables the usage of Antenna diversity.
+ *
+ * \param none
+ *
+ * \return 0 Success
+ */
+int8_t rf_enable_antenna_diversity(void)
+{
+ int8_t ret_val = 0;
+ rf_use_antenna_diversity = 1;
+ return ret_val;
+}
+
+/*
+ * \brief Function defines the CSD pin of the Front end.
+ *
+ * \param port CSD port
+ * \param port CSD pin
+ *
+ * \return 0 Success
+ */
+int8_t rf_set_csd_pin(uint8_t port, uint8_t pin)
+{
+ int8_t ret_val = -1;
+
+ rf_csd_port = port;
+ rf_csd_pin = pin;
+ ret_val = 0;
+
+ return ret_val;
+}
+
+/*
+ * \brief Function defines the CPS pin of the Front end.
+ *
+ * \param port CPS port
+ * \param port CPS pin
+ *
+ * \return 0 Success
+ */
+int8_t rf_set_cps_pin(uint8_t port, uint8_t pin)
+{
+ int8_t ret_val = -1;
+
+ rf_cps_port = port;
+ rf_cps_pin = pin;
+ ret_val = 0;
+
+ return ret_val;
+}
+
+/*
+ * \brief Function gives the control of RF states to MAC.
+ *
+ * \param new_state RF state
+ * \param rf_channel RF channel
+ *
+ * \return 0 Success
+ */
+static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
+{
+ int8_t ret_val = 0;
+ switch (new_state)
+ {
+ /*Reset PHY driver and set to idle*/
+ case PHY_INTERFACE_RESET:
+ break;
+ /*Disable PHY Interface driver*/
+ case PHY_INTERFACE_DOWN:
+ rf_shutdown();
+ break;
+ /*Enable PHY Interface driver*/
+ case PHY_INTERFACE_UP:
+ rf_channel_set(rf_channel);
+ rf_receive();
+ break;
+ /*Enable wireless interface ED scan mode*/
+ case PHY_INTERFACE_RX_ENERGY_STATE:
+ break;
+ }
+ return ret_val;
+}
+
+/*
+ * \brief Function controls the ACK pending, channel setting and energy detection.
+ *
+ * \param extension_type Type of control
+ * \param data_ptr Data from NET library
+ *
+ * \return 0 Success
+ */
+static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
+{
+ switch (extension_type)
+ {
+ /*Control MAC pending bit for Indirect data transmission*/
+ case PHY_EXTENSION_CTRL_PENDING_BIT:
+ if(*data_ptr)
+ {
+ rf_if_ack_pending_ctrl(1);
+ }
+ else
+ {
+ rf_if_ack_pending_ctrl(0);
+ }
+ break;
+ /*Return frame pending status*/
+ case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS:
+ *data_ptr = rf_if_last_acked_pending();
+ break;
+ /*Set channel*/
+ case PHY_EXTENSION_SET_CHANNEL:
+ break;
+ /*Read energy on the channel*/
+ case PHY_EXTENSION_READ_CHANNEL_ENERGY:
+ break;
+ /*Read status of the link*/
+ case PHY_EXTENSION_READ_LINK_STATUS:
+ break;
+ }
+ return 0;
+}
+
+/*
+ * \brief Function sets the addresses to RF address filters.
+ *
+ * \param address_type Type of address
+ * \param address_ptr Pointer to given address
+ *
+ * \return 0 Success
+ */
+static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
+{
+ int8_t ret_val = 0;
+ switch (address_type)
+ {
+ /*Set 48-bit address*/
+ case PHY_MAC_48BIT:
+ break;
+ /*Set 64-bit address*/
+ case PHY_MAC_64BIT:
+ rf_set_address(address_ptr);
+ break;
+ /*Set 16-bit address*/
+ case PHY_MAC_16BIT:
+ rf_set_short_adr(address_ptr);
+ break;
+ /*Set PAN Id*/
+ case PHY_MAC_PANID:
+ rf_set_pan_id(address_ptr);
+ break;
+ }
+ return ret_val;
+}
+
+/*
+ * \brief Function initialises the ACK wait time and returns the used PHY mode.
+ *
+ * \param none
+ *
+ * \return tmp Used PHY mode
+ */
+uint8_t rf_init_phy_mode(void)
+{
+ uint8_t tmp;
+ /*Read used PHY Mode*/
+ tmp = rf_if_read_register(TRX_CTRL_2);
+ /*Set ACK wait time for used data rate*/
+ if((tmp & 0x1f) == 0x00)
+ {
+ rf_ack_wait_duration = 938;
+ tmp = BPSK_20;
+ }
+ else if((tmp & 0x1f) == 0x04)
+ {
+ rf_ack_wait_duration = 469;
+ tmp = BPSK_40;
+ }
+ else if((tmp & 0x1f) == 0x14)
+ {
+ rf_ack_wait_duration = 469;
+ tmp = BPSK_40_ALT;
+ }
+ else if((tmp & 0x1f) == 0x08)
+ {
+ rf_ack_wait_duration = 100;
+ tmp = OQPSK_SIN_RC_100;
+ }
+ else if((tmp & 0x1f) == 0x09)
+ {
+ rf_ack_wait_duration = 50;
+ tmp = OQPSK_SIN_RC_200;
+ }
+ else if((tmp & 0x1f) == 0x18)
+ {
+ rf_ack_wait_duration = 100;
+ tmp = OQPSK_RC_100;
+ }
+ else if((tmp & 0x1f) == 0x19)
+ {
+ rf_ack_wait_duration = 50;
+ tmp = OQPSK_RC_200;
+ }
+ else if((tmp & 0x1f) == 0x0c)
+ {
+ rf_ack_wait_duration = 50;
+ tmp = OQPSK_SIN_250;
+ }
+ else if((tmp & 0x1f) == 0x0d)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_SIN_500;
+ }
+ else if((tmp & 0x1f) == 0x0f)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_SIN_500_ALT;
+ }
+ else if((tmp & 0x1f) == 0x1c)
+ {
+ rf_ack_wait_duration = 50;
+ tmp = OQPSK_RC_250;
+ }
+ else if((tmp & 0x1f) == 0x1d)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_RC_500;
+ }
+ else if((tmp & 0x1f) == 0x1f)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_RC_500_ALT;
+ }
+ else if((tmp & 0x3f) == 0x2A)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_SIN_RC_400_SCR_ON;
+ }
+ else if((tmp & 0x3f) == 0x0A)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_SIN_RC_400_SCR_OFF;
+ }
+ else if((tmp & 0x3f) == 0x3A)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_RC_400_SCR_ON;
+ }
+ else if((tmp & 0x3f) == 0x1A)
+ {
+ rf_ack_wait_duration = 25;
+ tmp = OQPSK_RC_400_SCR_OFF;
+ }
+ else if((tmp & 0x3f) == 0x2E)
+ {
+ rf_ack_wait_duration = 13;
+ tmp = OQPSK_SIN_1000_SCR_ON;
+ }
+ else if((tmp & 0x3f) == 0x0E)
+ {
+ rf_ack_wait_duration = 13;
+ tmp = OQPSK_SIN_1000_SCR_OFF;
+ }
+ else if((tmp & 0x3f) == 0x3E)
+ {
+ rf_ack_wait_duration = 13;
+ tmp = OQPSK_RC_1000_SCR_ON;
+ }
+ else if((tmp & 0x3f) == 0x1E)
+ {
+ rf_ack_wait_duration = 13;
+ tmp = OQPSK_RC_1000_SCR_OFF;
+ }
+ return tmp;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/driverRFPhy.h Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,77 @@
+/*
+ * driverRFPhy.h
+ *
+ * Created on: 14 July 2014
+ * Author: mBed Team
+ */
+
+#ifndef DRIVERRFPHY_H_
+#define DRIVERRFPHY_H_
+
+#include "arm_hal_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*Run calibration every 5 minutes*/
+#define RF_CALIBRATION_INTERVAL 6000000
+/*Wait ACK for 2.5ms*/
+#define RF_ACK_WAIT_TIMEOUT 50
+
+#define RF_BUFFER_SIZE 128
+#define RF_DEFAULT_CHANNEL 11
+
+/*Radio RX and TX state definitions*/
+#define RFF_ON 0x01
+#define RFF_RX 0x02
+#define RFF_TX 0x04
+#define RFF_CCA 0x08
+
+/*Atmel RF states*/
+typedef enum
+{
+ NOP = 0x00,
+ BUSY_RX = 0x01,
+ RF_TX_START = 0x02,
+ FORCE_TRX_OFF = 0x03,
+ FORCE_PLL_ON = 0x04,
+ RX_ON = 0x06,
+ TRX_OFF = 0x08,
+ PLL_ON = 0x09,
+ BUSY_RX_AACK = 0x11,
+ SLEEP = 0x0F,
+ RX_AACK_ON = 0x16,
+ TX_ARET_ON = 0x19
+}rf_trx_states_t;
+
+extern void rf_ack_wait_timer_start(uint16_t slots);
+extern void rf_ack_wait_timer_stop(void);
+extern void rf_handle_cca_ed_done(void);
+extern void rf_handle_tx_end(void);
+extern void rf_handle_rx_end(void);
+extern void rf_on(void);
+extern void rf_receive(void);
+extern void rf_poll_trx_state_change(rf_trx_states_t trx_state);
+extern void rf_init(void);
+extern void rf_set_mac_address(const uint8_t *ptr);
+extern int8_t rf_device_register(void);
+extern int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle);
+extern void rf_cca_abort(void);
+extern void rf_read_mac_address(uint8_t *ptr);
+extern int8_t rf_read_random(void);
+extern void rf_calibration_cb(void);
+extern uint8_t rf_init_phy_mode(void);
+extern void rf_ack_wait_timer_interrupt(void);
+extern void rf_calibration_timer_interrupt(void);
+extern void rf_calibration_timer_start(uint32_t slots);
+extern void rf_front_end_rx_lna(void);
+extern void rf_front_end_sleep(void);
+static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
+static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
+static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
+
+ #ifdef __cplusplus
+}
+#endif
+#endif /* DRIVERRFPHY_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/low_level_RF.cpp Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,144 @@
+/* this file needs customization
+ according the target hardware
+*/
+
+
+#include "mbed.h"
+
+extern "C" void rf_if_interrupt_handler(void);
+
+#if defined(TARGET_K64F)
+SPI spi(PTD2, PTD3, PTD1);
+#elif defined(TARGET_NUCLEO_F401RE)
+SPI spi(SPI_MOSI, SPI_MISO, SPI_SCK);
+#else
+ "SPI not defined for this platform"
+#endif
+
+DigitalOut RF_CS(D10);
+DigitalOut RF_RST(D5);
+DigitalOut RF_SLP_TR(D7); // Not used in FSL
+InterruptIn RF_IRQ (D2); // FSL //(D9); // Atmel Radio
+
+
+extern "C" void RF_IRQ_Init(void) {
+
+ RF_IRQ.rise(&rf_if_interrupt_handler);
+}
+
+extern "C" void RF_RST_Set(int state) {
+ RF_RST = state;
+}
+
+extern "C" void RF_SLP_TR_Set(int state) {
+ RF_SLP_TR = state;
+}
+
+extern "C" void RF_CS_while_active(void) {
+
+ while(!RF_CS);
+}
+
+
+extern "C" int spi_read(char addr) {
+
+ // Select the device by seting chip select low
+ RF_CS = 0;
+ // Write the reg. address
+ spi.write(addr);
+ // write a dummy value to read the reg. value
+ int val = spi.write(0x00);
+ // Deselect the device
+ RF_CS = 1;
+ return val;
+}
+
+extern "C" void spi_write(char addr, char val) {
+
+ // Select the device by seting chip select low
+ RF_CS = 0;
+ // Write the reg. address
+ spi.write(addr);
+ // write the value to the addresses register
+ spi.write(val);
+ // Deselect the device
+ RF_CS = 1;
+}
+
+extern "C" void spi_master_transfer(uint32_t instance,
+ uint8_t * sendBuffer,
+ uint8_t * receiveBuffer,
+ size_t transferByteCount)
+{
+
+ volatile uint8_t dummy;
+/*
+#if BOARD_USE_DSPI
+ uint32_t baseAddr = g_dspiBaseAddr[instance];
+#else
+ uint32_t baseAddr = g_spiBaseAddr[instance];
+#endif
+*/
+
+ if( !transferByteCount )
+ return;
+
+ if( !sendBuffer && !receiveBuffer )
+ return;
+/*
+#if BOARD_USE_DSPI
+ DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true);
+#endif
+*/
+
+ while( transferByteCount-- )
+ {
+ if( sendBuffer )
+ {
+ dummy = *sendBuffer;
+ sendBuffer++;
+ }
+ else
+ {
+ dummy = 0xFF;
+ }
+
+ /*
+#if BOARD_USE_DSPI
+ DSPI_HAL_WriteDataMastermodeBlocking(baseAddr, &mSpiCommand, dummy);
+ dummy = DSPI_HAL_ReadData(baseAddr);
+#else
+ #if FSL_FEATURE_SPI_16BIT_TRANSFERS
+ SPI_HAL_WriteDataBlocking(baseAddr, kSpi8BitMode, 0, dummy);
+ while(!SPI_HAL_IsReadBuffFullPending(baseAddr));
+ dummy = SPI_HAL_ReadDataLow(baseAddr);
+ #else
+ SPI_HAL_WriteDataBlocking(baseAddr, dummy);
+ dummy = SPI_HAL_ReadData(baseAddr);
+ #endif
+#endif
+*/
+
+ dummy = spi.write(dummy);
+ // write a dummy value to read the reg. value
+ //dummy = spi.write(0x00); //???
+
+ if( receiveBuffer )
+ {
+ *receiveBuffer = dummy;
+ receiveBuffer++;
+ }
+ }
+
+}
+
+extern "C" void RF_CS_Set(int state) {
+ RF_CS = state;
+}
+
+extern "C" int spi_exchange(char value) {
+
+ // write the value
+ int val = spi.write(value);
+ return val;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_Drivers_FSL/low_level_RF.h Thu Mar 05 14:32:32 2015 -0600
@@ -0,0 +1,31 @@
+#ifndef LOW_LEVEL_RF_H
+#define LOW_LEVEL_RF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "string.h"
+#include "EmbeddedTypes.h"
+
+void spi_write(char addr, char val);
+int spi_read(char addr);
+int spi_exchange(char data);
+
+void RF_RST_Set(int state);
+void RF_SLP_TR_Set(int state);
+void RF_CS_while_active(void);
+void RF_CS_Set(int state);
+void RF_IRQ_Init(void);
+
+void spi_master_transfer(uint32_t instance,
+ uint8_t * sendBuffer,
+ uint8_t * receiveBuffer,
+ size_t transferByteCount);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // LOW_LEVEL_RF_H