MCR20Reg.h

00001 /*!
00002 * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003 * All rights reserved.
00004 *
00005 * \file MCR20reg.h
00006 * MCR20 Registers
00007 *
00008 * Redistribution and use in source and binary forms, with or without modification,
00009 * are permitted provided that the following conditions are met:
00010 *
00011 * o Redistributions of source code must retain the above copyright notice, this list
00012 *   of conditions and the following disclaimer.
00013 *
00014 * o Redistributions in binary form must reproduce the above copyright notice, this
00015 *   list of conditions and the following disclaimer in the documentation and/or
00016 *   other materials provided with the distribution.
00017 *
00018 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00019 *   contributors may be used to endorse or promote products derived from this
00020 *   software without specific prior written permission.
00021 *
00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00023 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00024 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00026 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00027 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00028 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00029 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00030 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00031 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032 */
00033 
00034 #ifndef __MCR20_REG_H__
00035 #define __MCR20_REG_H__
00036 /*****************************************************************************
00037  *                               INCLUDED HEADERS                            *
00038  *---------------------------------------------------------------------------*
00039  * Add to this section all the headers that this module needs to include.    *
00040  * Note that it is not a good practice to include header files into header   *
00041  * files, so use this section only if there is no other better solution.     *
00042  *---------------------------------------------------------------------------*
00043  *****************************************************************************/
00044 
00045 /****************************************************************************/
00046 /* Transceiver SPI Registers */
00047 /****************************************************************************/
00048 
00049 #define TransceiverSPI_IARIndexReg                  (0x3E)
00050 
00051 #define TransceiverSPI_ReadSelect                   (1<<7)
00052 #define TransceiverSPI_WriteSelect                  (0<<7)
00053 #define TransceiverSPI_RegisterAccessSelect         (0<<6)
00054 #define TransceiverSPI_PacketBuffAccessSelect       (1<<6)
00055 #define TransceiverSPI_PacketBuffBurstModeSelect    (0<<5)
00056 #define TransceiverSPI_PacketBuffByteModeSelect     (1<<5)
00057 
00058 #define TransceiverSPI_DirectRegisterAddressMask    (0x3F)
00059 
00060 #define IRQSTS1             0x00
00061 #define IRQSTS2             0x01
00062 #define IRQSTS3             0x02
00063 #define PHY_CTRL1           0x03
00064 #define PHY_CTRL2           0x04
00065 #define PHY_CTRL3           0x05
00066 #define RX_FRM_LEN          0x06
00067 #define PHY_CTRL4           0x07
00068 #define SRC_CTRL            0x08
00069 #define SRC_ADDRS_SUM_LSB   0x09
00070 #define SRC_ADDRS_SUM_MSB   0x0A
00071 #define CCA1_ED_FNL         0x0B
00072 #define EVENT_TMR_LSB       0x0C
00073 #define EVENT_TMR_MSB       0x0D
00074 #define EVENT_TMR_USB       0x0E
00075 #define TIMESTAMP_LSB       0x0F
00076 #define TIMESTAMP_MSB       0x10
00077 #define TIMESTAMP_USB       0x11
00078 #define T3CMP_LSB           0x12
00079 #define T3CMP_MSB           0x13
00080 #define T3CMP_USB           0x14
00081 #define T2PRIMECMP_LSB      0x15
00082 #define T2PRIMECMP_MSB      0x16
00083 #define T1CMP_LSB           0x17
00084 #define T1CMP_MSB           0x18
00085 #define T1CMP_USB           0x19
00086 #define T2CMP_LSB           0x1A
00087 #define T2CMP_MSB           0x1B
00088 #define T2CMP_USB           0x1C
00089 #define T4CMP_LSB           0x1D
00090 #define T4CMP_MSB           0x1E
00091 #define T4CMP_USB           0x1F
00092 #define PLL_INT0            0x20
00093 #define PLL_FRAC0_LSB       0x21
00094 #define PLL_FRAC0_MSB       0x22
00095 #define PA_PWR              0x23
00096 #define SEQ_STATE           0x24
00097 #define LQI_VALUE           0x25
00098 #define RSSI_CCA_CONT       0x26
00099 //--------------            0x27
00100 #define ASM_CTRL1           0x28
00101 #define ASM_CTRL2           0x29
00102 #define ASM_DATA_0          0x2A
00103 #define ASM_DATA_1          0x2B
00104 #define ASM_DATA_2          0x2C
00105 #define ASM_DATA_3          0x2D
00106 #define ASM_DATA_4          0x2E
00107 #define ASM_DATA_5          0x2F
00108 #define ASM_DATA_6          0x30
00109 #define ASM_DATA_7          0x31
00110 #define ASM_DATA_8          0x32
00111 #define ASM_DATA_9          0x33
00112 #define ASM_DATA_A          0x34
00113 #define ASM_DATA_B          0x35
00114 #define ASM_DATA_C          0x36
00115 #define ASM_DATA_D          0x37
00116 #define ASM_DATA_E          0x38
00117 #define ASM_DATA_F          0x39
00118 //-------------------       0x3A
00119 #define OVERWRITE_VER       0x3B
00120 #define CLK_OUT_CTRL        0x3C
00121 #define PWR_MODES           0x3D
00122 #define IAR_INDEX           0x3E
00123 #define IAR_DATA            0x3F
00124 
00125 
00126 #define PART_ID             0x00
00127 #define XTAL_TRIM           0x01
00128 #define PMC_LP_TRIM         0x02
00129 #define MACPANID0_LSB       0x03
00130 #define MACPANID0_MSB       0x04
00131 #define MACSHORTADDRS0_LSB  0x05
00132 #define MACSHORTADDRS0_MSB  0x06
00133 #define MACLONGADDRS0_0     0x07
00134 #define MACLONGADDRS0_8     0x08
00135 #define MACLONGADDRS0_16    0x09
00136 #define MACLONGADDRS0_24    0x0A
00137 #define MACLONGADDRS0_32    0x0B
00138 #define MACLONGADDRS0_40    0x0C
00139 #define MACLONGADDRS0_48    0x0D
00140 #define MACLONGADDRS0_56    0x0E
00141 #define RX_FRAME_FILTER     0x0F
00142 #define PLL_INT1            0x10
00143 #define PLL_FRAC1_LSB       0x11
00144 #define PLL_FRAC1_MSB       0x12
00145 #define MACPANID1_LSB       0x13
00146 #define MACPANID1_MSB       0x14
00147 #define MACSHORTADDRS1_LSB  0x15
00148 #define MACSHORTADDRS1_MSB  0x16
00149 #define MACLONGADDRS1_0     0x17
00150 #define MACLONGADDRS1_8     0x18
00151 #define MACLONGADDRS1_16    0x19
00152 #define MACLONGADDRS1_24    0x1A
00153 #define MACLONGADDRS1_32    0x1B
00154 #define MACLONGADDRS1_40    0x1C
00155 #define MACLONGADDRS1_48    0x1D
00156 #define MACLONGADDRS1_56    0x1E
00157 #define DUAL_PAN_CTRL       0x1F
00158 #define DUAL_PAN_DWELL      0x20
00159 #define DUAL_PAN_STS        0x21
00160 #define CCA1_THRESH         0x22
00161 #define CCA1_ED_OFFSET_COMP 0x23
00162 #define LQI_OFFSET_COMP     0x24
00163 #define CCA_CTRL            0x25
00164 #define CCA2_CORR_PEAKS     0x26
00165 #define CCA2_CORR_THRESH    0x27
00166 #define TMR_PRESCALE        0x28
00167 //----------------          0x29
00168 #define GPIO_DATA           0x2A
00169 #define GPIO_DIR            0x2B
00170 #define GPIO_PUL_EN         0x2C
00171 #define GPIO_PUL_SEL        0x2D
00172 #define GPIO_DS             0x2E
00173 //--------------            0x2F
00174 #define ANT_PAD_CTRL        0x30
00175 #define MISC_PAD_CTRL       0x31
00176 #define BSM_CTRL            0x32
00177 //---------------           0x33
00178 #define _RNG                0x34
00179 #define RX_BYTE_COUNT       0x35
00180 #define RX_WTR_MARK         0x36
00181 #define SOFT_RESET          0x37
00182 #define TXDELAY             0x38
00183 #define ACKDELAY            0x39
00184 #define SEQ_MGR_CTRL        0x3A
00185 #define SEQ_MGR_STS         0x3B
00186 #define SEQ_T_STS           0x3C
00187 #define ABORT_STS           0x3D
00188 #define CCCA_BUSY_CNT       0x3E
00189 #define SRC_ADDR_CHECKSUM1  0x3F
00190 #define SRC_ADDR_CHECKSUM2  0x40
00191 #define SRC_TBL_VALID1      0x41
00192 #define SRC_TBL_VALID2      0x42
00193 #define FILTERFAIL_CODE1    0x43
00194 #define FILTERFAIL_CODE2    0x44
00195 #define SLOT_PRELOAD        0x45
00196 //----------------          0x46
00197 #define CORR_VT             0x47
00198 #define SYNC_CTRL           0x48
00199 #define PN_LSB_0            0x49
00200 #define PN_LSB_1            0x4A
00201 #define PN_MSB_0            0x4B
00202 #define PN_MSB_1            0x4C
00203 #define CORR_NVAL           0x4D
00204 #define TX_MODE_CTRL        0x4E
00205 #define SNF_THR             0x4F
00206 #define FAD_THR             0x50
00207 #define ANT_AGC_CTRL        0x51
00208 #define AGC_THR1            0x52
00209 #define AGC_THR2            0x53
00210 #define AGC_HYS             0x54
00211 #define AFC                 0x55
00212 //---------------           0x56
00213 //---------------           0x57
00214 #define PHY_STS             0x58
00215 #define RX_MAX_CORR         0x59
00216 #define RX_MAX_PREAMBLE     0x5A
00217 #define RSSI                0x5B
00218 //---------------           0x5C
00219 //---------------           0x5D
00220 #define PLL_DIG_CTRL        0x5E
00221 #define VCO_CAL             0x5F
00222 #define VCO_BEST_DIFF       0x60
00223 #define VCO_BIAS            0x61
00224 #define KMOD_CTRL           0x62
00225 #define KMOD_CAL            0x63
00226 #define PA_CAL              0x64
00227 #define PA_PWRCAL           0x65
00228 #define ATT_RSSI1           0x66
00229 #define ATT_RSSI2           0x67
00230 #define RSSI_OFFSET         0x68
00231 #define RSSI_SLOPE          0x69
00232 #define RSSI_CAL1           0x6A
00233 #define RSSI_CAL2           0x6B
00234 //---------------           0x6C
00235 //---------------           0x6D
00236 #define XTAL_CTRL           0x6E
00237 #define XTAL_COMP_MIN       0x6F
00238 #define XTAL_COMP_MAX       0x70
00239 #define XTAL_GM             0x71
00240 //---------------           0x72
00241 //---------------           0x73
00242 #define LNA_TUNE            0x74
00243 #define LNA_AGCGAIN         0x75
00244 //---------------           0x76
00245 //---------------           0x77
00246 #define CHF_PMA_GAIN        0x78
00247 #define CHF_IBUF            0x79
00248 #define CHF_QBUF            0x7A
00249 #define CHF_IRIN            0x7B
00250 #define CHF_QRIN            0x7C
00251 #define CHF_IL              0x7D
00252 #define CHF_QL              0x7E
00253 #define CHF_CC1             0x7F
00254 #define CHF_CCL             0x80
00255 #define CHF_CC2             0x81
00256 #define CHF_IROUT           0x82
00257 #define CHF_QROUT           0x83
00258 //---------------           0x84
00259 //---------------           0x85
00260 #define RSSI_CTRL           0x86
00261 //---------------           0x87
00262 //---------------           0x88
00263 #define PA_BIAS             0x89
00264 #define PA_TUNING           0x8A
00265 //---------------           0x8B
00266 //---------------           0x8C
00267 #define PMC_HP_TRIM         0x8D
00268 #define VREGA_TRIM          0x8E
00269 //---------------           0x8F
00270 //---------------           0x90
00271 #define VCO_CTRL1           0x91
00272 #define VCO_CTRL2           0x92
00273 //---------------           0x93
00274 //---------------           0x94
00275 #define ANA_SPARE_OUT1      0x95
00276 #define ANA_SPARE_OUT2      0x96
00277 #define ANA_SPARE_IN        0x97
00278 #define MISCELLANEOUS       0x98
00279 //---------------           0x99
00280 #define SEQ_MGR_OVRD0       0x9A
00281 #define SEQ_MGR_OVRD1       0x9B
00282 #define SEQ_MGR_OVRD2       0x9C
00283 #define SEQ_MGR_OVRD3       0x9D
00284 #define SEQ_MGR_OVRD4       0x9E
00285 #define SEQ_MGR_OVRD5       0x9F
00286 #define SEQ_MGR_OVRD6       0xA0
00287 #define SEQ_MGR_OVRD7       0xA1
00288 //---------------           0xA2
00289 #define TESTMODE_CTRL       0xA3
00290 #define DTM_CTRL1           0xA4
00291 #define DTM_CTRL2           0xA5
00292 #define ATM_CTRL1           0xA6
00293 #define ATM_CTRL2           0xA7
00294 #define ATM_CTRL3           0xA8
00295 //---------------           0xA9
00296 #define LIM_FE_TEST_CTRL    0xAA
00297 #define CHF_TEST_CTRL       0xAB
00298 #define VCO_TEST_CTRL       0xAC
00299 #define PLL_TEST_CTRL       0xAD
00300 #define PA_TEST_CTRL        0xAE
00301 #define PMC_TEST_CTRL       0xAF
00302 #define SCAN_DTM_PROTECT_1  0xFE
00303 #define SCAN_DTM_PROTECT_0  0xFF
00304 
00305 // IRQSTS1 bits
00306 #define cIRQSTS1_RX_FRM_PEND         (1<<7)
00307 #define cIRQSTS1_PLL_UNLOCK_IRQ      (1<<6)
00308 #define cIRQSTS1_FILTERFAIL_IRQ      (1<<5)
00309 #define cIRQSTS1_RXWTRMRKIRQ         (1<<4)
00310 #define cIRQSTS1_CCAIRQ              (1<<3)
00311 #define cIRQSTS1_RXIRQ               (1<<2)
00312 #define cIRQSTS1_TXIRQ               (1<<1)
00313 #define cIRQSTS1_SEQIRQ              (1<<0)
00314 
00315 typedef union regIRQSTS1_tag{
00316   uint8_t byte;
00317   struct{
00318     uint8_t SEQIRQ:1;
00319     uint8_t TXIRQ:1;
00320     uint8_t RXIRQ:1;
00321     uint8_t CCAIRQ:1;
00322     uint8_t RXWTRMRKIRQ:1;
00323     uint8_t FILTERFAIL_IRQ:1;
00324     uint8_t PLL_UNLOCK_IRQ:1;
00325     uint8_t RX_FRM_PEND:1;
00326   }bit;
00327 } regIRQSTS1_t;
00328 
00329 // IRQSTS2 bits
00330 #define cIRQSTS2_CRCVALID            (1<<7)
00331 #define cIRQSTS2_CCA                 (1<<6)
00332 #define cIRQSTS2_SRCADDR             (1<<5)
00333 #define cIRQSTS2_PI                  (1<<4)
00334 #define cIRQSTS2_TMRSTATUS           (1<<3)
00335 #define cIRQSTS2_ASM_IRQ             (1<<2)
00336 #define cIRQSTS2_PB_ERR_IRQ          (1<<1)
00337 #define cIRQSTS2_WAKE_IRQ            (1<<0)
00338 
00339 typedef union regIRQSTS2_tag{
00340   uint8_t byte;
00341   struct{
00342     uint8_t WAKE_IRQ:1;
00343     uint8_t PB_ERR_IRQ:1;
00344     uint8_t ASM_IRQ:1;
00345     uint8_t TMRSTATUS:1;
00346     uint8_t PI:1;
00347     uint8_t SRCADDR:1;
00348     uint8_t CCA:1;
00349     uint8_t CRCVALID:1;
00350   }bit;
00351 } regIRQSTS2_t;
00352 
00353 // IRQSTS3 bits
00354 #define cIRQSTS3_TMR4MSK             (1<<7)
00355 #define cIRQSTS3_TMR3MSK             (1<<6)
00356 #define cIRQSTS3_TMR2MSK             (1<<5)
00357 #define cIRQSTS3_TMR1MSK             (1<<4)
00358 #define cIRQSTS3_TMR4IRQ             (1<<3)
00359 #define cIRQSTS3_TMR3IRQ             (1<<2)
00360 #define cIRQSTS3_TMR2IRQ             (1<<1)
00361 #define cIRQSTS3_TMR1IRQ             (1<<0)
00362 
00363 typedef union regIRQSTS3_tag{
00364   uint8_t byte;
00365   struct{
00366     uint8_t TMR1IRQ:1;
00367     uint8_t TMR2IRQ:1;
00368     uint8_t TMR3IRQ:1;
00369     uint8_t TMR4IRQ:1;
00370     uint8_t TMR1MSK:1;
00371     uint8_t TMR2MSK:1;
00372     uint8_t TMR3MSK:1;
00373     uint8_t TMR4MSK:1;
00374   }bit;
00375 } regIRQSTS3_t;
00376 
00377 // PHY_CTRL1 bits
00378 #define cPHY_CTRL1_TMRTRIGEN           (1<<7)
00379 #define cPHY_CTRL1_SLOTTED             (1<<6)
00380 #define cPHY_CTRL1_CCABFRTX            (1<<5)
00381 #define cPHY_CTRL1_RXACKRQD            (1<<4)
00382 #define cPHY_CTRL1_AUTOACK             (1<<3)
00383 #define cPHY_CTRL1_XCVSEQ              (7<<0)
00384 
00385 typedef union regPHY_CTRL1_tag{
00386   uint8_t byte;
00387   struct{
00388     uint8_t XCVSEQ:3;
00389     uint8_t AUTOACK:1;
00390     uint8_t RXACKRQD:1;
00391     uint8_t CCABFRTX:1;
00392     uint8_t SLOTTED:1;
00393     uint8_t TMRTRIGEN:1;
00394   }bit;
00395 } regPHY_CTRL1_t; 
00396 
00397 // PHY_CTRL2 bits
00398 #define cPHY_CTRL2_CRC_MSK             (1<<7)
00399 #define cPHY_CTRL2_PLL_UNLOCK_MSK      (1<<6)
00400 #define cPHY_CTRL2_FILTERFAIL_MSK      (1<<5)
00401 #define cPHY_CTRL2_RX_WMRK_MSK         (1<<4)
00402 #define cPHY_CTRL2_CCAMSK              (1<<3)
00403 #define cPHY_CTRL2_RXMSK               (1<<2)
00404 #define cPHY_CTRL2_TXMSK               (1<<1)
00405 #define cPHY_CTRL2_SEQMSK              (1<<0)
00406 
00407 typedef union regPHY_CTRL2_tag{
00408   uint8_t byte;
00409   struct{
00410     uint8_t SEQMSK:1;
00411     uint8_t TXMSK:1;
00412     uint8_t RXMSK:1;
00413     uint8_t CCAMSK:1;
00414     uint8_t RX_WMRK_MSK:1;
00415     uint8_t FILTERFAIL_MSK:1;
00416     uint8_t PLL_UNLOCK_MSK:1;
00417     uint8_t CRC_MSK:1;
00418   }bit;
00419 } regPHY_CTRL2_t; 
00420 
00421 // PHY_CTRL3 bits
00422 #define cPHY_CTRL3_TMR4CMP_EN          (1<<7)
00423 #define cPHY_CTRL3_TMR3CMP_EN          (1<<6)
00424 #define cPHY_CTRL3_TMR2CMP_EN          (1<<5)
00425 #define cPHY_CTRL3_TMR1CMP_EN          (1<<4)
00426 #define cPHY_CTRL3_ASM_MSK             (1<<2)
00427 #define cPHY_CTRL3_PB_ERR_MSK          (1<<1)
00428 #define cPHY_CTRL3_WAKE_MSK            (1<<0)
00429 
00430 typedef union regPHY_CTRL3_tag{
00431   uint8_t byte;
00432   struct{
00433     uint8_t WAKE_MSK:1;
00434     uint8_t PB_ERR_MSK:1;
00435     uint8_t ASM_MSK:1;
00436     uint8_t RESERVED:1;
00437     uint8_t TMR1CMP_EN:1;
00438     uint8_t TMR2CMP_EN:1;
00439     uint8_t TMR3CMP_EN:1;
00440     uint8_t TMR4CMP_EN:1;
00441   }bit;
00442 } regPHY_CTRL3_t;
00443 
00444 // RX_FRM_LEN bits
00445 #define cRX_FRAME_LENGTH               (0x7F)
00446 
00447 // PHY_CTRL4 bits
00448 #define cPHY_CTRL4_TRCV_MSK            (1<<7)
00449 #define cPHY_CTRL4_TC3TMOUT            (1<<6)
00450 #define cPHY_CTRL4_PANCORDNTR0         (1<<5)
00451 #define cPHY_CTRL4_CCATYPE             (3<<0)
00452 #define cPHY_CTRL4_CCATYPE_Shift_c     (3)
00453 #define cPHY_CTRL4_TMRLOAD             (1<<2)
00454 #define cPHY_CTRL4_PROMISCUOUS         (1<<1)
00455 #define cPHY_CTRL4_TC2PRIME_EN         (1<<0)
00456 
00457 typedef union regPHY_CTRL4_tag{
00458   uint8_t byte;
00459   struct{
00460     uint8_t TC2PRIME_EN:1;
00461     uint8_t PROMISCUOUS:1;
00462     uint8_t TMRLOAD:1;
00463     uint8_t CCATYPE:2;
00464     uint8_t PANCORDNTR0:1;
00465     uint8_t TC3TMOUT:1;
00466     uint8_t TRCV_MSK:1;
00467   }bit;
00468 } regPHY_CTRL4_t;
00469 
00470 // SRC_CTRL bits
00471 #define cSRC_CTRL_INDEX               (0x0F)
00472 #define cSRC_CTRL_INDEX_Shift_c       (4)
00473 #define cSRC_CTRL_ACK_FRM_PND         (1<<3)
00474 #define cSRC_CTRL_SRCADDR_EN          (1<<2)
00475 #define cSRC_CTRL_INDEX_EN            (1<<1)
00476 #define cSRC_CTRL_INDEX_DISABLE       (1<<0)
00477 
00478 typedef union regSRC_CTRL_tag{
00479   uint8_t byte;
00480   struct{
00481     uint8_t INDEX_DISABLE:1;
00482     uint8_t INDEX_EN:1;
00483     uint8_t SRCADDR_EN:1;
00484     uint8_t ACK_FRM_PND:1;
00485     uint8_t INDEX:4;
00486   }bit;
00487 } regSRC_CTRL_t;
00488 
00489 // ASM_CTRL1 bits
00490 #define cASM_CTRL1_CLEAR               (1<<7)
00491 #define cASM_CTRL1_START               (1<<6)
00492 #define cASM_CTRL1_SELFTST             (1<<5)
00493 #define cASM_CTRL1_CTR                 (1<<4)
00494 #define cASM_CTRL1_CBC                 (1<<3)
00495 #define cASM_CTRL1_AES                 (1<<2)
00496 #define cASM_CTRL1_LOAD_MAC            (1<<1)
00497 
00498 // ASM_CTRL2 bits
00499 #define cASM_CTRL2_DATA_REG_TYPE_SEL          (7)
00500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c  (5)
00501 #define cASM_CTRL2_TSTPAS                     (1<<1)
00502 
00503 // CLK_OUT_CTRL bits
00504 #define cCLK_OUT_CTRL_EXTEND           (1<<7)
00505 #define cCLK_OUT_CTRL_HIZ              (1<<6)
00506 #define cCLK_OUT_CTRL_SR               (1<<5)
00507 #define cCLK_OUT_CTRL_DS               (1<<4)
00508 #define cCLK_OUT_CTRL_EN               (1<<3)
00509 #define cCLK_OUT_CTRL_DIV              (7)
00510 
00511 // PWR_MODES bits
00512 #define cPWR_MODES_XTAL_READY          (1<<5)
00513 #define cPWR_MODES_XTALEN              (1<<4)
00514 #define cPWR_MODES_ASM_CLK_EN          (1<<3)
00515 #define cPWR_MODES_AUTODOZE            (1<<1)
00516 #define cPWR_MODES_PMC_MODE            (1<<0)
00517 
00518 // RX_FRAME_FILTER bits
00519 #define cRX_FRAME_FLT_FRM_VER             (0xC0)
00520 #define cRX_FRAME_FLT_FRM_VER_Shift_c     (6)
00521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS  (1<<5)
00522 #define cRX_FRAME_FLT_NS_FT               (1<<4)
00523 #define cRX_FRAME_FLT_CMD_FT              (1<<3)
00524 #define cRX_FRAME_FLT_ACK_FT              (1<<2)
00525 #define cRX_FRAME_FLT_DATA_FT             (1<<1)
00526 #define cRX_FRAME_FLT_BEACON_FT           (1<<0)
00527 
00528 typedef union regRX_FRAME_FILTER_tag{
00529   uint8_t byte;
00530   struct{
00531     uint8_t FRAME_FLT_BEACON_FT:1;
00532     uint8_t FRAME_FLT_DATA_FT:1;
00533     uint8_t FRAME_FLT_ACK_FT:1;
00534     uint8_t FRAME_FLT_CMD_FT:1;
00535     uint8_t FRAME_FLT_NS_FT:1;
00536     uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
00537     uint8_t FRAME_FLT_FRM_VER:2;
00538   }bit;
00539 } regRX_FRAME_FILTER_t; 
00540 
00541 // DUAL_PAN_CTRL bits
00542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK       (0xF0)
00543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c   (4)
00544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK            (1<<3)
00545 #define cDUAL_PAN_CTRL_PANCORDNTR1                (1<<2)
00546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO              (1<<1)
00547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK             (1<<0)
00548 
00549 // DUAL_PAN_STS bits
00550 #define cDUAL_PAN_STS_RECD_ON_PAN1        (1<<7)
00551 #define cDUAL_PAN_STS_RECD_ON_PAN0        (1<<6)
00552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN     (0x3F)
00553 
00554 // CCA_CTRL bits
00555 #define cCCA_CTRL_AGC_FRZ_EN          (1<<6)
00556 #define cCCA_CTRL_CONT_RSSI_EN        (1<<5)
00557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR   (1<<4)
00558 #define cCCA_CTRL_CCA3_AND_NOT_OR     (1<<3)
00559 #define cCCA_CTRL_POWER_COMP_EN_LQI   (1<<2)
00560 #define cCCA_CTRL_POWER_COMP_EN_ED    (1<<1)
00561 #define cCCA_CTRL_POWER_COMP_EN_CCA1  (1<<0)
00562 
00563 // GPIO_DATA bits
00564 #define cGPIO_DATA_7        (1<<7)
00565 #define cGPIO_DATA_6        (1<<6)
00566 #define cGPIO_DATA_5        (1<<5)
00567 #define cGPIO_DATA_4        (1<<4)
00568 #define cGPIO_DATA_3        (1<<3)
00569 #define cGPIO_DATA_2        (1<<2)
00570 #define cGPIO_DATA_1        (1<<1)
00571 #define cGPIO_DATA_0        (1<<0)
00572 
00573 // GPIO_DIR bits
00574 #define cGPIO_DIR_7         (1<<7)
00575 #define cGPIO_DIR_6         (1<<6)
00576 #define cGPIO_DIR_5         (1<<5)
00577 #define cGPIO_DIR_4         (1<<4)
00578 #define cGPIO_DIR_3         (1<<3)
00579 #define cGPIO_DIR_2         (1<<2)
00580 #define cGPIO_DIR_1         (1<<1)
00581 #define cGPIO_DIR_0         (1<<0)
00582 
00583 // GPIO_PUL_EN bits
00584 #define cGPIO_PUL_EN_7      (1<<7)
00585 #define cGPIO_PUL_EN_6      (1<<6)
00586 #define cGPIO_PUL_EN_5      (1<<5)
00587 #define cGPIO_PUL_EN_4      (1<<4)
00588 #define cGPIO_PUL_EN_3      (1<<3)
00589 #define cGPIO_PUL_EN_2      (1<<2)
00590 #define cGPIO_PUL_EN_1      (1<<1)
00591 #define cGPIO_PUL_EN_0      (1<<0)
00592 
00593 // GPIO_PUL_SEL bits
00594 #define cGPIO_PUL_SEL_7     (1<<7)
00595 #define cGPIO_PUL_SEL_6     (1<<6)
00596 #define cGPIO_PUL_SEL_5     (1<<5)
00597 #define cGPIO_PUL_SEL_4     (1<<4)
00598 #define cGPIO_PUL_SEL_3     (1<<3)
00599 #define cGPIO_PUL_SEL_2     (1<<2)
00600 #define cGPIO_PUL_SEL_1     (1<<1)
00601 #define cGPIO_PUL_SEL_0     (1<<0)
00602 
00603 // GPIO_DS bits
00604 #define cGPIO_DS_7          (1<<7)
00605 #define cGPIO_DS_6          (1<<6)
00606 #define cGPIO_DS_5          (1<<5)
00607 #define cGPIO_DS_4          (1<<4)
00608 #define cGPIO_DS_3          (1<<3)
00609 #define cGPIO_DS_2          (1<<2)
00610 #define cGPIO_DS_1          (1<<1)
00611 #define cGPIO_DS_0          (1<<0)
00612 
00613 // SPI_CTRL bits
00614 //#define cSPI_CTRL_MISO_HIZ_EN        (1<<1)
00615 //#define cSPI_CTRL_PB_PROTECT         (1<<0)
00616 
00617 // ANT_PAD_CTRL bits
00618 #define cANT_PAD_CTRL_ANTX_POL           (0x0F)
00619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c   (4)
00620 #define cANT_PAD_CTRL_ANTX_CTRLMODE      (1<<3)
00621 #define cANT_PAD_CTRL_ANTX_HZ            (1<<2)
00622 #define cANT_PAD_CTRL_ANTX_EN            (3)
00623 
00624 // MISC_PAD_CTRL bits
00625 #define cMISC_PAD_CTRL_MISO_HIZ_EN        (1<<3)
00626 #define cMISC_PAD_CTRL_IRQ_B_OD           (1<<2)
00627 #define cMISC_PAD_CTRL_NON_GPIO_DS        (1<<1)
00628 #define cMISC_PAD_CTRL_ANTX_CURR          (1<<0)
00629 
00630 // ANT_AGC_CTRL bits
00631 #define cANT_AGC_CTRL_FAD_EN_Shift_c    (0)
00632 #define cANT_AGC_CTRL_FAD_EN_Mask_c     (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
00633 #define cANT_AGC_CTRL_ANTX_Shift_c      (1)
00634 #define cANT_AGC_CTRL_ANTX_Mask_c       (1<<cANT_AGC_CTRL_ANTX_Shift_c)
00635 
00636 // BSM_CTRL bits
00637 #define cBSM_CTRL_BSM_EN                  (1<<0)
00638 
00639 // SOFT_RESET bits
00640 #define cSOFT_RESET_SOG_RST            (1<<7)
00641 #define cSOFT_RESET_REGS_RST           (1<<4)
00642 #define cSOFT_RESET_PLL_RST            (1<<3)
00643 #define cSOFT_RESET_TX_RST             (1<<2)
00644 #define cSOFT_RESET_RX_RST             (1<<1)
00645 #define cSOFT_RESET_SEQ_MGR_RST        (1<<0)
00646 
00647 // SEQ_MGR_CTRL bits
00648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL          (3)
00649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c  (6)
00650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE           (1<<5)
00651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE          (1<<4)
00652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH  (1<<3)
00653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT     (1<<2)
00654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS            (1<<1)
00655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD          (1<<0)
00656 
00657 // SEQ_MGR_STS bits
00658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
00659 #define cSEQ_MGR_STS_RX_MODE             (1<<6)
00660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING  (1<<5)
00661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT     (1<<4)
00662 #define cSEQ_MGR_STS_SEQ_IDLE            (1<<3)
00663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL       (7)
00664 
00665 // ABORT_STS bits
00666 #define cABORT_STS_PLL_ABORTED        (1<<2)
00667 #define cABORT_STS_TC3_ABORTED        (1<<1)
00668 #define cABORT_STS_SW_ABORTED         (1<<0)
00669 
00670 // FILTERFAIL_CODE2 bits
00671 #define cFILTERFAIL_CODE2_PAN_SEL  (1<<7)
00672 #define cFILTERFAIL_CODE2_9_8      (3)
00673 
00674 // PHY_STS bits
00675 #define cPHY_STS_PLL_UNLOCK  (1<<7)
00676 #define cPHY_STS_PLL_LOCK_ERR        (1<<6)
00677 #define cPHY_STS_PLL_LOCK            (1<<5)
00678 #define cPHY_STS_CRCVALID            (1<<3)
00679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
00680 #define cPHY_STS_SFD_DET             (1<<1)
00681 #define cPHY_STS_PREAMBLE_DET        (1<<0)
00682 
00683 // TESTMODE_CTRL bits
00684 #define cTEST_MODE_CTRL_HOT_ANT            (1<<4)
00685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN      (1<<3)
00686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN       (1<<2)
00687 #define cTEST_MODE_CTRL_CONTINUOUS_EN      (1<<1)
00688 #define cTEST_MODE_CTRL_FPGA_EN            (1<<0)
00689 
00690 // DTM_CTRL1 bits
00691 #define cDTM_CTRL1_ATM_LOCKED  (1<<7)
00692 #define cDTM_CTRL1_DTM_EN      (1<<6)
00693 #define cDTM_CTRL1_PAGE5       (1<<5)
00694 #define cDTM_CTRL1_PAGE4       (1<<4)
00695 #define cDTM_CTRL1_PAGE3       (1<<3)
00696 #define cDTM_CTRL1_PAGE2       (1<<2)
00697 #define cDTM_CTRL1_PAGE1       (1<<1)
00698 #define cDTM_CTRL1_PAGE0       (1<<0)
00699 
00700 // TX_MODE_CTRL
00701 #define cTX_MODE_CTRL_TX_INV   (1<<4)
00702 #define cTX_MODE_CTRL_BT_EN    (1<<3)
00703 #define cTX_MODE_CTRL_DTS2     (1<<2)
00704 #define cTX_MODE_CTRL_DTS1     (1<<1)
00705 #define cTX_MODE_CTRL_DTS0     (1<<0)
00706 
00707 #define cTX_MODE_CTRL_DTS_MASK (7)
00708 
00709 // CLK_OUT_CTRL bits
00710 #define cCLK_OUT_EXTEND        (1<<7)
00711 #define cCLK_OUT_HIZ           (1<<6)
00712 #define cCLK_OUT_SR            (1<<5)
00713 #define cCLK_OUT_DS            (1<<4)
00714 #define cCLK_OUT_EN            (1<<3)
00715 #define cCLK_OUT_DIV_Mask      (7<<0)
00716 
00717 #define gCLK_OUT_FREQ_32_MHz      (0)
00718 #define gCLK_OUT_FREQ_16_MHz      (1)
00719 #define gCLK_OUT_FREQ_8_MHz       (2)
00720 #define gCLK_OUT_FREQ_4_MHz       (3)
00721 #define gCLK_OUT_FREQ_1_MHz       (4)
00722 #define gCLK_OUT_FREQ_250_KHz     (5)
00723 #define gCLK_OUT_FREQ_62_5_KHz    (6)
00724 #define gCLK_OUT_FREQ_32_78_KHz   (7)
00725 #define gCLK_OUT_FREQ_DISABLE     (8)
00726 
00727 
00728 
00729 
00730 #endif /* __MCR20_REG_H__ */