MK64F12_wdog.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_WDOG_REGISTERS_H__
00081 #define __HW_WDOG_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 WDOG
00088  *
00089  * Generation 2008 Watchdog Timer
00090  *
00091  * Registers defined in this header file:
00092  * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
00093  * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
00094  * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
00095  * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
00096  * - HW_WDOG_WINH - Watchdog Window Register High
00097  * - HW_WDOG_WINL - Watchdog Window Register Low
00098  * - HW_WDOG_REFRESH - Watchdog Refresh register
00099  * - HW_WDOG_UNLOCK - Watchdog Unlock register
00100  * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
00101  * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
00102  * - HW_WDOG_RSTCNT - Watchdog Reset Count register
00103  * - HW_WDOG_PRESC - Watchdog Prescaler register
00104  *
00105  * - hw_wdog_t - Struct containing all module registers.
00106  */
00107 
00108 #define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
00109 
00110 /*******************************************************************************
00111  * HW_WDOG_STCTRLH - Watchdog Status and Control Register High
00112  ******************************************************************************/
00113 
00114 /*!
00115  * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
00116  *
00117  * Reset value: 0x01D3U
00118  */
00119 typedef union _hw_wdog_stctrlh
00120 {
00121     uint16_t U;
00122     struct _hw_wdog_stctrlh_bitfields
00123     {
00124         uint16_t WDOGEN : 1;           /*!< [0]  */
00125         uint16_t CLKSRC : 1;           /*!< [1]  */
00126         uint16_t IRQRSTEN : 1;         /*!< [2]  */
00127         uint16_t WINEN : 1;            /*!< [3]  */
00128         uint16_t ALLOWUPDATE : 1;      /*!< [4]  */
00129         uint16_t DBGEN : 1;            /*!< [5]  */
00130         uint16_t STOPEN : 1;           /*!< [6]  */
00131         uint16_t WAITEN : 1;           /*!< [7]  */
00132         uint16_t RESERVED0 : 2;        /*!< [9:8]  */
00133         uint16_t TESTWDOG : 1;         /*!< [10]  */
00134         uint16_t TESTSEL : 1;          /*!< [11]  */
00135         uint16_t BYTESEL : 2;          /*!< [13:12]  */
00136         uint16_t DISTESTWDOG : 1;      /*!< [14]  */
00137         uint16_t RESERVED1 : 1;        /*!< [15]  */
00138     } B;
00139 } hw_wdog_stctrlh_t;
00140 
00141 /*!
00142  * @name Constants and macros for entire WDOG_STCTRLH register
00143  */
00144 /*@{*/
00145 #define HW_WDOG_STCTRLH_ADDR(x)  ((x) + 0x0U)
00146 
00147 #define HW_WDOG_STCTRLH(x)       (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x))
00148 #define HW_WDOG_STCTRLH_RD(x)    (HW_WDOG_STCTRLH(x).U)
00149 #define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v))
00150 #define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) |  (v)))
00151 #define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v)))
00152 #define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^  (v)))
00153 /*@}*/
00154 
00155 /*
00156  * Constants & macros for individual WDOG_STCTRLH bitfields
00157  */
00158 
00159 /*!
00160  * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
00161  *
00162  * Enables or disables the WDOG's operation. In the disabled state, the watchdog
00163  * timer is kept in the reset state, but the other exception conditions can
00164  * still trigger a reset/interrupt. A change in the value of this bit must be held
00165  * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
00166  *
00167  * Values:
00168  * - 0 - WDOG is disabled.
00169  * - 1 - WDOG is enabled.
00170  */
00171 /*@{*/
00172 #define BP_WDOG_STCTRLH_WDOGEN (0U)        /*!< Bit position for WDOG_STCTRLH_WDOGEN. */
00173 #define BM_WDOG_STCTRLH_WDOGEN (0x0001U)   /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */
00174 #define BS_WDOG_STCTRLH_WDOGEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */
00175 
00176 /*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
00177 #define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN))
00178 
00179 /*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */
00180 #define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN)
00181 
00182 /*! @brief Set the WDOGEN field to a new value. */
00183 #define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v))
00184 /*@}*/
00185 
00186 /*!
00187  * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
00188  *
00189  * Selects clock source for the WDOG timer and other internal timing operations.
00190  *
00191  * Values:
00192  * - 0 - WDOG clock sourced from LPO .
00193  * - 1 - WDOG clock sourced from alternate clock source.
00194  */
00195 /*@{*/
00196 #define BP_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit position for WDOG_STCTRLH_CLKSRC. */
00197 #define BM_WDOG_STCTRLH_CLKSRC (0x0002U)   /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */
00198 #define BS_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */
00199 
00200 /*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
00201 #define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC))
00202 
00203 /*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */
00204 #define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC)
00205 
00206 /*! @brief Set the CLKSRC field to a new value. */
00207 #define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v))
00208 /*@}*/
00209 
00210 /*!
00211  * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
00212  *
00213  * Used to enable the debug breadcrumbs feature. A change in this bit is updated
00214  * immediately, as opposed to updating after WCT.
00215  *
00216  * Values:
00217  * - 0 - WDOG time-out generates reset only.
00218  * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
00219  *     a reset.
00220  */
00221 /*@{*/
00222 #define BP_WDOG_STCTRLH_IRQRSTEN (2U)      /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */
00223 #define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */
00224 #define BS_WDOG_STCTRLH_IRQRSTEN (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */
00225 
00226 /*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
00227 #define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN))
00228 
00229 /*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */
00230 #define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN)
00231 
00232 /*! @brief Set the IRQRSTEN field to a new value. */
00233 #define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v))
00234 /*@}*/
00235 
00236 /*!
00237  * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
00238  *
00239  * Enables Windowing mode.
00240  *
00241  * Values:
00242  * - 0 - Windowing mode is disabled.
00243  * - 1 - Windowing mode is enabled.
00244  */
00245 /*@{*/
00246 #define BP_WDOG_STCTRLH_WINEN (3U)         /*!< Bit position for WDOG_STCTRLH_WINEN. */
00247 #define BM_WDOG_STCTRLH_WINEN (0x0008U)    /*!< Bit mask for WDOG_STCTRLH_WINEN. */
00248 #define BS_WDOG_STCTRLH_WINEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */
00249 
00250 /*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
00251 #define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN))
00252 
00253 /*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */
00254 #define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN)
00255 
00256 /*! @brief Set the WINEN field to a new value. */
00257 #define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v))
00258 /*@}*/
00259 
00260 /*!
00261  * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
00262  *
00263  * Enables updates to watchdog write-once registers, after the reset-triggered
00264  * initial configuration window (WCT) closes, through unlock sequence.
00265  *
00266  * Values:
00267  * - 0 - No further updates allowed to WDOG write-once registers.
00268  * - 1 - WDOG write-once registers can be unlocked for updating.
00269  */
00270 /*@{*/
00271 #define BP_WDOG_STCTRLH_ALLOWUPDATE (4U)   /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */
00272 #define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */
00273 #define BS_WDOG_STCTRLH_ALLOWUPDATE (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */
00274 
00275 /*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
00276 #define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE))
00277 
00278 /*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */
00279 #define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE)
00280 
00281 /*! @brief Set the ALLOWUPDATE field to a new value. */
00282 #define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
00283 /*@}*/
00284 
00285 /*!
00286  * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
00287  *
00288  * Enables or disables WDOG in Debug mode.
00289  *
00290  * Values:
00291  * - 0 - WDOG is disabled in CPU Debug mode.
00292  * - 1 - WDOG is enabled in CPU Debug mode.
00293  */
00294 /*@{*/
00295 #define BP_WDOG_STCTRLH_DBGEN (5U)         /*!< Bit position for WDOG_STCTRLH_DBGEN. */
00296 #define BM_WDOG_STCTRLH_DBGEN (0x0020U)    /*!< Bit mask for WDOG_STCTRLH_DBGEN. */
00297 #define BS_WDOG_STCTRLH_DBGEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */
00298 
00299 /*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
00300 #define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN))
00301 
00302 /*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */
00303 #define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN)
00304 
00305 /*! @brief Set the DBGEN field to a new value. */
00306 #define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v))
00307 /*@}*/
00308 
00309 /*!
00310  * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
00311  *
00312  * Enables or disables WDOG in Stop mode.
00313  *
00314  * Values:
00315  * - 0 - WDOG is disabled in CPU Stop mode.
00316  * - 1 - WDOG is enabled in CPU Stop mode.
00317  */
00318 /*@{*/
00319 #define BP_WDOG_STCTRLH_STOPEN (6U)        /*!< Bit position for WDOG_STCTRLH_STOPEN. */
00320 #define BM_WDOG_STCTRLH_STOPEN (0x0040U)   /*!< Bit mask for WDOG_STCTRLH_STOPEN. */
00321 #define BS_WDOG_STCTRLH_STOPEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */
00322 
00323 /*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
00324 #define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN))
00325 
00326 /*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */
00327 #define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN)
00328 
00329 /*! @brief Set the STOPEN field to a new value. */
00330 #define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v))
00331 /*@}*/
00332 
00333 /*!
00334  * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
00335  *
00336  * Enables or disables WDOG in Wait mode.
00337  *
00338  * Values:
00339  * - 0 - WDOG is disabled in CPU Wait mode.
00340  * - 1 - WDOG is enabled in CPU Wait mode.
00341  */
00342 /*@{*/
00343 #define BP_WDOG_STCTRLH_WAITEN (7U)        /*!< Bit position for WDOG_STCTRLH_WAITEN. */
00344 #define BM_WDOG_STCTRLH_WAITEN (0x0080U)   /*!< Bit mask for WDOG_STCTRLH_WAITEN. */
00345 #define BS_WDOG_STCTRLH_WAITEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */
00346 
00347 /*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
00348 #define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN))
00349 
00350 /*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */
00351 #define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN)
00352 
00353 /*! @brief Set the WAITEN field to a new value. */
00354 #define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v))
00355 /*@}*/
00356 
00357 /*!
00358  * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
00359  *
00360  * Puts the watchdog in the functional test mode. In this mode, the watchdog
00361  * timer and the associated compare and reset generation logic is tested for correct
00362  * operation. The clock for the timer is switched from the main watchdog clock
00363  * to the fast clock input for watchdog functional test. The TESTSEL bit selects
00364  * the test to be run.
00365  */
00366 /*@{*/
00367 #define BP_WDOG_STCTRLH_TESTWDOG (10U)     /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */
00368 #define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */
00369 #define BS_WDOG_STCTRLH_TESTWDOG (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */
00370 
00371 /*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
00372 #define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG))
00373 
00374 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */
00375 #define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG)
00376 
00377 /*! @brief Set the TESTWDOG field to a new value. */
00378 #define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v))
00379 /*@}*/
00380 
00381 /*!
00382  * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
00383  *
00384  * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
00385  * timer.
00386  *
00387  * Values:
00388  * - 0 - Quick test. The timer runs in normal operation. You can load a small
00389  *     time-out value to do a quick test.
00390  * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
00391  *     of the timer are enabled for operation and are compared for time-out
00392  *     against the corresponding byte of the programmed time-out value. Select the
00393  *     byte through BYTESEL[1:0] for testing.
00394  */
00395 /*@{*/
00396 #define BP_WDOG_STCTRLH_TESTSEL (11U)      /*!< Bit position for WDOG_STCTRLH_TESTSEL. */
00397 #define BM_WDOG_STCTRLH_TESTSEL (0x0800U)  /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */
00398 #define BS_WDOG_STCTRLH_TESTSEL (1U)       /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */
00399 
00400 /*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
00401 #define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL))
00402 
00403 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */
00404 #define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL)
00405 
00406 /*! @brief Set the TESTSEL field to a new value. */
00407 #define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v))
00408 /*@}*/
00409 
00410 /*!
00411  * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
00412  *
00413  * This 2-bit field selects the byte to be tested when the watchdog is in the
00414  * byte test mode.
00415  *
00416  * Values:
00417  * - 00 - Byte 0 selected
00418  * - 01 - Byte 1 selected
00419  * - 10 - Byte 2 selected
00420  * - 11 - Byte 3 selected
00421  */
00422 /*@{*/
00423 #define BP_WDOG_STCTRLH_BYTESEL (12U)      /*!< Bit position for WDOG_STCTRLH_BYTESEL. */
00424 #define BM_WDOG_STCTRLH_BYTESEL (0x3000U)  /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */
00425 #define BS_WDOG_STCTRLH_BYTESEL (2U)       /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */
00426 
00427 /*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
00428 #define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL)
00429 
00430 /*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */
00431 #define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL)
00432 
00433 /*! @brief Set the BYTESEL field to a new value. */
00434 #define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
00435 /*@}*/
00436 
00437 /*!
00438  * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
00439  *
00440  * Allows the WDOG's functional test mode to be disabled permanently. After it
00441  * is set, it can only be cleared by a reset. It cannot be unlocked for editing
00442  * after it is set.
00443  *
00444  * Values:
00445  * - 0 - WDOG functional test mode is not disabled.
00446  * - 1 - WDOG functional test mode is disabled permanently until reset.
00447  */
00448 /*@{*/
00449 #define BP_WDOG_STCTRLH_DISTESTWDOG (14U)  /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */
00450 #define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */
00451 #define BS_WDOG_STCTRLH_DISTESTWDOG (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */
00452 
00453 /*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
00454 #define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG))
00455 
00456 /*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */
00457 #define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG)
00458 
00459 /*! @brief Set the DISTESTWDOG field to a new value. */
00460 #define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
00461 /*@}*/
00462 
00463 /*******************************************************************************
00464  * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
00465  ******************************************************************************/
00466 
00467 /*!
00468  * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
00469  *
00470  * Reset value: 0x0001U
00471  */
00472 typedef union _hw_wdog_stctrll
00473 {
00474     uint16_t U;
00475     struct _hw_wdog_stctrll_bitfields
00476     {
00477         uint16_t RESERVED0 : 15;       /*!< [14:0]  */
00478         uint16_t INTFLG : 1;           /*!< [15]  */
00479     } B;
00480 } hw_wdog_stctrll_t;
00481 
00482 /*!
00483  * @name Constants and macros for entire WDOG_STCTRLL register
00484  */
00485 /*@{*/
00486 #define HW_WDOG_STCTRLL_ADDR(x)  ((x) + 0x2U)
00487 
00488 #define HW_WDOG_STCTRLL(x)       (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x))
00489 #define HW_WDOG_STCTRLL_RD(x)    (HW_WDOG_STCTRLL(x).U)
00490 #define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v))
00491 #define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) |  (v)))
00492 #define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v)))
00493 #define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^  (v)))
00494 /*@}*/
00495 
00496 /*
00497  * Constants & macros for individual WDOG_STCTRLL bitfields
00498  */
00499 
00500 /*!
00501  * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
00502  *
00503  * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
00504  * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
00505  * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
00506  * bit. It also gets cleared on a system reset.
00507  */
00508 /*@{*/
00509 #define BP_WDOG_STCTRLL_INTFLG (15U)       /*!< Bit position for WDOG_STCTRLL_INTFLG. */
00510 #define BM_WDOG_STCTRLL_INTFLG (0x8000U)   /*!< Bit mask for WDOG_STCTRLL_INTFLG. */
00511 #define BS_WDOG_STCTRLL_INTFLG (1U)        /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */
00512 
00513 /*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
00514 #define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG))
00515 
00516 /*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */
00517 #define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG)
00518 
00519 /*! @brief Set the INTFLG field to a new value. */
00520 #define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v))
00521 /*@}*/
00522 
00523 /*******************************************************************************
00524  * HW_WDOG_TOVALH - Watchdog Time-out Value Register High
00525  ******************************************************************************/
00526 
00527 /*!
00528  * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
00529  *
00530  * Reset value: 0x004CU
00531  */
00532 typedef union _hw_wdog_tovalh
00533 {
00534     uint16_t U;
00535     struct _hw_wdog_tovalh_bitfields
00536     {
00537         uint16_t TOVALHIGH : 16;       /*!< [15:0]  */
00538     } B;
00539 } hw_wdog_tovalh_t;
00540 
00541 /*!
00542  * @name Constants and macros for entire WDOG_TOVALH register
00543  */
00544 /*@{*/
00545 #define HW_WDOG_TOVALH_ADDR(x)   ((x) + 0x4U)
00546 
00547 #define HW_WDOG_TOVALH(x)        (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x))
00548 #define HW_WDOG_TOVALH_RD(x)     (HW_WDOG_TOVALH(x).U)
00549 #define HW_WDOG_TOVALH_WR(x, v)  (HW_WDOG_TOVALH(x).U = (v))
00550 #define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) |  (v)))
00551 #define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v)))
00552 #define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^  (v)))
00553 /*@}*/
00554 
00555 /*
00556  * Constants & macros for individual WDOG_TOVALH bitfields
00557  */
00558 
00559 /*!
00560  * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
00561  *
00562  * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
00563  * timer. It is defined in terms of cycles of the watchdog clock.
00564  */
00565 /*@{*/
00566 #define BP_WDOG_TOVALH_TOVALHIGH (0U)      /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */
00567 #define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */
00568 #define BS_WDOG_TOVALH_TOVALHIGH (16U)     /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */
00569 
00570 /*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */
00571 #define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U)
00572 
00573 /*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */
00574 #define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH)
00575 
00576 /*! @brief Set the TOVALHIGH field to a new value. */
00577 #define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v))
00578 /*@}*/
00579 
00580 /*******************************************************************************
00581  * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
00582  ******************************************************************************/
00583 
00584 /*!
00585  * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
00586  *
00587  * Reset value: 0x4B4CU
00588  *
00589  * The time-out value of the watchdog must be set to a minimum of four watchdog
00590  * clock cycles. This is to take into account the delay in new settings taking
00591  * effect in the watchdog clock domain.
00592  */
00593 typedef union _hw_wdog_tovall
00594 {
00595     uint16_t U;
00596     struct _hw_wdog_tovall_bitfields
00597     {
00598         uint16_t TOVALLOW : 16;        /*!< [15:0]  */
00599     } B;
00600 } hw_wdog_tovall_t;
00601 
00602 /*!
00603  * @name Constants and macros for entire WDOG_TOVALL register
00604  */
00605 /*@{*/
00606 #define HW_WDOG_TOVALL_ADDR(x)   ((x) + 0x6U)
00607 
00608 #define HW_WDOG_TOVALL(x)        (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x))
00609 #define HW_WDOG_TOVALL_RD(x)     (HW_WDOG_TOVALL(x).U)
00610 #define HW_WDOG_TOVALL_WR(x, v)  (HW_WDOG_TOVALL(x).U = (v))
00611 #define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) |  (v)))
00612 #define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v)))
00613 #define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^  (v)))
00614 /*@}*/
00615 
00616 /*
00617  * Constants & macros for individual WDOG_TOVALL bitfields
00618  */
00619 
00620 /*!
00621  * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
00622  *
00623  * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
00624  * timer. It is defined in terms of cycles of the watchdog clock.
00625  */
00626 /*@{*/
00627 #define BP_WDOG_TOVALL_TOVALLOW (0U)       /*!< Bit position for WDOG_TOVALL_TOVALLOW. */
00628 #define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU)  /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */
00629 #define BS_WDOG_TOVALL_TOVALLOW (16U)      /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */
00630 
00631 /*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */
00632 #define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U)
00633 
00634 /*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */
00635 #define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW)
00636 
00637 /*! @brief Set the TOVALLOW field to a new value. */
00638 #define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v))
00639 /*@}*/
00640 
00641 /*******************************************************************************
00642  * HW_WDOG_WINH - Watchdog Window Register High
00643  ******************************************************************************/
00644 
00645 /*!
00646  * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
00647  *
00648  * Reset value: 0x0000U
00649  *
00650  * You must set the Window Register value lower than the Time-out Value Register.
00651  */
00652 typedef union _hw_wdog_winh
00653 {
00654     uint16_t U;
00655     struct _hw_wdog_winh_bitfields
00656     {
00657         uint16_t WINHIGH : 16;         /*!< [15:0]  */
00658     } B;
00659 } hw_wdog_winh_t;
00660 
00661 /*!
00662  * @name Constants and macros for entire WDOG_WINH register
00663  */
00664 /*@{*/
00665 #define HW_WDOG_WINH_ADDR(x)     ((x) + 0x8U)
00666 
00667 #define HW_WDOG_WINH(x)          (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x))
00668 #define HW_WDOG_WINH_RD(x)       (HW_WDOG_WINH(x).U)
00669 #define HW_WDOG_WINH_WR(x, v)    (HW_WDOG_WINH(x).U = (v))
00670 #define HW_WDOG_WINH_SET(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) |  (v)))
00671 #define HW_WDOG_WINH_CLR(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v)))
00672 #define HW_WDOG_WINH_TOG(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^  (v)))
00673 /*@}*/
00674 
00675 /*
00676  * Constants & macros for individual WDOG_WINH bitfields
00677  */
00678 
00679 /*!
00680  * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
00681  *
00682  * Defines the upper 16 bits of the 32-bit window for the windowed mode of
00683  * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
00684  * In this mode, the watchdog can be refreshed only when the timer has reached a
00685  * value greater than or equal to this window length. A refresh outside this
00686  * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
00687  * system.
00688  */
00689 /*@{*/
00690 #define BP_WDOG_WINH_WINHIGH (0U)          /*!< Bit position for WDOG_WINH_WINHIGH. */
00691 #define BM_WDOG_WINH_WINHIGH (0xFFFFU)     /*!< Bit mask for WDOG_WINH_WINHIGH. */
00692 #define BS_WDOG_WINH_WINHIGH (16U)         /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */
00693 
00694 /*! @brief Read current value of the WDOG_WINH_WINHIGH field. */
00695 #define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U)
00696 
00697 /*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */
00698 #define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH)
00699 
00700 /*! @brief Set the WINHIGH field to a new value. */
00701 #define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v))
00702 /*@}*/
00703 
00704 /*******************************************************************************
00705  * HW_WDOG_WINL - Watchdog Window Register Low
00706  ******************************************************************************/
00707 
00708 /*!
00709  * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
00710  *
00711  * Reset value: 0x0010U
00712  *
00713  * You must set the Window Register value lower than the Time-out Value Register.
00714  */
00715 typedef union _hw_wdog_winl
00716 {
00717     uint16_t U;
00718     struct _hw_wdog_winl_bitfields
00719     {
00720         uint16_t WINLOW : 16;          /*!< [15:0]  */
00721     } B;
00722 } hw_wdog_winl_t;
00723 
00724 /*!
00725  * @name Constants and macros for entire WDOG_WINL register
00726  */
00727 /*@{*/
00728 #define HW_WDOG_WINL_ADDR(x)     ((x) + 0xAU)
00729 
00730 #define HW_WDOG_WINL(x)          (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x))
00731 #define HW_WDOG_WINL_RD(x)       (HW_WDOG_WINL(x).U)
00732 #define HW_WDOG_WINL_WR(x, v)    (HW_WDOG_WINL(x).U = (v))
00733 #define HW_WDOG_WINL_SET(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) |  (v)))
00734 #define HW_WDOG_WINL_CLR(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v)))
00735 #define HW_WDOG_WINL_TOG(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^  (v)))
00736 /*@}*/
00737 
00738 /*
00739  * Constants & macros for individual WDOG_WINL bitfields
00740  */
00741 
00742 /*!
00743  * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
00744  *
00745  * Defines the lower 16 bits of the 32-bit window for the windowed mode of
00746  * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
00747  * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
00748  * reaches a value greater than or equal to this window length value. A refresh
00749  * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
00750  * then resets the system.
00751  */
00752 /*@{*/
00753 #define BP_WDOG_WINL_WINLOW  (0U)          /*!< Bit position for WDOG_WINL_WINLOW. */
00754 #define BM_WDOG_WINL_WINLOW  (0xFFFFU)     /*!< Bit mask for WDOG_WINL_WINLOW. */
00755 #define BS_WDOG_WINL_WINLOW  (16U)         /*!< Bit field size in bits for WDOG_WINL_WINLOW. */
00756 
00757 /*! @brief Read current value of the WDOG_WINL_WINLOW field. */
00758 #define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U)
00759 
00760 /*! @brief Format value for bitfield WDOG_WINL_WINLOW. */
00761 #define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW)
00762 
00763 /*! @brief Set the WINLOW field to a new value. */
00764 #define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v))
00765 /*@}*/
00766 
00767 /*******************************************************************************
00768  * HW_WDOG_REFRESH - Watchdog Refresh register
00769  ******************************************************************************/
00770 
00771 /*!
00772  * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
00773  *
00774  * Reset value: 0xB480U
00775  */
00776 typedef union _hw_wdog_refresh
00777 {
00778     uint16_t U;
00779     struct _hw_wdog_refresh_bitfields
00780     {
00781         uint16_t WDOGREFRESH : 16;     /*!< [15:0]  */
00782     } B;
00783 } hw_wdog_refresh_t;
00784 
00785 /*!
00786  * @name Constants and macros for entire WDOG_REFRESH register
00787  */
00788 /*@{*/
00789 #define HW_WDOG_REFRESH_ADDR(x)  ((x) + 0xCU)
00790 
00791 #define HW_WDOG_REFRESH(x)       (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x))
00792 #define HW_WDOG_REFRESH_RD(x)    (HW_WDOG_REFRESH(x).U)
00793 #define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v))
00794 #define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) |  (v)))
00795 #define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v)))
00796 #define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^  (v)))
00797 /*@}*/
00798 
00799 /*
00800  * Constants & macros for individual WDOG_REFRESH bitfields
00801  */
00802 
00803 /*!
00804  * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
00805  *
00806  * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
00807  * bus clock cycles written to this register refreshes the WDOG and prevents it
00808  * from resetting the system. Writing a value other than the above mentioned
00809  * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
00810  * IRQRSTEN is set, it interrupts and then resets the system.
00811  */
00812 /*@{*/
00813 #define BP_WDOG_REFRESH_WDOGREFRESH (0U)   /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */
00814 #define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */
00815 #define BS_WDOG_REFRESH_WDOGREFRESH (16U)  /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */
00816 
00817 /*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */
00818 #define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U)
00819 
00820 /*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */
00821 #define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH)
00822 
00823 /*! @brief Set the WDOGREFRESH field to a new value. */
00824 #define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v))
00825 /*@}*/
00826 
00827 /*******************************************************************************
00828  * HW_WDOG_UNLOCK - Watchdog Unlock register
00829  ******************************************************************************/
00830 
00831 /*!
00832  * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
00833  *
00834  * Reset value: 0xD928U
00835  */
00836 typedef union _hw_wdog_unlock
00837 {
00838     uint16_t U;
00839     struct _hw_wdog_unlock_bitfields
00840     {
00841         uint16_t WDOGUNLOCK : 16;      /*!< [15:0]  */
00842     } B;
00843 } hw_wdog_unlock_t;
00844 
00845 /*!
00846  * @name Constants and macros for entire WDOG_UNLOCK register
00847  */
00848 /*@{*/
00849 #define HW_WDOG_UNLOCK_ADDR(x)   ((x) + 0xEU)
00850 
00851 #define HW_WDOG_UNLOCK(x)        (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x))
00852 #define HW_WDOG_UNLOCK_RD(x)     (HW_WDOG_UNLOCK(x).U)
00853 #define HW_WDOG_UNLOCK_WR(x, v)  (HW_WDOG_UNLOCK(x).U = (v))
00854 #define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) |  (v)))
00855 #define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v)))
00856 #define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^  (v)))
00857 /*@}*/
00858 
00859 /*
00860  * Constants & macros for individual WDOG_UNLOCK bitfields
00861  */
00862 
00863 /*!
00864  * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
00865  *
00866  * Writing the unlock sequence values to this register to makes the watchdog
00867  * write-once registers writable again. The required unlock sequence is 0xC520
00868  * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
00869  * window equal in length to the WCT within which you can update the registers.
00870  * Writing a value other than the above mentioned sequence or if the sequence is
00871  * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
00872  * and then resets the system. The unlock sequence is effective only if
00873  * ALLOWUPDATE is set.
00874  */
00875 /*@{*/
00876 #define BP_WDOG_UNLOCK_WDOGUNLOCK (0U)     /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */
00877 #define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */
00878 #define BS_WDOG_UNLOCK_WDOGUNLOCK (16U)    /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */
00879 
00880 /*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */
00881 #define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U)
00882 
00883 /*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */
00884 #define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK)
00885 
00886 /*! @brief Set the WDOGUNLOCK field to a new value. */
00887 #define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v))
00888 /*@}*/
00889 
00890 /*******************************************************************************
00891  * HW_WDOG_TMROUTH - Watchdog Timer Output Register High
00892  ******************************************************************************/
00893 
00894 /*!
00895  * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
00896  *
00897  * Reset value: 0x0000U
00898  */
00899 typedef union _hw_wdog_tmrouth
00900 {
00901     uint16_t U;
00902     struct _hw_wdog_tmrouth_bitfields
00903     {
00904         uint16_t TIMEROUTHIGH : 16;    /*!< [15:0]  */
00905     } B;
00906 } hw_wdog_tmrouth_t;
00907 
00908 /*!
00909  * @name Constants and macros for entire WDOG_TMROUTH register
00910  */
00911 /*@{*/
00912 #define HW_WDOG_TMROUTH_ADDR(x)  ((x) + 0x10U)
00913 
00914 #define HW_WDOG_TMROUTH(x)       (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x))
00915 #define HW_WDOG_TMROUTH_RD(x)    (HW_WDOG_TMROUTH(x).U)
00916 #define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v))
00917 #define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) |  (v)))
00918 #define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v)))
00919 #define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^  (v)))
00920 /*@}*/
00921 
00922 /*
00923  * Constants & macros for individual WDOG_TMROUTH bitfields
00924  */
00925 
00926 /*!
00927  * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
00928  *
00929  * Shows the value of the upper 16 bits of the watchdog timer.
00930  */
00931 /*@{*/
00932 #define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U)  /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */
00933 #define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */
00934 #define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */
00935 
00936 /*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */
00937 #define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U)
00938 
00939 /*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */
00940 #define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
00941 
00942 /*! @brief Set the TIMEROUTHIGH field to a new value. */
00943 #define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v))
00944 /*@}*/
00945 
00946 /*******************************************************************************
00947  * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
00948  ******************************************************************************/
00949 
00950 /*!
00951  * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
00952  *
00953  * Reset value: 0x0000U
00954  *
00955  * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
00956  * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
00957  * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
00958  * the watchdog timer.
00959  */
00960 typedef union _hw_wdog_tmroutl
00961 {
00962     uint16_t U;
00963     struct _hw_wdog_tmroutl_bitfields
00964     {
00965         uint16_t TIMEROUTLOW : 16;     /*!< [15:0]  */
00966     } B;
00967 } hw_wdog_tmroutl_t;
00968 
00969 /*!
00970  * @name Constants and macros for entire WDOG_TMROUTL register
00971  */
00972 /*@{*/
00973 #define HW_WDOG_TMROUTL_ADDR(x)  ((x) + 0x12U)
00974 
00975 #define HW_WDOG_TMROUTL(x)       (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x))
00976 #define HW_WDOG_TMROUTL_RD(x)    (HW_WDOG_TMROUTL(x).U)
00977 #define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v))
00978 #define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) |  (v)))
00979 #define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v)))
00980 #define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^  (v)))
00981 /*@}*/
00982 
00983 /*
00984  * Constants & macros for individual WDOG_TMROUTL bitfields
00985  */
00986 
00987 /*!
00988  * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
00989  *
00990  * Shows the value of the lower 16 bits of the watchdog timer.
00991  */
00992 /*@{*/
00993 #define BP_WDOG_TMROUTL_TIMEROUTLOW (0U)   /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */
00994 #define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */
00995 #define BS_WDOG_TMROUTL_TIMEROUTLOW (16U)  /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */
00996 
00997 /*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */
00998 #define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U)
00999 
01000 /*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */
01001 #define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW)
01002 
01003 /*! @brief Set the TIMEROUTLOW field to a new value. */
01004 #define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v))
01005 /*@}*/
01006 
01007 /*******************************************************************************
01008  * HW_WDOG_RSTCNT - Watchdog Reset Count register
01009  ******************************************************************************/
01010 
01011 /*!
01012  * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
01013  *
01014  * Reset value: 0x0000U
01015  */
01016 typedef union _hw_wdog_rstcnt
01017 {
01018     uint16_t U;
01019     struct _hw_wdog_rstcnt_bitfields
01020     {
01021         uint16_t RSTCNT : 16;          /*!< [15:0]  */
01022     } B;
01023 } hw_wdog_rstcnt_t;
01024 
01025 /*!
01026  * @name Constants and macros for entire WDOG_RSTCNT register
01027  */
01028 /*@{*/
01029 #define HW_WDOG_RSTCNT_ADDR(x)   ((x) + 0x14U)
01030 
01031 #define HW_WDOG_RSTCNT(x)        (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x))
01032 #define HW_WDOG_RSTCNT_RD(x)     (HW_WDOG_RSTCNT(x).U)
01033 #define HW_WDOG_RSTCNT_WR(x, v)  (HW_WDOG_RSTCNT(x).U = (v))
01034 #define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) |  (v)))
01035 #define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v)))
01036 #define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^  (v)))
01037 /*@}*/
01038 
01039 /*
01040  * Constants & macros for individual WDOG_RSTCNT bitfields
01041  */
01042 
01043 /*!
01044  * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
01045  *
01046  * Counts the number of times the watchdog resets the system. This register is
01047  * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
01048  * the contents of this register.
01049  */
01050 /*@{*/
01051 #define BP_WDOG_RSTCNT_RSTCNT (0U)         /*!< Bit position for WDOG_RSTCNT_RSTCNT. */
01052 #define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU)    /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */
01053 #define BS_WDOG_RSTCNT_RSTCNT (16U)        /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */
01054 
01055 /*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */
01056 #define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U)
01057 
01058 /*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */
01059 #define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT)
01060 
01061 /*! @brief Set the RSTCNT field to a new value. */
01062 #define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v))
01063 /*@}*/
01064 
01065 /*******************************************************************************
01066  * HW_WDOG_PRESC - Watchdog Prescaler register
01067  ******************************************************************************/
01068 
01069 /*!
01070  * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
01071  *
01072  * Reset value: 0x0400U
01073  */
01074 typedef union _hw_wdog_presc
01075 {
01076     uint16_t U;
01077     struct _hw_wdog_presc_bitfields
01078     {
01079         uint16_t RESERVED0 : 8;        /*!< [7:0]  */
01080         uint16_t PRESCVAL : 3;         /*!< [10:8]  */
01081         uint16_t RESERVED1 : 5;        /*!< [15:11]  */
01082     } B;
01083 } hw_wdog_presc_t;
01084 
01085 /*!
01086  * @name Constants and macros for entire WDOG_PRESC register
01087  */
01088 /*@{*/
01089 #define HW_WDOG_PRESC_ADDR(x)    ((x) + 0x16U)
01090 
01091 #define HW_WDOG_PRESC(x)         (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x))
01092 #define HW_WDOG_PRESC_RD(x)      (HW_WDOG_PRESC(x).U)
01093 #define HW_WDOG_PRESC_WR(x, v)   (HW_WDOG_PRESC(x).U = (v))
01094 #define HW_WDOG_PRESC_SET(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) |  (v)))
01095 #define HW_WDOG_PRESC_CLR(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v)))
01096 #define HW_WDOG_PRESC_TOG(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^  (v)))
01097 /*@}*/
01098 
01099 /*
01100  * Constants & macros for individual WDOG_PRESC bitfields
01101  */
01102 
01103 /*!
01104  * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
01105  *
01106  * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
01107  * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
01108  * 1) to provide the prescaled WDOG_CLK.
01109  */
01110 /*@{*/
01111 #define BP_WDOG_PRESC_PRESCVAL (8U)        /*!< Bit position for WDOG_PRESC_PRESCVAL. */
01112 #define BM_WDOG_PRESC_PRESCVAL (0x0700U)   /*!< Bit mask for WDOG_PRESC_PRESCVAL. */
01113 #define BS_WDOG_PRESC_PRESCVAL (3U)        /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */
01114 
01115 /*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
01116 #define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL)
01117 
01118 /*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */
01119 #define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL)
01120 
01121 /*! @brief Set the PRESCVAL field to a new value. */
01122 #define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
01123 /*@}*/
01124 
01125 /*******************************************************************************
01126  * hw_wdog_t - module struct
01127  ******************************************************************************/
01128 /*!
01129  * @brief All WDOG module registers.
01130  */
01131 #pragma pack(1)
01132 typedef struct _hw_wdog
01133 {
01134     __IO hw_wdog_stctrlh_t STCTRLH ;        /*!< [0x0] Watchdog Status and Control Register High */
01135     __IO hw_wdog_stctrll_t STCTRLL ;        /*!< [0x2] Watchdog Status and Control Register Low */
01136     __IO hw_wdog_tovalh_t TOVALH ;          /*!< [0x4] Watchdog Time-out Value Register High */
01137     __IO hw_wdog_tovall_t TOVALL ;          /*!< [0x6] Watchdog Time-out Value Register Low */
01138     __IO hw_wdog_winh_t WINH ;              /*!< [0x8] Watchdog Window Register High */
01139     __IO hw_wdog_winl_t WINL ;              /*!< [0xA] Watchdog Window Register Low */
01140     __IO hw_wdog_refresh_t REFRESH ;        /*!< [0xC] Watchdog Refresh register */
01141     __IO hw_wdog_unlock_t UNLOCK ;          /*!< [0xE] Watchdog Unlock register */
01142     __IO hw_wdog_tmrouth_t TMROUTH ;        /*!< [0x10] Watchdog Timer Output Register High */
01143     __IO hw_wdog_tmroutl_t TMROUTL ;        /*!< [0x12] Watchdog Timer Output Register Low */
01144     __IO hw_wdog_rstcnt_t RSTCNT ;          /*!< [0x14] Watchdog Reset Count register */
01145     __IO hw_wdog_presc_t PRESC ;            /*!< [0x16] Watchdog Prescaler register */
01146 } hw_wdog_t;
01147 #pragma pack()
01148 
01149 /*! @brief Macro to access all WDOG registers. */
01150 /*! @param x WDOG module instance base address. */
01151 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01152  *     use the '&' operator, like <code>&HW_WDOG(WDOG_BASE)</code>. */
01153 #define HW_WDOG(x)     (*(hw_wdog_t *)(x))
01154 
01155 #endif /* __HW_WDOG_REGISTERS_H__ */
01156 /* EOF */