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MK64F12_usb.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** Redistribution and use in source and binary forms, with or without modification, 00019 ** are permitted provided that the following conditions are met: 00020 ** 00021 ** o Redistributions of source code must retain the above copyright notice, this list 00022 ** of conditions and the following disclaimer. 00023 ** 00024 ** o Redistributions in binary form must reproduce the above copyright notice, this 00025 ** list of conditions and the following disclaimer in the documentation and/or 00026 ** other materials provided with the distribution. 00027 ** 00028 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00029 ** contributors may be used to endorse or promote products derived from this 00030 ** software without specific prior written permission. 00031 ** 00032 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00033 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00034 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00035 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00036 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00037 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00038 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00039 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00040 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00041 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00042 ** 00043 ** http: www.freescale.com 00044 ** mail: support@freescale.com 00045 ** 00046 ** Revisions: 00047 ** - rev. 1.0 (2013-08-12) 00048 ** Initial version. 00049 ** - rev. 2.0 (2013-10-29) 00050 ** Register accessor macros added to the memory map. 00051 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00052 ** Startup file for gcc has been updated according to CMSIS 3.2. 00053 ** System initialization updated. 00054 ** MCG - registers updated. 00055 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00056 ** - rev. 2.1 (2013-10-30) 00057 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00058 ** - rev. 2.2 (2013-12-09) 00059 ** DMA - EARS register removed. 00060 ** AIPS0, AIPS1 - MPRA register updated. 00061 ** - rev. 2.3 (2014-01-24) 00062 ** Update according to reference manual rev. 2 00063 ** ENET, MCG, MCM, SIM, USB - registers updated 00064 ** - rev. 2.4 (2014-02-10) 00065 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00066 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00067 ** - rev. 2.5 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00071 ** 00072 ** ################################################################### 00073 */ 00074 00075 /* 00076 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00077 * 00078 * This file was generated automatically and any changes may be lost. 00079 */ 00080 #ifndef __HW_USB_REGISTERS_H__ 00081 #define __HW_USB_REGISTERS_H__ 00082 00083 #include "MK64F12.h" 00084 #include "fsl_bitaccess.h" 00085 00086 /* 00087 * MK64F12 USB 00088 * 00089 * Universal Serial Bus, OTG Capable Controller 00090 * 00091 * Registers defined in this header file: 00092 * - HW_USB_PERID - Peripheral ID register 00093 * - HW_USB_IDCOMP - Peripheral ID Complement register 00094 * - HW_USB_REV - Peripheral Revision register 00095 * - HW_USB_ADDINFO - Peripheral Additional Info register 00096 * - HW_USB_OTGISTAT - OTG Interrupt Status register 00097 * - HW_USB_OTGICR - OTG Interrupt Control register 00098 * - HW_USB_OTGSTAT - OTG Status register 00099 * - HW_USB_OTGCTL - OTG Control register 00100 * - HW_USB_ISTAT - Interrupt Status register 00101 * - HW_USB_INTEN - Interrupt Enable register 00102 * - HW_USB_ERRSTAT - Error Interrupt Status register 00103 * - HW_USB_ERREN - Error Interrupt Enable register 00104 * - HW_USB_STAT - Status register 00105 * - HW_USB_CTL - Control register 00106 * - HW_USB_ADDR - Address register 00107 * - HW_USB_BDTPAGE1 - BDT Page register 1 00108 * - HW_USB_FRMNUML - Frame Number register Low 00109 * - HW_USB_FRMNUMH - Frame Number register High 00110 * - HW_USB_TOKEN - Token register 00111 * - HW_USB_SOFTHLD - SOF Threshold register 00112 * - HW_USB_BDTPAGE2 - BDT Page Register 2 00113 * - HW_USB_BDTPAGE3 - BDT Page Register 3 00114 * - HW_USB_ENDPTn - Endpoint Control register 00115 * - HW_USB_USBCTRL - USB Control register 00116 * - HW_USB_OBSERVE - USB OTG Observe register 00117 * - HW_USB_CONTROL - USB OTG Control register 00118 * - HW_USB_USBTRC0 - USB Transceiver Control register 0 00119 * - HW_USB_USBFRMADJUST - Frame Adjust Register 00120 * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control 00121 * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register 00122 * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status 00123 * 00124 * - hw_usb_t - Struct containing all module registers. 00125 */ 00126 00127 #define HW_USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */ 00128 00129 /******************************************************************************* 00130 * HW_USB_PERID - Peripheral ID register 00131 ******************************************************************************/ 00132 00133 /*! 00134 * @brief HW_USB_PERID - Peripheral ID register (RO) 00135 * 00136 * Reset value: 0x04U 00137 * 00138 * Reads back the value of 0x04. This value is defined for the USB peripheral. 00139 */ 00140 typedef union _hw_usb_perid 00141 { 00142 uint8_t U; 00143 struct _hw_usb_perid_bitfields 00144 { 00145 uint8_t ID : 6; /*!< [5:0] Peripheral Identification */ 00146 uint8_t RESERVED0 : 2; /*!< [7:6] */ 00147 } B; 00148 } hw_usb_perid_t; 00149 00150 /*! 00151 * @name Constants and macros for entire USB_PERID register 00152 */ 00153 /*@{*/ 00154 #define HW_USB_PERID_ADDR(x) ((x) + 0x0U) 00155 00156 #define HW_USB_PERID(x) (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR(x)) 00157 #define HW_USB_PERID_RD(x) (HW_USB_PERID(x).U) 00158 /*@}*/ 00159 00160 /* 00161 * Constants & macros for individual USB_PERID bitfields 00162 */ 00163 00164 /*! 00165 * @name Register USB_PERID, field ID[5:0] (RO) 00166 * 00167 * This field always reads 0x4h. 00168 */ 00169 /*@{*/ 00170 #define BP_USB_PERID_ID (0U) /*!< Bit position for USB_PERID_ID. */ 00171 #define BM_USB_PERID_ID (0x3FU) /*!< Bit mask for USB_PERID_ID. */ 00172 #define BS_USB_PERID_ID (6U) /*!< Bit field size in bits for USB_PERID_ID. */ 00173 00174 /*! @brief Read current value of the USB_PERID_ID field. */ 00175 #define BR_USB_PERID_ID(x) (HW_USB_PERID(x).B.ID) 00176 /*@}*/ 00177 00178 /******************************************************************************* 00179 * HW_USB_IDCOMP - Peripheral ID Complement register 00180 ******************************************************************************/ 00181 00182 /*! 00183 * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO) 00184 * 00185 * Reset value: 0xFBU 00186 * 00187 * Reads back the complement of the Peripheral ID register. For the USB 00188 * peripheral, the value is 0xFB. 00189 */ 00190 typedef union _hw_usb_idcomp 00191 { 00192 uint8_t U; 00193 struct _hw_usb_idcomp_bitfields 00194 { 00195 uint8_t NID : 6; /*!< [5:0] */ 00196 uint8_t RESERVED0 : 2; /*!< [7:6] */ 00197 } B; 00198 } hw_usb_idcomp_t; 00199 00200 /*! 00201 * @name Constants and macros for entire USB_IDCOMP register 00202 */ 00203 /*@{*/ 00204 #define HW_USB_IDCOMP_ADDR(x) ((x) + 0x4U) 00205 00206 #define HW_USB_IDCOMP(x) (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR(x)) 00207 #define HW_USB_IDCOMP_RD(x) (HW_USB_IDCOMP(x).U) 00208 /*@}*/ 00209 00210 /* 00211 * Constants & macros for individual USB_IDCOMP bitfields 00212 */ 00213 00214 /*! 00215 * @name Register USB_IDCOMP, field NID[5:0] (RO) 00216 * 00217 * Ones' complement of PERID[ID]. bits. 00218 */ 00219 /*@{*/ 00220 #define BP_USB_IDCOMP_NID (0U) /*!< Bit position for USB_IDCOMP_NID. */ 00221 #define BM_USB_IDCOMP_NID (0x3FU) /*!< Bit mask for USB_IDCOMP_NID. */ 00222 #define BS_USB_IDCOMP_NID (6U) /*!< Bit field size in bits for USB_IDCOMP_NID. */ 00223 00224 /*! @brief Read current value of the USB_IDCOMP_NID field. */ 00225 #define BR_USB_IDCOMP_NID(x) (HW_USB_IDCOMP(x).B.NID) 00226 /*@}*/ 00227 00228 /******************************************************************************* 00229 * HW_USB_REV - Peripheral Revision register 00230 ******************************************************************************/ 00231 00232 /*! 00233 * @brief HW_USB_REV - Peripheral Revision register (RO) 00234 * 00235 * Reset value: 0x33U 00236 * 00237 * Contains the revision number of the USB module. 00238 */ 00239 typedef union _hw_usb_rev 00240 { 00241 uint8_t U; 00242 struct _hw_usb_rev_bitfields 00243 { 00244 uint8_t REV : 8; /*!< [7:0] Revision */ 00245 } B; 00246 } hw_usb_rev_t; 00247 00248 /*! 00249 * @name Constants and macros for entire USB_REV register 00250 */ 00251 /*@{*/ 00252 #define HW_USB_REV_ADDR(x) ((x) + 0x8U) 00253 00254 #define HW_USB_REV(x) (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR(x)) 00255 #define HW_USB_REV_RD(x) (HW_USB_REV(x).U) 00256 /*@}*/ 00257 00258 /* 00259 * Constants & macros for individual USB_REV bitfields 00260 */ 00261 00262 /*! 00263 * @name Register USB_REV, field REV[7:0] (RO) 00264 * 00265 * Indicates the revision number of the USB Core. 00266 */ 00267 /*@{*/ 00268 #define BP_USB_REV_REV (0U) /*!< Bit position for USB_REV_REV. */ 00269 #define BM_USB_REV_REV (0xFFU) /*!< Bit mask for USB_REV_REV. */ 00270 #define BS_USB_REV_REV (8U) /*!< Bit field size in bits for USB_REV_REV. */ 00271 00272 /*! @brief Read current value of the USB_REV_REV field. */ 00273 #define BR_USB_REV_REV(x) (HW_USB_REV(x).U) 00274 /*@}*/ 00275 00276 /******************************************************************************* 00277 * HW_USB_ADDINFO - Peripheral Additional Info register 00278 ******************************************************************************/ 00279 00280 /*! 00281 * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO) 00282 * 00283 * Reset value: 0x01U 00284 * 00285 * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with 00286 * the Host Enable bit. 00287 */ 00288 typedef union _hw_usb_addinfo 00289 { 00290 uint8_t U; 00291 struct _hw_usb_addinfo_bitfields 00292 { 00293 uint8_t IEHOST : 1; /*!< [0] */ 00294 uint8_t RESERVED0 : 2; /*!< [2:1] */ 00295 uint8_t IRQNUM : 5; /*!< [7:3] Assigned Interrupt Request Number */ 00296 } B; 00297 } hw_usb_addinfo_t; 00298 00299 /*! 00300 * @name Constants and macros for entire USB_ADDINFO register 00301 */ 00302 /*@{*/ 00303 #define HW_USB_ADDINFO_ADDR(x) ((x) + 0xCU) 00304 00305 #define HW_USB_ADDINFO(x) (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR(x)) 00306 #define HW_USB_ADDINFO_RD(x) (HW_USB_ADDINFO(x).U) 00307 /*@}*/ 00308 00309 /* 00310 * Constants & macros for individual USB_ADDINFO bitfields 00311 */ 00312 00313 /*! 00314 * @name Register USB_ADDINFO, field IEHOST[0] (RO) 00315 * 00316 * This bit is set if host mode is enabled. 00317 */ 00318 /*@{*/ 00319 #define BP_USB_ADDINFO_IEHOST (0U) /*!< Bit position for USB_ADDINFO_IEHOST. */ 00320 #define BM_USB_ADDINFO_IEHOST (0x01U) /*!< Bit mask for USB_ADDINFO_IEHOST. */ 00321 #define BS_USB_ADDINFO_IEHOST (1U) /*!< Bit field size in bits for USB_ADDINFO_IEHOST. */ 00322 00323 /*! @brief Read current value of the USB_ADDINFO_IEHOST field. */ 00324 #define BR_USB_ADDINFO_IEHOST(x) (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR(x), BP_USB_ADDINFO_IEHOST)) 00325 /*@}*/ 00326 00327 /*! 00328 * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO) 00329 */ 00330 /*@{*/ 00331 #define BP_USB_ADDINFO_IRQNUM (3U) /*!< Bit position for USB_ADDINFO_IRQNUM. */ 00332 #define BM_USB_ADDINFO_IRQNUM (0xF8U) /*!< Bit mask for USB_ADDINFO_IRQNUM. */ 00333 #define BS_USB_ADDINFO_IRQNUM (5U) /*!< Bit field size in bits for USB_ADDINFO_IRQNUM. */ 00334 00335 /*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */ 00336 #define BR_USB_ADDINFO_IRQNUM(x) (HW_USB_ADDINFO(x).B.IRQNUM) 00337 /*@}*/ 00338 00339 /******************************************************************************* 00340 * HW_USB_OTGISTAT - OTG Interrupt Status register 00341 ******************************************************************************/ 00342 00343 /*! 00344 * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW) 00345 * 00346 * Reset value: 0x00U 00347 * 00348 * Records changes of the ID sense and VBUS signals. Software can read this 00349 * register to determine the event that triggers an interrupt. Only bits that have 00350 * changed since the last software read are set. Writing a one to a bit clears the 00351 * associated interrupt. 00352 */ 00353 typedef union _hw_usb_otgistat 00354 { 00355 uint8_t U; 00356 struct _hw_usb_otgistat_bitfields 00357 { 00358 uint8_t AVBUSCHG : 1; /*!< [0] */ 00359 uint8_t RESERVED0 : 1; /*!< [1] */ 00360 uint8_t B_SESS_CHG : 1; /*!< [2] */ 00361 uint8_t SESSVLDCHG : 1; /*!< [3] */ 00362 uint8_t RESERVED1 : 1; /*!< [4] */ 00363 uint8_t LINE_STATE_CHG : 1; /*!< [5] */ 00364 uint8_t ONEMSEC : 1; /*!< [6] */ 00365 uint8_t IDCHG : 1; /*!< [7] */ 00366 } B; 00367 } hw_usb_otgistat_t; 00368 00369 /*! 00370 * @name Constants and macros for entire USB_OTGISTAT register 00371 */ 00372 /*@{*/ 00373 #define HW_USB_OTGISTAT_ADDR(x) ((x) + 0x10U) 00374 00375 #define HW_USB_OTGISTAT(x) (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR(x)) 00376 #define HW_USB_OTGISTAT_RD(x) (HW_USB_OTGISTAT(x).U) 00377 #define HW_USB_OTGISTAT_WR(x, v) (HW_USB_OTGISTAT(x).U = (v)) 00378 #define HW_USB_OTGISTAT_SET(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) | (v))) 00379 #define HW_USB_OTGISTAT_CLR(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) & ~(v))) 00380 #define HW_USB_OTGISTAT_TOG(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) ^ (v))) 00381 /*@}*/ 00382 00383 /* 00384 * Constants & macros for individual USB_OTGISTAT bitfields 00385 */ 00386 00387 /*! 00388 * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW) 00389 * 00390 * This bit is set when a change in VBUS is detected on an A device. 00391 */ 00392 /*@{*/ 00393 #define BP_USB_OTGISTAT_AVBUSCHG (0U) /*!< Bit position for USB_OTGISTAT_AVBUSCHG. */ 00394 #define BM_USB_OTGISTAT_AVBUSCHG (0x01U) /*!< Bit mask for USB_OTGISTAT_AVBUSCHG. */ 00395 #define BS_USB_OTGISTAT_AVBUSCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG. */ 00396 00397 /*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */ 00398 #define BR_USB_OTGISTAT_AVBUSCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG)) 00399 00400 /*! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG. */ 00401 #define BF_USB_OTGISTAT_AVBUSCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_AVBUSCHG) & BM_USB_OTGISTAT_AVBUSCHG) 00402 00403 /*! @brief Set the AVBUSCHG field to a new value. */ 00404 #define BW_USB_OTGISTAT_AVBUSCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG) = (v)) 00405 /*@}*/ 00406 00407 /*! 00408 * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW) 00409 * 00410 * This bit is set when a change in VBUS is detected on a B device. 00411 */ 00412 /*@{*/ 00413 #define BP_USB_OTGISTAT_B_SESS_CHG (2U) /*!< Bit position for USB_OTGISTAT_B_SESS_CHG. */ 00414 #define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) /*!< Bit mask for USB_OTGISTAT_B_SESS_CHG. */ 00415 #define BS_USB_OTGISTAT_B_SESS_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG. */ 00416 00417 /*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */ 00418 #define BR_USB_OTGISTAT_B_SESS_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG)) 00419 00420 /*! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG. */ 00421 #define BF_USB_OTGISTAT_B_SESS_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_B_SESS_CHG) & BM_USB_OTGISTAT_B_SESS_CHG) 00422 00423 /*! @brief Set the B_SESS_CHG field to a new value. */ 00424 #define BW_USB_OTGISTAT_B_SESS_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG) = (v)) 00425 /*@}*/ 00426 00427 /*! 00428 * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW) 00429 * 00430 * This bit is set when a change in VBUS is detected indicating a session valid 00431 * or a session no longer valid. 00432 */ 00433 /*@{*/ 00434 #define BP_USB_OTGISTAT_SESSVLDCHG (3U) /*!< Bit position for USB_OTGISTAT_SESSVLDCHG. */ 00435 #define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) /*!< Bit mask for USB_OTGISTAT_SESSVLDCHG. */ 00436 #define BS_USB_OTGISTAT_SESSVLDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG. */ 00437 00438 /*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */ 00439 #define BR_USB_OTGISTAT_SESSVLDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG)) 00440 00441 /*! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG. */ 00442 #define BF_USB_OTGISTAT_SESSVLDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_SESSVLDCHG) & BM_USB_OTGISTAT_SESSVLDCHG) 00443 00444 /*! @brief Set the SESSVLDCHG field to a new value. */ 00445 #define BW_USB_OTGISTAT_SESSVLDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG) = (v)) 00446 /*@}*/ 00447 00448 /*! 00449 * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW) 00450 * 00451 * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) 00452 * are stable without change for 1 millisecond, and the value of the line state 00453 * is different from the last time when the line state was stable. It is set on 00454 * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state. 00455 * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt 00456 * can be used in detecting Reset, Resume, Connect, and Data Line Pulse 00457 * signaling. 00458 */ 00459 /*@{*/ 00460 #define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) /*!< Bit position for USB_OTGISTAT_LINE_STATE_CHG. */ 00461 #define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) /*!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG. */ 00462 #define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG. */ 00463 00464 /*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */ 00465 #define BR_USB_OTGISTAT_LINE_STATE_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG)) 00466 00467 /*! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG. */ 00468 #define BF_USB_OTGISTAT_LINE_STATE_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_LINE_STATE_CHG) & BM_USB_OTGISTAT_LINE_STATE_CHG) 00469 00470 /*! @brief Set the LINE_STATE_CHG field to a new value. */ 00471 #define BW_USB_OTGISTAT_LINE_STATE_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG) = (v)) 00472 /*@}*/ 00473 00474 /*! 00475 * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW) 00476 * 00477 * This bit is set when the 1 millisecond timer expires. This bit stays asserted 00478 * until cleared by software. The interrupt must be serviced every millisecond 00479 * to avoid losing 1msec counts. 00480 */ 00481 /*@{*/ 00482 #define BP_USB_OTGISTAT_ONEMSEC (6U) /*!< Bit position for USB_OTGISTAT_ONEMSEC. */ 00483 #define BM_USB_OTGISTAT_ONEMSEC (0x40U) /*!< Bit mask for USB_OTGISTAT_ONEMSEC. */ 00484 #define BS_USB_OTGISTAT_ONEMSEC (1U) /*!< Bit field size in bits for USB_OTGISTAT_ONEMSEC. */ 00485 00486 /*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */ 00487 #define BR_USB_OTGISTAT_ONEMSEC(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC)) 00488 00489 /*! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC. */ 00490 #define BF_USB_OTGISTAT_ONEMSEC(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_ONEMSEC) & BM_USB_OTGISTAT_ONEMSEC) 00491 00492 /*! @brief Set the ONEMSEC field to a new value. */ 00493 #define BW_USB_OTGISTAT_ONEMSEC(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC) = (v)) 00494 /*@}*/ 00495 00496 /*! 00497 * @name Register USB_OTGISTAT, field IDCHG[7] (RW) 00498 * 00499 * This bit is set when a change in the ID Signal from the USB connector is 00500 * sensed. 00501 */ 00502 /*@{*/ 00503 #define BP_USB_OTGISTAT_IDCHG (7U) /*!< Bit position for USB_OTGISTAT_IDCHG. */ 00504 #define BM_USB_OTGISTAT_IDCHG (0x80U) /*!< Bit mask for USB_OTGISTAT_IDCHG. */ 00505 #define BS_USB_OTGISTAT_IDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_IDCHG. */ 00506 00507 /*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */ 00508 #define BR_USB_OTGISTAT_IDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG)) 00509 00510 /*! @brief Format value for bitfield USB_OTGISTAT_IDCHG. */ 00511 #define BF_USB_OTGISTAT_IDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_IDCHG) & BM_USB_OTGISTAT_IDCHG) 00512 00513 /*! @brief Set the IDCHG field to a new value. */ 00514 #define BW_USB_OTGISTAT_IDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG) = (v)) 00515 /*@}*/ 00516 00517 /******************************************************************************* 00518 * HW_USB_OTGICR - OTG Interrupt Control register 00519 ******************************************************************************/ 00520 00521 /*! 00522 * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW) 00523 * 00524 * Reset value: 0x00U 00525 * 00526 * Enables the corresponding interrupt status bits defined in the OTG Interrupt 00527 * Status Register. 00528 */ 00529 typedef union _hw_usb_otgicr 00530 { 00531 uint8_t U; 00532 struct _hw_usb_otgicr_bitfields 00533 { 00534 uint8_t AVBUSEN : 1; /*!< [0] A VBUS Valid Interrupt Enable */ 00535 uint8_t RESERVED0 : 1; /*!< [1] */ 00536 uint8_t BSESSEN : 1; /*!< [2] B Session END Interrupt Enable */ 00537 uint8_t SESSVLDEN : 1; /*!< [3] Session Valid Interrupt Enable */ 00538 uint8_t RESERVED1 : 1; /*!< [4] */ 00539 uint8_t LINESTATEEN : 1; /*!< [5] Line State Change Interrupt Enable 00540 * */ 00541 uint8_t ONEMSECEN : 1; /*!< [6] One Millisecond Interrupt Enable */ 00542 uint8_t IDEN : 1; /*!< [7] ID Interrupt Enable */ 00543 } B; 00544 } hw_usb_otgicr_t; 00545 00546 /*! 00547 * @name Constants and macros for entire USB_OTGICR register 00548 */ 00549 /*@{*/ 00550 #define HW_USB_OTGICR_ADDR(x) ((x) + 0x14U) 00551 00552 #define HW_USB_OTGICR(x) (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR(x)) 00553 #define HW_USB_OTGICR_RD(x) (HW_USB_OTGICR(x).U) 00554 #define HW_USB_OTGICR_WR(x, v) (HW_USB_OTGICR(x).U = (v)) 00555 #define HW_USB_OTGICR_SET(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) | (v))) 00556 #define HW_USB_OTGICR_CLR(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) & ~(v))) 00557 #define HW_USB_OTGICR_TOG(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) ^ (v))) 00558 /*@}*/ 00559 00560 /* 00561 * Constants & macros for individual USB_OTGICR bitfields 00562 */ 00563 00564 /*! 00565 * @name Register USB_OTGICR, field AVBUSEN[0] (RW) 00566 * 00567 * Values: 00568 * - 0 - Disables the AVBUSCHG interrupt. 00569 * - 1 - Enables the AVBUSCHG interrupt. 00570 */ 00571 /*@{*/ 00572 #define BP_USB_OTGICR_AVBUSEN (0U) /*!< Bit position for USB_OTGICR_AVBUSEN. */ 00573 #define BM_USB_OTGICR_AVBUSEN (0x01U) /*!< Bit mask for USB_OTGICR_AVBUSEN. */ 00574 #define BS_USB_OTGICR_AVBUSEN (1U) /*!< Bit field size in bits for USB_OTGICR_AVBUSEN. */ 00575 00576 /*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */ 00577 #define BR_USB_OTGICR_AVBUSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN)) 00578 00579 /*! @brief Format value for bitfield USB_OTGICR_AVBUSEN. */ 00580 #define BF_USB_OTGICR_AVBUSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_AVBUSEN) & BM_USB_OTGICR_AVBUSEN) 00581 00582 /*! @brief Set the AVBUSEN field to a new value. */ 00583 #define BW_USB_OTGICR_AVBUSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN) = (v)) 00584 /*@}*/ 00585 00586 /*! 00587 * @name Register USB_OTGICR, field BSESSEN[2] (RW) 00588 * 00589 * Values: 00590 * - 0 - Disables the B_SESS_CHG interrupt. 00591 * - 1 - Enables the B_SESS_CHG interrupt. 00592 */ 00593 /*@{*/ 00594 #define BP_USB_OTGICR_BSESSEN (2U) /*!< Bit position for USB_OTGICR_BSESSEN. */ 00595 #define BM_USB_OTGICR_BSESSEN (0x04U) /*!< Bit mask for USB_OTGICR_BSESSEN. */ 00596 #define BS_USB_OTGICR_BSESSEN (1U) /*!< Bit field size in bits for USB_OTGICR_BSESSEN. */ 00597 00598 /*! @brief Read current value of the USB_OTGICR_BSESSEN field. */ 00599 #define BR_USB_OTGICR_BSESSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN)) 00600 00601 /*! @brief Format value for bitfield USB_OTGICR_BSESSEN. */ 00602 #define BF_USB_OTGICR_BSESSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_BSESSEN) & BM_USB_OTGICR_BSESSEN) 00603 00604 /*! @brief Set the BSESSEN field to a new value. */ 00605 #define BW_USB_OTGICR_BSESSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN) = (v)) 00606 /*@}*/ 00607 00608 /*! 00609 * @name Register USB_OTGICR, field SESSVLDEN[3] (RW) 00610 * 00611 * Values: 00612 * - 0 - Disables the SESSVLDCHG interrupt. 00613 * - 1 - Enables the SESSVLDCHG interrupt. 00614 */ 00615 /*@{*/ 00616 #define BP_USB_OTGICR_SESSVLDEN (3U) /*!< Bit position for USB_OTGICR_SESSVLDEN. */ 00617 #define BM_USB_OTGICR_SESSVLDEN (0x08U) /*!< Bit mask for USB_OTGICR_SESSVLDEN. */ 00618 #define BS_USB_OTGICR_SESSVLDEN (1U) /*!< Bit field size in bits for USB_OTGICR_SESSVLDEN. */ 00619 00620 /*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */ 00621 #define BR_USB_OTGICR_SESSVLDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN)) 00622 00623 /*! @brief Format value for bitfield USB_OTGICR_SESSVLDEN. */ 00624 #define BF_USB_OTGICR_SESSVLDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_SESSVLDEN) & BM_USB_OTGICR_SESSVLDEN) 00625 00626 /*! @brief Set the SESSVLDEN field to a new value. */ 00627 #define BW_USB_OTGICR_SESSVLDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN) = (v)) 00628 /*@}*/ 00629 00630 /*! 00631 * @name Register USB_OTGICR, field LINESTATEEN[5] (RW) 00632 * 00633 * Values: 00634 * - 0 - Disables the LINE_STAT_CHG interrupt. 00635 * - 1 - Enables the LINE_STAT_CHG interrupt. 00636 */ 00637 /*@{*/ 00638 #define BP_USB_OTGICR_LINESTATEEN (5U) /*!< Bit position for USB_OTGICR_LINESTATEEN. */ 00639 #define BM_USB_OTGICR_LINESTATEEN (0x20U) /*!< Bit mask for USB_OTGICR_LINESTATEEN. */ 00640 #define BS_USB_OTGICR_LINESTATEEN (1U) /*!< Bit field size in bits for USB_OTGICR_LINESTATEEN. */ 00641 00642 /*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */ 00643 #define BR_USB_OTGICR_LINESTATEEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN)) 00644 00645 /*! @brief Format value for bitfield USB_OTGICR_LINESTATEEN. */ 00646 #define BF_USB_OTGICR_LINESTATEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_LINESTATEEN) & BM_USB_OTGICR_LINESTATEEN) 00647 00648 /*! @brief Set the LINESTATEEN field to a new value. */ 00649 #define BW_USB_OTGICR_LINESTATEEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN) = (v)) 00650 /*@}*/ 00651 00652 /*! 00653 * @name Register USB_OTGICR, field ONEMSECEN[6] (RW) 00654 * 00655 * Values: 00656 * - 0 - Diables the 1ms timer interrupt. 00657 * - 1 - Enables the 1ms timer interrupt. 00658 */ 00659 /*@{*/ 00660 #define BP_USB_OTGICR_ONEMSECEN (6U) /*!< Bit position for USB_OTGICR_ONEMSECEN. */ 00661 #define BM_USB_OTGICR_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGICR_ONEMSECEN. */ 00662 #define BS_USB_OTGICR_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGICR_ONEMSECEN. */ 00663 00664 /*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */ 00665 #define BR_USB_OTGICR_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN)) 00666 00667 /*! @brief Format value for bitfield USB_OTGICR_ONEMSECEN. */ 00668 #define BF_USB_OTGICR_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_ONEMSECEN) & BM_USB_OTGICR_ONEMSECEN) 00669 00670 /*! @brief Set the ONEMSECEN field to a new value. */ 00671 #define BW_USB_OTGICR_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN) = (v)) 00672 /*@}*/ 00673 00674 /*! 00675 * @name Register USB_OTGICR, field IDEN[7] (RW) 00676 * 00677 * Values: 00678 * - 0 - The ID interrupt is disabled 00679 * - 1 - The ID interrupt is enabled 00680 */ 00681 /*@{*/ 00682 #define BP_USB_OTGICR_IDEN (7U) /*!< Bit position for USB_OTGICR_IDEN. */ 00683 #define BM_USB_OTGICR_IDEN (0x80U) /*!< Bit mask for USB_OTGICR_IDEN. */ 00684 #define BS_USB_OTGICR_IDEN (1U) /*!< Bit field size in bits for USB_OTGICR_IDEN. */ 00685 00686 /*! @brief Read current value of the USB_OTGICR_IDEN field. */ 00687 #define BR_USB_OTGICR_IDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN)) 00688 00689 /*! @brief Format value for bitfield USB_OTGICR_IDEN. */ 00690 #define BF_USB_OTGICR_IDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_IDEN) & BM_USB_OTGICR_IDEN) 00691 00692 /*! @brief Set the IDEN field to a new value. */ 00693 #define BW_USB_OTGICR_IDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN) = (v)) 00694 /*@}*/ 00695 00696 /******************************************************************************* 00697 * HW_USB_OTGSTAT - OTG Status register 00698 ******************************************************************************/ 00699 00700 /*! 00701 * @brief HW_USB_OTGSTAT - OTG Status register (RW) 00702 * 00703 * Reset value: 0x00U 00704 * 00705 * Displays the actual value from the external comparator outputs of the ID pin 00706 * and VBUS. 00707 */ 00708 typedef union _hw_usb_otgstat 00709 { 00710 uint8_t U; 00711 struct _hw_usb_otgstat_bitfields 00712 { 00713 uint8_t AVBUSVLD : 1; /*!< [0] A VBUS Valid */ 00714 uint8_t RESERVED0 : 1; /*!< [1] */ 00715 uint8_t BSESSEND : 1; /*!< [2] B Session End */ 00716 uint8_t SESS_VLD : 1; /*!< [3] Session Valid */ 00717 uint8_t RESERVED1 : 1; /*!< [4] */ 00718 uint8_t LINESTATESTABLE : 1; /*!< [5] */ 00719 uint8_t ONEMSECEN : 1; /*!< [6] */ 00720 uint8_t ID : 1; /*!< [7] */ 00721 } B; 00722 } hw_usb_otgstat_t; 00723 00724 /*! 00725 * @name Constants and macros for entire USB_OTGSTAT register 00726 */ 00727 /*@{*/ 00728 #define HW_USB_OTGSTAT_ADDR(x) ((x) + 0x18U) 00729 00730 #define HW_USB_OTGSTAT(x) (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR(x)) 00731 #define HW_USB_OTGSTAT_RD(x) (HW_USB_OTGSTAT(x).U) 00732 #define HW_USB_OTGSTAT_WR(x, v) (HW_USB_OTGSTAT(x).U = (v)) 00733 #define HW_USB_OTGSTAT_SET(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) | (v))) 00734 #define HW_USB_OTGSTAT_CLR(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) & ~(v))) 00735 #define HW_USB_OTGSTAT_TOG(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) ^ (v))) 00736 /*@}*/ 00737 00738 /* 00739 * Constants & macros for individual USB_OTGSTAT bitfields 00740 */ 00741 00742 /*! 00743 * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW) 00744 * 00745 * Values: 00746 * - 0 - The VBUS voltage is below the A VBUS Valid threshold. 00747 * - 1 - The VBUS voltage is above the A VBUS Valid threshold. 00748 */ 00749 /*@{*/ 00750 #define BP_USB_OTGSTAT_AVBUSVLD (0U) /*!< Bit position for USB_OTGSTAT_AVBUSVLD. */ 00751 #define BM_USB_OTGSTAT_AVBUSVLD (0x01U) /*!< Bit mask for USB_OTGSTAT_AVBUSVLD. */ 00752 #define BS_USB_OTGSTAT_AVBUSVLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD. */ 00753 00754 /*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */ 00755 #define BR_USB_OTGSTAT_AVBUSVLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD)) 00756 00757 /*! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD. */ 00758 #define BF_USB_OTGSTAT_AVBUSVLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_AVBUSVLD) & BM_USB_OTGSTAT_AVBUSVLD) 00759 00760 /*! @brief Set the AVBUSVLD field to a new value. */ 00761 #define BW_USB_OTGSTAT_AVBUSVLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD) = (v)) 00762 /*@}*/ 00763 00764 /*! 00765 * @name Register USB_OTGSTAT, field BSESSEND[2] (RW) 00766 * 00767 * Values: 00768 * - 0 - The VBUS voltage is above the B session end threshold. 00769 * - 1 - The VBUS voltage is below the B session end threshold. 00770 */ 00771 /*@{*/ 00772 #define BP_USB_OTGSTAT_BSESSEND (2U) /*!< Bit position for USB_OTGSTAT_BSESSEND. */ 00773 #define BM_USB_OTGSTAT_BSESSEND (0x04U) /*!< Bit mask for USB_OTGSTAT_BSESSEND. */ 00774 #define BS_USB_OTGSTAT_BSESSEND (1U) /*!< Bit field size in bits for USB_OTGSTAT_BSESSEND. */ 00775 00776 /*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */ 00777 #define BR_USB_OTGSTAT_BSESSEND(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND)) 00778 00779 /*! @brief Format value for bitfield USB_OTGSTAT_BSESSEND. */ 00780 #define BF_USB_OTGSTAT_BSESSEND(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_BSESSEND) & BM_USB_OTGSTAT_BSESSEND) 00781 00782 /*! @brief Set the BSESSEND field to a new value. */ 00783 #define BW_USB_OTGSTAT_BSESSEND(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND) = (v)) 00784 /*@}*/ 00785 00786 /*! 00787 * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW) 00788 * 00789 * Values: 00790 * - 0 - The VBUS voltage is below the B session valid threshold 00791 * - 1 - The VBUS voltage is above the B session valid threshold. 00792 */ 00793 /*@{*/ 00794 #define BP_USB_OTGSTAT_SESS_VLD (3U) /*!< Bit position for USB_OTGSTAT_SESS_VLD. */ 00795 #define BM_USB_OTGSTAT_SESS_VLD (0x08U) /*!< Bit mask for USB_OTGSTAT_SESS_VLD. */ 00796 #define BS_USB_OTGSTAT_SESS_VLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_SESS_VLD. */ 00797 00798 /*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */ 00799 #define BR_USB_OTGSTAT_SESS_VLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD)) 00800 00801 /*! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD. */ 00802 #define BF_USB_OTGSTAT_SESS_VLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_SESS_VLD) & BM_USB_OTGSTAT_SESS_VLD) 00803 00804 /*! @brief Set the SESS_VLD field to a new value. */ 00805 #define BW_USB_OTGSTAT_SESS_VLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD) = (v)) 00806 /*@}*/ 00807 00808 /*! 00809 * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW) 00810 * 00811 * Indicates that the internal signals that control the LINE_STATE_CHG field of 00812 * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG 00813 * field and then read this field. If this field reads as 1, then the value of 00814 * LINE_STATE_CHG can be considered stable. 00815 * 00816 * Values: 00817 * - 0 - The LINE_STAT_CHG bit is not yet stable. 00818 * - 1 - The LINE_STAT_CHG bit has been debounced and is stable. 00819 */ 00820 /*@{*/ 00821 #define BP_USB_OTGSTAT_LINESTATESTABLE (5U) /*!< Bit position for USB_OTGSTAT_LINESTATESTABLE. */ 00822 #define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) /*!< Bit mask for USB_OTGSTAT_LINESTATESTABLE. */ 00823 #define BS_USB_OTGSTAT_LINESTATESTABLE (1U) /*!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE. */ 00824 00825 /*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */ 00826 #define BR_USB_OTGSTAT_LINESTATESTABLE(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE)) 00827 00828 /*! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE. */ 00829 #define BF_USB_OTGSTAT_LINESTATESTABLE(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_LINESTATESTABLE) & BM_USB_OTGSTAT_LINESTATESTABLE) 00830 00831 /*! @brief Set the LINESTATESTABLE field to a new value. */ 00832 #define BW_USB_OTGSTAT_LINESTATESTABLE(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE) = (v)) 00833 /*@}*/ 00834 00835 /*! 00836 * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW) 00837 * 00838 * This bit is reserved for the 1ms count, but it is not useful to software. 00839 */ 00840 /*@{*/ 00841 #define BP_USB_OTGSTAT_ONEMSECEN (6U) /*!< Bit position for USB_OTGSTAT_ONEMSECEN. */ 00842 #define BM_USB_OTGSTAT_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGSTAT_ONEMSECEN. */ 00843 #define BS_USB_OTGSTAT_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN. */ 00844 00845 /*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */ 00846 #define BR_USB_OTGSTAT_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN)) 00847 00848 /*! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN. */ 00849 #define BF_USB_OTGSTAT_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ONEMSECEN) & BM_USB_OTGSTAT_ONEMSECEN) 00850 00851 /*! @brief Set the ONEMSECEN field to a new value. */ 00852 #define BW_USB_OTGSTAT_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN) = (v)) 00853 /*@}*/ 00854 00855 /*! 00856 * @name Register USB_OTGSTAT, field ID[7] (RW) 00857 * 00858 * Indicates the current state of the ID pin on the USB connector 00859 * 00860 * Values: 00861 * - 0 - Indicates a Type A cable is plugged into the USB connector. 00862 * - 1 - Indicates no cable is attached or a Type B cable is plugged into the 00863 * USB connector. 00864 */ 00865 /*@{*/ 00866 #define BP_USB_OTGSTAT_ID (7U) /*!< Bit position for USB_OTGSTAT_ID. */ 00867 #define BM_USB_OTGSTAT_ID (0x80U) /*!< Bit mask for USB_OTGSTAT_ID. */ 00868 #define BS_USB_OTGSTAT_ID (1U) /*!< Bit field size in bits for USB_OTGSTAT_ID. */ 00869 00870 /*! @brief Read current value of the USB_OTGSTAT_ID field. */ 00871 #define BR_USB_OTGSTAT_ID(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID)) 00872 00873 /*! @brief Format value for bitfield USB_OTGSTAT_ID. */ 00874 #define BF_USB_OTGSTAT_ID(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ID) & BM_USB_OTGSTAT_ID) 00875 00876 /*! @brief Set the ID field to a new value. */ 00877 #define BW_USB_OTGSTAT_ID(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID) = (v)) 00878 /*@}*/ 00879 00880 /******************************************************************************* 00881 * HW_USB_OTGCTL - OTG Control register 00882 ******************************************************************************/ 00883 00884 /*! 00885 * @brief HW_USB_OTGCTL - OTG Control register (RW) 00886 * 00887 * Reset value: 0x00U 00888 * 00889 * Controls the operation of VBUS and Data Line termination resistors. 00890 */ 00891 typedef union _hw_usb_otgctl 00892 { 00893 uint8_t U; 00894 struct _hw_usb_otgctl_bitfields 00895 { 00896 uint8_t RESERVED0 : 2; /*!< [1:0] */ 00897 uint8_t OTGEN : 1; /*!< [2] On-The-Go pullup/pulldown resistor enable 00898 * */ 00899 uint8_t RESERVED1 : 1; /*!< [3] */ 00900 uint8_t DMLOW : 1; /*!< [4] D- Data Line pull-down resistor enable */ 00901 uint8_t DPLOW : 1; /*!< [5] D+ Data Line pull-down resistor enable */ 00902 uint8_t RESERVED2 : 1; /*!< [6] */ 00903 uint8_t DPHIGH : 1; /*!< [7] D+ Data Line pullup resistor enable */ 00904 } B; 00905 } hw_usb_otgctl_t; 00906 00907 /*! 00908 * @name Constants and macros for entire USB_OTGCTL register 00909 */ 00910 /*@{*/ 00911 #define HW_USB_OTGCTL_ADDR(x) ((x) + 0x1CU) 00912 00913 #define HW_USB_OTGCTL(x) (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR(x)) 00914 #define HW_USB_OTGCTL_RD(x) (HW_USB_OTGCTL(x).U) 00915 #define HW_USB_OTGCTL_WR(x, v) (HW_USB_OTGCTL(x).U = (v)) 00916 #define HW_USB_OTGCTL_SET(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) | (v))) 00917 #define HW_USB_OTGCTL_CLR(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) & ~(v))) 00918 #define HW_USB_OTGCTL_TOG(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) ^ (v))) 00919 /*@}*/ 00920 00921 /* 00922 * Constants & macros for individual USB_OTGCTL bitfields 00923 */ 00924 00925 /*! 00926 * @name Register USB_OTGCTL, field OTGEN[2] (RW) 00927 * 00928 * Values: 00929 * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then 00930 * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ 00931 * and D- Data Line pull-down resistors are engaged. 00932 * - 1 - The pull-up and pull-down controls in this register are used. 00933 */ 00934 /*@{*/ 00935 #define BP_USB_OTGCTL_OTGEN (2U) /*!< Bit position for USB_OTGCTL_OTGEN. */ 00936 #define BM_USB_OTGCTL_OTGEN (0x04U) /*!< Bit mask for USB_OTGCTL_OTGEN. */ 00937 #define BS_USB_OTGCTL_OTGEN (1U) /*!< Bit field size in bits for USB_OTGCTL_OTGEN. */ 00938 00939 /*! @brief Read current value of the USB_OTGCTL_OTGEN field. */ 00940 #define BR_USB_OTGCTL_OTGEN(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN)) 00941 00942 /*! @brief Format value for bitfield USB_OTGCTL_OTGEN. */ 00943 #define BF_USB_OTGCTL_OTGEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_OTGEN) & BM_USB_OTGCTL_OTGEN) 00944 00945 /*! @brief Set the OTGEN field to a new value. */ 00946 #define BW_USB_OTGCTL_OTGEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN) = (v)) 00947 /*@}*/ 00948 00949 /*! 00950 * @name Register USB_OTGCTL, field DMLOW[4] (RW) 00951 * 00952 * Values: 00953 * - 0 - D- pulldown resistor is not enabled. 00954 * - 1 - D- pulldown resistor is enabled. 00955 */ 00956 /*@{*/ 00957 #define BP_USB_OTGCTL_DMLOW (4U) /*!< Bit position for USB_OTGCTL_DMLOW. */ 00958 #define BM_USB_OTGCTL_DMLOW (0x10U) /*!< Bit mask for USB_OTGCTL_DMLOW. */ 00959 #define BS_USB_OTGCTL_DMLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DMLOW. */ 00960 00961 /*! @brief Read current value of the USB_OTGCTL_DMLOW field. */ 00962 #define BR_USB_OTGCTL_DMLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW)) 00963 00964 /*! @brief Format value for bitfield USB_OTGCTL_DMLOW. */ 00965 #define BF_USB_OTGCTL_DMLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DMLOW) & BM_USB_OTGCTL_DMLOW) 00966 00967 /*! @brief Set the DMLOW field to a new value. */ 00968 #define BW_USB_OTGCTL_DMLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW) = (v)) 00969 /*@}*/ 00970 00971 /*! 00972 * @name Register USB_OTGCTL, field DPLOW[5] (RW) 00973 * 00974 * This bit should always be enabled together with bit 4 (DMLOW) 00975 * 00976 * Values: 00977 * - 0 - D+ pulldown resistor is not enabled. 00978 * - 1 - D+ pulldown resistor is enabled. 00979 */ 00980 /*@{*/ 00981 #define BP_USB_OTGCTL_DPLOW (5U) /*!< Bit position for USB_OTGCTL_DPLOW. */ 00982 #define BM_USB_OTGCTL_DPLOW (0x20U) /*!< Bit mask for USB_OTGCTL_DPLOW. */ 00983 #define BS_USB_OTGCTL_DPLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DPLOW. */ 00984 00985 /*! @brief Read current value of the USB_OTGCTL_DPLOW field. */ 00986 #define BR_USB_OTGCTL_DPLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW)) 00987 00988 /*! @brief Format value for bitfield USB_OTGCTL_DPLOW. */ 00989 #define BF_USB_OTGCTL_DPLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPLOW) & BM_USB_OTGCTL_DPLOW) 00990 00991 /*! @brief Set the DPLOW field to a new value. */ 00992 #define BW_USB_OTGCTL_DPLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW) = (v)) 00993 /*@}*/ 00994 00995 /*! 00996 * @name Register USB_OTGCTL, field DPHIGH[7] (RW) 00997 * 00998 * Values: 00999 * - 0 - D+ pullup resistor is not enabled 01000 * - 1 - D+ pullup resistor is enabled 01001 */ 01002 /*@{*/ 01003 #define BP_USB_OTGCTL_DPHIGH (7U) /*!< Bit position for USB_OTGCTL_DPHIGH. */ 01004 #define BM_USB_OTGCTL_DPHIGH (0x80U) /*!< Bit mask for USB_OTGCTL_DPHIGH. */ 01005 #define BS_USB_OTGCTL_DPHIGH (1U) /*!< Bit field size in bits for USB_OTGCTL_DPHIGH. */ 01006 01007 /*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */ 01008 #define BR_USB_OTGCTL_DPHIGH(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH)) 01009 01010 /*! @brief Format value for bitfield USB_OTGCTL_DPHIGH. */ 01011 #define BF_USB_OTGCTL_DPHIGH(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPHIGH) & BM_USB_OTGCTL_DPHIGH) 01012 01013 /*! @brief Set the DPHIGH field to a new value. */ 01014 #define BW_USB_OTGCTL_DPHIGH(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH) = (v)) 01015 /*@}*/ 01016 01017 /******************************************************************************* 01018 * HW_USB_ISTAT - Interrupt Status register 01019 ******************************************************************************/ 01020 01021 /*! 01022 * @brief HW_USB_ISTAT - Interrupt Status register (W1C) 01023 * 01024 * Reset value: 0x00U 01025 * 01026 * Contains fields for each of the interrupt sources within the USB Module. Each 01027 * of these fields are qualified with their respective interrupt enable bits. 01028 * All fields of this register are logically OR'd together along with the OTG 01029 * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the 01030 * processor's interrupt controller. After an interrupt bit has been set it may only 01031 * be cleared by writing a one to the respective interrupt bit. This register 01032 * contains the value of 0x00 after a reset. 01033 */ 01034 typedef union _hw_usb_istat 01035 { 01036 uint8_t U; 01037 struct _hw_usb_istat_bitfields 01038 { 01039 uint8_t USBRST : 1; /*!< [0] */ 01040 uint8_t ERROR : 1; /*!< [1] */ 01041 uint8_t SOFTOK : 1; /*!< [2] */ 01042 uint8_t TOKDNE : 1; /*!< [3] */ 01043 uint8_t SLEEP : 1; /*!< [4] */ 01044 uint8_t RESUME : 1; /*!< [5] */ 01045 uint8_t ATTACH : 1; /*!< [6] Attach Interrupt */ 01046 uint8_t STALL : 1; /*!< [7] Stall Interrupt */ 01047 } B; 01048 } hw_usb_istat_t; 01049 01050 /*! 01051 * @name Constants and macros for entire USB_ISTAT register 01052 */ 01053 /*@{*/ 01054 #define HW_USB_ISTAT_ADDR(x) ((x) + 0x80U) 01055 01056 #define HW_USB_ISTAT(x) (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR(x)) 01057 #define HW_USB_ISTAT_RD(x) (HW_USB_ISTAT(x).U) 01058 #define HW_USB_ISTAT_WR(x, v) (HW_USB_ISTAT(x).U = (v)) 01059 #define HW_USB_ISTAT_SET(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) | (v))) 01060 #define HW_USB_ISTAT_CLR(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) & ~(v))) 01061 #define HW_USB_ISTAT_TOG(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) ^ (v))) 01062 /*@}*/ 01063 01064 /* 01065 * Constants & macros for individual USB_ISTAT bitfields 01066 */ 01067 01068 /*! 01069 * @name Register USB_ISTAT, field USBRST[0] (W1C) 01070 * 01071 * This bit is set when the USB Module has decoded a valid USB reset. This 01072 * informs the processor that it should write 0x00 into the address register and 01073 * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5 01074 * microseconds. It is not asserted again until the USB reset condition has been 01075 * removed and then reasserted. 01076 */ 01077 /*@{*/ 01078 #define BP_USB_ISTAT_USBRST (0U) /*!< Bit position for USB_ISTAT_USBRST. */ 01079 #define BM_USB_ISTAT_USBRST (0x01U) /*!< Bit mask for USB_ISTAT_USBRST. */ 01080 #define BS_USB_ISTAT_USBRST (1U) /*!< Bit field size in bits for USB_ISTAT_USBRST. */ 01081 01082 /*! @brief Read current value of the USB_ISTAT_USBRST field. */ 01083 #define BR_USB_ISTAT_USBRST(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST)) 01084 01085 /*! @brief Format value for bitfield USB_ISTAT_USBRST. */ 01086 #define BF_USB_ISTAT_USBRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_USBRST) & BM_USB_ISTAT_USBRST) 01087 01088 /*! @brief Set the USBRST field to a new value. */ 01089 #define BW_USB_ISTAT_USBRST(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST) = (v)) 01090 /*@}*/ 01091 01092 /*! 01093 * @name Register USB_ISTAT, field ERROR[1] (W1C) 01094 * 01095 * This bit is set when any of the error conditions within Error Interrupt 01096 * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register 01097 * to determine the source of the error. 01098 */ 01099 /*@{*/ 01100 #define BP_USB_ISTAT_ERROR (1U) /*!< Bit position for USB_ISTAT_ERROR. */ 01101 #define BM_USB_ISTAT_ERROR (0x02U) /*!< Bit mask for USB_ISTAT_ERROR. */ 01102 #define BS_USB_ISTAT_ERROR (1U) /*!< Bit field size in bits for USB_ISTAT_ERROR. */ 01103 01104 /*! @brief Read current value of the USB_ISTAT_ERROR field. */ 01105 #define BR_USB_ISTAT_ERROR(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR)) 01106 01107 /*! @brief Format value for bitfield USB_ISTAT_ERROR. */ 01108 #define BF_USB_ISTAT_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ERROR) & BM_USB_ISTAT_ERROR) 01109 01110 /*! @brief Set the ERROR field to a new value. */ 01111 #define BW_USB_ISTAT_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR) = (v)) 01112 /*@}*/ 01113 01114 /*! 01115 * @name Register USB_ISTAT, field SOFTOK[2] (W1C) 01116 * 01117 * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In 01118 * Host mode this field is set when the SOF threshold is reached, so that 01119 * software can prepare for the next SOF. 01120 */ 01121 /*@{*/ 01122 #define BP_USB_ISTAT_SOFTOK (2U) /*!< Bit position for USB_ISTAT_SOFTOK. */ 01123 #define BM_USB_ISTAT_SOFTOK (0x04U) /*!< Bit mask for USB_ISTAT_SOFTOK. */ 01124 #define BS_USB_ISTAT_SOFTOK (1U) /*!< Bit field size in bits for USB_ISTAT_SOFTOK. */ 01125 01126 /*! @brief Read current value of the USB_ISTAT_SOFTOK field. */ 01127 #define BR_USB_ISTAT_SOFTOK(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK)) 01128 01129 /*! @brief Format value for bitfield USB_ISTAT_SOFTOK. */ 01130 #define BF_USB_ISTAT_SOFTOK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SOFTOK) & BM_USB_ISTAT_SOFTOK) 01131 01132 /*! @brief Set the SOFTOK field to a new value. */ 01133 #define BW_USB_ISTAT_SOFTOK(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK) = (v)) 01134 /*@}*/ 01135 01136 /*! 01137 * @name Register USB_ISTAT, field TOKDNE[3] (W1C) 01138 * 01139 * This bit is set when the current token being processed has completed. The 01140 * processor must immediately read the STATUS (STAT) register to determine the 01141 * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes 01142 * STAT to be cleared or the STAT holding register to be loaded into the STAT 01143 * register. 01144 */ 01145 /*@{*/ 01146 #define BP_USB_ISTAT_TOKDNE (3U) /*!< Bit position for USB_ISTAT_TOKDNE. */ 01147 #define BM_USB_ISTAT_TOKDNE (0x08U) /*!< Bit mask for USB_ISTAT_TOKDNE. */ 01148 #define BS_USB_ISTAT_TOKDNE (1U) /*!< Bit field size in bits for USB_ISTAT_TOKDNE. */ 01149 01150 /*! @brief Read current value of the USB_ISTAT_TOKDNE field. */ 01151 #define BR_USB_ISTAT_TOKDNE(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE)) 01152 01153 /*! @brief Format value for bitfield USB_ISTAT_TOKDNE. */ 01154 #define BF_USB_ISTAT_TOKDNE(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_TOKDNE) & BM_USB_ISTAT_TOKDNE) 01155 01156 /*! @brief Set the TOKDNE field to a new value. */ 01157 #define BW_USB_ISTAT_TOKDNE(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE) = (v)) 01158 /*@}*/ 01159 01160 /*! 01161 * @name Register USB_ISTAT, field SLEEP[4] (W1C) 01162 * 01163 * This bit is set when the USB Module detects a constant idle on the USB bus 01164 * for 3 ms. The sleep timer is reset by activity on the USB bus. 01165 */ 01166 /*@{*/ 01167 #define BP_USB_ISTAT_SLEEP (4U) /*!< Bit position for USB_ISTAT_SLEEP. */ 01168 #define BM_USB_ISTAT_SLEEP (0x10U) /*!< Bit mask for USB_ISTAT_SLEEP. */ 01169 #define BS_USB_ISTAT_SLEEP (1U) /*!< Bit field size in bits for USB_ISTAT_SLEEP. */ 01170 01171 /*! @brief Read current value of the USB_ISTAT_SLEEP field. */ 01172 #define BR_USB_ISTAT_SLEEP(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP)) 01173 01174 /*! @brief Format value for bitfield USB_ISTAT_SLEEP. */ 01175 #define BF_USB_ISTAT_SLEEP(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SLEEP) & BM_USB_ISTAT_SLEEP) 01176 01177 /*! @brief Set the SLEEP field to a new value. */ 01178 #define BW_USB_ISTAT_SLEEP(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP) = (v)) 01179 /*@}*/ 01180 01181 /*! 01182 * @name Register USB_ISTAT, field RESUME[5] (W1C) 01183 * 01184 * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us. 01185 * When not in suspend mode this interrupt must be disabled. 01186 */ 01187 /*@{*/ 01188 #define BP_USB_ISTAT_RESUME (5U) /*!< Bit position for USB_ISTAT_RESUME. */ 01189 #define BM_USB_ISTAT_RESUME (0x20U) /*!< Bit mask for USB_ISTAT_RESUME. */ 01190 #define BS_USB_ISTAT_RESUME (1U) /*!< Bit field size in bits for USB_ISTAT_RESUME. */ 01191 01192 /*! @brief Read current value of the USB_ISTAT_RESUME field. */ 01193 #define BR_USB_ISTAT_RESUME(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME)) 01194 01195 /*! @brief Format value for bitfield USB_ISTAT_RESUME. */ 01196 #define BF_USB_ISTAT_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_RESUME) & BM_USB_ISTAT_RESUME) 01197 01198 /*! @brief Set the RESUME field to a new value. */ 01199 #define BW_USB_ISTAT_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME) = (v)) 01200 /*@}*/ 01201 01202 /*! 01203 * @name Register USB_ISTAT, field ATTACH[6] (W1C) 01204 * 01205 * This bit is set when the USB Module detects an attach of a USB device. This 01206 * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a 01207 * peripheral is now present and must be configured; it is asserted if there have 01208 * been no transitions on the USB for 2.5 us and the current bus state is not SE0." 01209 */ 01210 /*@{*/ 01211 #define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */ 01212 #define BM_USB_ISTAT_ATTACH (0x40U) /*!< Bit mask for USB_ISTAT_ATTACH. */ 01213 #define BS_USB_ISTAT_ATTACH (1U) /*!< Bit field size in bits for USB_ISTAT_ATTACH. */ 01214 01215 /*! @brief Read current value of the USB_ISTAT_ATTACH field. */ 01216 #define BR_USB_ISTAT_ATTACH(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH)) 01217 01218 /*! @brief Format value for bitfield USB_ISTAT_ATTACH. */ 01219 #define BF_USB_ISTAT_ATTACH(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ATTACH) & BM_USB_ISTAT_ATTACH) 01220 01221 /*! @brief Set the ATTACH field to a new value. */ 01222 #define BW_USB_ISTAT_ATTACH(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH) = (v)) 01223 /*@}*/ 01224 01225 /*! 01226 * @name Register USB_ISTAT, field STALL[7] (W1C) 01227 * 01228 * In Target mode this bit is asserted when a STALL handshake is sent by the 01229 * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge 01230 * during the handshake phase of a USB transaction.This interrupt can be used to 01231 * determine whether the last USB transaction was completed successfully or 01232 * stalled. 01233 */ 01234 /*@{*/ 01235 #define BP_USB_ISTAT_STALL (7U) /*!< Bit position for USB_ISTAT_STALL. */ 01236 #define BM_USB_ISTAT_STALL (0x80U) /*!< Bit mask for USB_ISTAT_STALL. */ 01237 #define BS_USB_ISTAT_STALL (1U) /*!< Bit field size in bits for USB_ISTAT_STALL. */ 01238 01239 /*! @brief Read current value of the USB_ISTAT_STALL field. */ 01240 #define BR_USB_ISTAT_STALL(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL)) 01241 01242 /*! @brief Format value for bitfield USB_ISTAT_STALL. */ 01243 #define BF_USB_ISTAT_STALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_STALL) & BM_USB_ISTAT_STALL) 01244 01245 /*! @brief Set the STALL field to a new value. */ 01246 #define BW_USB_ISTAT_STALL(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL) = (v)) 01247 /*@}*/ 01248 01249 /******************************************************************************* 01250 * HW_USB_INTEN - Interrupt Enable register 01251 ******************************************************************************/ 01252 01253 /*! 01254 * @brief HW_USB_INTEN - Interrupt Enable register (RW) 01255 * 01256 * Reset value: 0x00U 01257 * 01258 * Contains enable fields for each of the interrupt sources within the USB 01259 * Module. Setting any of these bits enables the respective interrupt source in the 01260 * ISTAT register. This register contains the value of 0x00 after a reset. 01261 */ 01262 typedef union _hw_usb_inten 01263 { 01264 uint8_t U; 01265 struct _hw_usb_inten_bitfields 01266 { 01267 uint8_t USBRSTEN : 1; /*!< [0] USBRST Interrupt Enable */ 01268 uint8_t ERROREN : 1; /*!< [1] ERROR Interrupt Enable */ 01269 uint8_t SOFTOKEN : 1; /*!< [2] SOFTOK Interrupt Enable */ 01270 uint8_t TOKDNEEN : 1; /*!< [3] TOKDNE Interrupt Enable */ 01271 uint8_t SLEEPEN : 1; /*!< [4] SLEEP Interrupt Enable */ 01272 uint8_t RESUMEEN : 1; /*!< [5] RESUME Interrupt Enable */ 01273 uint8_t ATTACHEN : 1; /*!< [6] ATTACH Interrupt Enable */ 01274 uint8_t STALLEN : 1; /*!< [7] STALL Interrupt Enable */ 01275 } B; 01276 } hw_usb_inten_t; 01277 01278 /*! 01279 * @name Constants and macros for entire USB_INTEN register 01280 */ 01281 /*@{*/ 01282 #define HW_USB_INTEN_ADDR(x) ((x) + 0x84U) 01283 01284 #define HW_USB_INTEN(x) (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR(x)) 01285 #define HW_USB_INTEN_RD(x) (HW_USB_INTEN(x).U) 01286 #define HW_USB_INTEN_WR(x, v) (HW_USB_INTEN(x).U = (v)) 01287 #define HW_USB_INTEN_SET(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) | (v))) 01288 #define HW_USB_INTEN_CLR(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) & ~(v))) 01289 #define HW_USB_INTEN_TOG(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) ^ (v))) 01290 /*@}*/ 01291 01292 /* 01293 * Constants & macros for individual USB_INTEN bitfields 01294 */ 01295 01296 /*! 01297 * @name Register USB_INTEN, field USBRSTEN[0] (RW) 01298 * 01299 * Values: 01300 * - 0 - Disables the USBRST interrupt. 01301 * - 1 - Enables the USBRST interrupt. 01302 */ 01303 /*@{*/ 01304 #define BP_USB_INTEN_USBRSTEN (0U) /*!< Bit position for USB_INTEN_USBRSTEN. */ 01305 #define BM_USB_INTEN_USBRSTEN (0x01U) /*!< Bit mask for USB_INTEN_USBRSTEN. */ 01306 #define BS_USB_INTEN_USBRSTEN (1U) /*!< Bit field size in bits for USB_INTEN_USBRSTEN. */ 01307 01308 /*! @brief Read current value of the USB_INTEN_USBRSTEN field. */ 01309 #define BR_USB_INTEN_USBRSTEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN)) 01310 01311 /*! @brief Format value for bitfield USB_INTEN_USBRSTEN. */ 01312 #define BF_USB_INTEN_USBRSTEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_USBRSTEN) & BM_USB_INTEN_USBRSTEN) 01313 01314 /*! @brief Set the USBRSTEN field to a new value. */ 01315 #define BW_USB_INTEN_USBRSTEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN) = (v)) 01316 /*@}*/ 01317 01318 /*! 01319 * @name Register USB_INTEN, field ERROREN[1] (RW) 01320 * 01321 * Values: 01322 * - 0 - Disables the ERROR interrupt. 01323 * - 1 - Enables the ERROR interrupt. 01324 */ 01325 /*@{*/ 01326 #define BP_USB_INTEN_ERROREN (1U) /*!< Bit position for USB_INTEN_ERROREN. */ 01327 #define BM_USB_INTEN_ERROREN (0x02U) /*!< Bit mask for USB_INTEN_ERROREN. */ 01328 #define BS_USB_INTEN_ERROREN (1U) /*!< Bit field size in bits for USB_INTEN_ERROREN. */ 01329 01330 /*! @brief Read current value of the USB_INTEN_ERROREN field. */ 01331 #define BR_USB_INTEN_ERROREN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN)) 01332 01333 /*! @brief Format value for bitfield USB_INTEN_ERROREN. */ 01334 #define BF_USB_INTEN_ERROREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ERROREN) & BM_USB_INTEN_ERROREN) 01335 01336 /*! @brief Set the ERROREN field to a new value. */ 01337 #define BW_USB_INTEN_ERROREN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN) = (v)) 01338 /*@}*/ 01339 01340 /*! 01341 * @name Register USB_INTEN, field SOFTOKEN[2] (RW) 01342 * 01343 * Values: 01344 * - 0 - Disbles the SOFTOK interrupt. 01345 * - 1 - Enables the SOFTOK interrupt. 01346 */ 01347 /*@{*/ 01348 #define BP_USB_INTEN_SOFTOKEN (2U) /*!< Bit position for USB_INTEN_SOFTOKEN. */ 01349 #define BM_USB_INTEN_SOFTOKEN (0x04U) /*!< Bit mask for USB_INTEN_SOFTOKEN. */ 01350 #define BS_USB_INTEN_SOFTOKEN (1U) /*!< Bit field size in bits for USB_INTEN_SOFTOKEN. */ 01351 01352 /*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */ 01353 #define BR_USB_INTEN_SOFTOKEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN)) 01354 01355 /*! @brief Format value for bitfield USB_INTEN_SOFTOKEN. */ 01356 #define BF_USB_INTEN_SOFTOKEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SOFTOKEN) & BM_USB_INTEN_SOFTOKEN) 01357 01358 /*! @brief Set the SOFTOKEN field to a new value. */ 01359 #define BW_USB_INTEN_SOFTOKEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN) = (v)) 01360 /*@}*/ 01361 01362 /*! 01363 * @name Register USB_INTEN, field TOKDNEEN[3] (RW) 01364 * 01365 * Values: 01366 * - 0 - Disables the TOKDNE interrupt. 01367 * - 1 - Enables the TOKDNE interrupt. 01368 */ 01369 /*@{*/ 01370 #define BP_USB_INTEN_TOKDNEEN (3U) /*!< Bit position for USB_INTEN_TOKDNEEN. */ 01371 #define BM_USB_INTEN_TOKDNEEN (0x08U) /*!< Bit mask for USB_INTEN_TOKDNEEN. */ 01372 #define BS_USB_INTEN_TOKDNEEN (1U) /*!< Bit field size in bits for USB_INTEN_TOKDNEEN. */ 01373 01374 /*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */ 01375 #define BR_USB_INTEN_TOKDNEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN)) 01376 01377 /*! @brief Format value for bitfield USB_INTEN_TOKDNEEN. */ 01378 #define BF_USB_INTEN_TOKDNEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_TOKDNEEN) & BM_USB_INTEN_TOKDNEEN) 01379 01380 /*! @brief Set the TOKDNEEN field to a new value. */ 01381 #define BW_USB_INTEN_TOKDNEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN) = (v)) 01382 /*@}*/ 01383 01384 /*! 01385 * @name Register USB_INTEN, field SLEEPEN[4] (RW) 01386 * 01387 * Values: 01388 * - 0 - Disables the SLEEP interrupt. 01389 * - 1 - Enables the SLEEP interrupt. 01390 */ 01391 /*@{*/ 01392 #define BP_USB_INTEN_SLEEPEN (4U) /*!< Bit position for USB_INTEN_SLEEPEN. */ 01393 #define BM_USB_INTEN_SLEEPEN (0x10U) /*!< Bit mask for USB_INTEN_SLEEPEN. */ 01394 #define BS_USB_INTEN_SLEEPEN (1U) /*!< Bit field size in bits for USB_INTEN_SLEEPEN. */ 01395 01396 /*! @brief Read current value of the USB_INTEN_SLEEPEN field. */ 01397 #define BR_USB_INTEN_SLEEPEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN)) 01398 01399 /*! @brief Format value for bitfield USB_INTEN_SLEEPEN. */ 01400 #define BF_USB_INTEN_SLEEPEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SLEEPEN) & BM_USB_INTEN_SLEEPEN) 01401 01402 /*! @brief Set the SLEEPEN field to a new value. */ 01403 #define BW_USB_INTEN_SLEEPEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN) = (v)) 01404 /*@}*/ 01405 01406 /*! 01407 * @name Register USB_INTEN, field RESUMEEN[5] (RW) 01408 * 01409 * Values: 01410 * - 0 - Disables the RESUME interrupt. 01411 * - 1 - Enables the RESUME interrupt. 01412 */ 01413 /*@{*/ 01414 #define BP_USB_INTEN_RESUMEEN (5U) /*!< Bit position for USB_INTEN_RESUMEEN. */ 01415 #define BM_USB_INTEN_RESUMEEN (0x20U) /*!< Bit mask for USB_INTEN_RESUMEEN. */ 01416 #define BS_USB_INTEN_RESUMEEN (1U) /*!< Bit field size in bits for USB_INTEN_RESUMEEN. */ 01417 01418 /*! @brief Read current value of the USB_INTEN_RESUMEEN field. */ 01419 #define BR_USB_INTEN_RESUMEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN)) 01420 01421 /*! @brief Format value for bitfield USB_INTEN_RESUMEEN. */ 01422 #define BF_USB_INTEN_RESUMEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_RESUMEEN) & BM_USB_INTEN_RESUMEEN) 01423 01424 /*! @brief Set the RESUMEEN field to a new value. */ 01425 #define BW_USB_INTEN_RESUMEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN) = (v)) 01426 /*@}*/ 01427 01428 /*! 01429 * @name Register USB_INTEN, field ATTACHEN[6] (RW) 01430 * 01431 * Values: 01432 * - 0 - Disables the ATTACH interrupt. 01433 * - 1 - Enables the ATTACH interrupt. 01434 */ 01435 /*@{*/ 01436 #define BP_USB_INTEN_ATTACHEN (6U) /*!< Bit position for USB_INTEN_ATTACHEN. */ 01437 #define BM_USB_INTEN_ATTACHEN (0x40U) /*!< Bit mask for USB_INTEN_ATTACHEN. */ 01438 #define BS_USB_INTEN_ATTACHEN (1U) /*!< Bit field size in bits for USB_INTEN_ATTACHEN. */ 01439 01440 /*! @brief Read current value of the USB_INTEN_ATTACHEN field. */ 01441 #define BR_USB_INTEN_ATTACHEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN)) 01442 01443 /*! @brief Format value for bitfield USB_INTEN_ATTACHEN. */ 01444 #define BF_USB_INTEN_ATTACHEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ATTACHEN) & BM_USB_INTEN_ATTACHEN) 01445 01446 /*! @brief Set the ATTACHEN field to a new value. */ 01447 #define BW_USB_INTEN_ATTACHEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN) = (v)) 01448 /*@}*/ 01449 01450 /*! 01451 * @name Register USB_INTEN, field STALLEN[7] (RW) 01452 * 01453 * Values: 01454 * - 0 - Diasbles the STALL interrupt. 01455 * - 1 - Enables the STALL interrupt. 01456 */ 01457 /*@{*/ 01458 #define BP_USB_INTEN_STALLEN (7U) /*!< Bit position for USB_INTEN_STALLEN. */ 01459 #define BM_USB_INTEN_STALLEN (0x80U) /*!< Bit mask for USB_INTEN_STALLEN. */ 01460 #define BS_USB_INTEN_STALLEN (1U) /*!< Bit field size in bits for USB_INTEN_STALLEN. */ 01461 01462 /*! @brief Read current value of the USB_INTEN_STALLEN field. */ 01463 #define BR_USB_INTEN_STALLEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN)) 01464 01465 /*! @brief Format value for bitfield USB_INTEN_STALLEN. */ 01466 #define BF_USB_INTEN_STALLEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_STALLEN) & BM_USB_INTEN_STALLEN) 01467 01468 /*! @brief Set the STALLEN field to a new value. */ 01469 #define BW_USB_INTEN_STALLEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN) = (v)) 01470 /*@}*/ 01471 01472 /******************************************************************************* 01473 * HW_USB_ERRSTAT - Error Interrupt Status register 01474 ******************************************************************************/ 01475 01476 /*! 01477 * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW) 01478 * 01479 * Reset value: 0x00U 01480 * 01481 * Contains enable bits for each of the error sources within the USB Module. 01482 * Each of these bits are qualified with their respective error enable bits. All 01483 * bits of this register are logically OR'd together and the result placed in the 01484 * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only 01485 * be cleared by writing a one to the respective interrupt bit. Each bit is set 01486 * as soon as the error condition is detected. Therefore, the interrupt does not 01487 * typically correspond with the end of a token being processed. This register 01488 * contains the value of 0x00 after a reset. 01489 */ 01490 typedef union _hw_usb_errstat 01491 { 01492 uint8_t U; 01493 struct _hw_usb_errstat_bitfields 01494 { 01495 uint8_t PIDERR : 1; /*!< [0] */ 01496 uint8_t CRC5EOF : 1; /*!< [1] */ 01497 uint8_t CRC16 : 1; /*!< [2] */ 01498 uint8_t DFN8 : 1; /*!< [3] */ 01499 uint8_t BTOERR : 1; /*!< [4] */ 01500 uint8_t DMAERR : 1; /*!< [5] */ 01501 uint8_t RESERVED0 : 1; /*!< [6] */ 01502 uint8_t BTSERR : 1; /*!< [7] */ 01503 } B; 01504 } hw_usb_errstat_t; 01505 01506 /*! 01507 * @name Constants and macros for entire USB_ERRSTAT register 01508 */ 01509 /*@{*/ 01510 #define HW_USB_ERRSTAT_ADDR(x) ((x) + 0x88U) 01511 01512 #define HW_USB_ERRSTAT(x) (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR(x)) 01513 #define HW_USB_ERRSTAT_RD(x) (HW_USB_ERRSTAT(x).U) 01514 #define HW_USB_ERRSTAT_WR(x, v) (HW_USB_ERRSTAT(x).U = (v)) 01515 #define HW_USB_ERRSTAT_SET(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) | (v))) 01516 #define HW_USB_ERRSTAT_CLR(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) & ~(v))) 01517 #define HW_USB_ERRSTAT_TOG(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) ^ (v))) 01518 /*@}*/ 01519 01520 /* 01521 * Constants & macros for individual USB_ERRSTAT bitfields 01522 */ 01523 01524 /*! 01525 * @name Register USB_ERRSTAT, field PIDERR[0] (W1C) 01526 * 01527 * This bit is set when the PID check field fails. 01528 */ 01529 /*@{*/ 01530 #define BP_USB_ERRSTAT_PIDERR (0U) /*!< Bit position for USB_ERRSTAT_PIDERR. */ 01531 #define BM_USB_ERRSTAT_PIDERR (0x01U) /*!< Bit mask for USB_ERRSTAT_PIDERR. */ 01532 #define BS_USB_ERRSTAT_PIDERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_PIDERR. */ 01533 01534 /*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */ 01535 #define BR_USB_ERRSTAT_PIDERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR)) 01536 01537 /*! @brief Format value for bitfield USB_ERRSTAT_PIDERR. */ 01538 #define BF_USB_ERRSTAT_PIDERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_PIDERR) & BM_USB_ERRSTAT_PIDERR) 01539 01540 /*! @brief Set the PIDERR field to a new value. */ 01541 #define BW_USB_ERRSTAT_PIDERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR) = (v)) 01542 /*@}*/ 01543 01544 /*! 01545 * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C) 01546 * 01547 * This error interrupt has two functions. When the USB Module is operating in 01548 * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token 01549 * packets generated by the host. If set the token packet was rejected due to a 01550 * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this 01551 * interrupt detects End Of Frame (EOF) error conditions. This occurs when the 01552 * USB Module is transmitting or receiving data and the SOF counter reaches zero. 01553 * This interrupt is useful when developing USB packet scheduling software to 01554 * ensure that no USB transactions cross the start of the next frame. 01555 */ 01556 /*@{*/ 01557 #define BP_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit position for USB_ERRSTAT_CRC5EOF. */ 01558 #define BM_USB_ERRSTAT_CRC5EOF (0x02U) /*!< Bit mask for USB_ERRSTAT_CRC5EOF. */ 01559 #define BS_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC5EOF. */ 01560 01561 /*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */ 01562 #define BR_USB_ERRSTAT_CRC5EOF(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF)) 01563 01564 /*! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF. */ 01565 #define BF_USB_ERRSTAT_CRC5EOF(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC5EOF) & BM_USB_ERRSTAT_CRC5EOF) 01566 01567 /*! @brief Set the CRC5EOF field to a new value. */ 01568 #define BW_USB_ERRSTAT_CRC5EOF(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF) = (v)) 01569 /*@}*/ 01570 01571 /*! 01572 * @name Register USB_ERRSTAT, field CRC16[2] (W1C) 01573 * 01574 * This bit is set when a data packet is rejected due to a CRC16 error. 01575 */ 01576 /*@{*/ 01577 #define BP_USB_ERRSTAT_CRC16 (2U) /*!< Bit position for USB_ERRSTAT_CRC16. */ 01578 #define BM_USB_ERRSTAT_CRC16 (0x04U) /*!< Bit mask for USB_ERRSTAT_CRC16. */ 01579 #define BS_USB_ERRSTAT_CRC16 (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC16. */ 01580 01581 /*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */ 01582 #define BR_USB_ERRSTAT_CRC16(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16)) 01583 01584 /*! @brief Format value for bitfield USB_ERRSTAT_CRC16. */ 01585 #define BF_USB_ERRSTAT_CRC16(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC16) & BM_USB_ERRSTAT_CRC16) 01586 01587 /*! @brief Set the CRC16 field to a new value. */ 01588 #define BW_USB_ERRSTAT_CRC16(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16) = (v)) 01589 /*@}*/ 01590 01591 /*! 01592 * @name Register USB_ERRSTAT, field DFN8[3] (W1C) 01593 * 01594 * This bit is set if the data field received was not 8 bits in length. USB 01595 * Specification 1.0 requires that data fields be an integral number of bytes. If the 01596 * data field was not an integral number of bytes, this bit is set. 01597 */ 01598 /*@{*/ 01599 #define BP_USB_ERRSTAT_DFN8 (3U) /*!< Bit position for USB_ERRSTAT_DFN8. */ 01600 #define BM_USB_ERRSTAT_DFN8 (0x08U) /*!< Bit mask for USB_ERRSTAT_DFN8. */ 01601 #define BS_USB_ERRSTAT_DFN8 (1U) /*!< Bit field size in bits for USB_ERRSTAT_DFN8. */ 01602 01603 /*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */ 01604 #define BR_USB_ERRSTAT_DFN8(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8)) 01605 01606 /*! @brief Format value for bitfield USB_ERRSTAT_DFN8. */ 01607 #define BF_USB_ERRSTAT_DFN8(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DFN8) & BM_USB_ERRSTAT_DFN8) 01608 01609 /*! @brief Set the DFN8 field to a new value. */ 01610 #define BW_USB_ERRSTAT_DFN8(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8) = (v)) 01611 /*@}*/ 01612 01613 /*! 01614 * @name Register USB_ERRSTAT, field BTOERR[4] (W1C) 01615 * 01616 * This bit is set when a bus turnaround timeout error occurs. The USB module 01617 * contains a bus turnaround timer that keeps track of the amount of time elapsed 01618 * between the token and data phases of a SETUP or OUT TOKEN or the data and 01619 * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the 01620 * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. 01621 */ 01622 /*@{*/ 01623 #define BP_USB_ERRSTAT_BTOERR (4U) /*!< Bit position for USB_ERRSTAT_BTOERR. */ 01624 #define BM_USB_ERRSTAT_BTOERR (0x10U) /*!< Bit mask for USB_ERRSTAT_BTOERR. */ 01625 #define BS_USB_ERRSTAT_BTOERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTOERR. */ 01626 01627 /*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */ 01628 #define BR_USB_ERRSTAT_BTOERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR)) 01629 01630 /*! @brief Format value for bitfield USB_ERRSTAT_BTOERR. */ 01631 #define BF_USB_ERRSTAT_BTOERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTOERR) & BM_USB_ERRSTAT_BTOERR) 01632 01633 /*! @brief Set the BTOERR field to a new value. */ 01634 #define BW_USB_ERRSTAT_BTOERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR) = (v)) 01635 /*@}*/ 01636 01637 /*! 01638 * @name Register USB_ERRSTAT, field DMAERR[5] (W1C) 01639 * 01640 * This bit is set if the USB Module has requested a DMA access to read a new 01641 * BDT but has not been given the bus before it needs to receive or transmit data. 01642 * If processing a TX transfer this would cause a transmit data underflow 01643 * condition. If processing a RX transfer this would cause a receive data overflow 01644 * condition. This interrupt is useful when developing device arbitration hardware for 01645 * the microprocessor and the USB module to minimize bus request and bus grant 01646 * latency. This bit is also set if a data packet to or from the host is larger 01647 * than the buffer size allocated in the BDT. In this case the data packet is 01648 * truncated as it is put in buffer memory. 01649 */ 01650 /*@{*/ 01651 #define BP_USB_ERRSTAT_DMAERR (5U) /*!< Bit position for USB_ERRSTAT_DMAERR. */ 01652 #define BM_USB_ERRSTAT_DMAERR (0x20U) /*!< Bit mask for USB_ERRSTAT_DMAERR. */ 01653 #define BS_USB_ERRSTAT_DMAERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_DMAERR. */ 01654 01655 /*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */ 01656 #define BR_USB_ERRSTAT_DMAERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR)) 01657 01658 /*! @brief Format value for bitfield USB_ERRSTAT_DMAERR. */ 01659 #define BF_USB_ERRSTAT_DMAERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DMAERR) & BM_USB_ERRSTAT_DMAERR) 01660 01661 /*! @brief Set the DMAERR field to a new value. */ 01662 #define BW_USB_ERRSTAT_DMAERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR) = (v)) 01663 /*@}*/ 01664 01665 /*! 01666 * @name Register USB_ERRSTAT, field BTSERR[7] (W1C) 01667 * 01668 * This bit is set when a bit stuff error is detected. If set, the corresponding 01669 * packet is rejected due to the error. 01670 */ 01671 /*@{*/ 01672 #define BP_USB_ERRSTAT_BTSERR (7U) /*!< Bit position for USB_ERRSTAT_BTSERR. */ 01673 #define BM_USB_ERRSTAT_BTSERR (0x80U) /*!< Bit mask for USB_ERRSTAT_BTSERR. */ 01674 #define BS_USB_ERRSTAT_BTSERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTSERR. */ 01675 01676 /*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */ 01677 #define BR_USB_ERRSTAT_BTSERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR)) 01678 01679 /*! @brief Format value for bitfield USB_ERRSTAT_BTSERR. */ 01680 #define BF_USB_ERRSTAT_BTSERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTSERR) & BM_USB_ERRSTAT_BTSERR) 01681 01682 /*! @brief Set the BTSERR field to a new value. */ 01683 #define BW_USB_ERRSTAT_BTSERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR) = (v)) 01684 /*@}*/ 01685 01686 /******************************************************************************* 01687 * HW_USB_ERREN - Error Interrupt Enable register 01688 ******************************************************************************/ 01689 01690 /*! 01691 * @brief HW_USB_ERREN - Error Interrupt Enable register (RW) 01692 * 01693 * Reset value: 0x00U 01694 * 01695 * Contains enable bits for each of the error interrupt sources within the USB 01696 * module. Setting any of these bits enables the respective interrupt source in 01697 * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore, 01698 * the interrupt does not typically correspond with the end of a token being 01699 * processed. This register contains the value of 0x00 after a reset. 01700 */ 01701 typedef union _hw_usb_erren 01702 { 01703 uint8_t U; 01704 struct _hw_usb_erren_bitfields 01705 { 01706 uint8_t PIDERREN : 1; /*!< [0] PIDERR Interrupt Enable */ 01707 uint8_t CRC5EOFEN : 1; /*!< [1] CRC5/EOF Interrupt Enable */ 01708 uint8_t CRC16EN : 1; /*!< [2] CRC16 Interrupt Enable */ 01709 uint8_t DFN8EN : 1; /*!< [3] DFN8 Interrupt Enable */ 01710 uint8_t BTOERREN : 1; /*!< [4] BTOERR Interrupt Enable */ 01711 uint8_t DMAERREN : 1; /*!< [5] DMAERR Interrupt Enable */ 01712 uint8_t RESERVED0 : 1; /*!< [6] */ 01713 uint8_t BTSERREN : 1; /*!< [7] BTSERR Interrupt Enable */ 01714 } B; 01715 } hw_usb_erren_t; 01716 01717 /*! 01718 * @name Constants and macros for entire USB_ERREN register 01719 */ 01720 /*@{*/ 01721 #define HW_USB_ERREN_ADDR(x) ((x) + 0x8CU) 01722 01723 #define HW_USB_ERREN(x) (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR(x)) 01724 #define HW_USB_ERREN_RD(x) (HW_USB_ERREN(x).U) 01725 #define HW_USB_ERREN_WR(x, v) (HW_USB_ERREN(x).U = (v)) 01726 #define HW_USB_ERREN_SET(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) | (v))) 01727 #define HW_USB_ERREN_CLR(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) & ~(v))) 01728 #define HW_USB_ERREN_TOG(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) ^ (v))) 01729 /*@}*/ 01730 01731 /* 01732 * Constants & macros for individual USB_ERREN bitfields 01733 */ 01734 01735 /*! 01736 * @name Register USB_ERREN, field PIDERREN[0] (RW) 01737 * 01738 * Values: 01739 * - 0 - Disables the PIDERR interrupt. 01740 * - 1 - Enters the PIDERR interrupt. 01741 */ 01742 /*@{*/ 01743 #define BP_USB_ERREN_PIDERREN (0U) /*!< Bit position for USB_ERREN_PIDERREN. */ 01744 #define BM_USB_ERREN_PIDERREN (0x01U) /*!< Bit mask for USB_ERREN_PIDERREN. */ 01745 #define BS_USB_ERREN_PIDERREN (1U) /*!< Bit field size in bits for USB_ERREN_PIDERREN. */ 01746 01747 /*! @brief Read current value of the USB_ERREN_PIDERREN field. */ 01748 #define BR_USB_ERREN_PIDERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN)) 01749 01750 /*! @brief Format value for bitfield USB_ERREN_PIDERREN. */ 01751 #define BF_USB_ERREN_PIDERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_PIDERREN) & BM_USB_ERREN_PIDERREN) 01752 01753 /*! @brief Set the PIDERREN field to a new value. */ 01754 #define BW_USB_ERREN_PIDERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN) = (v)) 01755 /*@}*/ 01756 01757 /*! 01758 * @name Register USB_ERREN, field CRC5EOFEN[1] (RW) 01759 * 01760 * Values: 01761 * - 0 - Disables the CRC5/EOF interrupt. 01762 * - 1 - Enables the CRC5/EOF interrupt. 01763 */ 01764 /*@{*/ 01765 #define BP_USB_ERREN_CRC5EOFEN (1U) /*!< Bit position for USB_ERREN_CRC5EOFEN. */ 01766 #define BM_USB_ERREN_CRC5EOFEN (0x02U) /*!< Bit mask for USB_ERREN_CRC5EOFEN. */ 01767 #define BS_USB_ERREN_CRC5EOFEN (1U) /*!< Bit field size in bits for USB_ERREN_CRC5EOFEN. */ 01768 01769 /*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */ 01770 #define BR_USB_ERREN_CRC5EOFEN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN)) 01771 01772 /*! @brief Format value for bitfield USB_ERREN_CRC5EOFEN. */ 01773 #define BF_USB_ERREN_CRC5EOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC5EOFEN) & BM_USB_ERREN_CRC5EOFEN) 01774 01775 /*! @brief Set the CRC5EOFEN field to a new value. */ 01776 #define BW_USB_ERREN_CRC5EOFEN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN) = (v)) 01777 /*@}*/ 01778 01779 /*! 01780 * @name Register USB_ERREN, field CRC16EN[2] (RW) 01781 * 01782 * Values: 01783 * - 0 - Disables the CRC16 interrupt. 01784 * - 1 - Enables the CRC16 interrupt. 01785 */ 01786 /*@{*/ 01787 #define BP_USB_ERREN_CRC16EN (2U) /*!< Bit position for USB_ERREN_CRC16EN. */ 01788 #define BM_USB_ERREN_CRC16EN (0x04U) /*!< Bit mask for USB_ERREN_CRC16EN. */ 01789 #define BS_USB_ERREN_CRC16EN (1U) /*!< Bit field size in bits for USB_ERREN_CRC16EN. */ 01790 01791 /*! @brief Read current value of the USB_ERREN_CRC16EN field. */ 01792 #define BR_USB_ERREN_CRC16EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN)) 01793 01794 /*! @brief Format value for bitfield USB_ERREN_CRC16EN. */ 01795 #define BF_USB_ERREN_CRC16EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC16EN) & BM_USB_ERREN_CRC16EN) 01796 01797 /*! @brief Set the CRC16EN field to a new value. */ 01798 #define BW_USB_ERREN_CRC16EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN) = (v)) 01799 /*@}*/ 01800 01801 /*! 01802 * @name Register USB_ERREN, field DFN8EN[3] (RW) 01803 * 01804 * Values: 01805 * - 0 - Disables the DFN8 interrupt. 01806 * - 1 - Enables the DFN8 interrupt. 01807 */ 01808 /*@{*/ 01809 #define BP_USB_ERREN_DFN8EN (3U) /*!< Bit position for USB_ERREN_DFN8EN. */ 01810 #define BM_USB_ERREN_DFN8EN (0x08U) /*!< Bit mask for USB_ERREN_DFN8EN. */ 01811 #define BS_USB_ERREN_DFN8EN (1U) /*!< Bit field size in bits for USB_ERREN_DFN8EN. */ 01812 01813 /*! @brief Read current value of the USB_ERREN_DFN8EN field. */ 01814 #define BR_USB_ERREN_DFN8EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN)) 01815 01816 /*! @brief Format value for bitfield USB_ERREN_DFN8EN. */ 01817 #define BF_USB_ERREN_DFN8EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DFN8EN) & BM_USB_ERREN_DFN8EN) 01818 01819 /*! @brief Set the DFN8EN field to a new value. */ 01820 #define BW_USB_ERREN_DFN8EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN) = (v)) 01821 /*@}*/ 01822 01823 /*! 01824 * @name Register USB_ERREN, field BTOERREN[4] (RW) 01825 * 01826 * Values: 01827 * - 0 - Disables the BTOERR interrupt. 01828 * - 1 - Enables the BTOERR interrupt. 01829 */ 01830 /*@{*/ 01831 #define BP_USB_ERREN_BTOERREN (4U) /*!< Bit position for USB_ERREN_BTOERREN. */ 01832 #define BM_USB_ERREN_BTOERREN (0x10U) /*!< Bit mask for USB_ERREN_BTOERREN. */ 01833 #define BS_USB_ERREN_BTOERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTOERREN. */ 01834 01835 /*! @brief Read current value of the USB_ERREN_BTOERREN field. */ 01836 #define BR_USB_ERREN_BTOERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN)) 01837 01838 /*! @brief Format value for bitfield USB_ERREN_BTOERREN. */ 01839 #define BF_USB_ERREN_BTOERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTOERREN) & BM_USB_ERREN_BTOERREN) 01840 01841 /*! @brief Set the BTOERREN field to a new value. */ 01842 #define BW_USB_ERREN_BTOERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN) = (v)) 01843 /*@}*/ 01844 01845 /*! 01846 * @name Register USB_ERREN, field DMAERREN[5] (RW) 01847 * 01848 * Values: 01849 * - 0 - Disables the DMAERR interrupt. 01850 * - 1 - Enables the DMAERR interrupt. 01851 */ 01852 /*@{*/ 01853 #define BP_USB_ERREN_DMAERREN (5U) /*!< Bit position for USB_ERREN_DMAERREN. */ 01854 #define BM_USB_ERREN_DMAERREN (0x20U) /*!< Bit mask for USB_ERREN_DMAERREN. */ 01855 #define BS_USB_ERREN_DMAERREN (1U) /*!< Bit field size in bits for USB_ERREN_DMAERREN. */ 01856 01857 /*! @brief Read current value of the USB_ERREN_DMAERREN field. */ 01858 #define BR_USB_ERREN_DMAERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN)) 01859 01860 /*! @brief Format value for bitfield USB_ERREN_DMAERREN. */ 01861 #define BF_USB_ERREN_DMAERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DMAERREN) & BM_USB_ERREN_DMAERREN) 01862 01863 /*! @brief Set the DMAERREN field to a new value. */ 01864 #define BW_USB_ERREN_DMAERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN) = (v)) 01865 /*@}*/ 01866 01867 /*! 01868 * @name Register USB_ERREN, field BTSERREN[7] (RW) 01869 * 01870 * Values: 01871 * - 0 - Disables the BTSERR interrupt. 01872 * - 1 - Enables the BTSERR interrupt. 01873 */ 01874 /*@{*/ 01875 #define BP_USB_ERREN_BTSERREN (7U) /*!< Bit position for USB_ERREN_BTSERREN. */ 01876 #define BM_USB_ERREN_BTSERREN (0x80U) /*!< Bit mask for USB_ERREN_BTSERREN. */ 01877 #define BS_USB_ERREN_BTSERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTSERREN. */ 01878 01879 /*! @brief Read current value of the USB_ERREN_BTSERREN field. */ 01880 #define BR_USB_ERREN_BTSERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN)) 01881 01882 /*! @brief Format value for bitfield USB_ERREN_BTSERREN. */ 01883 #define BF_USB_ERREN_BTSERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTSERREN) & BM_USB_ERREN_BTSERREN) 01884 01885 /*! @brief Set the BTSERREN field to a new value. */ 01886 #define BW_USB_ERREN_BTSERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN) = (v)) 01887 /*@}*/ 01888 01889 /******************************************************************************* 01890 * HW_USB_STAT - Status register 01891 ******************************************************************************/ 01892 01893 /*! 01894 * @brief HW_USB_STAT - Status register (RO) 01895 * 01896 * Reset value: 0x00U 01897 * 01898 * Reports the transaction status within the USB module. When the processor's 01899 * interrupt controller has received a TOKDNE, interrupt the Status Register must 01900 * be read to determine the status of the previous endpoint communication. The 01901 * data in the status register is valid when TOKDNE interrupt is asserted. The 01902 * Status register is actually a read window into a status FIFO maintained by the USB 01903 * module. When the USB module uses a BD, it updates the Status register. If 01904 * another USB transaction is performed before the TOKDNE interrupt is serviced, the 01905 * USB module stores the status of the next transaction in the STAT FIFO. Thus 01906 * STAT is actually a four byte FIFO that allows the processor core to process one 01907 * transaction while the SIE is processing the next transaction. Clearing the 01908 * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents 01909 * of the next STAT value. If the data in the STAT holding register is valid, the 01910 * SIE immediately reasserts to TOKDNE interrupt. 01911 */ 01912 typedef union _hw_usb_stat 01913 { 01914 uint8_t U; 01915 struct _hw_usb_stat_bitfields 01916 { 01917 uint8_t RESERVED0 : 2; /*!< [1:0] */ 01918 uint8_t ODD : 1; /*!< [2] */ 01919 uint8_t TX : 1; /*!< [3] Transmit Indicator */ 01920 uint8_t ENDP : 4; /*!< [7:4] */ 01921 } B; 01922 } hw_usb_stat_t; 01923 01924 /*! 01925 * @name Constants and macros for entire USB_STAT register 01926 */ 01927 /*@{*/ 01928 #define HW_USB_STAT_ADDR(x) ((x) + 0x90U) 01929 01930 #define HW_USB_STAT(x) (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR(x)) 01931 #define HW_USB_STAT_RD(x) (HW_USB_STAT(x).U) 01932 /*@}*/ 01933 01934 /* 01935 * Constants & macros for individual USB_STAT bitfields 01936 */ 01937 01938 /*! 01939 * @name Register USB_STAT, field ODD[2] (RO) 01940 * 01941 * This bit is set if the last buffer descriptor updated was in the odd bank of 01942 * the BDT. 01943 */ 01944 /*@{*/ 01945 #define BP_USB_STAT_ODD (2U) /*!< Bit position for USB_STAT_ODD. */ 01946 #define BM_USB_STAT_ODD (0x04U) /*!< Bit mask for USB_STAT_ODD. */ 01947 #define BS_USB_STAT_ODD (1U) /*!< Bit field size in bits for USB_STAT_ODD. */ 01948 01949 /*! @brief Read current value of the USB_STAT_ODD field. */ 01950 #define BR_USB_STAT_ODD(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_ODD)) 01951 /*@}*/ 01952 01953 /*! 01954 * @name Register USB_STAT, field TX[3] (RO) 01955 * 01956 * Values: 01957 * - 0 - The most recent transaction was a receive operation. 01958 * - 1 - The most recent transaction was a transmit operation. 01959 */ 01960 /*@{*/ 01961 #define BP_USB_STAT_TX (3U) /*!< Bit position for USB_STAT_TX. */ 01962 #define BM_USB_STAT_TX (0x08U) /*!< Bit mask for USB_STAT_TX. */ 01963 #define BS_USB_STAT_TX (1U) /*!< Bit field size in bits for USB_STAT_TX. */ 01964 01965 /*! @brief Read current value of the USB_STAT_TX field. */ 01966 #define BR_USB_STAT_TX(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_TX)) 01967 /*@}*/ 01968 01969 /*! 01970 * @name Register USB_STAT, field ENDP[7:4] (RO) 01971 * 01972 * This four-bit field encodes the endpoint address that received or transmitted 01973 * the previous token. This allows the processor core to determine the BDT entry 01974 * that was updated by the last USB transaction. 01975 */ 01976 /*@{*/ 01977 #define BP_USB_STAT_ENDP (4U) /*!< Bit position for USB_STAT_ENDP. */ 01978 #define BM_USB_STAT_ENDP (0xF0U) /*!< Bit mask for USB_STAT_ENDP. */ 01979 #define BS_USB_STAT_ENDP (4U) /*!< Bit field size in bits for USB_STAT_ENDP. */ 01980 01981 /*! @brief Read current value of the USB_STAT_ENDP field. */ 01982 #define BR_USB_STAT_ENDP(x) (HW_USB_STAT(x).B.ENDP) 01983 /*@}*/ 01984 01985 /******************************************************************************* 01986 * HW_USB_CTL - Control register 01987 ******************************************************************************/ 01988 01989 /*! 01990 * @brief HW_USB_CTL - Control register (RW) 01991 * 01992 * Reset value: 0x00U 01993 * 01994 * Provides various control and configuration information for the USB module. 01995 */ 01996 typedef union _hw_usb_ctl 01997 { 01998 uint8_t U; 01999 struct _hw_usb_ctl_bitfields 02000 { 02001 uint8_t USBENSOFEN : 1; /*!< [0] USB Enable */ 02002 uint8_t ODDRST : 1; /*!< [1] */ 02003 uint8_t RESUME : 1; /*!< [2] */ 02004 uint8_t HOSTMODEEN : 1; /*!< [3] */ 02005 uint8_t RESET : 1; /*!< [4] */ 02006 uint8_t TXSUSPENDTOKENBUSY : 1; /*!< [5] */ 02007 uint8_t SE0 : 1; /*!< [6] Live USB Single Ended Zero signal */ 02008 uint8_t JSTATE : 1; /*!< [7] Live USB differential receiver JSTATE 02009 * signal */ 02010 } B; 02011 } hw_usb_ctl_t; 02012 02013 /*! 02014 * @name Constants and macros for entire USB_CTL register 02015 */ 02016 /*@{*/ 02017 #define HW_USB_CTL_ADDR(x) ((x) + 0x94U) 02018 02019 #define HW_USB_CTL(x) (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR(x)) 02020 #define HW_USB_CTL_RD(x) (HW_USB_CTL(x).U) 02021 #define HW_USB_CTL_WR(x, v) (HW_USB_CTL(x).U = (v)) 02022 #define HW_USB_CTL_SET(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) | (v))) 02023 #define HW_USB_CTL_CLR(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) & ~(v))) 02024 #define HW_USB_CTL_TOG(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) ^ (v))) 02025 /*@}*/ 02026 02027 /* 02028 * Constants & macros for individual USB_CTL bitfields 02029 */ 02030 02031 /*! 02032 * @name Register USB_CTL, field USBENSOFEN[0] (RW) 02033 * 02034 * Setting this bit enables the USB-FS to operate; clearing it disables the 02035 * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs. 02036 * Therefore, setting this bit resets much of the logic in the SIE. When host mode 02037 * is enabled, clearing this bit causes the SIE to stop sending SOF tokens. 02038 * 02039 * Values: 02040 * - 0 - Disables the USB Module. 02041 * - 1 - Enables the USB Module. 02042 */ 02043 /*@{*/ 02044 #define BP_USB_CTL_USBENSOFEN (0U) /*!< Bit position for USB_CTL_USBENSOFEN. */ 02045 #define BM_USB_CTL_USBENSOFEN (0x01U) /*!< Bit mask for USB_CTL_USBENSOFEN. */ 02046 #define BS_USB_CTL_USBENSOFEN (1U) /*!< Bit field size in bits for USB_CTL_USBENSOFEN. */ 02047 02048 /*! @brief Read current value of the USB_CTL_USBENSOFEN field. */ 02049 #define BR_USB_CTL_USBENSOFEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN)) 02050 02051 /*! @brief Format value for bitfield USB_CTL_USBENSOFEN. */ 02052 #define BF_USB_CTL_USBENSOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_USBENSOFEN) & BM_USB_CTL_USBENSOFEN) 02053 02054 /*! @brief Set the USBENSOFEN field to a new value. */ 02055 #define BW_USB_CTL_USBENSOFEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN) = (v)) 02056 /*@}*/ 02057 02058 /*! 02059 * @name Register USB_CTL, field ODDRST[1] (RW) 02060 * 02061 * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which 02062 * then specifies the EVEN BDT bank. 02063 */ 02064 /*@{*/ 02065 #define BP_USB_CTL_ODDRST (1U) /*!< Bit position for USB_CTL_ODDRST. */ 02066 #define BM_USB_CTL_ODDRST (0x02U) /*!< Bit mask for USB_CTL_ODDRST. */ 02067 #define BS_USB_CTL_ODDRST (1U) /*!< Bit field size in bits for USB_CTL_ODDRST. */ 02068 02069 /*! @brief Read current value of the USB_CTL_ODDRST field. */ 02070 #define BR_USB_CTL_ODDRST(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST)) 02071 02072 /*! @brief Format value for bitfield USB_CTL_ODDRST. */ 02073 #define BF_USB_CTL_ODDRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_ODDRST) & BM_USB_CTL_ODDRST) 02074 02075 /*! @brief Set the ODDRST field to a new value. */ 02076 #define BW_USB_CTL_ODDRST(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST) = (v)) 02077 /*@}*/ 02078 02079 /*! 02080 * @name Register USB_CTL, field RESUME[2] (RW) 02081 * 02082 * When set to 1 this bit enables the USB Module to execute resume signaling. 02083 * This allows the USB Module to perform remote wake-up. Software must set RESUME 02084 * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN 02085 * bit is set, the USB module appends a Low Speed End of Packet to the Resume 02086 * signaling when the RESUME bit is cleared. For more information on RESUME 02087 * signaling see Section 7.1.4.5 of the USB specification version 1.0. 02088 */ 02089 /*@{*/ 02090 #define BP_USB_CTL_RESUME (2U) /*!< Bit position for USB_CTL_RESUME. */ 02091 #define BM_USB_CTL_RESUME (0x04U) /*!< Bit mask for USB_CTL_RESUME. */ 02092 #define BS_USB_CTL_RESUME (1U) /*!< Bit field size in bits for USB_CTL_RESUME. */ 02093 02094 /*! @brief Read current value of the USB_CTL_RESUME field. */ 02095 #define BR_USB_CTL_RESUME(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME)) 02096 02097 /*! @brief Format value for bitfield USB_CTL_RESUME. */ 02098 #define BF_USB_CTL_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESUME) & BM_USB_CTL_RESUME) 02099 02100 /*! @brief Set the RESUME field to a new value. */ 02101 #define BW_USB_CTL_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME) = (v)) 02102 /*@}*/ 02103 02104 /*! 02105 * @name Register USB_CTL, field HOSTMODEEN[3] (RW) 02106 * 02107 * When set to 1, this bit enables the USB Module to operate in Host mode. In 02108 * host mode, the USB module performs USB transactions under the programmed control 02109 * of the host processor. 02110 */ 02111 /*@{*/ 02112 #define BP_USB_CTL_HOSTMODEEN (3U) /*!< Bit position for USB_CTL_HOSTMODEEN. */ 02113 #define BM_USB_CTL_HOSTMODEEN (0x08U) /*!< Bit mask for USB_CTL_HOSTMODEEN. */ 02114 #define BS_USB_CTL_HOSTMODEEN (1U) /*!< Bit field size in bits for USB_CTL_HOSTMODEEN. */ 02115 02116 /*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */ 02117 #define BR_USB_CTL_HOSTMODEEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN)) 02118 02119 /*! @brief Format value for bitfield USB_CTL_HOSTMODEEN. */ 02120 #define BF_USB_CTL_HOSTMODEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_HOSTMODEEN) & BM_USB_CTL_HOSTMODEEN) 02121 02122 /*! @brief Set the HOSTMODEEN field to a new value. */ 02123 #define BW_USB_CTL_HOSTMODEEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN) = (v)) 02124 /*@}*/ 02125 02126 /*! 02127 * @name Register USB_CTL, field RESET[4] (RW) 02128 * 02129 * Setting this bit enables the USB Module to generate USB reset signaling. This 02130 * allows the USB Module to reset USB peripherals. This control signal is only 02131 * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the 02132 * required amount of time and then clear it to 0 to end reset signaling. For more 02133 * information on reset signaling see Section 7.1.4.3 of the USB specification version 02134 * 1.0. 02135 */ 02136 /*@{*/ 02137 #define BP_USB_CTL_RESET (4U) /*!< Bit position for USB_CTL_RESET. */ 02138 #define BM_USB_CTL_RESET (0x10U) /*!< Bit mask for USB_CTL_RESET. */ 02139 #define BS_USB_CTL_RESET (1U) /*!< Bit field size in bits for USB_CTL_RESET. */ 02140 02141 /*! @brief Read current value of the USB_CTL_RESET field. */ 02142 #define BR_USB_CTL_RESET(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET)) 02143 02144 /*! @brief Format value for bitfield USB_CTL_RESET. */ 02145 #define BF_USB_CTL_RESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESET) & BM_USB_CTL_RESET) 02146 02147 /*! @brief Set the RESET field to a new value. */ 02148 #define BW_USB_CTL_RESET(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET) = (v)) 02149 /*@}*/ 02150 02151 /*! 02152 * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW) 02153 * 02154 * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB 02155 * token. Software must not write more token commands to the Token Register when 02156 * TOKEN_BUSY is set. Software should check this field before writing any tokens 02157 * to the Token Register to ensure that token commands are not lost. In Target 02158 * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and 02159 * reception. Clearing this bit allows the SIE to continue token processing. This bit 02160 * is set by the SIE when a SETUP Token is received allowing software to dequeue 02161 * any pending packet transactions in the BDT before resuming token processing. 02162 */ 02163 /*@{*/ 02164 #define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) /*!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY. */ 02165 #define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) /*!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY. */ 02166 #define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) /*!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY. */ 02167 02168 /*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */ 02169 #define BR_USB_CTL_TXSUSPENDTOKENBUSY(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY)) 02170 02171 /*! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY. */ 02172 #define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_TXSUSPENDTOKENBUSY) & BM_USB_CTL_TXSUSPENDTOKENBUSY) 02173 02174 /*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */ 02175 #define BW_USB_CTL_TXSUSPENDTOKENBUSY(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v)) 02176 /*@}*/ 02177 02178 /*! 02179 * @name Register USB_CTL, field SE0[6] (RW) 02180 */ 02181 /*@{*/ 02182 #define BP_USB_CTL_SE0 (6U) /*!< Bit position for USB_CTL_SE0. */ 02183 #define BM_USB_CTL_SE0 (0x40U) /*!< Bit mask for USB_CTL_SE0. */ 02184 #define BS_USB_CTL_SE0 (1U) /*!< Bit field size in bits for USB_CTL_SE0. */ 02185 02186 /*! @brief Read current value of the USB_CTL_SE0 field. */ 02187 #define BR_USB_CTL_SE0(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0)) 02188 02189 /*! @brief Format value for bitfield USB_CTL_SE0. */ 02190 #define BF_USB_CTL_SE0(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_SE0) & BM_USB_CTL_SE0) 02191 02192 /*! @brief Set the SE0 field to a new value. */ 02193 #define BW_USB_CTL_SE0(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0) = (v)) 02194 /*@}*/ 02195 02196 /*! 02197 * @name Register USB_CTL, field JSTATE[7] (RW) 02198 * 02199 * The polarity of this signal is affected by the current state of LSEN . 02200 */ 02201 /*@{*/ 02202 #define BP_USB_CTL_JSTATE (7U) /*!< Bit position for USB_CTL_JSTATE. */ 02203 #define BM_USB_CTL_JSTATE (0x80U) /*!< Bit mask for USB_CTL_JSTATE. */ 02204 #define BS_USB_CTL_JSTATE (1U) /*!< Bit field size in bits for USB_CTL_JSTATE. */ 02205 02206 /*! @brief Read current value of the USB_CTL_JSTATE field. */ 02207 #define BR_USB_CTL_JSTATE(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE)) 02208 02209 /*! @brief Format value for bitfield USB_CTL_JSTATE. */ 02210 #define BF_USB_CTL_JSTATE(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_JSTATE) & BM_USB_CTL_JSTATE) 02211 02212 /*! @brief Set the JSTATE field to a new value. */ 02213 #define BW_USB_CTL_JSTATE(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE) = (v)) 02214 /*@}*/ 02215 02216 /******************************************************************************* 02217 * HW_USB_ADDR - Address register 02218 ******************************************************************************/ 02219 02220 /*! 02221 * @brief HW_USB_ADDR - Address register (RW) 02222 * 02223 * Reset value: 0x00U 02224 * 02225 * Holds the unique USB address that the USB module decodes when in Peripheral 02226 * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module 02227 * transmits this address with a TOKEN packet. This enables the USB module to 02228 * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1. 02229 * The Address register is reset to 0x00 after the reset input becomes active or 02230 * the USB module decodes a USB reset signal. This action initializes the Address 02231 * register to decode address 0x00 as required by the USB specification. 02232 */ 02233 typedef union _hw_usb_addr 02234 { 02235 uint8_t U; 02236 struct _hw_usb_addr_bitfields 02237 { 02238 uint8_t ADDR : 7; /*!< [6:0] USB Address */ 02239 uint8_t LSEN : 1; /*!< [7] Low Speed Enable bit */ 02240 } B; 02241 } hw_usb_addr_t; 02242 02243 /*! 02244 * @name Constants and macros for entire USB_ADDR register 02245 */ 02246 /*@{*/ 02247 #define HW_USB_ADDR_ADDR(x) ((x) + 0x98U) 02248 02249 #define HW_USB_ADDR(x) (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR(x)) 02250 #define HW_USB_ADDR_RD(x) (HW_USB_ADDR(x).U) 02251 #define HW_USB_ADDR_WR(x, v) (HW_USB_ADDR(x).U = (v)) 02252 #define HW_USB_ADDR_SET(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) | (v))) 02253 #define HW_USB_ADDR_CLR(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) & ~(v))) 02254 #define HW_USB_ADDR_TOG(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) ^ (v))) 02255 /*@}*/ 02256 02257 /* 02258 * Constants & macros for individual USB_ADDR bitfields 02259 */ 02260 02261 /*! 02262 * @name Register USB_ADDR, field ADDR[6:0] (RW) 02263 * 02264 * Defines the USB address that the USB module decodes in peripheral mode, or 02265 * transmits when in host mode. 02266 */ 02267 /*@{*/ 02268 #define BP_USB_ADDR_ADDR (0U) /*!< Bit position for USB_ADDR_ADDR. */ 02269 #define BM_USB_ADDR_ADDR (0x7FU) /*!< Bit mask for USB_ADDR_ADDR. */ 02270 #define BS_USB_ADDR_ADDR (7U) /*!< Bit field size in bits for USB_ADDR_ADDR. */ 02271 02272 /*! @brief Read current value of the USB_ADDR_ADDR field. */ 02273 #define BR_USB_ADDR_ADDR(x) (HW_USB_ADDR(x).B.ADDR) 02274 02275 /*! @brief Format value for bitfield USB_ADDR_ADDR. */ 02276 #define BF_USB_ADDR_ADDR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_ADDR) & BM_USB_ADDR_ADDR) 02277 02278 /*! @brief Set the ADDR field to a new value. */ 02279 #define BW_USB_ADDR_ADDR(x, v) (HW_USB_ADDR_WR(x, (HW_USB_ADDR_RD(x) & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v))) 02280 /*@}*/ 02281 02282 /*! 02283 * @name Register USB_ADDR, field LSEN[7] (RW) 02284 * 02285 * Informs the USB module that the next token command written to the token 02286 * register must be performed at low speed. This enables the USB module to perform the 02287 * necessary preamble required for low-speed data transmissions. 02288 */ 02289 /*@{*/ 02290 #define BP_USB_ADDR_LSEN (7U) /*!< Bit position for USB_ADDR_LSEN. */ 02291 #define BM_USB_ADDR_LSEN (0x80U) /*!< Bit mask for USB_ADDR_LSEN. */ 02292 #define BS_USB_ADDR_LSEN (1U) /*!< Bit field size in bits for USB_ADDR_LSEN. */ 02293 02294 /*! @brief Read current value of the USB_ADDR_LSEN field. */ 02295 #define BR_USB_ADDR_LSEN(x) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN)) 02296 02297 /*! @brief Format value for bitfield USB_ADDR_LSEN. */ 02298 #define BF_USB_ADDR_LSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_LSEN) & BM_USB_ADDR_LSEN) 02299 02300 /*! @brief Set the LSEN field to a new value. */ 02301 #define BW_USB_ADDR_LSEN(x, v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN) = (v)) 02302 /*@}*/ 02303 02304 /******************************************************************************* 02305 * HW_USB_BDTPAGE1 - BDT Page register 1 02306 ******************************************************************************/ 02307 02308 /*! 02309 * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW) 02310 * 02311 * Reset value: 0x00U 02312 * 02313 * Provides address bits 15 through 9 of the base address where the current 02314 * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor 02315 * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so 02316 * bits 8 through 0 of the base address are always zero. 02317 */ 02318 typedef union _hw_usb_bdtpage1 02319 { 02320 uint8_t U; 02321 struct _hw_usb_bdtpage1_bitfields 02322 { 02323 uint8_t RESERVED0 : 1; /*!< [0] */ 02324 uint8_t BDTBA : 7; /*!< [7:1] */ 02325 } B; 02326 } hw_usb_bdtpage1_t; 02327 02328 /*! 02329 * @name Constants and macros for entire USB_BDTPAGE1 register 02330 */ 02331 /*@{*/ 02332 #define HW_USB_BDTPAGE1_ADDR(x) ((x) + 0x9CU) 02333 02334 #define HW_USB_BDTPAGE1(x) (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR(x)) 02335 #define HW_USB_BDTPAGE1_RD(x) (HW_USB_BDTPAGE1(x).U) 02336 #define HW_USB_BDTPAGE1_WR(x, v) (HW_USB_BDTPAGE1(x).U = (v)) 02337 #define HW_USB_BDTPAGE1_SET(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) | (v))) 02338 #define HW_USB_BDTPAGE1_CLR(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) & ~(v))) 02339 #define HW_USB_BDTPAGE1_TOG(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) ^ (v))) 02340 /*@}*/ 02341 02342 /* 02343 * Constants & macros for individual USB_BDTPAGE1 bitfields 02344 */ 02345 02346 /*! 02347 * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW) 02348 * 02349 * Provides address bits 15 through 9 of the BDT base address. 02350 */ 02351 /*@{*/ 02352 #define BP_USB_BDTPAGE1_BDTBA (1U) /*!< Bit position for USB_BDTPAGE1_BDTBA. */ 02353 #define BM_USB_BDTPAGE1_BDTBA (0xFEU) /*!< Bit mask for USB_BDTPAGE1_BDTBA. */ 02354 #define BS_USB_BDTPAGE1_BDTBA (7U) /*!< Bit field size in bits for USB_BDTPAGE1_BDTBA. */ 02355 02356 /*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */ 02357 #define BR_USB_BDTPAGE1_BDTBA(x) (HW_USB_BDTPAGE1(x).B.BDTBA) 02358 02359 /*! @brief Format value for bitfield USB_BDTPAGE1_BDTBA. */ 02360 #define BF_USB_BDTPAGE1_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE1_BDTBA) & BM_USB_BDTPAGE1_BDTBA) 02361 02362 /*! @brief Set the BDTBA field to a new value. */ 02363 #define BW_USB_BDTPAGE1_BDTBA(x, v) (HW_USB_BDTPAGE1_WR(x, (HW_USB_BDTPAGE1_RD(x) & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v))) 02364 /*@}*/ 02365 02366 /******************************************************************************* 02367 * HW_USB_FRMNUML - Frame Number register Low 02368 ******************************************************************************/ 02369 02370 /*! 02371 * @brief HW_USB_FRMNUML - Frame Number register Low (RW) 02372 * 02373 * Reset value: 0x00U 02374 * 02375 * The Frame Number registers (low and high) contain the 11-bit frame number. 02376 * These registers are updated with the current frame number whenever a SOF TOKEN 02377 * is received. 02378 */ 02379 typedef union _hw_usb_frmnuml 02380 { 02381 uint8_t U; 02382 struct _hw_usb_frmnuml_bitfields 02383 { 02384 uint8_t FRM : 8; /*!< [7:0] */ 02385 } B; 02386 } hw_usb_frmnuml_t; 02387 02388 /*! 02389 * @name Constants and macros for entire USB_FRMNUML register 02390 */ 02391 /*@{*/ 02392 #define HW_USB_FRMNUML_ADDR(x) ((x) + 0xA0U) 02393 02394 #define HW_USB_FRMNUML(x) (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR(x)) 02395 #define HW_USB_FRMNUML_RD(x) (HW_USB_FRMNUML(x).U) 02396 #define HW_USB_FRMNUML_WR(x, v) (HW_USB_FRMNUML(x).U = (v)) 02397 #define HW_USB_FRMNUML_SET(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) | (v))) 02398 #define HW_USB_FRMNUML_CLR(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) & ~(v))) 02399 #define HW_USB_FRMNUML_TOG(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) ^ (v))) 02400 /*@}*/ 02401 02402 /* 02403 * Constants & macros for individual USB_FRMNUML bitfields 02404 */ 02405 02406 /*! 02407 * @name Register USB_FRMNUML, field FRM[7:0] (RW) 02408 * 02409 * This 8-bit field and the 3-bit field in the Frame Number Register High are 02410 * used to compute the address where the current Buffer Descriptor Table (BDT) 02411 * resides in system memory. 02412 */ 02413 /*@{*/ 02414 #define BP_USB_FRMNUML_FRM (0U) /*!< Bit position for USB_FRMNUML_FRM. */ 02415 #define BM_USB_FRMNUML_FRM (0xFFU) /*!< Bit mask for USB_FRMNUML_FRM. */ 02416 #define BS_USB_FRMNUML_FRM (8U) /*!< Bit field size in bits for USB_FRMNUML_FRM. */ 02417 02418 /*! @brief Read current value of the USB_FRMNUML_FRM field. */ 02419 #define BR_USB_FRMNUML_FRM(x) (HW_USB_FRMNUML(x).U) 02420 02421 /*! @brief Format value for bitfield USB_FRMNUML_FRM. */ 02422 #define BF_USB_FRMNUML_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUML_FRM) & BM_USB_FRMNUML_FRM) 02423 02424 /*! @brief Set the FRM field to a new value. */ 02425 #define BW_USB_FRMNUML_FRM(x, v) (HW_USB_FRMNUML_WR(x, v)) 02426 /*@}*/ 02427 02428 /******************************************************************************* 02429 * HW_USB_FRMNUMH - Frame Number register High 02430 ******************************************************************************/ 02431 02432 /*! 02433 * @brief HW_USB_FRMNUMH - Frame Number register High (RW) 02434 * 02435 * Reset value: 0x00U 02436 * 02437 * The Frame Number registers (low and high) contain the 11-bit frame number. 02438 * These registers are updated with the current frame number whenever a SOF TOKEN 02439 * is received. 02440 */ 02441 typedef union _hw_usb_frmnumh 02442 { 02443 uint8_t U; 02444 struct _hw_usb_frmnumh_bitfields 02445 { 02446 uint8_t FRM : 3; /*!< [2:0] */ 02447 uint8_t RESERVED0 : 5; /*!< [7:3] */ 02448 } B; 02449 } hw_usb_frmnumh_t; 02450 02451 /*! 02452 * @name Constants and macros for entire USB_FRMNUMH register 02453 */ 02454 /*@{*/ 02455 #define HW_USB_FRMNUMH_ADDR(x) ((x) + 0xA4U) 02456 02457 #define HW_USB_FRMNUMH(x) (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR(x)) 02458 #define HW_USB_FRMNUMH_RD(x) (HW_USB_FRMNUMH(x).U) 02459 #define HW_USB_FRMNUMH_WR(x, v) (HW_USB_FRMNUMH(x).U = (v)) 02460 #define HW_USB_FRMNUMH_SET(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) | (v))) 02461 #define HW_USB_FRMNUMH_CLR(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) & ~(v))) 02462 #define HW_USB_FRMNUMH_TOG(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) ^ (v))) 02463 /*@}*/ 02464 02465 /* 02466 * Constants & macros for individual USB_FRMNUMH bitfields 02467 */ 02468 02469 /*! 02470 * @name Register USB_FRMNUMH, field FRM[2:0] (RW) 02471 * 02472 * This 3-bit field and the 8-bit field in the Frame Number Register Low are 02473 * used to compute the address where the current Buffer Descriptor Table (BDT) 02474 * resides in system memory. 02475 */ 02476 /*@{*/ 02477 #define BP_USB_FRMNUMH_FRM (0U) /*!< Bit position for USB_FRMNUMH_FRM. */ 02478 #define BM_USB_FRMNUMH_FRM (0x07U) /*!< Bit mask for USB_FRMNUMH_FRM. */ 02479 #define BS_USB_FRMNUMH_FRM (3U) /*!< Bit field size in bits for USB_FRMNUMH_FRM. */ 02480 02481 /*! @brief Read current value of the USB_FRMNUMH_FRM field. */ 02482 #define BR_USB_FRMNUMH_FRM(x) (HW_USB_FRMNUMH(x).B.FRM) 02483 02484 /*! @brief Format value for bitfield USB_FRMNUMH_FRM. */ 02485 #define BF_USB_FRMNUMH_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUMH_FRM) & BM_USB_FRMNUMH_FRM) 02486 02487 /*! @brief Set the FRM field to a new value. */ 02488 #define BW_USB_FRMNUMH_FRM(x, v) (HW_USB_FRMNUMH_WR(x, (HW_USB_FRMNUMH_RD(x) & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v))) 02489 /*@}*/ 02490 02491 /******************************************************************************* 02492 * HW_USB_TOKEN - Token register 02493 ******************************************************************************/ 02494 02495 /*! 02496 * @brief HW_USB_TOKEN - Token register (RW) 02497 * 02498 * Reset value: 0x00U 02499 * 02500 * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the 02501 * software needs to execute a USB transaction to a peripheral, it writes the 02502 * TOKEN type and endpoint to this register. After this register has been written, 02503 * the USB module begins the specified USB transaction to the address contained in 02504 * the address register. The processor core must always check that the 02505 * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register. 02506 * This ensures that the token commands are not overwritten before they can be 02507 * executed. The address register and endpoint control register 0 are also used when 02508 * performing a token command and therefore must also be written before the 02509 * Token Register. The address register is used to select the USB peripheral address 02510 * transmitted by the token command. The endpoint control register determines the 02511 * handshake and retry policies used during the transfer. 02512 */ 02513 typedef union _hw_usb_token 02514 { 02515 uint8_t U; 02516 struct _hw_usb_token_bitfields 02517 { 02518 uint8_t TOKENENDPT : 4; /*!< [3:0] */ 02519 uint8_t TOKENPID : 4; /*!< [7:4] */ 02520 } B; 02521 } hw_usb_token_t; 02522 02523 /*! 02524 * @name Constants and macros for entire USB_TOKEN register 02525 */ 02526 /*@{*/ 02527 #define HW_USB_TOKEN_ADDR(x) ((x) + 0xA8U) 02528 02529 #define HW_USB_TOKEN(x) (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR(x)) 02530 #define HW_USB_TOKEN_RD(x) (HW_USB_TOKEN(x).U) 02531 #define HW_USB_TOKEN_WR(x, v) (HW_USB_TOKEN(x).U = (v)) 02532 #define HW_USB_TOKEN_SET(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) | (v))) 02533 #define HW_USB_TOKEN_CLR(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) & ~(v))) 02534 #define HW_USB_TOKEN_TOG(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) ^ (v))) 02535 /*@}*/ 02536 02537 /* 02538 * Constants & macros for individual USB_TOKEN bitfields 02539 */ 02540 02541 /*! 02542 * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW) 02543 * 02544 * Holds the Endpoint address for the token command. The four bit value written 02545 * must be a valid endpoint. 02546 */ 02547 /*@{*/ 02548 #define BP_USB_TOKEN_TOKENENDPT (0U) /*!< Bit position for USB_TOKEN_TOKENENDPT. */ 02549 #define BM_USB_TOKEN_TOKENENDPT (0x0FU) /*!< Bit mask for USB_TOKEN_TOKENENDPT. */ 02550 #define BS_USB_TOKEN_TOKENENDPT (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENENDPT. */ 02551 02552 /*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */ 02553 #define BR_USB_TOKEN_TOKENENDPT(x) (HW_USB_TOKEN(x).B.TOKENENDPT) 02554 02555 /*! @brief Format value for bitfield USB_TOKEN_TOKENENDPT. */ 02556 #define BF_USB_TOKEN_TOKENENDPT(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENENDPT) & BM_USB_TOKEN_TOKENENDPT) 02557 02558 /*! @brief Set the TOKENENDPT field to a new value. */ 02559 #define BW_USB_TOKEN_TOKENENDPT(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v))) 02560 /*@}*/ 02561 02562 /*! 02563 * @name Register USB_TOKEN, field TOKENPID[7:4] (RW) 02564 * 02565 * Contains the token type executed by the USB module. 02566 * 02567 * Values: 02568 * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction. 02569 * - 1001 - IN Token. USB Module performs an In (RX) transaction. 02570 * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction 02571 */ 02572 /*@{*/ 02573 #define BP_USB_TOKEN_TOKENPID (4U) /*!< Bit position for USB_TOKEN_TOKENPID. */ 02574 #define BM_USB_TOKEN_TOKENPID (0xF0U) /*!< Bit mask for USB_TOKEN_TOKENPID. */ 02575 #define BS_USB_TOKEN_TOKENPID (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENPID. */ 02576 02577 /*! @brief Read current value of the USB_TOKEN_TOKENPID field. */ 02578 #define BR_USB_TOKEN_TOKENPID(x) (HW_USB_TOKEN(x).B.TOKENPID) 02579 02580 /*! @brief Format value for bitfield USB_TOKEN_TOKENPID. */ 02581 #define BF_USB_TOKEN_TOKENPID(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENPID) & BM_USB_TOKEN_TOKENPID) 02582 02583 /*! @brief Set the TOKENPID field to a new value. */ 02584 #define BW_USB_TOKEN_TOKENPID(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v))) 02585 /*@}*/ 02586 02587 /******************************************************************************* 02588 * HW_USB_SOFTHLD - SOF Threshold register 02589 ******************************************************************************/ 02590 02591 /*! 02592 * @brief HW_USB_SOFTHLD - SOF Threshold register (RW) 02593 * 02594 * Reset value: 0x00U 02595 * 02596 * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in 02597 * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The 02598 * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with 02599 * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF) 02600 * token is transmitted. The SOF threshold register is used to program the number 02601 * of USB byte times before the SOF to stop initiating token packet transactions. 02602 * This register must be set to a value that ensures that other packets are not 02603 * actively being transmitted when the SOF time counts to zero. When the SOF 02604 * counter reaches the threshold value, no more tokens are transmitted until after the 02605 * SOF has been transmitted. The value programmed into the threshold register 02606 * must reserve enough time to ensure the worst case transaction completes. In 02607 * general the worst case transaction is an IN token followed by a data packet from 02608 * the target followed by the response from the host. The actual time required is 02609 * a function of the maximum packet size on the bus. Typical values for the SOF 02610 * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26; 02611 * 8-byte packets=18. 02612 */ 02613 typedef union _hw_usb_softhld 02614 { 02615 uint8_t U; 02616 struct _hw_usb_softhld_bitfields 02617 { 02618 uint8_t CNT : 8; /*!< [7:0] */ 02619 } B; 02620 } hw_usb_softhld_t; 02621 02622 /*! 02623 * @name Constants and macros for entire USB_SOFTHLD register 02624 */ 02625 /*@{*/ 02626 #define HW_USB_SOFTHLD_ADDR(x) ((x) + 0xACU) 02627 02628 #define HW_USB_SOFTHLD(x) (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR(x)) 02629 #define HW_USB_SOFTHLD_RD(x) (HW_USB_SOFTHLD(x).U) 02630 #define HW_USB_SOFTHLD_WR(x, v) (HW_USB_SOFTHLD(x).U = (v)) 02631 #define HW_USB_SOFTHLD_SET(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) | (v))) 02632 #define HW_USB_SOFTHLD_CLR(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) & ~(v))) 02633 #define HW_USB_SOFTHLD_TOG(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) ^ (v))) 02634 /*@}*/ 02635 02636 /* 02637 * Constants & macros for individual USB_SOFTHLD bitfields 02638 */ 02639 02640 /*! 02641 * @name Register USB_SOFTHLD, field CNT[7:0] (RW) 02642 * 02643 * Represents the SOF count threshold in byte times. 02644 */ 02645 /*@{*/ 02646 #define BP_USB_SOFTHLD_CNT (0U) /*!< Bit position for USB_SOFTHLD_CNT. */ 02647 #define BM_USB_SOFTHLD_CNT (0xFFU) /*!< Bit mask for USB_SOFTHLD_CNT. */ 02648 #define BS_USB_SOFTHLD_CNT (8U) /*!< Bit field size in bits for USB_SOFTHLD_CNT. */ 02649 02650 /*! @brief Read current value of the USB_SOFTHLD_CNT field. */ 02651 #define BR_USB_SOFTHLD_CNT(x) (HW_USB_SOFTHLD(x).U) 02652 02653 /*! @brief Format value for bitfield USB_SOFTHLD_CNT. */ 02654 #define BF_USB_SOFTHLD_CNT(v) ((uint8_t)((uint8_t)(v) << BP_USB_SOFTHLD_CNT) & BM_USB_SOFTHLD_CNT) 02655 02656 /*! @brief Set the CNT field to a new value. */ 02657 #define BW_USB_SOFTHLD_CNT(x, v) (HW_USB_SOFTHLD_WR(x, v)) 02658 /*@}*/ 02659 02660 /******************************************************************************* 02661 * HW_USB_BDTPAGE2 - BDT Page Register 2 02662 ******************************************************************************/ 02663 02664 /*! 02665 * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW) 02666 * 02667 * Reset value: 0x00U 02668 * 02669 * Contains an 8-bit value used to compute the address where the current Buffer 02670 * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. 02671 */ 02672 typedef union _hw_usb_bdtpage2 02673 { 02674 uint8_t U; 02675 struct _hw_usb_bdtpage2_bitfields 02676 { 02677 uint8_t BDTBA : 8; /*!< [7:0] */ 02678 } B; 02679 } hw_usb_bdtpage2_t; 02680 02681 /*! 02682 * @name Constants and macros for entire USB_BDTPAGE2 register 02683 */ 02684 /*@{*/ 02685 #define HW_USB_BDTPAGE2_ADDR(x) ((x) + 0xB0U) 02686 02687 #define HW_USB_BDTPAGE2(x) (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR(x)) 02688 #define HW_USB_BDTPAGE2_RD(x) (HW_USB_BDTPAGE2(x).U) 02689 #define HW_USB_BDTPAGE2_WR(x, v) (HW_USB_BDTPAGE2(x).U = (v)) 02690 #define HW_USB_BDTPAGE2_SET(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) | (v))) 02691 #define HW_USB_BDTPAGE2_CLR(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) & ~(v))) 02692 #define HW_USB_BDTPAGE2_TOG(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) ^ (v))) 02693 /*@}*/ 02694 02695 /* 02696 * Constants & macros for individual USB_BDTPAGE2 bitfields 02697 */ 02698 02699 /*! 02700 * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW) 02701 * 02702 * Provides address bits 23 through 16 of the BDT base address that defines the 02703 * location of Buffer Descriptor Table resides in system memory. 02704 */ 02705 /*@{*/ 02706 #define BP_USB_BDTPAGE2_BDTBA (0U) /*!< Bit position for USB_BDTPAGE2_BDTBA. */ 02707 #define BM_USB_BDTPAGE2_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE2_BDTBA. */ 02708 #define BS_USB_BDTPAGE2_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE2_BDTBA. */ 02709 02710 /*! @brief Read current value of the USB_BDTPAGE2_BDTBA field. */ 02711 #define BR_USB_BDTPAGE2_BDTBA(x) (HW_USB_BDTPAGE2(x).U) 02712 02713 /*! @brief Format value for bitfield USB_BDTPAGE2_BDTBA. */ 02714 #define BF_USB_BDTPAGE2_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE2_BDTBA) & BM_USB_BDTPAGE2_BDTBA) 02715 02716 /*! @brief Set the BDTBA field to a new value. */ 02717 #define BW_USB_BDTPAGE2_BDTBA(x, v) (HW_USB_BDTPAGE2_WR(x, v)) 02718 /*@}*/ 02719 02720 /******************************************************************************* 02721 * HW_USB_BDTPAGE3 - BDT Page Register 3 02722 ******************************************************************************/ 02723 02724 /*! 02725 * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW) 02726 * 02727 * Reset value: 0x00U 02728 * 02729 * Contains an 8-bit value used to compute the address where the current Buffer 02730 * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. 02731 */ 02732 typedef union _hw_usb_bdtpage3 02733 { 02734 uint8_t U; 02735 struct _hw_usb_bdtpage3_bitfields 02736 { 02737 uint8_t BDTBA : 8; /*!< [7:0] */ 02738 } B; 02739 } hw_usb_bdtpage3_t; 02740 02741 /*! 02742 * @name Constants and macros for entire USB_BDTPAGE3 register 02743 */ 02744 /*@{*/ 02745 #define HW_USB_BDTPAGE3_ADDR(x) ((x) + 0xB4U) 02746 02747 #define HW_USB_BDTPAGE3(x) (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR(x)) 02748 #define HW_USB_BDTPAGE3_RD(x) (HW_USB_BDTPAGE3(x).U) 02749 #define HW_USB_BDTPAGE3_WR(x, v) (HW_USB_BDTPAGE3(x).U = (v)) 02750 #define HW_USB_BDTPAGE3_SET(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) | (v))) 02751 #define HW_USB_BDTPAGE3_CLR(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) & ~(v))) 02752 #define HW_USB_BDTPAGE3_TOG(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) ^ (v))) 02753 /*@}*/ 02754 02755 /* 02756 * Constants & macros for individual USB_BDTPAGE3 bitfields 02757 */ 02758 02759 /*! 02760 * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW) 02761 * 02762 * Provides address bits 31 through 24 of the BDT base address that defines the 02763 * location of Buffer Descriptor Table resides in system memory. 02764 */ 02765 /*@{*/ 02766 #define BP_USB_BDTPAGE3_BDTBA (0U) /*!< Bit position for USB_BDTPAGE3_BDTBA. */ 02767 #define BM_USB_BDTPAGE3_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE3_BDTBA. */ 02768 #define BS_USB_BDTPAGE3_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE3_BDTBA. */ 02769 02770 /*! @brief Read current value of the USB_BDTPAGE3_BDTBA field. */ 02771 #define BR_USB_BDTPAGE3_BDTBA(x) (HW_USB_BDTPAGE3(x).U) 02772 02773 /*! @brief Format value for bitfield USB_BDTPAGE3_BDTBA. */ 02774 #define BF_USB_BDTPAGE3_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE3_BDTBA) & BM_USB_BDTPAGE3_BDTBA) 02775 02776 /*! @brief Set the BDTBA field to a new value. */ 02777 #define BW_USB_BDTPAGE3_BDTBA(x, v) (HW_USB_BDTPAGE3_WR(x, v)) 02778 /*@}*/ 02779 02780 /******************************************************************************* 02781 * HW_USB_ENDPTn - Endpoint Control register 02782 ******************************************************************************/ 02783 02784 /*! 02785 * @brief HW_USB_ENDPTn - Endpoint Control register (RW) 02786 * 02787 * Reset value: 0x00U 02788 * 02789 * Contains the endpoint control bits for each of the 16 endpoints available 02790 * within the USB module for a decoded address. The format for these registers is 02791 * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control 02792 * pipe 0, which is required for all USB functions. Therefore, after a USBRST 02793 * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode 02794 * ENDPT0 is used to determine the handshake, retry and low speed 02795 * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK 02796 * bit should be 1. For Isochronous transfers it should be 0. Common values to 02797 * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, 02798 * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and 02799 * EPTXEN define if an endpoint is enabled and define the direction of the endpoint. 02800 * The endpoint enable/direction control is defined in the following table. 02801 * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint 02802 * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only 02803 * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and 02804 * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP) 02805 * transfers. 02806 */ 02807 typedef union _hw_usb_endptn 02808 { 02809 uint8_t U; 02810 struct _hw_usb_endptn_bitfields 02811 { 02812 uint8_t EPHSHK : 1; /*!< [0] */ 02813 uint8_t EPSTALL : 1; /*!< [1] */ 02814 uint8_t EPTXEN : 1; /*!< [2] */ 02815 uint8_t EPRXEN : 1; /*!< [3] */ 02816 uint8_t EPCTLDIS : 1; /*!< [4] */ 02817 uint8_t RESERVED0 : 1; /*!< [5] */ 02818 uint8_t RETRYDIS : 1; /*!< [6] */ 02819 uint8_t HOSTWOHUB : 1; /*!< [7] */ 02820 } B; 02821 } hw_usb_endptn_t; 02822 02823 /*! 02824 * @name Constants and macros for entire USB_ENDPTn register 02825 */ 02826 /*@{*/ 02827 #define HW_USB_ENDPTn_COUNT (16U) 02828 02829 #define HW_USB_ENDPTn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n))) 02830 02831 #define HW_USB_ENDPTn(x, n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(x, n)) 02832 #define HW_USB_ENDPTn_RD(x, n) (HW_USB_ENDPTn(x, n).U) 02833 #define HW_USB_ENDPTn_WR(x, n, v) (HW_USB_ENDPTn(x, n).U = (v)) 02834 #define HW_USB_ENDPTn_SET(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) | (v))) 02835 #define HW_USB_ENDPTn_CLR(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) & ~(v))) 02836 #define HW_USB_ENDPTn_TOG(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) ^ (v))) 02837 /*@}*/ 02838 02839 /* 02840 * Constants & macros for individual USB_ENDPTn bitfields 02841 */ 02842 02843 /*! 02844 * @name Register USB_ENDPTn, field EPHSHK[0] (RW) 02845 * 02846 * When set this bit enables an endpoint to perform handshaking during a 02847 * transaction to this endpoint. This bit is generally 1 unless the endpoint is 02848 * Isochronous. 02849 */ 02850 /*@{*/ 02851 #define BP_USB_ENDPTn_EPHSHK (0U) /*!< Bit position for USB_ENDPTn_EPHSHK. */ 02852 #define BM_USB_ENDPTn_EPHSHK (0x01U) /*!< Bit mask for USB_ENDPTn_EPHSHK. */ 02853 #define BS_USB_ENDPTn_EPHSHK (1U) /*!< Bit field size in bits for USB_ENDPTn_EPHSHK. */ 02854 02855 /*! @brief Read current value of the USB_ENDPTn_EPHSHK field. */ 02856 #define BR_USB_ENDPTn_EPHSHK(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK)) 02857 02858 /*! @brief Format value for bitfield USB_ENDPTn_EPHSHK. */ 02859 #define BF_USB_ENDPTn_EPHSHK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPHSHK) & BM_USB_ENDPTn_EPHSHK) 02860 02861 /*! @brief Set the EPHSHK field to a new value. */ 02862 #define BW_USB_ENDPTn_EPHSHK(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK) = (v)) 02863 /*@}*/ 02864 02865 /*! 02866 * @name Register USB_ENDPTn, field EPSTALL[1] (RW) 02867 * 02868 * When set this bit indicates that the endpoint is called. This bit has 02869 * priority over all other control bits in the EndPoint Enable Register, but it is only 02870 * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB 02871 * Module to return a STALL handshake. After an endpoint is stalled it requires 02872 * intervention from the Host Controller. 02873 */ 02874 /*@{*/ 02875 #define BP_USB_ENDPTn_EPSTALL (1U) /*!< Bit position for USB_ENDPTn_EPSTALL. */ 02876 #define BM_USB_ENDPTn_EPSTALL (0x02U) /*!< Bit mask for USB_ENDPTn_EPSTALL. */ 02877 #define BS_USB_ENDPTn_EPSTALL (1U) /*!< Bit field size in bits for USB_ENDPTn_EPSTALL. */ 02878 02879 /*! @brief Read current value of the USB_ENDPTn_EPSTALL field. */ 02880 #define BR_USB_ENDPTn_EPSTALL(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL)) 02881 02882 /*! @brief Format value for bitfield USB_ENDPTn_EPSTALL. */ 02883 #define BF_USB_ENDPTn_EPSTALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPSTALL) & BM_USB_ENDPTn_EPSTALL) 02884 02885 /*! @brief Set the EPSTALL field to a new value. */ 02886 #define BW_USB_ENDPTn_EPSTALL(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL) = (v)) 02887 /*@}*/ 02888 02889 /*! 02890 * @name Register USB_ENDPTn, field EPTXEN[2] (RW) 02891 * 02892 * This bit, when set, enables the endpoint for TX transfers. 02893 */ 02894 /*@{*/ 02895 #define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */ 02896 #define BM_USB_ENDPTn_EPTXEN (0x04U) /*!< Bit mask for USB_ENDPTn_EPTXEN. */ 02897 #define BS_USB_ENDPTn_EPTXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPTXEN. */ 02898 02899 /*! @brief Read current value of the USB_ENDPTn_EPTXEN field. */ 02900 #define BR_USB_ENDPTn_EPTXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN)) 02901 02902 /*! @brief Format value for bitfield USB_ENDPTn_EPTXEN. */ 02903 #define BF_USB_ENDPTn_EPTXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPTXEN) & BM_USB_ENDPTn_EPTXEN) 02904 02905 /*! @brief Set the EPTXEN field to a new value. */ 02906 #define BW_USB_ENDPTn_EPTXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN) = (v)) 02907 /*@}*/ 02908 02909 /*! 02910 * @name Register USB_ENDPTn, field EPRXEN[3] (RW) 02911 * 02912 * This bit, when set, enables the endpoint for RX transfers. 02913 */ 02914 /*@{*/ 02915 #define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */ 02916 #define BM_USB_ENDPTn_EPRXEN (0x08U) /*!< Bit mask for USB_ENDPTn_EPRXEN. */ 02917 #define BS_USB_ENDPTn_EPRXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPRXEN. */ 02918 02919 /*! @brief Read current value of the USB_ENDPTn_EPRXEN field. */ 02920 #define BR_USB_ENDPTn_EPRXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN)) 02921 02922 /*! @brief Format value for bitfield USB_ENDPTn_EPRXEN. */ 02923 #define BF_USB_ENDPTn_EPRXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPRXEN) & BM_USB_ENDPTn_EPRXEN) 02924 02925 /*! @brief Set the EPRXEN field to a new value. */ 02926 #define BW_USB_ENDPTn_EPRXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN) = (v)) 02927 /*@}*/ 02928 02929 /*! 02930 * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW) 02931 * 02932 * This bit, when set, disables control (SETUP) transfers. When cleared, control 02933 * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits 02934 * are also set. 02935 */ 02936 /*@{*/ 02937 #define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */ 02938 #define BM_USB_ENDPTn_EPCTLDIS (0x10U) /*!< Bit mask for USB_ENDPTn_EPCTLDIS. */ 02939 #define BS_USB_ENDPTn_EPCTLDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_EPCTLDIS. */ 02940 02941 /*! @brief Read current value of the USB_ENDPTn_EPCTLDIS field. */ 02942 #define BR_USB_ENDPTn_EPCTLDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS)) 02943 02944 /*! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS. */ 02945 #define BF_USB_ENDPTn_EPCTLDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPCTLDIS) & BM_USB_ENDPTn_EPCTLDIS) 02946 02947 /*! @brief Set the EPCTLDIS field to a new value. */ 02948 #define BW_USB_ENDPTn_EPCTLDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS) = (v)) 02949 /*@}*/ 02950 02951 /*! 02952 * @name Register USB_ENDPTn, field RETRYDIS[6] (RW) 02953 * 02954 * This is a Host mode only bit and is present in the control register for 02955 * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed 02956 * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID 02957 * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When 02958 * this bit is cleared, NAKed transactions are retried in hardware. This bit must 02959 * be set when the host is attempting to poll an interrupt endpoint. 02960 */ 02961 /*@{*/ 02962 #define BP_USB_ENDPTn_RETRYDIS (6U) /*!< Bit position for USB_ENDPTn_RETRYDIS. */ 02963 #define BM_USB_ENDPTn_RETRYDIS (0x40U) /*!< Bit mask for USB_ENDPTn_RETRYDIS. */ 02964 #define BS_USB_ENDPTn_RETRYDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_RETRYDIS. */ 02965 02966 /*! @brief Read current value of the USB_ENDPTn_RETRYDIS field. */ 02967 #define BR_USB_ENDPTn_RETRYDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS)) 02968 02969 /*! @brief Format value for bitfield USB_ENDPTn_RETRYDIS. */ 02970 #define BF_USB_ENDPTn_RETRYDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_RETRYDIS) & BM_USB_ENDPTn_RETRYDIS) 02971 02972 /*! @brief Set the RETRYDIS field to a new value. */ 02973 #define BW_USB_ENDPTn_RETRYDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS) = (v)) 02974 /*@}*/ 02975 02976 /*! 02977 * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW) 02978 * 02979 * This is a Host mode only field and is present in the control register for 02980 * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a 02981 * directly connected low speed device. When cleared, the host produces the 02982 * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed 02983 * device as required to communicate with a low speed device through a hub. 02984 */ 02985 /*@{*/ 02986 #define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */ 02987 #define BM_USB_ENDPTn_HOSTWOHUB (0x80U) /*!< Bit mask for USB_ENDPTn_HOSTWOHUB. */ 02988 #define BS_USB_ENDPTn_HOSTWOHUB (1U) /*!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB. */ 02989 02990 /*! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field. */ 02991 #define BR_USB_ENDPTn_HOSTWOHUB(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB)) 02992 02993 /*! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB. */ 02994 #define BF_USB_ENDPTn_HOSTWOHUB(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_HOSTWOHUB) & BM_USB_ENDPTn_HOSTWOHUB) 02995 02996 /*! @brief Set the HOSTWOHUB field to a new value. */ 02997 #define BW_USB_ENDPTn_HOSTWOHUB(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB) = (v)) 02998 /*@}*/ 02999 03000 /******************************************************************************* 03001 * HW_USB_USBCTRL - USB Control register 03002 ******************************************************************************/ 03003 03004 /*! 03005 * @brief HW_USB_USBCTRL - USB Control register (RW) 03006 * 03007 * Reset value: 0xC0U 03008 */ 03009 typedef union _hw_usb_usbctrl 03010 { 03011 uint8_t U; 03012 struct _hw_usb_usbctrl_bitfields 03013 { 03014 uint8_t RESERVED0 : 6; /*!< [5:0] */ 03015 uint8_t PDE : 1; /*!< [6] */ 03016 uint8_t SUSP : 1; /*!< [7] */ 03017 } B; 03018 } hw_usb_usbctrl_t; 03019 03020 /*! 03021 * @name Constants and macros for entire USB_USBCTRL register 03022 */ 03023 /*@{*/ 03024 #define HW_USB_USBCTRL_ADDR(x) ((x) + 0x100U) 03025 03026 #define HW_USB_USBCTRL(x) (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR(x)) 03027 #define HW_USB_USBCTRL_RD(x) (HW_USB_USBCTRL(x).U) 03028 #define HW_USB_USBCTRL_WR(x, v) (HW_USB_USBCTRL(x).U = (v)) 03029 #define HW_USB_USBCTRL_SET(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) | (v))) 03030 #define HW_USB_USBCTRL_CLR(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) & ~(v))) 03031 #define HW_USB_USBCTRL_TOG(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) ^ (v))) 03032 /*@}*/ 03033 03034 /* 03035 * Constants & macros for individual USB_USBCTRL bitfields 03036 */ 03037 03038 /*! 03039 * @name Register USB_USBCTRL, field PDE[6] (RW) 03040 * 03041 * Enables the weak pulldowns on the USB transceiver. 03042 * 03043 * Values: 03044 * - 0 - Weak pulldowns are disabled on D+ and D-. 03045 * - 1 - Weak pulldowns are enabled on D+ and D-. 03046 */ 03047 /*@{*/ 03048 #define BP_USB_USBCTRL_PDE (6U) /*!< Bit position for USB_USBCTRL_PDE. */ 03049 #define BM_USB_USBCTRL_PDE (0x40U) /*!< Bit mask for USB_USBCTRL_PDE. */ 03050 #define BS_USB_USBCTRL_PDE (1U) /*!< Bit field size in bits for USB_USBCTRL_PDE. */ 03051 03052 /*! @brief Read current value of the USB_USBCTRL_PDE field. */ 03053 #define BR_USB_USBCTRL_PDE(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE)) 03054 03055 /*! @brief Format value for bitfield USB_USBCTRL_PDE. */ 03056 #define BF_USB_USBCTRL_PDE(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_PDE) & BM_USB_USBCTRL_PDE) 03057 03058 /*! @brief Set the PDE field to a new value. */ 03059 #define BW_USB_USBCTRL_PDE(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE) = (v)) 03060 /*@}*/ 03061 03062 /*! 03063 * @name Register USB_USBCTRL, field SUSP[7] (RW) 03064 * 03065 * Places the USB transceiver into the suspend state. 03066 * 03067 * Values: 03068 * - 0 - USB transceiver is not in suspend state. 03069 * - 1 - USB transceiver is in suspend state. 03070 */ 03071 /*@{*/ 03072 #define BP_USB_USBCTRL_SUSP (7U) /*!< Bit position for USB_USBCTRL_SUSP. */ 03073 #define BM_USB_USBCTRL_SUSP (0x80U) /*!< Bit mask for USB_USBCTRL_SUSP. */ 03074 #define BS_USB_USBCTRL_SUSP (1U) /*!< Bit field size in bits for USB_USBCTRL_SUSP. */ 03075 03076 /*! @brief Read current value of the USB_USBCTRL_SUSP field. */ 03077 #define BR_USB_USBCTRL_SUSP(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP)) 03078 03079 /*! @brief Format value for bitfield USB_USBCTRL_SUSP. */ 03080 #define BF_USB_USBCTRL_SUSP(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_SUSP) & BM_USB_USBCTRL_SUSP) 03081 03082 /*! @brief Set the SUSP field to a new value. */ 03083 #define BW_USB_USBCTRL_SUSP(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP) = (v)) 03084 /*@}*/ 03085 03086 /******************************************************************************* 03087 * HW_USB_OBSERVE - USB OTG Observe register 03088 ******************************************************************************/ 03089 03090 /*! 03091 * @brief HW_USB_OBSERVE - USB OTG Observe register (RO) 03092 * 03093 * Reset value: 0x50U 03094 * 03095 * Provides visibility on the state of the pull-ups and pull-downs at the 03096 * transceiver. Useful when interfacing to an external OTG control module via a serial 03097 * interface. 03098 */ 03099 typedef union _hw_usb_observe 03100 { 03101 uint8_t U; 03102 struct _hw_usb_observe_bitfields 03103 { 03104 uint8_t RESERVED0 : 4; /*!< [3:0] */ 03105 uint8_t DMPD : 1; /*!< [4] */ 03106 uint8_t RESERVED1 : 1; /*!< [5] */ 03107 uint8_t DPPD : 1; /*!< [6] */ 03108 uint8_t DPPU : 1; /*!< [7] */ 03109 } B; 03110 } hw_usb_observe_t; 03111 03112 /*! 03113 * @name Constants and macros for entire USB_OBSERVE register 03114 */ 03115 /*@{*/ 03116 #define HW_USB_OBSERVE_ADDR(x) ((x) + 0x104U) 03117 03118 #define HW_USB_OBSERVE(x) (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR(x)) 03119 #define HW_USB_OBSERVE_RD(x) (HW_USB_OBSERVE(x).U) 03120 /*@}*/ 03121 03122 /* 03123 * Constants & macros for individual USB_OBSERVE bitfields 03124 */ 03125 03126 /*! 03127 * @name Register USB_OBSERVE, field DMPD[4] (RO) 03128 * 03129 * Provides observability of the D- Pulldown enable at the USB transceiver. 03130 * 03131 * Values: 03132 * - 0 - D- pulldown disabled. 03133 * - 1 - D- pulldown enabled. 03134 */ 03135 /*@{*/ 03136 #define BP_USB_OBSERVE_DMPD (4U) /*!< Bit position for USB_OBSERVE_DMPD. */ 03137 #define BM_USB_OBSERVE_DMPD (0x10U) /*!< Bit mask for USB_OBSERVE_DMPD. */ 03138 #define BS_USB_OBSERVE_DMPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DMPD. */ 03139 03140 /*! @brief Read current value of the USB_OBSERVE_DMPD field. */ 03141 #define BR_USB_OBSERVE_DMPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DMPD)) 03142 /*@}*/ 03143 03144 /*! 03145 * @name Register USB_OBSERVE, field DPPD[6] (RO) 03146 * 03147 * Provides observability of the D+ Pulldown enable at the USB transceiver. 03148 * 03149 * Values: 03150 * - 0 - D+ pulldown disabled. 03151 * - 1 - D+ pulldown enabled. 03152 */ 03153 /*@{*/ 03154 #define BP_USB_OBSERVE_DPPD (6U) /*!< Bit position for USB_OBSERVE_DPPD. */ 03155 #define BM_USB_OBSERVE_DPPD (0x40U) /*!< Bit mask for USB_OBSERVE_DPPD. */ 03156 #define BS_USB_OBSERVE_DPPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPD. */ 03157 03158 /*! @brief Read current value of the USB_OBSERVE_DPPD field. */ 03159 #define BR_USB_OBSERVE_DPPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPD)) 03160 /*@}*/ 03161 03162 /*! 03163 * @name Register USB_OBSERVE, field DPPU[7] (RO) 03164 * 03165 * Provides observability of the D+ Pullup enable at the USB transceiver. 03166 * 03167 * Values: 03168 * - 0 - D+ pullup disabled. 03169 * - 1 - D+ pullup enabled. 03170 */ 03171 /*@{*/ 03172 #define BP_USB_OBSERVE_DPPU (7U) /*!< Bit position for USB_OBSERVE_DPPU. */ 03173 #define BM_USB_OBSERVE_DPPU (0x80U) /*!< Bit mask for USB_OBSERVE_DPPU. */ 03174 #define BS_USB_OBSERVE_DPPU (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPU. */ 03175 03176 /*! @brief Read current value of the USB_OBSERVE_DPPU field. */ 03177 #define BR_USB_OBSERVE_DPPU(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPU)) 03178 /*@}*/ 03179 03180 /******************************************************************************* 03181 * HW_USB_CONTROL - USB OTG Control register 03182 ******************************************************************************/ 03183 03184 /*! 03185 * @brief HW_USB_CONTROL - USB OTG Control register (RW) 03186 * 03187 * Reset value: 0x00U 03188 */ 03189 typedef union _hw_usb_control 03190 { 03191 uint8_t U; 03192 struct _hw_usb_control_bitfields 03193 { 03194 uint8_t RESERVED0 : 4; /*!< [3:0] */ 03195 uint8_t DPPULLUPNONOTG : 1; /*!< [4] */ 03196 uint8_t RESERVED1 : 3; /*!< [7:5] */ 03197 } B; 03198 } hw_usb_control_t; 03199 03200 /*! 03201 * @name Constants and macros for entire USB_CONTROL register 03202 */ 03203 /*@{*/ 03204 #define HW_USB_CONTROL_ADDR(x) ((x) + 0x108U) 03205 03206 #define HW_USB_CONTROL(x) (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR(x)) 03207 #define HW_USB_CONTROL_RD(x) (HW_USB_CONTROL(x).U) 03208 #define HW_USB_CONTROL_WR(x, v) (HW_USB_CONTROL(x).U = (v)) 03209 #define HW_USB_CONTROL_SET(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) | (v))) 03210 #define HW_USB_CONTROL_CLR(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) & ~(v))) 03211 #define HW_USB_CONTROL_TOG(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) ^ (v))) 03212 /*@}*/ 03213 03214 /* 03215 * Constants & macros for individual USB_CONTROL bitfields 03216 */ 03217 03218 /*! 03219 * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW) 03220 * 03221 * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG 03222 * device mode. 03223 * 03224 * Values: 03225 * - 0 - DP Pullup in non-OTG device mode is not enabled. 03226 * - 1 - DP Pullup in non-OTG device mode is enabled. 03227 */ 03228 /*@{*/ 03229 #define BP_USB_CONTROL_DPPULLUPNONOTG (4U) /*!< Bit position for USB_CONTROL_DPPULLUPNONOTG. */ 03230 #define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) /*!< Bit mask for USB_CONTROL_DPPULLUPNONOTG. */ 03231 #define BS_USB_CONTROL_DPPULLUPNONOTG (1U) /*!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG. */ 03232 03233 /*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */ 03234 #define BR_USB_CONTROL_DPPULLUPNONOTG(x) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG)) 03235 03236 /*! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG. */ 03237 #define BF_USB_CONTROL_DPPULLUPNONOTG(v) ((uint8_t)((uint8_t)(v) << BP_USB_CONTROL_DPPULLUPNONOTG) & BM_USB_CONTROL_DPPULLUPNONOTG) 03238 03239 /*! @brief Set the DPPULLUPNONOTG field to a new value. */ 03240 #define BW_USB_CONTROL_DPPULLUPNONOTG(x, v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG) = (v)) 03241 /*@}*/ 03242 03243 /******************************************************************************* 03244 * HW_USB_USBTRC0 - USB Transceiver Control register 0 03245 ******************************************************************************/ 03246 03247 /*! 03248 * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW) 03249 * 03250 * Reset value: 0x00U 03251 * 03252 * Includes signals for basic operation of the on-chip USB Full Speed 03253 * transceiver and configuration of the USB data connection that are not otherwise included 03254 * in the USB Full Speed controller registers. 03255 */ 03256 typedef union _hw_usb_usbtrc0 03257 { 03258 uint8_t U; 03259 struct _hw_usb_usbtrc0_bitfields 03260 { 03261 uint8_t USB_RESUME_INT : 1; /*!< [0] USB Asynchronous Interrupt */ 03262 uint8_t SYNC_DET : 1; /*!< [1] Synchronous USB Interrupt Detect */ 03263 uint8_t USB_CLK_RECOVERY_INT : 1; /*!< [2] Combined USB Clock 03264 * Recovery interrupt status */ 03265 uint8_t RESERVED0 : 2; /*!< [4:3] */ 03266 uint8_t USBRESMEN : 1; /*!< [5] Asynchronous Resume Interrupt Enable 03267 * */ 03268 uint8_t RESERVED1 : 1; /*!< [6] */ 03269 uint8_t USBRESET : 1; /*!< [7] USB Reset */ 03270 } B; 03271 } hw_usb_usbtrc0_t; 03272 03273 /*! 03274 * @name Constants and macros for entire USB_USBTRC0 register 03275 */ 03276 /*@{*/ 03277 #define HW_USB_USBTRC0_ADDR(x) ((x) + 0x10CU) 03278 03279 #define HW_USB_USBTRC0(x) (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR(x)) 03280 #define HW_USB_USBTRC0_RD(x) (HW_USB_USBTRC0(x).U) 03281 #define HW_USB_USBTRC0_WR(x, v) (HW_USB_USBTRC0(x).U = (v)) 03282 #define HW_USB_USBTRC0_SET(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) | (v))) 03283 #define HW_USB_USBTRC0_CLR(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) & ~(v))) 03284 #define HW_USB_USBTRC0_TOG(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) ^ (v))) 03285 /*@}*/ 03286 03287 /* 03288 * Constants & macros for individual USB_USBTRC0 bitfields 03289 */ 03290 03291 /*! 03292 * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO) 03293 * 03294 * Values: 03295 * - 0 - No interrupt was generated. 03296 * - 1 - Interrupt was generated because of the USB asynchronous interrupt. 03297 */ 03298 /*@{*/ 03299 #define BP_USB_USBTRC0_USB_RESUME_INT (0U) /*!< Bit position for USB_USBTRC0_USB_RESUME_INT. */ 03300 #define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) /*!< Bit mask for USB_USBTRC0_USB_RESUME_INT. */ 03301 #define BS_USB_USBTRC0_USB_RESUME_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT. */ 03302 03303 /*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */ 03304 #define BR_USB_USBTRC0_USB_RESUME_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_RESUME_INT)) 03305 /*@}*/ 03306 03307 /*! 03308 * @name Register USB_USBTRC0, field SYNC_DET[1] (RO) 03309 * 03310 * Values: 03311 * - 0 - Synchronous interrupt has not been detected. 03312 * - 1 - Synchronous interrupt has been detected. 03313 */ 03314 /*@{*/ 03315 #define BP_USB_USBTRC0_SYNC_DET (1U) /*!< Bit position for USB_USBTRC0_SYNC_DET. */ 03316 #define BM_USB_USBTRC0_SYNC_DET (0x02U) /*!< Bit mask for USB_USBTRC0_SYNC_DET. */ 03317 #define BS_USB_USBTRC0_SYNC_DET (1U) /*!< Bit field size in bits for USB_USBTRC0_SYNC_DET. */ 03318 03319 /*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */ 03320 #define BR_USB_USBTRC0_SYNC_DET(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_SYNC_DET)) 03321 /*@}*/ 03322 03323 /*! 03324 * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO) 03325 * 03326 * This read-only field will be set to value high at 1'b1 when any of USB clock 03327 * recovery interrupt conditions are detected and those interrupts are unmasked. 03328 * For customer use the only unmasked USB clock recovery interrupt condition 03329 * results from an overflow of the frequency trim setting values indicating that the 03330 * frequency trim calculated is out of the adjustment range of the IRC48M output 03331 * clock. To clear this bit after it has been set, Write 0xFF to register 03332 * USB_CLK_RECOVER_INT_STATUS. 03333 */ 03334 /*@{*/ 03335 #define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) /*!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ 03336 #define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) /*!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ 03337 #define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ 03338 03339 /*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */ 03340 #define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_CLK_RECOVERY_INT)) 03341 /*@}*/ 03342 03343 /*! 03344 * @name Register USB_USBTRC0, field USBRESMEN[5] (RW) 03345 * 03346 * This bit, when set, allows the USB module to send an asynchronous wakeup 03347 * event to the MCU upon detection of resume signaling on the USB bus. The MCU then 03348 * re-enables clocks to the USB module. It is used for low-power suspend mode when 03349 * USB module clocks are stopped or the USB transceiver is in Suspend mode. 03350 * Async wakeup only works in device mode. 03351 * 03352 * Values: 03353 * - 0 - USB asynchronous wakeup from suspend mode disabled. 03354 * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous 03355 * resume interrupt differs from the synchronous resume interrupt in that it 03356 * asynchronously detects K-state using the unfiltered state of the D+ and D- 03357 * pins. This interrupt should only be enabled when the Transceiver is 03358 * suspended. 03359 */ 03360 /*@{*/ 03361 #define BP_USB_USBTRC0_USBRESMEN (5U) /*!< Bit position for USB_USBTRC0_USBRESMEN. */ 03362 #define BM_USB_USBTRC0_USBRESMEN (0x20U) /*!< Bit mask for USB_USBTRC0_USBRESMEN. */ 03363 #define BS_USB_USBTRC0_USBRESMEN (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESMEN. */ 03364 03365 /*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */ 03366 #define BR_USB_USBTRC0_USBRESMEN(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN)) 03367 03368 /*! @brief Format value for bitfield USB_USBTRC0_USBRESMEN. */ 03369 #define BF_USB_USBTRC0_USBRESMEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESMEN) & BM_USB_USBTRC0_USBRESMEN) 03370 03371 /*! @brief Set the USBRESMEN field to a new value. */ 03372 #define BW_USB_USBTRC0_USBRESMEN(x, v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN) = (v)) 03373 /*@}*/ 03374 03375 /*! 03376 * @name Register USB_USBTRC0, field USBRESET[7] (WO) 03377 * 03378 * Generates a hard reset to USBOTG. After this bit is set and the reset occurs, 03379 * this bit is automatically cleared. This bit is always read as zero. Wait two 03380 * USB clock cycles after setting this bit. 03381 * 03382 * Values: 03383 * - 0 - Normal USB module operation. 03384 * - 1 - Returns the USB module to its reset state. 03385 */ 03386 /*@{*/ 03387 #define BP_USB_USBTRC0_USBRESET (7U) /*!< Bit position for USB_USBTRC0_USBRESET. */ 03388 #define BM_USB_USBTRC0_USBRESET (0x80U) /*!< Bit mask for USB_USBTRC0_USBRESET. */ 03389 #define BS_USB_USBTRC0_USBRESET (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESET. */ 03390 03391 /*! @brief Format value for bitfield USB_USBTRC0_USBRESET. */ 03392 #define BF_USB_USBTRC0_USBRESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESET) & BM_USB_USBTRC0_USBRESET) 03393 /*@}*/ 03394 03395 /******************************************************************************* 03396 * HW_USB_USBFRMADJUST - Frame Adjust Register 03397 ******************************************************************************/ 03398 03399 /*! 03400 * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW) 03401 * 03402 * Reset value: 0x00U 03403 */ 03404 typedef union _hw_usb_usbfrmadjust 03405 { 03406 uint8_t U; 03407 struct _hw_usb_usbfrmadjust_bitfields 03408 { 03409 uint8_t ADJ : 8; /*!< [7:0] Frame Adjustment */ 03410 } B; 03411 } hw_usb_usbfrmadjust_t; 03412 03413 /*! 03414 * @name Constants and macros for entire USB_USBFRMADJUST register 03415 */ 03416 /*@{*/ 03417 #define HW_USB_USBFRMADJUST_ADDR(x) ((x) + 0x114U) 03418 03419 #define HW_USB_USBFRMADJUST(x) (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR(x)) 03420 #define HW_USB_USBFRMADJUST_RD(x) (HW_USB_USBFRMADJUST(x).U) 03421 #define HW_USB_USBFRMADJUST_WR(x, v) (HW_USB_USBFRMADJUST(x).U = (v)) 03422 #define HW_USB_USBFRMADJUST_SET(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) | (v))) 03423 #define HW_USB_USBFRMADJUST_CLR(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) & ~(v))) 03424 #define HW_USB_USBFRMADJUST_TOG(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) ^ (v))) 03425 /*@}*/ 03426 03427 /* 03428 * Constants & macros for individual USB_USBFRMADJUST bitfields 03429 */ 03430 03431 /*! 03432 * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW) 03433 * 03434 * In Host mode, the frame adjustment is a twos complement number that adjusts 03435 * the period of each USB frame in 12-MHz clock periods. A SOF is normally 03436 * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this 03437 * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock. 03438 * Changes to the ADJ bit take effect at the next start of the next frame. 03439 */ 03440 /*@{*/ 03441 #define BP_USB_USBFRMADJUST_ADJ (0U) /*!< Bit position for USB_USBFRMADJUST_ADJ. */ 03442 #define BM_USB_USBFRMADJUST_ADJ (0xFFU) /*!< Bit mask for USB_USBFRMADJUST_ADJ. */ 03443 #define BS_USB_USBFRMADJUST_ADJ (8U) /*!< Bit field size in bits for USB_USBFRMADJUST_ADJ. */ 03444 03445 /*! @brief Read current value of the USB_USBFRMADJUST_ADJ field. */ 03446 #define BR_USB_USBFRMADJUST_ADJ(x) (HW_USB_USBFRMADJUST(x).U) 03447 03448 /*! @brief Format value for bitfield USB_USBFRMADJUST_ADJ. */ 03449 #define BF_USB_USBFRMADJUST_ADJ(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBFRMADJUST_ADJ) & BM_USB_USBFRMADJUST_ADJ) 03450 03451 /*! @brief Set the ADJ field to a new value. */ 03452 #define BW_USB_USBFRMADJUST_ADJ(x, v) (HW_USB_USBFRMADJUST_WR(x, v)) 03453 /*@}*/ 03454 03455 /******************************************************************************* 03456 * HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control 03457 ******************************************************************************/ 03458 03459 /*! 03460 * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW) 03461 * 03462 * Reset value: 0x00U 03463 * 03464 * Signals in this register control the crystal-less USB clock mode in which the 03465 * internal IRC48M oscillator is tuned to match the clock extracted from the 03466 * incoming USB data stream. The IRC48M internal oscillator module must be enabled 03467 * in register USB_CLK_RECOVER_IRC_EN for this mode. 03468 */ 03469 typedef union _hw_usb_clk_recover_ctrl 03470 { 03471 uint8_t U; 03472 struct _hw_usb_clk_recover_ctrl_bitfields 03473 { 03474 uint8_t RESERVED0 : 5; /*!< [4:0] */ 03475 uint8_t RESTART_IFRTRIM_EN : 1; /*!< [5] Restart from IFR trim value 03476 * */ 03477 uint8_t RESET_RESUME_ROUGH_EN : 1; /*!< [6] Reset/resume to rough 03478 * phase enable */ 03479 uint8_t CLOCK_RECOVER_EN : 1; /*!< [7] Crystal-less USB enable */ 03480 } B; 03481 } hw_usb_clk_recover_ctrl_t; 03482 03483 /*! 03484 * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register 03485 */ 03486 /*@{*/ 03487 #define HW_USB_CLK_RECOVER_CTRL_ADDR(x) ((x) + 0x140U) 03488 03489 #define HW_USB_CLK_RECOVER_CTRL(x) (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR(x)) 03490 #define HW_USB_CLK_RECOVER_CTRL_RD(x) (HW_USB_CLK_RECOVER_CTRL(x).U) 03491 #define HW_USB_CLK_RECOVER_CTRL_WR(x, v) (HW_USB_CLK_RECOVER_CTRL(x).U = (v)) 03492 #define HW_USB_CLK_RECOVER_CTRL_SET(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) | (v))) 03493 #define HW_USB_CLK_RECOVER_CTRL_CLR(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) & ~(v))) 03494 #define HW_USB_CLK_RECOVER_CTRL_TOG(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) ^ (v))) 03495 /*@}*/ 03496 03497 /* 03498 * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields 03499 */ 03500 03501 /*! 03502 * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW) 03503 * 03504 * IRC48 has a default trim fine value whose default value is factory trimmed 03505 * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz 03506 * and keeps updating the trim fine value accordingly 03507 * 03508 * Values: 03509 * - 0 - Trim fine adjustment always works based on the previous updated trim 03510 * fine value (default) 03511 * - 1 - Trim fine restarts from the IFR trim value whenever 03512 * bus_reset/bus_resume is detected or module enable is desasserted 03513 */ 03514 /*@{*/ 03515 #define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ 03516 #define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ 03517 #define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ 03518 03519 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */ 03520 #define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)) 03521 03522 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ 03523 #define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) 03524 03525 /*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */ 03526 #define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v)) 03527 /*@}*/ 03528 03529 /*! 03530 * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW) 03531 * 03532 * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock. 03533 * It has two phases after user enables clock_recover_en bit, rough phase and 03534 * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine 03535 * value is different during these two phases. The step in rough phase is larger 03536 * than that in tracking phase. Switch back to rough stage whenever USB bus reset 03537 * or bus resume occurs. 03538 * 03539 * Values: 03540 * - 0 - Always works in tracking phase after the 1st time rough to track 03541 * transition (default) 03542 * - 1 - Go back to rough stage whenever bus reset or bus resume occurs 03543 */ 03544 /*@{*/ 03545 #define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ 03546 #define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ 03547 #define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ 03548 03549 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */ 03550 #define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)) 03551 03552 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ 03553 #define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) 03554 03555 /*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */ 03556 #define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v)) 03557 /*@}*/ 03558 03559 /*! 03560 * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW) 03561 * 03562 * This bit must be enabled if user wants to use the crystal-less USB mode for 03563 * the Full Speed USB controller and transceiver. This bit should not be set for 03564 * USB host mode or OTG. 03565 * 03566 * Values: 03567 * - 0 - Disable clock recovery block (default) 03568 * - 1 - Enable clock recovery block 03569 */ 03570 /*@{*/ 03571 #define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) /*!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ 03572 #define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ 03573 #define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ 03574 03575 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */ 03576 #define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)) 03577 03578 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ 03579 #define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) 03580 03581 /*! @brief Set the CLOCK_RECOVER_EN field to a new value. */ 03582 #define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v)) 03583 /*@}*/ 03584 03585 /******************************************************************************* 03586 * HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register 03587 ******************************************************************************/ 03588 03589 /*! 03590 * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW) 03591 * 03592 * Reset value: 0x01U 03593 * 03594 * Controls basic operation of the on-chip IRC48M module used to produce nominal 03595 * 48MHz clocks for USB crystal-less operation and other functions. See 03596 * additional information about the IRC48M operation in the Clock Distribution chapter. 03597 */ 03598 typedef union _hw_usb_clk_recover_irc_en 03599 { 03600 uint8_t U; 03601 struct _hw_usb_clk_recover_irc_en_bitfields 03602 { 03603 uint8_t REG_EN : 1; /*!< [0] IRC48M regulator enable */ 03604 uint8_t IRC_EN : 1; /*!< [1] IRC48M enable */ 03605 uint8_t RESERVED0 : 6; /*!< [7:2] */ 03606 } B; 03607 } hw_usb_clk_recover_irc_en_t; 03608 03609 /*! 03610 * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register 03611 */ 03612 /*@{*/ 03613 #define HW_USB_CLK_RECOVER_IRC_EN_ADDR(x) ((x) + 0x144U) 03614 03615 #define HW_USB_CLK_RECOVER_IRC_EN(x) (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR(x)) 03616 #define HW_USB_CLK_RECOVER_IRC_EN_RD(x) (HW_USB_CLK_RECOVER_IRC_EN(x).U) 03617 #define HW_USB_CLK_RECOVER_IRC_EN_WR(x, v) (HW_USB_CLK_RECOVER_IRC_EN(x).U = (v)) 03618 #define HW_USB_CLK_RECOVER_IRC_EN_SET(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) | (v))) 03619 #define HW_USB_CLK_RECOVER_IRC_EN_CLR(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) & ~(v))) 03620 #define HW_USB_CLK_RECOVER_IRC_EN_TOG(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) ^ (v))) 03621 /*@}*/ 03622 03623 /* 03624 * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields 03625 */ 03626 03627 /*! 03628 * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW) 03629 * 03630 * This bit is used to enable the local analog regulator for IRC48Mhz module. 03631 * This bit must be set if user wants to use the crystal-less USB clock 03632 * configuration. 03633 * 03634 * Values: 03635 * - 0 - IRC48M local regulator is disabled 03636 * - 1 - IRC48M local regulator is enabled (default) 03637 */ 03638 /*@{*/ 03639 #define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN. */ 03640 #define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN. */ 03641 #define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN. */ 03642 03643 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */ 03644 #define BR_USB_CLK_RECOVER_IRC_EN_REG_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN)) 03645 03646 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN. */ 03647 #define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN) 03648 03649 /*! @brief Set the REG_EN field to a new value. */ 03650 #define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v)) 03651 /*@}*/ 03652 03653 /*! 03654 * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW) 03655 * 03656 * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for 03657 * crystal-less USB. It can only be used for FS USB device mode operation. This 03658 * bit must be set before using the crystal-less USB clock configuration. 03659 * 03660 * Values: 03661 * - 0 - Disable the IRC48M module (default) 03662 * - 1 - Enable the IRC48M module 03663 */ 03664 /*@{*/ 03665 #define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ 03666 #define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ 03667 #define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ 03668 03669 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */ 03670 #define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN)) 03671 03672 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN. */ 03673 #define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN) 03674 03675 /*! @brief Set the IRC_EN field to a new value. */ 03676 #define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v)) 03677 /*@}*/ 03678 03679 /******************************************************************************* 03680 * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status 03681 ******************************************************************************/ 03682 03683 /*! 03684 * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C) 03685 * 03686 * Reset value: 0x00U 03687 * 03688 * A Write operation with value high at 1'b1 on any combination of individual 03689 * bits will clear those bits. 03690 */ 03691 typedef union _hw_usb_clk_recover_int_status 03692 { 03693 uint8_t U; 03694 struct _hw_usb_clk_recover_int_status_bitfields 03695 { 03696 uint8_t RESERVED0 : 4; /*!< [3:0] */ 03697 uint8_t OVF_ERROR : 1; /*!< [4] */ 03698 uint8_t RESERVED1 : 3; /*!< [7:5] */ 03699 } B; 03700 } hw_usb_clk_recover_int_status_t; 03701 03702 /*! 03703 * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register 03704 */ 03705 /*@{*/ 03706 #define HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x) ((x) + 0x15CU) 03707 03708 #define HW_USB_CLK_RECOVER_INT_STATUS(x) (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x)) 03709 #define HW_USB_CLK_RECOVER_INT_STATUS_RD(x) (HW_USB_CLK_RECOVER_INT_STATUS(x).U) 03710 #define HW_USB_CLK_RECOVER_INT_STATUS_WR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS(x).U = (v)) 03711 #define HW_USB_CLK_RECOVER_INT_STATUS_SET(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) | (v))) 03712 #define HW_USB_CLK_RECOVER_INT_STATUS_CLR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) & ~(v))) 03713 #define HW_USB_CLK_RECOVER_INT_STATUS_TOG(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) ^ (v))) 03714 /*@}*/ 03715 03716 /* 03717 * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields 03718 */ 03719 03720 /*! 03721 * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C) 03722 * 03723 * Indicates that the USB clock recovery algorithm has detected that the 03724 * frequency trim adjustment needed for the IRC48M output clock is outside the available 03725 * TRIM_FINE adjustment range for the IRC48M module. 03726 * 03727 * Values: 03728 * - 0 - No interrupt is reported 03729 * - 1 - Unmasked interrupt has been generated 03730 */ 03731 /*@{*/ 03732 #define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) /*!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ 03733 #define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ 03734 #define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ 03735 03736 /*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */ 03737 #define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)) 03738 03739 /*! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ 03740 #define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) 03741 03742 /*! @brief Set the OVF_ERROR field to a new value. */ 03743 #define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v)) 03744 /*@}*/ 03745 03746 /******************************************************************************* 03747 * hw_usb_t - module struct 03748 ******************************************************************************/ 03749 /*! 03750 * @brief All USB module registers. 03751 */ 03752 #pragma pack(1) 03753 typedef struct _hw_usb 03754 { 03755 __I hw_usb_perid_t PERID ; /*!< [0x0] Peripheral ID register */ 03756 uint8_t _reserved0[3]; 03757 __I hw_usb_idcomp_t IDCOMP ; /*!< [0x4] Peripheral ID Complement register */ 03758 uint8_t _reserved1[3]; 03759 __I hw_usb_rev_t REV ; /*!< [0x8] Peripheral Revision register */ 03760 uint8_t _reserved2[3]; 03761 __I hw_usb_addinfo_t ADDINFO ; /*!< [0xC] Peripheral Additional Info register */ 03762 uint8_t _reserved3[3]; 03763 __IO hw_usb_otgistat_t OTGISTAT ; /*!< [0x10] OTG Interrupt Status register */ 03764 uint8_t _reserved4[3]; 03765 __IO hw_usb_otgicr_t OTGICR ; /*!< [0x14] OTG Interrupt Control register */ 03766 uint8_t _reserved5[3]; 03767 __IO hw_usb_otgstat_t OTGSTAT ; /*!< [0x18] OTG Status register */ 03768 uint8_t _reserved6[3]; 03769 __IO hw_usb_otgctl_t OTGCTL ; /*!< [0x1C] OTG Control register */ 03770 uint8_t _reserved7[99]; 03771 __IO hw_usb_istat_t ISTAT ; /*!< [0x80] Interrupt Status register */ 03772 uint8_t _reserved8[3]; 03773 __IO hw_usb_inten_t INTEN ; /*!< [0x84] Interrupt Enable register */ 03774 uint8_t _reserved9[3]; 03775 __IO hw_usb_errstat_t ERRSTAT ; /*!< [0x88] Error Interrupt Status register */ 03776 uint8_t _reserved10[3]; 03777 __IO hw_usb_erren_t ERREN ; /*!< [0x8C] Error Interrupt Enable register */ 03778 uint8_t _reserved11[3]; 03779 __I hw_usb_stat_t STAT ; /*!< [0x90] Status register */ 03780 uint8_t _reserved12[3]; 03781 __IO hw_usb_ctl_t CTL ; /*!< [0x94] Control register */ 03782 uint8_t _reserved13[3]; 03783 __IO hw_usb_addr_t ADDR ; /*!< [0x98] Address register */ 03784 uint8_t _reserved14[3]; 03785 __IO hw_usb_bdtpage1_t BDTPAGE1 ; /*!< [0x9C] BDT Page register 1 */ 03786 uint8_t _reserved15[3]; 03787 __IO hw_usb_frmnuml_t FRMNUML ; /*!< [0xA0] Frame Number register Low */ 03788 uint8_t _reserved16[3]; 03789 __IO hw_usb_frmnumh_t FRMNUMH ; /*!< [0xA4] Frame Number register High */ 03790 uint8_t _reserved17[3]; 03791 __IO hw_usb_token_t TOKEN ; /*!< [0xA8] Token register */ 03792 uint8_t _reserved18[3]; 03793 __IO hw_usb_softhld_t SOFTHLD ; /*!< [0xAC] SOF Threshold register */ 03794 uint8_t _reserved19[3]; 03795 __IO hw_usb_bdtpage2_t BDTPAGE2 ; /*!< [0xB0] BDT Page Register 2 */ 03796 uint8_t _reserved20[3]; 03797 __IO hw_usb_bdtpage3_t BDTPAGE3 ; /*!< [0xB4] BDT Page Register 3 */ 03798 uint8_t _reserved21[11]; 03799 struct { 03800 __IO hw_usb_endptn_t ENDPTn ; /*!< [0xC0] Endpoint Control register */ 03801 uint8_t _reserved0[3]; 03802 } ENDPOINT[16]; 03803 __IO hw_usb_usbctrl_t USBCTRL ; /*!< [0x100] USB Control register */ 03804 uint8_t _reserved22[3]; 03805 __I hw_usb_observe_t OBSERVE ; /*!< [0x104] USB OTG Observe register */ 03806 uint8_t _reserved23[3]; 03807 __IO hw_usb_control_t CONTROL ; /*!< [0x108] USB OTG Control register */ 03808 uint8_t _reserved24[3]; 03809 __IO hw_usb_usbtrc0_t USBTRC0 ; /*!< [0x10C] USB Transceiver Control register 0 */ 03810 uint8_t _reserved25[7]; 03811 __IO hw_usb_usbfrmadjust_t USBFRMADJUST ; /*!< [0x114] Frame Adjust Register */ 03812 uint8_t _reserved26[43]; 03813 __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL ; /*!< [0x140] USB Clock recovery control */ 03814 uint8_t _reserved27[3]; 03815 __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN ; /*!< [0x144] IRC48M oscillator enable register */ 03816 uint8_t _reserved28[23]; 03817 __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS ; /*!< [0x15C] Clock recovery separated interrupt status */ 03818 } hw_usb_t; 03819 #pragma pack() 03820 03821 /*! @brief Macro to access all USB registers. */ 03822 /*! @param x USB module instance base address. */ 03823 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 03824 * use the '&' operator, like <code>&HW_USB(USB0_BASE)</code>. */ 03825 #define HW_USB(x) (*(hw_usb_t *)(x)) 03826 03827 #endif /* __HW_USB_REGISTERS_H__ */ 03828 /* EOF */
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