MK64F12_uart.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_UART_REGISTERS_H__
00081 #define __HW_UART_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 UART
00088  *
00089  * Serial Communication Interface
00090  *
00091  * Registers defined in this header file:
00092  * - HW_UART_BDH - UART Baud Rate Registers: High
00093  * - HW_UART_BDL - UART Baud Rate Registers: Low
00094  * - HW_UART_C1 - UART Control Register 1
00095  * - HW_UART_C2 - UART Control Register 2
00096  * - HW_UART_S1 - UART Status Register 1
00097  * - HW_UART_S2 - UART Status Register 2
00098  * - HW_UART_C3 - UART Control Register 3
00099  * - HW_UART_D - UART Data Register
00100  * - HW_UART_MA1 - UART Match Address Registers 1
00101  * - HW_UART_MA2 - UART Match Address Registers 2
00102  * - HW_UART_C4 - UART Control Register 4
00103  * - HW_UART_C5 - UART Control Register 5
00104  * - HW_UART_ED - UART Extended Data Register
00105  * - HW_UART_MODEM - UART Modem Register
00106  * - HW_UART_IR - UART Infrared Register
00107  * - HW_UART_PFIFO - UART FIFO Parameters
00108  * - HW_UART_CFIFO - UART FIFO Control Register
00109  * - HW_UART_SFIFO - UART FIFO Status Register
00110  * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
00111  * - HW_UART_TCFIFO - UART FIFO Transmit Count
00112  * - HW_UART_RWFIFO - UART FIFO Receive Watermark
00113  * - HW_UART_RCFIFO - UART FIFO Receive Count
00114  * - HW_UART_C7816 - UART 7816 Control Register
00115  * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
00116  * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
00117  * - HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
00118  * - HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
00119  * - HW_UART_WN7816 - UART 7816 Wait N Register
00120  * - HW_UART_WF7816 - UART 7816 Wait FD Register
00121  * - HW_UART_ET7816 - UART 7816 Error Threshold Register
00122  * - HW_UART_TL7816 - UART 7816 Transmit Length Register
00123  *
00124  * - hw_uart_t - Struct containing all module registers.
00125  */
00126 
00127 #define HW_UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
00128 #define HW_UART0 (0U) /*!< Instance number for UART0. */
00129 #define HW_UART1 (1U) /*!< Instance number for UART1. */
00130 #define HW_UART2 (2U) /*!< Instance number for UART2. */
00131 #define HW_UART3 (3U) /*!< Instance number for UART3. */
00132 #define HW_UART4 (4U) /*!< Instance number for UART4. */
00133 #define HW_UART5 (5U) /*!< Instance number for UART5. */
00134 
00135 /*******************************************************************************
00136  * HW_UART_BDH - UART Baud Rate Registers: High
00137  ******************************************************************************/
00138 
00139 /*!
00140  * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
00141  *
00142  * Reset value: 0x00U
00143  *
00144  * This register, along with the BDL register, controls the prescale divisor for
00145  * UART baud rate generation. To update the 13-bit baud rate setting
00146  * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
00147  * to BDL. The working value in BDH does not change until BDL is written. BDL is
00148  * reset to a nonzero value, but after reset, the baud rate generator remains
00149  * disabled until the first time the receiver or transmitter is enabled, that is,
00150  * when C2[RE] or C2[TE] is set.
00151  */
00152 typedef union _hw_uart_bdh
00153 {
00154     uint8_t U;
00155     struct _hw_uart_bdh_bitfields
00156     {
00157         uint8_t SBR : 5;               /*!< [4:0] UART Baud Rate Bits */
00158         uint8_t SBNS : 1;              /*!< [5] Stop Bit Number Select */
00159         uint8_t RXEDGIE : 1;           /*!< [6] RxD Input Active Edge Interrupt Enable
00160                                         * */
00161         uint8_t LBKDIE : 1;            /*!< [7] LIN Break Detect Interrupt or DMA
00162                                         * Request Enable */
00163     } B;
00164 } hw_uart_bdh_t;
00165 
00166 /*!
00167  * @name Constants and macros for entire UART_BDH register
00168  */
00169 /*@{*/
00170 #define HW_UART_BDH_ADDR(x)      ((x) + 0x0U)
00171 
00172 #define HW_UART_BDH(x)           (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
00173 #define HW_UART_BDH_RD(x)        (HW_UART_BDH(x).U)
00174 #define HW_UART_BDH_WR(x, v)     (HW_UART_BDH(x).U = (v))
00175 #define HW_UART_BDH_SET(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) |  (v)))
00176 #define HW_UART_BDH_CLR(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
00177 #define HW_UART_BDH_TOG(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^  (v)))
00178 /*@}*/
00179 
00180 /*
00181  * Constants & macros for individual UART_BDH bitfields
00182  */
00183 
00184 /*!
00185  * @name Register UART_BDH, field SBR[4:0] (RW)
00186  *
00187  * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
00188  * generation for details. The baud rate generator is disabled until C2[TE] or
00189  * C2[RE] is set for the first time after reset.The baud rate generator is disabled
00190  * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
00191  * writing to BDH puts the data in a temporary location until BDL is written.
00192  */
00193 /*@{*/
00194 #define BP_UART_BDH_SBR      (0U)          /*!< Bit position for UART_BDH_SBR. */
00195 #define BM_UART_BDH_SBR      (0x1FU)       /*!< Bit mask for UART_BDH_SBR. */
00196 #define BS_UART_BDH_SBR      (5U)          /*!< Bit field size in bits for UART_BDH_SBR. */
00197 
00198 /*! @brief Read current value of the UART_BDH_SBR field. */
00199 #define BR_UART_BDH_SBR(x)   (HW_UART_BDH(x).B.SBR)
00200 
00201 /*! @brief Format value for bitfield UART_BDH_SBR. */
00202 #define BF_UART_BDH_SBR(v)   ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR)
00203 
00204 /*! @brief Set the SBR field to a new value. */
00205 #define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
00206 /*@}*/
00207 
00208 /*!
00209  * @name Register UART_BDH, field SBNS[5] (RW)
00210  *
00211  * SBNS selects the number of stop bits present in a data frame. This field
00212  * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
00213  * C7816[ISO7816E] is enabled.
00214  *
00215  * Values:
00216  * - 0 - Data frame consists of a single stop bit.
00217  * - 1 - Data frame consists of two stop bits.
00218  */
00219 /*@{*/
00220 #define BP_UART_BDH_SBNS     (5U)          /*!< Bit position for UART_BDH_SBNS. */
00221 #define BM_UART_BDH_SBNS     (0x20U)       /*!< Bit mask for UART_BDH_SBNS. */
00222 #define BS_UART_BDH_SBNS     (1U)          /*!< Bit field size in bits for UART_BDH_SBNS. */
00223 
00224 /*! @brief Read current value of the UART_BDH_SBNS field. */
00225 #define BR_UART_BDH_SBNS(x)  (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
00226 
00227 /*! @brief Format value for bitfield UART_BDH_SBNS. */
00228 #define BF_UART_BDH_SBNS(v)  ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBNS) & BM_UART_BDH_SBNS)
00229 
00230 /*! @brief Set the SBNS field to a new value. */
00231 #define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
00232 /*@}*/
00233 
00234 /*!
00235  * @name Register UART_BDH, field RXEDGIE[6] (RW)
00236  *
00237  * Enables the receive input active edge, RXEDGIF, to generate interrupt
00238  * requests.
00239  *
00240  * Values:
00241  * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
00242  * - 1 - RXEDGIF interrupt request enabled.
00243  */
00244 /*@{*/
00245 #define BP_UART_BDH_RXEDGIE  (6U)          /*!< Bit position for UART_BDH_RXEDGIE. */
00246 #define BM_UART_BDH_RXEDGIE  (0x40U)       /*!< Bit mask for UART_BDH_RXEDGIE. */
00247 #define BS_UART_BDH_RXEDGIE  (1U)          /*!< Bit field size in bits for UART_BDH_RXEDGIE. */
00248 
00249 /*! @brief Read current value of the UART_BDH_RXEDGIE field. */
00250 #define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
00251 
00252 /*! @brief Format value for bitfield UART_BDH_RXEDGIE. */
00253 #define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE)
00254 
00255 /*! @brief Set the RXEDGIE field to a new value. */
00256 #define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
00257 /*@}*/
00258 
00259 /*!
00260  * @name Register UART_BDH, field LBKDIE[7] (RW)
00261  *
00262  * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
00263  * based on the state of LBKDDMAS. or DMA transfer requests,
00264  *
00265  * Values:
00266  * - 0 - LBKDIF interrupt and DMA transfer requests disabled.
00267  * - 1 - LBKDIF interrupt or DMA transfer requests enabled.
00268  */
00269 /*@{*/
00270 #define BP_UART_BDH_LBKDIE   (7U)          /*!< Bit position for UART_BDH_LBKDIE. */
00271 #define BM_UART_BDH_LBKDIE   (0x80U)       /*!< Bit mask for UART_BDH_LBKDIE. */
00272 #define BS_UART_BDH_LBKDIE   (1U)          /*!< Bit field size in bits for UART_BDH_LBKDIE. */
00273 
00274 /*! @brief Read current value of the UART_BDH_LBKDIE field. */
00275 #define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
00276 
00277 /*! @brief Format value for bitfield UART_BDH_LBKDIE. */
00278 #define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE)
00279 
00280 /*! @brief Set the LBKDIE field to a new value. */
00281 #define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
00282 /*@}*/
00283 
00284 /*******************************************************************************
00285  * HW_UART_BDL - UART Baud Rate Registers: Low
00286  ******************************************************************************/
00287 
00288 /*!
00289  * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
00290  *
00291  * Reset value: 0x04U
00292  *
00293  * This register, along with the BDH register, controls the prescale divisor for
00294  * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
00295  * first write to BDH to buffer the high half of the new value and then write to
00296  * BDL. The working value in BDH does not change until BDL is written. BDL is
00297  * reset to a nonzero value, but after reset, the baud rate generator remains
00298  * disabled until the first time the receiver or transmitter is enabled, that is, when
00299  * C2[RE] or C2[TE] is set.
00300  */
00301 typedef union _hw_uart_bdl
00302 {
00303     uint8_t U;
00304     struct _hw_uart_bdl_bitfields
00305     {
00306         uint8_t SBR : 8;               /*!< [7:0] UART Baud Rate Bits */
00307     } B;
00308 } hw_uart_bdl_t;
00309 
00310 /*!
00311  * @name Constants and macros for entire UART_BDL register
00312  */
00313 /*@{*/
00314 #define HW_UART_BDL_ADDR(x)      ((x) + 0x1U)
00315 
00316 #define HW_UART_BDL(x)           (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
00317 #define HW_UART_BDL_RD(x)        (HW_UART_BDL(x).U)
00318 #define HW_UART_BDL_WR(x, v)     (HW_UART_BDL(x).U = (v))
00319 #define HW_UART_BDL_SET(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) |  (v)))
00320 #define HW_UART_BDL_CLR(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
00321 #define HW_UART_BDL_TOG(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^  (v)))
00322 /*@}*/
00323 
00324 /*
00325  * Constants & macros for individual UART_BDL bitfields
00326  */
00327 
00328 /*!
00329  * @name Register UART_BDL, field SBR[7:0] (RW)
00330  *
00331  * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
00332  * generation for details. The baud rate generator is disabled until C2[TE] or
00333  * C2[RE] is set for the first time after reset.The baud rate generator is disabled
00334  * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
00335  * writing to BDH puts the data in a temporary location until BDL is written. When
00336  * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
00337  * fields must be even, the least significant bit is 0. See MODEM register for more
00338  * details.
00339  */
00340 /*@{*/
00341 #define BP_UART_BDL_SBR      (0U)          /*!< Bit position for UART_BDL_SBR. */
00342 #define BM_UART_BDL_SBR      (0xFFU)       /*!< Bit mask for UART_BDL_SBR. */
00343 #define BS_UART_BDL_SBR      (8U)          /*!< Bit field size in bits for UART_BDL_SBR. */
00344 
00345 /*! @brief Read current value of the UART_BDL_SBR field. */
00346 #define BR_UART_BDL_SBR(x)   (HW_UART_BDL(x).U)
00347 
00348 /*! @brief Format value for bitfield UART_BDL_SBR. */
00349 #define BF_UART_BDL_SBR(v)   ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR)
00350 
00351 /*! @brief Set the SBR field to a new value. */
00352 #define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
00353 /*@}*/
00354 
00355 /*******************************************************************************
00356  * HW_UART_C1 - UART Control Register 1
00357  ******************************************************************************/
00358 
00359 /*!
00360  * @brief HW_UART_C1 - UART Control Register 1 (RW)
00361  *
00362  * Reset value: 0x00U
00363  *
00364  * This read/write register controls various optional features of the UART
00365  * system.
00366  */
00367 typedef union _hw_uart_c1
00368 {
00369     uint8_t U;
00370     struct _hw_uart_c1_bitfields
00371     {
00372         uint8_t PT : 1;                /*!< [0] Parity Type */
00373         uint8_t PE : 1;                /*!< [1] Parity Enable */
00374         uint8_t ILT : 1;               /*!< [2] Idle Line Type Select */
00375         uint8_t WAKE : 1;              /*!< [3] Receiver Wakeup Method Select */
00376         uint8_t M : 1;                 /*!< [4] 9-bit or 8-bit Mode Select */
00377         uint8_t RSRC : 1;              /*!< [5] Receiver Source Select */
00378         uint8_t UARTSWAI : 1;          /*!< [6] UART Stops in Wait Mode */
00379         uint8_t LOOPS : 1;             /*!< [7] Loop Mode Select */
00380     } B;
00381 } hw_uart_c1_t;
00382 
00383 /*!
00384  * @name Constants and macros for entire UART_C1 register
00385  */
00386 /*@{*/
00387 #define HW_UART_C1_ADDR(x)       ((x) + 0x2U)
00388 
00389 #define HW_UART_C1(x)            (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
00390 #define HW_UART_C1_RD(x)         (HW_UART_C1(x).U)
00391 #define HW_UART_C1_WR(x, v)      (HW_UART_C1(x).U = (v))
00392 #define HW_UART_C1_SET(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) |  (v)))
00393 #define HW_UART_C1_CLR(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
00394 #define HW_UART_C1_TOG(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^  (v)))
00395 /*@}*/
00396 
00397 /*
00398  * Constants & macros for individual UART_C1 bitfields
00399  */
00400 
00401 /*!
00402  * @name Register UART_C1, field PT[0] (RW)
00403  *
00404  * Determines whether the UART generates and checks for even parity or odd
00405  * parity. With even parity, an even number of 1s clears the parity bit and an odd
00406  * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
00407  * parity bit and an even number of 1s sets the parity bit. This field must be
00408  * cleared when C7816[ISO_7816E] is set/enabled.
00409  *
00410  * Values:
00411  * - 0 - Even parity.
00412  * - 1 - Odd parity.
00413  */
00414 /*@{*/
00415 #define BP_UART_C1_PT        (0U)          /*!< Bit position for UART_C1_PT. */
00416 #define BM_UART_C1_PT        (0x01U)       /*!< Bit mask for UART_C1_PT. */
00417 #define BS_UART_C1_PT        (1U)          /*!< Bit field size in bits for UART_C1_PT. */
00418 
00419 /*! @brief Read current value of the UART_C1_PT field. */
00420 #define BR_UART_C1_PT(x)     (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
00421 
00422 /*! @brief Format value for bitfield UART_C1_PT. */
00423 #define BF_UART_C1_PT(v)     ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT)
00424 
00425 /*! @brief Set the PT field to a new value. */
00426 #define BW_UART_C1_PT(x, v)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
00427 /*@}*/
00428 
00429 /*!
00430  * @name Register UART_C1, field PE[1] (RW)
00431  *
00432  * Enables the parity function. When parity is enabled, parity function inserts
00433  * a parity bit in the bit position immediately preceding the stop bit. This
00434  * field must be set when C7816[ISO_7816E] is set/enabled.
00435  *
00436  * Values:
00437  * - 0 - Parity function disabled.
00438  * - 1 - Parity function enabled.
00439  */
00440 /*@{*/
00441 #define BP_UART_C1_PE        (1U)          /*!< Bit position for UART_C1_PE. */
00442 #define BM_UART_C1_PE        (0x02U)       /*!< Bit mask for UART_C1_PE. */
00443 #define BS_UART_C1_PE        (1U)          /*!< Bit field size in bits for UART_C1_PE. */
00444 
00445 /*! @brief Read current value of the UART_C1_PE field. */
00446 #define BR_UART_C1_PE(x)     (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
00447 
00448 /*! @brief Format value for bitfield UART_C1_PE. */
00449 #define BF_UART_C1_PE(v)     ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE)
00450 
00451 /*! @brief Set the PE field to a new value. */
00452 #define BW_UART_C1_PE(x, v)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
00453 /*@}*/
00454 
00455 /*!
00456  * @name Register UART_C1, field ILT[2] (RW)
00457  *
00458  * Determines when the receiver starts counting logic 1s as idle character bits.
00459  * The count begins either after a valid start bit or after the stop bit. If the
00460  * count begins after the start bit, then a string of logic 1s preceding the
00461  * stop bit can cause false recognition of an idle character. Beginning the count
00462  * after the stop bit avoids false idle character recognition, but requires
00463  * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
00464  * logic of 1'b0 is automatically shifted after a received stop bit, therefore
00465  * resetting the idle count. In case the UART is programmed for IDLE line wakeup
00466  * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
00467  * logic 1s as idle character bits. In idle line wakeup, an idle character is
00468  * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
00469  * and C4[M10] fields.
00470  *
00471  * Values:
00472  * - 0 - Idle character bit count starts after start bit.
00473  * - 1 - Idle character bit count starts after stop bit.
00474  */
00475 /*@{*/
00476 #define BP_UART_C1_ILT       (2U)          /*!< Bit position for UART_C1_ILT. */
00477 #define BM_UART_C1_ILT       (0x04U)       /*!< Bit mask for UART_C1_ILT. */
00478 #define BS_UART_C1_ILT       (1U)          /*!< Bit field size in bits for UART_C1_ILT. */
00479 
00480 /*! @brief Read current value of the UART_C1_ILT field. */
00481 #define BR_UART_C1_ILT(x)    (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
00482 
00483 /*! @brief Format value for bitfield UART_C1_ILT. */
00484 #define BF_UART_C1_ILT(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT)
00485 
00486 /*! @brief Set the ILT field to a new value. */
00487 #define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
00488 /*@}*/
00489 
00490 /*!
00491  * @name Register UART_C1, field WAKE[3] (RW)
00492  *
00493  * Determines which condition wakes the UART: Address mark in the most
00494  * significant bit position of a received data character, or An idle condition on the
00495  * receive pin input signal.
00496  *
00497  * Values:
00498  * - 0 - Idle line wakeup.
00499  * - 1 - Address mark wakeup.
00500  */
00501 /*@{*/
00502 #define BP_UART_C1_WAKE      (3U)          /*!< Bit position for UART_C1_WAKE. */
00503 #define BM_UART_C1_WAKE      (0x08U)       /*!< Bit mask for UART_C1_WAKE. */
00504 #define BS_UART_C1_WAKE      (1U)          /*!< Bit field size in bits for UART_C1_WAKE. */
00505 
00506 /*! @brief Read current value of the UART_C1_WAKE field. */
00507 #define BR_UART_C1_WAKE(x)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
00508 
00509 /*! @brief Format value for bitfield UART_C1_WAKE. */
00510 #define BF_UART_C1_WAKE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE)
00511 
00512 /*! @brief Set the WAKE field to a new value. */
00513 #define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
00514 /*@}*/
00515 
00516 /*!
00517  * @name Register UART_C1, field M[4] (RW)
00518  *
00519  * This field must be set when C7816[ISO_7816E] is set/enabled.
00520  *
00521  * Values:
00522  * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
00523  * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
00524  */
00525 /*@{*/
00526 #define BP_UART_C1_M         (4U)          /*!< Bit position for UART_C1_M. */
00527 #define BM_UART_C1_M         (0x10U)       /*!< Bit mask for UART_C1_M. */
00528 #define BS_UART_C1_M         (1U)          /*!< Bit field size in bits for UART_C1_M. */
00529 
00530 /*! @brief Read current value of the UART_C1_M field. */
00531 #define BR_UART_C1_M(x)      (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
00532 
00533 /*! @brief Format value for bitfield UART_C1_M. */
00534 #define BF_UART_C1_M(v)      ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M)
00535 
00536 /*! @brief Set the M field to a new value. */
00537 #define BW_UART_C1_M(x, v)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
00538 /*@}*/
00539 
00540 /*!
00541  * @name Register UART_C1, field RSRC[5] (RW)
00542  *
00543  * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
00544  * is set, the RSRC field determines the source for the receiver shift register
00545  * input.
00546  *
00547  * Values:
00548  * - 0 - Selects internal loop back mode. The receiver input is internally
00549  *     connected to transmitter output.
00550  * - 1 - Single wire UART mode where the receiver input is connected to the
00551  *     transmit pin input signal.
00552  */
00553 /*@{*/
00554 #define BP_UART_C1_RSRC      (5U)          /*!< Bit position for UART_C1_RSRC. */
00555 #define BM_UART_C1_RSRC      (0x20U)       /*!< Bit mask for UART_C1_RSRC. */
00556 #define BS_UART_C1_RSRC      (1U)          /*!< Bit field size in bits for UART_C1_RSRC. */
00557 
00558 /*! @brief Read current value of the UART_C1_RSRC field. */
00559 #define BR_UART_C1_RSRC(x)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
00560 
00561 /*! @brief Format value for bitfield UART_C1_RSRC. */
00562 #define BF_UART_C1_RSRC(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC)
00563 
00564 /*! @brief Set the RSRC field to a new value. */
00565 #define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
00566 /*@}*/
00567 
00568 /*!
00569  * @name Register UART_C1, field UARTSWAI[6] (RW)
00570  *
00571  * Values:
00572  * - 0 - UART clock continues to run in Wait mode.
00573  * - 1 - UART clock freezes while CPU is in Wait mode.
00574  */
00575 /*@{*/
00576 #define BP_UART_C1_UARTSWAI  (6U)          /*!< Bit position for UART_C1_UARTSWAI. */
00577 #define BM_UART_C1_UARTSWAI  (0x40U)       /*!< Bit mask for UART_C1_UARTSWAI. */
00578 #define BS_UART_C1_UARTSWAI  (1U)          /*!< Bit field size in bits for UART_C1_UARTSWAI. */
00579 
00580 /*! @brief Read current value of the UART_C1_UARTSWAI field. */
00581 #define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
00582 
00583 /*! @brief Format value for bitfield UART_C1_UARTSWAI. */
00584 #define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI)
00585 
00586 /*! @brief Set the UARTSWAI field to a new value. */
00587 #define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
00588 /*@}*/
00589 
00590 /*!
00591  * @name Register UART_C1, field LOOPS[7] (RW)
00592  *
00593  * When LOOPS is set, the RxD pin is disconnected from the UART and the
00594  * transmitter output is internally connected to the receiver input. The transmitter and
00595  * the receiver must be enabled to use the loop function.
00596  *
00597  * Values:
00598  * - 0 - Normal operation.
00599  * - 1 - Loop mode where transmitter output is internally connected to receiver
00600  *     input. The receiver input is determined by RSRC.
00601  */
00602 /*@{*/
00603 #define BP_UART_C1_LOOPS     (7U)          /*!< Bit position for UART_C1_LOOPS. */
00604 #define BM_UART_C1_LOOPS     (0x80U)       /*!< Bit mask for UART_C1_LOOPS. */
00605 #define BS_UART_C1_LOOPS     (1U)          /*!< Bit field size in bits for UART_C1_LOOPS. */
00606 
00607 /*! @brief Read current value of the UART_C1_LOOPS field. */
00608 #define BR_UART_C1_LOOPS(x)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
00609 
00610 /*! @brief Format value for bitfield UART_C1_LOOPS. */
00611 #define BF_UART_C1_LOOPS(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS)
00612 
00613 /*! @brief Set the LOOPS field to a new value. */
00614 #define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
00615 /*@}*/
00616 
00617 /*******************************************************************************
00618  * HW_UART_C2 - UART Control Register 2
00619  ******************************************************************************/
00620 
00621 /*!
00622  * @brief HW_UART_C2 - UART Control Register 2 (RW)
00623  *
00624  * Reset value: 0x00U
00625  *
00626  * This register can be read or written at any time.
00627  */
00628 typedef union _hw_uart_c2
00629 {
00630     uint8_t U;
00631     struct _hw_uart_c2_bitfields
00632     {
00633         uint8_t SBK : 1;               /*!< [0] Send Break */
00634         uint8_t RWU : 1;               /*!< [1] Receiver Wakeup Control */
00635         uint8_t RE : 1;                /*!< [2] Receiver Enable */
00636         uint8_t TE : 1;                /*!< [3] Transmitter Enable */
00637         uint8_t ILIE : 1;              /*!< [4] Idle Line Interrupt DMA Transfer Enable */
00638         uint8_t RIE : 1;               /*!< [5] Receiver Full Interrupt or DMA Transfer
00639                                         * Enable */
00640         uint8_t TCIE : 1;              /*!< [6] Transmission Complete Interrupt or DMA
00641                                         * Transfer Enable */
00642         uint8_t TIE : 1;               /*!< [7] Transmitter Interrupt or DMA Transfer
00643                                         * Enable. */
00644     } B;
00645 } hw_uart_c2_t;
00646 
00647 /*!
00648  * @name Constants and macros for entire UART_C2 register
00649  */
00650 /*@{*/
00651 #define HW_UART_C2_ADDR(x)       ((x) + 0x3U)
00652 
00653 #define HW_UART_C2(x)            (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
00654 #define HW_UART_C2_RD(x)         (HW_UART_C2(x).U)
00655 #define HW_UART_C2_WR(x, v)      (HW_UART_C2(x).U = (v))
00656 #define HW_UART_C2_SET(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) |  (v)))
00657 #define HW_UART_C2_CLR(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
00658 #define HW_UART_C2_TOG(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^  (v)))
00659 /*@}*/
00660 
00661 /*
00662  * Constants & macros for individual UART_C2 bitfields
00663  */
00664 
00665 /*!
00666  * @name Register UART_C2, field SBK[0] (RW)
00667  *
00668  * Toggling SBK sends one break character from the following: See Transmitting
00669  * break characters for the number of logic 0s for the different configurations.
00670  * Toggling implies clearing the SBK field before the break character has finished
00671  * transmitting. As long as SBK is set, the transmitter continues to send
00672  * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
00673  * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
00674  * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
00675  * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
00676  * C7816[ISO_7816E] is set.
00677  *
00678  * Values:
00679  * - 0 - Normal transmitter operation.
00680  * - 1 - Queue break characters to be sent.
00681  */
00682 /*@{*/
00683 #define BP_UART_C2_SBK       (0U)          /*!< Bit position for UART_C2_SBK. */
00684 #define BM_UART_C2_SBK       (0x01U)       /*!< Bit mask for UART_C2_SBK. */
00685 #define BS_UART_C2_SBK       (1U)          /*!< Bit field size in bits for UART_C2_SBK. */
00686 
00687 /*! @brief Read current value of the UART_C2_SBK field. */
00688 #define BR_UART_C2_SBK(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
00689 
00690 /*! @brief Format value for bitfield UART_C2_SBK. */
00691 #define BF_UART_C2_SBK(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK)
00692 
00693 /*! @brief Set the SBK field to a new value. */
00694 #define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
00695 /*@}*/
00696 
00697 /*!
00698  * @name Register UART_C2, field RWU[1] (RW)
00699  *
00700  * This field can be set to place the UART receiver in a standby state. RWU
00701  * automatically clears when an RWU event occurs, that is, an IDLE event when
00702  * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
00703  * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
00704  * on idle) if the channel is currently not idle. This can be determined by
00705  * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
00706  * idle, it is possible that the UART will discard data. This is because the data
00707  * must be received or a LIN break detected after an IDLE is detected before IDLE
00708  * is allowed to reasserted.
00709  *
00710  * Values:
00711  * - 0 - Normal operation.
00712  * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
00713  *     requests. Normally, hardware wakes the receiver by automatically clearing
00714  *     RWU.
00715  */
00716 /*@{*/
00717 #define BP_UART_C2_RWU       (1U)          /*!< Bit position for UART_C2_RWU. */
00718 #define BM_UART_C2_RWU       (0x02U)       /*!< Bit mask for UART_C2_RWU. */
00719 #define BS_UART_C2_RWU       (1U)          /*!< Bit field size in bits for UART_C2_RWU. */
00720 
00721 /*! @brief Read current value of the UART_C2_RWU field. */
00722 #define BR_UART_C2_RWU(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
00723 
00724 /*! @brief Format value for bitfield UART_C2_RWU. */
00725 #define BF_UART_C2_RWU(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU)
00726 
00727 /*! @brief Set the RWU field to a new value. */
00728 #define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
00729 /*@}*/
00730 
00731 /*!
00732  * @name Register UART_C2, field RE[2] (RW)
00733  *
00734  * Enables the UART receiver.
00735  *
00736  * Values:
00737  * - 0 - Receiver off.
00738  * - 1 - Receiver on.
00739  */
00740 /*@{*/
00741 #define BP_UART_C2_RE        (2U)          /*!< Bit position for UART_C2_RE. */
00742 #define BM_UART_C2_RE        (0x04U)       /*!< Bit mask for UART_C2_RE. */
00743 #define BS_UART_C2_RE        (1U)          /*!< Bit field size in bits for UART_C2_RE. */
00744 
00745 /*! @brief Read current value of the UART_C2_RE field. */
00746 #define BR_UART_C2_RE(x)     (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
00747 
00748 /*! @brief Format value for bitfield UART_C2_RE. */
00749 #define BF_UART_C2_RE(v)     ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE)
00750 
00751 /*! @brief Set the RE field to a new value. */
00752 #define BW_UART_C2_RE(x, v)  (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
00753 /*@}*/
00754 
00755 /*!
00756  * @name Register UART_C2, field TE[3] (RW)
00757  *
00758  * Enables the UART transmitter. TE can be used to queue an idle preamble by
00759  * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
00760  * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
00761  * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
00762  * additional characters are transmitted.
00763  *
00764  * Values:
00765  * - 0 - Transmitter off.
00766  * - 1 - Transmitter on.
00767  */
00768 /*@{*/
00769 #define BP_UART_C2_TE        (3U)          /*!< Bit position for UART_C2_TE. */
00770 #define BM_UART_C2_TE        (0x08U)       /*!< Bit mask for UART_C2_TE. */
00771 #define BS_UART_C2_TE        (1U)          /*!< Bit field size in bits for UART_C2_TE. */
00772 
00773 /*! @brief Read current value of the UART_C2_TE field. */
00774 #define BR_UART_C2_TE(x)     (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
00775 
00776 /*! @brief Format value for bitfield UART_C2_TE. */
00777 #define BF_UART_C2_TE(v)     ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE)
00778 
00779 /*! @brief Set the TE field to a new value. */
00780 #define BW_UART_C2_TE(x, v)  (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
00781 /*@}*/
00782 
00783 /*!
00784  * @name Register UART_C2, field ILIE[4] (RW)
00785  *
00786  * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
00787  * transfer requests based on the state of C5[ILDMAS].
00788  *
00789  * Values:
00790  * - 0 - IDLE interrupt requests disabled. and DMA transfer
00791  * - 1 - IDLE interrupt requests enabled. or DMA transfer
00792  */
00793 /*@{*/
00794 #define BP_UART_C2_ILIE      (4U)          /*!< Bit position for UART_C2_ILIE. */
00795 #define BM_UART_C2_ILIE      (0x10U)       /*!< Bit mask for UART_C2_ILIE. */
00796 #define BS_UART_C2_ILIE      (1U)          /*!< Bit field size in bits for UART_C2_ILIE. */
00797 
00798 /*! @brief Read current value of the UART_C2_ILIE field. */
00799 #define BR_UART_C2_ILIE(x)   (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
00800 
00801 /*! @brief Format value for bitfield UART_C2_ILIE. */
00802 #define BF_UART_C2_ILIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE)
00803 
00804 /*! @brief Set the ILIE field to a new value. */
00805 #define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
00806 /*@}*/
00807 
00808 /*!
00809  * @name Register UART_C2, field RIE[5] (RW)
00810  *
00811  * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
00812  * based on the state of C5[RDMAS].
00813  *
00814  * Values:
00815  * - 0 - RDRF interrupt and DMA transfer requests disabled.
00816  * - 1 - RDRF interrupt or DMA transfer requests enabled.
00817  */
00818 /*@{*/
00819 #define BP_UART_C2_RIE       (5U)          /*!< Bit position for UART_C2_RIE. */
00820 #define BM_UART_C2_RIE       (0x20U)       /*!< Bit mask for UART_C2_RIE. */
00821 #define BS_UART_C2_RIE       (1U)          /*!< Bit field size in bits for UART_C2_RIE. */
00822 
00823 /*! @brief Read current value of the UART_C2_RIE field. */
00824 #define BR_UART_C2_RIE(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
00825 
00826 /*! @brief Format value for bitfield UART_C2_RIE. */
00827 #define BF_UART_C2_RIE(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE)
00828 
00829 /*! @brief Set the RIE field to a new value. */
00830 #define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
00831 /*@}*/
00832 
00833 /*!
00834  * @name Register UART_C2, field TCIE[6] (RW)
00835  *
00836  * Enables the transmission complete flag, S1[TC], to generate interrupt
00837  * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
00838  * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
00839  * written unless servicing a DMA request.
00840  *
00841  * Values:
00842  * - 0 - TC interrupt and DMA transfer requests disabled.
00843  * - 1 - TC interrupt or DMA transfer requests enabled.
00844  */
00845 /*@{*/
00846 #define BP_UART_C2_TCIE      (6U)          /*!< Bit position for UART_C2_TCIE. */
00847 #define BM_UART_C2_TCIE      (0x40U)       /*!< Bit mask for UART_C2_TCIE. */
00848 #define BS_UART_C2_TCIE      (1U)          /*!< Bit field size in bits for UART_C2_TCIE. */
00849 
00850 /*! @brief Read current value of the UART_C2_TCIE field. */
00851 #define BR_UART_C2_TCIE(x)   (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
00852 
00853 /*! @brief Format value for bitfield UART_C2_TCIE. */
00854 #define BF_UART_C2_TCIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE)
00855 
00856 /*! @brief Set the TCIE field to a new value. */
00857 #define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
00858 /*@}*/
00859 
00860 /*!
00861  * @name Register UART_C2, field TIE[7] (RW)
00862  *
00863  * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
00864  * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
00865  * must be cleared, and D[D] must not be written unless servicing a DMA request.
00866  *
00867  * Values:
00868  * - 0 - TDRE interrupt and DMA transfer requests disabled.
00869  * - 1 - TDRE interrupt or DMA transfer requests enabled.
00870  */
00871 /*@{*/
00872 #define BP_UART_C2_TIE       (7U)          /*!< Bit position for UART_C2_TIE. */
00873 #define BM_UART_C2_TIE       (0x80U)       /*!< Bit mask for UART_C2_TIE. */
00874 #define BS_UART_C2_TIE       (1U)          /*!< Bit field size in bits for UART_C2_TIE. */
00875 
00876 /*! @brief Read current value of the UART_C2_TIE field. */
00877 #define BR_UART_C2_TIE(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
00878 
00879 /*! @brief Format value for bitfield UART_C2_TIE. */
00880 #define BF_UART_C2_TIE(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE)
00881 
00882 /*! @brief Set the TIE field to a new value. */
00883 #define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
00884 /*@}*/
00885 
00886 /*******************************************************************************
00887  * HW_UART_S1 - UART Status Register 1
00888  ******************************************************************************/
00889 
00890 /*!
00891  * @brief HW_UART_S1 - UART Status Register 1 (RO)
00892  *
00893  * Reset value: 0xC0U
00894  *
00895  * The S1 register provides inputs to the MCU for generation of UART interrupts
00896  * or DMA requests. This register can also be polled by the MCU to check the
00897  * status of its fields. To clear a flag, the status register should be read followed
00898  * by a read or write to D register, depending on the interrupt flag type. Other
00899  * instructions can be executed between the two steps as long the handling of
00900  * I/O is not compromised, but the order of operations is important for flag
00901  * clearing. When a flag is configured to trigger a DMA request, assertion of the
00902  * associated DMA done signal from the DMA controller clears the flag. If the
00903  * condition that results in the assertion of the flag, interrupt, or DMA request is not
00904  * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
00905  * reasserts. For example, if the DMA or interrupt service routine fails to write
00906  * sufficient data to the transmit buffer to raise it above the watermark level, the
00907  * flag reasserts and generates another interrupt or DMA request. Reading an
00908  * empty data register to clear one of the flags of the S1 register causes the FIFO
00909  * pointers to become misaligned. A receive FIFO flush reinitializes the
00910  * pointers. A better way to prevent this situation is to always leave one byte in FIFO
00911  * and this byte will be read eventually in clearing the flag bit.
00912  */
00913 typedef union _hw_uart_s1
00914 {
00915     uint8_t U;
00916     struct _hw_uart_s1_bitfields
00917     {
00918         uint8_t PF : 1;                /*!< [0] Parity Error Flag */
00919         uint8_t FE : 1;                /*!< [1] Framing Error Flag */
00920         uint8_t NF : 1;                /*!< [2] Noise Flag */
00921         uint8_t OR : 1;                /*!< [3] Receiver Overrun Flag */
00922         uint8_t IDLE : 1;              /*!< [4] Idle Line Flag */
00923         uint8_t RDRF : 1;              /*!< [5] Receive Data Register Full Flag */
00924         uint8_t TC : 1;                /*!< [6] Transmit Complete Flag */
00925         uint8_t TDRE : 1;              /*!< [7] Transmit Data Register Empty Flag */
00926     } B;
00927 } hw_uart_s1_t;
00928 
00929 /*!
00930  * @name Constants and macros for entire UART_S1 register
00931  */
00932 /*@{*/
00933 #define HW_UART_S1_ADDR(x)       ((x) + 0x4U)
00934 
00935 #define HW_UART_S1(x)            (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
00936 #define HW_UART_S1_RD(x)         (HW_UART_S1(x).U)
00937 /*@}*/
00938 
00939 /*
00940  * Constants & macros for individual UART_S1 bitfields
00941  */
00942 
00943 /*!
00944  * @name Register UART_S1, field PF[0] (RO)
00945  *
00946  * PF is set when PE is set and the parity of the received data does not match
00947  * its parity bit. The PF is not set in the case of an overrun condition. When PF
00948  * is set, it indicates only that a dataword was received with parity error since
00949  * the last time it was cleared. There is no guarantee that the first dataword
00950  * read from the receive buffer has a parity error or that there is only one
00951  * dataword in the buffer that was received with a parity error, unless the receive
00952  * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
00953  * disabled, Within the receive buffer structure the received dataword is tagged
00954  * if it is received with a parity error. This information is available by reading
00955  * the ED register prior to reading the D register.
00956  *
00957  * Values:
00958  * - 0 - No parity error detected since the last time this flag was cleared. If
00959  *     the receive buffer has a depth greater than 1, then there may be data in
00960  *     the receive buffer what was received with a parity error.
00961  * - 1 - At least one dataword was received with a parity error since the last
00962  *     time this flag was cleared.
00963  */
00964 /*@{*/
00965 #define BP_UART_S1_PF        (0U)          /*!< Bit position for UART_S1_PF. */
00966 #define BM_UART_S1_PF        (0x01U)       /*!< Bit mask for UART_S1_PF. */
00967 #define BS_UART_S1_PF        (1U)          /*!< Bit field size in bits for UART_S1_PF. */
00968 
00969 /*! @brief Read current value of the UART_S1_PF field. */
00970 #define BR_UART_S1_PF(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
00971 /*@}*/
00972 
00973 /*!
00974  * @name Register UART_S1, field FE[1] (RO)
00975  *
00976  * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
00977  * then FE will set when a logic 0 is accepted for either of the two stop bits.
00978  * FE does not set in the case of an overrun or while the LIN break detect feature
00979  * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
00980  * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
00981  * receive buffer represents the data that was received with the frame error
00982  * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
00983  * this flag is set, data is still not received in 7816 mode.
00984  *
00985  * Values:
00986  * - 0 - No framing error detected.
00987  * - 1 - Framing error.
00988  */
00989 /*@{*/
00990 #define BP_UART_S1_FE        (1U)          /*!< Bit position for UART_S1_FE. */
00991 #define BM_UART_S1_FE        (0x02U)       /*!< Bit mask for UART_S1_FE. */
00992 #define BS_UART_S1_FE        (1U)          /*!< Bit field size in bits for UART_S1_FE. */
00993 
00994 /*! @brief Read current value of the UART_S1_FE field. */
00995 #define BR_UART_S1_FE(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
00996 /*@}*/
00997 
00998 /*!
00999  * @name Register UART_S1, field NF[2] (RO)
01000  *
01001  * NF is set when the UART detects noise on the receiver input. NF does not
01002  * become set in the case of an overrun or while the LIN break detect feature is
01003  * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
01004  * been received with noise since the last time it was cleared. There is no
01005  * guarantee that the first dataword read from the receive buffer has noise or that there
01006  * is only one dataword in the buffer that was received with noise unless the
01007  * receive buffer has a depth of one. To clear NF, read S1 and then read D.
01008  *
01009  * Values:
01010  * - 0 - No noise detected since the last time this flag was cleared. If the
01011  *     receive buffer has a depth greater than 1 then there may be data in the
01012  *     receiver buffer that was received with noise.
01013  * - 1 - At least one dataword was received with noise detected since the last
01014  *     time the flag was cleared.
01015  */
01016 /*@{*/
01017 #define BP_UART_S1_NF        (2U)          /*!< Bit position for UART_S1_NF. */
01018 #define BM_UART_S1_NF        (0x04U)       /*!< Bit mask for UART_S1_NF. */
01019 #define BS_UART_S1_NF        (1U)          /*!< Bit field size in bits for UART_S1_NF. */
01020 
01021 /*! @brief Read current value of the UART_S1_NF field. */
01022 #define BR_UART_S1_NF(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
01023 /*@}*/
01024 
01025 /*!
01026  * @name Register UART_S1, field OR[3] (RO)
01027  *
01028  * OR is set when software fails to prevent the receive data register from
01029  * overflowing with data. The OR bit is set immediately after the stop bit has been
01030  * completely received for the dataword that overflows the buffer and all the other
01031  * error flags (FE, NF, and PF) are prevented from setting. The data in the
01032  * shift register is lost, but the data already in the UART data registers is not
01033  * affected. If the OR flag is set, no data is stored in the data buffer even if
01034  * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
01035  * flags are blocked from asserting, that is, transition from an inactive to an
01036  * active state. To clear OR, read S1 when OR is set and then read D. See
01037  * functional description for more details regarding the operation of the OR bit.If
01038  * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
01039  * is not cleared before the next data character is received. In 7816 mode, it is
01040  * possible to configure a NACK to be returned by programing C7816[ONACK].
01041  *
01042  * Values:
01043  * - 0 - No overrun has occurred since the last time the flag was cleared.
01044  * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
01045  *     last overrun occured.
01046  */
01047 /*@{*/
01048 #define BP_UART_S1_OR        (3U)          /*!< Bit position for UART_S1_OR. */
01049 #define BM_UART_S1_OR        (0x08U)       /*!< Bit mask for UART_S1_OR. */
01050 #define BS_UART_S1_OR        (1U)          /*!< Bit field size in bits for UART_S1_OR. */
01051 
01052 /*! @brief Read current value of the UART_S1_OR field. */
01053 #define BR_UART_S1_OR(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
01054 /*@}*/
01055 
01056 /*!
01057  * @name Register UART_S1, field IDLE[4] (RO)
01058  *
01059  * After the IDLE flag is cleared, a frame must be received (although not
01060  * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
01061  * break character must set the S2[LBKDIF] flag before an idle condition can set the
01062  * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
01063  * IDLE is set when either of the following appear on the receiver input: 10
01064  * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
01065  * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
01066  * detection is not supported when 7816E is set/enabled and hence this flag is
01067  * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
01068  * flag if RWUID is set, else the IDLE flag does not become set.
01069  *
01070  * Values:
01071  * - 0 - Receiver input is either active now or has never become active since
01072  *     the IDLE flag was last cleared.
01073  * - 1 - Receiver input has become idle or the flag has not been cleared since
01074  *     it last asserted.
01075  */
01076 /*@{*/
01077 #define BP_UART_S1_IDLE      (4U)          /*!< Bit position for UART_S1_IDLE. */
01078 #define BM_UART_S1_IDLE      (0x10U)       /*!< Bit mask for UART_S1_IDLE. */
01079 #define BS_UART_S1_IDLE      (1U)          /*!< Bit field size in bits for UART_S1_IDLE. */
01080 
01081 /*! @brief Read current value of the UART_S1_IDLE field. */
01082 #define BR_UART_S1_IDLE(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
01083 /*@}*/
01084 
01085 /*!
01086  * @name Register UART_S1, field RDRF[5] (RO)
01087  *
01088  * RDRF is set when the number of datawords in the receive buffer is equal to or
01089  * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
01090  * process of being received is not included in the count. To clear RDRF, read S1
01091  * when RDRF is set and then read D. For more efficient interrupt and DMA
01092  * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
01093  * Then read S1 and the final data value, resulting in the clearing of the RDRF
01094  * flag. Even if RDRF is set, data will continue to be received until an overrun
01095  * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
01096  * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
01097  * buffer but over-write each other.
01098  *
01099  * Values:
01100  * - 0 - The number of datawords in the receive buffer is less than the number
01101  *     indicated by RXWATER.
01102  * - 1 - The number of datawords in the receive buffer is equal to or greater
01103  *     than the number indicated by RXWATER at some point in time since this flag
01104  *     was last cleared.
01105  */
01106 /*@{*/
01107 #define BP_UART_S1_RDRF      (5U)          /*!< Bit position for UART_S1_RDRF. */
01108 #define BM_UART_S1_RDRF      (0x20U)       /*!< Bit mask for UART_S1_RDRF. */
01109 #define BS_UART_S1_RDRF      (1U)          /*!< Bit field size in bits for UART_S1_RDRF. */
01110 
01111 /*! @brief Read current value of the UART_S1_RDRF field. */
01112 #define BR_UART_S1_RDRF(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
01113 /*@}*/
01114 
01115 /*!
01116  * @name Register UART_S1, field TC[6] (RO)
01117  *
01118  * TC is set when the transmit buffer is empty and no data, preamble, or break
01119  * character is being transmitted. When TC is set, the transmit data output signal
01120  * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
01121  * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
01122  * set after any NACK signal has been received, but prior to any corresponding
01123  * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
01124  * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
01125  * in C2.
01126  *
01127  * Values:
01128  * - 0 - Transmitter active (sending data, a preamble, or a break).
01129  * - 1 - Transmitter idle (transmission activity complete).
01130  */
01131 /*@{*/
01132 #define BP_UART_S1_TC        (6U)          /*!< Bit position for UART_S1_TC. */
01133 #define BM_UART_S1_TC        (0x40U)       /*!< Bit mask for UART_S1_TC. */
01134 #define BS_UART_S1_TC        (1U)          /*!< Bit field size in bits for UART_S1_TC. */
01135 
01136 /*! @brief Read current value of the UART_S1_TC field. */
01137 #define BR_UART_S1_TC(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
01138 /*@}*/
01139 
01140 /*!
01141  * @name Register UART_S1, field TDRE[7] (RO)
01142  *
01143  * TDRE will set when the number of datawords in the transmit buffer (D and
01144  * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
01145  * character that is in the process of being transmitted is not included in the count.
01146  * To clear TDRE, read S1 when TDRE is set and then write to the UART data
01147  * register (D). For more efficient interrupt servicing, all data except the final value
01148  * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
01149  * before writing the final data value, resulting in the clearing of the TRDE
01150  * flag. This is more efficient because the TDRE reasserts until the watermark has
01151  * been exceeded. So, attempting to clear the TDRE with every write will be
01152  * ineffective until sufficient data has been written.
01153  *
01154  * Values:
01155  * - 0 - The amount of data in the transmit buffer is greater than the value
01156  *     indicated by TWFIFO[TXWATER].
01157  * - 1 - The amount of data in the transmit buffer is less than or equal to the
01158  *     value indicated by TWFIFO[TXWATER] at some point in time since the flag
01159  *     has been cleared.
01160  */
01161 /*@{*/
01162 #define BP_UART_S1_TDRE      (7U)          /*!< Bit position for UART_S1_TDRE. */
01163 #define BM_UART_S1_TDRE      (0x80U)       /*!< Bit mask for UART_S1_TDRE. */
01164 #define BS_UART_S1_TDRE      (1U)          /*!< Bit field size in bits for UART_S1_TDRE. */
01165 
01166 /*! @brief Read current value of the UART_S1_TDRE field. */
01167 #define BR_UART_S1_TDRE(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
01168 /*@}*/
01169 
01170 /*******************************************************************************
01171  * HW_UART_S2 - UART Status Register 2
01172  ******************************************************************************/
01173 
01174 /*!
01175  * @brief HW_UART_S2 - UART Status Register 2 (RW)
01176  *
01177  * Reset value: 0x00U
01178  *
01179  * The S2 register provides inputs to the MCU for generation of UART interrupts
01180  * or DMA requests. Also, this register can be polled by the MCU to check the
01181  * status of these bits. This register can be read or written at any time, with the
01182  * exception of the MSBF and RXINV bits, which should be changed by the user only
01183  * between transmit and receive packets.
01184  */
01185 typedef union _hw_uart_s2
01186 {
01187     uint8_t U;
01188     struct _hw_uart_s2_bitfields
01189     {
01190         uint8_t RAF : 1;               /*!< [0] Receiver Active Flag */
01191         uint8_t LBKDE : 1;             /*!< [1] LIN Break Detection Enable */
01192         uint8_t BRK13 : 1;             /*!< [2] Break Transmit Character Length */
01193         uint8_t RWUID : 1;             /*!< [3] Receive Wakeup Idle Detect */
01194         uint8_t RXINV : 1;             /*!< [4] Receive Data Inversion */
01195         uint8_t MSBF : 1;              /*!< [5] Most Significant Bit First */
01196         uint8_t RXEDGIF : 1;           /*!< [6] RxD Pin Active Edge Interrupt Flag */
01197         uint8_t LBKDIF : 1;            /*!< [7] LIN Break Detect Interrupt Flag */
01198     } B;
01199 } hw_uart_s2_t;
01200 
01201 /*!
01202  * @name Constants and macros for entire UART_S2 register
01203  */
01204 /*@{*/
01205 #define HW_UART_S2_ADDR(x)       ((x) + 0x5U)
01206 
01207 #define HW_UART_S2(x)            (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
01208 #define HW_UART_S2_RD(x)         (HW_UART_S2(x).U)
01209 #define HW_UART_S2_WR(x, v)      (HW_UART_S2(x).U = (v))
01210 #define HW_UART_S2_SET(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) |  (v)))
01211 #define HW_UART_S2_CLR(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
01212 #define HW_UART_S2_TOG(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^  (v)))
01213 /*@}*/
01214 
01215 /*
01216  * Constants & macros for individual UART_S2 bitfields
01217  */
01218 
01219 /*!
01220  * @name Register UART_S2, field RAF[0] (RO)
01221  *
01222  * RAF is set when the UART receiver detects a logic 0 during the RT1 time
01223  * period of the start bit search. RAF is cleared when the receiver detects an idle
01224  * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
01225  * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
01226  * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
01227  * to configure the guard time to 12. However, if a NACK is required to be
01228  * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
01229  * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
01230  * prior to actually being inactive.
01231  *
01232  * Values:
01233  * - 0 - UART receiver idle/inactive waiting for a start bit.
01234  * - 1 - UART receiver active, RxD input not idle.
01235  */
01236 /*@{*/
01237 #define BP_UART_S2_RAF       (0U)          /*!< Bit position for UART_S2_RAF. */
01238 #define BM_UART_S2_RAF       (0x01U)       /*!< Bit mask for UART_S2_RAF. */
01239 #define BS_UART_S2_RAF       (1U)          /*!< Bit field size in bits for UART_S2_RAF. */
01240 
01241 /*! @brief Read current value of the UART_S2_RAF field. */
01242 #define BR_UART_S2_RAF(x)    (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
01243 /*@}*/
01244 
01245 /*!
01246  * @name Register UART_S2, field LBKDE[1] (RW)
01247  *
01248  * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
01249  * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
01250  * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
01251  *
01252  * Values:
01253  * - 0 - Break character detection is disabled.
01254  * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
01255  *     12 bits time if C1[M] = 1.
01256  */
01257 /*@{*/
01258 #define BP_UART_S2_LBKDE     (1U)          /*!< Bit position for UART_S2_LBKDE. */
01259 #define BM_UART_S2_LBKDE     (0x02U)       /*!< Bit mask for UART_S2_LBKDE. */
01260 #define BS_UART_S2_LBKDE     (1U)          /*!< Bit field size in bits for UART_S2_LBKDE. */
01261 
01262 /*! @brief Read current value of the UART_S2_LBKDE field. */
01263 #define BR_UART_S2_LBKDE(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
01264 
01265 /*! @brief Format value for bitfield UART_S2_LBKDE. */
01266 #define BF_UART_S2_LBKDE(v)  ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE)
01267 
01268 /*! @brief Set the LBKDE field to a new value. */
01269 #define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
01270 /*@}*/
01271 
01272 /*!
01273  * @name Register UART_S2, field BRK13[2] (RW)
01274  *
01275  * Determines whether the transmit break character is 10, 11, or 12 bits long,
01276  * or 13 or 14 bits long. See for the length of the break character for the
01277  * different configurations. The detection of a framing error is not affected by this
01278  * field. Transmitting break characters
01279  *
01280  * Values:
01281  * - 0 - Break character is 10, 11, or 12 bits long.
01282  * - 1 - Break character is 13 or 14 bits long.
01283  */
01284 /*@{*/
01285 #define BP_UART_S2_BRK13     (2U)          /*!< Bit position for UART_S2_BRK13. */
01286 #define BM_UART_S2_BRK13     (0x04U)       /*!< Bit mask for UART_S2_BRK13. */
01287 #define BS_UART_S2_BRK13     (1U)          /*!< Bit field size in bits for UART_S2_BRK13. */
01288 
01289 /*! @brief Read current value of the UART_S2_BRK13 field. */
01290 #define BR_UART_S2_BRK13(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
01291 
01292 /*! @brief Format value for bitfield UART_S2_BRK13. */
01293 #define BF_UART_S2_BRK13(v)  ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13)
01294 
01295 /*! @brief Set the BRK13 field to a new value. */
01296 #define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
01297 /*@}*/
01298 
01299 /*!
01300  * @name Register UART_S2, field RWUID[3] (RW)
01301  *
01302  * When RWU is set and WAKE is cleared, this field controls whether the idle
01303  * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
01304  * C7816[ISO7816E] is set/enabled.
01305  *
01306  * Values:
01307  * - 0 - S1[IDLE] is not set upon detection of an idle character.
01308  * - 1 - S1[IDLE] is set upon detection of an idle character.
01309  */
01310 /*@{*/
01311 #define BP_UART_S2_RWUID     (3U)          /*!< Bit position for UART_S2_RWUID. */
01312 #define BM_UART_S2_RWUID     (0x08U)       /*!< Bit mask for UART_S2_RWUID. */
01313 #define BS_UART_S2_RWUID     (1U)          /*!< Bit field size in bits for UART_S2_RWUID. */
01314 
01315 /*! @brief Read current value of the UART_S2_RWUID field. */
01316 #define BR_UART_S2_RWUID(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
01317 
01318 /*! @brief Format value for bitfield UART_S2_RWUID. */
01319 #define BF_UART_S2_RWUID(v)  ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID)
01320 
01321 /*! @brief Set the RWUID field to a new value. */
01322 #define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
01323 /*@}*/
01324 
01325 /*!
01326  * @name Register UART_S2, field RXINV[4] (RW)
01327  *
01328  * Setting this field reverses the polarity of the received data input. In NRZ
01329  * format, a one is represented by a mark and a zero is represented by a space for
01330  * normal polarity, and the opposite for inverted polarity. In IrDA format, a
01331  * zero is represented by short high pulse in the middle of a bit time remaining
01332  * idle low for a one for normal polarity. A zero is represented by a short low
01333  * pulse in the middle of a bit time remaining idle high for a one for inverted
01334  * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
01335  * enabled and an initial character is detected in T = 0 protocol mode. Setting
01336  * RXINV inverts the RxD input for data bits, start and stop bits, break, and
01337  * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
01338  * are inverted.
01339  *
01340  * Values:
01341  * - 0 - Receive data is not inverted.
01342  * - 1 - Receive data is inverted.
01343  */
01344 /*@{*/
01345 #define BP_UART_S2_RXINV     (4U)          /*!< Bit position for UART_S2_RXINV. */
01346 #define BM_UART_S2_RXINV     (0x10U)       /*!< Bit mask for UART_S2_RXINV. */
01347 #define BS_UART_S2_RXINV     (1U)          /*!< Bit field size in bits for UART_S2_RXINV. */
01348 
01349 /*! @brief Read current value of the UART_S2_RXINV field. */
01350 #define BR_UART_S2_RXINV(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
01351 
01352 /*! @brief Format value for bitfield UART_S2_RXINV. */
01353 #define BF_UART_S2_RXINV(v)  ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV)
01354 
01355 /*! @brief Set the RXINV field to a new value. */
01356 #define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
01357 /*@}*/
01358 
01359 /*!
01360  * @name Register UART_S2, field MSBF[5] (RW)
01361  *
01362  * Setting this field reverses the order of the bits that are transmitted and
01363  * received on the wire. This field does not affect the polarity of the bits, the
01364  * location of the parity bit, or the location of the start or stop bits. This
01365  * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
01366  * an initial character is detected in T = 0 protocol mode.
01367  *
01368  * Values:
01369  * - 0 - LSB (bit0) is the first bit that is transmitted following the start
01370  *     bit. Further, the first bit received after the start bit is identified as
01371  *     bit0.
01372  * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
01373  *     the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
01374  *     first bit received after the start bit is identified as bit8, bit7, or
01375  *     bit6, depending on the setting of C1[M] and C1[PE].
01376  */
01377 /*@{*/
01378 #define BP_UART_S2_MSBF      (5U)          /*!< Bit position for UART_S2_MSBF. */
01379 #define BM_UART_S2_MSBF      (0x20U)       /*!< Bit mask for UART_S2_MSBF. */
01380 #define BS_UART_S2_MSBF      (1U)          /*!< Bit field size in bits for UART_S2_MSBF. */
01381 
01382 /*! @brief Read current value of the UART_S2_MSBF field. */
01383 #define BR_UART_S2_MSBF(x)   (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
01384 
01385 /*! @brief Format value for bitfield UART_S2_MSBF. */
01386 #define BF_UART_S2_MSBF(v)   ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF)
01387 
01388 /*! @brief Set the MSBF field to a new value. */
01389 #define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
01390 /*@}*/
01391 
01392 /*!
01393  * @name Register UART_S2, field RXEDGIF[6] (W1C)
01394  *
01395  * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
01396  * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
01397  * to it. See for additional details. RXEDGIF description The active edge is
01398  * detected only in two wire mode and on receiving data coming from the RxD pin.
01399  *
01400  * Values:
01401  * - 0 - No active edge on the receive pin has occurred.
01402  * - 1 - An active edge on the receive pin has occurred.
01403  */
01404 /*@{*/
01405 #define BP_UART_S2_RXEDGIF   (6U)          /*!< Bit position for UART_S2_RXEDGIF. */
01406 #define BM_UART_S2_RXEDGIF   (0x40U)       /*!< Bit mask for UART_S2_RXEDGIF. */
01407 #define BS_UART_S2_RXEDGIF   (1U)          /*!< Bit field size in bits for UART_S2_RXEDGIF. */
01408 
01409 /*! @brief Read current value of the UART_S2_RXEDGIF field. */
01410 #define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
01411 
01412 /*! @brief Format value for bitfield UART_S2_RXEDGIF. */
01413 #define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF)
01414 
01415 /*! @brief Set the RXEDGIF field to a new value. */
01416 #define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
01417 /*@}*/
01418 
01419 /*!
01420  * @name Register UART_S2, field LBKDIF[7] (W1C)
01421  *
01422  * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
01423  * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
01424  * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
01425  * last LIN break character. LBKDIF is cleared by writing a 1 to it.
01426  *
01427  * Values:
01428  * - 0 - No LIN break character detected.
01429  * - 1 - LIN break character detected.
01430  */
01431 /*@{*/
01432 #define BP_UART_S2_LBKDIF    (7U)          /*!< Bit position for UART_S2_LBKDIF. */
01433 #define BM_UART_S2_LBKDIF    (0x80U)       /*!< Bit mask for UART_S2_LBKDIF. */
01434 #define BS_UART_S2_LBKDIF    (1U)          /*!< Bit field size in bits for UART_S2_LBKDIF. */
01435 
01436 /*! @brief Read current value of the UART_S2_LBKDIF field. */
01437 #define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
01438 
01439 /*! @brief Format value for bitfield UART_S2_LBKDIF. */
01440 #define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF)
01441 
01442 /*! @brief Set the LBKDIF field to a new value. */
01443 #define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
01444 /*@}*/
01445 
01446 /*******************************************************************************
01447  * HW_UART_C3 - UART Control Register 3
01448  ******************************************************************************/
01449 
01450 /*!
01451  * @brief HW_UART_C3 - UART Control Register 3 (RW)
01452  *
01453  * Reset value: 0x00U
01454  *
01455  * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
01456  * between transmit and receive packets.
01457  */
01458 typedef union _hw_uart_c3
01459 {
01460     uint8_t U;
01461     struct _hw_uart_c3_bitfields
01462     {
01463         uint8_t PEIE : 1;              /*!< [0] Parity Error Interrupt Enable */
01464         uint8_t FEIE : 1;              /*!< [1] Framing Error Interrupt Enable */
01465         uint8_t NEIE : 1;              /*!< [2] Noise Error Interrupt Enable */
01466         uint8_t ORIE : 1;              /*!< [3] Overrun Error Interrupt Enable */
01467         uint8_t TXINV : 1;             /*!< [4] Transmit Data Inversion. */
01468         uint8_t TXDIR : 1;             /*!< [5] Transmitter Pin Data Direction in
01469                                         * Single-Wire mode */
01470         uint8_t T8 : 1;                /*!< [6] Transmit Bit 8 */
01471         uint8_t R8 : 1;                /*!< [7] Received Bit 8 */
01472     } B;
01473 } hw_uart_c3_t;
01474 
01475 /*!
01476  * @name Constants and macros for entire UART_C3 register
01477  */
01478 /*@{*/
01479 #define HW_UART_C3_ADDR(x)       ((x) + 0x6U)
01480 
01481 #define HW_UART_C3(x)            (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
01482 #define HW_UART_C3_RD(x)         (HW_UART_C3(x).U)
01483 #define HW_UART_C3_WR(x, v)      (HW_UART_C3(x).U = (v))
01484 #define HW_UART_C3_SET(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) |  (v)))
01485 #define HW_UART_C3_CLR(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
01486 #define HW_UART_C3_TOG(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^  (v)))
01487 /*@}*/
01488 
01489 /*
01490  * Constants & macros for individual UART_C3 bitfields
01491  */
01492 
01493 /*!
01494  * @name Register UART_C3, field PEIE[0] (RW)
01495  *
01496  * Enables the parity error flag, S1[PF], to generate interrupt requests.
01497  *
01498  * Values:
01499  * - 0 - PF interrupt requests are disabled.
01500  * - 1 - PF interrupt requests are enabled.
01501  */
01502 /*@{*/
01503 #define BP_UART_C3_PEIE      (0U)          /*!< Bit position for UART_C3_PEIE. */
01504 #define BM_UART_C3_PEIE      (0x01U)       /*!< Bit mask for UART_C3_PEIE. */
01505 #define BS_UART_C3_PEIE      (1U)          /*!< Bit field size in bits for UART_C3_PEIE. */
01506 
01507 /*! @brief Read current value of the UART_C3_PEIE field. */
01508 #define BR_UART_C3_PEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
01509 
01510 /*! @brief Format value for bitfield UART_C3_PEIE. */
01511 #define BF_UART_C3_PEIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE)
01512 
01513 /*! @brief Set the PEIE field to a new value. */
01514 #define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
01515 /*@}*/
01516 
01517 /*!
01518  * @name Register UART_C3, field FEIE[1] (RW)
01519  *
01520  * Enables the framing error flag, S1[FE], to generate interrupt requests.
01521  *
01522  * Values:
01523  * - 0 - FE interrupt requests are disabled.
01524  * - 1 - FE interrupt requests are enabled.
01525  */
01526 /*@{*/
01527 #define BP_UART_C3_FEIE      (1U)          /*!< Bit position for UART_C3_FEIE. */
01528 #define BM_UART_C3_FEIE      (0x02U)       /*!< Bit mask for UART_C3_FEIE. */
01529 #define BS_UART_C3_FEIE      (1U)          /*!< Bit field size in bits for UART_C3_FEIE. */
01530 
01531 /*! @brief Read current value of the UART_C3_FEIE field. */
01532 #define BR_UART_C3_FEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
01533 
01534 /*! @brief Format value for bitfield UART_C3_FEIE. */
01535 #define BF_UART_C3_FEIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE)
01536 
01537 /*! @brief Set the FEIE field to a new value. */
01538 #define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
01539 /*@}*/
01540 
01541 /*!
01542  * @name Register UART_C3, field NEIE[2] (RW)
01543  *
01544  * Enables the noise flag, S1[NF], to generate interrupt requests.
01545  *
01546  * Values:
01547  * - 0 - NF interrupt requests are disabled.
01548  * - 1 - NF interrupt requests are enabled.
01549  */
01550 /*@{*/
01551 #define BP_UART_C3_NEIE      (2U)          /*!< Bit position for UART_C3_NEIE. */
01552 #define BM_UART_C3_NEIE      (0x04U)       /*!< Bit mask for UART_C3_NEIE. */
01553 #define BS_UART_C3_NEIE      (1U)          /*!< Bit field size in bits for UART_C3_NEIE. */
01554 
01555 /*! @brief Read current value of the UART_C3_NEIE field. */
01556 #define BR_UART_C3_NEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
01557 
01558 /*! @brief Format value for bitfield UART_C3_NEIE. */
01559 #define BF_UART_C3_NEIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE)
01560 
01561 /*! @brief Set the NEIE field to a new value. */
01562 #define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
01563 /*@}*/
01564 
01565 /*!
01566  * @name Register UART_C3, field ORIE[3] (RW)
01567  *
01568  * Enables the overrun error flag, S1[OR], to generate interrupt requests.
01569  *
01570  * Values:
01571  * - 0 - OR interrupts are disabled.
01572  * - 1 - OR interrupt requests are enabled.
01573  */
01574 /*@{*/
01575 #define BP_UART_C3_ORIE      (3U)          /*!< Bit position for UART_C3_ORIE. */
01576 #define BM_UART_C3_ORIE      (0x08U)       /*!< Bit mask for UART_C3_ORIE. */
01577 #define BS_UART_C3_ORIE      (1U)          /*!< Bit field size in bits for UART_C3_ORIE. */
01578 
01579 /*! @brief Read current value of the UART_C3_ORIE field. */
01580 #define BR_UART_C3_ORIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
01581 
01582 /*! @brief Format value for bitfield UART_C3_ORIE. */
01583 #define BF_UART_C3_ORIE(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE)
01584 
01585 /*! @brief Set the ORIE field to a new value. */
01586 #define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
01587 /*@}*/
01588 
01589 /*!
01590  * @name Register UART_C3, field TXINV[4] (RW)
01591  *
01592  * Setting this field reverses the polarity of the transmitted data output. In
01593  * NRZ format, a one is represented by a mark and a zero is represented by a space
01594  * for normal polarity, and the opposite for inverted polarity. In IrDA format,
01595  * a zero is represented by short high pulse in the middle of a bit time
01596  * remaining idle low for a one for normal polarity, and a zero is represented by short
01597  * low pulse in the middle of a bit time remaining idle high for a one for
01598  * inverted polarity. This field is automatically set when C7816[INIT] and
01599  * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
01600  * Setting TXINV inverts all transmitted values, including idle, break, start, and
01601  * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
01602  * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
01603  * the transmitted data bits and parity bit are inverted.
01604  *
01605  * Values:
01606  * - 0 - Transmit data is not inverted.
01607  * - 1 - Transmit data is inverted.
01608  */
01609 /*@{*/
01610 #define BP_UART_C3_TXINV     (4U)          /*!< Bit position for UART_C3_TXINV. */
01611 #define BM_UART_C3_TXINV     (0x10U)       /*!< Bit mask for UART_C3_TXINV. */
01612 #define BS_UART_C3_TXINV     (1U)          /*!< Bit field size in bits for UART_C3_TXINV. */
01613 
01614 /*! @brief Read current value of the UART_C3_TXINV field. */
01615 #define BR_UART_C3_TXINV(x)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
01616 
01617 /*! @brief Format value for bitfield UART_C3_TXINV. */
01618 #define BF_UART_C3_TXINV(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV)
01619 
01620 /*! @brief Set the TXINV field to a new value. */
01621 #define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
01622 /*@}*/
01623 
01624 /*!
01625  * @name Register UART_C3, field TXDIR[5] (RW)
01626  *
01627  * Determines whether the TXD pin is used as an input or output in the
01628  * single-wire mode of operation. This field is relevant only to the single wire mode.
01629  * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
01630  * automatically cleared after the requested block is transmitted. This condition is
01631  * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
01632  * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
01633  * being transmitted, the hardware automatically overrides this field as needed. In
01634  * this situation, TXDIR does not reflect the temporary state associated with
01635  * the NACK.
01636  *
01637  * Values:
01638  * - 0 - TXD pin is an input in single wire mode.
01639  * - 1 - TXD pin is an output in single wire mode.
01640  */
01641 /*@{*/
01642 #define BP_UART_C3_TXDIR     (5U)          /*!< Bit position for UART_C3_TXDIR. */
01643 #define BM_UART_C3_TXDIR     (0x20U)       /*!< Bit mask for UART_C3_TXDIR. */
01644 #define BS_UART_C3_TXDIR     (1U)          /*!< Bit field size in bits for UART_C3_TXDIR. */
01645 
01646 /*! @brief Read current value of the UART_C3_TXDIR field. */
01647 #define BR_UART_C3_TXDIR(x)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
01648 
01649 /*! @brief Format value for bitfield UART_C3_TXDIR. */
01650 #define BF_UART_C3_TXDIR(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR)
01651 
01652 /*! @brief Set the TXDIR field to a new value. */
01653 #define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
01654 /*@}*/
01655 
01656 /*!
01657  * @name Register UART_C3, field T8[6] (RW)
01658  *
01659  * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
01660  * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
01661  * same as in the previous transmission, T8 does not have to be rewritten. The same
01662  * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
01663  * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
01664  * the remaining data.
01665  */
01666 /*@{*/
01667 #define BP_UART_C3_T8        (6U)          /*!< Bit position for UART_C3_T8. */
01668 #define BM_UART_C3_T8        (0x40U)       /*!< Bit mask for UART_C3_T8. */
01669 #define BS_UART_C3_T8        (1U)          /*!< Bit field size in bits for UART_C3_T8. */
01670 
01671 /*! @brief Read current value of the UART_C3_T8 field. */
01672 #define BR_UART_C3_T8(x)     (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
01673 
01674 /*! @brief Format value for bitfield UART_C3_T8. */
01675 #define BF_UART_C3_T8(v)     ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8)
01676 
01677 /*! @brief Set the T8 field to a new value. */
01678 #define BW_UART_C3_T8(x, v)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
01679 /*@}*/
01680 
01681 /*!
01682  * @name Register UART_C3, field R8[7] (RO)
01683  *
01684  * R8 is the ninth data bit received when the UART is configured for 9-bit data
01685  * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
01686  * current data value in the UARTx_D register. To read the 9th bit, read the
01687  * value of UARTx_C3[R8], then read the UARTx_D register.
01688  */
01689 /*@{*/
01690 #define BP_UART_C3_R8        (7U)          /*!< Bit position for UART_C3_R8. */
01691 #define BM_UART_C3_R8        (0x80U)       /*!< Bit mask for UART_C3_R8. */
01692 #define BS_UART_C3_R8        (1U)          /*!< Bit field size in bits for UART_C3_R8. */
01693 
01694 /*! @brief Read current value of the UART_C3_R8 field. */
01695 #define BR_UART_C3_R8(x)     (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
01696 /*@}*/
01697 
01698 /*******************************************************************************
01699  * HW_UART_D - UART Data Register
01700  ******************************************************************************/
01701 
01702 /*!
01703  * @brief HW_UART_D - UART Data Register (RW)
01704  *
01705  * Reset value: 0x00U
01706  *
01707  * This register is actually two separate registers. Reads return the contents
01708  * of the read-only receive data register and writes go to the write-only transmit
01709  * data register. In 8-bit or 9-bit data format, only UART data register (D)
01710  * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
01711  * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
01712  * register, only if the ninth bit of data needs to be captured. Similarly, the
01713  * ED register needs to be read, prior to the D register, only if the additional
01714  * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
01715  * bit cleared) if the parity is enabled, you get seven data bits and one parity
01716  * bit. That one parity bit is loaded into the D register. So, for the data bits,
01717  * mask off the parity bit from the value you read out of this register. When
01718  * transmitting in 9-bit data format and using 8-bit write instructions, write first
01719  * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
01720  * C3[T8] stores the data in a temporary register. If D register is written first,
01721  * and then the new data on data bus is stored in D, the temporary value written by
01722  * the last write to C3[T8] gets stored in the C3[T8] register.
01723  */
01724 typedef union _hw_uart_d
01725 {
01726     uint8_t U;
01727     struct _hw_uart_d_bitfields
01728     {
01729         uint8_t RT : 8;                /*!< [7:0]  */
01730     } B;
01731 } hw_uart_d_t;
01732 
01733 /*!
01734  * @name Constants and macros for entire UART_D register
01735  */
01736 /*@{*/
01737 #define HW_UART_D_ADDR(x)        ((x) + 0x7U)
01738 
01739 #define HW_UART_D(x)             (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
01740 #define HW_UART_D_RD(x)          (HW_UART_D(x).U)
01741 #define HW_UART_D_WR(x, v)       (HW_UART_D(x).U = (v))
01742 #define HW_UART_D_SET(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) |  (v)))
01743 #define HW_UART_D_CLR(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
01744 #define HW_UART_D_TOG(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) ^  (v)))
01745 /*@}*/
01746 
01747 /*
01748  * Constants & macros for individual UART_D bitfields
01749  */
01750 
01751 /*!
01752  * @name Register UART_D, field RT[7:0] (RW)
01753  *
01754  * Reads return the contents of the read-only receive data register and writes
01755  * go to the write-only transmit data register.
01756  */
01757 /*@{*/
01758 #define BP_UART_D_RT         (0U)          /*!< Bit position for UART_D_RT. */
01759 #define BM_UART_D_RT         (0xFFU)       /*!< Bit mask for UART_D_RT. */
01760 #define BS_UART_D_RT         (8U)          /*!< Bit field size in bits for UART_D_RT. */
01761 
01762 /*! @brief Read current value of the UART_D_RT field. */
01763 #define BR_UART_D_RT(x)      (HW_UART_D(x).U)
01764 
01765 /*! @brief Format value for bitfield UART_D_RT. */
01766 #define BF_UART_D_RT(v)      ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT)
01767 
01768 /*! @brief Set the RT field to a new value. */
01769 #define BW_UART_D_RT(x, v)   (HW_UART_D_WR(x, v))
01770 /*@}*/
01771 
01772 /*******************************************************************************
01773  * HW_UART_MA1 - UART Match Address Registers 1
01774  ******************************************************************************/
01775 
01776 /*!
01777  * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
01778  *
01779  * Reset value: 0x00U
01780  *
01781  * The MA1 and MA2 registers are compared to input data addresses when the most
01782  * significant bit is set and the associated C4[MAEN] field is set. If a match
01783  * occurs, the following data is transferred to the data register. If a match
01784  * fails, the following data is discarded. These registers can be read and written at
01785  * anytime.
01786  */
01787 typedef union _hw_uart_ma1
01788 {
01789     uint8_t U;
01790     struct _hw_uart_ma1_bitfields
01791     {
01792         uint8_t MA : 8;                /*!< [7:0] Match Address */
01793     } B;
01794 } hw_uart_ma1_t;
01795 
01796 /*!
01797  * @name Constants and macros for entire UART_MA1 register
01798  */
01799 /*@{*/
01800 #define HW_UART_MA1_ADDR(x)      ((x) + 0x8U)
01801 
01802 #define HW_UART_MA1(x)           (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
01803 #define HW_UART_MA1_RD(x)        (HW_UART_MA1(x).U)
01804 #define HW_UART_MA1_WR(x, v)     (HW_UART_MA1(x).U = (v))
01805 #define HW_UART_MA1_SET(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) |  (v)))
01806 #define HW_UART_MA1_CLR(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
01807 #define HW_UART_MA1_TOG(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^  (v)))
01808 /*@}*/
01809 
01810 /*
01811  * Constants & macros for individual UART_MA1 bitfields
01812  */
01813 
01814 /*!
01815  * @name Register UART_MA1, field MA[7:0] (RW)
01816  */
01817 /*@{*/
01818 #define BP_UART_MA1_MA       (0U)          /*!< Bit position for UART_MA1_MA. */
01819 #define BM_UART_MA1_MA       (0xFFU)       /*!< Bit mask for UART_MA1_MA. */
01820 #define BS_UART_MA1_MA       (8U)          /*!< Bit field size in bits for UART_MA1_MA. */
01821 
01822 /*! @brief Read current value of the UART_MA1_MA field. */
01823 #define BR_UART_MA1_MA(x)    (HW_UART_MA1(x).U)
01824 
01825 /*! @brief Format value for bitfield UART_MA1_MA. */
01826 #define BF_UART_MA1_MA(v)    ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA)
01827 
01828 /*! @brief Set the MA field to a new value. */
01829 #define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
01830 /*@}*/
01831 
01832 /*******************************************************************************
01833  * HW_UART_MA2 - UART Match Address Registers 2
01834  ******************************************************************************/
01835 
01836 /*!
01837  * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
01838  *
01839  * Reset value: 0x00U
01840  *
01841  * These registers can be read and written at anytime. The MA1 and MA2 registers
01842  * are compared to input data addresses when the most significant bit is set and
01843  * the associated C4[MAEN] field is set. If a match occurs, the following data
01844  * is transferred to the data register. If a match fails, the following data is
01845  * discarded.
01846  */
01847 typedef union _hw_uart_ma2
01848 {
01849     uint8_t U;
01850     struct _hw_uart_ma2_bitfields
01851     {
01852         uint8_t MA : 8;                /*!< [7:0] Match Address */
01853     } B;
01854 } hw_uart_ma2_t;
01855 
01856 /*!
01857  * @name Constants and macros for entire UART_MA2 register
01858  */
01859 /*@{*/
01860 #define HW_UART_MA2_ADDR(x)      ((x) + 0x9U)
01861 
01862 #define HW_UART_MA2(x)           (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
01863 #define HW_UART_MA2_RD(x)        (HW_UART_MA2(x).U)
01864 #define HW_UART_MA2_WR(x, v)     (HW_UART_MA2(x).U = (v))
01865 #define HW_UART_MA2_SET(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) |  (v)))
01866 #define HW_UART_MA2_CLR(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
01867 #define HW_UART_MA2_TOG(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^  (v)))
01868 /*@}*/
01869 
01870 /*
01871  * Constants & macros for individual UART_MA2 bitfields
01872  */
01873 
01874 /*!
01875  * @name Register UART_MA2, field MA[7:0] (RW)
01876  */
01877 /*@{*/
01878 #define BP_UART_MA2_MA       (0U)          /*!< Bit position for UART_MA2_MA. */
01879 #define BM_UART_MA2_MA       (0xFFU)       /*!< Bit mask for UART_MA2_MA. */
01880 #define BS_UART_MA2_MA       (8U)          /*!< Bit field size in bits for UART_MA2_MA. */
01881 
01882 /*! @brief Read current value of the UART_MA2_MA field. */
01883 #define BR_UART_MA2_MA(x)    (HW_UART_MA2(x).U)
01884 
01885 /*! @brief Format value for bitfield UART_MA2_MA. */
01886 #define BF_UART_MA2_MA(v)    ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA)
01887 
01888 /*! @brief Set the MA field to a new value. */
01889 #define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
01890 /*@}*/
01891 
01892 /*******************************************************************************
01893  * HW_UART_C4 - UART Control Register 4
01894  ******************************************************************************/
01895 
01896 /*!
01897  * @brief HW_UART_C4 - UART Control Register 4 (RW)
01898  *
01899  * Reset value: 0x00U
01900  */
01901 typedef union _hw_uart_c4
01902 {
01903     uint8_t U;
01904     struct _hw_uart_c4_bitfields
01905     {
01906         uint8_t BRFA : 5;              /*!< [4:0] Baud Rate Fine Adjust */
01907         uint8_t M10 : 1;               /*!< [5] 10-bit Mode select */
01908         uint8_t MAEN2 : 1;             /*!< [6] Match Address Mode Enable 2 */
01909         uint8_t MAEN1 : 1;             /*!< [7] Match Address Mode Enable 1 */
01910     } B;
01911 } hw_uart_c4_t;
01912 
01913 /*!
01914  * @name Constants and macros for entire UART_C4 register
01915  */
01916 /*@{*/
01917 #define HW_UART_C4_ADDR(x)       ((x) + 0xAU)
01918 
01919 #define HW_UART_C4(x)            (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
01920 #define HW_UART_C4_RD(x)         (HW_UART_C4(x).U)
01921 #define HW_UART_C4_WR(x, v)      (HW_UART_C4(x).U = (v))
01922 #define HW_UART_C4_SET(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) |  (v)))
01923 #define HW_UART_C4_CLR(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
01924 #define HW_UART_C4_TOG(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^  (v)))
01925 /*@}*/
01926 
01927 /*
01928  * Constants & macros for individual UART_C4 bitfields
01929  */
01930 
01931 /*!
01932  * @name Register UART_C4, field BRFA[4:0] (RW)
01933  *
01934  * This bit field is used to add more timing resolution to the average baud
01935  * frequency, in increments of 1/32. See Baud rate generation for more information.
01936  */
01937 /*@{*/
01938 #define BP_UART_C4_BRFA      (0U)          /*!< Bit position for UART_C4_BRFA. */
01939 #define BM_UART_C4_BRFA      (0x1FU)       /*!< Bit mask for UART_C4_BRFA. */
01940 #define BS_UART_C4_BRFA      (5U)          /*!< Bit field size in bits for UART_C4_BRFA. */
01941 
01942 /*! @brief Read current value of the UART_C4_BRFA field. */
01943 #define BR_UART_C4_BRFA(x)   (HW_UART_C4(x).B.BRFA)
01944 
01945 /*! @brief Format value for bitfield UART_C4_BRFA. */
01946 #define BF_UART_C4_BRFA(v)   ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA)
01947 
01948 /*! @brief Set the BRFA field to a new value. */
01949 #define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
01950 /*@}*/
01951 
01952 /*!
01953  * @name Register UART_C4, field M10[5] (RW)
01954  *
01955  * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
01956  * This tenth bit is generated and interpreted as a parity bit. The M10 field
01957  * does not affect the LIN send or detect break behavior. If M10 is set, then both
01958  * C1[M] and C1[PE] must also be set. This field must be cleared when
01959  * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
01960  *
01961  * Values:
01962  * - 0 - The parity bit is the ninth bit in the serial transmission.
01963  * - 1 - The parity bit is the tenth bit in the serial transmission.
01964  */
01965 /*@{*/
01966 #define BP_UART_C4_M10       (5U)          /*!< Bit position for UART_C4_M10. */
01967 #define BM_UART_C4_M10       (0x20U)       /*!< Bit mask for UART_C4_M10. */
01968 #define BS_UART_C4_M10       (1U)          /*!< Bit field size in bits for UART_C4_M10. */
01969 
01970 /*! @brief Read current value of the UART_C4_M10 field. */
01971 #define BR_UART_C4_M10(x)    (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
01972 
01973 /*! @brief Format value for bitfield UART_C4_M10. */
01974 #define BF_UART_C4_M10(v)    ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10)
01975 
01976 /*! @brief Set the M10 field to a new value. */
01977 #define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
01978 /*@}*/
01979 
01980 /*!
01981  * @name Register UART_C4, field MAEN2[6] (RW)
01982  *
01983  * See Match address operation for more information.
01984  *
01985  * Values:
01986  * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
01987  * - 1 - All data received with the most significant bit cleared, is discarded.
01988  *     All data received with the most significant bit set, is compared with
01989  *     contents of MA2 register. If no match occurs, the data is discarded. If a
01990  *     match occurs, data is transferred to the data buffer. This field must be
01991  *     cleared when C7816[ISO7816E] is set/enabled.
01992  */
01993 /*@{*/
01994 #define BP_UART_C4_MAEN2     (6U)          /*!< Bit position for UART_C4_MAEN2. */
01995 #define BM_UART_C4_MAEN2     (0x40U)       /*!< Bit mask for UART_C4_MAEN2. */
01996 #define BS_UART_C4_MAEN2     (1U)          /*!< Bit field size in bits for UART_C4_MAEN2. */
01997 
01998 /*! @brief Read current value of the UART_C4_MAEN2 field. */
01999 #define BR_UART_C4_MAEN2(x)  (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
02000 
02001 /*! @brief Format value for bitfield UART_C4_MAEN2. */
02002 #define BF_UART_C4_MAEN2(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2)
02003 
02004 /*! @brief Set the MAEN2 field to a new value. */
02005 #define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
02006 /*@}*/
02007 
02008 /*!
02009  * @name Register UART_C4, field MAEN1[7] (RW)
02010  *
02011  * See Match address operation for more information.
02012  *
02013  * Values:
02014  * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
02015  * - 1 - All data received with the most significant bit cleared, is discarded.
02016  *     All data received with the most significant bit set, is compared with
02017  *     contents of MA1 register. If no match occurs, the data is discarded. If match
02018  *     occurs, data is transferred to the data buffer. This field must be cleared
02019  *     when C7816[ISO7816E] is set/enabled.
02020  */
02021 /*@{*/
02022 #define BP_UART_C4_MAEN1     (7U)          /*!< Bit position for UART_C4_MAEN1. */
02023 #define BM_UART_C4_MAEN1     (0x80U)       /*!< Bit mask for UART_C4_MAEN1. */
02024 #define BS_UART_C4_MAEN1     (1U)          /*!< Bit field size in bits for UART_C4_MAEN1. */
02025 
02026 /*! @brief Read current value of the UART_C4_MAEN1 field. */
02027 #define BR_UART_C4_MAEN1(x)  (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
02028 
02029 /*! @brief Format value for bitfield UART_C4_MAEN1. */
02030 #define BF_UART_C4_MAEN1(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1)
02031 
02032 /*! @brief Set the MAEN1 field to a new value. */
02033 #define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
02034 /*@}*/
02035 
02036 /*******************************************************************************
02037  * HW_UART_C5 - UART Control Register 5
02038  ******************************************************************************/
02039 
02040 /*!
02041  * @brief HW_UART_C5 - UART Control Register 5 (RW)
02042  *
02043  * Reset value: 0x00U
02044  */
02045 typedef union _hw_uart_c5
02046 {
02047     uint8_t U;
02048     struct _hw_uart_c5_bitfields
02049     {
02050         uint8_t RESERVED0 : 3;         /*!< [2:0]  */
02051         uint8_t LBKDDMAS : 1;          /*!< [3] LIN Break Detect DMA Select Bit */
02052         uint8_t ILDMAS : 1;            /*!< [4] Idle Line DMA Select */
02053         uint8_t RDMAS : 1;             /*!< [5] Receiver Full DMA Select */
02054         uint8_t TCDMAS : 1;            /*!< [6] Transmission Complete DMA Select */
02055         uint8_t TDMAS : 1;             /*!< [7] Transmitter DMA Select */
02056     } B;
02057 } hw_uart_c5_t;
02058 
02059 /*!
02060  * @name Constants and macros for entire UART_C5 register
02061  */
02062 /*@{*/
02063 #define HW_UART_C5_ADDR(x)       ((x) + 0xBU)
02064 
02065 #define HW_UART_C5(x)            (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
02066 #define HW_UART_C5_RD(x)         (HW_UART_C5(x).U)
02067 #define HW_UART_C5_WR(x, v)      (HW_UART_C5(x).U = (v))
02068 #define HW_UART_C5_SET(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) |  (v)))
02069 #define HW_UART_C5_CLR(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
02070 #define HW_UART_C5_TOG(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^  (v)))
02071 /*@}*/
02072 
02073 /*
02074  * Constants & macros for individual UART_C5 bitfields
02075  */
02076 
02077 /*!
02078  * @name Register UART_C5, field LBKDDMAS[3] (RW)
02079  *
02080  * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
02081  * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
02082  * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
02083  * of the state of LBKDDMAS.
02084  *
02085  * Values:
02086  * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
02087  *     asserted to request an interrupt service.
02088  * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
02089  *     asserted to request a DMA transfer.
02090  */
02091 /*@{*/
02092 #define BP_UART_C5_LBKDDMAS  (3U)          /*!< Bit position for UART_C5_LBKDDMAS. */
02093 #define BM_UART_C5_LBKDDMAS  (0x08U)       /*!< Bit mask for UART_C5_LBKDDMAS. */
02094 #define BS_UART_C5_LBKDDMAS  (1U)          /*!< Bit field size in bits for UART_C5_LBKDDMAS. */
02095 
02096 /*! @brief Read current value of the UART_C5_LBKDDMAS field. */
02097 #define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
02098 
02099 /*! @brief Format value for bitfield UART_C5_LBKDDMAS. */
02100 #define BF_UART_C5_LBKDDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_LBKDDMAS) & BM_UART_C5_LBKDDMAS)
02101 
02102 /*! @brief Set the LBKDDMAS field to a new value. */
02103 #define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
02104 /*@}*/
02105 
02106 /*!
02107  * @name Register UART_C5, field ILDMAS[4] (RW)
02108  *
02109  * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
02110  * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
02111  * DMA and IDLE interrupt request signals are not asserted, regardless of the state
02112  * of ILDMAS.
02113  *
02114  * Values:
02115  * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
02116  *     asserted to request an interrupt service.
02117  * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
02118  *     asserted to request a DMA transfer.
02119  */
02120 /*@{*/
02121 #define BP_UART_C5_ILDMAS    (4U)          /*!< Bit position for UART_C5_ILDMAS. */
02122 #define BM_UART_C5_ILDMAS    (0x10U)       /*!< Bit mask for UART_C5_ILDMAS. */
02123 #define BS_UART_C5_ILDMAS    (1U)          /*!< Bit field size in bits for UART_C5_ILDMAS. */
02124 
02125 /*! @brief Read current value of the UART_C5_ILDMAS field. */
02126 #define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
02127 
02128 /*! @brief Format value for bitfield UART_C5_ILDMAS. */
02129 #define BF_UART_C5_ILDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_ILDMAS) & BM_UART_C5_ILDMAS)
02130 
02131 /*! @brief Set the ILDMAS field to a new value. */
02132 #define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
02133 /*@}*/
02134 
02135 /*!
02136  * @name Register UART_C5, field RDMAS[5] (RW)
02137  *
02138  * Configures the receiver data register full flag, S1[RDRF], to generate
02139  * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
02140  * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
02141  * regardless of the state of RDMAS.
02142  *
02143  * Values:
02144  * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
02145  *     asserted to request an interrupt service.
02146  * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
02147  *     asserted to request a DMA transfer.
02148  */
02149 /*@{*/
02150 #define BP_UART_C5_RDMAS     (5U)          /*!< Bit position for UART_C5_RDMAS. */
02151 #define BM_UART_C5_RDMAS     (0x20U)       /*!< Bit mask for UART_C5_RDMAS. */
02152 #define BS_UART_C5_RDMAS     (1U)          /*!< Bit field size in bits for UART_C5_RDMAS. */
02153 
02154 /*! @brief Read current value of the UART_C5_RDMAS field. */
02155 #define BR_UART_C5_RDMAS(x)  (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
02156 
02157 /*! @brief Format value for bitfield UART_C5_RDMAS. */
02158 #define BF_UART_C5_RDMAS(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS)
02159 
02160 /*! @brief Set the RDMAS field to a new value. */
02161 #define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
02162 /*@}*/
02163 
02164 /*!
02165  * @name Register UART_C5, field TCDMAS[6] (RW)
02166  *
02167  * Configures the transmission complete flag, S1[TC], to generate interrupt or
02168  * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
02169  * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
02170  * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
02171  * must be cleared, and D must not be written unless a DMA request is being serviced.
02172  *
02173  * Values:
02174  * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
02175  *     signal is asserted to request an interrupt service.
02176  * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
02177  *     signal is asserted to request a DMA transfer.
02178  */
02179 /*@{*/
02180 #define BP_UART_C5_TCDMAS    (6U)          /*!< Bit position for UART_C5_TCDMAS. */
02181 #define BM_UART_C5_TCDMAS    (0x40U)       /*!< Bit mask for UART_C5_TCDMAS. */
02182 #define BS_UART_C5_TCDMAS    (1U)          /*!< Bit field size in bits for UART_C5_TCDMAS. */
02183 
02184 /*! @brief Read current value of the UART_C5_TCDMAS field. */
02185 #define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
02186 
02187 /*! @brief Format value for bitfield UART_C5_TCDMAS. */
02188 #define BF_UART_C5_TCDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TCDMAS) & BM_UART_C5_TCDMAS)
02189 
02190 /*! @brief Set the TCDMAS field to a new value. */
02191 #define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
02192 /*@}*/
02193 
02194 /*!
02195  * @name Register UART_C5, field TDMAS[7] (RW)
02196  *
02197  * Configures the transmit data register empty flag, S1[TDRE], to generate
02198  * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
02199  * TDRE interrupt request signals are not asserted when the TDRE flag is set,
02200  * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
02201  * must be cleared, and D must not be written unless a DMA request is being
02202  * serviced.
02203  *
02204  * Values:
02205  * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
02206  *     request signal is asserted to request interrupt service.
02207  * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
02208  *     signal is asserted to request a DMA transfer.
02209  */
02210 /*@{*/
02211 #define BP_UART_C5_TDMAS     (7U)          /*!< Bit position for UART_C5_TDMAS. */
02212 #define BM_UART_C5_TDMAS     (0x80U)       /*!< Bit mask for UART_C5_TDMAS. */
02213 #define BS_UART_C5_TDMAS     (1U)          /*!< Bit field size in bits for UART_C5_TDMAS. */
02214 
02215 /*! @brief Read current value of the UART_C5_TDMAS field. */
02216 #define BR_UART_C5_TDMAS(x)  (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
02217 
02218 /*! @brief Format value for bitfield UART_C5_TDMAS. */
02219 #define BF_UART_C5_TDMAS(v)  ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS)
02220 
02221 /*! @brief Set the TDMAS field to a new value. */
02222 #define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
02223 /*@}*/
02224 
02225 /*******************************************************************************
02226  * HW_UART_ED - UART Extended Data Register
02227  ******************************************************************************/
02228 
02229 /*!
02230  * @brief HW_UART_ED - UART Extended Data Register (RO)
02231  *
02232  * Reset value: 0x00U
02233  *
02234  * This register contains additional information flags that are stored with a
02235  * received dataword. This register may be read at any time but contains valid data
02236  * only if there is a dataword in the receive FIFO. The data contained in this
02237  * register represents additional information regarding the conditions on which a
02238  * dataword was received. The importance of this data varies with the
02239  * application, and in some cases maybe completely optional. These fields automatically
02240  * update to reflect the conditions of the next dataword whenever D is read. If
02241  * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
02242  * empty, the NOISY and PARITYE fields will be zero.
02243  */
02244 typedef union _hw_uart_ed
02245 {
02246     uint8_t U;
02247     struct _hw_uart_ed_bitfields
02248     {
02249         uint8_t RESERVED0 : 6;         /*!< [5:0]  */
02250         uint8_t PARITYE : 1;           /*!< [6]  */
02251         uint8_t NOISY : 1;             /*!< [7]  */
02252     } B;
02253 } hw_uart_ed_t;
02254 
02255 /*!
02256  * @name Constants and macros for entire UART_ED register
02257  */
02258 /*@{*/
02259 #define HW_UART_ED_ADDR(x)       ((x) + 0xCU)
02260 
02261 #define HW_UART_ED(x)            (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
02262 #define HW_UART_ED_RD(x)         (HW_UART_ED(x).U)
02263 /*@}*/
02264 
02265 /*
02266  * Constants & macros for individual UART_ED bitfields
02267  */
02268 
02269 /*!
02270  * @name Register UART_ED, field PARITYE[6] (RO)
02271  *
02272  * The current received dataword contained in D and C3[R8] was received with a
02273  * parity error.
02274  *
02275  * Values:
02276  * - 0 - The dataword was received without a parity error.
02277  * - 1 - The dataword was received with a parity error.
02278  */
02279 /*@{*/
02280 #define BP_UART_ED_PARITYE   (6U)          /*!< Bit position for UART_ED_PARITYE. */
02281 #define BM_UART_ED_PARITYE   (0x40U)       /*!< Bit mask for UART_ED_PARITYE. */
02282 #define BS_UART_ED_PARITYE   (1U)          /*!< Bit field size in bits for UART_ED_PARITYE. */
02283 
02284 /*! @brief Read current value of the UART_ED_PARITYE field. */
02285 #define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
02286 /*@}*/
02287 
02288 /*!
02289  * @name Register UART_ED, field NOISY[7] (RO)
02290  *
02291  * The current received dataword contained in D and C3[R8] was received with
02292  * noise.
02293  *
02294  * Values:
02295  * - 0 - The dataword was received without noise.
02296  * - 1 - The data was received with noise.
02297  */
02298 /*@{*/
02299 #define BP_UART_ED_NOISY     (7U)          /*!< Bit position for UART_ED_NOISY. */
02300 #define BM_UART_ED_NOISY     (0x80U)       /*!< Bit mask for UART_ED_NOISY. */
02301 #define BS_UART_ED_NOISY     (1U)          /*!< Bit field size in bits for UART_ED_NOISY. */
02302 
02303 /*! @brief Read current value of the UART_ED_NOISY field. */
02304 #define BR_UART_ED_NOISY(x)  (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
02305 /*@}*/
02306 
02307 /*******************************************************************************
02308  * HW_UART_MODEM - UART Modem Register
02309  ******************************************************************************/
02310 
02311 /*!
02312  * @brief HW_UART_MODEM - UART Modem Register (RW)
02313  *
02314  * Reset value: 0x00U
02315  *
02316  * The MODEM register controls options for setting the modem configuration.
02317  * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
02318  * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
02319  * ISO-7816 protocol does not use the RTS and CTS signals.
02320  */
02321 typedef union _hw_uart_modem
02322 {
02323     uint8_t U;
02324     struct _hw_uart_modem_bitfields
02325     {
02326         uint8_t TXCTSE : 1;            /*!< [0] Transmitter clear-to-send enable */
02327         uint8_t TXRTSE : 1;            /*!< [1] Transmitter request-to-send enable */
02328         uint8_t TXRTSPOL : 1;          /*!< [2] Transmitter request-to-send polarity */
02329         uint8_t RXRTSE : 1;            /*!< [3] Receiver request-to-send enable */
02330         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
02331     } B;
02332 } hw_uart_modem_t;
02333 
02334 /*!
02335  * @name Constants and macros for entire UART_MODEM register
02336  */
02337 /*@{*/
02338 #define HW_UART_MODEM_ADDR(x)    ((x) + 0xDU)
02339 
02340 #define HW_UART_MODEM(x)         (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
02341 #define HW_UART_MODEM_RD(x)      (HW_UART_MODEM(x).U)
02342 #define HW_UART_MODEM_WR(x, v)   (HW_UART_MODEM(x).U = (v))
02343 #define HW_UART_MODEM_SET(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) |  (v)))
02344 #define HW_UART_MODEM_CLR(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
02345 #define HW_UART_MODEM_TOG(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^  (v)))
02346 /*@}*/
02347 
02348 /*
02349  * Constants & macros for individual UART_MODEM bitfields
02350  */
02351 
02352 /*!
02353  * @name Register UART_MODEM, field TXCTSE[0] (RW)
02354  *
02355  * TXCTSE controls the operation of the transmitter. TXCTSE can be set
02356  * independently from the state of TXRTSE and RXRTSE.
02357  *
02358  * Values:
02359  * - 0 - CTS has no effect on the transmitter.
02360  * - 1 - Enables clear-to-send operation. The transmitter checks the state of
02361  *     CTS each time it is ready to send a character. If CTS is asserted, the
02362  *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
02363  *     state and transmission is delayed until CTS is asserted. Changes in CTS as a
02364  *     character is being sent do not affect its transmission.
02365  */
02366 /*@{*/
02367 #define BP_UART_MODEM_TXCTSE (0U)          /*!< Bit position for UART_MODEM_TXCTSE. */
02368 #define BM_UART_MODEM_TXCTSE (0x01U)       /*!< Bit mask for UART_MODEM_TXCTSE. */
02369 #define BS_UART_MODEM_TXCTSE (1U)          /*!< Bit field size in bits for UART_MODEM_TXCTSE. */
02370 
02371 /*! @brief Read current value of the UART_MODEM_TXCTSE field. */
02372 #define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
02373 
02374 /*! @brief Format value for bitfield UART_MODEM_TXCTSE. */
02375 #define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE)
02376 
02377 /*! @brief Set the TXCTSE field to a new value. */
02378 #define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
02379 /*@}*/
02380 
02381 /*!
02382  * @name Register UART_MODEM, field TXRTSE[1] (RW)
02383  *
02384  * Controls RTS before and after a transmission.
02385  *
02386  * Values:
02387  * - 0 - The transmitter has no effect on RTS.
02388  * - 1 - When a character is placed into an empty transmitter data buffer , RTS
02389  *     asserts one bit time before the start bit is transmitted. RTS deasserts
02390  *     one bit time after all characters in the transmitter data buffer and shift
02391  *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
02392  */
02393 /*@{*/
02394 #define BP_UART_MODEM_TXRTSE (1U)          /*!< Bit position for UART_MODEM_TXRTSE. */
02395 #define BM_UART_MODEM_TXRTSE (0x02U)       /*!< Bit mask for UART_MODEM_TXRTSE. */
02396 #define BS_UART_MODEM_TXRTSE (1U)          /*!< Bit field size in bits for UART_MODEM_TXRTSE. */
02397 
02398 /*! @brief Read current value of the UART_MODEM_TXRTSE field. */
02399 #define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
02400 
02401 /*! @brief Format value for bitfield UART_MODEM_TXRTSE. */
02402 #define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE)
02403 
02404 /*! @brief Set the TXRTSE field to a new value. */
02405 #define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
02406 /*@}*/
02407 
02408 /*!
02409  * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
02410  *
02411  * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
02412  * polarity of the receiver RTS. RTS will remain negated in the active low state
02413  * unless TXRTSE is set.
02414  *
02415  * Values:
02416  * - 0 - Transmitter RTS is active low.
02417  * - 1 - Transmitter RTS is active high.
02418  */
02419 /*@{*/
02420 #define BP_UART_MODEM_TXRTSPOL (2U)        /*!< Bit position for UART_MODEM_TXRTSPOL. */
02421 #define BM_UART_MODEM_TXRTSPOL (0x04U)     /*!< Bit mask for UART_MODEM_TXRTSPOL. */
02422 #define BS_UART_MODEM_TXRTSPOL (1U)        /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */
02423 
02424 /*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
02425 #define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
02426 
02427 /*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */
02428 #define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL)
02429 
02430 /*! @brief Set the TXRTSPOL field to a new value. */
02431 #define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
02432 /*@}*/
02433 
02434 /*!
02435  * @name Register UART_MODEM, field RXRTSE[3] (RW)
02436  *
02437  * Allows the RTS output to control the CTS input of the transmitting device to
02438  * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
02439  *
02440  * Values:
02441  * - 0 - The receiver has no effect on RTS.
02442  * - 1 - RTS is deasserted if the number of characters in the receiver data
02443  *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
02444  *     when the number of characters in the receiver data register (FIFO) is less
02445  *     than RWFIFO[RXWATER].
02446  */
02447 /*@{*/
02448 #define BP_UART_MODEM_RXRTSE (3U)          /*!< Bit position for UART_MODEM_RXRTSE. */
02449 #define BM_UART_MODEM_RXRTSE (0x08U)       /*!< Bit mask for UART_MODEM_RXRTSE. */
02450 #define BS_UART_MODEM_RXRTSE (1U)          /*!< Bit field size in bits for UART_MODEM_RXRTSE. */
02451 
02452 /*! @brief Read current value of the UART_MODEM_RXRTSE field. */
02453 #define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
02454 
02455 /*! @brief Format value for bitfield UART_MODEM_RXRTSE. */
02456 #define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE)
02457 
02458 /*! @brief Set the RXRTSE field to a new value. */
02459 #define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
02460 /*@}*/
02461 
02462 /*******************************************************************************
02463  * HW_UART_IR - UART Infrared Register
02464  ******************************************************************************/
02465 
02466 /*!
02467  * @brief HW_UART_IR - UART Infrared Register (RW)
02468  *
02469  * Reset value: 0x00U
02470  *
02471  * The IR register controls options for setting the infrared configuration.
02472  */
02473 typedef union _hw_uart_ir
02474 {
02475     uint8_t U;
02476     struct _hw_uart_ir_bitfields
02477     {
02478         uint8_t TNP : 2;               /*!< [1:0] Transmitter narrow pulse */
02479         uint8_t IREN : 1;              /*!< [2] Infrared enable */
02480         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
02481     } B;
02482 } hw_uart_ir_t;
02483 
02484 /*!
02485  * @name Constants and macros for entire UART_IR register
02486  */
02487 /*@{*/
02488 #define HW_UART_IR_ADDR(x)       ((x) + 0xEU)
02489 
02490 #define HW_UART_IR(x)            (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
02491 #define HW_UART_IR_RD(x)         (HW_UART_IR(x).U)
02492 #define HW_UART_IR_WR(x, v)      (HW_UART_IR(x).U = (v))
02493 #define HW_UART_IR_SET(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) |  (v)))
02494 #define HW_UART_IR_CLR(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
02495 #define HW_UART_IR_TOG(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^  (v)))
02496 /*@}*/
02497 
02498 /*
02499  * Constants & macros for individual UART_IR bitfields
02500  */
02501 
02502 /*!
02503  * @name Register UART_IR, field TNP[1:0] (RW)
02504  *
02505  * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
02506  *
02507  * Values:
02508  * - 00 - 3/16.
02509  * - 01 - 1/16.
02510  * - 10 - 1/32.
02511  * - 11 - 1/4.
02512  */
02513 /*@{*/
02514 #define BP_UART_IR_TNP       (0U)          /*!< Bit position for UART_IR_TNP. */
02515 #define BM_UART_IR_TNP       (0x03U)       /*!< Bit mask for UART_IR_TNP. */
02516 #define BS_UART_IR_TNP       (2U)          /*!< Bit field size in bits for UART_IR_TNP. */
02517 
02518 /*! @brief Read current value of the UART_IR_TNP field. */
02519 #define BR_UART_IR_TNP(x)    (HW_UART_IR(x).B.TNP)
02520 
02521 /*! @brief Format value for bitfield UART_IR_TNP. */
02522 #define BF_UART_IR_TNP(v)    ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP)
02523 
02524 /*! @brief Set the TNP field to a new value. */
02525 #define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
02526 /*@}*/
02527 
02528 /*!
02529  * @name Register UART_IR, field IREN[2] (RW)
02530  *
02531  * Enables/disables the infrared modulation/demodulation.
02532  *
02533  * Values:
02534  * - 0 - IR disabled.
02535  * - 1 - IR enabled.
02536  */
02537 /*@{*/
02538 #define BP_UART_IR_IREN      (2U)          /*!< Bit position for UART_IR_IREN. */
02539 #define BM_UART_IR_IREN      (0x04U)       /*!< Bit mask for UART_IR_IREN. */
02540 #define BS_UART_IR_IREN      (1U)          /*!< Bit field size in bits for UART_IR_IREN. */
02541 
02542 /*! @brief Read current value of the UART_IR_IREN field. */
02543 #define BR_UART_IR_IREN(x)   (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
02544 
02545 /*! @brief Format value for bitfield UART_IR_IREN. */
02546 #define BF_UART_IR_IREN(v)   ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN)
02547 
02548 /*! @brief Set the IREN field to a new value. */
02549 #define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
02550 /*@}*/
02551 
02552 /*******************************************************************************
02553  * HW_UART_PFIFO - UART FIFO Parameters
02554  ******************************************************************************/
02555 
02556 /*!
02557  * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
02558  *
02559  * Reset value: 0x00U
02560  *
02561  * This register provides the ability for the programmer to turn on and off FIFO
02562  * functionality. It also provides the size of the FIFO that has been
02563  * implemented. This register may be read at any time. This register must be written only
02564  * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
02565  * empty.
02566  */
02567 typedef union _hw_uart_pfifo
02568 {
02569     uint8_t U;
02570     struct _hw_uart_pfifo_bitfields
02571     {
02572         uint8_t RXFIFOSIZE : 3;        /*!< [2:0] Receive FIFO. Buffer Depth */
02573         uint8_t RXFE : 1;              /*!< [3] Receive FIFO Enable */
02574         uint8_t TXFIFOSIZE : 3;        /*!< [6:4] Transmit FIFO. Buffer Depth */
02575         uint8_t TXFE : 1;              /*!< [7] Transmit FIFO Enable */
02576     } B;
02577 } hw_uart_pfifo_t;
02578 
02579 /*!
02580  * @name Constants and macros for entire UART_PFIFO register
02581  */
02582 /*@{*/
02583 #define HW_UART_PFIFO_ADDR(x)    ((x) + 0x10U)
02584 
02585 #define HW_UART_PFIFO(x)         (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
02586 #define HW_UART_PFIFO_RD(x)      (HW_UART_PFIFO(x).U)
02587 #define HW_UART_PFIFO_WR(x, v)   (HW_UART_PFIFO(x).U = (v))
02588 #define HW_UART_PFIFO_SET(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) |  (v)))
02589 #define HW_UART_PFIFO_CLR(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
02590 #define HW_UART_PFIFO_TOG(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^  (v)))
02591 /*@}*/
02592 
02593 /*
02594  * Constants & macros for individual UART_PFIFO bitfields
02595  */
02596 
02597 /*!
02598  * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
02599  *
02600  * The maximum number of receive datawords that can be stored in the receive
02601  * buffer before an overrun occurs. This field is read only.
02602  *
02603  * Values:
02604  * - 000 - Receive FIFO/Buffer depth = 1 dataword.
02605  * - 001 - Receive FIFO/Buffer depth = 4 datawords.
02606  * - 010 - Receive FIFO/Buffer depth = 8 datawords.
02607  * - 011 - Receive FIFO/Buffer depth = 16 datawords.
02608  * - 100 - Receive FIFO/Buffer depth = 32 datawords.
02609  * - 101 - Receive FIFO/Buffer depth = 64 datawords.
02610  * - 110 - Receive FIFO/Buffer depth = 128 datawords.
02611  * - 111 - Reserved.
02612  */
02613 /*@{*/
02614 #define BP_UART_PFIFO_RXFIFOSIZE (0U)      /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */
02615 #define BM_UART_PFIFO_RXFIFOSIZE (0x07U)   /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */
02616 #define BS_UART_PFIFO_RXFIFOSIZE (3U)      /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */
02617 
02618 /*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
02619 #define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
02620 /*@}*/
02621 
02622 /*!
02623  * @name Register UART_PFIFO, field RXFE[3] (RW)
02624  *
02625  * When this field is set, the built in FIFO structure for the receive buffer is
02626  * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
02627  * If this field is not set, the receive buffer operates as a FIFO of depth one
02628  * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
02629  * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
02630  * commands must be issued immediately after changing this field.
02631  *
02632  * Values:
02633  * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
02634  * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
02635  */
02636 /*@{*/
02637 #define BP_UART_PFIFO_RXFE   (3U)          /*!< Bit position for UART_PFIFO_RXFE. */
02638 #define BM_UART_PFIFO_RXFE   (0x08U)       /*!< Bit mask for UART_PFIFO_RXFE. */
02639 #define BS_UART_PFIFO_RXFE   (1U)          /*!< Bit field size in bits for UART_PFIFO_RXFE. */
02640 
02641 /*! @brief Read current value of the UART_PFIFO_RXFE field. */
02642 #define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
02643 
02644 /*! @brief Format value for bitfield UART_PFIFO_RXFE. */
02645 #define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE)
02646 
02647 /*! @brief Set the RXFE field to a new value. */
02648 #define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
02649 /*@}*/
02650 
02651 /*!
02652  * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
02653  *
02654  * The maximum number of transmit datawords that can be stored in the transmit
02655  * buffer. This field is read only.
02656  *
02657  * Values:
02658  * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
02659  * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
02660  * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
02661  * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
02662  * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
02663  * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
02664  * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
02665  * - 111 - Reserved.
02666  */
02667 /*@{*/
02668 #define BP_UART_PFIFO_TXFIFOSIZE (4U)      /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */
02669 #define BM_UART_PFIFO_TXFIFOSIZE (0x70U)   /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */
02670 #define BS_UART_PFIFO_TXFIFOSIZE (3U)      /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */
02671 
02672 /*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
02673 #define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
02674 /*@}*/
02675 
02676 /*!
02677  * @name Register UART_PFIFO, field TXFE[7] (RW)
02678  *
02679  * When this field is set, the built in FIFO structure for the transmit buffer
02680  * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
02681  * field is not set, the transmit buffer operates as a FIFO of depth one dataword
02682  * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
02683  * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
02684  * be issued immediately after changing this field.
02685  *
02686  * Values:
02687  * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
02688  * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
02689  */
02690 /*@{*/
02691 #define BP_UART_PFIFO_TXFE   (7U)          /*!< Bit position for UART_PFIFO_TXFE. */
02692 #define BM_UART_PFIFO_TXFE   (0x80U)       /*!< Bit mask for UART_PFIFO_TXFE. */
02693 #define BS_UART_PFIFO_TXFE   (1U)          /*!< Bit field size in bits for UART_PFIFO_TXFE. */
02694 
02695 /*! @brief Read current value of the UART_PFIFO_TXFE field. */
02696 #define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
02697 
02698 /*! @brief Format value for bitfield UART_PFIFO_TXFE. */
02699 #define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE)
02700 
02701 /*! @brief Set the TXFE field to a new value. */
02702 #define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
02703 /*@}*/
02704 
02705 /*******************************************************************************
02706  * HW_UART_CFIFO - UART FIFO Control Register
02707  ******************************************************************************/
02708 
02709 /*!
02710  * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
02711  *
02712  * Reset value: 0x00U
02713  *
02714  * This register provides the ability to program various control fields for FIFO
02715  * operation. This register may be read or written at any time. Note that
02716  * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
02717  * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
02718  * TE and RE be cleared prior to flushing the corresponding FIFO.
02719  */
02720 typedef union _hw_uart_cfifo
02721 {
02722     uint8_t U;
02723     struct _hw_uart_cfifo_bitfields
02724     {
02725         uint8_t RXUFE : 1;             /*!< [0] Receive FIFO Underflow Interrupt Enable */
02726         uint8_t TXOFE : 1;             /*!< [1] Transmit FIFO Overflow Interrupt Enable */
02727         uint8_t RXOFE : 1;             /*!< [2] Receive FIFO Overflow Interrupt Enable */
02728         uint8_t RESERVED0 : 3;         /*!< [5:3]  */
02729         uint8_t RXFLUSH : 1;           /*!< [6] Receive FIFO/Buffer Flush */
02730         uint8_t TXFLUSH : 1;           /*!< [7] Transmit FIFO/Buffer Flush */
02731     } B;
02732 } hw_uart_cfifo_t;
02733 
02734 /*!
02735  * @name Constants and macros for entire UART_CFIFO register
02736  */
02737 /*@{*/
02738 #define HW_UART_CFIFO_ADDR(x)    ((x) + 0x11U)
02739 
02740 #define HW_UART_CFIFO(x)         (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
02741 #define HW_UART_CFIFO_RD(x)      (HW_UART_CFIFO(x).U)
02742 #define HW_UART_CFIFO_WR(x, v)   (HW_UART_CFIFO(x).U = (v))
02743 #define HW_UART_CFIFO_SET(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) |  (v)))
02744 #define HW_UART_CFIFO_CLR(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
02745 #define HW_UART_CFIFO_TOG(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^  (v)))
02746 /*@}*/
02747 
02748 /*
02749  * Constants & macros for individual UART_CFIFO bitfields
02750  */
02751 
02752 /*!
02753  * @name Register UART_CFIFO, field RXUFE[0] (RW)
02754  *
02755  * When this field is set, the RXUF flag generates an interrupt to the host.
02756  *
02757  * Values:
02758  * - 0 - RXUF flag does not generate an interrupt to the host.
02759  * - 1 - RXUF flag generates an interrupt to the host.
02760  */
02761 /*@{*/
02762 #define BP_UART_CFIFO_RXUFE  (0U)          /*!< Bit position for UART_CFIFO_RXUFE. */
02763 #define BM_UART_CFIFO_RXUFE  (0x01U)       /*!< Bit mask for UART_CFIFO_RXUFE. */
02764 #define BS_UART_CFIFO_RXUFE  (1U)          /*!< Bit field size in bits for UART_CFIFO_RXUFE. */
02765 
02766 /*! @brief Read current value of the UART_CFIFO_RXUFE field. */
02767 #define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
02768 
02769 /*! @brief Format value for bitfield UART_CFIFO_RXUFE. */
02770 #define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE)
02771 
02772 /*! @brief Set the RXUFE field to a new value. */
02773 #define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
02774 /*@}*/
02775 
02776 /*!
02777  * @name Register UART_CFIFO, field TXOFE[1] (RW)
02778  *
02779  * When this field is set, the TXOF flag generates an interrupt to the host.
02780  *
02781  * Values:
02782  * - 0 - TXOF flag does not generate an interrupt to the host.
02783  * - 1 - TXOF flag generates an interrupt to the host.
02784  */
02785 /*@{*/
02786 #define BP_UART_CFIFO_TXOFE  (1U)          /*!< Bit position for UART_CFIFO_TXOFE. */
02787 #define BM_UART_CFIFO_TXOFE  (0x02U)       /*!< Bit mask for UART_CFIFO_TXOFE. */
02788 #define BS_UART_CFIFO_TXOFE  (1U)          /*!< Bit field size in bits for UART_CFIFO_TXOFE. */
02789 
02790 /*! @brief Read current value of the UART_CFIFO_TXOFE field. */
02791 #define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
02792 
02793 /*! @brief Format value for bitfield UART_CFIFO_TXOFE. */
02794 #define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE)
02795 
02796 /*! @brief Set the TXOFE field to a new value. */
02797 #define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
02798 /*@}*/
02799 
02800 /*!
02801  * @name Register UART_CFIFO, field RXOFE[2] (RW)
02802  *
02803  * When this field is set, the RXOF flag generates an interrupt to the host.
02804  *
02805  * Values:
02806  * - 0 - RXOF flag does not generate an interrupt to the host.
02807  * - 1 - RXOF flag generates an interrupt to the host.
02808  */
02809 /*@{*/
02810 #define BP_UART_CFIFO_RXOFE  (2U)          /*!< Bit position for UART_CFIFO_RXOFE. */
02811 #define BM_UART_CFIFO_RXOFE  (0x04U)       /*!< Bit mask for UART_CFIFO_RXOFE. */
02812 #define BS_UART_CFIFO_RXOFE  (1U)          /*!< Bit field size in bits for UART_CFIFO_RXOFE. */
02813 
02814 /*! @brief Read current value of the UART_CFIFO_RXOFE field. */
02815 #define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
02816 
02817 /*! @brief Format value for bitfield UART_CFIFO_RXOFE. */
02818 #define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE)
02819 
02820 /*! @brief Set the RXOFE field to a new value. */
02821 #define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
02822 /*@}*/
02823 
02824 /*!
02825  * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
02826  *
02827  * Writing to this field causes all data that is stored in the receive
02828  * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
02829  * register.
02830  *
02831  * Values:
02832  * - 0 - No flush operation occurs.
02833  * - 1 - All data in the receive FIFO/buffer is cleared out.
02834  */
02835 /*@{*/
02836 #define BP_UART_CFIFO_RXFLUSH (6U)         /*!< Bit position for UART_CFIFO_RXFLUSH. */
02837 #define BM_UART_CFIFO_RXFLUSH (0x40U)      /*!< Bit mask for UART_CFIFO_RXFLUSH. */
02838 #define BS_UART_CFIFO_RXFLUSH (1U)         /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */
02839 
02840 /*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */
02841 #define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH)
02842 
02843 /*! @brief Set the RXFLUSH field to a new value. */
02844 #define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
02845 /*@}*/
02846 
02847 /*!
02848  * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
02849  *
02850  * Writing to this field causes all data that is stored in the transmit
02851  * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
02852  * register.
02853  *
02854  * Values:
02855  * - 0 - No flush operation occurs.
02856  * - 1 - All data in the transmit FIFO/Buffer is cleared out.
02857  */
02858 /*@{*/
02859 #define BP_UART_CFIFO_TXFLUSH (7U)         /*!< Bit position for UART_CFIFO_TXFLUSH. */
02860 #define BM_UART_CFIFO_TXFLUSH (0x80U)      /*!< Bit mask for UART_CFIFO_TXFLUSH. */
02861 #define BS_UART_CFIFO_TXFLUSH (1U)         /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */
02862 
02863 /*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */
02864 #define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH)
02865 
02866 /*! @brief Set the TXFLUSH field to a new value. */
02867 #define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
02868 /*@}*/
02869 
02870 /*******************************************************************************
02871  * HW_UART_SFIFO - UART FIFO Status Register
02872  ******************************************************************************/
02873 
02874 /*!
02875  * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
02876  *
02877  * Reset value: 0xC0U
02878  *
02879  * This register provides status information regarding the transmit and receiver
02880  * buffers/FIFOs, including interrupt information. This register may be written
02881  * to or read at any time.
02882  */
02883 typedef union _hw_uart_sfifo
02884 {
02885     uint8_t U;
02886     struct _hw_uart_sfifo_bitfields
02887     {
02888         uint8_t RXUF : 1;              /*!< [0] Receiver Buffer Underflow Flag */
02889         uint8_t TXOF : 1;              /*!< [1] Transmitter Buffer Overflow Flag */
02890         uint8_t RXOF : 1;              /*!< [2] Receiver Buffer Overflow Flag */
02891         uint8_t RESERVED0 : 3;         /*!< [5:3]  */
02892         uint8_t RXEMPT : 1;            /*!< [6] Receive Buffer/FIFO Empty */
02893         uint8_t TXEMPT : 1;            /*!< [7] Transmit Buffer/FIFO Empty */
02894     } B;
02895 } hw_uart_sfifo_t;
02896 
02897 /*!
02898  * @name Constants and macros for entire UART_SFIFO register
02899  */
02900 /*@{*/
02901 #define HW_UART_SFIFO_ADDR(x)    ((x) + 0x12U)
02902 
02903 #define HW_UART_SFIFO(x)         (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
02904 #define HW_UART_SFIFO_RD(x)      (HW_UART_SFIFO(x).U)
02905 #define HW_UART_SFIFO_WR(x, v)   (HW_UART_SFIFO(x).U = (v))
02906 #define HW_UART_SFIFO_SET(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) |  (v)))
02907 #define HW_UART_SFIFO_CLR(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
02908 #define HW_UART_SFIFO_TOG(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^  (v)))
02909 /*@}*/
02910 
02911 /*
02912  * Constants & macros for individual UART_SFIFO bitfields
02913  */
02914 
02915 /*!
02916  * @name Register UART_SFIFO, field RXUF[0] (W1C)
02917  *
02918  * Indicates that more data has been read from the receive buffer than was
02919  * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
02920  * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
02921  * is cleared by writing a 1.
02922  *
02923  * Values:
02924  * - 0 - No receive buffer underflow has occurred since the last time the flag
02925  *     was cleared.
02926  * - 1 - At least one receive buffer underflow has occurred since the last time
02927  *     the flag was cleared.
02928  */
02929 /*@{*/
02930 #define BP_UART_SFIFO_RXUF   (0U)          /*!< Bit position for UART_SFIFO_RXUF. */
02931 #define BM_UART_SFIFO_RXUF   (0x01U)       /*!< Bit mask for UART_SFIFO_RXUF. */
02932 #define BS_UART_SFIFO_RXUF   (1U)          /*!< Bit field size in bits for UART_SFIFO_RXUF. */
02933 
02934 /*! @brief Read current value of the UART_SFIFO_RXUF field. */
02935 #define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
02936 
02937 /*! @brief Format value for bitfield UART_SFIFO_RXUF. */
02938 #define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF)
02939 
02940 /*! @brief Set the RXUF field to a new value. */
02941 #define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
02942 /*@}*/
02943 
02944 /*!
02945  * @name Register UART_SFIFO, field TXOF[1] (W1C)
02946  *
02947  * Indicates that more data has been written to the transmit buffer than it can
02948  * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
02949  * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
02950  * flag is cleared by writing a 1.
02951  *
02952  * Values:
02953  * - 0 - No transmit buffer overflow has occurred since the last time the flag
02954  *     was cleared.
02955  * - 1 - At least one transmit buffer overflow has occurred since the last time
02956  *     the flag was cleared.
02957  */
02958 /*@{*/
02959 #define BP_UART_SFIFO_TXOF   (1U)          /*!< Bit position for UART_SFIFO_TXOF. */
02960 #define BM_UART_SFIFO_TXOF   (0x02U)       /*!< Bit mask for UART_SFIFO_TXOF. */
02961 #define BS_UART_SFIFO_TXOF   (1U)          /*!< Bit field size in bits for UART_SFIFO_TXOF. */
02962 
02963 /*! @brief Read current value of the UART_SFIFO_TXOF field. */
02964 #define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
02965 
02966 /*! @brief Format value for bitfield UART_SFIFO_TXOF. */
02967 #define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF)
02968 
02969 /*! @brief Set the TXOF field to a new value. */
02970 #define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
02971 /*@}*/
02972 
02973 /*!
02974  * @name Register UART_SFIFO, field RXOF[2] (W1C)
02975  *
02976  * Indicates that more data has been written to the receive buffer than it can
02977  * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
02978  * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
02979  * is cleared by writing a 1.
02980  *
02981  * Values:
02982  * - 0 - No receive buffer overflow has occurred since the last time the flag
02983  *     was cleared.
02984  * - 1 - At least one receive buffer overflow has occurred since the last time
02985  *     the flag was cleared.
02986  */
02987 /*@{*/
02988 #define BP_UART_SFIFO_RXOF   (2U)          /*!< Bit position for UART_SFIFO_RXOF. */
02989 #define BM_UART_SFIFO_RXOF   (0x04U)       /*!< Bit mask for UART_SFIFO_RXOF. */
02990 #define BS_UART_SFIFO_RXOF   (1U)          /*!< Bit field size in bits for UART_SFIFO_RXOF. */
02991 
02992 /*! @brief Read current value of the UART_SFIFO_RXOF field. */
02993 #define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
02994 
02995 /*! @brief Format value for bitfield UART_SFIFO_RXOF. */
02996 #define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF)
02997 
02998 /*! @brief Set the RXOF field to a new value. */
02999 #define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
03000 /*@}*/
03001 
03002 /*!
03003  * @name Register UART_SFIFO, field RXEMPT[6] (RO)
03004  *
03005  * Asserts when there is no data in the receive FIFO/Buffer. This field does not
03006  * take into account data that is in the receive shift register.
03007  *
03008  * Values:
03009  * - 0 - Receive buffer is not empty.
03010  * - 1 - Receive buffer is empty.
03011  */
03012 /*@{*/
03013 #define BP_UART_SFIFO_RXEMPT (6U)          /*!< Bit position for UART_SFIFO_RXEMPT. */
03014 #define BM_UART_SFIFO_RXEMPT (0x40U)       /*!< Bit mask for UART_SFIFO_RXEMPT. */
03015 #define BS_UART_SFIFO_RXEMPT (1U)          /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */
03016 
03017 /*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
03018 #define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
03019 /*@}*/
03020 
03021 /*!
03022  * @name Register UART_SFIFO, field TXEMPT[7] (RO)
03023  *
03024  * Asserts when there is no data in the Transmit FIFO/buffer. This field does
03025  * not take into account data that is in the transmit shift register.
03026  *
03027  * Values:
03028  * - 0 - Transmit buffer is not empty.
03029  * - 1 - Transmit buffer is empty.
03030  */
03031 /*@{*/
03032 #define BP_UART_SFIFO_TXEMPT (7U)          /*!< Bit position for UART_SFIFO_TXEMPT. */
03033 #define BM_UART_SFIFO_TXEMPT (0x80U)       /*!< Bit mask for UART_SFIFO_TXEMPT. */
03034 #define BS_UART_SFIFO_TXEMPT (1U)          /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */
03035 
03036 /*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
03037 #define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
03038 /*@}*/
03039 
03040 /*******************************************************************************
03041  * HW_UART_TWFIFO - UART FIFO Transmit Watermark
03042  ******************************************************************************/
03043 
03044 /*!
03045  * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
03046  *
03047  * Reset value: 0x00U
03048  *
03049  * This register provides the ability to set a programmable threshold for
03050  * notification of needing additional transmit data. This register may be read at any
03051  * time but must be written only when C2[TE] is not set. Changing the value of the
03052  * watermark will not clear the S1[TDRE] flag.
03053  */
03054 typedef union _hw_uart_twfifo
03055 {
03056     uint8_t U;
03057     struct _hw_uart_twfifo_bitfields
03058     {
03059         uint8_t TXWATER : 8;           /*!< [7:0] Transmit Watermark */
03060     } B;
03061 } hw_uart_twfifo_t;
03062 
03063 /*!
03064  * @name Constants and macros for entire UART_TWFIFO register
03065  */
03066 /*@{*/
03067 #define HW_UART_TWFIFO_ADDR(x)   ((x) + 0x13U)
03068 
03069 #define HW_UART_TWFIFO(x)        (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
03070 #define HW_UART_TWFIFO_RD(x)     (HW_UART_TWFIFO(x).U)
03071 #define HW_UART_TWFIFO_WR(x, v)  (HW_UART_TWFIFO(x).U = (v))
03072 #define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) |  (v)))
03073 #define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
03074 #define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^  (v)))
03075 /*@}*/
03076 
03077 /*
03078  * Constants & macros for individual UART_TWFIFO bitfields
03079  */
03080 
03081 /*!
03082  * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
03083  *
03084  * When the number of datawords in the transmit FIFO/buffer is equal to or less
03085  * than the value in this register field, an interrupt via S1[TDRE] or a DMA
03086  * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
03087  * proper operation, the value in TXWATER must be set to be less than the size of
03088  * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
03089  */
03090 /*@{*/
03091 #define BP_UART_TWFIFO_TXWATER (0U)        /*!< Bit position for UART_TWFIFO_TXWATER. */
03092 #define BM_UART_TWFIFO_TXWATER (0xFFU)     /*!< Bit mask for UART_TWFIFO_TXWATER. */
03093 #define BS_UART_TWFIFO_TXWATER (8U)        /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */
03094 
03095 /*! @brief Read current value of the UART_TWFIFO_TXWATER field. */
03096 #define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
03097 
03098 /*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */
03099 #define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER)
03100 
03101 /*! @brief Set the TXWATER field to a new value. */
03102 #define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
03103 /*@}*/
03104 
03105 /*******************************************************************************
03106  * HW_UART_TCFIFO - UART FIFO Transmit Count
03107  ******************************************************************************/
03108 
03109 /*!
03110  * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
03111  *
03112  * Reset value: 0x00U
03113  *
03114  * This is a read only register that indicates how many datawords are currently
03115  * in the transmit buffer/FIFO. It may be read at any time.
03116  */
03117 typedef union _hw_uart_tcfifo
03118 {
03119     uint8_t U;
03120     struct _hw_uart_tcfifo_bitfields
03121     {
03122         uint8_t TXCOUNT : 8;           /*!< [7:0] Transmit Counter */
03123     } B;
03124 } hw_uart_tcfifo_t;
03125 
03126 /*!
03127  * @name Constants and macros for entire UART_TCFIFO register
03128  */
03129 /*@{*/
03130 #define HW_UART_TCFIFO_ADDR(x)   ((x) + 0x14U)
03131 
03132 #define HW_UART_TCFIFO(x)        (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
03133 #define HW_UART_TCFIFO_RD(x)     (HW_UART_TCFIFO(x).U)
03134 /*@}*/
03135 
03136 /*
03137  * Constants & macros for individual UART_TCFIFO bitfields
03138  */
03139 
03140 /*!
03141  * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
03142  *
03143  * The value in this register indicates the number of datawords that are in the
03144  * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
03145  * transmit shift register, it is not included in the count. This value may be used
03146  * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
03147  * transmit FIFO/buffer.
03148  */
03149 /*@{*/
03150 #define BP_UART_TCFIFO_TXCOUNT (0U)        /*!< Bit position for UART_TCFIFO_TXCOUNT. */
03151 #define BM_UART_TCFIFO_TXCOUNT (0xFFU)     /*!< Bit mask for UART_TCFIFO_TXCOUNT. */
03152 #define BS_UART_TCFIFO_TXCOUNT (8U)        /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */
03153 
03154 /*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */
03155 #define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
03156 /*@}*/
03157 
03158 /*******************************************************************************
03159  * HW_UART_RWFIFO - UART FIFO Receive Watermark
03160  ******************************************************************************/
03161 
03162 /*!
03163  * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
03164  *
03165  * Reset value: 0x01U
03166  *
03167  * This register provides the ability to set a programmable threshold for
03168  * notification of the need to remove data from the receiver FIFO/buffer. This register
03169  * may be read at any time but must be written only when C2[RE] is not asserted.
03170  * Changing the value in this register will not clear S1[RDRF].
03171  */
03172 typedef union _hw_uart_rwfifo
03173 {
03174     uint8_t U;
03175     struct _hw_uart_rwfifo_bitfields
03176     {
03177         uint8_t RXWATER : 8;           /*!< [7:0] Receive Watermark */
03178     } B;
03179 } hw_uart_rwfifo_t;
03180 
03181 /*!
03182  * @name Constants and macros for entire UART_RWFIFO register
03183  */
03184 /*@{*/
03185 #define HW_UART_RWFIFO_ADDR(x)   ((x) + 0x15U)
03186 
03187 #define HW_UART_RWFIFO(x)        (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
03188 #define HW_UART_RWFIFO_RD(x)     (HW_UART_RWFIFO(x).U)
03189 #define HW_UART_RWFIFO_WR(x, v)  (HW_UART_RWFIFO(x).U = (v))
03190 #define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) |  (v)))
03191 #define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
03192 #define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^  (v)))
03193 /*@}*/
03194 
03195 /*
03196  * Constants & macros for individual UART_RWFIFO bitfields
03197  */
03198 
03199 /*!
03200  * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
03201  *
03202  * When the number of datawords in the receive FIFO/buffer is equal to or
03203  * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
03204  * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
03205  * proper operation, the value in RXWATER must be set to be less than the receive
03206  * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
03207  * greater than 0.
03208  */
03209 /*@{*/
03210 #define BP_UART_RWFIFO_RXWATER (0U)        /*!< Bit position for UART_RWFIFO_RXWATER. */
03211 #define BM_UART_RWFIFO_RXWATER (0xFFU)     /*!< Bit mask for UART_RWFIFO_RXWATER. */
03212 #define BS_UART_RWFIFO_RXWATER (8U)        /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */
03213 
03214 /*! @brief Read current value of the UART_RWFIFO_RXWATER field. */
03215 #define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
03216 
03217 /*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */
03218 #define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER)
03219 
03220 /*! @brief Set the RXWATER field to a new value. */
03221 #define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
03222 /*@}*/
03223 
03224 /*******************************************************************************
03225  * HW_UART_RCFIFO - UART FIFO Receive Count
03226  ******************************************************************************/
03227 
03228 /*!
03229  * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
03230  *
03231  * Reset value: 0x00U
03232  *
03233  * This is a read only register that indicates how many datawords are currently
03234  * in the receive FIFO/buffer. It may be read at any time.
03235  */
03236 typedef union _hw_uart_rcfifo
03237 {
03238     uint8_t U;
03239     struct _hw_uart_rcfifo_bitfields
03240     {
03241         uint8_t RXCOUNT : 8;           /*!< [7:0] Receive Counter */
03242     } B;
03243 } hw_uart_rcfifo_t;
03244 
03245 /*!
03246  * @name Constants and macros for entire UART_RCFIFO register
03247  */
03248 /*@{*/
03249 #define HW_UART_RCFIFO_ADDR(x)   ((x) + 0x16U)
03250 
03251 #define HW_UART_RCFIFO(x)        (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
03252 #define HW_UART_RCFIFO_RD(x)     (HW_UART_RCFIFO(x).U)
03253 /*@}*/
03254 
03255 /*
03256  * Constants & macros for individual UART_RCFIFO bitfields
03257  */
03258 
03259 /*!
03260  * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
03261  *
03262  * The value in this register indicates the number of datawords that are in the
03263  * receive FIFO/buffer. If a dataword is being received, that is, in the receive
03264  * shift register, it is not included in the count. This value may be used in
03265  * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
03266  * receive FIFO/buffer.
03267  */
03268 /*@{*/
03269 #define BP_UART_RCFIFO_RXCOUNT (0U)        /*!< Bit position for UART_RCFIFO_RXCOUNT. */
03270 #define BM_UART_RCFIFO_RXCOUNT (0xFFU)     /*!< Bit mask for UART_RCFIFO_RXCOUNT. */
03271 #define BS_UART_RCFIFO_RXCOUNT (8U)        /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */
03272 
03273 /*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */
03274 #define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
03275 /*@}*/
03276 
03277 /*******************************************************************************
03278  * HW_UART_C7816 - UART 7816 Control Register
03279  ******************************************************************************/
03280 
03281 /*!
03282  * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
03283  *
03284  * Reset value: 0x00U
03285  *
03286  * The C7816 register is the primary control register for ISO-7816 specific
03287  * functionality. This register is specific to 7816 functionality and the values in
03288  * this register have no effect on UART operation and should be ignored if
03289  * ISO_7816E is not set/enabled. This register may be read at any time but values must
03290  * be changed only when ISO_7816E is not set.
03291  */
03292 typedef union _hw_uart_c7816
03293 {
03294     uint8_t U;
03295     struct _hw_uart_c7816_bitfields
03296     {
03297         uint8_t ISO_7816E : 1;         /*!< [0] ISO-7816 Functionality Enabled */
03298         uint8_t TTYPE : 1;             /*!< [1] Transfer Type */
03299         uint8_t INIT : 1;              /*!< [2] Detect Initial Character */
03300         uint8_t ANACK : 1;             /*!< [3] Generate NACK on Error */
03301         uint8_t ONACK : 1;             /*!< [4] Generate NACK on Overflow */
03302         uint8_t RESERVED0 : 3;         /*!< [7:5]  */
03303     } B;
03304 } hw_uart_c7816_t;
03305 
03306 /*!
03307  * @name Constants and macros for entire UART_C7816 register
03308  */
03309 /*@{*/
03310 #define HW_UART_C7816_ADDR(x)    ((x) + 0x18U)
03311 
03312 #define HW_UART_C7816(x)         (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
03313 #define HW_UART_C7816_RD(x)      (HW_UART_C7816(x).U)
03314 #define HW_UART_C7816_WR(x, v)   (HW_UART_C7816(x).U = (v))
03315 #define HW_UART_C7816_SET(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) |  (v)))
03316 #define HW_UART_C7816_CLR(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
03317 #define HW_UART_C7816_TOG(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^  (v)))
03318 /*@}*/
03319 
03320 /*
03321  * Constants & macros for individual UART_C7816 bitfields
03322  */
03323 
03324 /*!
03325  * @name Register UART_C7816, field ISO_7816E[0] (RW)
03326  *
03327  * Indicates that the UART is operating according to the ISO-7816 protocol. This
03328  * field must be modified only when no transmit or receive is occurring. If this
03329  * field is changed during a data transfer, the data being transmitted or
03330  * received may be transferred incorrectly.
03331  *
03332  * Values:
03333  * - 0 - ISO-7816 functionality is turned off/not enabled.
03334  * - 1 - ISO-7816 functionality is turned on/enabled.
03335  */
03336 /*@{*/
03337 #define BP_UART_C7816_ISO_7816E (0U)       /*!< Bit position for UART_C7816_ISO_7816E. */
03338 #define BM_UART_C7816_ISO_7816E (0x01U)    /*!< Bit mask for UART_C7816_ISO_7816E. */
03339 #define BS_UART_C7816_ISO_7816E (1U)       /*!< Bit field size in bits for UART_C7816_ISO_7816E. */
03340 
03341 /*! @brief Read current value of the UART_C7816_ISO_7816E field. */
03342 #define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
03343 
03344 /*! @brief Format value for bitfield UART_C7816_ISO_7816E. */
03345 #define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E)
03346 
03347 /*! @brief Set the ISO_7816E field to a new value. */
03348 #define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
03349 /*@}*/
03350 
03351 /*!
03352  * @name Register UART_C7816, field TTYPE[1] (RW)
03353  *
03354  * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
03355  * for more details.
03356  *
03357  * Values:
03358  * - 0 - T = 0 per the ISO-7816 specification.
03359  * - 1 - T = 1 per the ISO-7816 specification.
03360  */
03361 /*@{*/
03362 #define BP_UART_C7816_TTYPE  (1U)          /*!< Bit position for UART_C7816_TTYPE. */
03363 #define BM_UART_C7816_TTYPE  (0x02U)       /*!< Bit mask for UART_C7816_TTYPE. */
03364 #define BS_UART_C7816_TTYPE  (1U)          /*!< Bit field size in bits for UART_C7816_TTYPE. */
03365 
03366 /*! @brief Read current value of the UART_C7816_TTYPE field. */
03367 #define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
03368 
03369 /*! @brief Format value for bitfield UART_C7816_TTYPE. */
03370 #define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE)
03371 
03372 /*! @brief Set the TTYPE field to a new value. */
03373 #define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
03374 /*@}*/
03375 
03376 /*!
03377  * @name Register UART_C7816, field INIT[2] (RW)
03378  *
03379  * When this field is set, all received characters are searched for a valid
03380  * initial character. If an invalid initial character is identified, and ANACK is
03381  * set, a NACK is sent. All received data is discarded and error flags blocked
03382  * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
03383  * until a valid initial character is detected. Upon detecting a valid initial
03384  * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
03385  * automatically updated to reflect the initial character that was received. The
03386  * actual INIT data value is not stored in the receive buffer. Additionally, upon
03387  * detection of a valid initial character, IS7816[INITD] is set and an interrupt
03388  * issued as programmed by IE7816[INITDE]. When a valid initial character is
03389  * detected, INIT is automatically cleared. This Initial Character Detect feature is
03390  * supported only in T = 0 protocol mode.
03391  *
03392  * Values:
03393  * - 0 - Normal operating mode. Receiver does not seek to identify initial
03394  *     character.
03395  * - 1 - Receiver searches for initial character.
03396  */
03397 /*@{*/
03398 #define BP_UART_C7816_INIT   (2U)          /*!< Bit position for UART_C7816_INIT. */
03399 #define BM_UART_C7816_INIT   (0x04U)       /*!< Bit mask for UART_C7816_INIT. */
03400 #define BS_UART_C7816_INIT   (1U)          /*!< Bit field size in bits for UART_C7816_INIT. */
03401 
03402 /*! @brief Read current value of the UART_C7816_INIT field. */
03403 #define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
03404 
03405 /*! @brief Format value for bitfield UART_C7816_INIT. */
03406 #define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT)
03407 
03408 /*! @brief Set the INIT field to a new value. */
03409 #define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
03410 /*@}*/
03411 
03412 /*!
03413  * @name Register UART_C7816, field ANACK[3] (RW)
03414  *
03415  * When this field is set, the receiver automatically generates a NACK response
03416  * if a parity error occurs or if INIT is set and an invalid initial character is
03417  * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
03418  * attempts to retransmit the data indefinitely. To stop retransmission attempts,
03419  * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
03420  *
03421  * Values:
03422  * - 0 - No NACK is automatically generated.
03423  * - 1 - A NACK is automatically generated if a parity error is detected or if
03424  *     an invalid initial character is detected.
03425  */
03426 /*@{*/
03427 #define BP_UART_C7816_ANACK  (3U)          /*!< Bit position for UART_C7816_ANACK. */
03428 #define BM_UART_C7816_ANACK  (0x08U)       /*!< Bit mask for UART_C7816_ANACK. */
03429 #define BS_UART_C7816_ANACK  (1U)          /*!< Bit field size in bits for UART_C7816_ANACK. */
03430 
03431 /*! @brief Read current value of the UART_C7816_ANACK field. */
03432 #define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
03433 
03434 /*! @brief Format value for bitfield UART_C7816_ANACK. */
03435 #define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK)
03436 
03437 /*! @brief Set the ANACK field to a new value. */
03438 #define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
03439 /*@}*/
03440 
03441 /*!
03442  * @name Register UART_C7816, field ONACK[4] (RW)
03443  *
03444  * When this field is set, the receiver automatically generates a NACK response
03445  * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
03446  * this results in the transmitter resending the packet that overflowed until the
03447  * retransmit threshold for that transmitter is reached. A NACK is generated only
03448  * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
03449  * considerations
03450  *
03451  * Values:
03452  * - 0 - The received data does not generate a NACK when the receipt of the data
03453  *     results in an overflow event.
03454  * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
03455  *     received character.
03456  */
03457 /*@{*/
03458 #define BP_UART_C7816_ONACK  (4U)          /*!< Bit position for UART_C7816_ONACK. */
03459 #define BM_UART_C7816_ONACK  (0x10U)       /*!< Bit mask for UART_C7816_ONACK. */
03460 #define BS_UART_C7816_ONACK  (1U)          /*!< Bit field size in bits for UART_C7816_ONACK. */
03461 
03462 /*! @brief Read current value of the UART_C7816_ONACK field. */
03463 #define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
03464 
03465 /*! @brief Format value for bitfield UART_C7816_ONACK. */
03466 #define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK)
03467 
03468 /*! @brief Set the ONACK field to a new value. */
03469 #define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
03470 /*@}*/
03471 
03472 /*******************************************************************************
03473  * HW_UART_IE7816 - UART 7816 Interrupt Enable Register
03474  ******************************************************************************/
03475 
03476 /*!
03477  * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
03478  *
03479  * Reset value: 0x00U
03480  *
03481  * The IE7816 register controls which flags result in an interrupt being issued.
03482  * This register is specific to 7816 functionality, the corresponding flags that
03483  * drive the interrupts are not asserted when 7816E is not set/enabled. However,
03484  * these flags may remain set if they are asserted while 7816E was set and not
03485  * subsequently cleared. This register may be read or written to at any time.
03486  */
03487 typedef union _hw_uart_ie7816
03488 {
03489     uint8_t U;
03490     struct _hw_uart_ie7816_bitfields
03491     {
03492         uint8_t RXTE : 1;              /*!< [0] Receive Threshold Exceeded Interrupt
03493                                         * Enable */
03494         uint8_t TXTE : 1;              /*!< [1] Transmit Threshold Exceeded Interrupt
03495                                         * Enable */
03496         uint8_t GTVE : 1;              /*!< [2] Guard Timer Violated Interrupt Enable */
03497         uint8_t RESERVED0 : 1;         /*!< [3]  */
03498         uint8_t INITDE : 1;            /*!< [4] Initial Character Detected Interrupt
03499                                         * Enable */
03500         uint8_t BWTE : 1;              /*!< [5] Block Wait Timer Interrupt Enable */
03501         uint8_t CWTE : 1;              /*!< [6] Character Wait Timer Interrupt Enable */
03502         uint8_t WTE : 1;               /*!< [7] Wait Timer Interrupt Enable */
03503     } B;
03504 } hw_uart_ie7816_t;
03505 
03506 /*!
03507  * @name Constants and macros for entire UART_IE7816 register
03508  */
03509 /*@{*/
03510 #define HW_UART_IE7816_ADDR(x)   ((x) + 0x19U)
03511 
03512 #define HW_UART_IE7816(x)        (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
03513 #define HW_UART_IE7816_RD(x)     (HW_UART_IE7816(x).U)
03514 #define HW_UART_IE7816_WR(x, v)  (HW_UART_IE7816(x).U = (v))
03515 #define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) |  (v)))
03516 #define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
03517 #define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^  (v)))
03518 /*@}*/
03519 
03520 /*
03521  * Constants & macros for individual UART_IE7816 bitfields
03522  */
03523 
03524 /*!
03525  * @name Register UART_IE7816, field RXTE[0] (RW)
03526  *
03527  * Values:
03528  * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
03529  *     interrupt.
03530  * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
03531  */
03532 /*@{*/
03533 #define BP_UART_IE7816_RXTE  (0U)          /*!< Bit position for UART_IE7816_RXTE. */
03534 #define BM_UART_IE7816_RXTE  (0x01U)       /*!< Bit mask for UART_IE7816_RXTE. */
03535 #define BS_UART_IE7816_RXTE  (1U)          /*!< Bit field size in bits for UART_IE7816_RXTE. */
03536 
03537 /*! @brief Read current value of the UART_IE7816_RXTE field. */
03538 #define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
03539 
03540 /*! @brief Format value for bitfield UART_IE7816_RXTE. */
03541 #define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE)
03542 
03543 /*! @brief Set the RXTE field to a new value. */
03544 #define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
03545 /*@}*/
03546 
03547 /*!
03548  * @name Register UART_IE7816, field TXTE[1] (RW)
03549  *
03550  * Values:
03551  * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
03552  *     interrupt.
03553  * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
03554  */
03555 /*@{*/
03556 #define BP_UART_IE7816_TXTE  (1U)          /*!< Bit position for UART_IE7816_TXTE. */
03557 #define BM_UART_IE7816_TXTE  (0x02U)       /*!< Bit mask for UART_IE7816_TXTE. */
03558 #define BS_UART_IE7816_TXTE  (1U)          /*!< Bit field size in bits for UART_IE7816_TXTE. */
03559 
03560 /*! @brief Read current value of the UART_IE7816_TXTE field. */
03561 #define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
03562 
03563 /*! @brief Format value for bitfield UART_IE7816_TXTE. */
03564 #define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE)
03565 
03566 /*! @brief Set the TXTE field to a new value. */
03567 #define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
03568 /*@}*/
03569 
03570 /*!
03571  * @name Register UART_IE7816, field GTVE[2] (RW)
03572  *
03573  * Values:
03574  * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
03575  *     interrupt.
03576  * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
03577  */
03578 /*@{*/
03579 #define BP_UART_IE7816_GTVE  (2U)          /*!< Bit position for UART_IE7816_GTVE. */
03580 #define BM_UART_IE7816_GTVE  (0x04U)       /*!< Bit mask for UART_IE7816_GTVE. */
03581 #define BS_UART_IE7816_GTVE  (1U)          /*!< Bit field size in bits for UART_IE7816_GTVE. */
03582 
03583 /*! @brief Read current value of the UART_IE7816_GTVE field. */
03584 #define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
03585 
03586 /*! @brief Format value for bitfield UART_IE7816_GTVE. */
03587 #define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE)
03588 
03589 /*! @brief Set the GTVE field to a new value. */
03590 #define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
03591 /*@}*/
03592 
03593 /*!
03594  * @name Register UART_IE7816, field INITDE[4] (RW)
03595  *
03596  * Values:
03597  * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
03598  *     interrupt.
03599  * - 1 - The assertion of IS7816[INITD] results in the generation of an
03600  *     interrupt.
03601  */
03602 /*@{*/
03603 #define BP_UART_IE7816_INITDE (4U)         /*!< Bit position for UART_IE7816_INITDE. */
03604 #define BM_UART_IE7816_INITDE (0x10U)      /*!< Bit mask for UART_IE7816_INITDE. */
03605 #define BS_UART_IE7816_INITDE (1U)         /*!< Bit field size in bits for UART_IE7816_INITDE. */
03606 
03607 /*! @brief Read current value of the UART_IE7816_INITDE field. */
03608 #define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
03609 
03610 /*! @brief Format value for bitfield UART_IE7816_INITDE. */
03611 #define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE)
03612 
03613 /*! @brief Set the INITDE field to a new value. */
03614 #define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
03615 /*@}*/
03616 
03617 /*!
03618  * @name Register UART_IE7816, field BWTE[5] (RW)
03619  *
03620  * Values:
03621  * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
03622  *     interrupt.
03623  * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
03624  */
03625 /*@{*/
03626 #define BP_UART_IE7816_BWTE  (5U)          /*!< Bit position for UART_IE7816_BWTE. */
03627 #define BM_UART_IE7816_BWTE  (0x20U)       /*!< Bit mask for UART_IE7816_BWTE. */
03628 #define BS_UART_IE7816_BWTE  (1U)          /*!< Bit field size in bits for UART_IE7816_BWTE. */
03629 
03630 /*! @brief Read current value of the UART_IE7816_BWTE field. */
03631 #define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
03632 
03633 /*! @brief Format value for bitfield UART_IE7816_BWTE. */
03634 #define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE)
03635 
03636 /*! @brief Set the BWTE field to a new value. */
03637 #define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
03638 /*@}*/
03639 
03640 /*!
03641  * @name Register UART_IE7816, field CWTE[6] (RW)
03642  *
03643  * Values:
03644  * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
03645  *     interrupt.
03646  * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
03647  */
03648 /*@{*/
03649 #define BP_UART_IE7816_CWTE  (6U)          /*!< Bit position for UART_IE7816_CWTE. */
03650 #define BM_UART_IE7816_CWTE  (0x40U)       /*!< Bit mask for UART_IE7816_CWTE. */
03651 #define BS_UART_IE7816_CWTE  (1U)          /*!< Bit field size in bits for UART_IE7816_CWTE. */
03652 
03653 /*! @brief Read current value of the UART_IE7816_CWTE field. */
03654 #define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
03655 
03656 /*! @brief Format value for bitfield UART_IE7816_CWTE. */
03657 #define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE)
03658 
03659 /*! @brief Set the CWTE field to a new value. */
03660 #define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
03661 /*@}*/
03662 
03663 /*!
03664  * @name Register UART_IE7816, field WTE[7] (RW)
03665  *
03666  * Values:
03667  * - 0 - The assertion of IS7816[WT] does not result in the generation of an
03668  *     interrupt.
03669  * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
03670  */
03671 /*@{*/
03672 #define BP_UART_IE7816_WTE   (7U)          /*!< Bit position for UART_IE7816_WTE. */
03673 #define BM_UART_IE7816_WTE   (0x80U)       /*!< Bit mask for UART_IE7816_WTE. */
03674 #define BS_UART_IE7816_WTE   (1U)          /*!< Bit field size in bits for UART_IE7816_WTE. */
03675 
03676 /*! @brief Read current value of the UART_IE7816_WTE field. */
03677 #define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
03678 
03679 /*! @brief Format value for bitfield UART_IE7816_WTE. */
03680 #define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE)
03681 
03682 /*! @brief Set the WTE field to a new value. */
03683 #define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
03684 /*@}*/
03685 
03686 /*******************************************************************************
03687  * HW_UART_IS7816 - UART 7816 Interrupt Status Register
03688  ******************************************************************************/
03689 
03690 /*!
03691  * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
03692  *
03693  * Reset value: 0x00U
03694  *
03695  * The IS7816 register provides a mechanism to read and clear the interrupt
03696  * flags. All flags/interrupts are cleared by writing a 1 to the field location.
03697  * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
03698  * the flag condition that occurred since the last time the bit was cleared, not
03699  * that the condition currently exists. The status flags are set regardless of
03700  * whether the corresponding field in the IE7816 is set or cleared. The IE7816
03701  * controls only if an interrupt is issued to the host processor. This register is
03702  * specific to 7816 functionality and the values in this register have no affect on
03703  * UART operation and should be ignored if 7816E is not set/enabled. This
03704  * register may be read or written at anytime.
03705  */
03706 typedef union _hw_uart_is7816
03707 {
03708     uint8_t U;
03709     struct _hw_uart_is7816_bitfields
03710     {
03711         uint8_t RXT : 1;               /*!< [0] Receive Threshold Exceeded Interrupt */
03712         uint8_t TXT : 1;               /*!< [1] Transmit Threshold Exceeded Interrupt */
03713         uint8_t GTV : 1;               /*!< [2] Guard Timer Violated Interrupt */
03714         uint8_t RESERVED0 : 1;         /*!< [3]  */
03715         uint8_t INITD : 1;             /*!< [4] Initial Character Detected Interrupt */
03716         uint8_t BWT : 1;               /*!< [5] Block Wait Timer Interrupt */
03717         uint8_t CWT : 1;               /*!< [6] Character Wait Timer Interrupt */
03718         uint8_t WT : 1;                /*!< [7] Wait Timer Interrupt */
03719     } B;
03720 } hw_uart_is7816_t;
03721 
03722 /*!
03723  * @name Constants and macros for entire UART_IS7816 register
03724  */
03725 /*@{*/
03726 #define HW_UART_IS7816_ADDR(x)   ((x) + 0x1AU)
03727 
03728 #define HW_UART_IS7816(x)        (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
03729 #define HW_UART_IS7816_RD(x)     (HW_UART_IS7816(x).U)
03730 #define HW_UART_IS7816_WR(x, v)  (HW_UART_IS7816(x).U = (v))
03731 #define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) |  (v)))
03732 #define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
03733 #define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^  (v)))
03734 /*@}*/
03735 
03736 /*
03737  * Constants & macros for individual UART_IS7816 bitfields
03738  */
03739 
03740 /*!
03741  * @name Register UART_IS7816, field RXT[0] (W1C)
03742  *
03743  * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
03744  * generated in response to parity errors on received data. This flag requires ANACK
03745  * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
03746  * Clearing this field also resets the counter keeping track of consecutive NACKS. The
03747  * UART will continue to attempt to receive data regardless of whether this flag
03748  * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
03749  * or packet is received without needing to issue a NACK, the internal NACK
03750  * detection counter is cleared and the count restarts from zero on the next
03751  * transmitted NACK. This interrupt is cleared by writing 1.
03752  *
03753  * Values:
03754  * - 0 - The number of consecutive NACKS generated as a result of parity errors
03755  *     and buffer overruns is less than or equal to the value in
03756  *     ET7816[RXTHRESHOLD].
03757  * - 1 - The number of consecutive NACKS generated as a result of parity errors
03758  *     and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
03759  */
03760 /*@{*/
03761 #define BP_UART_IS7816_RXT   (0U)          /*!< Bit position for UART_IS7816_RXT. */
03762 #define BM_UART_IS7816_RXT   (0x01U)       /*!< Bit mask for UART_IS7816_RXT. */
03763 #define BS_UART_IS7816_RXT   (1U)          /*!< Bit field size in bits for UART_IS7816_RXT. */
03764 
03765 /*! @brief Read current value of the UART_IS7816_RXT field. */
03766 #define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
03767 
03768 /*! @brief Format value for bitfield UART_IS7816_RXT. */
03769 #define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT)
03770 
03771 /*! @brief Set the RXT field to a new value. */
03772 #define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
03773 /*@}*/
03774 
03775 /*!
03776  * @name Register UART_IS7816, field TXT[1] (W1C)
03777  *
03778  * Indicates that the transmit NACK threshold has been exceeded as indicated by
03779  * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
03780  * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
03781  * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
03782  * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
03783  * internal NACK detection counter is cleared and the count restarts from zero on
03784  * the next received NACK. This interrupt is cleared by writing 1.
03785  *
03786  * Values:
03787  * - 0 - The number of retries and corresponding NACKS does not exceed the value
03788  *     in ET7816[TXTHRESHOLD].
03789  * - 1 - The number of retries and corresponding NACKS exceeds the value in
03790  *     ET7816[TXTHRESHOLD].
03791  */
03792 /*@{*/
03793 #define BP_UART_IS7816_TXT   (1U)          /*!< Bit position for UART_IS7816_TXT. */
03794 #define BM_UART_IS7816_TXT   (0x02U)       /*!< Bit mask for UART_IS7816_TXT. */
03795 #define BS_UART_IS7816_TXT   (1U)          /*!< Bit field size in bits for UART_IS7816_TXT. */
03796 
03797 /*! @brief Read current value of the UART_IS7816_TXT field. */
03798 #define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
03799 
03800 /*! @brief Format value for bitfield UART_IS7816_TXT. */
03801 #define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT)
03802 
03803 /*! @brief Set the TXT field to a new value. */
03804 #define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
03805 /*@}*/
03806 
03807 /*!
03808  * @name Register UART_IS7816, field GTV[2] (W1C)
03809  *
03810  * Indicates that one or more of the character guard time, block guard time, or
03811  * guard time are violated. This interrupt is cleared by writing 1.
03812  *
03813  * Values:
03814  * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
03815  * - 1 - A guard time (GT, CGT, or BGT) has been violated.
03816  */
03817 /*@{*/
03818 #define BP_UART_IS7816_GTV   (2U)          /*!< Bit position for UART_IS7816_GTV. */
03819 #define BM_UART_IS7816_GTV   (0x04U)       /*!< Bit mask for UART_IS7816_GTV. */
03820 #define BS_UART_IS7816_GTV   (1U)          /*!< Bit field size in bits for UART_IS7816_GTV. */
03821 
03822 /*! @brief Read current value of the UART_IS7816_GTV field. */
03823 #define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
03824 
03825 /*! @brief Format value for bitfield UART_IS7816_GTV. */
03826 #define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV)
03827 
03828 /*! @brief Set the GTV field to a new value. */
03829 #define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
03830 /*@}*/
03831 
03832 /*!
03833  * @name Register UART_IS7816, field INITD[4] (W1C)
03834  *
03835  * Indicates that a valid initial character is received. This interrupt is
03836  * cleared by writing 1.
03837  *
03838  * Values:
03839  * - 0 - A valid initial character has not been received.
03840  * - 1 - A valid initial character has been received.
03841  */
03842 /*@{*/
03843 #define BP_UART_IS7816_INITD (4U)          /*!< Bit position for UART_IS7816_INITD. */
03844 #define BM_UART_IS7816_INITD (0x10U)       /*!< Bit mask for UART_IS7816_INITD. */
03845 #define BS_UART_IS7816_INITD (1U)          /*!< Bit field size in bits for UART_IS7816_INITD. */
03846 
03847 /*! @brief Read current value of the UART_IS7816_INITD field. */
03848 #define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
03849 
03850 /*! @brief Format value for bitfield UART_IS7816_INITD. */
03851 #define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD)
03852 
03853 /*! @brief Set the INITD field to a new value. */
03854 #define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
03855 /*@}*/
03856 
03857 /*!
03858  * @name Register UART_IS7816, field BWT[5] (W1C)
03859  *
03860  * Indicates that the block wait time, the time between the leading edge of
03861  * first received character of a block and the leading edge of the last character the
03862  * previously transmitted block, has exceeded the programmed value. This flag
03863  * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
03864  *
03865  * Values:
03866  * - 0 - Block wait time (BWT) has not been violated.
03867  * - 1 - Block wait time (BWT) has been violated.
03868  */
03869 /*@{*/
03870 #define BP_UART_IS7816_BWT   (5U)          /*!< Bit position for UART_IS7816_BWT. */
03871 #define BM_UART_IS7816_BWT   (0x20U)       /*!< Bit mask for UART_IS7816_BWT. */
03872 #define BS_UART_IS7816_BWT   (1U)          /*!< Bit field size in bits for UART_IS7816_BWT. */
03873 
03874 /*! @brief Read current value of the UART_IS7816_BWT field. */
03875 #define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
03876 
03877 /*! @brief Format value for bitfield UART_IS7816_BWT. */
03878 #define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT)
03879 
03880 /*! @brief Set the BWT field to a new value. */
03881 #define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
03882 /*@}*/
03883 
03884 /*!
03885  * @name Register UART_IS7816, field CWT[6] (W1C)
03886  *
03887  * Indicates that the character wait time, the time between the leading edges of
03888  * two consecutive characters in a block, has exceeded the programmed value.
03889  * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
03890  * writing 1.
03891  *
03892  * Values:
03893  * - 0 - Character wait time (CWT) has not been violated.
03894  * - 1 - Character wait time (CWT) has been violated.
03895  */
03896 /*@{*/
03897 #define BP_UART_IS7816_CWT   (6U)          /*!< Bit position for UART_IS7816_CWT. */
03898 #define BM_UART_IS7816_CWT   (0x40U)       /*!< Bit mask for UART_IS7816_CWT. */
03899 #define BS_UART_IS7816_CWT   (1U)          /*!< Bit field size in bits for UART_IS7816_CWT. */
03900 
03901 /*! @brief Read current value of the UART_IS7816_CWT field. */
03902 #define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
03903 
03904 /*! @brief Format value for bitfield UART_IS7816_CWT. */
03905 #define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT)
03906 
03907 /*! @brief Set the CWT field to a new value. */
03908 #define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
03909 /*@}*/
03910 
03911 /*!
03912  * @name Register UART_IS7816, field WT[7] (W1C)
03913  *
03914  * Indicates that the wait time, the time between the leading edge of a
03915  * character being transmitted and the leading edge of the next response character, has
03916  * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
03917  * This interrupt is cleared by writing 1.
03918  *
03919  * Values:
03920  * - 0 - Wait time (WT) has not been violated.
03921  * - 1 - Wait time (WT) has been violated.
03922  */
03923 /*@{*/
03924 #define BP_UART_IS7816_WT    (7U)          /*!< Bit position for UART_IS7816_WT. */
03925 #define BM_UART_IS7816_WT    (0x80U)       /*!< Bit mask for UART_IS7816_WT. */
03926 #define BS_UART_IS7816_WT    (1U)          /*!< Bit field size in bits for UART_IS7816_WT. */
03927 
03928 /*! @brief Read current value of the UART_IS7816_WT field. */
03929 #define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
03930 
03931 /*! @brief Format value for bitfield UART_IS7816_WT. */
03932 #define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT)
03933 
03934 /*! @brief Set the WT field to a new value. */
03935 #define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
03936 /*@}*/
03937 
03938 /*******************************************************************************
03939  * HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
03940  ******************************************************************************/
03941 
03942 /*!
03943  * @brief HW_UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
03944  *
03945  * Reset value: 0x0AU
03946  *
03947  * The WP7816 register contains constants used in the generation of various wait
03948  * timer counters. To save register space, this register is used differently
03949  * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
03950  * time. This register must be written to only when C7816[ISO_7816E] is not set.
03951  */
03952 typedef union _hw_uart_wp7816t0
03953 {
03954     uint8_t U;
03955     struct _hw_uart_wp7816t0_bitfields
03956     {
03957         uint8_t WI : 8;                /*!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) */
03958     } B;
03959 } hw_uart_wp7816t0_t;
03960 
03961 /*!
03962  * @name Constants and macros for entire UART_WP7816T0 register
03963  */
03964 /*@{*/
03965 #define HW_UART_WP7816T0_ADDR(x) ((x) + 0x1BU)
03966 
03967 #define HW_UART_WP7816T0(x)      (*(__IO hw_uart_wp7816t0_t *) HW_UART_WP7816T0_ADDR(x))
03968 #define HW_UART_WP7816T0_RD(x)   (HW_UART_WP7816T0(x).U)
03969 #define HW_UART_WP7816T0_WR(x, v) (HW_UART_WP7816T0(x).U = (v))
03970 #define HW_UART_WP7816T0_SET(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) |  (v)))
03971 #define HW_UART_WP7816T0_CLR(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) & ~(v)))
03972 #define HW_UART_WP7816T0_TOG(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) ^  (v)))
03973 /*@}*/
03974 
03975 /*
03976  * Constants & macros for individual UART_WP7816T0 bitfields
03977  */
03978 
03979 /*!
03980  * @name Register UART_WP7816T0, field WI[7:0] (RW)
03981  *
03982  * Used to calculate the value used for the WT counter. It represents a value
03983  * between 1 and 255. The value of zero is not valid. This value is used only when
03984  * C7816[TTYPE] = 0. See Wait time and guard time parameters.
03985  */
03986 /*@{*/
03987 #define BP_UART_WP7816T0_WI  (0U)          /*!< Bit position for UART_WP7816T0_WI. */
03988 #define BM_UART_WP7816T0_WI  (0xFFU)       /*!< Bit mask for UART_WP7816T0_WI. */
03989 #define BS_UART_WP7816T0_WI  (8U)          /*!< Bit field size in bits for UART_WP7816T0_WI. */
03990 
03991 /*! @brief Read current value of the UART_WP7816T0_WI field. */
03992 #define BR_UART_WP7816T0_WI(x) (HW_UART_WP7816T0(x).U)
03993 
03994 /*! @brief Format value for bitfield UART_WP7816T0_WI. */
03995 #define BF_UART_WP7816T0_WI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T0_WI) & BM_UART_WP7816T0_WI)
03996 
03997 /*! @brief Set the WI field to a new value. */
03998 #define BW_UART_WP7816T0_WI(x, v) (HW_UART_WP7816T0_WR(x, v))
03999 /*@}*/
04000 /*******************************************************************************
04001  * HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
04002  ******************************************************************************/
04003 
04004 /*!
04005  * @brief HW_UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
04006  *
04007  * Reset value: 0x0AU
04008  *
04009  * The WP7816 register contains constants used in the generation of various wait
04010  * timer counters. To save register space, this register is used differently
04011  * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
04012  * time. This register must be written to only when C7816[ISO_7816E] is not set.
04013  */
04014 typedef union _hw_uart_wp7816t1
04015 {
04016     uint8_t U;
04017     struct _hw_uart_wp7816t1_bitfields
04018     {
04019         uint8_t BWI : 4;               /*!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
04020                                         * */
04021         uint8_t CWI : 4;               /*!< [7:4] Character Wait Time Integer (C7816[TTYPE]
04022                                         * = 1) */
04023     } B;
04024 } hw_uart_wp7816t1_t;
04025 
04026 /*!
04027  * @name Constants and macros for entire UART_WP7816T1 register
04028  */
04029 /*@{*/
04030 #define HW_UART_WP7816T1_ADDR(x) ((x) + 0x1BU)
04031 
04032 #define HW_UART_WP7816T1(x)      (*(__IO hw_uart_wp7816t1_t *) HW_UART_WP7816T1_ADDR(x))
04033 #define HW_UART_WP7816T1_RD(x)   (HW_UART_WP7816T1(x).U)
04034 #define HW_UART_WP7816T1_WR(x, v) (HW_UART_WP7816T1(x).U = (v))
04035 #define HW_UART_WP7816T1_SET(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) |  (v)))
04036 #define HW_UART_WP7816T1_CLR(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) & ~(v)))
04037 #define HW_UART_WP7816T1_TOG(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) ^  (v)))
04038 /*@}*/
04039 
04040 /*
04041  * Constants & macros for individual UART_WP7816T1 bitfields
04042  */
04043 
04044 /*!
04045  * @name Register UART_WP7816T1, field BWI[3:0] (RW)
04046  *
04047  * Used to calculate the value used for the BWT counter. It represent a value
04048  * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
04049  * and guard time parameters .
04050  */
04051 /*@{*/
04052 #define BP_UART_WP7816T1_BWI (0U)          /*!< Bit position for UART_WP7816T1_BWI. */
04053 #define BM_UART_WP7816T1_BWI (0x0FU)       /*!< Bit mask for UART_WP7816T1_BWI. */
04054 #define BS_UART_WP7816T1_BWI (4U)          /*!< Bit field size in bits for UART_WP7816T1_BWI. */
04055 
04056 /*! @brief Read current value of the UART_WP7816T1_BWI field. */
04057 #define BR_UART_WP7816T1_BWI(x) (HW_UART_WP7816T1(x).B.BWI)
04058 
04059 /*! @brief Format value for bitfield UART_WP7816T1_BWI. */
04060 #define BF_UART_WP7816T1_BWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_BWI) & BM_UART_WP7816T1_BWI)
04061 
04062 /*! @brief Set the BWI field to a new value. */
04063 #define BW_UART_WP7816T1_BWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_BWI) | BF_UART_WP7816T1_BWI(v)))
04064 /*@}*/
04065 
04066 /*!
04067  * @name Register UART_WP7816T1, field CWI[7:4] (RW)
04068  *
04069  * Used to calculate the value used for the CWT counter. It represents a value
04070  * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
04071  * and guard time parameters .
04072  */
04073 /*@{*/
04074 #define BP_UART_WP7816T1_CWI (4U)          /*!< Bit position for UART_WP7816T1_CWI. */
04075 #define BM_UART_WP7816T1_CWI (0xF0U)       /*!< Bit mask for UART_WP7816T1_CWI. */
04076 #define BS_UART_WP7816T1_CWI (4U)          /*!< Bit field size in bits for UART_WP7816T1_CWI. */
04077 
04078 /*! @brief Read current value of the UART_WP7816T1_CWI field. */
04079 #define BR_UART_WP7816T1_CWI(x) (HW_UART_WP7816T1(x).B.CWI)
04080 
04081 /*! @brief Format value for bitfield UART_WP7816T1_CWI. */
04082 #define BF_UART_WP7816T1_CWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_CWI) & BM_UART_WP7816T1_CWI)
04083 
04084 /*! @brief Set the CWI field to a new value. */
04085 #define BW_UART_WP7816T1_CWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_CWI) | BF_UART_WP7816T1_CWI(v)))
04086 /*@}*/
04087 
04088 /*******************************************************************************
04089  * HW_UART_WN7816 - UART 7816 Wait N Register
04090  ******************************************************************************/
04091 
04092 /*!
04093  * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
04094  *
04095  * Reset value: 0x00U
04096  *
04097  * The WN7816 register contains a parameter that is used in the calculation of
04098  * the guard time counter. This register may be read at any time. This register
04099  * must be written to only when C7816[ISO_7816E] is not set.
04100  */
04101 typedef union _hw_uart_wn7816
04102 {
04103     uint8_t U;
04104     struct _hw_uart_wn7816_bitfields
04105     {
04106         uint8_t GTN : 8;               /*!< [7:0] Guard Band N */
04107     } B;
04108 } hw_uart_wn7816_t;
04109 
04110 /*!
04111  * @name Constants and macros for entire UART_WN7816 register
04112  */
04113 /*@{*/
04114 #define HW_UART_WN7816_ADDR(x)   ((x) + 0x1CU)
04115 
04116 #define HW_UART_WN7816(x)        (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
04117 #define HW_UART_WN7816_RD(x)     (HW_UART_WN7816(x).U)
04118 #define HW_UART_WN7816_WR(x, v)  (HW_UART_WN7816(x).U = (v))
04119 #define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) |  (v)))
04120 #define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
04121 #define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^  (v)))
04122 /*@}*/
04123 
04124 /*
04125  * Constants & macros for individual UART_WN7816 bitfields
04126  */
04127 
04128 /*!
04129  * @name Register UART_WN7816, field GTN[7:0] (RW)
04130  *
04131  * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
04132  * value represents an integer number between 0 and 255. See Wait time and guard
04133  * time parameters .
04134  */
04135 /*@{*/
04136 #define BP_UART_WN7816_GTN   (0U)          /*!< Bit position for UART_WN7816_GTN. */
04137 #define BM_UART_WN7816_GTN   (0xFFU)       /*!< Bit mask for UART_WN7816_GTN. */
04138 #define BS_UART_WN7816_GTN   (8U)          /*!< Bit field size in bits for UART_WN7816_GTN. */
04139 
04140 /*! @brief Read current value of the UART_WN7816_GTN field. */
04141 #define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
04142 
04143 /*! @brief Format value for bitfield UART_WN7816_GTN. */
04144 #define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN)
04145 
04146 /*! @brief Set the GTN field to a new value. */
04147 #define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
04148 /*@}*/
04149 
04150 /*******************************************************************************
04151  * HW_UART_WF7816 - UART 7816 Wait FD Register
04152  ******************************************************************************/
04153 
04154 /*!
04155  * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
04156  *
04157  * Reset value: 0x01U
04158  *
04159  * The WF7816 contains parameters that are used in the generation of various
04160  * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
04161  * time. This register must be written to only when C7816[ISO_7816E] is not set.
04162  */
04163 typedef union _hw_uart_wf7816
04164 {
04165     uint8_t U;
04166     struct _hw_uart_wf7816_bitfields
04167     {
04168         uint8_t GTFD : 8;              /*!< [7:0] FD Multiplier */
04169     } B;
04170 } hw_uart_wf7816_t;
04171 
04172 /*!
04173  * @name Constants and macros for entire UART_WF7816 register
04174  */
04175 /*@{*/
04176 #define HW_UART_WF7816_ADDR(x)   ((x) + 0x1DU)
04177 
04178 #define HW_UART_WF7816(x)        (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
04179 #define HW_UART_WF7816_RD(x)     (HW_UART_WF7816(x).U)
04180 #define HW_UART_WF7816_WR(x, v)  (HW_UART_WF7816(x).U = (v))
04181 #define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) |  (v)))
04182 #define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
04183 #define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^  (v)))
04184 /*@}*/
04185 
04186 /*
04187  * Constants & macros for individual UART_WF7816 bitfields
04188  */
04189 
04190 /*!
04191  * @name Register UART_WF7816, field GTFD[7:0] (RW)
04192  *
04193  * Used as another multiplier in the calculation of WT and BWT. This value
04194  * represents a number between 1 and 255. The value of 0 is invalid. This value is not
04195  * used in baud rate generation. See Wait time and guard time parameters and
04196  * Baud rate generation .
04197  */
04198 /*@{*/
04199 #define BP_UART_WF7816_GTFD  (0U)          /*!< Bit position for UART_WF7816_GTFD. */
04200 #define BM_UART_WF7816_GTFD  (0xFFU)       /*!< Bit mask for UART_WF7816_GTFD. */
04201 #define BS_UART_WF7816_GTFD  (8U)          /*!< Bit field size in bits for UART_WF7816_GTFD. */
04202 
04203 /*! @brief Read current value of the UART_WF7816_GTFD field. */
04204 #define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
04205 
04206 /*! @brief Format value for bitfield UART_WF7816_GTFD. */
04207 #define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD)
04208 
04209 /*! @brief Set the GTFD field to a new value. */
04210 #define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
04211 /*@}*/
04212 
04213 /*******************************************************************************
04214  * HW_UART_ET7816 - UART 7816 Error Threshold Register
04215  ******************************************************************************/
04216 
04217 /*!
04218  * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
04219  *
04220  * Reset value: 0x00U
04221  *
04222  * The ET7816 register contains fields that determine the number of NACKs that
04223  * must be received or transmitted before the host processor is notified. This
04224  * register may be read at anytime. This register must be written to only when
04225  * C7816[ISO_7816E] is not set.
04226  */
04227 typedef union _hw_uart_et7816
04228 {
04229     uint8_t U;
04230     struct _hw_uart_et7816_bitfields
04231     {
04232         uint8_t RXTHRESHOLD : 4;       /*!< [3:0] Receive NACK Threshold */
04233         uint8_t TXTHRESHOLD : 4;       /*!< [7:4] Transmit NACK Threshold */
04234     } B;
04235 } hw_uart_et7816_t;
04236 
04237 /*!
04238  * @name Constants and macros for entire UART_ET7816 register
04239  */
04240 /*@{*/
04241 #define HW_UART_ET7816_ADDR(x)   ((x) + 0x1EU)
04242 
04243 #define HW_UART_ET7816(x)        (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
04244 #define HW_UART_ET7816_RD(x)     (HW_UART_ET7816(x).U)
04245 #define HW_UART_ET7816_WR(x, v)  (HW_UART_ET7816(x).U = (v))
04246 #define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) |  (v)))
04247 #define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
04248 #define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^  (v)))
04249 /*@}*/
04250 
04251 /*
04252  * Constants & macros for individual UART_ET7816 bitfields
04253  */
04254 
04255 /*!
04256  * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
04257  *
04258  * The value written to this field indicates the maximum number of consecutive
04259  * NACKs generated as a result of a parity error or receiver buffer overruns
04260  * before the host processor is notified. After the counter exceeds that value in the
04261  * field, the IS7816[RXT] is asserted. This field is meaningful only when
04262  * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
04263  * NACKs that have been transmitted since the last successful reception. This
04264  * counter saturates at 4'hF and does not wrap around. Regardless of the number of
04265  * NACKs sent, the UART continues to receive valid packets indefinitely. For
04266  * additional information, see IS7816[RXT] field description.
04267  */
04268 /*@{*/
04269 #define BP_UART_ET7816_RXTHRESHOLD (0U)    /*!< Bit position for UART_ET7816_RXTHRESHOLD. */
04270 #define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */
04271 #define BS_UART_ET7816_RXTHRESHOLD (4U)    /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */
04272 
04273 /*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
04274 #define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
04275 
04276 /*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */
04277 #define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD)
04278 
04279 /*! @brief Set the RXTHRESHOLD field to a new value. */
04280 #define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
04281 /*@}*/
04282 
04283 /*!
04284  * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
04285  *
04286  * The value written to this field indicates the maximum number of failed
04287  * attempts (NACKs) a transmitted character can have before the host processor is
04288  * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
04289  * The value read from this field represents the number of consecutive NACKs
04290  * that have been received since the last successful transmission. This counter
04291  * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
04292  * received, the UART continues to retransmit indefinitely. This flag only
04293  * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
04294  * description.
04295  *
04296  * Values:
04297  * - 0 - TXT asserts on the first NACK that is received.
04298  * - 1 - TXT asserts on the second NACK that is received.
04299  */
04300 /*@{*/
04301 #define BP_UART_ET7816_TXTHRESHOLD (4U)    /*!< Bit position for UART_ET7816_TXTHRESHOLD. */
04302 #define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */
04303 #define BS_UART_ET7816_TXTHRESHOLD (4U)    /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */
04304 
04305 /*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
04306 #define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
04307 
04308 /*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */
04309 #define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD)
04310 
04311 /*! @brief Set the TXTHRESHOLD field to a new value. */
04312 #define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
04313 /*@}*/
04314 
04315 /*******************************************************************************
04316  * HW_UART_TL7816 - UART 7816 Transmit Length Register
04317  ******************************************************************************/
04318 
04319 /*!
04320  * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
04321  *
04322  * Reset value: 0x00U
04323  *
04324  * The TL7816 register is used to indicate the number of characters contained in
04325  * the block being transmitted. This register is used only when C7816[TTYPE] =
04326  * 1. This register may be read at anytime. This register must be written only
04327  * when C2[TE] is not enabled.
04328  */
04329 typedef union _hw_uart_tl7816
04330 {
04331     uint8_t U;
04332     struct _hw_uart_tl7816_bitfields
04333     {
04334         uint8_t TLEN : 8;              /*!< [7:0] Transmit Length */
04335     } B;
04336 } hw_uart_tl7816_t;
04337 
04338 /*!
04339  * @name Constants and macros for entire UART_TL7816 register
04340  */
04341 /*@{*/
04342 #define HW_UART_TL7816_ADDR(x)   ((x) + 0x1FU)
04343 
04344 #define HW_UART_TL7816(x)        (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
04345 #define HW_UART_TL7816_RD(x)     (HW_UART_TL7816(x).U)
04346 #define HW_UART_TL7816_WR(x, v)  (HW_UART_TL7816(x).U = (v))
04347 #define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) |  (v)))
04348 #define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
04349 #define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^  (v)))
04350 /*@}*/
04351 
04352 /*
04353  * Constants & macros for individual UART_TL7816 bitfields
04354  */
04355 
04356 /*!
04357  * @name Register UART_TL7816, field TLEN[7:0] (RW)
04358  *
04359  * This value plus four indicates the number of characters contained in the
04360  * block being transmitted. This register is automatically decremented by 1 for each
04361  * character in the information field portion of the block. Additionally, this
04362  * register is automatically decremented by 1 for the first character of a CRC in
04363  * the epilogue field. Therefore, this register must be programmed with the number
04364  * of bytes in the data packet if an LRC is being transmitted, and the number of
04365  * bytes + 1 if a CRC is being transmitted. This register is not decremented for
04366  * characters that are assumed to be part of the Prologue field, that is, the
04367  * first three characters transmitted in a block, or the LRC or last CRC character
04368  * in the Epilogue field, that is, the last character transmitted. This field
04369  * must be programed or adjusted only when C2[TE] is cleared.
04370  */
04371 /*@{*/
04372 #define BP_UART_TL7816_TLEN  (0U)          /*!< Bit position for UART_TL7816_TLEN. */
04373 #define BM_UART_TL7816_TLEN  (0xFFU)       /*!< Bit mask for UART_TL7816_TLEN. */
04374 #define BS_UART_TL7816_TLEN  (8U)          /*!< Bit field size in bits for UART_TL7816_TLEN. */
04375 
04376 /*! @brief Read current value of the UART_TL7816_TLEN field. */
04377 #define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
04378 
04379 /*! @brief Format value for bitfield UART_TL7816_TLEN. */
04380 #define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN)
04381 
04382 /*! @brief Set the TLEN field to a new value. */
04383 #define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
04384 /*@}*/
04385 
04386 /*
04387 ** Start of section using anonymous unions
04388 */
04389 
04390 #if defined(__ARMCC_VERSION)
04391   #pragma push
04392   #pragma anon_unions
04393 #elif defined(__CWCC__)
04394   #pragma push
04395   #pragma cpp_extensions on
04396 #elif defined(__GNUC__)
04397   /* anonymous unions are enabled by default */
04398 #elif defined(__IAR_SYSTEMS_ICC__)
04399   #pragma language=extended
04400 #else
04401   #error Not supported compiler type
04402 #endif
04403 
04404 /*******************************************************************************
04405  * hw_uart_t - module struct
04406  ******************************************************************************/
04407 /*!
04408  * @brief All UART module registers.
04409  */
04410 #pragma pack(1)
04411 typedef struct _hw_uart
04412 {
04413     __IO hw_uart_bdh_t BDH ;                /*!< [0x0] UART Baud Rate Registers: High */
04414     __IO hw_uart_bdl_t BDL ;                /*!< [0x1] UART Baud Rate Registers: Low */
04415     __IO hw_uart_c1_t C1 ;                  /*!< [0x2] UART Control Register 1 */
04416     __IO hw_uart_c2_t C2 ;                  /*!< [0x3] UART Control Register 2 */
04417     __I hw_uart_s1_t S1 ;                   /*!< [0x4] UART Status Register 1 */
04418     __IO hw_uart_s2_t S2 ;                  /*!< [0x5] UART Status Register 2 */
04419     __IO hw_uart_c3_t C3 ;                  /*!< [0x6] UART Control Register 3 */
04420     __IO hw_uart_d_t D ;                    /*!< [0x7] UART Data Register */
04421     __IO hw_uart_ma1_t MA1 ;                /*!< [0x8] UART Match Address Registers 1 */
04422     __IO hw_uart_ma2_t MA2 ;                /*!< [0x9] UART Match Address Registers 2 */
04423     __IO hw_uart_c4_t C4 ;                  /*!< [0xA] UART Control Register 4 */
04424     __IO hw_uart_c5_t C5 ;                  /*!< [0xB] UART Control Register 5 */
04425     __I hw_uart_ed_t ED ;                   /*!< [0xC] UART Extended Data Register */
04426     __IO hw_uart_modem_t MODEM ;            /*!< [0xD] UART Modem Register */
04427     __IO hw_uart_ir_t IR ;                  /*!< [0xE] UART Infrared Register */
04428     uint8_t _reserved0[1];
04429     __IO hw_uart_pfifo_t PFIFO ;            /*!< [0x10] UART FIFO Parameters */
04430     __IO hw_uart_cfifo_t CFIFO ;            /*!< [0x11] UART FIFO Control Register */
04431     __IO hw_uart_sfifo_t SFIFO ;            /*!< [0x12] UART FIFO Status Register */
04432     __IO hw_uart_twfifo_t TWFIFO ;          /*!< [0x13] UART FIFO Transmit Watermark */
04433     __I hw_uart_tcfifo_t TCFIFO ;           /*!< [0x14] UART FIFO Transmit Count */
04434     __IO hw_uart_rwfifo_t RWFIFO ;          /*!< [0x15] UART FIFO Receive Watermark */
04435     __I hw_uart_rcfifo_t RCFIFO ;           /*!< [0x16] UART FIFO Receive Count */
04436     uint8_t _reserved1[1];
04437     __IO hw_uart_c7816_t C7816 ;            /*!< [0x18] UART 7816 Control Register */
04438     __IO hw_uart_ie7816_t IE7816 ;          /*!< [0x19] UART 7816 Interrupt Enable Register */
04439     __IO hw_uart_is7816_t IS7816 ;          /*!< [0x1A] UART 7816 Interrupt Status Register */
04440     union {
04441         __IO hw_uart_wp7816t0_t WP7816T0 ;  /*!< [0x1B] UART 7816 Wait Parameter Register */
04442         __IO hw_uart_wp7816t1_t WP7816T1 ;  /*!< [0x1B] UART 7816 Wait Parameter Register */
04443     };
04444     __IO hw_uart_wn7816_t WN7816 ;          /*!< [0x1C] UART 7816 Wait N Register */
04445     __IO hw_uart_wf7816_t WF7816 ;          /*!< [0x1D] UART 7816 Wait FD Register */
04446     __IO hw_uart_et7816_t ET7816 ;          /*!< [0x1E] UART 7816 Error Threshold Register */
04447     __IO hw_uart_tl7816_t TL7816 ;          /*!< [0x1F] UART 7816 Transmit Length Register */
04448 } hw_uart_t;
04449 #pragma pack()
04450 
04451 /*! @brief Macro to access all UART registers. */
04452 /*! @param x UART module instance base address. */
04453 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
04454  *     use the '&' operator, like <code>&HW_UART(UART0_BASE)</code>. */
04455 #define HW_UART(x)     (*(hw_uart_t *)(x))
04456 
04457 /*
04458 ** End of section using anonymous unions
04459 */
04460 
04461 #if defined(__ARMCC_VERSION)
04462   #pragma pop
04463 #elif defined(__CWCC__)
04464   #pragma pop
04465 #elif defined(__GNUC__)
04466   /* leave anonymous unions enabled */
04467 #elif defined(__IAR_SYSTEMS_ICC__)
04468   #pragma language=default
04469 #else
04470   #error Not supported compiler type
04471 #endif
04472 
04473 #endif /* __HW_UART_REGISTERS_H__ */
04474 /* EOF */