MK64F12_sdhc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_SDHC_REGISTERS_H__
00081 #define __HW_SDHC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 SDHC
00088  *
00089  * Secured Digital Host Controller
00090  *
00091  * Registers defined in this header file:
00092  * - HW_SDHC_DSADDR - DMA System Address register
00093  * - HW_SDHC_BLKATTR - Block Attributes register
00094  * - HW_SDHC_CMDARG - Command Argument register
00095  * - HW_SDHC_XFERTYP - Transfer Type register
00096  * - HW_SDHC_CMDRSP0 - Command Response 0
00097  * - HW_SDHC_CMDRSP1 - Command Response 1
00098  * - HW_SDHC_CMDRSP2 - Command Response 2
00099  * - HW_SDHC_CMDRSP3 - Command Response 3
00100  * - HW_SDHC_DATPORT - Buffer Data Port register
00101  * - HW_SDHC_PRSSTAT - Present State register
00102  * - HW_SDHC_PROCTL - Protocol Control register
00103  * - HW_SDHC_SYSCTL - System Control register
00104  * - HW_SDHC_IRQSTAT - Interrupt Status register
00105  * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
00106  * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
00107  * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
00108  * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
00109  * - HW_SDHC_WML - Watermark Level Register
00110  * - HW_SDHC_FEVT - Force Event register
00111  * - HW_SDHC_ADMAES - ADMA Error Status register
00112  * - HW_SDHC_ADSADDR - ADMA System Addressregister
00113  * - HW_SDHC_VENDOR - Vendor Specific register
00114  * - HW_SDHC_MMCBOOT - MMC Boot register
00115  * - HW_SDHC_HOSTVER - Host Controller Version
00116  *
00117  * - hw_sdhc_t - Struct containing all module registers.
00118  */
00119 
00120 #define HW_SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
00121 
00122 /*******************************************************************************
00123  * HW_SDHC_DSADDR - DMA System Address register
00124  ******************************************************************************/
00125 
00126 /*!
00127  * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
00128  *
00129  * Reset value: 0x00000000U
00130  *
00131  * This register contains the physical system memory address used for DMA
00132  * transfers.
00133  */
00134 typedef union _hw_sdhc_dsaddr
00135 {
00136     uint32_t U;
00137     struct _hw_sdhc_dsaddr_bitfields
00138     {
00139         uint32_t RESERVED0 : 2;        /*!< [1:0]  */
00140         uint32_t DSADDR : 30;          /*!< [31:2] DMA System Address */
00141     } B;
00142 } hw_sdhc_dsaddr_t;
00143 
00144 /*!
00145  * @name Constants and macros for entire SDHC_DSADDR register
00146  */
00147 /*@{*/
00148 #define HW_SDHC_DSADDR_ADDR(x)   ((x) + 0x0U)
00149 
00150 #define HW_SDHC_DSADDR(x)        (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR(x))
00151 #define HW_SDHC_DSADDR_RD(x)     (HW_SDHC_DSADDR(x).U)
00152 #define HW_SDHC_DSADDR_WR(x, v)  (HW_SDHC_DSADDR(x).U = (v))
00153 #define HW_SDHC_DSADDR_SET(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) |  (v)))
00154 #define HW_SDHC_DSADDR_CLR(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) & ~(v)))
00155 #define HW_SDHC_DSADDR_TOG(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) ^  (v)))
00156 /*@}*/
00157 
00158 /*
00159  * Constants & macros for individual SDHC_DSADDR bitfields
00160  */
00161 
00162 /*!
00163  * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
00164  *
00165  * Contains the 32-bit system memory address for a DMA transfer. Because the
00166  * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
00167  * When the SDHC stops a DMA transfer, this register points to the system address
00168  * of the next contiguous data position. It can be accessed only when no
00169  * transaction is executing, that is, after a transaction has stopped. Read operation
00170  * during transfers may return an invalid value. The host driver shall initialize
00171  * this register before starting a DMA transaction. After DMA has stopped, the
00172  * system address of the next contiguous data position can be read from this register.
00173  * This register is protected during a data transfer. When data lines are
00174  * active, write to this register is ignored. The host driver shall wait, until
00175  * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
00176  * not support a virtual memory system. It supports only continuous physical
00177  * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
00178  * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
00179  * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
00180  * automatically alters the value of internal address counter, so SW cannot
00181  * change this register when IRQSTAT[TC] is set.
00182  */
00183 /*@{*/
00184 #define BP_SDHC_DSADDR_DSADDR (2U)         /*!< Bit position for SDHC_DSADDR_DSADDR. */
00185 #define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_DSADDR_DSADDR. */
00186 #define BS_SDHC_DSADDR_DSADDR (30U)        /*!< Bit field size in bits for SDHC_DSADDR_DSADDR. */
00187 
00188 /*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
00189 #define BR_SDHC_DSADDR_DSADDR(x) (HW_SDHC_DSADDR(x).B.DSADDR)
00190 
00191 /*! @brief Format value for bitfield SDHC_DSADDR_DSADDR. */
00192 #define BF_SDHC_DSADDR_DSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DSADDR_DSADDR) & BM_SDHC_DSADDR_DSADDR)
00193 
00194 /*! @brief Set the DSADDR field to a new value. */
00195 #define BW_SDHC_DSADDR_DSADDR(x, v) (HW_SDHC_DSADDR_WR(x, (HW_SDHC_DSADDR_RD(x) & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
00196 /*@}*/
00197 
00198 /*******************************************************************************
00199  * HW_SDHC_BLKATTR - Block Attributes register
00200  ******************************************************************************/
00201 
00202 /*!
00203  * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
00204  *
00205  * Reset value: 0x00000000U
00206  *
00207  * This register is used to configure the number of data blocks and the number
00208  * of bytes in each block.
00209  */
00210 typedef union _hw_sdhc_blkattr
00211 {
00212     uint32_t U;
00213     struct _hw_sdhc_blkattr_bitfields
00214     {
00215         uint32_t BLKSIZE : 13;         /*!< [12:0] Transfer Block Size */
00216         uint32_t RESERVED0 : 3;        /*!< [15:13]  */
00217         uint32_t BLKCNT : 16;          /*!< [31:16] Blocks Count For Current Transfer
00218                                         * */
00219     } B;
00220 } hw_sdhc_blkattr_t;
00221 
00222 /*!
00223  * @name Constants and macros for entire SDHC_BLKATTR register
00224  */
00225 /*@{*/
00226 #define HW_SDHC_BLKATTR_ADDR(x)  ((x) + 0x4U)
00227 
00228 #define HW_SDHC_BLKATTR(x)       (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR(x))
00229 #define HW_SDHC_BLKATTR_RD(x)    (HW_SDHC_BLKATTR(x).U)
00230 #define HW_SDHC_BLKATTR_WR(x, v) (HW_SDHC_BLKATTR(x).U = (v))
00231 #define HW_SDHC_BLKATTR_SET(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) |  (v)))
00232 #define HW_SDHC_BLKATTR_CLR(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) & ~(v)))
00233 #define HW_SDHC_BLKATTR_TOG(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) ^  (v)))
00234 /*@}*/
00235 
00236 /*
00237  * Constants & macros for individual SDHC_BLKATTR bitfields
00238  */
00239 
00240 /*!
00241  * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
00242  *
00243  * Specifies the block size for block data transfers. Values ranging from 1 byte
00244  * up to the maximum buffer size can be set. It can be accessed only when no
00245  * transaction is executing, that is, after a transaction has stopped. Read
00246  * operations during transfers may return an invalid value, and write operations will be
00247  * ignored.
00248  *
00249  * Values:
00250  * - 0 - No data transfer.
00251  * - 1 - 1 Byte
00252  * - 10 - 2 Bytes
00253  * - 11 - 3 Bytes
00254  * - 100 - 4 Bytes
00255  * - 111111111 - 511 Bytes
00256  * - 1000000000 - 512 Bytes
00257  * - 100000000000 - 2048 Bytes
00258  * - 1000000000000 - 4096 Bytes
00259  */
00260 /*@{*/
00261 #define BP_SDHC_BLKATTR_BLKSIZE (0U)       /*!< Bit position for SDHC_BLKATTR_BLKSIZE. */
00262 #define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) /*!< Bit mask for SDHC_BLKATTR_BLKSIZE. */
00263 #define BS_SDHC_BLKATTR_BLKSIZE (13U)      /*!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE. */
00264 
00265 /*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
00266 #define BR_SDHC_BLKATTR_BLKSIZE(x) (HW_SDHC_BLKATTR(x).B.BLKSIZE)
00267 
00268 /*! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE. */
00269 #define BF_SDHC_BLKATTR_BLKSIZE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKSIZE) & BM_SDHC_BLKATTR_BLKSIZE)
00270 
00271 /*! @brief Set the BLKSIZE field to a new value. */
00272 #define BW_SDHC_BLKATTR_BLKSIZE(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
00273 /*@}*/
00274 
00275 /*!
00276  * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
00277  *
00278  * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
00279  * multiple block transfers. For single block transfer, this register will
00280  * always read as 1. The host driver shall set this register to a value between 1 and
00281  * the maximum block count. The SDHC decrements the block count after each block
00282  * transfer and stops when the count reaches zero. Setting the block count to 0
00283  * results in no data blocks being transferred. This register must be accessed
00284  * only when no transaction is executing, that is, after transactions are stopped.
00285  * During data transfer, read operations on this register may return an invalid
00286  * value and write operations are ignored. When saving transfer content as a result
00287  * of a suspend command, the number of blocks yet to be transferred can be
00288  * determined by reading this register. The reading of this register must be applied
00289  * after transfer is paused by stop at block gap operation and before sending the
00290  * command marked as suspend. This is because when suspend command is sent out,
00291  * SDHC will regard the current transfer as aborted and change BLKCNT back to its
00292  * original value instead of keeping the dynamical indicator of remained block
00293  * count. When restoring transfer content prior to issuing a resume command, the
00294  * host driver shall restore the previously saved block count. Although the BLKCNT
00295  * field is 0 after reset, the read of reset value is 0x1. This is because when
00296  * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
00297  * BLKCNT is always 1.
00298  *
00299  * Values:
00300  * - 0 - Stop count.
00301  * - 1 - 1 block
00302  * - 10 - 2 blocks
00303  * - 1111111111111111 - 65535 blocks
00304  */
00305 /*@{*/
00306 #define BP_SDHC_BLKATTR_BLKCNT (16U)       /*!< Bit position for SDHC_BLKATTR_BLKCNT. */
00307 #define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_BLKATTR_BLKCNT. */
00308 #define BS_SDHC_BLKATTR_BLKCNT (16U)       /*!< Bit field size in bits for SDHC_BLKATTR_BLKCNT. */
00309 
00310 /*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
00311 #define BR_SDHC_BLKATTR_BLKCNT(x) (HW_SDHC_BLKATTR(x).B.BLKCNT)
00312 
00313 /*! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT. */
00314 #define BF_SDHC_BLKATTR_BLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKCNT) & BM_SDHC_BLKATTR_BLKCNT)
00315 
00316 /*! @brief Set the BLKCNT field to a new value. */
00317 #define BW_SDHC_BLKATTR_BLKCNT(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
00318 /*@}*/
00319 
00320 /*******************************************************************************
00321  * HW_SDHC_CMDARG - Command Argument register
00322  ******************************************************************************/
00323 
00324 /*!
00325  * @brief HW_SDHC_CMDARG - Command Argument register (RW)
00326  *
00327  * Reset value: 0x00000000U
00328  *
00329  * This register contains the SD/MMC command argument.
00330  */
00331 typedef union _hw_sdhc_cmdarg
00332 {
00333     uint32_t U;
00334     struct _hw_sdhc_cmdarg_bitfields
00335     {
00336         uint32_t CMDARG : 32;          /*!< [31:0] Command Argument */
00337     } B;
00338 } hw_sdhc_cmdarg_t;
00339 
00340 /*!
00341  * @name Constants and macros for entire SDHC_CMDARG register
00342  */
00343 /*@{*/
00344 #define HW_SDHC_CMDARG_ADDR(x)   ((x) + 0x8U)
00345 
00346 #define HW_SDHC_CMDARG(x)        (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR(x))
00347 #define HW_SDHC_CMDARG_RD(x)     (HW_SDHC_CMDARG(x).U)
00348 #define HW_SDHC_CMDARG_WR(x, v)  (HW_SDHC_CMDARG(x).U = (v))
00349 #define HW_SDHC_CMDARG_SET(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) |  (v)))
00350 #define HW_SDHC_CMDARG_CLR(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) & ~(v)))
00351 #define HW_SDHC_CMDARG_TOG(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) ^  (v)))
00352 /*@}*/
00353 
00354 /*
00355  * Constants & macros for individual SDHC_CMDARG bitfields
00356  */
00357 
00358 /*!
00359  * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
00360  *
00361  * The SD/MMC command argument is specified as bits 39-8 of the command format
00362  * in the SD or MMC specification. This register is write protected when
00363  * PRSSTAT[CDIHB0] is set.
00364  */
00365 /*@{*/
00366 #define BP_SDHC_CMDARG_CMDARG (0U)         /*!< Bit position for SDHC_CMDARG_CMDARG. */
00367 #define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDARG_CMDARG. */
00368 #define BS_SDHC_CMDARG_CMDARG (32U)        /*!< Bit field size in bits for SDHC_CMDARG_CMDARG. */
00369 
00370 /*! @brief Read current value of the SDHC_CMDARG_CMDARG field. */
00371 #define BR_SDHC_CMDARG_CMDARG(x) (HW_SDHC_CMDARG(x).U)
00372 
00373 /*! @brief Format value for bitfield SDHC_CMDARG_CMDARG. */
00374 #define BF_SDHC_CMDARG_CMDARG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_CMDARG_CMDARG) & BM_SDHC_CMDARG_CMDARG)
00375 
00376 /*! @brief Set the CMDARG field to a new value. */
00377 #define BW_SDHC_CMDARG_CMDARG(x, v) (HW_SDHC_CMDARG_WR(x, v))
00378 /*@}*/
00379 
00380 /*******************************************************************************
00381  * HW_SDHC_XFERTYP - Transfer Type register
00382  ******************************************************************************/
00383 
00384 /*!
00385  * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
00386  *
00387  * Reset value: 0x00000000U
00388  *
00389  * This register is used to control the operation of data transfers. The host
00390  * driver shall set this register before issuing a command followed by a data
00391  * transfer, or before issuing a resume command. To prevent data loss, the SDHC
00392  * prevents writing to the bits that are involved in the data transfer of this
00393  * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
00394  * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
00395  * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
00396  * send a command with data by writing to this register is ignored; when
00397  * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
00398  * data transfer involved, it is mandatory that the block size is nonzero.
00399  * Besides, block count must also be nonzero, or indicated as single block transfer
00400  * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
00401  * this register is 0 when written), otherwise SDHC will ignore the sending of
00402  * this command and do nothing. For write command, with all above restrictions, it
00403  * is also mandatory that the write protect switch is not active (WPSPL bit of
00404  * Present State Register is 1), otherwise SDHC will also ignore the command. If
00405  * the commands with data transfer does not receive the response in 64 clock
00406  * cycles, that is, response time-out, SDHC will regard the external device does not
00407  * accept the command and abort the data transfer. In this scenario, the driver
00408  * must issue the command again to retry the transfer. It is also possible that,
00409  * for some reason, the card responds to the command but SDHC does not receive the
00410  * response, and if it is internal DMA (either simple DMA or ADMA) read
00411  * operation, the external system memory is over-written by the internal DMA with data
00412  * sent back from the card. The following table shows the summary of how register
00413  * settings determine the type of data transfer. Transfer Type register setting for
00414  * various transfer types Multi/Single block select Block count enable Block
00415  * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
00416  * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
00417  * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
00418  * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
00419  * Relationship between parameters and the name of the response type Response type
00420  * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
00421  * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
00422  * the SDIO specification, response type notation for R5b is not defined. R5
00423  * includes R5b in the SDIO specification. But R5b is defined in this specification
00424  * to specify that the SDHC will check the busy status after receiving a
00425  * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
00426  * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
00427  * The CRC check shall be disabled for these response types.
00428  */
00429 typedef union _hw_sdhc_xfertyp
00430 {
00431     uint32_t U;
00432     struct _hw_sdhc_xfertyp_bitfields
00433     {
00434         uint32_t DMAEN : 1;            /*!< [0] DMA Enable */
00435         uint32_t BCEN : 1;             /*!< [1] Block Count Enable */
00436         uint32_t AC12EN : 1;           /*!< [2] Auto CMD12 Enable */
00437         uint32_t RESERVED0 : 1;        /*!< [3]  */
00438         uint32_t DTDSEL : 1;           /*!< [4] Data Transfer Direction Select */
00439         uint32_t MSBSEL : 1;           /*!< [5] Multi/Single Block Select */
00440         uint32_t RESERVED1 : 10;       /*!< [15:6]  */
00441         uint32_t RSPTYP : 2;           /*!< [17:16] Response Type Select */
00442         uint32_t RESERVED2 : 1;        /*!< [18]  */
00443         uint32_t CCCEN : 1;            /*!< [19] Command CRC Check Enable */
00444         uint32_t CICEN : 1;            /*!< [20] Command Index Check Enable */
00445         uint32_t DPSEL : 1;            /*!< [21] Data Present Select */
00446         uint32_t CMDTYP : 2;           /*!< [23:22] Command Type */
00447         uint32_t CMDINX : 6;           /*!< [29:24] Command Index */
00448         uint32_t RESERVED3 : 2;        /*!< [31:30]  */
00449     } B;
00450 } hw_sdhc_xfertyp_t;
00451 
00452 /*!
00453  * @name Constants and macros for entire SDHC_XFERTYP register
00454  */
00455 /*@{*/
00456 #define HW_SDHC_XFERTYP_ADDR(x)  ((x) + 0xCU)
00457 
00458 #define HW_SDHC_XFERTYP(x)       (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR(x))
00459 #define HW_SDHC_XFERTYP_RD(x)    (HW_SDHC_XFERTYP(x).U)
00460 #define HW_SDHC_XFERTYP_WR(x, v) (HW_SDHC_XFERTYP(x).U = (v))
00461 #define HW_SDHC_XFERTYP_SET(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) |  (v)))
00462 #define HW_SDHC_XFERTYP_CLR(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) & ~(v)))
00463 #define HW_SDHC_XFERTYP_TOG(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) ^  (v)))
00464 /*@}*/
00465 
00466 /*
00467  * Constants & macros for individual SDHC_XFERTYP bitfields
00468  */
00469 
00470 /*!
00471  * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
00472  *
00473  * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
00474  * begin when the host driver sets the DPSEL bit of this register. Whether the
00475  * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
00476  *
00477  * Values:
00478  * - 0 - Disable
00479  * - 1 - Enable
00480  */
00481 /*@{*/
00482 #define BP_SDHC_XFERTYP_DMAEN (0U)         /*!< Bit position for SDHC_XFERTYP_DMAEN. */
00483 #define BM_SDHC_XFERTYP_DMAEN (0x00000001U) /*!< Bit mask for SDHC_XFERTYP_DMAEN. */
00484 #define BS_SDHC_XFERTYP_DMAEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_DMAEN. */
00485 
00486 /*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
00487 #define BR_SDHC_XFERTYP_DMAEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN))
00488 
00489 /*! @brief Format value for bitfield SDHC_XFERTYP_DMAEN. */
00490 #define BF_SDHC_XFERTYP_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DMAEN) & BM_SDHC_XFERTYP_DMAEN)
00491 
00492 /*! @brief Set the DMAEN field to a new value. */
00493 #define BW_SDHC_XFERTYP_DMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN) = (v))
00494 /*@}*/
00495 
00496 /*!
00497  * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
00498  *
00499  * Used to enable the Block Count register, which is only relevant for multiple
00500  * block transfers. When this bit is 0, the internal counter for block is
00501  * disabled, which is useful in executing an infinite transfer.
00502  *
00503  * Values:
00504  * - 0 - Disable
00505  * - 1 - Enable
00506  */
00507 /*@{*/
00508 #define BP_SDHC_XFERTYP_BCEN (1U)          /*!< Bit position for SDHC_XFERTYP_BCEN. */
00509 #define BM_SDHC_XFERTYP_BCEN (0x00000002U) /*!< Bit mask for SDHC_XFERTYP_BCEN. */
00510 #define BS_SDHC_XFERTYP_BCEN (1U)          /*!< Bit field size in bits for SDHC_XFERTYP_BCEN. */
00511 
00512 /*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
00513 #define BR_SDHC_XFERTYP_BCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN))
00514 
00515 /*! @brief Format value for bitfield SDHC_XFERTYP_BCEN. */
00516 #define BF_SDHC_XFERTYP_BCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_BCEN) & BM_SDHC_XFERTYP_BCEN)
00517 
00518 /*! @brief Set the BCEN field to a new value. */
00519 #define BW_SDHC_XFERTYP_BCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN) = (v))
00520 /*@}*/
00521 
00522 /*!
00523  * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
00524  *
00525  * Multiple block transfers for memory require a CMD12 to stop the transaction.
00526  * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
00527  * last block transfer has completed. The host driver shall not set this bit to
00528  * issue commands that do not require CMD12 to stop a multiple block data
00529  * transfer. In particular, secure commands defined in File Security Specification (see
00530  * reference list) do not require CMD12. In single block transfer, the SDHC will
00531  * ignore this bit whether it is set or not.
00532  *
00533  * Values:
00534  * - 0 - Disable
00535  * - 1 - Enable
00536  */
00537 /*@{*/
00538 #define BP_SDHC_XFERTYP_AC12EN (2U)        /*!< Bit position for SDHC_XFERTYP_AC12EN. */
00539 #define BM_SDHC_XFERTYP_AC12EN (0x00000004U) /*!< Bit mask for SDHC_XFERTYP_AC12EN. */
00540 #define BS_SDHC_XFERTYP_AC12EN (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_AC12EN. */
00541 
00542 /*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
00543 #define BR_SDHC_XFERTYP_AC12EN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN))
00544 
00545 /*! @brief Format value for bitfield SDHC_XFERTYP_AC12EN. */
00546 #define BF_SDHC_XFERTYP_AC12EN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_AC12EN) & BM_SDHC_XFERTYP_AC12EN)
00547 
00548 /*! @brief Set the AC12EN field to a new value. */
00549 #define BW_SDHC_XFERTYP_AC12EN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN) = (v))
00550 /*@}*/
00551 
00552 /*!
00553  * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
00554  *
00555  * Defines the direction of DAT line data transfers. The bit is set to 1 by the
00556  * host driver to transfer data from the SD card to the SDHC and is set to 0 for
00557  * all other commands.
00558  *
00559  * Values:
00560  * - 0 - Write host to card.
00561  * - 1 - Read card to host.
00562  */
00563 /*@{*/
00564 #define BP_SDHC_XFERTYP_DTDSEL (4U)        /*!< Bit position for SDHC_XFERTYP_DTDSEL. */
00565 #define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) /*!< Bit mask for SDHC_XFERTYP_DTDSEL. */
00566 #define BS_SDHC_XFERTYP_DTDSEL (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_DTDSEL. */
00567 
00568 /*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
00569 #define BR_SDHC_XFERTYP_DTDSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL))
00570 
00571 /*! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL. */
00572 #define BF_SDHC_XFERTYP_DTDSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DTDSEL) & BM_SDHC_XFERTYP_DTDSEL)
00573 
00574 /*! @brief Set the DTDSEL field to a new value. */
00575 #define BW_SDHC_XFERTYP_DTDSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL) = (v))
00576 /*@}*/
00577 
00578 /*!
00579  * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
00580  *
00581  * Enables multiple block DAT line data transfers. For any other commands, this
00582  * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
00583  * count register.
00584  *
00585  * Values:
00586  * - 0 - Single block.
00587  * - 1 - Multiple blocks.
00588  */
00589 /*@{*/
00590 #define BP_SDHC_XFERTYP_MSBSEL (5U)        /*!< Bit position for SDHC_XFERTYP_MSBSEL. */
00591 #define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) /*!< Bit mask for SDHC_XFERTYP_MSBSEL. */
00592 #define BS_SDHC_XFERTYP_MSBSEL (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_MSBSEL. */
00593 
00594 /*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
00595 #define BR_SDHC_XFERTYP_MSBSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL))
00596 
00597 /*! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL. */
00598 #define BF_SDHC_XFERTYP_MSBSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_MSBSEL) & BM_SDHC_XFERTYP_MSBSEL)
00599 
00600 /*! @brief Set the MSBSEL field to a new value. */
00601 #define BW_SDHC_XFERTYP_MSBSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL) = (v))
00602 /*@}*/
00603 
00604 /*!
00605  * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
00606  *
00607  * Values:
00608  * - 00 - No response.
00609  * - 01 - Response length 136.
00610  * - 10 - Response length 48.
00611  * - 11 - Response length 48, check busy after response.
00612  */
00613 /*@{*/
00614 #define BP_SDHC_XFERTYP_RSPTYP (16U)       /*!< Bit position for SDHC_XFERTYP_RSPTYP. */
00615 #define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) /*!< Bit mask for SDHC_XFERTYP_RSPTYP. */
00616 #define BS_SDHC_XFERTYP_RSPTYP (2U)        /*!< Bit field size in bits for SDHC_XFERTYP_RSPTYP. */
00617 
00618 /*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
00619 #define BR_SDHC_XFERTYP_RSPTYP(x) (HW_SDHC_XFERTYP(x).B.RSPTYP)
00620 
00621 /*! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP. */
00622 #define BF_SDHC_XFERTYP_RSPTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
00623 
00624 /*! @brief Set the RSPTYP field to a new value. */
00625 #define BW_SDHC_XFERTYP_RSPTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
00626 /*@}*/
00627 
00628 /*!
00629  * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
00630  *
00631  * If this bit is set to 1, the SDHC shall check the CRC field in the response.
00632  * If an error is detected, it is reported as a Command CRC Error. If this bit is
00633  * set to 0, the CRC field is not checked. The number of bits checked by the CRC
00634  * field value changes according to the length of the response.
00635  *
00636  * Values:
00637  * - 0 - Disable
00638  * - 1 - Enable
00639  */
00640 /*@{*/
00641 #define BP_SDHC_XFERTYP_CCCEN (19U)        /*!< Bit position for SDHC_XFERTYP_CCCEN. */
00642 #define BM_SDHC_XFERTYP_CCCEN (0x00080000U) /*!< Bit mask for SDHC_XFERTYP_CCCEN. */
00643 #define BS_SDHC_XFERTYP_CCCEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_CCCEN. */
00644 
00645 /*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
00646 #define BR_SDHC_XFERTYP_CCCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN))
00647 
00648 /*! @brief Format value for bitfield SDHC_XFERTYP_CCCEN. */
00649 #define BF_SDHC_XFERTYP_CCCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CCCEN) & BM_SDHC_XFERTYP_CCCEN)
00650 
00651 /*! @brief Set the CCCEN field to a new value. */
00652 #define BW_SDHC_XFERTYP_CCCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN) = (v))
00653 /*@}*/
00654 
00655 /*!
00656  * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
00657  *
00658  * If this bit is set to 1, the SDHC will check the index field in the response
00659  * to see if it has the same value as the command index. If it is not, it is
00660  * reported as a command index error. If this bit is set to 0, the index field is not
00661  * checked.
00662  *
00663  * Values:
00664  * - 0 - Disable
00665  * - 1 - Enable
00666  */
00667 /*@{*/
00668 #define BP_SDHC_XFERTYP_CICEN (20U)        /*!< Bit position for SDHC_XFERTYP_CICEN. */
00669 #define BM_SDHC_XFERTYP_CICEN (0x00100000U) /*!< Bit mask for SDHC_XFERTYP_CICEN. */
00670 #define BS_SDHC_XFERTYP_CICEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_CICEN. */
00671 
00672 /*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
00673 #define BR_SDHC_XFERTYP_CICEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN))
00674 
00675 /*! @brief Format value for bitfield SDHC_XFERTYP_CICEN. */
00676 #define BF_SDHC_XFERTYP_CICEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CICEN) & BM_SDHC_XFERTYP_CICEN)
00677 
00678 /*! @brief Set the CICEN field to a new value. */
00679 #define BW_SDHC_XFERTYP_CICEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN) = (v))
00680 /*@}*/
00681 
00682 /*!
00683  * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
00684  *
00685  * This bit is set to 1 to indicate that data is present and shall be
00686  * transferred using the DAT line. It is set to 0 for the following: Commands using only
00687  * the CMD line, for example: CMD52. Commands with no data transfer, but using the
00688  * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
00689  * this bit shall be set, and other bits in this register shall be set the same
00690  * as when the transfer was initially launched. When the Write Protect switch is
00691  * on, that is, the WPSPL bit is active as 0, any command with a write operation
00692  * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
00693  * 0, writes to the register Transfer Type are ignored.
00694  *
00695  * Values:
00696  * - 0 - No data present.
00697  * - 1 - Data present.
00698  */
00699 /*@{*/
00700 #define BP_SDHC_XFERTYP_DPSEL (21U)        /*!< Bit position for SDHC_XFERTYP_DPSEL. */
00701 #define BM_SDHC_XFERTYP_DPSEL (0x00200000U) /*!< Bit mask for SDHC_XFERTYP_DPSEL. */
00702 #define BS_SDHC_XFERTYP_DPSEL (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_DPSEL. */
00703 
00704 /*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
00705 #define BR_SDHC_XFERTYP_DPSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL))
00706 
00707 /*! @brief Format value for bitfield SDHC_XFERTYP_DPSEL. */
00708 #define BF_SDHC_XFERTYP_DPSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DPSEL) & BM_SDHC_XFERTYP_DPSEL)
00709 
00710 /*! @brief Set the DPSEL field to a new value. */
00711 #define BW_SDHC_XFERTYP_DPSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL) = (v))
00712 /*@}*/
00713 
00714 /*!
00715  * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
00716  *
00717  * There are three types of special commands: suspend, resume, and abort. These
00718  * bits shall be set to 00b for all other commands. Suspend command: If the
00719  * suspend command succeeds, the SDHC shall assume that the card bus has been released
00720  * and that it is possible to issue the next command which uses the DAT line.
00721  * Because the SDHC does not monitor the content of command response, it does not
00722  * know if the suspend command succeeded or not. It is the host driver's
00723  * responsibility to check the status of the suspend command and send another command
00724  * marked as suspend to inform the SDHC that a suspend command was successfully
00725  * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
00726  * transactions and stops checking busy for write transactions. In 4-bit mode,
00727  * the interrupt cycle starts. If the suspend command fails, the SDHC will
00728  * maintain its current state, and the host driver shall restart the transfer by setting
00729  * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
00730  * restoring the registers saved before sending the suspend command and then sends
00731  * the resume command. The SDHC will check for a pending busy state before
00732  * starting write transfers. Abort command: If this command is set when executing a
00733  * read transfer, the SDHC will stop reads to the buffer. If this command is set
00734  * when executing a write transfer, the SDHC will stop driving the DAT line. After
00735  * issuing the abort command, the host driver must issue a software reset (abort
00736  * transaction).
00737  *
00738  * Values:
00739  * - 00 - Normal other commands.
00740  * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
00741  * - 10 - Resume CMD52 for writing function select in CCCR.
00742  * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
00743  */
00744 /*@{*/
00745 #define BP_SDHC_XFERTYP_CMDTYP (22U)       /*!< Bit position for SDHC_XFERTYP_CMDTYP. */
00746 #define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) /*!< Bit mask for SDHC_XFERTYP_CMDTYP. */
00747 #define BS_SDHC_XFERTYP_CMDTYP (2U)        /*!< Bit field size in bits for SDHC_XFERTYP_CMDTYP. */
00748 
00749 /*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
00750 #define BR_SDHC_XFERTYP_CMDTYP(x) (HW_SDHC_XFERTYP(x).B.CMDTYP)
00751 
00752 /*! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP. */
00753 #define BF_SDHC_XFERTYP_CMDTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDTYP) & BM_SDHC_XFERTYP_CMDTYP)
00754 
00755 /*! @brief Set the CMDTYP field to a new value. */
00756 #define BW_SDHC_XFERTYP_CMDTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
00757 /*@}*/
00758 
00759 /*!
00760  * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
00761  *
00762  * These bits shall be set to the command number that is specified in bits 45-40
00763  * of the command-format in the SD Memory Card Physical Layer Specification and
00764  * SDIO Card Specification.
00765  */
00766 /*@{*/
00767 #define BP_SDHC_XFERTYP_CMDINX (24U)       /*!< Bit position for SDHC_XFERTYP_CMDINX. */
00768 #define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) /*!< Bit mask for SDHC_XFERTYP_CMDINX. */
00769 #define BS_SDHC_XFERTYP_CMDINX (6U)        /*!< Bit field size in bits for SDHC_XFERTYP_CMDINX. */
00770 
00771 /*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
00772 #define BR_SDHC_XFERTYP_CMDINX(x) (HW_SDHC_XFERTYP(x).B.CMDINX)
00773 
00774 /*! @brief Format value for bitfield SDHC_XFERTYP_CMDINX. */
00775 #define BF_SDHC_XFERTYP_CMDINX(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX)
00776 
00777 /*! @brief Set the CMDINX field to a new value. */
00778 #define BW_SDHC_XFERTYP_CMDINX(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
00779 /*@}*/
00780 
00781 /*******************************************************************************
00782  * HW_SDHC_CMDRSP0 - Command Response 0
00783  ******************************************************************************/
00784 
00785 /*!
00786  * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
00787  *
00788  * Reset value: 0x00000000U
00789  *
00790  * This register is used to store part 0 of the response bits from the card.
00791  */
00792 typedef union _hw_sdhc_cmdrsp0
00793 {
00794     uint32_t U;
00795     struct _hw_sdhc_cmdrsp0_bitfields
00796     {
00797         uint32_t CMDRSP0 : 32;         /*!< [31:0] Command Response 0 */
00798     } B;
00799 } hw_sdhc_cmdrsp0_t;
00800 
00801 /*!
00802  * @name Constants and macros for entire SDHC_CMDRSP0 register
00803  */
00804 /*@{*/
00805 #define HW_SDHC_CMDRSP0_ADDR(x)  ((x) + 0x10U)
00806 
00807 #define HW_SDHC_CMDRSP0(x)       (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR(x))
00808 #define HW_SDHC_CMDRSP0_RD(x)    (HW_SDHC_CMDRSP0(x).U)
00809 /*@}*/
00810 
00811 /*
00812  * Constants & macros for individual SDHC_CMDRSP0 bitfields
00813  */
00814 
00815 /*!
00816  * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
00817  */
00818 /*@{*/
00819 #define BP_SDHC_CMDRSP0_CMDRSP0 (0U)       /*!< Bit position for SDHC_CMDRSP0_CMDRSP0. */
00820 #define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP0_CMDRSP0. */
00821 #define BS_SDHC_CMDRSP0_CMDRSP0 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0. */
00822 
00823 /*! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field. */
00824 #define BR_SDHC_CMDRSP0_CMDRSP0(x) (HW_SDHC_CMDRSP0(x).U)
00825 /*@}*/
00826 
00827 /*******************************************************************************
00828  * HW_SDHC_CMDRSP1 - Command Response 1
00829  ******************************************************************************/
00830 
00831 /*!
00832  * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
00833  *
00834  * Reset value: 0x00000000U
00835  *
00836  * This register is used to store part 1 of the response bits from the card.
00837  */
00838 typedef union _hw_sdhc_cmdrsp1
00839 {
00840     uint32_t U;
00841     struct _hw_sdhc_cmdrsp1_bitfields
00842     {
00843         uint32_t CMDRSP1 : 32;         /*!< [31:0] Command Response 1 */
00844     } B;
00845 } hw_sdhc_cmdrsp1_t;
00846 
00847 /*!
00848  * @name Constants and macros for entire SDHC_CMDRSP1 register
00849  */
00850 /*@{*/
00851 #define HW_SDHC_CMDRSP1_ADDR(x)  ((x) + 0x14U)
00852 
00853 #define HW_SDHC_CMDRSP1(x)       (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR(x))
00854 #define HW_SDHC_CMDRSP1_RD(x)    (HW_SDHC_CMDRSP1(x).U)
00855 /*@}*/
00856 
00857 /*
00858  * Constants & macros for individual SDHC_CMDRSP1 bitfields
00859  */
00860 
00861 /*!
00862  * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
00863  */
00864 /*@{*/
00865 #define BP_SDHC_CMDRSP1_CMDRSP1 (0U)       /*!< Bit position for SDHC_CMDRSP1_CMDRSP1. */
00866 #define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP1_CMDRSP1. */
00867 #define BS_SDHC_CMDRSP1_CMDRSP1 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1. */
00868 
00869 /*! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field. */
00870 #define BR_SDHC_CMDRSP1_CMDRSP1(x) (HW_SDHC_CMDRSP1(x).U)
00871 /*@}*/
00872 
00873 /*******************************************************************************
00874  * HW_SDHC_CMDRSP2 - Command Response 2
00875  ******************************************************************************/
00876 
00877 /*!
00878  * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
00879  *
00880  * Reset value: 0x00000000U
00881  *
00882  * This register is used to store part 2 of the response bits from the card.
00883  */
00884 typedef union _hw_sdhc_cmdrsp2
00885 {
00886     uint32_t U;
00887     struct _hw_sdhc_cmdrsp2_bitfields
00888     {
00889         uint32_t CMDRSP2 : 32;         /*!< [31:0] Command Response 2 */
00890     } B;
00891 } hw_sdhc_cmdrsp2_t;
00892 
00893 /*!
00894  * @name Constants and macros for entire SDHC_CMDRSP2 register
00895  */
00896 /*@{*/
00897 #define HW_SDHC_CMDRSP2_ADDR(x)  ((x) + 0x18U)
00898 
00899 #define HW_SDHC_CMDRSP2(x)       (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR(x))
00900 #define HW_SDHC_CMDRSP2_RD(x)    (HW_SDHC_CMDRSP2(x).U)
00901 /*@}*/
00902 
00903 /*
00904  * Constants & macros for individual SDHC_CMDRSP2 bitfields
00905  */
00906 
00907 /*!
00908  * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
00909  */
00910 /*@{*/
00911 #define BP_SDHC_CMDRSP2_CMDRSP2 (0U)       /*!< Bit position for SDHC_CMDRSP2_CMDRSP2. */
00912 #define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP2_CMDRSP2. */
00913 #define BS_SDHC_CMDRSP2_CMDRSP2 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2. */
00914 
00915 /*! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field. */
00916 #define BR_SDHC_CMDRSP2_CMDRSP2(x) (HW_SDHC_CMDRSP2(x).U)
00917 /*@}*/
00918 
00919 /*******************************************************************************
00920  * HW_SDHC_CMDRSP3 - Command Response 3
00921  ******************************************************************************/
00922 
00923 /*!
00924  * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
00925  *
00926  * Reset value: 0x00000000U
00927  *
00928  * This register is used to store part 3 of the response bits from the card. The
00929  * following table describes the mapping of command responses from the SD bus to
00930  * command response registers for each response type. In the table, R[ ] refers
00931  * to a bit range within the response data as transmitted on the SD bus. Response
00932  * bit definition for each response type Response type Meaning of response
00933  * Response field Response register R1,R1b (normal response) Card status R[39:8]
00934  * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
00935  * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
00936  * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
00937  * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
00938  * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
00939  * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
00940  * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
00941  * register. Responses of type R1b (auto CMD12 responses) have response data bits
00942  * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
00943  * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
00944  * registers. To be able to read the response status efficiently, the SDHC stores
00945  * only a part of the response data in the command response registers. This
00946  * enables the host driver to efficiently read 32-bit of response data in one read
00947  * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
00948  * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
00949  * and generate an error interrupt if any error is detected. The bit range for the
00950  * CRC check depends on the response length. If the response length is 48, the
00951  * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
00952  * R[119:1]. Because the SDHC may have a multiple block data transfer executing
00953  * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
00954  * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
00955  * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
00956  * and vice versa. When the SDHC modifies part of the command response
00957  * registers, as shown in the table above, it preserves the unmodified bits.
00958  */
00959 typedef union _hw_sdhc_cmdrsp3
00960 {
00961     uint32_t U;
00962     struct _hw_sdhc_cmdrsp3_bitfields
00963     {
00964         uint32_t CMDRSP3 : 32;         /*!< [31:0] Command Response 3 */
00965     } B;
00966 } hw_sdhc_cmdrsp3_t;
00967 
00968 /*!
00969  * @name Constants and macros for entire SDHC_CMDRSP3 register
00970  */
00971 /*@{*/
00972 #define HW_SDHC_CMDRSP3_ADDR(x)  ((x) + 0x1CU)
00973 
00974 #define HW_SDHC_CMDRSP3(x)       (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR(x))
00975 #define HW_SDHC_CMDRSP3_RD(x)    (HW_SDHC_CMDRSP3(x).U)
00976 /*@}*/
00977 
00978 /*
00979  * Constants & macros for individual SDHC_CMDRSP3 bitfields
00980  */
00981 
00982 /*!
00983  * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
00984  */
00985 /*@{*/
00986 #define BP_SDHC_CMDRSP3_CMDRSP3 (0U)       /*!< Bit position for SDHC_CMDRSP3_CMDRSP3. */
00987 #define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP3_CMDRSP3. */
00988 #define BS_SDHC_CMDRSP3_CMDRSP3 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3. */
00989 
00990 /*! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field. */
00991 #define BR_SDHC_CMDRSP3_CMDRSP3(x) (HW_SDHC_CMDRSP3(x).U)
00992 /*@}*/
00993 
00994 /*******************************************************************************
00995  * HW_SDHC_DATPORT - Buffer Data Port register
00996  ******************************************************************************/
00997 
00998 /*!
00999  * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
01000  *
01001  * Reset value: 0x00000000U
01002  *
01003  * This is a 32-bit data port register used to access the internal buffer and it
01004  * cannot be updated in Idle mode.
01005  */
01006 typedef union _hw_sdhc_datport
01007 {
01008     uint32_t U;
01009     struct _hw_sdhc_datport_bitfields
01010     {
01011         uint32_t DATCONT : 32;         /*!< [31:0] Data Content */
01012     } B;
01013 } hw_sdhc_datport_t;
01014 
01015 /*!
01016  * @name Constants and macros for entire SDHC_DATPORT register
01017  */
01018 /*@{*/
01019 #define HW_SDHC_DATPORT_ADDR(x)  ((x) + 0x20U)
01020 
01021 #define HW_SDHC_DATPORT(x)       (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR(x))
01022 #define HW_SDHC_DATPORT_RD(x)    (HW_SDHC_DATPORT(x).U)
01023 #define HW_SDHC_DATPORT_WR(x, v) (HW_SDHC_DATPORT(x).U = (v))
01024 #define HW_SDHC_DATPORT_SET(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) |  (v)))
01025 #define HW_SDHC_DATPORT_CLR(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) & ~(v)))
01026 #define HW_SDHC_DATPORT_TOG(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) ^  (v)))
01027 /*@}*/
01028 
01029 /*
01030  * Constants & macros for individual SDHC_DATPORT bitfields
01031  */
01032 
01033 /*!
01034  * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
01035  *
01036  * The Buffer Data Port register is for 32-bit data access by the CPU or the
01037  * external DMA. When the internal DMA is enabled, any write to this register is
01038  * ignored, and any read from this register will always yield 0s.
01039  */
01040 /*@{*/
01041 #define BP_SDHC_DATPORT_DATCONT (0U)       /*!< Bit position for SDHC_DATPORT_DATCONT. */
01042 #define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) /*!< Bit mask for SDHC_DATPORT_DATCONT. */
01043 #define BS_SDHC_DATPORT_DATCONT (32U)      /*!< Bit field size in bits for SDHC_DATPORT_DATCONT. */
01044 
01045 /*! @brief Read current value of the SDHC_DATPORT_DATCONT field. */
01046 #define BR_SDHC_DATPORT_DATCONT(x) (HW_SDHC_DATPORT(x).U)
01047 
01048 /*! @brief Format value for bitfield SDHC_DATPORT_DATCONT. */
01049 #define BF_SDHC_DATPORT_DATCONT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DATPORT_DATCONT) & BM_SDHC_DATPORT_DATCONT)
01050 
01051 /*! @brief Set the DATCONT field to a new value. */
01052 #define BW_SDHC_DATPORT_DATCONT(x, v) (HW_SDHC_DATPORT_WR(x, v))
01053 /*@}*/
01054 
01055 /*******************************************************************************
01056  * HW_SDHC_PRSSTAT - Present State register
01057  ******************************************************************************/
01058 
01059 /*!
01060  * @brief HW_SDHC_PRSSTAT - Present State register (RO)
01061  *
01062  * Reset value: 0x00000000U
01063  *
01064  * The host driver can get status of the SDHC from this 32-bit read-only
01065  * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
01066  * SDIO) when the DAT lines are busy during a data transfer. These commands can be
01067  * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
01068  * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
01069  * Physical Specification may add other commands to this list in the future.
01070  */
01071 typedef union _hw_sdhc_prsstat
01072 {
01073     uint32_t U;
01074     struct _hw_sdhc_prsstat_bitfields
01075     {
01076         uint32_t CIHB : 1;             /*!< [0] Command Inhibit (CMD) */
01077         uint32_t CDIHB : 1;            /*!< [1] Command Inhibit (DAT) */
01078         uint32_t DLA : 1;              /*!< [2] Data Line Active */
01079         uint32_t SDSTB : 1;            /*!< [3] SD Clock Stable */
01080         uint32_t IPGOFF : 1;           /*!< [4] Bus Clock Gated Off Internally */
01081         uint32_t HCKOFF : 1;           /*!< [5] System Clock Gated Off Internally */
01082         uint32_t PEROFF : 1;           /*!< [6] SDHC clock Gated Off Internally */
01083         uint32_t SDOFF : 1;            /*!< [7] SD Clock Gated Off Internally */
01084         uint32_t WTA : 1;              /*!< [8] Write Transfer Active */
01085         uint32_t RTA : 1;              /*!< [9] Read Transfer Active */
01086         uint32_t BWEN : 1;             /*!< [10] Buffer Write Enable */
01087         uint32_t BREN : 1;             /*!< [11] Buffer Read Enable */
01088         uint32_t RESERVED0 : 4;        /*!< [15:12]  */
01089         uint32_t CINS : 1;             /*!< [16] Card Inserted */
01090         uint32_t RESERVED1 : 6;        /*!< [22:17]  */
01091         uint32_t CLSL : 1;             /*!< [23] CMD Line Signal Level */
01092         uint32_t DLSL : 8;             /*!< [31:24] DAT Line Signal Level */
01093     } B;
01094 } hw_sdhc_prsstat_t;
01095 
01096 /*!
01097  * @name Constants and macros for entire SDHC_PRSSTAT register
01098  */
01099 /*@{*/
01100 #define HW_SDHC_PRSSTAT_ADDR(x)  ((x) + 0x24U)
01101 
01102 #define HW_SDHC_PRSSTAT(x)       (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR(x))
01103 #define HW_SDHC_PRSSTAT_RD(x)    (HW_SDHC_PRSSTAT(x).U)
01104 /*@}*/
01105 
01106 /*
01107  * Constants & macros for individual SDHC_PRSSTAT bitfields
01108  */
01109 
01110 /*!
01111  * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
01112  *
01113  * If this status bit is 0, it indicates that the CMD line is not in use and the
01114  * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
01115  * immediately after the Transfer Type register is written. This bit is cleared when
01116  * the command response is received. Even if the CDIHB bit is set to 1, Commands
01117  * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
01118  * generates a command complete interrupt in the interrupt status register. If the
01119  * SDHC cannot issue the command because of a command conflict error (see
01120  * command CRC error) or because of a command not issued by auto CMD12 error, this bit
01121  * will remain 1 and the command complete is not set. The status of issuing an
01122  * auto CMD12 does not show on this bit.
01123  *
01124  * Values:
01125  * - 0 - Can issue command using only CMD line.
01126  * - 1 - Cannot issue command.
01127  */
01128 /*@{*/
01129 #define BP_SDHC_PRSSTAT_CIHB (0U)          /*!< Bit position for SDHC_PRSSTAT_CIHB. */
01130 #define BM_SDHC_PRSSTAT_CIHB (0x00000001U) /*!< Bit mask for SDHC_PRSSTAT_CIHB. */
01131 #define BS_SDHC_PRSSTAT_CIHB (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CIHB. */
01132 
01133 /*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
01134 #define BR_SDHC_PRSSTAT_CIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CIHB))
01135 /*@}*/
01136 
01137 /*!
01138  * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
01139  *
01140  * This status bit is generated if either the DLA or the RTA is set to 1. If
01141  * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
01142  * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
01143  * the case when the command busy is finished, changing from 1 to 0 generates a
01144  * transfer complete interrupt in the Interrupt Status register. The SD host
01145  * driver can save registers for a suspend transaction after this bit has changed
01146  * from 1 to 0.
01147  *
01148  * Values:
01149  * - 0 - Can issue command which uses the DAT line.
01150  * - 1 - Cannot issue command which uses the DAT line.
01151  */
01152 /*@{*/
01153 #define BP_SDHC_PRSSTAT_CDIHB (1U)         /*!< Bit position for SDHC_PRSSTAT_CDIHB. */
01154 #define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) /*!< Bit mask for SDHC_PRSSTAT_CDIHB. */
01155 #define BS_SDHC_PRSSTAT_CDIHB (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_CDIHB. */
01156 
01157 /*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
01158 #define BR_SDHC_PRSSTAT_CDIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CDIHB))
01159 /*@}*/
01160 
01161 /*!
01162  * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
01163  *
01164  * Indicates whether one of the DAT lines on the SD bus is in use. In the case
01165  * of read transactions: This status indicates whether a read transfer is
01166  * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
01167  * generates a block gap event interrupt in the Interrupt Status register. This bit
01168  * will be set in either of the following cases: After the end bit of the read
01169  * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
01170  * will be cleared in either of the following cases: When the end bit of the last
01171  * data block is sent from the SD bus to the SDHC. When the read wait state is
01172  * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
01173  * the next block gap by driving read wait at the start of the interrupt cycle.
01174  * If the read wait signal is already driven (data buffer cannot receive data),
01175  * the SDHC can wait for a current block gap by continuing to drive the read wait
01176  * signal. It is necessary to support read wait to use the suspend / resume
01177  * function. This bit will remain 1 during read wait. In the case of write
01178  * transactions: This status indicates that a write transfer is executing on the SD bus.
01179  * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
01180  * interrupt status register. This bit will be set in either of the following
01181  * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
01182  * continue a write transfer. This bit will be cleared in either of the
01183  * following cases: When the SD card releases write busy of the last data block, the SDHC
01184  * will also detect if the output is not busy. If the SD card does not drive the
01185  * busy signal after the CRC status is received, the SDHC shall assume the card
01186  * drive "Not busy". When the SD card releases write busy, prior to waiting for
01187  * write transfer, and as a result of a stop at block gap request. In the case of
01188  * command with busy pending: This status indicates that a busy state follows the
01189  * command and the data line is in use. This bit will be cleared when the DAT0
01190  * line is released.
01191  *
01192  * Values:
01193  * - 0 - DAT line inactive.
01194  * - 1 - DAT line active.
01195  */
01196 /*@{*/
01197 #define BP_SDHC_PRSSTAT_DLA  (2U)          /*!< Bit position for SDHC_PRSSTAT_DLA. */
01198 #define BM_SDHC_PRSSTAT_DLA  (0x00000004U) /*!< Bit mask for SDHC_PRSSTAT_DLA. */
01199 #define BS_SDHC_PRSSTAT_DLA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_DLA. */
01200 
01201 /*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
01202 #define BR_SDHC_PRSSTAT_DLA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_DLA))
01203 /*@}*/
01204 
01205 /*!
01206  * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
01207  *
01208  * Indicates that the internal card clock is stable. This bit is for the host
01209  * driver to poll clock status when changing the clock frequency. It is recommended
01210  * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
01211  * frequency is changing.
01212  *
01213  * Values:
01214  * - 0 - Clock is changing frequency and not stable.
01215  * - 1 - Clock is stable.
01216  */
01217 /*@{*/
01218 #define BP_SDHC_PRSSTAT_SDSTB (3U)         /*!< Bit position for SDHC_PRSSTAT_SDSTB. */
01219 #define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) /*!< Bit mask for SDHC_PRSSTAT_SDSTB. */
01220 #define BS_SDHC_PRSSTAT_SDSTB (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_SDSTB. */
01221 
01222 /*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
01223 #define BR_SDHC_PRSSTAT_SDSTB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDSTB))
01224 /*@}*/
01225 
01226 /*!
01227  * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
01228  *
01229  * Indicates that the bus clock is internally gated off. This bit is for the
01230  * host driver to debug.
01231  *
01232  * Values:
01233  * - 0 - Bus clock is active.
01234  * - 1 - Bus clock is gated off.
01235  */
01236 /*@{*/
01237 #define BP_SDHC_PRSSTAT_IPGOFF (4U)        /*!< Bit position for SDHC_PRSSTAT_IPGOFF. */
01238 #define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) /*!< Bit mask for SDHC_PRSSTAT_IPGOFF. */
01239 #define BS_SDHC_PRSSTAT_IPGOFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF. */
01240 
01241 /*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
01242 #define BR_SDHC_PRSSTAT_IPGOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_IPGOFF))
01243 /*@}*/
01244 
01245 /*!
01246  * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
01247  *
01248  * Indicates that the system clock is internally gated off. This bit is for the
01249  * host driver to debug during a data transfer.
01250  *
01251  * Values:
01252  * - 0 - System clock is active.
01253  * - 1 - System clock is gated off.
01254  */
01255 /*@{*/
01256 #define BP_SDHC_PRSSTAT_HCKOFF (5U)        /*!< Bit position for SDHC_PRSSTAT_HCKOFF. */
01257 #define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) /*!< Bit mask for SDHC_PRSSTAT_HCKOFF. */
01258 #define BS_SDHC_PRSSTAT_HCKOFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF. */
01259 
01260 /*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
01261 #define BR_SDHC_PRSSTAT_HCKOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_HCKOFF))
01262 /*@}*/
01263 
01264 /*!
01265  * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
01266  *
01267  * Indicates that the is internally gated off. This bit is for the host driver
01268  * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
01269  * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
01270  * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
01271  * clock SDHC clock bus clock
01272  *
01273  * Values:
01274  * - 0 - SDHC clock is active.
01275  * - 1 - SDHC clock is gated off.
01276  */
01277 /*@{*/
01278 #define BP_SDHC_PRSSTAT_PEROFF (6U)        /*!< Bit position for SDHC_PRSSTAT_PEROFF. */
01279 #define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) /*!< Bit mask for SDHC_PRSSTAT_PEROFF. */
01280 #define BS_SDHC_PRSSTAT_PEROFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_PEROFF. */
01281 
01282 /*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
01283 #define BR_SDHC_PRSSTAT_PEROFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_PEROFF))
01284 /*@}*/
01285 
01286 /*!
01287  * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
01288  *
01289  * Indicates that the SD clock is internally gated off, because of buffer
01290  * over/under-run or read pause without read wait assertion, or the driver has cleared
01291  * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
01292  * data transaction on the SD bus.
01293  *
01294  * Values:
01295  * - 0 - SD clock is active.
01296  * - 1 - SD clock is gated off.
01297  */
01298 /*@{*/
01299 #define BP_SDHC_PRSSTAT_SDOFF (7U)         /*!< Bit position for SDHC_PRSSTAT_SDOFF. */
01300 #define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) /*!< Bit mask for SDHC_PRSSTAT_SDOFF. */
01301 #define BS_SDHC_PRSSTAT_SDOFF (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_SDOFF. */
01302 
01303 /*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
01304 #define BR_SDHC_PRSSTAT_SDOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDOFF))
01305 /*@}*/
01306 
01307 /*!
01308  * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
01309  *
01310  * Indicates that a write transfer is active. If this bit is 0, it means no
01311  * valid write data exists in the SDHC. This bit is set in either of the following
01312  * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
01313  * restart a write transfer. This bit is cleared in either of the following
01314  * cases: After getting the CRC status of the last data block as specified by the
01315  * transfer count (single and multiple). After getting the CRC status of any block
01316  * where data transmission is about to be stopped by a stop at block gap request.
01317  * During a write transaction, a block gap event interrupt is generated when this
01318  * bit is changed to 0, as result of the stop at block gap request being set.
01319  * This status is useful for the host driver in determining when to issue commands
01320  * during write busy state.
01321  *
01322  * Values:
01323  * - 0 - No valid data.
01324  * - 1 - Transferring data.
01325  */
01326 /*@{*/
01327 #define BP_SDHC_PRSSTAT_WTA  (8U)          /*!< Bit position for SDHC_PRSSTAT_WTA. */
01328 #define BM_SDHC_PRSSTAT_WTA  (0x00000100U) /*!< Bit mask for SDHC_PRSSTAT_WTA. */
01329 #define BS_SDHC_PRSSTAT_WTA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_WTA. */
01330 
01331 /*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
01332 #define BR_SDHC_PRSSTAT_WTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_WTA))
01333 /*@}*/
01334 
01335 /*!
01336  * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
01337  *
01338  * Used for detecting completion of a read transfer. This bit is set for either
01339  * of the following conditions: After the end bit of the read command. When
01340  * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
01341  * interrupt is generated when this bit changes to 0. This bit is cleared for either of
01342  * the following conditions: When the last data block as specified by block
01343  * length is transferred to the system, that is, all data are read away from SDHC
01344  * internal buffer. When all valid data blocks have been transferred from SDHC
01345  * internal buffer to the system and no current block transfers are being sent as a
01346  * result of the stop at block gap request being set to 1.
01347  *
01348  * Values:
01349  * - 0 - No valid data.
01350  * - 1 - Transferring data.
01351  */
01352 /*@{*/
01353 #define BP_SDHC_PRSSTAT_RTA  (9U)          /*!< Bit position for SDHC_PRSSTAT_RTA. */
01354 #define BM_SDHC_PRSSTAT_RTA  (0x00000200U) /*!< Bit mask for SDHC_PRSSTAT_RTA. */
01355 #define BS_SDHC_PRSSTAT_RTA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_RTA. */
01356 
01357 /*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
01358 #define BR_SDHC_PRSSTAT_RTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_RTA))
01359 /*@}*/
01360 
01361 /*!
01362  * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
01363  *
01364  * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
01365  * transfer data efficiently. This read-only flag indicates whether space is
01366  * available for write data. If this bit is 1, valid data greater than the watermark
01367  * level can be written to the buffer. This read-only flag indicates whether
01368  * space is available for write data.
01369  *
01370  * Values:
01371  * - 0 - Write disable, the buffer can hold valid data less than the write
01372  *     watermark level.
01373  * - 1 - Write enable, the buffer can hold valid data greater than the write
01374  *     watermark level.
01375  */
01376 /*@{*/
01377 #define BP_SDHC_PRSSTAT_BWEN (10U)         /*!< Bit position for SDHC_PRSSTAT_BWEN. */
01378 #define BM_SDHC_PRSSTAT_BWEN (0x00000400U) /*!< Bit mask for SDHC_PRSSTAT_BWEN. */
01379 #define BS_SDHC_PRSSTAT_BWEN (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_BWEN. */
01380 
01381 /*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
01382 #define BR_SDHC_PRSSTAT_BWEN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BWEN))
01383 /*@}*/
01384 
01385 /*!
01386  * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
01387  *
01388  * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
01389  * transfer data efficiently. This read-only flag indicates that valid data exists
01390  * in the host side buffer. If this bit is high, valid data greater than the
01391  * watermark level exist in the buffer. This read-only flag indicates that valid
01392  * data exists in the host side buffer.
01393  *
01394  * Values:
01395  * - 0 - Read disable, valid data less than the watermark level exist in the
01396  *     buffer.
01397  * - 1 - Read enable, valid data greater than the watermark level exist in the
01398  *     buffer.
01399  */
01400 /*@{*/
01401 #define BP_SDHC_PRSSTAT_BREN (11U)         /*!< Bit position for SDHC_PRSSTAT_BREN. */
01402 #define BM_SDHC_PRSSTAT_BREN (0x00000800U) /*!< Bit mask for SDHC_PRSSTAT_BREN. */
01403 #define BS_SDHC_PRSSTAT_BREN (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_BREN. */
01404 
01405 /*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
01406 #define BR_SDHC_PRSSTAT_BREN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BREN))
01407 /*@}*/
01408 
01409 /*!
01410  * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
01411  *
01412  * Indicates whether a card has been inserted. The SDHC debounces this signal so
01413  * that the host driver will not need to wait for it to stabilize. Changing from
01414  * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
01415  * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
01416  * Status register. A write to the force event register does not effect this bit.
01417  * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
01418  * bit.
01419  *
01420  * Values:
01421  * - 0 - Power on reset or no card.
01422  * - 1 - Card inserted.
01423  */
01424 /*@{*/
01425 #define BP_SDHC_PRSSTAT_CINS (16U)         /*!< Bit position for SDHC_PRSSTAT_CINS. */
01426 #define BM_SDHC_PRSSTAT_CINS (0x00010000U) /*!< Bit mask for SDHC_PRSSTAT_CINS. */
01427 #define BS_SDHC_PRSSTAT_CINS (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CINS. */
01428 
01429 /*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
01430 #define BR_SDHC_PRSSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CINS))
01431 /*@}*/
01432 
01433 /*!
01434  * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
01435  *
01436  * Used to check the CMD line level to recover from errors, and for debugging.
01437  * The reset value is effected by the external pullup/pulldown resistor, by
01438  * default, the read value of this bit after reset is 1b, when the command line is
01439  * pulled up.
01440  */
01441 /*@{*/
01442 #define BP_SDHC_PRSSTAT_CLSL (23U)         /*!< Bit position for SDHC_PRSSTAT_CLSL. */
01443 #define BM_SDHC_PRSSTAT_CLSL (0x00800000U) /*!< Bit mask for SDHC_PRSSTAT_CLSL. */
01444 #define BS_SDHC_PRSSTAT_CLSL (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CLSL. */
01445 
01446 /*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
01447 #define BR_SDHC_PRSSTAT_CLSL(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CLSL))
01448 /*@}*/
01449 
01450 /*!
01451  * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
01452  *
01453  * Used to check the DAT line level to recover from errors, and for debugging.
01454  * This is especially useful in detecting the busy signal level from DAT[0]. The
01455  * reset value is effected by the external pullup/pulldown resistors. By default,
01456  * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
01457  * down and the other lines are pulled up.
01458  */
01459 /*@{*/
01460 #define BP_SDHC_PRSSTAT_DLSL (24U)         /*!< Bit position for SDHC_PRSSTAT_DLSL. */
01461 #define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) /*!< Bit mask for SDHC_PRSSTAT_DLSL. */
01462 #define BS_SDHC_PRSSTAT_DLSL (8U)          /*!< Bit field size in bits for SDHC_PRSSTAT_DLSL. */
01463 
01464 /*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
01465 #define BR_SDHC_PRSSTAT_DLSL(x) (HW_SDHC_PRSSTAT(x).B.DLSL)
01466 /*@}*/
01467 
01468 /*******************************************************************************
01469  * HW_SDHC_PROCTL - Protocol Control register
01470  ******************************************************************************/
01471 
01472 /*!
01473  * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
01474  *
01475  * Reset value: 0x00000020U
01476  *
01477  * There are three cases to restart the transfer after stop at the block gap.
01478  * Which case is appropriate depends on whether the SDHC issues a suspend command
01479  * or the SD card accepts the suspend command: If the host driver does not issue a
01480  * suspend command, the continue request shall be used to restart the transfer.
01481  * If the host driver issues a suspend command and the SD card accepts it, a
01482  * resume command shall be used to restart the transfer. If the host driver issues a
01483  * suspend command and the SD card does not accept it, the continue request shall
01484  * be used to restart the transfer. Any time stop at block gap request stops the
01485  * data transfer, the host driver shall wait for a transfer complete (in the
01486  * interrupt status register), before attempting to restart the transfer. When
01487  * restarting the data transfer by continue request, the host driver shall clear the
01488  * stop at block gap request before or simultaneously.
01489  */
01490 typedef union _hw_sdhc_proctl
01491 {
01492     uint32_t U;
01493     struct _hw_sdhc_proctl_bitfields
01494     {
01495         uint32_t LCTL : 1;             /*!< [0] LED Control */
01496         uint32_t DTW : 2;              /*!< [2:1] Data Transfer Width */
01497         uint32_t D3CD : 1;             /*!< [3] DAT3 As Card Detection Pin */
01498         uint32_t EMODE : 2;            /*!< [5:4] Endian Mode */
01499         uint32_t CDTL : 1;             /*!< [6] Card Detect Test Level */
01500         uint32_t CDSS : 1;             /*!< [7] Card Detect Signal Selection */
01501         uint32_t DMAS : 2;             /*!< [9:8] DMA Select */
01502         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
01503         uint32_t SABGREQ : 1;          /*!< [16] Stop At Block Gap Request */
01504         uint32_t CREQ : 1;             /*!< [17] Continue Request */
01505         uint32_t RWCTL : 1;            /*!< [18] Read Wait Control */
01506         uint32_t IABG : 1;             /*!< [19] Interrupt At Block Gap */
01507         uint32_t RESERVED1 : 4;        /*!< [23:20]  */
01508         uint32_t WECINT : 1;           /*!< [24] Wakeup Event Enable On Card Interrupt
01509                                         * */
01510         uint32_t WECINS : 1;           /*!< [25] Wakeup Event Enable On SD Card
01511                                         * Insertion */
01512         uint32_t WECRM : 1;            /*!< [26] Wakeup Event Enable On SD Card Removal
01513                                         * */
01514         uint32_t RESERVED2 : 5;        /*!< [31:27]  */
01515     } B;
01516 } hw_sdhc_proctl_t;
01517 
01518 /*!
01519  * @name Constants and macros for entire SDHC_PROCTL register
01520  */
01521 /*@{*/
01522 #define HW_SDHC_PROCTL_ADDR(x)   ((x) + 0x28U)
01523 
01524 #define HW_SDHC_PROCTL(x)        (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR(x))
01525 #define HW_SDHC_PROCTL_RD(x)     (HW_SDHC_PROCTL(x).U)
01526 #define HW_SDHC_PROCTL_WR(x, v)  (HW_SDHC_PROCTL(x).U = (v))
01527 #define HW_SDHC_PROCTL_SET(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) |  (v)))
01528 #define HW_SDHC_PROCTL_CLR(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) & ~(v)))
01529 #define HW_SDHC_PROCTL_TOG(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) ^  (v)))
01530 /*@}*/
01531 
01532 /*
01533  * Constants & macros for individual SDHC_PROCTL bitfields
01534  */
01535 
01536 /*!
01537  * @name Register SDHC_PROCTL, field LCTL[0] (RW)
01538  *
01539  * This bit, fully controlled by the host driver, is used to caution the user
01540  * not to remove the card while the card is being accessed. If the software is
01541  * going to issue multiple SD commands, this bit can be set during all these
01542  * transactions. It is not necessary to change for each transaction. When the software
01543  * issues multiple SD commands, setting the bit once before the first command is
01544  * sufficient: it is not necessary to reset the bit between commands.
01545  *
01546  * Values:
01547  * - 0 - LED off.
01548  * - 1 - LED on.
01549  */
01550 /*@{*/
01551 #define BP_SDHC_PROCTL_LCTL  (0U)          /*!< Bit position for SDHC_PROCTL_LCTL. */
01552 #define BM_SDHC_PROCTL_LCTL  (0x00000001U) /*!< Bit mask for SDHC_PROCTL_LCTL. */
01553 #define BS_SDHC_PROCTL_LCTL  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_LCTL. */
01554 
01555 /*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
01556 #define BR_SDHC_PROCTL_LCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL))
01557 
01558 /*! @brief Format value for bitfield SDHC_PROCTL_LCTL. */
01559 #define BF_SDHC_PROCTL_LCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_LCTL) & BM_SDHC_PROCTL_LCTL)
01560 
01561 /*! @brief Set the LCTL field to a new value. */
01562 #define BW_SDHC_PROCTL_LCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL) = (v))
01563 /*@}*/
01564 
01565 /*!
01566  * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
01567  *
01568  * Selects the data width of the SD bus for a data transfer. The host driver
01569  * shall set it to match the data width of the card. Possible data transfer width is
01570  * 1-bit, 4-bits or 8-bits.
01571  *
01572  * Values:
01573  * - 00 - 1-bit mode
01574  * - 01 - 4-bit mode
01575  * - 10 - 8-bit mode
01576  * - 11 - Reserved
01577  */
01578 /*@{*/
01579 #define BP_SDHC_PROCTL_DTW   (1U)          /*!< Bit position for SDHC_PROCTL_DTW. */
01580 #define BM_SDHC_PROCTL_DTW   (0x00000006U) /*!< Bit mask for SDHC_PROCTL_DTW. */
01581 #define BS_SDHC_PROCTL_DTW   (2U)          /*!< Bit field size in bits for SDHC_PROCTL_DTW. */
01582 
01583 /*! @brief Read current value of the SDHC_PROCTL_DTW field. */
01584 #define BR_SDHC_PROCTL_DTW(x) (HW_SDHC_PROCTL(x).B.DTW)
01585 
01586 /*! @brief Format value for bitfield SDHC_PROCTL_DTW. */
01587 #define BF_SDHC_PROCTL_DTW(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DTW) & BM_SDHC_PROCTL_DTW)
01588 
01589 /*! @brief Set the DTW field to a new value. */
01590 #define BW_SDHC_PROCTL_DTW(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
01591 /*@}*/
01592 
01593 /*!
01594  * @name Register SDHC_PROCTL, field D3CD[3] (RW)
01595  *
01596  * If this bit is set, DAT3 should be pulled down to act as a card detection
01597  * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
01598  * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
01599  * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
01600  * is used.
01601  *
01602  * Values:
01603  * - 0 - DAT3 does not monitor card Insertion.
01604  * - 1 - DAT3 as card detection pin.
01605  */
01606 /*@{*/
01607 #define BP_SDHC_PROCTL_D3CD  (3U)          /*!< Bit position for SDHC_PROCTL_D3CD. */
01608 #define BM_SDHC_PROCTL_D3CD  (0x00000008U) /*!< Bit mask for SDHC_PROCTL_D3CD. */
01609 #define BS_SDHC_PROCTL_D3CD  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_D3CD. */
01610 
01611 /*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
01612 #define BR_SDHC_PROCTL_D3CD(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD))
01613 
01614 /*! @brief Format value for bitfield SDHC_PROCTL_D3CD. */
01615 #define BF_SDHC_PROCTL_D3CD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_D3CD) & BM_SDHC_PROCTL_D3CD)
01616 
01617 /*! @brief Set the D3CD field to a new value. */
01618 #define BW_SDHC_PROCTL_D3CD(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD) = (v))
01619 /*@}*/
01620 
01621 /*!
01622  * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
01623  *
01624  * The SDHC supports all four endian modes in data transfer.
01625  *
01626  * Values:
01627  * - 00 - Big endian mode
01628  * - 01 - Half word big endian mode
01629  * - 10 - Little endian mode
01630  * - 11 - Reserved
01631  */
01632 /*@{*/
01633 #define BP_SDHC_PROCTL_EMODE (4U)          /*!< Bit position for SDHC_PROCTL_EMODE. */
01634 #define BM_SDHC_PROCTL_EMODE (0x00000030U) /*!< Bit mask for SDHC_PROCTL_EMODE. */
01635 #define BS_SDHC_PROCTL_EMODE (2U)          /*!< Bit field size in bits for SDHC_PROCTL_EMODE. */
01636 
01637 /*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
01638 #define BR_SDHC_PROCTL_EMODE(x) (HW_SDHC_PROCTL(x).B.EMODE)
01639 
01640 /*! @brief Format value for bitfield SDHC_PROCTL_EMODE. */
01641 #define BF_SDHC_PROCTL_EMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_EMODE) & BM_SDHC_PROCTL_EMODE)
01642 
01643 /*! @brief Set the EMODE field to a new value. */
01644 #define BW_SDHC_PROCTL_EMODE(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
01645 /*@}*/
01646 
01647 /*!
01648  * @name Register SDHC_PROCTL, field CDTL[6] (RW)
01649  *
01650  * Enabled while the CDSS is set to 1 and it indicates card insertion.
01651  *
01652  * Values:
01653  * - 0 - Card detect test level is 0, no card inserted.
01654  * - 1 - Card detect test level is 1, card inserted.
01655  */
01656 /*@{*/
01657 #define BP_SDHC_PROCTL_CDTL  (6U)          /*!< Bit position for SDHC_PROCTL_CDTL. */
01658 #define BM_SDHC_PROCTL_CDTL  (0x00000040U) /*!< Bit mask for SDHC_PROCTL_CDTL. */
01659 #define BS_SDHC_PROCTL_CDTL  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CDTL. */
01660 
01661 /*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
01662 #define BR_SDHC_PROCTL_CDTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL))
01663 
01664 /*! @brief Format value for bitfield SDHC_PROCTL_CDTL. */
01665 #define BF_SDHC_PROCTL_CDTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDTL) & BM_SDHC_PROCTL_CDTL)
01666 
01667 /*! @brief Set the CDTL field to a new value. */
01668 #define BW_SDHC_PROCTL_CDTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL) = (v))
01669 /*@}*/
01670 
01671 /*!
01672  * @name Register SDHC_PROCTL, field CDSS[7] (RW)
01673  *
01674  * Selects the source for the card detection.
01675  *
01676  * Values:
01677  * - 0 - Card detection level is selected for normal purpose.
01678  * - 1 - Card detection test level is selected for test purpose.
01679  */
01680 /*@{*/
01681 #define BP_SDHC_PROCTL_CDSS  (7U)          /*!< Bit position for SDHC_PROCTL_CDSS. */
01682 #define BM_SDHC_PROCTL_CDSS  (0x00000080U) /*!< Bit mask for SDHC_PROCTL_CDSS. */
01683 #define BS_SDHC_PROCTL_CDSS  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CDSS. */
01684 
01685 /*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
01686 #define BR_SDHC_PROCTL_CDSS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS))
01687 
01688 /*! @brief Format value for bitfield SDHC_PROCTL_CDSS. */
01689 #define BF_SDHC_PROCTL_CDSS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDSS) & BM_SDHC_PROCTL_CDSS)
01690 
01691 /*! @brief Set the CDSS field to a new value. */
01692 #define BW_SDHC_PROCTL_CDSS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS) = (v))
01693 /*@}*/
01694 
01695 /*!
01696  * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
01697  *
01698  * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
01699  * operation.
01700  *
01701  * Values:
01702  * - 00 - No DMA or simple DMA is selected.
01703  * - 01 - ADMA1 is selected.
01704  * - 10 - ADMA2 is selected.
01705  * - 11 - Reserved
01706  */
01707 /*@{*/
01708 #define BP_SDHC_PROCTL_DMAS  (8U)          /*!< Bit position for SDHC_PROCTL_DMAS. */
01709 #define BM_SDHC_PROCTL_DMAS  (0x00000300U) /*!< Bit mask for SDHC_PROCTL_DMAS. */
01710 #define BS_SDHC_PROCTL_DMAS  (2U)          /*!< Bit field size in bits for SDHC_PROCTL_DMAS. */
01711 
01712 /*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
01713 #define BR_SDHC_PROCTL_DMAS(x) (HW_SDHC_PROCTL(x).B.DMAS)
01714 
01715 /*! @brief Format value for bitfield SDHC_PROCTL_DMAS. */
01716 #define BF_SDHC_PROCTL_DMAS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DMAS) & BM_SDHC_PROCTL_DMAS)
01717 
01718 /*! @brief Set the DMAS field to a new value. */
01719 #define BW_SDHC_PROCTL_DMAS(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
01720 /*@}*/
01721 
01722 /*!
01723  * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
01724  *
01725  * Used to stop executing a transaction at the next block gap for both DMA and
01726  * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
01727  * transfer completion, the host driver shall leave this bit set to 1. Clearing both
01728  * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
01729  * Wait is used to stop the read transaction at the block gap. The SDHC will
01730  * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
01731  * that SDIO card support read wait. Therefore, the host driver shall not set
01732  * this bit during read transfers unless the SDIO card supports read wait and has
01733  * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
01734  * the read operation during block gap. In the case of write transfers in which
01735  * the host driver writes data to the data port register, the host driver shall set
01736  * this bit after all block data is written. If this bit is set to 1, the host
01737  * driver shall not write data to the Data Port register after a block is sent.
01738  * Once this bit is set, the host driver shall not clear this bit before
01739  * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
01740  * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
01741  *
01742  * Values:
01743  * - 0 - Transfer
01744  * - 1 - Stop
01745  */
01746 /*@{*/
01747 #define BP_SDHC_PROCTL_SABGREQ (16U)       /*!< Bit position for SDHC_PROCTL_SABGREQ. */
01748 #define BM_SDHC_PROCTL_SABGREQ (0x00010000U) /*!< Bit mask for SDHC_PROCTL_SABGREQ. */
01749 #define BS_SDHC_PROCTL_SABGREQ (1U)        /*!< Bit field size in bits for SDHC_PROCTL_SABGREQ. */
01750 
01751 /*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
01752 #define BR_SDHC_PROCTL_SABGREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ))
01753 
01754 /*! @brief Format value for bitfield SDHC_PROCTL_SABGREQ. */
01755 #define BF_SDHC_PROCTL_SABGREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_SABGREQ) & BM_SDHC_PROCTL_SABGREQ)
01756 
01757 /*! @brief Set the SABGREQ field to a new value. */
01758 #define BW_SDHC_PROCTL_SABGREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ) = (v))
01759 /*@}*/
01760 
01761 /*!
01762  * @name Register SDHC_PROCTL, field CREQ[17] (RW)
01763  *
01764  * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
01765  * When a suspend operation is not accepted by the card, it is also by setting this
01766  * bit to restart the paused transfer. To cancel stop at the block gap, set
01767  * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
01768  * automatically clears this bit, therefore it is not necessary for the host driver to
01769  * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
01770  * request is ignored.
01771  *
01772  * Values:
01773  * - 0 - No effect.
01774  * - 1 - Restart
01775  */
01776 /*@{*/
01777 #define BP_SDHC_PROCTL_CREQ  (17U)         /*!< Bit position for SDHC_PROCTL_CREQ. */
01778 #define BM_SDHC_PROCTL_CREQ  (0x00020000U) /*!< Bit mask for SDHC_PROCTL_CREQ. */
01779 #define BS_SDHC_PROCTL_CREQ  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CREQ. */
01780 
01781 /*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
01782 #define BR_SDHC_PROCTL_CREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ))
01783 
01784 /*! @brief Format value for bitfield SDHC_PROCTL_CREQ. */
01785 #define BF_SDHC_PROCTL_CREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CREQ) & BM_SDHC_PROCTL_CREQ)
01786 
01787 /*! @brief Set the CREQ field to a new value. */
01788 #define BW_SDHC_PROCTL_CREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ) = (v))
01789 /*@}*/
01790 
01791 /*!
01792  * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
01793  *
01794  * The read wait function is optional for SDIO cards. If the card supports read
01795  * wait, set this bit to enable use of the read wait protocol to stop read data
01796  * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
01797  * read data, which restricts commands generation. When the host driver detects an
01798  * SDIO card insertion, it shall set this bit according to the CCCR of the card.
01799  * If the card does not support read wait, this bit shall never be set to 1,
01800  * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
01801  * during read operation is also supported, but the SDHC will stop the SD Clock
01802  * to pause reading operation.
01803  *
01804  * Values:
01805  * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
01806  *     is set.
01807  * - 1 - Enable read wait control, and assert read wait without stopping SD
01808  *     clock at block gap when SABGREQ bit is set.
01809  */
01810 /*@{*/
01811 #define BP_SDHC_PROCTL_RWCTL (18U)         /*!< Bit position for SDHC_PROCTL_RWCTL. */
01812 #define BM_SDHC_PROCTL_RWCTL (0x00040000U) /*!< Bit mask for SDHC_PROCTL_RWCTL. */
01813 #define BS_SDHC_PROCTL_RWCTL (1U)          /*!< Bit field size in bits for SDHC_PROCTL_RWCTL. */
01814 
01815 /*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
01816 #define BR_SDHC_PROCTL_RWCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL))
01817 
01818 /*! @brief Format value for bitfield SDHC_PROCTL_RWCTL. */
01819 #define BF_SDHC_PROCTL_RWCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_RWCTL) & BM_SDHC_PROCTL_RWCTL)
01820 
01821 /*! @brief Set the RWCTL field to a new value. */
01822 #define BW_SDHC_PROCTL_RWCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL) = (v))
01823 /*@}*/
01824 
01825 /*!
01826  * @name Register SDHC_PROCTL, field IABG[19] (RW)
01827  *
01828  * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
01829  * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
01830  * for a multiple block transfer. Setting to 0 disables interrupt detection during
01831  * a multiple block transfer. If the SDIO card can't signal an interrupt during a
01832  * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
01833  * interrupt. When the host driver detects an SDIO card insertion, it shall set
01834  * this bit according to the CCCR of the card.
01835  *
01836  * Values:
01837  * - 0 - Disabled
01838  * - 1 - Enabled
01839  */
01840 /*@{*/
01841 #define BP_SDHC_PROCTL_IABG  (19U)         /*!< Bit position for SDHC_PROCTL_IABG. */
01842 #define BM_SDHC_PROCTL_IABG  (0x00080000U) /*!< Bit mask for SDHC_PROCTL_IABG. */
01843 #define BS_SDHC_PROCTL_IABG  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_IABG. */
01844 
01845 /*! @brief Read current value of the SDHC_PROCTL_IABG field. */
01846 #define BR_SDHC_PROCTL_IABG(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG))
01847 
01848 /*! @brief Format value for bitfield SDHC_PROCTL_IABG. */
01849 #define BF_SDHC_PROCTL_IABG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_IABG) & BM_SDHC_PROCTL_IABG)
01850 
01851 /*! @brief Set the IABG field to a new value. */
01852 #define BW_SDHC_PROCTL_IABG(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG) = (v))
01853 /*@}*/
01854 
01855 /*!
01856  * @name Register SDHC_PROCTL, field WECINT[24] (RW)
01857  *
01858  * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
01859  * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
01860  * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
01861  * the wakeup feature is not enabled, the SD_CLK must be active to assert the
01862  * card interrupt status and the SDHC interrupt.
01863  *
01864  * Values:
01865  * - 0 - Disabled
01866  * - 1 - Enabled
01867  */
01868 /*@{*/
01869 #define BP_SDHC_PROCTL_WECINT (24U)        /*!< Bit position for SDHC_PROCTL_WECINT. */
01870 #define BM_SDHC_PROCTL_WECINT (0x01000000U) /*!< Bit mask for SDHC_PROCTL_WECINT. */
01871 #define BS_SDHC_PROCTL_WECINT (1U)         /*!< Bit field size in bits for SDHC_PROCTL_WECINT. */
01872 
01873 /*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
01874 #define BR_SDHC_PROCTL_WECINT(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT))
01875 
01876 /*! @brief Format value for bitfield SDHC_PROCTL_WECINT. */
01877 #define BF_SDHC_PROCTL_WECINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINT) & BM_SDHC_PROCTL_WECINT)
01878 
01879 /*! @brief Set the WECINT field to a new value. */
01880 #define BW_SDHC_PROCTL_WECINT(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT) = (v))
01881 /*@}*/
01882 
01883 /*!
01884  * @name Register SDHC_PROCTL, field WECINS[25] (RW)
01885  *
01886  * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
01887  * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
01888  * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
01889  * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
01890  * interrupt.
01891  *
01892  * Values:
01893  * - 0 - Disabled
01894  * - 1 - Enabled
01895  */
01896 /*@{*/
01897 #define BP_SDHC_PROCTL_WECINS (25U)        /*!< Bit position for SDHC_PROCTL_WECINS. */
01898 #define BM_SDHC_PROCTL_WECINS (0x02000000U) /*!< Bit mask for SDHC_PROCTL_WECINS. */
01899 #define BS_SDHC_PROCTL_WECINS (1U)         /*!< Bit field size in bits for SDHC_PROCTL_WECINS. */
01900 
01901 /*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
01902 #define BR_SDHC_PROCTL_WECINS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS))
01903 
01904 /*! @brief Format value for bitfield SDHC_PROCTL_WECINS. */
01905 #define BF_SDHC_PROCTL_WECINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINS) & BM_SDHC_PROCTL_WECINS)
01906 
01907 /*! @brief Set the WECINS field to a new value. */
01908 #define BW_SDHC_PROCTL_WECINS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS) = (v))
01909 /*@}*/
01910 
01911 /*!
01912  * @name Register SDHC_PROCTL, field WECRM[26] (RW)
01913  *
01914  * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
01915  * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
01916  * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
01917  * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
01918  *
01919  * Values:
01920  * - 0 - Disabled
01921  * - 1 - Enabled
01922  */
01923 /*@{*/
01924 #define BP_SDHC_PROCTL_WECRM (26U)         /*!< Bit position for SDHC_PROCTL_WECRM. */
01925 #define BM_SDHC_PROCTL_WECRM (0x04000000U) /*!< Bit mask for SDHC_PROCTL_WECRM. */
01926 #define BS_SDHC_PROCTL_WECRM (1U)          /*!< Bit field size in bits for SDHC_PROCTL_WECRM. */
01927 
01928 /*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
01929 #define BR_SDHC_PROCTL_WECRM(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM))
01930 
01931 /*! @brief Format value for bitfield SDHC_PROCTL_WECRM. */
01932 #define BF_SDHC_PROCTL_WECRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECRM) & BM_SDHC_PROCTL_WECRM)
01933 
01934 /*! @brief Set the WECRM field to a new value. */
01935 #define BW_SDHC_PROCTL_WECRM(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM) = (v))
01936 /*@}*/
01937 
01938 /*******************************************************************************
01939  * HW_SDHC_SYSCTL - System Control register
01940  ******************************************************************************/
01941 
01942 /*!
01943  * @brief HW_SDHC_SYSCTL - System Control register (RW)
01944  *
01945  * Reset value: 0x00008008U
01946  */
01947 typedef union _hw_sdhc_sysctl
01948 {
01949     uint32_t U;
01950     struct _hw_sdhc_sysctl_bitfields
01951     {
01952         uint32_t IPGEN : 1;            /*!< [0] IPG Clock Enable */
01953         uint32_t HCKEN : 1;            /*!< [1] System Clock Enable */
01954         uint32_t PEREN : 1;            /*!< [2] Peripheral Clock Enable */
01955         uint32_t SDCLKEN : 1;          /*!< [3] SD Clock Enable */
01956         uint32_t DVS : 4;              /*!< [7:4] Divisor */
01957         uint32_t SDCLKFS : 8;          /*!< [15:8] SDCLK Frequency Select */
01958         uint32_t DTOCV : 4;            /*!< [19:16] Data Timeout Counter Value */
01959         uint32_t RESERVED0 : 4;        /*!< [23:20]  */
01960         uint32_t RSTA : 1;             /*!< [24] Software Reset For ALL */
01961         uint32_t RSTC : 1;             /*!< [25] Software Reset For CMD Line */
01962         uint32_t RSTD : 1;             /*!< [26] Software Reset For DAT Line */
01963         uint32_t INITA : 1;            /*!< [27] Initialization Active */
01964         uint32_t RESERVED1 : 4;        /*!< [31:28]  */
01965     } B;
01966 } hw_sdhc_sysctl_t;
01967 
01968 /*!
01969  * @name Constants and macros for entire SDHC_SYSCTL register
01970  */
01971 /*@{*/
01972 #define HW_SDHC_SYSCTL_ADDR(x)   ((x) + 0x2CU)
01973 
01974 #define HW_SDHC_SYSCTL(x)        (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR(x))
01975 #define HW_SDHC_SYSCTL_RD(x)     (HW_SDHC_SYSCTL(x).U)
01976 #define HW_SDHC_SYSCTL_WR(x, v)  (HW_SDHC_SYSCTL(x).U = (v))
01977 #define HW_SDHC_SYSCTL_SET(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) |  (v)))
01978 #define HW_SDHC_SYSCTL_CLR(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) & ~(v)))
01979 #define HW_SDHC_SYSCTL_TOG(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) ^  (v)))
01980 /*@}*/
01981 
01982 /*
01983  * Constants & macros for individual SDHC_SYSCTL bitfields
01984  */
01985 
01986 /*!
01987  * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
01988  *
01989  * If this bit is set, bus clock will always be active and no automatic gating
01990  * is applied. The bus clock will be internally gated off, if none of the
01991  * following factors are met: The cmd part is reset, or Data part is reset, or Soft
01992  * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
01993  * request is just set, or This bit is set, or Card insertion is detected, or Card
01994  * removal is detected, or Card external interrupt is detected, or The SDHC
01995  * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
01996  * is not gated off. So clearing only this bit has no effect unless the PEREN bit
01997  * is also cleared.
01998  *
01999  * Values:
02000  * - 0 - Bus clock will be internally gated off.
02001  * - 1 - Bus clock will not be automatically gated off.
02002  */
02003 /*@{*/
02004 #define BP_SDHC_SYSCTL_IPGEN (0U)          /*!< Bit position for SDHC_SYSCTL_IPGEN. */
02005 #define BM_SDHC_SYSCTL_IPGEN (0x00000001U) /*!< Bit mask for SDHC_SYSCTL_IPGEN. */
02006 #define BS_SDHC_SYSCTL_IPGEN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_IPGEN. */
02007 
02008 /*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
02009 #define BR_SDHC_SYSCTL_IPGEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN))
02010 
02011 /*! @brief Format value for bitfield SDHC_SYSCTL_IPGEN. */
02012 #define BF_SDHC_SYSCTL_IPGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_IPGEN) & BM_SDHC_SYSCTL_IPGEN)
02013 
02014 /*! @brief Set the IPGEN field to a new value. */
02015 #define BW_SDHC_SYSCTL_IPGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN) = (v))
02016 /*@}*/
02017 
02018 /*!
02019  * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
02020  *
02021  * If this bit is set, system clock will always be active and no automatic
02022  * gating is applied. When this bit is cleared, system clock will be automatically off
02023  * when no data transfer is on the SD bus.
02024  *
02025  * Values:
02026  * - 0 - System clock will be internally gated off.
02027  * - 1 - System clock will not be automatically gated off.
02028  */
02029 /*@{*/
02030 #define BP_SDHC_SYSCTL_HCKEN (1U)          /*!< Bit position for SDHC_SYSCTL_HCKEN. */
02031 #define BM_SDHC_SYSCTL_HCKEN (0x00000002U) /*!< Bit mask for SDHC_SYSCTL_HCKEN. */
02032 #define BS_SDHC_SYSCTL_HCKEN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_HCKEN. */
02033 
02034 /*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
02035 #define BR_SDHC_SYSCTL_HCKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN))
02036 
02037 /*! @brief Format value for bitfield SDHC_SYSCTL_HCKEN. */
02038 #define BF_SDHC_SYSCTL_HCKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_HCKEN) & BM_SDHC_SYSCTL_HCKEN)
02039 
02040 /*! @brief Set the HCKEN field to a new value. */
02041 #define BW_SDHC_SYSCTL_HCKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN) = (v))
02042 /*@}*/
02043 
02044 /*!
02045  * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
02046  *
02047  * If this bit is set, SDHC clock will always be active and no automatic gating
02048  * is applied. Thus the SDCLK is active except for when auto gating-off during
02049  * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
02050  * the SDHC clock will be automatically off whenever there is no transaction on
02051  * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
02052  * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
02053  * if none of the following factors are met: The cmd part is reset, or Data part
02054  * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
02055  * just updated, or Continue request is just set, or This bit is set, or Card
02056  * insertion is detected, or Card removal is detected, or Card external interrupt is
02057  * detected, or 80 clocks for initialization phase is ongoing
02058  *
02059  * Values:
02060  * - 0 - SDHC clock will be internally gated off.
02061  * - 1 - SDHC clock will not be automatically gated off.
02062  */
02063 /*@{*/
02064 #define BP_SDHC_SYSCTL_PEREN (2U)          /*!< Bit position for SDHC_SYSCTL_PEREN. */
02065 #define BM_SDHC_SYSCTL_PEREN (0x00000004U) /*!< Bit mask for SDHC_SYSCTL_PEREN. */
02066 #define BS_SDHC_SYSCTL_PEREN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_PEREN. */
02067 
02068 /*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
02069 #define BR_SDHC_SYSCTL_PEREN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN))
02070 
02071 /*! @brief Format value for bitfield SDHC_SYSCTL_PEREN. */
02072 #define BF_SDHC_SYSCTL_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_PEREN) & BM_SDHC_SYSCTL_PEREN)
02073 
02074 /*! @brief Set the PEREN field to a new value. */
02075 #define BW_SDHC_SYSCTL_PEREN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN) = (v))
02076 /*@}*/
02077 
02078 /*!
02079  * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
02080  *
02081  * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
02082  * frequency can be changed when this bit is 0. Then, the host controller shall
02083  * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
02084  * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
02085  * power.
02086  */
02087 /*@{*/
02088 #define BP_SDHC_SYSCTL_SDCLKEN (3U)        /*!< Bit position for SDHC_SYSCTL_SDCLKEN. */
02089 #define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) /*!< Bit mask for SDHC_SYSCTL_SDCLKEN. */
02090 #define BS_SDHC_SYSCTL_SDCLKEN (1U)        /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN. */
02091 
02092 /*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
02093 #define BR_SDHC_SYSCTL_SDCLKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN))
02094 
02095 /*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN. */
02096 #define BF_SDHC_SYSCTL_SDCLKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKEN) & BM_SDHC_SYSCTL_SDCLKEN)
02097 
02098 /*! @brief Set the SDCLKEN field to a new value. */
02099 #define BW_SDHC_SYSCTL_SDCLKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN) = (v))
02100 /*@}*/
02101 
02102 /*!
02103  * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
02104  *
02105  * Used to provide a more exact divisor to generate the desired SD clock
02106  * frequency. Note the divider can even support odd divisor without deterioration of
02107  * duty cycle. The setting are as following:
02108  *
02109  * Values:
02110  * - 0 - Divisor by 1.
02111  * - 1 - Divisor by 2.
02112  * - 1110 - Divisor by 15.
02113  * - 1111 - Divisor by 16.
02114  */
02115 /*@{*/
02116 #define BP_SDHC_SYSCTL_DVS   (4U)          /*!< Bit position for SDHC_SYSCTL_DVS. */
02117 #define BM_SDHC_SYSCTL_DVS   (0x000000F0U) /*!< Bit mask for SDHC_SYSCTL_DVS. */
02118 #define BS_SDHC_SYSCTL_DVS   (4U)          /*!< Bit field size in bits for SDHC_SYSCTL_DVS. */
02119 
02120 /*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
02121 #define BR_SDHC_SYSCTL_DVS(x) (HW_SDHC_SYSCTL(x).B.DVS)
02122 
02123 /*! @brief Format value for bitfield SDHC_SYSCTL_DVS. */
02124 #define BF_SDHC_SYSCTL_DVS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DVS) & BM_SDHC_SYSCTL_DVS)
02125 
02126 /*! @brief Set the DVS field to a new value. */
02127 #define BW_SDHC_SYSCTL_DVS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
02128 /*@}*/
02129 
02130 /*!
02131  * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
02132  *
02133  * Used to select the frequency of the SDCLK pin. The frequency is not
02134  * programmed directly. Rather this register holds the prescaler (this register) and
02135  * divisor (next register) of the base clock frequency register. Setting 00h bypasses
02136  * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
02137  * behavior of this prescaler is undefined. The two default divider values can
02138  * be calculated by the frequency of SDHC clock and the following divisor bits.
02139  * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
02140  * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
02141  * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
02142  * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
02143  * less than or equal to the target. Similarly, to approach a clock value of 400
02144  * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
02145  * value of 400 kHz. The reset value of this field is 80h, so if the input base
02146  * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
02147  * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
02148  * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
02149  * never exceed this limit. Only the following settings are allowed:
02150  *
02151  * Values:
02152  * - 1 - Base clock divided by 2.
02153  * - 10 - Base clock divided by 4.
02154  * - 100 - Base clock divided by 8.
02155  * - 1000 - Base clock divided by 16.
02156  * - 10000 - Base clock divided by 32.
02157  * - 100000 - Base clock divided by 64.
02158  * - 1000000 - Base clock divided by 128.
02159  * - 10000000 - Base clock divided by 256.
02160  */
02161 /*@{*/
02162 #define BP_SDHC_SYSCTL_SDCLKFS (8U)        /*!< Bit position for SDHC_SYSCTL_SDCLKFS. */
02163 #define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) /*!< Bit mask for SDHC_SYSCTL_SDCLKFS. */
02164 #define BS_SDHC_SYSCTL_SDCLKFS (8U)        /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS. */
02165 
02166 /*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
02167 #define BR_SDHC_SYSCTL_SDCLKFS(x) (HW_SDHC_SYSCTL(x).B.SDCLKFS)
02168 
02169 /*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS. */
02170 #define BF_SDHC_SYSCTL_SDCLKFS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKFS) & BM_SDHC_SYSCTL_SDCLKFS)
02171 
02172 /*! @brief Set the SDCLKFS field to a new value. */
02173 #define BW_SDHC_SYSCTL_SDCLKFS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
02174 /*@}*/
02175 
02176 /*!
02177  * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
02178  *
02179  * Determines the interval by which DAT line timeouts are detected. See
02180  * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
02181  * clock frequency will be generated by dividing the base clock SDCLK value by this
02182  * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
02183  * time-out events.
02184  *
02185  * Values:
02186  * - 0000 - SDCLK x 2 13
02187  * - 0001 - SDCLK x 2 14
02188  * - 1110 - SDCLK x 2 27
02189  * - 1111 - Reserved
02190  */
02191 /*@{*/
02192 #define BP_SDHC_SYSCTL_DTOCV (16U)         /*!< Bit position for SDHC_SYSCTL_DTOCV. */
02193 #define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) /*!< Bit mask for SDHC_SYSCTL_DTOCV. */
02194 #define BS_SDHC_SYSCTL_DTOCV (4U)          /*!< Bit field size in bits for SDHC_SYSCTL_DTOCV. */
02195 
02196 /*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
02197 #define BR_SDHC_SYSCTL_DTOCV(x) (HW_SDHC_SYSCTL(x).B.DTOCV)
02198 
02199 /*! @brief Format value for bitfield SDHC_SYSCTL_DTOCV. */
02200 #define BF_SDHC_SYSCTL_DTOCV(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DTOCV) & BM_SDHC_SYSCTL_DTOCV)
02201 
02202 /*! @brief Set the DTOCV field to a new value. */
02203 #define BW_SDHC_SYSCTL_DTOCV(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
02204 /*@}*/
02205 
02206 /*!
02207  * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
02208  *
02209  * Effects the entire host controller except for the card detection circuit.
02210  * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
02211  * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
02212  * reset this bit to 0 when the capabilities registers are valid and the host driver
02213  * can read them. Additional use of software reset for all does not affect the
02214  * value of the capabilities registers. After this bit is set, it is recommended
02215  * that the host driver reset the external card and reinitialize it.
02216  *
02217  * Values:
02218  * - 0 - No reset.
02219  * - 1 - Reset.
02220  */
02221 /*@{*/
02222 #define BP_SDHC_SYSCTL_RSTA  (24U)         /*!< Bit position for SDHC_SYSCTL_RSTA. */
02223 #define BM_SDHC_SYSCTL_RSTA  (0x01000000U) /*!< Bit mask for SDHC_SYSCTL_RSTA. */
02224 #define BS_SDHC_SYSCTL_RSTA  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTA. */
02225 
02226 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTA. */
02227 #define BF_SDHC_SYSCTL_RSTA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTA) & BM_SDHC_SYSCTL_RSTA)
02228 
02229 /*! @brief Set the RSTA field to a new value. */
02230 #define BW_SDHC_SYSCTL_RSTA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTA) = (v))
02231 /*@}*/
02232 
02233 /*!
02234  * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
02235  *
02236  * Only part of the command circuit is reset. The following registers and bits
02237  * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
02238  *
02239  * Values:
02240  * - 0 - No reset.
02241  * - 1 - Reset.
02242  */
02243 /*@{*/
02244 #define BP_SDHC_SYSCTL_RSTC  (25U)         /*!< Bit position for SDHC_SYSCTL_RSTC. */
02245 #define BM_SDHC_SYSCTL_RSTC  (0x02000000U) /*!< Bit mask for SDHC_SYSCTL_RSTC. */
02246 #define BS_SDHC_SYSCTL_RSTC  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTC. */
02247 
02248 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTC. */
02249 #define BF_SDHC_SYSCTL_RSTC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTC) & BM_SDHC_SYSCTL_RSTC)
02250 
02251 /*! @brief Set the RSTC field to a new value. */
02252 #define BW_SDHC_SYSCTL_RSTC(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTC) = (v))
02253 /*@}*/
02254 
02255 /*!
02256  * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
02257  *
02258  * Only part of the data circuit is reset. DMA circuit is also reset. The
02259  * following registers and bits are cleared by this bit: Data Port register Buffer Is
02260  * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
02261  * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
02262  * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
02263  * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
02264  * Block Gap Event Transfer Complete
02265  *
02266  * Values:
02267  * - 0 - No reset.
02268  * - 1 - Reset.
02269  */
02270 /*@{*/
02271 #define BP_SDHC_SYSCTL_RSTD  (26U)         /*!< Bit position for SDHC_SYSCTL_RSTD. */
02272 #define BM_SDHC_SYSCTL_RSTD  (0x04000000U) /*!< Bit mask for SDHC_SYSCTL_RSTD. */
02273 #define BS_SDHC_SYSCTL_RSTD  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTD. */
02274 
02275 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTD. */
02276 #define BF_SDHC_SYSCTL_RSTD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTD) & BM_SDHC_SYSCTL_RSTD)
02277 
02278 /*! @brief Set the RSTD field to a new value. */
02279 #define BW_SDHC_SYSCTL_RSTD(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTD) = (v))
02280 /*@}*/
02281 
02282 /*!
02283  * @name Register SDHC_SYSCTL, field INITA[27] (RW)
02284  *
02285  * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
02286  * are sent, this bit is self-cleared. This bit is very useful during the card
02287  * power-up period when 74 SD-clocks are needed and the clock auto gating feature
02288  * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
02289  * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
02290  * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
02291  * when command line or data lines are active, write to this bit is not allowed.
02292  * On the otherhand, when this bit is set, that is, during intialization active
02293  * period, it is allowed to issue command, and the command bit stream will appear
02294  * on the CMD pad after all 80 clock cycles are done. So when this command ends,
02295  * the driver can make sure the 80 clock cycles are sent out. This is very useful
02296  * when the driver needs send 80 cycles to the card and does not want to wait
02297  * till this bit is self-cleared.
02298  */
02299 /*@{*/
02300 #define BP_SDHC_SYSCTL_INITA (27U)         /*!< Bit position for SDHC_SYSCTL_INITA. */
02301 #define BM_SDHC_SYSCTL_INITA (0x08000000U) /*!< Bit mask for SDHC_SYSCTL_INITA. */
02302 #define BS_SDHC_SYSCTL_INITA (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_INITA. */
02303 
02304 /*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
02305 #define BR_SDHC_SYSCTL_INITA(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA))
02306 
02307 /*! @brief Format value for bitfield SDHC_SYSCTL_INITA. */
02308 #define BF_SDHC_SYSCTL_INITA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_INITA) & BM_SDHC_SYSCTL_INITA)
02309 
02310 /*! @brief Set the INITA field to a new value. */
02311 #define BW_SDHC_SYSCTL_INITA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA) = (v))
02312 /*@}*/
02313 
02314 /*******************************************************************************
02315  * HW_SDHC_IRQSTAT - Interrupt Status register
02316  ******************************************************************************/
02317 
02318 /*!
02319  * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
02320  *
02321  * Reset value: 0x00000000U
02322  *
02323  * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
02324  * and at least one of the status bits is set to 1. For all bits, writing 1 to a
02325  * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
02326  * be cleared with a single register write. For Card Interrupt, before writing 1
02327  * to clear, it is required that the card stops asserting the interrupt, meaning
02328  * that when the Card Driver services the interrupt condition, otherwise the CINT
02329  * bit will be asserted again. The table below shows the relationship between
02330  * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
02331  * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
02332  * received within 64 SDCLK cycles 1 0 Response received The table below shows the
02333  * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
02334  * for data timeout error/transfer complete bit combinations Transfer complete
02335  * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
02336  * transfer 1 X Data transfer complete The table below shows the relationship between
02337  * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
02338  * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
02339  * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
02340  * CMD line conflict
02341  */
02342 typedef union _hw_sdhc_irqstat
02343 {
02344     uint32_t U;
02345     struct _hw_sdhc_irqstat_bitfields
02346     {
02347         uint32_t CC : 1;               /*!< [0] Command Complete */
02348         uint32_t TC : 1;               /*!< [1] Transfer Complete */
02349         uint32_t BGE : 1;              /*!< [2] Block Gap Event */
02350         uint32_t DINT : 1;             /*!< [3] DMA Interrupt */
02351         uint32_t BWR : 1;              /*!< [4] Buffer Write Ready */
02352         uint32_t BRR : 1;              /*!< [5] Buffer Read Ready */
02353         uint32_t CINS : 1;             /*!< [6] Card Insertion */
02354         uint32_t CRM : 1;              /*!< [7] Card Removal */
02355         uint32_t CINT : 1;             /*!< [8] Card Interrupt */
02356         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
02357         uint32_t CTOE : 1;             /*!< [16] Command Timeout Error */
02358         uint32_t CCE : 1;              /*!< [17] Command CRC Error */
02359         uint32_t CEBE : 1;             /*!< [18] Command End Bit Error */
02360         uint32_t CIE : 1;              /*!< [19] Command Index Error */
02361         uint32_t DTOE : 1;             /*!< [20] Data Timeout Error */
02362         uint32_t DCE : 1;              /*!< [21] Data CRC Error */
02363         uint32_t DEBE : 1;             /*!< [22] Data End Bit Error */
02364         uint32_t RESERVED1 : 1;        /*!< [23]  */
02365         uint32_t AC12E : 1;            /*!< [24] Auto CMD12 Error */
02366         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
02367         uint32_t DMAE : 1;             /*!< [28] DMA Error */
02368         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02369     } B;
02370 } hw_sdhc_irqstat_t;
02371 
02372 /*!
02373  * @name Constants and macros for entire SDHC_IRQSTAT register
02374  */
02375 /*@{*/
02376 #define HW_SDHC_IRQSTAT_ADDR(x)  ((x) + 0x30U)
02377 
02378 #define HW_SDHC_IRQSTAT(x)       (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR(x))
02379 #define HW_SDHC_IRQSTAT_RD(x)    (HW_SDHC_IRQSTAT(x).U)
02380 #define HW_SDHC_IRQSTAT_WR(x, v) (HW_SDHC_IRQSTAT(x).U = (v))
02381 #define HW_SDHC_IRQSTAT_SET(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) |  (v)))
02382 #define HW_SDHC_IRQSTAT_CLR(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) & ~(v)))
02383 #define HW_SDHC_IRQSTAT_TOG(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) ^  (v)))
02384 /*@}*/
02385 
02386 /*
02387  * Constants & macros for individual SDHC_IRQSTAT bitfields
02388  */
02389 
02390 /*!
02391  * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
02392  *
02393  * This bit is set when you receive the end bit of the command response, except
02394  * Auto CMD12. See PRSSTAT[CIHB].
02395  *
02396  * Values:
02397  * - 0 - Command not complete.
02398  * - 1 - Command complete.
02399  */
02400 /*@{*/
02401 #define BP_SDHC_IRQSTAT_CC   (0U)          /*!< Bit position for SDHC_IRQSTAT_CC. */
02402 #define BM_SDHC_IRQSTAT_CC   (0x00000001U) /*!< Bit mask for SDHC_IRQSTAT_CC. */
02403 #define BS_SDHC_IRQSTAT_CC   (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CC. */
02404 
02405 /*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
02406 #define BR_SDHC_IRQSTAT_CC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC))
02407 
02408 /*! @brief Format value for bitfield SDHC_IRQSTAT_CC. */
02409 #define BF_SDHC_IRQSTAT_CC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CC) & BM_SDHC_IRQSTAT_CC)
02410 
02411 /*! @brief Set the CC field to a new value. */
02412 #define BW_SDHC_IRQSTAT_CC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC) = (v))
02413 /*@}*/
02414 
02415 /*!
02416  * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
02417  *
02418  * This bit is set when a read or write transfer is completed. In the case of a
02419  * read transaction: This bit is set at the falling edge of the read transfer
02420  * active status. There are two cases in which this interrupt is generated. The
02421  * first is when a data transfer is completed as specified by the data length, after
02422  * the last data has been read to the host system. The second is when data has
02423  * stopped at the block gap and completed the data transfer by setting
02424  * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
02425  * transaction: This bit is set at the falling edge of the DAT line active
02426  * status. There are two cases in which this interrupt is generated. The first is when
02427  * the last data is written to the SD card as specified by the data length and
02428  * the busy signal is released. The second is when data transfers are stopped at
02429  * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
02430  * completed,after valid data is written to the SD card and the busy signal released.
02431  *
02432  * Values:
02433  * - 0 - Transfer not complete.
02434  * - 1 - Transfer complete.
02435  */
02436 /*@{*/
02437 #define BP_SDHC_IRQSTAT_TC   (1U)          /*!< Bit position for SDHC_IRQSTAT_TC. */
02438 #define BM_SDHC_IRQSTAT_TC   (0x00000002U) /*!< Bit mask for SDHC_IRQSTAT_TC. */
02439 #define BS_SDHC_IRQSTAT_TC   (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_TC. */
02440 
02441 /*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
02442 #define BR_SDHC_IRQSTAT_TC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC))
02443 
02444 /*! @brief Format value for bitfield SDHC_IRQSTAT_TC. */
02445 #define BF_SDHC_IRQSTAT_TC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_TC) & BM_SDHC_IRQSTAT_TC)
02446 
02447 /*! @brief Set the TC field to a new value. */
02448 #define BW_SDHC_IRQSTAT_TC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC) = (v))
02449 /*@}*/
02450 
02451 /*!
02452  * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
02453  *
02454  * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
02455  * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
02456  * set to 1. In the case of a read transaction: This bit is set at the falling
02457  * edge of the DAT line active status, when the transaction is stopped at SD Bus
02458  * timing. The read wait must be supported in order to use this function. In the
02459  * case of write transaction: This bit is set at the falling edge of write transfer
02460  * active status, after getting CRC status at SD bus timing.
02461  *
02462  * Values:
02463  * - 0 - No block gap event.
02464  * - 1 - Transaction stopped at block gap.
02465  */
02466 /*@{*/
02467 #define BP_SDHC_IRQSTAT_BGE  (2U)          /*!< Bit position for SDHC_IRQSTAT_BGE. */
02468 #define BM_SDHC_IRQSTAT_BGE  (0x00000004U) /*!< Bit mask for SDHC_IRQSTAT_BGE. */
02469 #define BS_SDHC_IRQSTAT_BGE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BGE. */
02470 
02471 /*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
02472 #define BR_SDHC_IRQSTAT_BGE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE))
02473 
02474 /*! @brief Format value for bitfield SDHC_IRQSTAT_BGE. */
02475 #define BF_SDHC_IRQSTAT_BGE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BGE) & BM_SDHC_IRQSTAT_BGE)
02476 
02477 /*! @brief Set the BGE field to a new value. */
02478 #define BW_SDHC_IRQSTAT_BGE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE) = (v))
02479 /*@}*/
02480 
02481 /*!
02482  * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
02483  *
02484  * Occurs only when the internal DMA finishes the data transfer successfully.
02485  * Whenever errors occur during data transfer, this bit will not be set. Instead,
02486  * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
02487  * this bit will be set.
02488  *
02489  * Values:
02490  * - 0 - No DMA Interrupt.
02491  * - 1 - DMA Interrupt is generated.
02492  */
02493 /*@{*/
02494 #define BP_SDHC_IRQSTAT_DINT (3U)          /*!< Bit position for SDHC_IRQSTAT_DINT. */
02495 #define BM_SDHC_IRQSTAT_DINT (0x00000008U) /*!< Bit mask for SDHC_IRQSTAT_DINT. */
02496 #define BS_SDHC_IRQSTAT_DINT (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DINT. */
02497 
02498 /*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
02499 #define BR_SDHC_IRQSTAT_DINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT))
02500 
02501 /*! @brief Format value for bitfield SDHC_IRQSTAT_DINT. */
02502 #define BF_SDHC_IRQSTAT_DINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DINT) & BM_SDHC_IRQSTAT_DINT)
02503 
02504 /*! @brief Set the DINT field to a new value. */
02505 #define BW_SDHC_IRQSTAT_DINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT) = (v))
02506 /*@}*/
02507 
02508 /*!
02509  * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
02510  *
02511  * This status bit is set if the Buffer Write Enable bit, in the Present State
02512  * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
02513  * State register for additional information.
02514  *
02515  * Values:
02516  * - 0 - Not ready to write buffer.
02517  * - 1 - Ready to write buffer.
02518  */
02519 /*@{*/
02520 #define BP_SDHC_IRQSTAT_BWR  (4U)          /*!< Bit position for SDHC_IRQSTAT_BWR. */
02521 #define BM_SDHC_IRQSTAT_BWR  (0x00000010U) /*!< Bit mask for SDHC_IRQSTAT_BWR. */
02522 #define BS_SDHC_IRQSTAT_BWR  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BWR. */
02523 
02524 /*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
02525 #define BR_SDHC_IRQSTAT_BWR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR))
02526 
02527 /*! @brief Format value for bitfield SDHC_IRQSTAT_BWR. */
02528 #define BF_SDHC_IRQSTAT_BWR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BWR) & BM_SDHC_IRQSTAT_BWR)
02529 
02530 /*! @brief Set the BWR field to a new value. */
02531 #define BW_SDHC_IRQSTAT_BWR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR) = (v))
02532 /*@}*/
02533 
02534 /*!
02535  * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
02536  *
02537  * This status bit is set if the Buffer Read Enable bit, in the Present State
02538  * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
02539  * State register for additional information.
02540  *
02541  * Values:
02542  * - 0 - Not ready to read buffer.
02543  * - 1 - Ready to read buffer.
02544  */
02545 /*@{*/
02546 #define BP_SDHC_IRQSTAT_BRR  (5U)          /*!< Bit position for SDHC_IRQSTAT_BRR. */
02547 #define BM_SDHC_IRQSTAT_BRR  (0x00000020U) /*!< Bit mask for SDHC_IRQSTAT_BRR. */
02548 #define BS_SDHC_IRQSTAT_BRR  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BRR. */
02549 
02550 /*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
02551 #define BR_SDHC_IRQSTAT_BRR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR))
02552 
02553 /*! @brief Format value for bitfield SDHC_IRQSTAT_BRR. */
02554 #define BF_SDHC_IRQSTAT_BRR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BRR) & BM_SDHC_IRQSTAT_BRR)
02555 
02556 /*! @brief Set the BRR field to a new value. */
02557 #define BW_SDHC_IRQSTAT_BRR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR) = (v))
02558 /*@}*/
02559 
02560 /*!
02561  * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
02562  *
02563  * This status bit is set if the Card Inserted bit in the Present State register
02564  * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
02565  * status, the status of the Card Inserted in the Present State register must be
02566  * confirmed. Because the card state may possibly be changed when the host driver
02567  * clears this bit and the interrupt event may not be generated. When this bit
02568  * is cleared, it will be set again if a card is inserted. To leave it cleared,
02569  * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
02570  *
02571  * Values:
02572  * - 0 - Card state unstable or removed.
02573  * - 1 - Card inserted.
02574  */
02575 /*@{*/
02576 #define BP_SDHC_IRQSTAT_CINS (6U)          /*!< Bit position for SDHC_IRQSTAT_CINS. */
02577 #define BM_SDHC_IRQSTAT_CINS (0x00000040U) /*!< Bit mask for SDHC_IRQSTAT_CINS. */
02578 #define BS_SDHC_IRQSTAT_CINS (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CINS. */
02579 
02580 /*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
02581 #define BR_SDHC_IRQSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS))
02582 
02583 /*! @brief Format value for bitfield SDHC_IRQSTAT_CINS. */
02584 #define BF_SDHC_IRQSTAT_CINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINS) & BM_SDHC_IRQSTAT_CINS)
02585 
02586 /*! @brief Set the CINS field to a new value. */
02587 #define BW_SDHC_IRQSTAT_CINS(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS) = (v))
02588 /*@}*/
02589 
02590 /*!
02591  * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
02592  *
02593  * This status bit is set if the Card Inserted bit in the Present State register
02594  * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
02595  * status, the status of the Card Inserted in the Present State register must be
02596  * confirmed. Because the card state may possibly be changed when the host driver
02597  * clears this bit and the interrupt event may not be generated. When this bit
02598  * is cleared, it will be set again if no card is inserted. To leave it cleared,
02599  * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
02600  *
02601  * Values:
02602  * - 0 - Card state unstable or inserted.
02603  * - 1 - Card removed.
02604  */
02605 /*@{*/
02606 #define BP_SDHC_IRQSTAT_CRM  (7U)          /*!< Bit position for SDHC_IRQSTAT_CRM. */
02607 #define BM_SDHC_IRQSTAT_CRM  (0x00000080U) /*!< Bit mask for SDHC_IRQSTAT_CRM. */
02608 #define BS_SDHC_IRQSTAT_CRM  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CRM. */
02609 
02610 /*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
02611 #define BR_SDHC_IRQSTAT_CRM(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM))
02612 
02613 /*! @brief Format value for bitfield SDHC_IRQSTAT_CRM. */
02614 #define BF_SDHC_IRQSTAT_CRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CRM) & BM_SDHC_IRQSTAT_CRM)
02615 
02616 /*! @brief Set the CRM field to a new value. */
02617 #define BW_SDHC_IRQSTAT_CRM(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM) = (v))
02618 /*@}*/
02619 
02620 /*!
02621  * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
02622  *
02623  * This status bit is set when an interrupt signal is detected from the external
02624  * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
02625  * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
02626  * during the interrupt cycle, so the interrupt from card can only be sampled
02627  * during interrupt cycle, introducing some delay between the interrupt signal from
02628  * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
02629  * clear this bit, but as the interrupt factor from the SDIO card does not clear,
02630  * this bit is set again. To clear this bit, it is required to reset the interrupt
02631  * factor from the external card followed by a writing 1 to this bit. When this
02632  * status has been set, and the host driver needs to service this interrupt, the
02633  * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
02634  * 0 to stop driving the interrupt signal to the host system. After completion
02635  * of the card interrupt service (it must reset the interrupt factors in the SDIO
02636  * card and the interrupt signal may not be asserted), write 1 to clear this bit,
02637  * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
02638  * signal again.
02639  *
02640  * Values:
02641  * - 0 - No Card Interrupt.
02642  * - 1 - Generate Card Interrupt.
02643  */
02644 /*@{*/
02645 #define BP_SDHC_IRQSTAT_CINT (8U)          /*!< Bit position for SDHC_IRQSTAT_CINT. */
02646 #define BM_SDHC_IRQSTAT_CINT (0x00000100U) /*!< Bit mask for SDHC_IRQSTAT_CINT. */
02647 #define BS_SDHC_IRQSTAT_CINT (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CINT. */
02648 
02649 /*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
02650 #define BR_SDHC_IRQSTAT_CINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT))
02651 
02652 /*! @brief Format value for bitfield SDHC_IRQSTAT_CINT. */
02653 #define BF_SDHC_IRQSTAT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINT) & BM_SDHC_IRQSTAT_CINT)
02654 
02655 /*! @brief Set the CINT field to a new value. */
02656 #define BW_SDHC_IRQSTAT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT) = (v))
02657 /*@}*/
02658 
02659 /*!
02660  * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
02661  *
02662  * Occurs only if no response is returned within 64 SDCLK cycles from the end
02663  * bit of the command. If the SDHC detects a CMD line conflict, in which case a
02664  * Command CRC Error shall also be set, this bit shall be set without waiting for 64
02665  * SDCLK cycles. This is because the command will be aborted by the SDHC.
02666  *
02667  * Values:
02668  * - 0 - No error.
02669  * - 1 - Time out.
02670  */
02671 /*@{*/
02672 #define BP_SDHC_IRQSTAT_CTOE (16U)         /*!< Bit position for SDHC_IRQSTAT_CTOE. */
02673 #define BM_SDHC_IRQSTAT_CTOE (0x00010000U) /*!< Bit mask for SDHC_IRQSTAT_CTOE. */
02674 #define BS_SDHC_IRQSTAT_CTOE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CTOE. */
02675 
02676 /*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
02677 #define BR_SDHC_IRQSTAT_CTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE))
02678 
02679 /*! @brief Format value for bitfield SDHC_IRQSTAT_CTOE. */
02680 #define BF_SDHC_IRQSTAT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CTOE) & BM_SDHC_IRQSTAT_CTOE)
02681 
02682 /*! @brief Set the CTOE field to a new value. */
02683 #define BW_SDHC_IRQSTAT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE) = (v))
02684 /*@}*/
02685 
02686 /*!
02687  * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
02688  *
02689  * Command CRC Error is generated in two cases. If a response is returned and
02690  * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
02691  * when detecting a CRC error in the command response. The SDHC detects a CMD line
02692  * conflict by monitoring the CMD line when a command is issued. If the SDHC
02693  * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
02694  * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
02695  * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
02696  * conflict.
02697  *
02698  * Values:
02699  * - 0 - No error.
02700  * - 1 - CRC Error generated.
02701  */
02702 /*@{*/
02703 #define BP_SDHC_IRQSTAT_CCE  (17U)         /*!< Bit position for SDHC_IRQSTAT_CCE. */
02704 #define BM_SDHC_IRQSTAT_CCE  (0x00020000U) /*!< Bit mask for SDHC_IRQSTAT_CCE. */
02705 #define BS_SDHC_IRQSTAT_CCE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CCE. */
02706 
02707 /*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
02708 #define BR_SDHC_IRQSTAT_CCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE))
02709 
02710 /*! @brief Format value for bitfield SDHC_IRQSTAT_CCE. */
02711 #define BF_SDHC_IRQSTAT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CCE) & BM_SDHC_IRQSTAT_CCE)
02712 
02713 /*! @brief Set the CCE field to a new value. */
02714 #define BW_SDHC_IRQSTAT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE) = (v))
02715 /*@}*/
02716 
02717 /*!
02718  * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
02719  *
02720  * Occurs when detecting that the end bit of a command response is 0.
02721  *
02722  * Values:
02723  * - 0 - No error.
02724  * - 1 - End Bit Error generated.
02725  */
02726 /*@{*/
02727 #define BP_SDHC_IRQSTAT_CEBE (18U)         /*!< Bit position for SDHC_IRQSTAT_CEBE. */
02728 #define BM_SDHC_IRQSTAT_CEBE (0x00040000U) /*!< Bit mask for SDHC_IRQSTAT_CEBE. */
02729 #define BS_SDHC_IRQSTAT_CEBE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CEBE. */
02730 
02731 /*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
02732 #define BR_SDHC_IRQSTAT_CEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE))
02733 
02734 /*! @brief Format value for bitfield SDHC_IRQSTAT_CEBE. */
02735 #define BF_SDHC_IRQSTAT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CEBE) & BM_SDHC_IRQSTAT_CEBE)
02736 
02737 /*! @brief Set the CEBE field to a new value. */
02738 #define BW_SDHC_IRQSTAT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE) = (v))
02739 /*@}*/
02740 
02741 /*!
02742  * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
02743  *
02744  * Occurs if a Command Index error occurs in the command response.
02745  *
02746  * Values:
02747  * - 0 - No error.
02748  * - 1 - Error.
02749  */
02750 /*@{*/
02751 #define BP_SDHC_IRQSTAT_CIE  (19U)         /*!< Bit position for SDHC_IRQSTAT_CIE. */
02752 #define BM_SDHC_IRQSTAT_CIE  (0x00080000U) /*!< Bit mask for SDHC_IRQSTAT_CIE. */
02753 #define BS_SDHC_IRQSTAT_CIE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CIE. */
02754 
02755 /*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
02756 #define BR_SDHC_IRQSTAT_CIE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE))
02757 
02758 /*! @brief Format value for bitfield SDHC_IRQSTAT_CIE. */
02759 #define BF_SDHC_IRQSTAT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CIE) & BM_SDHC_IRQSTAT_CIE)
02760 
02761 /*! @brief Set the CIE field to a new value. */
02762 #define BW_SDHC_IRQSTAT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE) = (v))
02763 /*@}*/
02764 
02765 /*!
02766  * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
02767  *
02768  * Occurs when detecting one of following time-out conditions. Busy time-out for
02769  * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
02770  *
02771  * Values:
02772  * - 0 - No error.
02773  * - 1 - Time out.
02774  */
02775 /*@{*/
02776 #define BP_SDHC_IRQSTAT_DTOE (20U)         /*!< Bit position for SDHC_IRQSTAT_DTOE. */
02777 #define BM_SDHC_IRQSTAT_DTOE (0x00100000U) /*!< Bit mask for SDHC_IRQSTAT_DTOE. */
02778 #define BS_SDHC_IRQSTAT_DTOE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DTOE. */
02779 
02780 /*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
02781 #define BR_SDHC_IRQSTAT_DTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE))
02782 
02783 /*! @brief Format value for bitfield SDHC_IRQSTAT_DTOE. */
02784 #define BF_SDHC_IRQSTAT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DTOE) & BM_SDHC_IRQSTAT_DTOE)
02785 
02786 /*! @brief Set the DTOE field to a new value. */
02787 #define BW_SDHC_IRQSTAT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE) = (v))
02788 /*@}*/
02789 
02790 /*!
02791  * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
02792  *
02793  * Occurs when detecting a CRC error when transferring read data, which uses the
02794  * DAT line, or when detecting the Write CRC status having a value other than
02795  * 010.
02796  *
02797  * Values:
02798  * - 0 - No error.
02799  * - 1 - Error.
02800  */
02801 /*@{*/
02802 #define BP_SDHC_IRQSTAT_DCE  (21U)         /*!< Bit position for SDHC_IRQSTAT_DCE. */
02803 #define BM_SDHC_IRQSTAT_DCE  (0x00200000U) /*!< Bit mask for SDHC_IRQSTAT_DCE. */
02804 #define BS_SDHC_IRQSTAT_DCE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DCE. */
02805 
02806 /*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
02807 #define BR_SDHC_IRQSTAT_DCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE))
02808 
02809 /*! @brief Format value for bitfield SDHC_IRQSTAT_DCE. */
02810 #define BF_SDHC_IRQSTAT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DCE) & BM_SDHC_IRQSTAT_DCE)
02811 
02812 /*! @brief Set the DCE field to a new value. */
02813 #define BW_SDHC_IRQSTAT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE) = (v))
02814 /*@}*/
02815 
02816 /*!
02817  * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
02818  *
02819  * Occurs either when detecting 0 at the end bit position of read data, which
02820  * uses the DAT line, or at the end bit position of the CRC.
02821  *
02822  * Values:
02823  * - 0 - No error.
02824  * - 1 - Error.
02825  */
02826 /*@{*/
02827 #define BP_SDHC_IRQSTAT_DEBE (22U)         /*!< Bit position for SDHC_IRQSTAT_DEBE. */
02828 #define BM_SDHC_IRQSTAT_DEBE (0x00400000U) /*!< Bit mask for SDHC_IRQSTAT_DEBE. */
02829 #define BS_SDHC_IRQSTAT_DEBE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DEBE. */
02830 
02831 /*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
02832 #define BR_SDHC_IRQSTAT_DEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE))
02833 
02834 /*! @brief Format value for bitfield SDHC_IRQSTAT_DEBE. */
02835 #define BF_SDHC_IRQSTAT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DEBE) & BM_SDHC_IRQSTAT_DEBE)
02836 
02837 /*! @brief Set the DEBE field to a new value. */
02838 #define BW_SDHC_IRQSTAT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE) = (v))
02839 /*@}*/
02840 
02841 /*!
02842  * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
02843  *
02844  * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
02845  * register has changed from 0 to 1. This bit is set to 1, not only when the errors
02846  * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
02847  * previous command error.
02848  *
02849  * Values:
02850  * - 0 - No error.
02851  * - 1 - Error.
02852  */
02853 /*@{*/
02854 #define BP_SDHC_IRQSTAT_AC12E (24U)        /*!< Bit position for SDHC_IRQSTAT_AC12E. */
02855 #define BM_SDHC_IRQSTAT_AC12E (0x01000000U) /*!< Bit mask for SDHC_IRQSTAT_AC12E. */
02856 #define BS_SDHC_IRQSTAT_AC12E (1U)         /*!< Bit field size in bits for SDHC_IRQSTAT_AC12E. */
02857 
02858 /*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
02859 #define BR_SDHC_IRQSTAT_AC12E(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E))
02860 
02861 /*! @brief Format value for bitfield SDHC_IRQSTAT_AC12E. */
02862 #define BF_SDHC_IRQSTAT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_AC12E) & BM_SDHC_IRQSTAT_AC12E)
02863 
02864 /*! @brief Set the AC12E field to a new value. */
02865 #define BW_SDHC_IRQSTAT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E) = (v))
02866 /*@}*/
02867 
02868 /*!
02869  * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
02870  *
02871  * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
02872  * some error occurs in the data transfer. This error can be caused by either
02873  * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
02874  * Address register is the next fetch address where the error occurs. Because any
02875  * error corrupts the whole data block, the host driver shall restart the transfer
02876  * from the corrupted block boundary. The address of the block boundary can be
02877  * calculated either from the current DSADDR value or from the remaining number of
02878  * blocks and the block size.
02879  *
02880  * Values:
02881  * - 0 - No error.
02882  * - 1 - Error.
02883  */
02884 /*@{*/
02885 #define BP_SDHC_IRQSTAT_DMAE (28U)         /*!< Bit position for SDHC_IRQSTAT_DMAE. */
02886 #define BM_SDHC_IRQSTAT_DMAE (0x10000000U) /*!< Bit mask for SDHC_IRQSTAT_DMAE. */
02887 #define BS_SDHC_IRQSTAT_DMAE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DMAE. */
02888 
02889 /*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
02890 #define BR_SDHC_IRQSTAT_DMAE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE))
02891 
02892 /*! @brief Format value for bitfield SDHC_IRQSTAT_DMAE. */
02893 #define BF_SDHC_IRQSTAT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DMAE) & BM_SDHC_IRQSTAT_DMAE)
02894 
02895 /*! @brief Set the DMAE field to a new value. */
02896 #define BW_SDHC_IRQSTAT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE) = (v))
02897 /*@}*/
02898 
02899 /*******************************************************************************
02900  * HW_SDHC_IRQSTATEN - Interrupt Status Enable register
02901  ******************************************************************************/
02902 
02903 /*!
02904  * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
02905  *
02906  * Reset value: 0x117F013FU
02907  *
02908  * Setting the bits in this register to 1 enables the corresponding interrupt
02909  * status to be set by the specified event. If any bit is cleared, the
02910  * corresponding interrupt status bit is also cleared, that is, when the bit in this register
02911  * is cleared, the corresponding bit in interrupt status register is always 0.
02912  * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
02913  * card interrupt signal during the interrupt period and hold its value in the
02914  * flip-flop. There will be some delays on the card interrupt, asserted from the card,
02915  * to the time the host system is informed. To detect a CMD line conflict, the
02916  * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
02917  */
02918 typedef union _hw_sdhc_irqstaten
02919 {
02920     uint32_t U;
02921     struct _hw_sdhc_irqstaten_bitfields
02922     {
02923         uint32_t CCSEN : 1;            /*!< [0] Command Complete Status Enable */
02924         uint32_t TCSEN : 1;            /*!< [1] Transfer Complete Status Enable */
02925         uint32_t BGESEN : 1;           /*!< [2] Block Gap Event Status Enable */
02926         uint32_t DINTSEN : 1;          /*!< [3] DMA Interrupt Status Enable */
02927         uint32_t BWRSEN : 1;           /*!< [4] Buffer Write Ready Status Enable */
02928         uint32_t BRRSEN : 1;           /*!< [5] Buffer Read Ready Status Enable */
02929         uint32_t CINSEN : 1;           /*!< [6] Card Insertion Status Enable */
02930         uint32_t CRMSEN : 1;           /*!< [7] Card Removal Status Enable */
02931         uint32_t CINTSEN : 1;          /*!< [8] Card Interrupt Status Enable */
02932         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
02933         uint32_t CTOESEN : 1;          /*!< [16] Command Timeout Error Status Enable */
02934         uint32_t CCESEN : 1;           /*!< [17] Command CRC Error Status Enable */
02935         uint32_t CEBESEN : 1;          /*!< [18] Command End Bit Error Status Enable */
02936         uint32_t CIESEN : 1;           /*!< [19] Command Index Error Status Enable */
02937         uint32_t DTOESEN : 1;          /*!< [20] Data Timeout Error Status Enable */
02938         uint32_t DCESEN : 1;           /*!< [21] Data CRC Error Status Enable */
02939         uint32_t DEBESEN : 1;          /*!< [22] Data End Bit Error Status Enable */
02940         uint32_t RESERVED1 : 1;        /*!< [23]  */
02941         uint32_t AC12ESEN : 1;         /*!< [24] Auto CMD12 Error Status Enable */
02942         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
02943         uint32_t DMAESEN : 1;          /*!< [28] DMA Error Status Enable */
02944         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02945     } B;
02946 } hw_sdhc_irqstaten_t;
02947 
02948 /*!
02949  * @name Constants and macros for entire SDHC_IRQSTATEN register
02950  */
02951 /*@{*/
02952 #define HW_SDHC_IRQSTATEN_ADDR(x) ((x) + 0x34U)
02953 
02954 #define HW_SDHC_IRQSTATEN(x)     (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR(x))
02955 #define HW_SDHC_IRQSTATEN_RD(x)  (HW_SDHC_IRQSTATEN(x).U)
02956 #define HW_SDHC_IRQSTATEN_WR(x, v) (HW_SDHC_IRQSTATEN(x).U = (v))
02957 #define HW_SDHC_IRQSTATEN_SET(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) |  (v)))
02958 #define HW_SDHC_IRQSTATEN_CLR(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) & ~(v)))
02959 #define HW_SDHC_IRQSTATEN_TOG(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) ^  (v)))
02960 /*@}*/
02961 
02962 /*
02963  * Constants & macros for individual SDHC_IRQSTATEN bitfields
02964  */
02965 
02966 /*!
02967  * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
02968  *
02969  * Values:
02970  * - 0 - Masked
02971  * - 1 - Enabled
02972  */
02973 /*@{*/
02974 #define BP_SDHC_IRQSTATEN_CCSEN (0U)       /*!< Bit position for SDHC_IRQSTATEN_CCSEN. */
02975 #define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) /*!< Bit mask for SDHC_IRQSTATEN_CCSEN. */
02976 #define BS_SDHC_IRQSTATEN_CCSEN (1U)       /*!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN. */
02977 
02978 /*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
02979 #define BR_SDHC_IRQSTATEN_CCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN))
02980 
02981 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN. */
02982 #define BF_SDHC_IRQSTATEN_CCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCSEN) & BM_SDHC_IRQSTATEN_CCSEN)
02983 
02984 /*! @brief Set the CCSEN field to a new value. */
02985 #define BW_SDHC_IRQSTATEN_CCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN) = (v))
02986 /*@}*/
02987 
02988 /*!
02989  * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
02990  *
02991  * Values:
02992  * - 0 - Masked
02993  * - 1 - Enabled
02994  */
02995 /*@{*/
02996 #define BP_SDHC_IRQSTATEN_TCSEN (1U)       /*!< Bit position for SDHC_IRQSTATEN_TCSEN. */
02997 #define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) /*!< Bit mask for SDHC_IRQSTATEN_TCSEN. */
02998 #define BS_SDHC_IRQSTATEN_TCSEN (1U)       /*!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN. */
02999 
03000 /*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
03001 #define BR_SDHC_IRQSTATEN_TCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN))
03002 
03003 /*! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN. */
03004 #define BF_SDHC_IRQSTATEN_TCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_TCSEN) & BM_SDHC_IRQSTATEN_TCSEN)
03005 
03006 /*! @brief Set the TCSEN field to a new value. */
03007 #define BW_SDHC_IRQSTATEN_TCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN) = (v))
03008 /*@}*/
03009 
03010 /*!
03011  * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
03012  *
03013  * Values:
03014  * - 0 - Masked
03015  * - 1 - Enabled
03016  */
03017 /*@{*/
03018 #define BP_SDHC_IRQSTATEN_BGESEN (2U)      /*!< Bit position for SDHC_IRQSTATEN_BGESEN. */
03019 #define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) /*!< Bit mask for SDHC_IRQSTATEN_BGESEN. */
03020 #define BS_SDHC_IRQSTATEN_BGESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN. */
03021 
03022 /*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
03023 #define BR_SDHC_IRQSTATEN_BGESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN))
03024 
03025 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN. */
03026 #define BF_SDHC_IRQSTATEN_BGESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BGESEN) & BM_SDHC_IRQSTATEN_BGESEN)
03027 
03028 /*! @brief Set the BGESEN field to a new value. */
03029 #define BW_SDHC_IRQSTATEN_BGESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN) = (v))
03030 /*@}*/
03031 
03032 /*!
03033  * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
03034  *
03035  * Values:
03036  * - 0 - Masked
03037  * - 1 - Enabled
03038  */
03039 /*@{*/
03040 #define BP_SDHC_IRQSTATEN_DINTSEN (3U)     /*!< Bit position for SDHC_IRQSTATEN_DINTSEN. */
03041 #define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) /*!< Bit mask for SDHC_IRQSTATEN_DINTSEN. */
03042 #define BS_SDHC_IRQSTATEN_DINTSEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN. */
03043 
03044 /*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
03045 #define BR_SDHC_IRQSTATEN_DINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN))
03046 
03047 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN. */
03048 #define BF_SDHC_IRQSTATEN_DINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DINTSEN) & BM_SDHC_IRQSTATEN_DINTSEN)
03049 
03050 /*! @brief Set the DINTSEN field to a new value. */
03051 #define BW_SDHC_IRQSTATEN_DINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN) = (v))
03052 /*@}*/
03053 
03054 /*!
03055  * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
03056  *
03057  * Values:
03058  * - 0 - Masked
03059  * - 1 - Enabled
03060  */
03061 /*@{*/
03062 #define BP_SDHC_IRQSTATEN_BWRSEN (4U)      /*!< Bit position for SDHC_IRQSTATEN_BWRSEN. */
03063 #define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) /*!< Bit mask for SDHC_IRQSTATEN_BWRSEN. */
03064 #define BS_SDHC_IRQSTATEN_BWRSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN. */
03065 
03066 /*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
03067 #define BR_SDHC_IRQSTATEN_BWRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN))
03068 
03069 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN. */
03070 #define BF_SDHC_IRQSTATEN_BWRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BWRSEN) & BM_SDHC_IRQSTATEN_BWRSEN)
03071 
03072 /*! @brief Set the BWRSEN field to a new value. */
03073 #define BW_SDHC_IRQSTATEN_BWRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN) = (v))
03074 /*@}*/
03075 
03076 /*!
03077  * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
03078  *
03079  * Values:
03080  * - 0 - Masked
03081  * - 1 - Enabled
03082  */
03083 /*@{*/
03084 #define BP_SDHC_IRQSTATEN_BRRSEN (5U)      /*!< Bit position for SDHC_IRQSTATEN_BRRSEN. */
03085 #define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) /*!< Bit mask for SDHC_IRQSTATEN_BRRSEN. */
03086 #define BS_SDHC_IRQSTATEN_BRRSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN. */
03087 
03088 /*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
03089 #define BR_SDHC_IRQSTATEN_BRRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN))
03090 
03091 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN. */
03092 #define BF_SDHC_IRQSTATEN_BRRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BRRSEN) & BM_SDHC_IRQSTATEN_BRRSEN)
03093 
03094 /*! @brief Set the BRRSEN field to a new value. */
03095 #define BW_SDHC_IRQSTATEN_BRRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN) = (v))
03096 /*@}*/
03097 
03098 /*!
03099  * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
03100  *
03101  * Values:
03102  * - 0 - Masked
03103  * - 1 - Enabled
03104  */
03105 /*@{*/
03106 #define BP_SDHC_IRQSTATEN_CINSEN (6U)      /*!< Bit position for SDHC_IRQSTATEN_CINSEN. */
03107 #define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) /*!< Bit mask for SDHC_IRQSTATEN_CINSEN. */
03108 #define BS_SDHC_IRQSTATEN_CINSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN. */
03109 
03110 /*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
03111 #define BR_SDHC_IRQSTATEN_CINSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN))
03112 
03113 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN. */
03114 #define BF_SDHC_IRQSTATEN_CINSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINSEN) & BM_SDHC_IRQSTATEN_CINSEN)
03115 
03116 /*! @brief Set the CINSEN field to a new value. */
03117 #define BW_SDHC_IRQSTATEN_CINSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN) = (v))
03118 /*@}*/
03119 
03120 /*!
03121  * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
03122  *
03123  * Values:
03124  * - 0 - Masked
03125  * - 1 - Enabled
03126  */
03127 /*@{*/
03128 #define BP_SDHC_IRQSTATEN_CRMSEN (7U)      /*!< Bit position for SDHC_IRQSTATEN_CRMSEN. */
03129 #define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) /*!< Bit mask for SDHC_IRQSTATEN_CRMSEN. */
03130 #define BS_SDHC_IRQSTATEN_CRMSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN. */
03131 
03132 /*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
03133 #define BR_SDHC_IRQSTATEN_CRMSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN))
03134 
03135 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN. */
03136 #define BF_SDHC_IRQSTATEN_CRMSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CRMSEN) & BM_SDHC_IRQSTATEN_CRMSEN)
03137 
03138 /*! @brief Set the CRMSEN field to a new value. */
03139 #define BW_SDHC_IRQSTATEN_CRMSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN) = (v))
03140 /*@}*/
03141 
03142 /*!
03143  * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
03144  *
03145  * If this bit is set to 0, the SDHC will clear the interrupt request to the
03146  * system. The card interrupt detection is stopped when this bit is cleared and
03147  * restarted when this bit is set to 1. The host driver must clear the this bit
03148  * before servicing the card interrupt and must set this bit again after all interrupt
03149  * requests from the card are cleared to prevent inadvertent interrupts.
03150  *
03151  * Values:
03152  * - 0 - Masked
03153  * - 1 - Enabled
03154  */
03155 /*@{*/
03156 #define BP_SDHC_IRQSTATEN_CINTSEN (8U)     /*!< Bit position for SDHC_IRQSTATEN_CINTSEN. */
03157 #define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) /*!< Bit mask for SDHC_IRQSTATEN_CINTSEN. */
03158 #define BS_SDHC_IRQSTATEN_CINTSEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN. */
03159 
03160 /*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
03161 #define BR_SDHC_IRQSTATEN_CINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN))
03162 
03163 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN. */
03164 #define BF_SDHC_IRQSTATEN_CINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINTSEN) & BM_SDHC_IRQSTATEN_CINTSEN)
03165 
03166 /*! @brief Set the CINTSEN field to a new value. */
03167 #define BW_SDHC_IRQSTATEN_CINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN) = (v))
03168 /*@}*/
03169 
03170 /*!
03171  * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
03172  *
03173  * Values:
03174  * - 0 - Masked
03175  * - 1 - Enabled
03176  */
03177 /*@{*/
03178 #define BP_SDHC_IRQSTATEN_CTOESEN (16U)    /*!< Bit position for SDHC_IRQSTATEN_CTOESEN. */
03179 #define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) /*!< Bit mask for SDHC_IRQSTATEN_CTOESEN. */
03180 #define BS_SDHC_IRQSTATEN_CTOESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN. */
03181 
03182 /*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
03183 #define BR_SDHC_IRQSTATEN_CTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN))
03184 
03185 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN. */
03186 #define BF_SDHC_IRQSTATEN_CTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CTOESEN) & BM_SDHC_IRQSTATEN_CTOESEN)
03187 
03188 /*! @brief Set the CTOESEN field to a new value. */
03189 #define BW_SDHC_IRQSTATEN_CTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN) = (v))
03190 /*@}*/
03191 
03192 /*!
03193  * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
03194  *
03195  * Values:
03196  * - 0 - Masked
03197  * - 1 - Enabled
03198  */
03199 /*@{*/
03200 #define BP_SDHC_IRQSTATEN_CCESEN (17U)     /*!< Bit position for SDHC_IRQSTATEN_CCESEN. */
03201 #define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) /*!< Bit mask for SDHC_IRQSTATEN_CCESEN. */
03202 #define BS_SDHC_IRQSTATEN_CCESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN. */
03203 
03204 /*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
03205 #define BR_SDHC_IRQSTATEN_CCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN))
03206 
03207 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN. */
03208 #define BF_SDHC_IRQSTATEN_CCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCESEN) & BM_SDHC_IRQSTATEN_CCESEN)
03209 
03210 /*! @brief Set the CCESEN field to a new value. */
03211 #define BW_SDHC_IRQSTATEN_CCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN) = (v))
03212 /*@}*/
03213 
03214 /*!
03215  * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
03216  *
03217  * Values:
03218  * - 0 - Masked
03219  * - 1 - Enabled
03220  */
03221 /*@{*/
03222 #define BP_SDHC_IRQSTATEN_CEBESEN (18U)    /*!< Bit position for SDHC_IRQSTATEN_CEBESEN. */
03223 #define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) /*!< Bit mask for SDHC_IRQSTATEN_CEBESEN. */
03224 #define BS_SDHC_IRQSTATEN_CEBESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN. */
03225 
03226 /*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
03227 #define BR_SDHC_IRQSTATEN_CEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN))
03228 
03229 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN. */
03230 #define BF_SDHC_IRQSTATEN_CEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CEBESEN) & BM_SDHC_IRQSTATEN_CEBESEN)
03231 
03232 /*! @brief Set the CEBESEN field to a new value. */
03233 #define BW_SDHC_IRQSTATEN_CEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN) = (v))
03234 /*@}*/
03235 
03236 /*!
03237  * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
03238  *
03239  * Values:
03240  * - 0 - Masked
03241  * - 1 - Enabled
03242  */
03243 /*@{*/
03244 #define BP_SDHC_IRQSTATEN_CIESEN (19U)     /*!< Bit position for SDHC_IRQSTATEN_CIESEN. */
03245 #define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) /*!< Bit mask for SDHC_IRQSTATEN_CIESEN. */
03246 #define BS_SDHC_IRQSTATEN_CIESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN. */
03247 
03248 /*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
03249 #define BR_SDHC_IRQSTATEN_CIESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN))
03250 
03251 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN. */
03252 #define BF_SDHC_IRQSTATEN_CIESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CIESEN) & BM_SDHC_IRQSTATEN_CIESEN)
03253 
03254 /*! @brief Set the CIESEN field to a new value. */
03255 #define BW_SDHC_IRQSTATEN_CIESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN) = (v))
03256 /*@}*/
03257 
03258 /*!
03259  * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
03260  *
03261  * Values:
03262  * - 0 - Masked
03263  * - 1 - Enabled
03264  */
03265 /*@{*/
03266 #define BP_SDHC_IRQSTATEN_DTOESEN (20U)    /*!< Bit position for SDHC_IRQSTATEN_DTOESEN. */
03267 #define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) /*!< Bit mask for SDHC_IRQSTATEN_DTOESEN. */
03268 #define BS_SDHC_IRQSTATEN_DTOESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN. */
03269 
03270 /*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
03271 #define BR_SDHC_IRQSTATEN_DTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN))
03272 
03273 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN. */
03274 #define BF_SDHC_IRQSTATEN_DTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DTOESEN) & BM_SDHC_IRQSTATEN_DTOESEN)
03275 
03276 /*! @brief Set the DTOESEN field to a new value. */
03277 #define BW_SDHC_IRQSTATEN_DTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN) = (v))
03278 /*@}*/
03279 
03280 /*!
03281  * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
03282  *
03283  * Values:
03284  * - 0 - Masked
03285  * - 1 - Enabled
03286  */
03287 /*@{*/
03288 #define BP_SDHC_IRQSTATEN_DCESEN (21U)     /*!< Bit position for SDHC_IRQSTATEN_DCESEN. */
03289 #define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) /*!< Bit mask for SDHC_IRQSTATEN_DCESEN. */
03290 #define BS_SDHC_IRQSTATEN_DCESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN. */
03291 
03292 /*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
03293 #define BR_SDHC_IRQSTATEN_DCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN))
03294 
03295 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN. */
03296 #define BF_SDHC_IRQSTATEN_DCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DCESEN) & BM_SDHC_IRQSTATEN_DCESEN)
03297 
03298 /*! @brief Set the DCESEN field to a new value. */
03299 #define BW_SDHC_IRQSTATEN_DCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN) = (v))
03300 /*@}*/
03301 
03302 /*!
03303  * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
03304  *
03305  * Values:
03306  * - 0 - Masked
03307  * - 1 - Enabled
03308  */
03309 /*@{*/
03310 #define BP_SDHC_IRQSTATEN_DEBESEN (22U)    /*!< Bit position for SDHC_IRQSTATEN_DEBESEN. */
03311 #define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) /*!< Bit mask for SDHC_IRQSTATEN_DEBESEN. */
03312 #define BS_SDHC_IRQSTATEN_DEBESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN. */
03313 
03314 /*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
03315 #define BR_SDHC_IRQSTATEN_DEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN))
03316 
03317 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN. */
03318 #define BF_SDHC_IRQSTATEN_DEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DEBESEN) & BM_SDHC_IRQSTATEN_DEBESEN)
03319 
03320 /*! @brief Set the DEBESEN field to a new value. */
03321 #define BW_SDHC_IRQSTATEN_DEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN) = (v))
03322 /*@}*/
03323 
03324 /*!
03325  * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
03326  *
03327  * Values:
03328  * - 0 - Masked
03329  * - 1 - Enabled
03330  */
03331 /*@{*/
03332 #define BP_SDHC_IRQSTATEN_AC12ESEN (24U)   /*!< Bit position for SDHC_IRQSTATEN_AC12ESEN. */
03333 #define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) /*!< Bit mask for SDHC_IRQSTATEN_AC12ESEN. */
03334 #define BS_SDHC_IRQSTATEN_AC12ESEN (1U)    /*!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN. */
03335 
03336 /*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
03337 #define BR_SDHC_IRQSTATEN_AC12ESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN))
03338 
03339 /*! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN. */
03340 #define BF_SDHC_IRQSTATEN_AC12ESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_AC12ESEN) & BM_SDHC_IRQSTATEN_AC12ESEN)
03341 
03342 /*! @brief Set the AC12ESEN field to a new value. */
03343 #define BW_SDHC_IRQSTATEN_AC12ESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
03344 /*@}*/
03345 
03346 /*!
03347  * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
03348  *
03349  * Values:
03350  * - 0 - Masked
03351  * - 1 - Enabled
03352  */
03353 /*@{*/
03354 #define BP_SDHC_IRQSTATEN_DMAESEN (28U)    /*!< Bit position for SDHC_IRQSTATEN_DMAESEN. */
03355 #define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) /*!< Bit mask for SDHC_IRQSTATEN_DMAESEN. */
03356 #define BS_SDHC_IRQSTATEN_DMAESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN. */
03357 
03358 /*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
03359 #define BR_SDHC_IRQSTATEN_DMAESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN))
03360 
03361 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN. */
03362 #define BF_SDHC_IRQSTATEN_DMAESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DMAESEN) & BM_SDHC_IRQSTATEN_DMAESEN)
03363 
03364 /*! @brief Set the DMAESEN field to a new value. */
03365 #define BW_SDHC_IRQSTATEN_DMAESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN) = (v))
03366 /*@}*/
03367 
03368 /*******************************************************************************
03369  * HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
03370  ******************************************************************************/
03371 
03372 /*!
03373  * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
03374  *
03375  * Reset value: 0x00000000U
03376  *
03377  * This register is used to select which interrupt status is indicated to the
03378  * host system as the interrupt. All of these status bits share the same interrupt
03379  * line. Setting any of these bits to 1 enables interrupt generation. The
03380  * corresponding status register bit will generate an interrupt when the corresponding
03381  * interrupt signal enable bit is set.
03382  */
03383 typedef union _hw_sdhc_irqsigen
03384 {
03385     uint32_t U;
03386     struct _hw_sdhc_irqsigen_bitfields
03387     {
03388         uint32_t CCIEN : 1;            /*!< [0] Command Complete Interrupt Enable */
03389         uint32_t TCIEN : 1;            /*!< [1] Transfer Complete Interrupt Enable */
03390         uint32_t BGEIEN : 1;           /*!< [2] Block Gap Event Interrupt Enable */
03391         uint32_t DINTIEN : 1;          /*!< [3] DMA Interrupt Enable */
03392         uint32_t BWRIEN : 1;           /*!< [4] Buffer Write Ready Interrupt Enable */
03393         uint32_t BRRIEN : 1;           /*!< [5] Buffer Read Ready Interrupt Enable */
03394         uint32_t CINSIEN : 1;          /*!< [6] Card Insertion Interrupt Enable */
03395         uint32_t CRMIEN : 1;           /*!< [7] Card Removal Interrupt Enable */
03396         uint32_t CINTIEN : 1;          /*!< [8] Card Interrupt Enable */
03397         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
03398         uint32_t CTOEIEN : 1;          /*!< [16] Command Timeout Error Interrupt
03399                                         * Enable */
03400         uint32_t CCEIEN : 1;           /*!< [17] Command CRC Error Interrupt Enable */
03401         uint32_t CEBEIEN : 1;          /*!< [18] Command End Bit Error Interrupt
03402                                         * Enable */
03403         uint32_t CIEIEN : 1;           /*!< [19] Command Index Error Interrupt Enable */
03404         uint32_t DTOEIEN : 1;          /*!< [20] Data Timeout Error Interrupt Enable */
03405         uint32_t DCEIEN : 1;           /*!< [21] Data CRC Error Interrupt Enable */
03406         uint32_t DEBEIEN : 1;          /*!< [22] Data End Bit Error Interrupt Enable */
03407         uint32_t RESERVED1 : 1;        /*!< [23]  */
03408         uint32_t AC12EIEN : 1;         /*!< [24] Auto CMD12 Error Interrupt Enable */
03409         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
03410         uint32_t DMAEIEN : 1;          /*!< [28] DMA Error Interrupt Enable */
03411         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
03412     } B;
03413 } hw_sdhc_irqsigen_t;
03414 
03415 /*!
03416  * @name Constants and macros for entire SDHC_IRQSIGEN register
03417  */
03418 /*@{*/
03419 #define HW_SDHC_IRQSIGEN_ADDR(x) ((x) + 0x38U)
03420 
03421 #define HW_SDHC_IRQSIGEN(x)      (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR(x))
03422 #define HW_SDHC_IRQSIGEN_RD(x)   (HW_SDHC_IRQSIGEN(x).U)
03423 #define HW_SDHC_IRQSIGEN_WR(x, v) (HW_SDHC_IRQSIGEN(x).U = (v))
03424 #define HW_SDHC_IRQSIGEN_SET(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) |  (v)))
03425 #define HW_SDHC_IRQSIGEN_CLR(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) & ~(v)))
03426 #define HW_SDHC_IRQSIGEN_TOG(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) ^  (v)))
03427 /*@}*/
03428 
03429 /*
03430  * Constants & macros for individual SDHC_IRQSIGEN bitfields
03431  */
03432 
03433 /*!
03434  * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
03435  *
03436  * Values:
03437  * - 0 - Masked
03438  * - 1 - Enabled
03439  */
03440 /*@{*/
03441 #define BP_SDHC_IRQSIGEN_CCIEN (0U)        /*!< Bit position for SDHC_IRQSIGEN_CCIEN. */
03442 #define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) /*!< Bit mask for SDHC_IRQSIGEN_CCIEN. */
03443 #define BS_SDHC_IRQSIGEN_CCIEN (1U)        /*!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN. */
03444 
03445 /*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
03446 #define BR_SDHC_IRQSIGEN_CCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN))
03447 
03448 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN. */
03449 #define BF_SDHC_IRQSIGEN_CCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCIEN) & BM_SDHC_IRQSIGEN_CCIEN)
03450 
03451 /*! @brief Set the CCIEN field to a new value. */
03452 #define BW_SDHC_IRQSIGEN_CCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN) = (v))
03453 /*@}*/
03454 
03455 /*!
03456  * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
03457  *
03458  * Values:
03459  * - 0 - Masked
03460  * - 1 - Enabled
03461  */
03462 /*@{*/
03463 #define BP_SDHC_IRQSIGEN_TCIEN (1U)        /*!< Bit position for SDHC_IRQSIGEN_TCIEN. */
03464 #define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) /*!< Bit mask for SDHC_IRQSIGEN_TCIEN. */
03465 #define BS_SDHC_IRQSIGEN_TCIEN (1U)        /*!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN. */
03466 
03467 /*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
03468 #define BR_SDHC_IRQSIGEN_TCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN))
03469 
03470 /*! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN. */
03471 #define BF_SDHC_IRQSIGEN_TCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_TCIEN) & BM_SDHC_IRQSIGEN_TCIEN)
03472 
03473 /*! @brief Set the TCIEN field to a new value. */
03474 #define BW_SDHC_IRQSIGEN_TCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN) = (v))
03475 /*@}*/
03476 
03477 /*!
03478  * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
03479  *
03480  * Values:
03481  * - 0 - Masked
03482  * - 1 - Enabled
03483  */
03484 /*@{*/
03485 #define BP_SDHC_IRQSIGEN_BGEIEN (2U)       /*!< Bit position for SDHC_IRQSIGEN_BGEIEN. */
03486 #define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) /*!< Bit mask for SDHC_IRQSIGEN_BGEIEN. */
03487 #define BS_SDHC_IRQSIGEN_BGEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN. */
03488 
03489 /*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
03490 #define BR_SDHC_IRQSIGEN_BGEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN))
03491 
03492 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN. */
03493 #define BF_SDHC_IRQSIGEN_BGEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BGEIEN) & BM_SDHC_IRQSIGEN_BGEIEN)
03494 
03495 /*! @brief Set the BGEIEN field to a new value. */
03496 #define BW_SDHC_IRQSIGEN_BGEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN) = (v))
03497 /*@}*/
03498 
03499 /*!
03500  * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
03501  *
03502  * Values:
03503  * - 0 - Masked
03504  * - 1 - Enabled
03505  */
03506 /*@{*/
03507 #define BP_SDHC_IRQSIGEN_DINTIEN (3U)      /*!< Bit position for SDHC_IRQSIGEN_DINTIEN. */
03508 #define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) /*!< Bit mask for SDHC_IRQSIGEN_DINTIEN. */
03509 #define BS_SDHC_IRQSIGEN_DINTIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN. */
03510 
03511 /*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
03512 #define BR_SDHC_IRQSIGEN_DINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN))
03513 
03514 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN. */
03515 #define BF_SDHC_IRQSIGEN_DINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DINTIEN) & BM_SDHC_IRQSIGEN_DINTIEN)
03516 
03517 /*! @brief Set the DINTIEN field to a new value. */
03518 #define BW_SDHC_IRQSIGEN_DINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN) = (v))
03519 /*@}*/
03520 
03521 /*!
03522  * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
03523  *
03524  * Values:
03525  * - 0 - Masked
03526  * - 1 - Enabled
03527  */
03528 /*@{*/
03529 #define BP_SDHC_IRQSIGEN_BWRIEN (4U)       /*!< Bit position for SDHC_IRQSIGEN_BWRIEN. */
03530 #define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) /*!< Bit mask for SDHC_IRQSIGEN_BWRIEN. */
03531 #define BS_SDHC_IRQSIGEN_BWRIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN. */
03532 
03533 /*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
03534 #define BR_SDHC_IRQSIGEN_BWRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN))
03535 
03536 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN. */
03537 #define BF_SDHC_IRQSIGEN_BWRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BWRIEN) & BM_SDHC_IRQSIGEN_BWRIEN)
03538 
03539 /*! @brief Set the BWRIEN field to a new value. */
03540 #define BW_SDHC_IRQSIGEN_BWRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN) = (v))
03541 /*@}*/
03542 
03543 /*!
03544  * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
03545  *
03546  * Values:
03547  * - 0 - Masked
03548  * - 1 - Enabled
03549  */
03550 /*@{*/
03551 #define BP_SDHC_IRQSIGEN_BRRIEN (5U)       /*!< Bit position for SDHC_IRQSIGEN_BRRIEN. */
03552 #define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) /*!< Bit mask for SDHC_IRQSIGEN_BRRIEN. */
03553 #define BS_SDHC_IRQSIGEN_BRRIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN. */
03554 
03555 /*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
03556 #define BR_SDHC_IRQSIGEN_BRRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN))
03557 
03558 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN. */
03559 #define BF_SDHC_IRQSIGEN_BRRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BRRIEN) & BM_SDHC_IRQSIGEN_BRRIEN)
03560 
03561 /*! @brief Set the BRRIEN field to a new value. */
03562 #define BW_SDHC_IRQSIGEN_BRRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN) = (v))
03563 /*@}*/
03564 
03565 /*!
03566  * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
03567  *
03568  * Values:
03569  * - 0 - Masked
03570  * - 1 - Enabled
03571  */
03572 /*@{*/
03573 #define BP_SDHC_IRQSIGEN_CINSIEN (6U)      /*!< Bit position for SDHC_IRQSIGEN_CINSIEN. */
03574 #define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) /*!< Bit mask for SDHC_IRQSIGEN_CINSIEN. */
03575 #define BS_SDHC_IRQSIGEN_CINSIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN. */
03576 
03577 /*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
03578 #define BR_SDHC_IRQSIGEN_CINSIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN))
03579 
03580 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN. */
03581 #define BF_SDHC_IRQSIGEN_CINSIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINSIEN) & BM_SDHC_IRQSIGEN_CINSIEN)
03582 
03583 /*! @brief Set the CINSIEN field to a new value. */
03584 #define BW_SDHC_IRQSIGEN_CINSIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN) = (v))
03585 /*@}*/
03586 
03587 /*!
03588  * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
03589  *
03590  * Values:
03591  * - 0 - Masked
03592  * - 1 - Enabled
03593  */
03594 /*@{*/
03595 #define BP_SDHC_IRQSIGEN_CRMIEN (7U)       /*!< Bit position for SDHC_IRQSIGEN_CRMIEN. */
03596 #define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) /*!< Bit mask for SDHC_IRQSIGEN_CRMIEN. */
03597 #define BS_SDHC_IRQSIGEN_CRMIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN. */
03598 
03599 /*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
03600 #define BR_SDHC_IRQSIGEN_CRMIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN))
03601 
03602 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN. */
03603 #define BF_SDHC_IRQSIGEN_CRMIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CRMIEN) & BM_SDHC_IRQSIGEN_CRMIEN)
03604 
03605 /*! @brief Set the CRMIEN field to a new value. */
03606 #define BW_SDHC_IRQSIGEN_CRMIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN) = (v))
03607 /*@}*/
03608 
03609 /*!
03610  * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
03611  *
03612  * Values:
03613  * - 0 - Masked
03614  * - 1 - Enabled
03615  */
03616 /*@{*/
03617 #define BP_SDHC_IRQSIGEN_CINTIEN (8U)      /*!< Bit position for SDHC_IRQSIGEN_CINTIEN. */
03618 #define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) /*!< Bit mask for SDHC_IRQSIGEN_CINTIEN. */
03619 #define BS_SDHC_IRQSIGEN_CINTIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN. */
03620 
03621 /*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
03622 #define BR_SDHC_IRQSIGEN_CINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN))
03623 
03624 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN. */
03625 #define BF_SDHC_IRQSIGEN_CINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINTIEN) & BM_SDHC_IRQSIGEN_CINTIEN)
03626 
03627 /*! @brief Set the CINTIEN field to a new value. */
03628 #define BW_SDHC_IRQSIGEN_CINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN) = (v))
03629 /*@}*/
03630 
03631 /*!
03632  * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
03633  *
03634  * Values:
03635  * - 0 - Masked
03636  * - 1 - Enabled
03637  */
03638 /*@{*/
03639 #define BP_SDHC_IRQSIGEN_CTOEIEN (16U)     /*!< Bit position for SDHC_IRQSIGEN_CTOEIEN. */
03640 #define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) /*!< Bit mask for SDHC_IRQSIGEN_CTOEIEN. */
03641 #define BS_SDHC_IRQSIGEN_CTOEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN. */
03642 
03643 /*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
03644 #define BR_SDHC_IRQSIGEN_CTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN))
03645 
03646 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN. */
03647 #define BF_SDHC_IRQSIGEN_CTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CTOEIEN) & BM_SDHC_IRQSIGEN_CTOEIEN)
03648 
03649 /*! @brief Set the CTOEIEN field to a new value. */
03650 #define BW_SDHC_IRQSIGEN_CTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
03651 /*@}*/
03652 
03653 /*!
03654  * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
03655  *
03656  * Values:
03657  * - 0 - Masked
03658  * - 1 - Enabled
03659  */
03660 /*@{*/
03661 #define BP_SDHC_IRQSIGEN_CCEIEN (17U)      /*!< Bit position for SDHC_IRQSIGEN_CCEIEN. */
03662 #define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) /*!< Bit mask for SDHC_IRQSIGEN_CCEIEN. */
03663 #define BS_SDHC_IRQSIGEN_CCEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN. */
03664 
03665 /*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
03666 #define BR_SDHC_IRQSIGEN_CCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN))
03667 
03668 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN. */
03669 #define BF_SDHC_IRQSIGEN_CCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCEIEN) & BM_SDHC_IRQSIGEN_CCEIEN)
03670 
03671 /*! @brief Set the CCEIEN field to a new value. */
03672 #define BW_SDHC_IRQSIGEN_CCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN) = (v))
03673 /*@}*/
03674 
03675 /*!
03676  * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
03677  *
03678  * Values:
03679  * - 0 - Masked
03680  * - 1 - Enabled
03681  */
03682 /*@{*/
03683 #define BP_SDHC_IRQSIGEN_CEBEIEN (18U)     /*!< Bit position for SDHC_IRQSIGEN_CEBEIEN. */
03684 #define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) /*!< Bit mask for SDHC_IRQSIGEN_CEBEIEN. */
03685 #define BS_SDHC_IRQSIGEN_CEBEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN. */
03686 
03687 /*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
03688 #define BR_SDHC_IRQSIGEN_CEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN))
03689 
03690 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN. */
03691 #define BF_SDHC_IRQSIGEN_CEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CEBEIEN) & BM_SDHC_IRQSIGEN_CEBEIEN)
03692 
03693 /*! @brief Set the CEBEIEN field to a new value. */
03694 #define BW_SDHC_IRQSIGEN_CEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
03695 /*@}*/
03696 
03697 /*!
03698  * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
03699  *
03700  * Values:
03701  * - 0 - Masked
03702  * - 1 - Enabled
03703  */
03704 /*@{*/
03705 #define BP_SDHC_IRQSIGEN_CIEIEN (19U)      /*!< Bit position for SDHC_IRQSIGEN_CIEIEN. */
03706 #define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) /*!< Bit mask for SDHC_IRQSIGEN_CIEIEN. */
03707 #define BS_SDHC_IRQSIGEN_CIEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN. */
03708 
03709 /*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
03710 #define BR_SDHC_IRQSIGEN_CIEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN))
03711 
03712 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN. */
03713 #define BF_SDHC_IRQSIGEN_CIEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CIEIEN) & BM_SDHC_IRQSIGEN_CIEIEN)
03714 
03715 /*! @brief Set the CIEIEN field to a new value. */
03716 #define BW_SDHC_IRQSIGEN_CIEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN) = (v))
03717 /*@}*/
03718 
03719 /*!
03720  * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
03721  *
03722  * Values:
03723  * - 0 - Masked
03724  * - 1 - Enabled
03725  */
03726 /*@{*/
03727 #define BP_SDHC_IRQSIGEN_DTOEIEN (20U)     /*!< Bit position for SDHC_IRQSIGEN_DTOEIEN. */
03728 #define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) /*!< Bit mask for SDHC_IRQSIGEN_DTOEIEN. */
03729 #define BS_SDHC_IRQSIGEN_DTOEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN. */
03730 
03731 /*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
03732 #define BR_SDHC_IRQSIGEN_DTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN))
03733 
03734 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN. */
03735 #define BF_SDHC_IRQSIGEN_DTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DTOEIEN) & BM_SDHC_IRQSIGEN_DTOEIEN)
03736 
03737 /*! @brief Set the DTOEIEN field to a new value. */
03738 #define BW_SDHC_IRQSIGEN_DTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
03739 /*@}*/
03740 
03741 /*!
03742  * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
03743  *
03744  * Values:
03745  * - 0 - Masked
03746  * - 1 - Enabled
03747  */
03748 /*@{*/
03749 #define BP_SDHC_IRQSIGEN_DCEIEN (21U)      /*!< Bit position for SDHC_IRQSIGEN_DCEIEN. */
03750 #define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) /*!< Bit mask for SDHC_IRQSIGEN_DCEIEN. */
03751 #define BS_SDHC_IRQSIGEN_DCEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN. */
03752 
03753 /*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
03754 #define BR_SDHC_IRQSIGEN_DCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN))
03755 
03756 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN. */
03757 #define BF_SDHC_IRQSIGEN_DCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DCEIEN) & BM_SDHC_IRQSIGEN_DCEIEN)
03758 
03759 /*! @brief Set the DCEIEN field to a new value. */
03760 #define BW_SDHC_IRQSIGEN_DCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN) = (v))
03761 /*@}*/
03762 
03763 /*!
03764  * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
03765  *
03766  * Values:
03767  * - 0 - Masked
03768  * - 1 - Enabled
03769  */
03770 /*@{*/
03771 #define BP_SDHC_IRQSIGEN_DEBEIEN (22U)     /*!< Bit position for SDHC_IRQSIGEN_DEBEIEN. */
03772 #define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) /*!< Bit mask for SDHC_IRQSIGEN_DEBEIEN. */
03773 #define BS_SDHC_IRQSIGEN_DEBEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN. */
03774 
03775 /*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
03776 #define BR_SDHC_IRQSIGEN_DEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN))
03777 
03778 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN. */
03779 #define BF_SDHC_IRQSIGEN_DEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DEBEIEN) & BM_SDHC_IRQSIGEN_DEBEIEN)
03780 
03781 /*! @brief Set the DEBEIEN field to a new value. */
03782 #define BW_SDHC_IRQSIGEN_DEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
03783 /*@}*/
03784 
03785 /*!
03786  * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
03787  *
03788  * Values:
03789  * - 0 - Masked
03790  * - 1 - Enabled
03791  */
03792 /*@{*/
03793 #define BP_SDHC_IRQSIGEN_AC12EIEN (24U)    /*!< Bit position for SDHC_IRQSIGEN_AC12EIEN. */
03794 #define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) /*!< Bit mask for SDHC_IRQSIGEN_AC12EIEN. */
03795 #define BS_SDHC_IRQSIGEN_AC12EIEN (1U)     /*!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN. */
03796 
03797 /*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
03798 #define BR_SDHC_IRQSIGEN_AC12EIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN))
03799 
03800 /*! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN. */
03801 #define BF_SDHC_IRQSIGEN_AC12EIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_AC12EIEN) & BM_SDHC_IRQSIGEN_AC12EIEN)
03802 
03803 /*! @brief Set the AC12EIEN field to a new value. */
03804 #define BW_SDHC_IRQSIGEN_AC12EIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
03805 /*@}*/
03806 
03807 /*!
03808  * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
03809  *
03810  * Values:
03811  * - 0 - Masked
03812  * - 1 - Enabled
03813  */
03814 /*@{*/
03815 #define BP_SDHC_IRQSIGEN_DMAEIEN (28U)     /*!< Bit position for SDHC_IRQSIGEN_DMAEIEN. */
03816 #define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) /*!< Bit mask for SDHC_IRQSIGEN_DMAEIEN. */
03817 #define BS_SDHC_IRQSIGEN_DMAEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN. */
03818 
03819 /*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
03820 #define BR_SDHC_IRQSIGEN_DMAEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN))
03821 
03822 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN. */
03823 #define BF_SDHC_IRQSIGEN_DMAEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DMAEIEN) & BM_SDHC_IRQSIGEN_DMAEIEN)
03824 
03825 /*! @brief Set the DMAEIEN field to a new value. */
03826 #define BW_SDHC_IRQSIGEN_DMAEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
03827 /*@}*/
03828 
03829 /*******************************************************************************
03830  * HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
03831  ******************************************************************************/
03832 
03833 /*!
03834  * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
03835  *
03836  * Reset value: 0x00000000U
03837  *
03838  * When the AC12ESEN bit in the Status register is set, the host driver shall
03839  * check this register to identify what kind of error the Auto CMD12 indicated.
03840  * This register is valid only when the Auto CMD12 Error status bit is set. The
03841  * following table shows the relationship between the Auto CMGD12 CRC error and the
03842  * Auto CMD12 command timeout error. Relationship between Command CRC Error and
03843  * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
03844  * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
03845  * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
03846  * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
03847  * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
03848  * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
03849  * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
03850  * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
03851  * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
03852  * command that can't be issued. Clear bit 7 if there is no command to issue. The
03853  * timing for generating the auto CMD12 error and writing to the command register
03854  * are asynchronous. After that, bit 7 shall be sampled when the driver is not
03855  * writing to the command register. So it is suggested to read this register only
03856  * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
03857  * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
03858  * error does not generate an interrupt.
03859  */
03860 typedef union _hw_sdhc_ac12err
03861 {
03862     uint32_t U;
03863     struct _hw_sdhc_ac12err_bitfields
03864     {
03865         uint32_t AC12NE : 1;           /*!< [0] Auto CMD12 Not Executed */
03866         uint32_t AC12TOE : 1;          /*!< [1] Auto CMD12 Timeout Error */
03867         uint32_t AC12EBE : 1;          /*!< [2] Auto CMD12 End Bit Error */
03868         uint32_t AC12CE : 1;           /*!< [3] Auto CMD12 CRC Error */
03869         uint32_t AC12IE : 1;           /*!< [4] Auto CMD12 Index Error */
03870         uint32_t RESERVED0 : 2;        /*!< [6:5]  */
03871         uint32_t CNIBAC12E : 1;        /*!< [7] Command Not Issued By Auto CMD12
03872                                         * Error */
03873         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
03874     } B;
03875 } hw_sdhc_ac12err_t;
03876 
03877 /*!
03878  * @name Constants and macros for entire SDHC_AC12ERR register
03879  */
03880 /*@{*/
03881 #define HW_SDHC_AC12ERR_ADDR(x)  ((x) + 0x3CU)
03882 
03883 #define HW_SDHC_AC12ERR(x)       (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR(x))
03884 #define HW_SDHC_AC12ERR_RD(x)    (HW_SDHC_AC12ERR(x).U)
03885 /*@}*/
03886 
03887 /*
03888  * Constants & macros for individual SDHC_AC12ERR bitfields
03889  */
03890 
03891 /*!
03892  * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
03893  *
03894  * If memory multiple block data transfer is not started, due to a command
03895  * error, this bit is not set because it is not necessary to issue an auto CMD12.
03896  * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
03897  * multiple block data transfer due to some error. If this bit is set to 1, other
03898  * error status bits (1-4) have no meaning.
03899  *
03900  * Values:
03901  * - 0 - Executed.
03902  * - 1 - Not executed.
03903  */
03904 /*@{*/
03905 #define BP_SDHC_AC12ERR_AC12NE (0U)        /*!< Bit position for SDHC_AC12ERR_AC12NE. */
03906 #define BM_SDHC_AC12ERR_AC12NE (0x00000001U) /*!< Bit mask for SDHC_AC12ERR_AC12NE. */
03907 #define BS_SDHC_AC12ERR_AC12NE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12NE. */
03908 
03909 /*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
03910 #define BR_SDHC_AC12ERR_AC12NE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12NE))
03911 /*@}*/
03912 
03913 /*!
03914  * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
03915  *
03916  * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
03917  * the command. If this bit is set to 1, the other error status bits (2-4) have
03918  * no meaning.
03919  *
03920  * Values:
03921  * - 0 - No error.
03922  * - 1 - Time out.
03923  */
03924 /*@{*/
03925 #define BP_SDHC_AC12ERR_AC12TOE (1U)       /*!< Bit position for SDHC_AC12ERR_AC12TOE. */
03926 #define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_AC12ERR_AC12TOE. */
03927 #define BS_SDHC_AC12ERR_AC12TOE (1U)       /*!< Bit field size in bits for SDHC_AC12ERR_AC12TOE. */
03928 
03929 /*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
03930 #define BR_SDHC_AC12ERR_AC12TOE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12TOE))
03931 /*@}*/
03932 
03933 /*!
03934  * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
03935  *
03936  * Occurs when detecting that the end bit of command response is 0 which must be
03937  * 1.
03938  *
03939  * Values:
03940  * - 0 - No error.
03941  * - 1 - End bit error generated.
03942  */
03943 /*@{*/
03944 #define BP_SDHC_AC12ERR_AC12EBE (2U)       /*!< Bit position for SDHC_AC12ERR_AC12EBE. */
03945 #define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) /*!< Bit mask for SDHC_AC12ERR_AC12EBE. */
03946 #define BS_SDHC_AC12ERR_AC12EBE (1U)       /*!< Bit field size in bits for SDHC_AC12ERR_AC12EBE. */
03947 
03948 /*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
03949 #define BR_SDHC_AC12ERR_AC12EBE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12EBE))
03950 /*@}*/
03951 
03952 /*!
03953  * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
03954  *
03955  * Occurs when detecting a CRC error in the command response.
03956  *
03957  * Values:
03958  * - 0 - No CRC error.
03959  * - 1 - CRC error met in Auto CMD12 response.
03960  */
03961 /*@{*/
03962 #define BP_SDHC_AC12ERR_AC12CE (3U)        /*!< Bit position for SDHC_AC12ERR_AC12CE. */
03963 #define BM_SDHC_AC12ERR_AC12CE (0x00000008U) /*!< Bit mask for SDHC_AC12ERR_AC12CE. */
03964 #define BS_SDHC_AC12ERR_AC12CE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12CE. */
03965 
03966 /*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
03967 #define BR_SDHC_AC12ERR_AC12CE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12CE))
03968 /*@}*/
03969 
03970 /*!
03971  * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
03972  *
03973  * Occurs if the command index error occurs in response to a command.
03974  *
03975  * Values:
03976  * - 0 - No error.
03977  * - 1 - Error, the CMD index in response is not CMD12.
03978  */
03979 /*@{*/
03980 #define BP_SDHC_AC12ERR_AC12IE (4U)        /*!< Bit position for SDHC_AC12ERR_AC12IE. */
03981 #define BM_SDHC_AC12ERR_AC12IE (0x00000010U) /*!< Bit mask for SDHC_AC12ERR_AC12IE. */
03982 #define BS_SDHC_AC12ERR_AC12IE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12IE. */
03983 
03984 /*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
03985 #define BR_SDHC_AC12ERR_AC12IE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12IE))
03986 /*@}*/
03987 
03988 /*!
03989  * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
03990  *
03991  * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
03992  * error (D04-D01) in this register.
03993  *
03994  * Values:
03995  * - 0 - No error.
03996  * - 1 - Not issued.
03997  */
03998 /*@{*/
03999 #define BP_SDHC_AC12ERR_CNIBAC12E (7U)     /*!< Bit position for SDHC_AC12ERR_CNIBAC12E. */
04000 #define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_AC12ERR_CNIBAC12E. */
04001 #define BS_SDHC_AC12ERR_CNIBAC12E (1U)     /*!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E. */
04002 
04003 /*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
04004 #define BR_SDHC_AC12ERR_CNIBAC12E(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_CNIBAC12E))
04005 /*@}*/
04006 
04007 /*******************************************************************************
04008  * HW_SDHC_HTCAPBLT - Host Controller Capabilities
04009  ******************************************************************************/
04010 
04011 /*!
04012  * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
04013  *
04014  * Reset value: 0x07F30000U
04015  *
04016  * This register provides the host driver with information specific to the SDHC
04017  * implementation. The value in this register is the power-on-reset value, and
04018  * does not change with a software reset. Any write to this register is ignored.
04019  */
04020 typedef union _hw_sdhc_htcapblt
04021 {
04022     uint32_t U;
04023     struct _hw_sdhc_htcapblt_bitfields
04024     {
04025         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
04026         uint32_t MBL : 3;              /*!< [18:16] Max Block Length */
04027         uint32_t RESERVED1 : 1;        /*!< [19]  */
04028         uint32_t ADMAS : 1;            /*!< [20] ADMA Support */
04029         uint32_t HSS : 1;              /*!< [21] High Speed Support */
04030         uint32_t DMAS : 1;             /*!< [22] DMA Support */
04031         uint32_t SRS : 1;              /*!< [23] Suspend/Resume Support */
04032         uint32_t VS33 : 1;             /*!< [24] Voltage Support 3.3 V */
04033         uint32_t RESERVED2 : 7;        /*!< [31:25]  */
04034     } B;
04035 } hw_sdhc_htcapblt_t;
04036 
04037 /*!
04038  * @name Constants and macros for entire SDHC_HTCAPBLT register
04039  */
04040 /*@{*/
04041 #define HW_SDHC_HTCAPBLT_ADDR(x) ((x) + 0x40U)
04042 
04043 #define HW_SDHC_HTCAPBLT(x)      (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR(x))
04044 #define HW_SDHC_HTCAPBLT_RD(x)   (HW_SDHC_HTCAPBLT(x).U)
04045 /*@}*/
04046 
04047 /*
04048  * Constants & macros for individual SDHC_HTCAPBLT bitfields
04049  */
04050 
04051 /*!
04052  * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
04053  *
04054  * This value indicates the maximum block size that the host driver can read and
04055  * write to the buffer in the SDHC. The buffer shall transfer block size without
04056  * wait cycles.
04057  *
04058  * Values:
04059  * - 000 - 512 bytes
04060  * - 001 - 1024 bytes
04061  * - 010 - 2048 bytes
04062  * - 011 - 4096 bytes
04063  */
04064 /*@{*/
04065 #define BP_SDHC_HTCAPBLT_MBL (16U)         /*!< Bit position for SDHC_HTCAPBLT_MBL. */
04066 #define BM_SDHC_HTCAPBLT_MBL (0x00070000U) /*!< Bit mask for SDHC_HTCAPBLT_MBL. */
04067 #define BS_SDHC_HTCAPBLT_MBL (3U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_MBL. */
04068 
04069 /*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
04070 #define BR_SDHC_HTCAPBLT_MBL(x) (HW_SDHC_HTCAPBLT(x).B.MBL)
04071 /*@}*/
04072 
04073 /*!
04074  * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
04075  *
04076  * This bit indicates whether the SDHC supports the ADMA feature.
04077  *
04078  * Values:
04079  * - 0 - Advanced DMA not supported.
04080  * - 1 - Advanced DMA supported.
04081  */
04082 /*@{*/
04083 #define BP_SDHC_HTCAPBLT_ADMAS (20U)       /*!< Bit position for SDHC_HTCAPBLT_ADMAS. */
04084 #define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) /*!< Bit mask for SDHC_HTCAPBLT_ADMAS. */
04085 #define BS_SDHC_HTCAPBLT_ADMAS (1U)        /*!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS. */
04086 
04087 /*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
04088 #define BR_SDHC_HTCAPBLT_ADMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_ADMAS))
04089 /*@}*/
04090 
04091 /*!
04092  * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
04093  *
04094  * This bit indicates whether the SDHC supports high speed mode and the host
04095  * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
04096  *
04097  * Values:
04098  * - 0 - High speed not supported.
04099  * - 1 - High speed supported.
04100  */
04101 /*@{*/
04102 #define BP_SDHC_HTCAPBLT_HSS (21U)         /*!< Bit position for SDHC_HTCAPBLT_HSS. */
04103 #define BM_SDHC_HTCAPBLT_HSS (0x00200000U) /*!< Bit mask for SDHC_HTCAPBLT_HSS. */
04104 #define BS_SDHC_HTCAPBLT_HSS (1U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_HSS. */
04105 
04106 /*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
04107 #define BR_SDHC_HTCAPBLT_HSS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_HSS))
04108 /*@}*/
04109 
04110 /*!
04111  * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
04112  *
04113  * This bit indicates whether the SDHC is capable of using the internal DMA to
04114  * transfer data between system memory and the data buffer directly.
04115  *
04116  * Values:
04117  * - 0 - DMA not supported.
04118  * - 1 - DMA supported.
04119  */
04120 /*@{*/
04121 #define BP_SDHC_HTCAPBLT_DMAS (22U)        /*!< Bit position for SDHC_HTCAPBLT_DMAS. */
04122 #define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) /*!< Bit mask for SDHC_HTCAPBLT_DMAS. */
04123 #define BS_SDHC_HTCAPBLT_DMAS (1U)         /*!< Bit field size in bits for SDHC_HTCAPBLT_DMAS. */
04124 
04125 /*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
04126 #define BR_SDHC_HTCAPBLT_DMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_DMAS))
04127 /*@}*/
04128 
04129 /*!
04130  * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
04131  *
04132  * This bit indicates whether the SDHC supports suspend / resume functionality.
04133  * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
04134  * are not supported, and the host driver shall not issue either suspend or
04135  * resume commands.
04136  *
04137  * Values:
04138  * - 0 - Not supported.
04139  * - 1 - Supported.
04140  */
04141 /*@{*/
04142 #define BP_SDHC_HTCAPBLT_SRS (23U)         /*!< Bit position for SDHC_HTCAPBLT_SRS. */
04143 #define BM_SDHC_HTCAPBLT_SRS (0x00800000U) /*!< Bit mask for SDHC_HTCAPBLT_SRS. */
04144 #define BS_SDHC_HTCAPBLT_SRS (1U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_SRS. */
04145 
04146 /*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
04147 #define BR_SDHC_HTCAPBLT_SRS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_SRS))
04148 /*@}*/
04149 
04150 /*!
04151  * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
04152  *
04153  * This bit shall depend on the host system ability.
04154  *
04155  * Values:
04156  * - 0 - 3.3 V not supported.
04157  * - 1 - 3.3 V supported.
04158  */
04159 /*@{*/
04160 #define BP_SDHC_HTCAPBLT_VS33 (24U)        /*!< Bit position for SDHC_HTCAPBLT_VS33. */
04161 #define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) /*!< Bit mask for SDHC_HTCAPBLT_VS33. */
04162 #define BS_SDHC_HTCAPBLT_VS33 (1U)         /*!< Bit field size in bits for SDHC_HTCAPBLT_VS33. */
04163 
04164 /*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
04165 #define BR_SDHC_HTCAPBLT_VS33(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_VS33))
04166 /*@}*/
04167 
04168 /*******************************************************************************
04169  * HW_SDHC_WML - Watermark Level Register
04170  ******************************************************************************/
04171 
04172 /*!
04173  * @brief HW_SDHC_WML - Watermark Level Register (RW)
04174  *
04175  * Reset value: 0x00100010U
04176  *
04177  * Both write and read watermark levels (FIFO threshold) are configurable. There
04178  * value can range from 1 to 128 words. Both write and read burst lengths are
04179  * also configurable. There value can range from 1 to 31 words.
04180  */
04181 typedef union _hw_sdhc_wml
04182 {
04183     uint32_t U;
04184     struct _hw_sdhc_wml_bitfields
04185     {
04186         uint32_t RDWML : 8;            /*!< [7:0] Read Watermark Level */
04187         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
04188         uint32_t WRWML : 8;            /*!< [23:16] Write Watermark Level */
04189         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
04190     } B;
04191 } hw_sdhc_wml_t;
04192 
04193 /*!
04194  * @name Constants and macros for entire SDHC_WML register
04195  */
04196 /*@{*/
04197 #define HW_SDHC_WML_ADDR(x)      ((x) + 0x44U)
04198 
04199 #define HW_SDHC_WML(x)           (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR(x))
04200 #define HW_SDHC_WML_RD(x)        (HW_SDHC_WML(x).U)
04201 #define HW_SDHC_WML_WR(x, v)     (HW_SDHC_WML(x).U = (v))
04202 #define HW_SDHC_WML_SET(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) |  (v)))
04203 #define HW_SDHC_WML_CLR(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) & ~(v)))
04204 #define HW_SDHC_WML_TOG(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) ^  (v)))
04205 /*@}*/
04206 
04207 /*
04208  * Constants & macros for individual SDHC_WML bitfields
04209  */
04210 
04211 /*!
04212  * @name Register SDHC_WML, field RDWML[7:0] (RW)
04213  *
04214  * The number of words used as the watermark level (FIFO threshold) in a DMA
04215  * read operation. Also the number of words as a sequence of read bursts in
04216  * back-to-back mode. The maximum legal value for the read water mark level is 128.
04217  */
04218 /*@{*/
04219 #define BP_SDHC_WML_RDWML    (0U)          /*!< Bit position for SDHC_WML_RDWML. */
04220 #define BM_SDHC_WML_RDWML    (0x000000FFU) /*!< Bit mask for SDHC_WML_RDWML. */
04221 #define BS_SDHC_WML_RDWML    (8U)          /*!< Bit field size in bits for SDHC_WML_RDWML. */
04222 
04223 /*! @brief Read current value of the SDHC_WML_RDWML field. */
04224 #define BR_SDHC_WML_RDWML(x) (HW_SDHC_WML(x).B.RDWML)
04225 
04226 /*! @brief Format value for bitfield SDHC_WML_RDWML. */
04227 #define BF_SDHC_WML_RDWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_RDWML) & BM_SDHC_WML_RDWML)
04228 
04229 /*! @brief Set the RDWML field to a new value. */
04230 #define BW_SDHC_WML_RDWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
04231 /*@}*/
04232 
04233 /*!
04234  * @name Register SDHC_WML, field WRWML[23:16] (RW)
04235  *
04236  * The number of words used as the watermark level (FIFO threshold) in a DMA
04237  * write operation. Also the number of words as a sequence of write bursts in
04238  * back-to-back mode. The maximum legal value for the write watermark level is 128.
04239  */
04240 /*@{*/
04241 #define BP_SDHC_WML_WRWML    (16U)         /*!< Bit position for SDHC_WML_WRWML. */
04242 #define BM_SDHC_WML_WRWML    (0x00FF0000U) /*!< Bit mask for SDHC_WML_WRWML. */
04243 #define BS_SDHC_WML_WRWML    (8U)          /*!< Bit field size in bits for SDHC_WML_WRWML. */
04244 
04245 /*! @brief Read current value of the SDHC_WML_WRWML field. */
04246 #define BR_SDHC_WML_WRWML(x) (HW_SDHC_WML(x).B.WRWML)
04247 
04248 /*! @brief Format value for bitfield SDHC_WML_WRWML. */
04249 #define BF_SDHC_WML_WRWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_WRWML) & BM_SDHC_WML_WRWML)
04250 
04251 /*! @brief Set the WRWML field to a new value. */
04252 #define BW_SDHC_WML_WRWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
04253 /*@}*/
04254 
04255 /*******************************************************************************
04256  * HW_SDHC_FEVT - Force Event register
04257  ******************************************************************************/
04258 
04259 /*!
04260  * @brief HW_SDHC_FEVT - Force Event register (WO)
04261  *
04262  * Reset value: 0x00000000U
04263  *
04264  * The Force Event (FEVT) register is not a physically implemented register.
04265  * Rather, it is an address at which the Interrupt Status register can be written if
04266  * the corresponding bit of the Interrupt Status Enable register is set. This
04267  * register is a write only register and writing 0 to it has no effect. Writing 1
04268  * to this register actually sets the corresponding bit of Interrupt Status
04269  * register. A read from this register always results in 0's. To change the
04270  * corresponding status bits in the interrupt status register, make sure to set
04271  * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
04272  * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
04273  * normal interrupt. The interrupt service routine may skip polling the card
04274  * interrupt factor as the interrupt is selfcleared.
04275  */
04276 typedef union _hw_sdhc_fevt
04277 {
04278     uint32_t U;
04279     struct _hw_sdhc_fevt_bitfields
04280     {
04281         uint32_t AC12NE : 1;           /*!< [0] Force Event Auto Command 12 Not
04282                                         * Executed */
04283         uint32_t AC12TOE : 1;          /*!< [1] Force Event Auto Command 12 Time Out
04284                                         * Error */
04285         uint32_t AC12CE : 1;           /*!< [2] Force Event Auto Command 12 CRC Error */
04286         uint32_t AC12EBE : 1;          /*!< [3] Force Event Auto Command 12 End Bit
04287                                         * Error */
04288         uint32_t AC12IE : 1;           /*!< [4] Force Event Auto Command 12 Index Error
04289                                         * */
04290         uint32_t RESERVED0 : 2;        /*!< [6:5]  */
04291         uint32_t CNIBAC12E : 1;        /*!< [7] Force Event Command Not Executed By
04292                                         * Auto Command 12 Error */
04293         uint32_t RESERVED1 : 8;        /*!< [15:8]  */
04294         uint32_t CTOE : 1;             /*!< [16] Force Event Command Time Out Error */
04295         uint32_t CCE : 1;              /*!< [17] Force Event Command CRC Error */
04296         uint32_t CEBE : 1;             /*!< [18] Force Event Command End Bit Error */
04297         uint32_t CIE : 1;              /*!< [19] Force Event Command Index Error */
04298         uint32_t DTOE : 1;             /*!< [20] Force Event Data Time Out Error */
04299         uint32_t DCE : 1;              /*!< [21] Force Event Data CRC Error */
04300         uint32_t DEBE : 1;             /*!< [22] Force Event Data End Bit Error */
04301         uint32_t RESERVED2 : 1;        /*!< [23]  */
04302         uint32_t AC12E : 1;            /*!< [24] Force Event Auto Command 12 Error */
04303         uint32_t RESERVED3 : 3;        /*!< [27:25]  */
04304         uint32_t DMAE : 1;             /*!< [28] Force Event DMA Error */
04305         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
04306         uint32_t CINT : 1;             /*!< [31] Force Event Card Interrupt */
04307     } B;
04308 } hw_sdhc_fevt_t;
04309 
04310 /*!
04311  * @name Constants and macros for entire SDHC_FEVT register
04312  */
04313 /*@{*/
04314 #define HW_SDHC_FEVT_ADDR(x)     ((x) + 0x50U)
04315 
04316 #define HW_SDHC_FEVT(x)          (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR(x))
04317 #define HW_SDHC_FEVT_RD(x)       (HW_SDHC_FEVT(x).U)
04318 #define HW_SDHC_FEVT_WR(x, v)    (HW_SDHC_FEVT(x).U = (v))
04319 /*@}*/
04320 
04321 /*
04322  * Constants & macros for individual SDHC_FEVT bitfields
04323  */
04324 
04325 /*!
04326  * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
04327  *
04328  * Forces AC12ERR[AC12NE] to be set.
04329  */
04330 /*@{*/
04331 #define BP_SDHC_FEVT_AC12NE  (0U)          /*!< Bit position for SDHC_FEVT_AC12NE. */
04332 #define BM_SDHC_FEVT_AC12NE  (0x00000001U) /*!< Bit mask for SDHC_FEVT_AC12NE. */
04333 #define BS_SDHC_FEVT_AC12NE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12NE. */
04334 
04335 /*! @brief Format value for bitfield SDHC_FEVT_AC12NE. */
04336 #define BF_SDHC_FEVT_AC12NE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12NE) & BM_SDHC_FEVT_AC12NE)
04337 
04338 /*! @brief Set the AC12NE field to a new value. */
04339 #define BW_SDHC_FEVT_AC12NE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12NE) = (v))
04340 /*@}*/
04341 
04342 /*!
04343  * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
04344  *
04345  * Forces AC12ERR[AC12TOE] to be set.
04346  */
04347 /*@{*/
04348 #define BP_SDHC_FEVT_AC12TOE (1U)          /*!< Bit position for SDHC_FEVT_AC12TOE. */
04349 #define BM_SDHC_FEVT_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_FEVT_AC12TOE. */
04350 #define BS_SDHC_FEVT_AC12TOE (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12TOE. */
04351 
04352 /*! @brief Format value for bitfield SDHC_FEVT_AC12TOE. */
04353 #define BF_SDHC_FEVT_AC12TOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12TOE) & BM_SDHC_FEVT_AC12TOE)
04354 
04355 /*! @brief Set the AC12TOE field to a new value. */
04356 #define BW_SDHC_FEVT_AC12TOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12TOE) = (v))
04357 /*@}*/
04358 
04359 /*!
04360  * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
04361  *
04362  * Forces AC12ERR[AC12CE] to be set.
04363  */
04364 /*@{*/
04365 #define BP_SDHC_FEVT_AC12CE  (2U)          /*!< Bit position for SDHC_FEVT_AC12CE. */
04366 #define BM_SDHC_FEVT_AC12CE  (0x00000004U) /*!< Bit mask for SDHC_FEVT_AC12CE. */
04367 #define BS_SDHC_FEVT_AC12CE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12CE. */
04368 
04369 /*! @brief Format value for bitfield SDHC_FEVT_AC12CE. */
04370 #define BF_SDHC_FEVT_AC12CE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12CE) & BM_SDHC_FEVT_AC12CE)
04371 
04372 /*! @brief Set the AC12CE field to a new value. */
04373 #define BW_SDHC_FEVT_AC12CE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12CE) = (v))
04374 /*@}*/
04375 
04376 /*!
04377  * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
04378  *
04379  * Forces AC12ERR[AC12EBE] to be set.
04380  */
04381 /*@{*/
04382 #define BP_SDHC_FEVT_AC12EBE (3U)          /*!< Bit position for SDHC_FEVT_AC12EBE. */
04383 #define BM_SDHC_FEVT_AC12EBE (0x00000008U) /*!< Bit mask for SDHC_FEVT_AC12EBE. */
04384 #define BS_SDHC_FEVT_AC12EBE (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12EBE. */
04385 
04386 /*! @brief Format value for bitfield SDHC_FEVT_AC12EBE. */
04387 #define BF_SDHC_FEVT_AC12EBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12EBE) & BM_SDHC_FEVT_AC12EBE)
04388 
04389 /*! @brief Set the AC12EBE field to a new value. */
04390 #define BW_SDHC_FEVT_AC12EBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12EBE) = (v))
04391 /*@}*/
04392 
04393 /*!
04394  * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
04395  *
04396  * Forces AC12ERR[AC12IE] to be set.
04397  */
04398 /*@{*/
04399 #define BP_SDHC_FEVT_AC12IE  (4U)          /*!< Bit position for SDHC_FEVT_AC12IE. */
04400 #define BM_SDHC_FEVT_AC12IE  (0x00000010U) /*!< Bit mask for SDHC_FEVT_AC12IE. */
04401 #define BS_SDHC_FEVT_AC12IE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12IE. */
04402 
04403 /*! @brief Format value for bitfield SDHC_FEVT_AC12IE. */
04404 #define BF_SDHC_FEVT_AC12IE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12IE) & BM_SDHC_FEVT_AC12IE)
04405 
04406 /*! @brief Set the AC12IE field to a new value. */
04407 #define BW_SDHC_FEVT_AC12IE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12IE) = (v))
04408 /*@}*/
04409 
04410 /*!
04411  * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
04412  *
04413  * Forces AC12ERR[CNIBAC12E] to be set.
04414  */
04415 /*@{*/
04416 #define BP_SDHC_FEVT_CNIBAC12E (7U)        /*!< Bit position for SDHC_FEVT_CNIBAC12E. */
04417 #define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_FEVT_CNIBAC12E. */
04418 #define BS_SDHC_FEVT_CNIBAC12E (1U)        /*!< Bit field size in bits for SDHC_FEVT_CNIBAC12E. */
04419 
04420 /*! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E. */
04421 #define BF_SDHC_FEVT_CNIBAC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CNIBAC12E) & BM_SDHC_FEVT_CNIBAC12E)
04422 
04423 /*! @brief Set the CNIBAC12E field to a new value. */
04424 #define BW_SDHC_FEVT_CNIBAC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CNIBAC12E) = (v))
04425 /*@}*/
04426 
04427 /*!
04428  * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
04429  *
04430  * Forces IRQSTAT[CTOE] to be set.
04431  */
04432 /*@{*/
04433 #define BP_SDHC_FEVT_CTOE    (16U)         /*!< Bit position for SDHC_FEVT_CTOE. */
04434 #define BM_SDHC_FEVT_CTOE    (0x00010000U) /*!< Bit mask for SDHC_FEVT_CTOE. */
04435 #define BS_SDHC_FEVT_CTOE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CTOE. */
04436 
04437 /*! @brief Format value for bitfield SDHC_FEVT_CTOE. */
04438 #define BF_SDHC_FEVT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CTOE) & BM_SDHC_FEVT_CTOE)
04439 
04440 /*! @brief Set the CTOE field to a new value. */
04441 #define BW_SDHC_FEVT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CTOE) = (v))
04442 /*@}*/
04443 
04444 /*!
04445  * @name Register SDHC_FEVT, field CCE[17] (WORZ)
04446  *
04447  * Forces IRQSTAT[CCE] to be set.
04448  */
04449 /*@{*/
04450 #define BP_SDHC_FEVT_CCE     (17U)         /*!< Bit position for SDHC_FEVT_CCE. */
04451 #define BM_SDHC_FEVT_CCE     (0x00020000U) /*!< Bit mask for SDHC_FEVT_CCE. */
04452 #define BS_SDHC_FEVT_CCE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_CCE. */
04453 
04454 /*! @brief Format value for bitfield SDHC_FEVT_CCE. */
04455 #define BF_SDHC_FEVT_CCE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CCE) & BM_SDHC_FEVT_CCE)
04456 
04457 /*! @brief Set the CCE field to a new value. */
04458 #define BW_SDHC_FEVT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CCE) = (v))
04459 /*@}*/
04460 
04461 /*!
04462  * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
04463  *
04464  * Forces IRQSTAT[CEBE] to be set.
04465  */
04466 /*@{*/
04467 #define BP_SDHC_FEVT_CEBE    (18U)         /*!< Bit position for SDHC_FEVT_CEBE. */
04468 #define BM_SDHC_FEVT_CEBE    (0x00040000U) /*!< Bit mask for SDHC_FEVT_CEBE. */
04469 #define BS_SDHC_FEVT_CEBE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CEBE. */
04470 
04471 /*! @brief Format value for bitfield SDHC_FEVT_CEBE. */
04472 #define BF_SDHC_FEVT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CEBE) & BM_SDHC_FEVT_CEBE)
04473 
04474 /*! @brief Set the CEBE field to a new value. */
04475 #define BW_SDHC_FEVT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CEBE) = (v))
04476 /*@}*/
04477 
04478 /*!
04479  * @name Register SDHC_FEVT, field CIE[19] (WORZ)
04480  *
04481  * Forces IRQSTAT[CCE] to be set.
04482  */
04483 /*@{*/
04484 #define BP_SDHC_FEVT_CIE     (19U)         /*!< Bit position for SDHC_FEVT_CIE. */
04485 #define BM_SDHC_FEVT_CIE     (0x00080000U) /*!< Bit mask for SDHC_FEVT_CIE. */
04486 #define BS_SDHC_FEVT_CIE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_CIE. */
04487 
04488 /*! @brief Format value for bitfield SDHC_FEVT_CIE. */
04489 #define BF_SDHC_FEVT_CIE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CIE) & BM_SDHC_FEVT_CIE)
04490 
04491 /*! @brief Set the CIE field to a new value. */
04492 #define BW_SDHC_FEVT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CIE) = (v))
04493 /*@}*/
04494 
04495 /*!
04496  * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
04497  *
04498  * Forces IRQSTAT[DTOE] to be set.
04499  */
04500 /*@{*/
04501 #define BP_SDHC_FEVT_DTOE    (20U)         /*!< Bit position for SDHC_FEVT_DTOE. */
04502 #define BM_SDHC_FEVT_DTOE    (0x00100000U) /*!< Bit mask for SDHC_FEVT_DTOE. */
04503 #define BS_SDHC_FEVT_DTOE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DTOE. */
04504 
04505 /*! @brief Format value for bitfield SDHC_FEVT_DTOE. */
04506 #define BF_SDHC_FEVT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DTOE) & BM_SDHC_FEVT_DTOE)
04507 
04508 /*! @brief Set the DTOE field to a new value. */
04509 #define BW_SDHC_FEVT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DTOE) = (v))
04510 /*@}*/
04511 
04512 /*!
04513  * @name Register SDHC_FEVT, field DCE[21] (WORZ)
04514  *
04515  * Forces IRQSTAT[DCE] to be set.
04516  */
04517 /*@{*/
04518 #define BP_SDHC_FEVT_DCE     (21U)         /*!< Bit position for SDHC_FEVT_DCE. */
04519 #define BM_SDHC_FEVT_DCE     (0x00200000U) /*!< Bit mask for SDHC_FEVT_DCE. */
04520 #define BS_SDHC_FEVT_DCE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_DCE. */
04521 
04522 /*! @brief Format value for bitfield SDHC_FEVT_DCE. */
04523 #define BF_SDHC_FEVT_DCE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DCE) & BM_SDHC_FEVT_DCE)
04524 
04525 /*! @brief Set the DCE field to a new value. */
04526 #define BW_SDHC_FEVT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DCE) = (v))
04527 /*@}*/
04528 
04529 /*!
04530  * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
04531  *
04532  * Forces IRQSTAT[DEBE] to be set.
04533  */
04534 /*@{*/
04535 #define BP_SDHC_FEVT_DEBE    (22U)         /*!< Bit position for SDHC_FEVT_DEBE. */
04536 #define BM_SDHC_FEVT_DEBE    (0x00400000U) /*!< Bit mask for SDHC_FEVT_DEBE. */
04537 #define BS_SDHC_FEVT_DEBE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DEBE. */
04538 
04539 /*! @brief Format value for bitfield SDHC_FEVT_DEBE. */
04540 #define BF_SDHC_FEVT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DEBE) & BM_SDHC_FEVT_DEBE)
04541 
04542 /*! @brief Set the DEBE field to a new value. */
04543 #define BW_SDHC_FEVT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DEBE) = (v))
04544 /*@}*/
04545 
04546 /*!
04547  * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
04548  *
04549  * Forces IRQSTAT[AC12E] to be set.
04550  */
04551 /*@{*/
04552 #define BP_SDHC_FEVT_AC12E   (24U)         /*!< Bit position for SDHC_FEVT_AC12E. */
04553 #define BM_SDHC_FEVT_AC12E   (0x01000000U) /*!< Bit mask for SDHC_FEVT_AC12E. */
04554 #define BS_SDHC_FEVT_AC12E   (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12E. */
04555 
04556 /*! @brief Format value for bitfield SDHC_FEVT_AC12E. */
04557 #define BF_SDHC_FEVT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12E) & BM_SDHC_FEVT_AC12E)
04558 
04559 /*! @brief Set the AC12E field to a new value. */
04560 #define BW_SDHC_FEVT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12E) = (v))
04561 /*@}*/
04562 
04563 /*!
04564  * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
04565  *
04566  * Forces the DMAE bit of Interrupt Status Register to be set.
04567  */
04568 /*@{*/
04569 #define BP_SDHC_FEVT_DMAE    (28U)         /*!< Bit position for SDHC_FEVT_DMAE. */
04570 #define BM_SDHC_FEVT_DMAE    (0x10000000U) /*!< Bit mask for SDHC_FEVT_DMAE. */
04571 #define BS_SDHC_FEVT_DMAE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DMAE. */
04572 
04573 /*! @brief Format value for bitfield SDHC_FEVT_DMAE. */
04574 #define BF_SDHC_FEVT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DMAE) & BM_SDHC_FEVT_DMAE)
04575 
04576 /*! @brief Set the DMAE field to a new value. */
04577 #define BW_SDHC_FEVT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DMAE) = (v))
04578 /*@}*/
04579 
04580 /*!
04581  * @name Register SDHC_FEVT, field CINT[31] (WORZ)
04582  *
04583  * Writing 1 to this bit generates a short low-level pulse on the internal
04584  * DAT[1] line, as if a self-clearing interrupt was received from the external card.
04585  * If enabled, the CINT bit will be set and the interrupt service routine may
04586  * treat this interrupt as a normal interrupt from the external card.
04587  */
04588 /*@{*/
04589 #define BP_SDHC_FEVT_CINT    (31U)         /*!< Bit position for SDHC_FEVT_CINT. */
04590 #define BM_SDHC_FEVT_CINT    (0x80000000U) /*!< Bit mask for SDHC_FEVT_CINT. */
04591 #define BS_SDHC_FEVT_CINT    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CINT. */
04592 
04593 /*! @brief Format value for bitfield SDHC_FEVT_CINT. */
04594 #define BF_SDHC_FEVT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CINT) & BM_SDHC_FEVT_CINT)
04595 
04596 /*! @brief Set the CINT field to a new value. */
04597 #define BW_SDHC_FEVT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CINT) = (v))
04598 /*@}*/
04599 
04600 /*******************************************************************************
04601  * HW_SDHC_ADMAES - ADMA Error Status register
04602  ******************************************************************************/
04603 
04604 /*!
04605  * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
04606  *
04607  * Reset value: 0x00000000U
04608  *
04609  * When an ADMA error interrupt has occurred, the ADMA Error States field in
04610  * this register holds the ADMA state and the ADMA System Address register holds the
04611  * address around the error descriptor. For recovering from this error, the host
04612  * driver requires the ADMA state to identify the error descriptor address as
04613  * follows: ST_STOP: Previous location set in the ADMA System Address register is
04614  * the error descriptor address. ST_FDS: Current location set in the ADMA System
04615  * Address register is the error descriptor address. ST_CADR: This state is never
04616  * set because it only increments the descriptor pointer and doesn't generate an
04617  * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
04618  * is the error descriptor address. In case of a write operation, the host driver
04619  * must use the ACMD22 to get the number of the written block, rather than using
04620  * this information, because unwritten data may exist in the host controller.
04621  * The host controller generates the ADMA error interrupt when it detects invalid
04622  * descriptor data (valid = 0) in the ST_FDS state. The host driver can
04623  * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
04624  * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
04625  * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
04626  * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
04627  * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
04628  * (Transfer Data) Holds the address of the next executable descriptor command
04629  */
04630 typedef union _hw_sdhc_admaes
04631 {
04632     uint32_t U;
04633     struct _hw_sdhc_admaes_bitfields
04634     {
04635         uint32_t ADMAES : 2;           /*!< [1:0] ADMA Error State (When ADMA Error Is
04636                                         * Occurred.) */
04637         uint32_t ADMALME : 1;          /*!< [2] ADMA Length Mismatch Error */
04638         uint32_t ADMADCE : 1;          /*!< [3] ADMA Descriptor Error */
04639         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
04640     } B;
04641 } hw_sdhc_admaes_t;
04642 
04643 /*!
04644  * @name Constants and macros for entire SDHC_ADMAES register
04645  */
04646 /*@{*/
04647 #define HW_SDHC_ADMAES_ADDR(x)   ((x) + 0x54U)
04648 
04649 #define HW_SDHC_ADMAES(x)        (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR(x))
04650 #define HW_SDHC_ADMAES_RD(x)     (HW_SDHC_ADMAES(x).U)
04651 /*@}*/
04652 
04653 /*
04654  * Constants & macros for individual SDHC_ADMAES bitfields
04655  */
04656 
04657 /*!
04658  * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
04659  *
04660  * Indicates the state of the ADMA when an error has occurred during an ADMA
04661  * data transfer.
04662  */
04663 /*@{*/
04664 #define BP_SDHC_ADMAES_ADMAES (0U)         /*!< Bit position for SDHC_ADMAES_ADMAES. */
04665 #define BM_SDHC_ADMAES_ADMAES (0x00000003U) /*!< Bit mask for SDHC_ADMAES_ADMAES. */
04666 #define BS_SDHC_ADMAES_ADMAES (2U)         /*!< Bit field size in bits for SDHC_ADMAES_ADMAES. */
04667 
04668 /*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
04669 #define BR_SDHC_ADMAES_ADMAES(x) (HW_SDHC_ADMAES(x).B.ADMAES)
04670 /*@}*/
04671 
04672 /*!
04673  * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
04674  *
04675  * This error occurs in the following 2 cases: While the block count enable is
04676  * being set, the total data length specified by the descriptor table is different
04677  * from that specified by the block count and block length. Total data length
04678  * can not be divided by the block length.
04679  *
04680  * Values:
04681  * - 0 - No error.
04682  * - 1 - Error.
04683  */
04684 /*@{*/
04685 #define BP_SDHC_ADMAES_ADMALME (2U)        /*!< Bit position for SDHC_ADMAES_ADMALME. */
04686 #define BM_SDHC_ADMAES_ADMALME (0x00000004U) /*!< Bit mask for SDHC_ADMAES_ADMALME. */
04687 #define BS_SDHC_ADMAES_ADMALME (1U)        /*!< Bit field size in bits for SDHC_ADMAES_ADMALME. */
04688 
04689 /*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
04690 #define BR_SDHC_ADMAES_ADMALME(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMALME))
04691 /*@}*/
04692 
04693 /*!
04694  * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
04695  *
04696  * This error occurs when an invalid descriptor is fetched by ADMA.
04697  *
04698  * Values:
04699  * - 0 - No error.
04700  * - 1 - Error.
04701  */
04702 /*@{*/
04703 #define BP_SDHC_ADMAES_ADMADCE (3U)        /*!< Bit position for SDHC_ADMAES_ADMADCE. */
04704 #define BM_SDHC_ADMAES_ADMADCE (0x00000008U) /*!< Bit mask for SDHC_ADMAES_ADMADCE. */
04705 #define BS_SDHC_ADMAES_ADMADCE (1U)        /*!< Bit field size in bits for SDHC_ADMAES_ADMADCE. */
04706 
04707 /*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
04708 #define BR_SDHC_ADMAES_ADMADCE(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMADCE))
04709 /*@}*/
04710 
04711 /*******************************************************************************
04712  * HW_SDHC_ADSADDR - ADMA System Addressregister
04713  ******************************************************************************/
04714 
04715 /*!
04716  * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
04717  *
04718  * Reset value: 0x00000000U
04719  *
04720  * This register contains the physical system memory address used for ADMA
04721  * transfers.
04722  */
04723 typedef union _hw_sdhc_adsaddr
04724 {
04725     uint32_t U;
04726     struct _hw_sdhc_adsaddr_bitfields
04727     {
04728         uint32_t RESERVED0 : 2;        /*!< [1:0]  */
04729         uint32_t ADSADDR : 30;         /*!< [31:2] ADMA System Address */
04730     } B;
04731 } hw_sdhc_adsaddr_t;
04732 
04733 /*!
04734  * @name Constants and macros for entire SDHC_ADSADDR register
04735  */
04736 /*@{*/
04737 #define HW_SDHC_ADSADDR_ADDR(x)  ((x) + 0x58U)
04738 
04739 #define HW_SDHC_ADSADDR(x)       (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR(x))
04740 #define HW_SDHC_ADSADDR_RD(x)    (HW_SDHC_ADSADDR(x).U)
04741 #define HW_SDHC_ADSADDR_WR(x, v) (HW_SDHC_ADSADDR(x).U = (v))
04742 #define HW_SDHC_ADSADDR_SET(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) |  (v)))
04743 #define HW_SDHC_ADSADDR_CLR(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) & ~(v)))
04744 #define HW_SDHC_ADSADDR_TOG(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) ^  (v)))
04745 /*@}*/
04746 
04747 /*
04748  * Constants & macros for individual SDHC_ADSADDR bitfields
04749  */
04750 
04751 /*!
04752  * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
04753  *
04754  * Holds the word address of the executing command in the descriptor table. At
04755  * the start of ADMA, the host driver shall set the start address of the
04756  * Descriptor table. The ADMA engine increments this register address whenever fetching a
04757  * descriptor command. When the ADMA is stopped at the block gap, this register
04758  * indicates the address of the next executable descriptor command. When the ADMA
04759  * error interrupt is generated, this register shall hold the valid descriptor
04760  * address depending on the ADMA state. The lower 2 bits of this register is tied
04761  * to '0' so the ADMA address is always word-aligned. Because this register
04762  * supports dynamic address reflecting, when TC bit is set, it automatically alters the
04763  * value of internal address counter, so SW cannot change this register when TC
04764  * bit is set.
04765  */
04766 /*@{*/
04767 #define BP_SDHC_ADSADDR_ADSADDR (2U)       /*!< Bit position for SDHC_ADSADDR_ADSADDR. */
04768 #define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_ADSADDR_ADSADDR. */
04769 #define BS_SDHC_ADSADDR_ADSADDR (30U)      /*!< Bit field size in bits for SDHC_ADSADDR_ADSADDR. */
04770 
04771 /*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
04772 #define BR_SDHC_ADSADDR_ADSADDR(x) (HW_SDHC_ADSADDR(x).B.ADSADDR)
04773 
04774 /*! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR. */
04775 #define BF_SDHC_ADSADDR_ADSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_ADSADDR_ADSADDR) & BM_SDHC_ADSADDR_ADSADDR)
04776 
04777 /*! @brief Set the ADSADDR field to a new value. */
04778 #define BW_SDHC_ADSADDR_ADSADDR(x, v) (HW_SDHC_ADSADDR_WR(x, (HW_SDHC_ADSADDR_RD(x) & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
04779 /*@}*/
04780 
04781 /*******************************************************************************
04782  * HW_SDHC_VENDOR - Vendor Specific register
04783  ******************************************************************************/
04784 
04785 /*!
04786  * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
04787  *
04788  * Reset value: 0x00000001U
04789  *
04790  * This register contains the vendor-specific control/status register.
04791  */
04792 typedef union _hw_sdhc_vendor
04793 {
04794     uint32_t U;
04795     struct _hw_sdhc_vendor_bitfields
04796     {
04797         uint32_t EXTDMAEN : 1;         /*!< [0] External DMA Request Enable */
04798         uint32_t EXBLKNU : 1;          /*!< [1] Exact Block Number Block Read Enable
04799                                         * For SDIO CMD53 */
04800         uint32_t RESERVED0 : 14;       /*!< [15:2]  */
04801         uint32_t INTSTVAL : 8;         /*!< [23:16] Internal State Value */
04802         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
04803     } B;
04804 } hw_sdhc_vendor_t;
04805 
04806 /*!
04807  * @name Constants and macros for entire SDHC_VENDOR register
04808  */
04809 /*@{*/
04810 #define HW_SDHC_VENDOR_ADDR(x)   ((x) + 0xC0U)
04811 
04812 #define HW_SDHC_VENDOR(x)        (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR(x))
04813 #define HW_SDHC_VENDOR_RD(x)     (HW_SDHC_VENDOR(x).U)
04814 #define HW_SDHC_VENDOR_WR(x, v)  (HW_SDHC_VENDOR(x).U = (v))
04815 #define HW_SDHC_VENDOR_SET(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) |  (v)))
04816 #define HW_SDHC_VENDOR_CLR(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) & ~(v)))
04817 #define HW_SDHC_VENDOR_TOG(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) ^  (v)))
04818 /*@}*/
04819 
04820 /*
04821  * Constants & macros for individual SDHC_VENDOR bitfields
04822  */
04823 
04824 /*!
04825  * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
04826  *
04827  * Enables the request to external DMA. When the internal DMA (either simple DMA
04828  * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
04829  * request when the internal buffer is ready. This bit is particularly useful when
04830  * transferring data by CPU polling mode, and it is not allowed to send out the
04831  * external DMA request. By default, this bit is set.
04832  *
04833  * Values:
04834  * - 0 - In any scenario, SDHC does not send out the external DMA request.
04835  * - 1 - When internal DMA is not active, the external DMA request will be sent
04836  *     out.
04837  */
04838 /*@{*/
04839 #define BP_SDHC_VENDOR_EXTDMAEN (0U)       /*!< Bit position for SDHC_VENDOR_EXTDMAEN. */
04840 #define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) /*!< Bit mask for SDHC_VENDOR_EXTDMAEN. */
04841 #define BS_SDHC_VENDOR_EXTDMAEN (1U)       /*!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN. */
04842 
04843 /*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
04844 #define BR_SDHC_VENDOR_EXTDMAEN(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN))
04845 
04846 /*! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN. */
04847 #define BF_SDHC_VENDOR_EXTDMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXTDMAEN) & BM_SDHC_VENDOR_EXTDMAEN)
04848 
04849 /*! @brief Set the EXTDMAEN field to a new value. */
04850 #define BW_SDHC_VENDOR_EXTDMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN) = (v))
04851 /*@}*/
04852 
04853 /*!
04854  * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
04855  *
04856  * This bit must be set before S/W issues CMD53 multi-block read with exact
04857  * block number. This bit must not be set if the CMD53 multi-block read is not exact
04858  * block number.
04859  *
04860  * Values:
04861  * - 0 - None exact block read.
04862  * - 1 - Exact block read for SDIO CMD53.
04863  */
04864 /*@{*/
04865 #define BP_SDHC_VENDOR_EXBLKNU (1U)        /*!< Bit position for SDHC_VENDOR_EXBLKNU. */
04866 #define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) /*!< Bit mask for SDHC_VENDOR_EXBLKNU. */
04867 #define BS_SDHC_VENDOR_EXBLKNU (1U)        /*!< Bit field size in bits for SDHC_VENDOR_EXBLKNU. */
04868 
04869 /*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
04870 #define BR_SDHC_VENDOR_EXBLKNU(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU))
04871 
04872 /*! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU. */
04873 #define BF_SDHC_VENDOR_EXBLKNU(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXBLKNU) & BM_SDHC_VENDOR_EXBLKNU)
04874 
04875 /*! @brief Set the EXBLKNU field to a new value. */
04876 #define BW_SDHC_VENDOR_EXBLKNU(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU) = (v))
04877 /*@}*/
04878 
04879 /*!
04880  * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
04881  *
04882  * Internal state value, reflecting the corresponding state value selected by
04883  * Debug Select field. This field is read-only and write to this field does not
04884  * have effect.
04885  */
04886 /*@{*/
04887 #define BP_SDHC_VENDOR_INTSTVAL (16U)      /*!< Bit position for SDHC_VENDOR_INTSTVAL. */
04888 #define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) /*!< Bit mask for SDHC_VENDOR_INTSTVAL. */
04889 #define BS_SDHC_VENDOR_INTSTVAL (8U)       /*!< Bit field size in bits for SDHC_VENDOR_INTSTVAL. */
04890 
04891 /*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
04892 #define BR_SDHC_VENDOR_INTSTVAL(x) (HW_SDHC_VENDOR(x).B.INTSTVAL)
04893 /*@}*/
04894 
04895 /*******************************************************************************
04896  * HW_SDHC_MMCBOOT - MMC Boot register
04897  ******************************************************************************/
04898 
04899 /*!
04900  * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
04901  *
04902  * Reset value: 0x00000000U
04903  *
04904  * This register contains the MMC fast boot control register.
04905  */
04906 typedef union _hw_sdhc_mmcboot
04907 {
04908     uint32_t U;
04909     struct _hw_sdhc_mmcboot_bitfields
04910     {
04911         uint32_t DTOCVACK : 4;         /*!< [3:0] Boot ACK Time Out Counter Value */
04912         uint32_t BOOTACK : 1;          /*!< [4] Boot Ack Mode Select */
04913         uint32_t BOOTMODE : 1;         /*!< [5] Boot Mode Select */
04914         uint32_t BOOTEN : 1;           /*!< [6] Boot Mode Enable */
04915         uint32_t AUTOSABGEN : 1;       /*!< [7]  */
04916         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
04917         uint32_t BOOTBLKCNT : 16;      /*!< [31:16]  */
04918     } B;
04919 } hw_sdhc_mmcboot_t;
04920 
04921 /*!
04922  * @name Constants and macros for entire SDHC_MMCBOOT register
04923  */
04924 /*@{*/
04925 #define HW_SDHC_MMCBOOT_ADDR(x)  ((x) + 0xC4U)
04926 
04927 #define HW_SDHC_MMCBOOT(x)       (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR(x))
04928 #define HW_SDHC_MMCBOOT_RD(x)    (HW_SDHC_MMCBOOT(x).U)
04929 #define HW_SDHC_MMCBOOT_WR(x, v) (HW_SDHC_MMCBOOT(x).U = (v))
04930 #define HW_SDHC_MMCBOOT_SET(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) |  (v)))
04931 #define HW_SDHC_MMCBOOT_CLR(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) & ~(v)))
04932 #define HW_SDHC_MMCBOOT_TOG(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) ^  (v)))
04933 /*@}*/
04934 
04935 /*
04936  * Constants & macros for individual SDHC_MMCBOOT bitfields
04937  */
04938 
04939 /*!
04940  * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
04941  *
04942  * Values:
04943  * - 0000 - SDCLK x 2^8
04944  * - 0001 - SDCLK x 2^9
04945  * - 0010 - SDCLK x 2^10
04946  * - 0011 - SDCLK x 2^11
04947  * - 0100 - SDCLK x 2^12
04948  * - 0101 - SDCLK x 2^13
04949  * - 0110 - SDCLK x 2^14
04950  * - 0111 - SDCLK x 2^15
04951  * - 1110 - SDCLK x 2^22
04952  * - 1111 - Reserved
04953  */
04954 /*@{*/
04955 #define BP_SDHC_MMCBOOT_DTOCVACK (0U)      /*!< Bit position for SDHC_MMCBOOT_DTOCVACK. */
04956 #define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) /*!< Bit mask for SDHC_MMCBOOT_DTOCVACK. */
04957 #define BS_SDHC_MMCBOOT_DTOCVACK (4U)      /*!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK. */
04958 
04959 /*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
04960 #define BR_SDHC_MMCBOOT_DTOCVACK(x) (HW_SDHC_MMCBOOT(x).B.DTOCVACK)
04961 
04962 /*! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK. */
04963 #define BF_SDHC_MMCBOOT_DTOCVACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_DTOCVACK) & BM_SDHC_MMCBOOT_DTOCVACK)
04964 
04965 /*! @brief Set the DTOCVACK field to a new value. */
04966 #define BW_SDHC_MMCBOOT_DTOCVACK(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
04967 /*@}*/
04968 
04969 /*!
04970  * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
04971  *
04972  * Values:
04973  * - 0 - No ack.
04974  * - 1 - Ack.
04975  */
04976 /*@{*/
04977 #define BP_SDHC_MMCBOOT_BOOTACK (4U)       /*!< Bit position for SDHC_MMCBOOT_BOOTACK. */
04978 #define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) /*!< Bit mask for SDHC_MMCBOOT_BOOTACK. */
04979 #define BS_SDHC_MMCBOOT_BOOTACK (1U)       /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK. */
04980 
04981 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
04982 #define BR_SDHC_MMCBOOT_BOOTACK(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK))
04983 
04984 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK. */
04985 #define BF_SDHC_MMCBOOT_BOOTACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTACK) & BM_SDHC_MMCBOOT_BOOTACK)
04986 
04987 /*! @brief Set the BOOTACK field to a new value. */
04988 #define BW_SDHC_MMCBOOT_BOOTACK(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK) = (v))
04989 /*@}*/
04990 
04991 /*!
04992  * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
04993  *
04994  * Values:
04995  * - 0 - Normal boot.
04996  * - 1 - Alternative boot.
04997  */
04998 /*@{*/
04999 #define BP_SDHC_MMCBOOT_BOOTMODE (5U)      /*!< Bit position for SDHC_MMCBOOT_BOOTMODE. */
05000 #define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) /*!< Bit mask for SDHC_MMCBOOT_BOOTMODE. */
05001 #define BS_SDHC_MMCBOOT_BOOTMODE (1U)      /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE. */
05002 
05003 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
05004 #define BR_SDHC_MMCBOOT_BOOTMODE(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE))
05005 
05006 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE. */
05007 #define BF_SDHC_MMCBOOT_BOOTMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTMODE) & BM_SDHC_MMCBOOT_BOOTMODE)
05008 
05009 /*! @brief Set the BOOTMODE field to a new value. */
05010 #define BW_SDHC_MMCBOOT_BOOTMODE(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE) = (v))
05011 /*@}*/
05012 
05013 /*!
05014  * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
05015  *
05016  * Values:
05017  * - 0 - Fast boot disable.
05018  * - 1 - Fast boot enable.
05019  */
05020 /*@{*/
05021 #define BP_SDHC_MMCBOOT_BOOTEN (6U)        /*!< Bit position for SDHC_MMCBOOT_BOOTEN. */
05022 #define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) /*!< Bit mask for SDHC_MMCBOOT_BOOTEN. */
05023 #define BS_SDHC_MMCBOOT_BOOTEN (1U)        /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN. */
05024 
05025 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
05026 #define BR_SDHC_MMCBOOT_BOOTEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN))
05027 
05028 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN. */
05029 #define BF_SDHC_MMCBOOT_BOOTEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTEN) & BM_SDHC_MMCBOOT_BOOTEN)
05030 
05031 /*! @brief Set the BOOTEN field to a new value. */
05032 #define BW_SDHC_MMCBOOT_BOOTEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN) = (v))
05033 /*@}*/
05034 
05035 /*!
05036  * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
05037  *
05038  * When boot, enable auto stop at block gap function. This function will be
05039  * triggered, and host will stop at block gap when received card block cnt is equal
05040  * to BOOTBLKCNT.
05041  */
05042 /*@{*/
05043 #define BP_SDHC_MMCBOOT_AUTOSABGEN (7U)    /*!< Bit position for SDHC_MMCBOOT_AUTOSABGEN. */
05044 #define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) /*!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN. */
05045 #define BS_SDHC_MMCBOOT_AUTOSABGEN (1U)    /*!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN. */
05046 
05047 /*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
05048 #define BR_SDHC_MMCBOOT_AUTOSABGEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN))
05049 
05050 /*! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN. */
05051 #define BF_SDHC_MMCBOOT_AUTOSABGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_AUTOSABGEN) & BM_SDHC_MMCBOOT_AUTOSABGEN)
05052 
05053 /*! @brief Set the AUTOSABGEN field to a new value. */
05054 #define BW_SDHC_MMCBOOT_AUTOSABGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
05055 /*@}*/
05056 
05057 /*!
05058  * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
05059  *
05060  * Defines the stop at block gap value of automatic mode. When received card
05061  * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
05062  */
05063 /*@{*/
05064 #define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U)   /*!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT. */
05065 #define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT. */
05066 #define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U)   /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT. */
05067 
05068 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
05069 #define BR_SDHC_MMCBOOT_BOOTBLKCNT(x) (HW_SDHC_MMCBOOT(x).B.BOOTBLKCNT)
05070 
05071 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT. */
05072 #define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTBLKCNT) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
05073 
05074 /*! @brief Set the BOOTBLKCNT field to a new value. */
05075 #define BW_SDHC_MMCBOOT_BOOTBLKCNT(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
05076 /*@}*/
05077 
05078 /*******************************************************************************
05079  * HW_SDHC_HOSTVER - Host Controller Version
05080  ******************************************************************************/
05081 
05082 /*!
05083  * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
05084  *
05085  * Reset value: 0x00001201U
05086  *
05087  * This register contains the vendor host controller version information. All
05088  * bits are read only and will read the same as the power-reset value.
05089  */
05090 typedef union _hw_sdhc_hostver
05091 {
05092     uint32_t U;
05093     struct _hw_sdhc_hostver_bitfields
05094     {
05095         uint32_t SVN : 8;              /*!< [7:0] Specification Version Number */
05096         uint32_t VVN : 8;              /*!< [15:8] Vendor Version Number */
05097         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05098     } B;
05099 } hw_sdhc_hostver_t;
05100 
05101 /*!
05102  * @name Constants and macros for entire SDHC_HOSTVER register
05103  */
05104 /*@{*/
05105 #define HW_SDHC_HOSTVER_ADDR(x)  ((x) + 0xFCU)
05106 
05107 #define HW_SDHC_HOSTVER(x)       (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR(x))
05108 #define HW_SDHC_HOSTVER_RD(x)    (HW_SDHC_HOSTVER(x).U)
05109 /*@}*/
05110 
05111 /*
05112  * Constants & macros for individual SDHC_HOSTVER bitfields
05113  */
05114 
05115 /*!
05116  * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
05117  *
05118  * These status bits indicate the host controller specification version.
05119  *
05120  * Values:
05121  * - 1 - SD host specification version 2.0, supports test event register and
05122  *     ADMA.
05123  */
05124 /*@{*/
05125 #define BP_SDHC_HOSTVER_SVN  (0U)          /*!< Bit position for SDHC_HOSTVER_SVN. */
05126 #define BM_SDHC_HOSTVER_SVN  (0x000000FFU) /*!< Bit mask for SDHC_HOSTVER_SVN. */
05127 #define BS_SDHC_HOSTVER_SVN  (8U)          /*!< Bit field size in bits for SDHC_HOSTVER_SVN. */
05128 
05129 /*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
05130 #define BR_SDHC_HOSTVER_SVN(x) (HW_SDHC_HOSTVER(x).B.SVN)
05131 /*@}*/
05132 
05133 /*!
05134  * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
05135  *
05136  * These status bits are reserved for the vendor version number. The host driver
05137  * shall not use this status.
05138  *
05139  * Values:
05140  * - 0 - Freescale SDHC version 1.0
05141  * - 10000 - Freescale SDHC version 2.0
05142  * - 10001 - Freescale SDHC version 2.1
05143  * - 10010 - Freescale SDHC version 2.2
05144  */
05145 /*@{*/
05146 #define BP_SDHC_HOSTVER_VVN  (8U)          /*!< Bit position for SDHC_HOSTVER_VVN. */
05147 #define BM_SDHC_HOSTVER_VVN  (0x0000FF00U) /*!< Bit mask for SDHC_HOSTVER_VVN. */
05148 #define BS_SDHC_HOSTVER_VVN  (8U)          /*!< Bit field size in bits for SDHC_HOSTVER_VVN. */
05149 
05150 /*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
05151 #define BR_SDHC_HOSTVER_VVN(x) (HW_SDHC_HOSTVER(x).B.VVN)
05152 /*@}*/
05153 
05154 /*******************************************************************************
05155  * hw_sdhc_t - module struct
05156  ******************************************************************************/
05157 /*!
05158  * @brief All SDHC module registers.
05159  */
05160 #pragma pack(1)
05161 typedef struct _hw_sdhc
05162 {
05163     __IO hw_sdhc_dsaddr_t DSADDR ;          /*!< [0x0] DMA System Address register */
05164     __IO hw_sdhc_blkattr_t BLKATTR ;        /*!< [0x4] Block Attributes register */
05165     __IO hw_sdhc_cmdarg_t CMDARG ;          /*!< [0x8] Command Argument register */
05166     __IO hw_sdhc_xfertyp_t XFERTYP ;        /*!< [0xC] Transfer Type register */
05167     __I hw_sdhc_cmdrsp0_t CMDRSP0 ;         /*!< [0x10] Command Response 0 */
05168     __I hw_sdhc_cmdrsp1_t CMDRSP1 ;         /*!< [0x14] Command Response 1 */
05169     __I hw_sdhc_cmdrsp2_t CMDRSP2 ;         /*!< [0x18] Command Response 2 */
05170     __I hw_sdhc_cmdrsp3_t CMDRSP3 ;         /*!< [0x1C] Command Response 3 */
05171     __IO hw_sdhc_datport_t DATPORT ;        /*!< [0x20] Buffer Data Port register */
05172     __I hw_sdhc_prsstat_t PRSSTAT ;         /*!< [0x24] Present State register */
05173     __IO hw_sdhc_proctl_t PROCTL ;          /*!< [0x28] Protocol Control register */
05174     __IO hw_sdhc_sysctl_t SYSCTL ;          /*!< [0x2C] System Control register */
05175     __IO hw_sdhc_irqstat_t IRQSTAT ;        /*!< [0x30] Interrupt Status register */
05176     __IO hw_sdhc_irqstaten_t IRQSTATEN ;    /*!< [0x34] Interrupt Status Enable register */
05177     __IO hw_sdhc_irqsigen_t IRQSIGEN ;      /*!< [0x38] Interrupt Signal Enable register */
05178     __I hw_sdhc_ac12err_t AC12ERR ;         /*!< [0x3C] Auto CMD12 Error Status Register */
05179     __I hw_sdhc_htcapblt_t HTCAPBLT ;       /*!< [0x40] Host Controller Capabilities */
05180     __IO hw_sdhc_wml_t WML ;                /*!< [0x44] Watermark Level Register */
05181     uint8_t _reserved0[8];
05182     __O hw_sdhc_fevt_t FEVT ;               /*!< [0x50] Force Event register */
05183     __I hw_sdhc_admaes_t ADMAES ;           /*!< [0x54] ADMA Error Status register */
05184     __IO hw_sdhc_adsaddr_t ADSADDR ;        /*!< [0x58] ADMA System Addressregister */
05185     uint8_t _reserved1[100];
05186     __IO hw_sdhc_vendor_t VENDOR ;          /*!< [0xC0] Vendor Specific register */
05187     __IO hw_sdhc_mmcboot_t MMCBOOT ;        /*!< [0xC4] MMC Boot register */
05188     uint8_t _reserved2[52];
05189     __I hw_sdhc_hostver_t HOSTVER ;         /*!< [0xFC] Host Controller Version */
05190 } hw_sdhc_t;
05191 #pragma pack()
05192 
05193 /*! @brief Macro to access all SDHC registers. */
05194 /*! @param x SDHC module instance base address. */
05195 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
05196  *     use the '&' operator, like <code>&HW_SDHC(SDHC_BASE)</code>. */
05197 #define HW_SDHC(x)     (*(hw_sdhc_t *)(x))
05198 
05199 #endif /* __HW_SDHC_REGISTERS_H__ */
05200 /* EOF */