MK64F12_port.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_PORT_REGISTERS_H__
00081 #define __HW_PORT_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 PORT
00088  *
00089  * Pin Control and Interrupts
00090  *
00091  * Registers defined in this header file:
00092  * - HW_PORT_PCRn - Pin Control Register n
00093  * - HW_PORT_GPCLR - Global Pin Control Low Register
00094  * - HW_PORT_GPCHR - Global Pin Control High Register
00095  * - HW_PORT_ISFR - Interrupt Status Flag Register
00096  * - HW_PORT_DFER - Digital Filter Enable Register
00097  * - HW_PORT_DFCR - Digital Filter Clock Register
00098  * - HW_PORT_DFWR - Digital Filter Width Register
00099  *
00100  * - hw_port_t - Struct containing all module registers.
00101  */
00102 
00103 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
00104 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
00105 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
00106 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
00107 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
00108 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
00109 
00110 /*******************************************************************************
00111  * HW_PORT_PCRn - Pin Control Register n
00112  ******************************************************************************/
00113 
00114 /*!
00115  * @brief HW_PORT_PCRn - Pin Control Register n (RW)
00116  *
00117  * Reset value: 0x00000742U
00118  *
00119  * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
00120  * this device. See the GPIO Configuration section for details on the available
00121  * functions for each pin. Do not modify pin configuration registers associated
00122  * with pins not available in your selected package. All unbonded pins not
00123  * available in your package will default to DISABLE state for lowest power consumption.
00124  */
00125 typedef union _hw_port_pcrn
00126 {
00127     uint32_t U;
00128     struct _hw_port_pcrn_bitfields
00129     {
00130         uint32_t PS : 1;               /*!< [0] Pull Select */
00131         uint32_t PE : 1;               /*!< [1] Pull Enable */
00132         uint32_t SRE : 1;              /*!< [2] Slew Rate Enable */
00133         uint32_t RESERVED0 : 1;        /*!< [3]  */
00134         uint32_t PFE : 1;              /*!< [4] Passive Filter Enable */
00135         uint32_t ODE : 1;              /*!< [5] Open Drain Enable */
00136         uint32_t DSE : 1;              /*!< [6] Drive Strength Enable */
00137         uint32_t RESERVED1 : 1;        /*!< [7]  */
00138         uint32_t MUX : 3;              /*!< [10:8] Pin Mux Control */
00139         uint32_t RESERVED2 : 4;        /*!< [14:11]  */
00140         uint32_t LK : 1;               /*!< [15] Lock Register */
00141         uint32_t IRQC : 4;             /*!< [19:16] Interrupt Configuration */
00142         uint32_t RESERVED3 : 4;        /*!< [23:20]  */
00143         uint32_t ISF : 1;              /*!< [24] Interrupt Status Flag */
00144         uint32_t RESERVED4 : 7;        /*!< [31:25]  */
00145     } B;
00146 } hw_port_pcrn_t;
00147 
00148 /*!
00149  * @name Constants and macros for entire PORT_PCRn register
00150  */
00151 /*@{*/
00152 #define HW_PORT_PCRn_COUNT (32U)
00153 
00154 #define HW_PORT_PCRn_ADDR(x, n)  ((x) + 0x0U + (0x4U * (n)))
00155 
00156 #define HW_PORT_PCRn(x, n)       (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
00157 #define HW_PORT_PCRn_RD(x, n)    (HW_PORT_PCRn(x, n).U)
00158 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
00159 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) |  (v)))
00160 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
00161 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^  (v)))
00162 /*@}*/
00163 
00164 /*
00165  * Constants & macros for individual PORT_PCRn bitfields
00166  */
00167 
00168 /*!
00169  * @name Register PORT_PCRn, field PS[0] (RW)
00170  *
00171  * Pull configuration is valid in all digital pin muxing modes.
00172  *
00173  * Values:
00174  * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
00175  *     corresponding PE field is set.
00176  * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
00177  *     corresponding PE field is set.
00178  */
00179 /*@{*/
00180 #define BP_PORT_PCRn_PS      (0U)          /*!< Bit position for PORT_PCRn_PS. */
00181 #define BM_PORT_PCRn_PS      (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
00182 #define BS_PORT_PCRn_PS      (1U)          /*!< Bit field size in bits for PORT_PCRn_PS. */
00183 
00184 /*! @brief Read current value of the PORT_PCRn_PS field. */
00185 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
00186 
00187 /*! @brief Format value for bitfield PORT_PCRn_PS. */
00188 #define BF_PORT_PCRn_PS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
00189 
00190 /*! @brief Set the PS field to a new value. */
00191 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
00192 /*@}*/
00193 
00194 /*!
00195  * @name Register PORT_PCRn, field PE[1] (RW)
00196  *
00197  * Pull configuration is valid in all digital pin muxing modes.
00198  *
00199  * Values:
00200  * - 0 - Internal pullup or pulldown resistor is not enabled on the
00201  *     corresponding pin.
00202  * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
00203  *     pin, if the pin is configured as a digital input.
00204  */
00205 /*@{*/
00206 #define BP_PORT_PCRn_PE      (1U)          /*!< Bit position for PORT_PCRn_PE. */
00207 #define BM_PORT_PCRn_PE      (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
00208 #define BS_PORT_PCRn_PE      (1U)          /*!< Bit field size in bits for PORT_PCRn_PE. */
00209 
00210 /*! @brief Read current value of the PORT_PCRn_PE field. */
00211 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
00212 
00213 /*! @brief Format value for bitfield PORT_PCRn_PE. */
00214 #define BF_PORT_PCRn_PE(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
00215 
00216 /*! @brief Set the PE field to a new value. */
00217 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
00218 /*@}*/
00219 
00220 /*!
00221  * @name Register PORT_PCRn, field SRE[2] (RW)
00222  *
00223  * Slew rate configuration is valid in all digital pin muxing modes.
00224  *
00225  * Values:
00226  * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
00227  *     configured as a digital output.
00228  * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
00229  *     configured as a digital output.
00230  */
00231 /*@{*/
00232 #define BP_PORT_PCRn_SRE     (2U)          /*!< Bit position for PORT_PCRn_SRE. */
00233 #define BM_PORT_PCRn_SRE     (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
00234 #define BS_PORT_PCRn_SRE     (1U)          /*!< Bit field size in bits for PORT_PCRn_SRE. */
00235 
00236 /*! @brief Read current value of the PORT_PCRn_SRE field. */
00237 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
00238 
00239 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
00240 #define BF_PORT_PCRn_SRE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
00241 
00242 /*! @brief Set the SRE field to a new value. */
00243 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
00244 /*@}*/
00245 
00246 /*!
00247  * @name Register PORT_PCRn, field PFE[4] (RW)
00248  *
00249  * Passive filter configuration is valid in all digital pin muxing modes.
00250  *
00251  * Values:
00252  * - 0 - Passive input filter is disabled on the corresponding pin.
00253  * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
00254  *     configured as a digital input. Refer to the device data sheet for filter
00255  *     characteristics.
00256  */
00257 /*@{*/
00258 #define BP_PORT_PCRn_PFE     (4U)          /*!< Bit position for PORT_PCRn_PFE. */
00259 #define BM_PORT_PCRn_PFE     (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
00260 #define BS_PORT_PCRn_PFE     (1U)          /*!< Bit field size in bits for PORT_PCRn_PFE. */
00261 
00262 /*! @brief Read current value of the PORT_PCRn_PFE field. */
00263 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
00264 
00265 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
00266 #define BF_PORT_PCRn_PFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
00267 
00268 /*! @brief Set the PFE field to a new value. */
00269 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
00270 /*@}*/
00271 
00272 /*!
00273  * @name Register PORT_PCRn, field ODE[5] (RW)
00274  *
00275  * Open drain configuration is valid in all digital pin muxing modes.
00276  *
00277  * Values:
00278  * - 0 - Open drain output is disabled on the corresponding pin.
00279  * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
00280  *     configured as a digital output.
00281  */
00282 /*@{*/
00283 #define BP_PORT_PCRn_ODE     (5U)          /*!< Bit position for PORT_PCRn_ODE. */
00284 #define BM_PORT_PCRn_ODE     (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
00285 #define BS_PORT_PCRn_ODE     (1U)          /*!< Bit field size in bits for PORT_PCRn_ODE. */
00286 
00287 /*! @brief Read current value of the PORT_PCRn_ODE field. */
00288 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
00289 
00290 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
00291 #define BF_PORT_PCRn_ODE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
00292 
00293 /*! @brief Set the ODE field to a new value. */
00294 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
00295 /*@}*/
00296 
00297 /*!
00298  * @name Register PORT_PCRn, field DSE[6] (RW)
00299  *
00300  * Drive strength configuration is valid in all digital pin muxing modes.
00301  *
00302  * Values:
00303  * - 0 - Low drive strength is configured on the corresponding pin, if pin is
00304  *     configured as a digital output.
00305  * - 1 - High drive strength is configured on the corresponding pin, if pin is
00306  *     configured as a digital output.
00307  */
00308 /*@{*/
00309 #define BP_PORT_PCRn_DSE     (6U)          /*!< Bit position for PORT_PCRn_DSE. */
00310 #define BM_PORT_PCRn_DSE     (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
00311 #define BS_PORT_PCRn_DSE     (1U)          /*!< Bit field size in bits for PORT_PCRn_DSE. */
00312 
00313 /*! @brief Read current value of the PORT_PCRn_DSE field. */
00314 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
00315 
00316 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
00317 #define BF_PORT_PCRn_DSE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
00318 
00319 /*! @brief Set the DSE field to a new value. */
00320 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
00321 /*@}*/
00322 
00323 /*!
00324  * @name Register PORT_PCRn, field MUX[10:8] (RW)
00325  *
00326  * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
00327  * reserved and may result in configuring the pin for a different pin muxing
00328  * slot. The corresponding pin is configured in the following pin muxing slot as
00329  * follows:
00330  *
00331  * Values:
00332  * - 000 - Pin disabled (analog).
00333  * - 001 - Alternative 1 (GPIO).
00334  * - 010 - Alternative 2 (chip-specific).
00335  * - 011 - Alternative 3 (chip-specific).
00336  * - 100 - Alternative 4 (chip-specific).
00337  * - 101 - Alternative 5 (chip-specific).
00338  * - 110 - Alternative 6 (chip-specific).
00339  * - 111 - Alternative 7 (chip-specific).
00340  */
00341 /*@{*/
00342 #define BP_PORT_PCRn_MUX     (8U)          /*!< Bit position for PORT_PCRn_MUX. */
00343 #define BM_PORT_PCRn_MUX     (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
00344 #define BS_PORT_PCRn_MUX     (3U)          /*!< Bit field size in bits for PORT_PCRn_MUX. */
00345 
00346 /*! @brief Read current value of the PORT_PCRn_MUX field. */
00347 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
00348 
00349 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
00350 #define BF_PORT_PCRn_MUX(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
00351 
00352 /*! @brief Set the MUX field to a new value. */
00353 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
00354 /*@}*/
00355 
00356 /*!
00357  * @name Register PORT_PCRn, field LK[15] (RW)
00358  *
00359  * Values:
00360  * - 0 - Pin Control Register fields [15:0] are not locked.
00361  * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
00362  *     until the next system reset.
00363  */
00364 /*@{*/
00365 #define BP_PORT_PCRn_LK      (15U)         /*!< Bit position for PORT_PCRn_LK. */
00366 #define BM_PORT_PCRn_LK      (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
00367 #define BS_PORT_PCRn_LK      (1U)          /*!< Bit field size in bits for PORT_PCRn_LK. */
00368 
00369 /*! @brief Read current value of the PORT_PCRn_LK field. */
00370 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
00371 
00372 /*! @brief Format value for bitfield PORT_PCRn_LK. */
00373 #define BF_PORT_PCRn_LK(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
00374 
00375 /*! @brief Set the LK field to a new value. */
00376 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
00377 /*@}*/
00378 
00379 /*!
00380  * @name Register PORT_PCRn, field IRQC[19:16] (RW)
00381  *
00382  * The pin interrupt configuration is valid in all digital pin muxing modes. The
00383  * corresponding pin is configured to generate interrupt/DMA request as follows:
00384  *
00385  * Values:
00386  * - 0000 - Interrupt/DMA request disabled.
00387  * - 0001 - DMA request on rising edge.
00388  * - 0010 - DMA request on falling edge.
00389  * - 0011 - DMA request on either edge.
00390  * - 1000 - Interrupt when logic 0.
00391  * - 1001 - Interrupt on rising-edge.
00392  * - 1010 - Interrupt on falling-edge.
00393  * - 1011 - Interrupt on either edge.
00394  * - 1100 - Interrupt when logic 1.
00395  */
00396 /*@{*/
00397 #define BP_PORT_PCRn_IRQC    (16U)         /*!< Bit position for PORT_PCRn_IRQC. */
00398 #define BM_PORT_PCRn_IRQC    (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
00399 #define BS_PORT_PCRn_IRQC    (4U)          /*!< Bit field size in bits for PORT_PCRn_IRQC. */
00400 
00401 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
00402 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
00403 
00404 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
00405 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
00406 
00407 /*! @brief Set the IRQC field to a new value. */
00408 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
00409 /*@}*/
00410 
00411 /*!
00412  * @name Register PORT_PCRn, field ISF[24] (W1C)
00413  *
00414  * The pin interrupt configuration is valid in all digital pin muxing modes.
00415  *
00416  * Values:
00417  * - 0 - Configured interrupt is not detected.
00418  * - 1 - Configured interrupt is detected. If the pin is configured to generate
00419  *     a DMA request, then the corresponding flag will be cleared automatically
00420  *     at the completion of the requested DMA transfer. Otherwise, the flag
00421  *     remains set until a logic 1 is written to the flag. If the pin is configured for
00422  *     a level sensitive interrupt and the pin remains asserted, then the flag
00423  *     is set again immediately after it is cleared.
00424  */
00425 /*@{*/
00426 #define BP_PORT_PCRn_ISF     (24U)         /*!< Bit position for PORT_PCRn_ISF. */
00427 #define BM_PORT_PCRn_ISF     (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
00428 #define BS_PORT_PCRn_ISF     (1U)          /*!< Bit field size in bits for PORT_PCRn_ISF. */
00429 
00430 /*! @brief Read current value of the PORT_PCRn_ISF field. */
00431 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
00432 
00433 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
00434 #define BF_PORT_PCRn_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
00435 
00436 /*! @brief Set the ISF field to a new value. */
00437 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
00438 /*@}*/
00439 
00440 /*******************************************************************************
00441  * HW_PORT_GPCLR - Global Pin Control Low Register
00442  ******************************************************************************/
00443 
00444 /*!
00445  * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
00446  *
00447  * Reset value: 0x00000000U
00448  *
00449  * Only 32-bit writes are supported to this register.
00450  */
00451 typedef union _hw_port_gpclr
00452 {
00453     uint32_t U;
00454     struct _hw_port_gpclr_bitfields
00455     {
00456         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
00457         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
00458     } B;
00459 } hw_port_gpclr_t;
00460 
00461 /*!
00462  * @name Constants and macros for entire PORT_GPCLR register
00463  */
00464 /*@{*/
00465 #define HW_PORT_GPCLR_ADDR(x)    ((x) + 0x80U)
00466 
00467 #define HW_PORT_GPCLR(x)         (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
00468 #define HW_PORT_GPCLR_RD(x)      (HW_PORT_GPCLR(x).U)
00469 #define HW_PORT_GPCLR_WR(x, v)   (HW_PORT_GPCLR(x).U = (v))
00470 /*@}*/
00471 
00472 /*
00473  * Constants & macros for individual PORT_GPCLR bitfields
00474  */
00475 
00476 /*!
00477  * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
00478  *
00479  * Write value that is written to all Pin Control Registers bits [15:0] that are
00480  * selected by GPWE.
00481  */
00482 /*@{*/
00483 #define BP_PORT_GPCLR_GPWD   (0U)          /*!< Bit position for PORT_GPCLR_GPWD. */
00484 #define BM_PORT_GPCLR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
00485 #define BS_PORT_GPCLR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
00486 
00487 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
00488 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
00489 
00490 /*! @brief Set the GPWD field to a new value. */
00491 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
00492 /*@}*/
00493 
00494 /*!
00495  * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
00496  *
00497  * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
00498  * the value in GPWD. If a selected Pin Control Register is locked then the write
00499  * to that register is ignored.
00500  *
00501  * Values:
00502  * - 0 - Corresponding Pin Control Register is not updated with the value in
00503  *     GPWD.
00504  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
00505  */
00506 /*@{*/
00507 #define BP_PORT_GPCLR_GPWE   (16U)         /*!< Bit position for PORT_GPCLR_GPWE. */
00508 #define BM_PORT_GPCLR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
00509 #define BS_PORT_GPCLR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
00510 
00511 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
00512 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
00513 
00514 /*! @brief Set the GPWE field to a new value. */
00515 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
00516 /*@}*/
00517 
00518 /*******************************************************************************
00519  * HW_PORT_GPCHR - Global Pin Control High Register
00520  ******************************************************************************/
00521 
00522 /*!
00523  * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
00524  *
00525  * Reset value: 0x00000000U
00526  *
00527  * Only 32-bit writes are supported to this register.
00528  */
00529 typedef union _hw_port_gpchr
00530 {
00531     uint32_t U;
00532     struct _hw_port_gpchr_bitfields
00533     {
00534         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
00535         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
00536     } B;
00537 } hw_port_gpchr_t;
00538 
00539 /*!
00540  * @name Constants and macros for entire PORT_GPCHR register
00541  */
00542 /*@{*/
00543 #define HW_PORT_GPCHR_ADDR(x)    ((x) + 0x84U)
00544 
00545 #define HW_PORT_GPCHR(x)         (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
00546 #define HW_PORT_GPCHR_RD(x)      (HW_PORT_GPCHR(x).U)
00547 #define HW_PORT_GPCHR_WR(x, v)   (HW_PORT_GPCHR(x).U = (v))
00548 /*@}*/
00549 
00550 /*
00551  * Constants & macros for individual PORT_GPCHR bitfields
00552  */
00553 
00554 /*!
00555  * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
00556  *
00557  * Write value that is written to all Pin Control Registers bits [15:0] that are
00558  * selected by GPWE.
00559  */
00560 /*@{*/
00561 #define BP_PORT_GPCHR_GPWD   (0U)          /*!< Bit position for PORT_GPCHR_GPWD. */
00562 #define BM_PORT_GPCHR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
00563 #define BS_PORT_GPCHR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
00564 
00565 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
00566 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
00567 
00568 /*! @brief Set the GPWD field to a new value. */
00569 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
00570 /*@}*/
00571 
00572 /*!
00573  * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
00574  *
00575  * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
00576  * the value in GPWD. If a selected Pin Control Register is locked then the write
00577  * to that register is ignored.
00578  *
00579  * Values:
00580  * - 0 - Corresponding Pin Control Register is not updated with the value in
00581  *     GPWD.
00582  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
00583  */
00584 /*@{*/
00585 #define BP_PORT_GPCHR_GPWE   (16U)         /*!< Bit position for PORT_GPCHR_GPWE. */
00586 #define BM_PORT_GPCHR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
00587 #define BS_PORT_GPCHR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
00588 
00589 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
00590 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
00591 
00592 /*! @brief Set the GPWE field to a new value. */
00593 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
00594 /*@}*/
00595 
00596 /*******************************************************************************
00597  * HW_PORT_ISFR - Interrupt Status Flag Register
00598  ******************************************************************************/
00599 
00600 /*!
00601  * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
00602  *
00603  * Reset value: 0x00000000U
00604  *
00605  * The pin interrupt configuration is valid in all digital pin muxing modes. The
00606  * Interrupt Status Flag for each pin is also visible in the corresponding Pin
00607  * Control Register, and each flag can be cleared in either location.
00608  */
00609 typedef union _hw_port_isfr
00610 {
00611     uint32_t U;
00612     struct _hw_port_isfr_bitfields
00613     {
00614         uint32_t ISF : 32;             /*!< [31:0] Interrupt Status Flag */
00615     } B;
00616 } hw_port_isfr_t;
00617 
00618 /*!
00619  * @name Constants and macros for entire PORT_ISFR register
00620  */
00621 /*@{*/
00622 #define HW_PORT_ISFR_ADDR(x)     ((x) + 0xA0U)
00623 
00624 #define HW_PORT_ISFR(x)          (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
00625 #define HW_PORT_ISFR_RD(x)       (HW_PORT_ISFR(x).U)
00626 #define HW_PORT_ISFR_WR(x, v)    (HW_PORT_ISFR(x).U = (v))
00627 #define HW_PORT_ISFR_SET(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) |  (v)))
00628 #define HW_PORT_ISFR_CLR(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
00629 #define HW_PORT_ISFR_TOG(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^  (v)))
00630 /*@}*/
00631 
00632 /*
00633  * Constants & macros for individual PORT_ISFR bitfields
00634  */
00635 
00636 /*!
00637  * @name Register PORT_ISFR, field ISF[31:0] (W1C)
00638  *
00639  * Each bit in the field indicates the detection of the configured interrupt of
00640  * the same number as the field.
00641  *
00642  * Values:
00643  * - 0 - Configured interrupt is not detected.
00644  * - 1 - Configured interrupt is detected. If the pin is configured to generate
00645  *     a DMA request, then the corresponding flag will be cleared automatically
00646  *     at the completion of the requested DMA transfer. Otherwise, the flag
00647  *     remains set until a logic 1 is written to the flag. If the pin is configured for
00648  *     a level sensitive interrupt and the pin remains asserted, then the flag
00649  *     is set again immediately after it is cleared.
00650  */
00651 /*@{*/
00652 #define BP_PORT_ISFR_ISF     (0U)          /*!< Bit position for PORT_ISFR_ISF. */
00653 #define BM_PORT_ISFR_ISF     (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
00654 #define BS_PORT_ISFR_ISF     (32U)         /*!< Bit field size in bits for PORT_ISFR_ISF. */
00655 
00656 /*! @brief Read current value of the PORT_ISFR_ISF field. */
00657 #define BR_PORT_ISFR_ISF(x)  (HW_PORT_ISFR(x).U)
00658 
00659 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
00660 #define BF_PORT_ISFR_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
00661 
00662 /*! @brief Set the ISF field to a new value. */
00663 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
00664 /*@}*/
00665 
00666 /*******************************************************************************
00667  * HW_PORT_DFER - Digital Filter Enable Register
00668  ******************************************************************************/
00669 
00670 /*!
00671  * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
00672  *
00673  * Reset value: 0x00000000U
00674  *
00675  * The corresponding bit is read only for pins that do not support a digital
00676  * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
00677  * the pins that support digital filter. The digital filter configuration is valid
00678  * in all digital pin muxing modes.
00679  */
00680 typedef union _hw_port_dfer
00681 {
00682     uint32_t U;
00683     struct _hw_port_dfer_bitfields
00684     {
00685         uint32_t DFE : 32;             /*!< [31:0] Digital Filter Enable */
00686     } B;
00687 } hw_port_dfer_t;
00688 
00689 /*!
00690  * @name Constants and macros for entire PORT_DFER register
00691  */
00692 /*@{*/
00693 #define HW_PORT_DFER_ADDR(x)     ((x) + 0xC0U)
00694 
00695 #define HW_PORT_DFER(x)          (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
00696 #define HW_PORT_DFER_RD(x)       (HW_PORT_DFER(x).U)
00697 #define HW_PORT_DFER_WR(x, v)    (HW_PORT_DFER(x).U = (v))
00698 #define HW_PORT_DFER_SET(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) |  (v)))
00699 #define HW_PORT_DFER_CLR(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
00700 #define HW_PORT_DFER_TOG(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^  (v)))
00701 /*@}*/
00702 
00703 /*
00704  * Constants & macros for individual PORT_DFER bitfields
00705  */
00706 
00707 /*!
00708  * @name Register PORT_DFER, field DFE[31:0] (RW)
00709  *
00710  * The digital filter configuration is valid in all digital pin muxing modes.
00711  * The output of each digital filter is reset to zero at system reset and whenever
00712  * the digital filter is disabled. Each bit in the field enables the digital
00713  * filter of the same number as the field.
00714  *
00715  * Values:
00716  * - 0 - Digital filter is disabled on the corresponding pin and output of the
00717  *     digital filter is reset to zero.
00718  * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
00719  *     configured as a digital input.
00720  */
00721 /*@{*/
00722 #define BP_PORT_DFER_DFE     (0U)          /*!< Bit position for PORT_DFER_DFE. */
00723 #define BM_PORT_DFER_DFE     (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
00724 #define BS_PORT_DFER_DFE     (32U)         /*!< Bit field size in bits for PORT_DFER_DFE. */
00725 
00726 /*! @brief Read current value of the PORT_DFER_DFE field. */
00727 #define BR_PORT_DFER_DFE(x)  (HW_PORT_DFER(x).U)
00728 
00729 /*! @brief Format value for bitfield PORT_DFER_DFE. */
00730 #define BF_PORT_DFER_DFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
00731 
00732 /*! @brief Set the DFE field to a new value. */
00733 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
00734 /*@}*/
00735 
00736 /*******************************************************************************
00737  * HW_PORT_DFCR - Digital Filter Clock Register
00738  ******************************************************************************/
00739 
00740 /*!
00741  * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
00742  *
00743  * Reset value: 0x00000000U
00744  *
00745  * This register is read only for ports that do not support a digital filter.
00746  * The digital filter configuration is valid in all digital pin muxing modes.
00747  */
00748 typedef union _hw_port_dfcr
00749 {
00750     uint32_t U;
00751     struct _hw_port_dfcr_bitfields
00752     {
00753         uint32_t CS : 1;               /*!< [0] Clock Source */
00754         uint32_t RESERVED0 : 31;       /*!< [31:1]  */
00755     } B;
00756 } hw_port_dfcr_t;
00757 
00758 /*!
00759  * @name Constants and macros for entire PORT_DFCR register
00760  */
00761 /*@{*/
00762 #define HW_PORT_DFCR_ADDR(x)     ((x) + 0xC4U)
00763 
00764 #define HW_PORT_DFCR(x)          (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
00765 #define HW_PORT_DFCR_RD(x)       (HW_PORT_DFCR(x).U)
00766 #define HW_PORT_DFCR_WR(x, v)    (HW_PORT_DFCR(x).U = (v))
00767 #define HW_PORT_DFCR_SET(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) |  (v)))
00768 #define HW_PORT_DFCR_CLR(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
00769 #define HW_PORT_DFCR_TOG(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^  (v)))
00770 /*@}*/
00771 
00772 /*
00773  * Constants & macros for individual PORT_DFCR bitfields
00774  */
00775 
00776 /*!
00777  * @name Register PORT_DFCR, field CS[0] (RW)
00778  *
00779  * The digital filter configuration is valid in all digital pin muxing modes.
00780  * Configures the clock source for the digital input filters. Changing the filter
00781  * clock source must be done only when all digital filters are disabled.
00782  *
00783  * Values:
00784  * - 0 - Digital filters are clocked by the bus clock.
00785  * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
00786  */
00787 /*@{*/
00788 #define BP_PORT_DFCR_CS      (0U)          /*!< Bit position for PORT_DFCR_CS. */
00789 #define BM_PORT_DFCR_CS      (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
00790 #define BS_PORT_DFCR_CS      (1U)          /*!< Bit field size in bits for PORT_DFCR_CS. */
00791 
00792 /*! @brief Read current value of the PORT_DFCR_CS field. */
00793 #define BR_PORT_DFCR_CS(x)   (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
00794 
00795 /*! @brief Format value for bitfield PORT_DFCR_CS. */
00796 #define BF_PORT_DFCR_CS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
00797 
00798 /*! @brief Set the CS field to a new value. */
00799 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
00800 /*@}*/
00801 
00802 /*******************************************************************************
00803  * HW_PORT_DFWR - Digital Filter Width Register
00804  ******************************************************************************/
00805 
00806 /*!
00807  * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
00808  *
00809  * Reset value: 0x00000000U
00810  *
00811  * This register is read only for ports that do not support a digital filter.
00812  * The digital filter configuration is valid in all digital pin muxing modes.
00813  */
00814 typedef union _hw_port_dfwr
00815 {
00816     uint32_t U;
00817     struct _hw_port_dfwr_bitfields
00818     {
00819         uint32_t FILT : 5;             /*!< [4:0] Filter Length */
00820         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
00821     } B;
00822 } hw_port_dfwr_t;
00823 
00824 /*!
00825  * @name Constants and macros for entire PORT_DFWR register
00826  */
00827 /*@{*/
00828 #define HW_PORT_DFWR_ADDR(x)     ((x) + 0xC8U)
00829 
00830 #define HW_PORT_DFWR(x)          (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
00831 #define HW_PORT_DFWR_RD(x)       (HW_PORT_DFWR(x).U)
00832 #define HW_PORT_DFWR_WR(x, v)    (HW_PORT_DFWR(x).U = (v))
00833 #define HW_PORT_DFWR_SET(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) |  (v)))
00834 #define HW_PORT_DFWR_CLR(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
00835 #define HW_PORT_DFWR_TOG(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^  (v)))
00836 /*@}*/
00837 
00838 /*
00839  * Constants & macros for individual PORT_DFWR bitfields
00840  */
00841 
00842 /*!
00843  * @name Register PORT_DFWR, field FILT[4:0] (RW)
00844  *
00845  * The digital filter configuration is valid in all digital pin muxing modes.
00846  * Configures the maximum size of the glitches, in clock cycles, that the digital
00847  * filter absorbs for the enabled digital filters. Glitches that are longer than
00848  * this register setting will pass through the digital filter, and glitches that
00849  * are equal to or less than this register setting are filtered. Changing the
00850  * filter length must be done only after all filters are disabled.
00851  */
00852 /*@{*/
00853 #define BP_PORT_DFWR_FILT    (0U)          /*!< Bit position for PORT_DFWR_FILT. */
00854 #define BM_PORT_DFWR_FILT    (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
00855 #define BS_PORT_DFWR_FILT    (5U)          /*!< Bit field size in bits for PORT_DFWR_FILT. */
00856 
00857 /*! @brief Read current value of the PORT_DFWR_FILT field. */
00858 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
00859 
00860 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
00861 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
00862 
00863 /*! @brief Set the FILT field to a new value. */
00864 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
00865 /*@}*/
00866 
00867 /*******************************************************************************
00868  * hw_port_t - module struct
00869  ******************************************************************************/
00870 /*!
00871  * @brief All PORT module registers.
00872  */
00873 #pragma pack(1)
00874 typedef struct _hw_port
00875 {
00876     __IO hw_port_pcrn_t PCRn [32];          /*!< [0x0] Pin Control Register n */
00877     __O hw_port_gpclr_t GPCLR ;             /*!< [0x80] Global Pin Control Low Register */
00878     __O hw_port_gpchr_t GPCHR ;             /*!< [0x84] Global Pin Control High Register */
00879     uint8_t _reserved0[24];
00880     __IO hw_port_isfr_t ISFR ;              /*!< [0xA0] Interrupt Status Flag Register */
00881     uint8_t _reserved1[28];
00882     __IO hw_port_dfer_t DFER ;              /*!< [0xC0] Digital Filter Enable Register */
00883     __IO hw_port_dfcr_t DFCR ;              /*!< [0xC4] Digital Filter Clock Register */
00884     __IO hw_port_dfwr_t DFWR ;              /*!< [0xC8] Digital Filter Width Register */
00885 } hw_port_t;
00886 #pragma pack()
00887 
00888 /*! @brief Macro to access all PORT registers. */
00889 /*! @param x PORT module instance base address. */
00890 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00891  *     use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
00892 #define HW_PORT(x)     (*(hw_port_t *)(x))
00893 
00894 #endif /* __HW_PORT_REGISTERS_H__ */
00895 /* EOF */