MK64F12_pmc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_PMC_REGISTERS_H__
00081 #define __HW_PMC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 PMC
00088  *
00089  * Power Management Controller
00090  *
00091  * Registers defined in this header file:
00092  * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
00093  * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
00094  * - HW_PMC_REGSC - Regulator Status And Control register
00095  *
00096  * - hw_pmc_t - Struct containing all module registers.
00097  */
00098 
00099 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
00100 
00101 /*******************************************************************************
00102  * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
00103  ******************************************************************************/
00104 
00105 /*!
00106  * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
00107  *
00108  * Reset value: 0x10U
00109  *
00110  * This register contains status and control bits to support the low voltage
00111  * detect function. This register should be written during the reset initialization
00112  * program to set the desired controls even if the desired settings are the same
00113  * as the reset settings. While the device is in the very low power or low
00114  * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
00115  * systems that must have LVD always on, configure the Power Mode Protection
00116  * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
00117  * low leakage modes from being enabled. See the device's data sheet for the
00118  * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
00119  * register's other bits are reset on Chip Reset Not VLLS. For more information
00120  * about these reset types, refer to the Reset section details.
00121  */
00122 typedef union _hw_pmc_lvdsc1
00123 {
00124     uint8_t U;
00125     struct _hw_pmc_lvdsc1_bitfields
00126     {
00127         uint8_t LVDV : 2;              /*!< [1:0] Low-Voltage Detect Voltage Select */
00128         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
00129         uint8_t LVDRE : 1;             /*!< [4] Low-Voltage Detect Reset Enable */
00130         uint8_t LVDIE : 1;             /*!< [5] Low-Voltage Detect Interrupt Enable */
00131         uint8_t LVDACK : 1;            /*!< [6] Low-Voltage Detect Acknowledge */
00132         uint8_t LVDF : 1;              /*!< [7] Low-Voltage Detect Flag */
00133     } B;
00134 } hw_pmc_lvdsc1_t;
00135 
00136 /*!
00137  * @name Constants and macros for entire PMC_LVDSC1 register
00138  */
00139 /*@{*/
00140 #define HW_PMC_LVDSC1_ADDR(x)    ((x) + 0x0U)
00141 
00142 #define HW_PMC_LVDSC1(x)         (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
00143 #define HW_PMC_LVDSC1_RD(x)      (HW_PMC_LVDSC1(x).U)
00144 #define HW_PMC_LVDSC1_WR(x, v)   (HW_PMC_LVDSC1(x).U = (v))
00145 #define HW_PMC_LVDSC1_SET(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) |  (v)))
00146 #define HW_PMC_LVDSC1_CLR(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
00147 #define HW_PMC_LVDSC1_TOG(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^  (v)))
00148 /*@}*/
00149 
00150 /*
00151  * Constants & macros for individual PMC_LVDSC1 bitfields
00152  */
00153 
00154 /*!
00155  * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
00156  *
00157  * Selects the LVD trip point voltage (V LVD ).
00158  *
00159  * Values:
00160  * - 00 - Low trip point selected (V LVD = V LVDL )
00161  * - 01 - High trip point selected (V LVD = V LVDH )
00162  * - 10 - Reserved
00163  * - 11 - Reserved
00164  */
00165 /*@{*/
00166 #define BP_PMC_LVDSC1_LVDV   (0U)          /*!< Bit position for PMC_LVDSC1_LVDV. */
00167 #define BM_PMC_LVDSC1_LVDV   (0x03U)       /*!< Bit mask for PMC_LVDSC1_LVDV. */
00168 #define BS_PMC_LVDSC1_LVDV   (2U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
00169 
00170 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
00171 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
00172 
00173 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
00174 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
00175 
00176 /*! @brief Set the LVDV field to a new value. */
00177 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
00178 /*@}*/
00179 
00180 /*!
00181  * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
00182  *
00183  * This write-once bit enables LVDF events to generate a hardware reset.
00184  * Additional writes are ignored.
00185  *
00186  * Values:
00187  * - 0 - LVDF does not generate hardware resets
00188  * - 1 - Force an MCU reset when LVDF = 1
00189  */
00190 /*@{*/
00191 #define BP_PMC_LVDSC1_LVDRE  (4U)          /*!< Bit position for PMC_LVDSC1_LVDRE. */
00192 #define BM_PMC_LVDSC1_LVDRE  (0x10U)       /*!< Bit mask for PMC_LVDSC1_LVDRE. */
00193 #define BS_PMC_LVDSC1_LVDRE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
00194 
00195 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
00196 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
00197 
00198 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
00199 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
00200 
00201 /*! @brief Set the LVDRE field to a new value. */
00202 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
00203 /*@}*/
00204 
00205 /*!
00206  * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
00207  *
00208  * Enables hardware interrupt requests for LVDF.
00209  *
00210  * Values:
00211  * - 0 - Hardware interrupt disabled (use polling)
00212  * - 1 - Request a hardware interrupt when LVDF = 1
00213  */
00214 /*@{*/
00215 #define BP_PMC_LVDSC1_LVDIE  (5U)          /*!< Bit position for PMC_LVDSC1_LVDIE. */
00216 #define BM_PMC_LVDSC1_LVDIE  (0x20U)       /*!< Bit mask for PMC_LVDSC1_LVDIE. */
00217 #define BS_PMC_LVDSC1_LVDIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
00218 
00219 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
00220 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
00221 
00222 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
00223 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
00224 
00225 /*! @brief Set the LVDIE field to a new value. */
00226 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
00227 /*@}*/
00228 
00229 /*!
00230  * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
00231  *
00232  * This write-only field is used to acknowledge low voltage detection errors.
00233  * Write 1 to clear LVDF. Reads always return 0.
00234  */
00235 /*@{*/
00236 #define BP_PMC_LVDSC1_LVDACK (6U)          /*!< Bit position for PMC_LVDSC1_LVDACK. */
00237 #define BM_PMC_LVDSC1_LVDACK (0x40U)       /*!< Bit mask for PMC_LVDSC1_LVDACK. */
00238 #define BS_PMC_LVDSC1_LVDACK (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
00239 
00240 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
00241 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
00242 
00243 /*! @brief Set the LVDACK field to a new value. */
00244 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
00245 /*@}*/
00246 
00247 /*!
00248  * @name Register PMC_LVDSC1, field LVDF[7] (RO)
00249  *
00250  * This read-only status field indicates a low-voltage detect event.
00251  *
00252  * Values:
00253  * - 0 - Low-voltage event not detected
00254  * - 1 - Low-voltage event detected
00255  */
00256 /*@{*/
00257 #define BP_PMC_LVDSC1_LVDF   (7U)          /*!< Bit position for PMC_LVDSC1_LVDF. */
00258 #define BM_PMC_LVDSC1_LVDF   (0x80U)       /*!< Bit mask for PMC_LVDSC1_LVDF. */
00259 #define BS_PMC_LVDSC1_LVDF   (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
00260 
00261 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
00262 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
00263 /*@}*/
00264 
00265 /*******************************************************************************
00266  * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
00267  ******************************************************************************/
00268 
00269 /*!
00270  * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
00271  *
00272  * Reset value: 0x00U
00273  *
00274  * This register contains status and control bits to support the low voltage
00275  * warning function. While the device is in the very low power or low leakage modes,
00276  * the LVD system is disabled regardless of LVDSC2 settings. See the device's
00277  * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
00278  * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
00279  * register are reset on Chip Reset Not VLLS. For more information about these
00280  * reset types, refer to the Reset section details.
00281  */
00282 typedef union _hw_pmc_lvdsc2
00283 {
00284     uint8_t U;
00285     struct _hw_pmc_lvdsc2_bitfields
00286     {
00287         uint8_t LVWV : 2;              /*!< [1:0] Low-Voltage Warning Voltage Select */
00288         uint8_t RESERVED0 : 3;         /*!< [4:2]  */
00289         uint8_t LVWIE : 1;             /*!< [5] Low-Voltage Warning Interrupt Enable */
00290         uint8_t LVWACK : 1;            /*!< [6] Low-Voltage Warning Acknowledge */
00291         uint8_t LVWF : 1;              /*!< [7] Low-Voltage Warning Flag */
00292     } B;
00293 } hw_pmc_lvdsc2_t;
00294 
00295 /*!
00296  * @name Constants and macros for entire PMC_LVDSC2 register
00297  */
00298 /*@{*/
00299 #define HW_PMC_LVDSC2_ADDR(x)    ((x) + 0x1U)
00300 
00301 #define HW_PMC_LVDSC2(x)         (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
00302 #define HW_PMC_LVDSC2_RD(x)      (HW_PMC_LVDSC2(x).U)
00303 #define HW_PMC_LVDSC2_WR(x, v)   (HW_PMC_LVDSC2(x).U = (v))
00304 #define HW_PMC_LVDSC2_SET(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) |  (v)))
00305 #define HW_PMC_LVDSC2_CLR(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
00306 #define HW_PMC_LVDSC2_TOG(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^  (v)))
00307 /*@}*/
00308 
00309 /*
00310  * Constants & macros for individual PMC_LVDSC2 bitfields
00311  */
00312 
00313 /*!
00314  * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
00315  *
00316  * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
00317  * depends on LVDSC1[LVDV].
00318  *
00319  * Values:
00320  * - 00 - Low trip point selected (VLVW = VLVW1)
00321  * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
00322  * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
00323  * - 11 - High trip point selected (VLVW = VLVW4)
00324  */
00325 /*@{*/
00326 #define BP_PMC_LVDSC2_LVWV   (0U)          /*!< Bit position for PMC_LVDSC2_LVWV. */
00327 #define BM_PMC_LVDSC2_LVWV   (0x03U)       /*!< Bit mask for PMC_LVDSC2_LVWV. */
00328 #define BS_PMC_LVDSC2_LVWV   (2U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
00329 
00330 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
00331 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
00332 
00333 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
00334 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
00335 
00336 /*! @brief Set the LVWV field to a new value. */
00337 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
00338 /*@}*/
00339 
00340 /*!
00341  * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
00342  *
00343  * Enables hardware interrupt requests for LVWF.
00344  *
00345  * Values:
00346  * - 0 - Hardware interrupt disabled (use polling)
00347  * - 1 - Request a hardware interrupt when LVWF = 1
00348  */
00349 /*@{*/
00350 #define BP_PMC_LVDSC2_LVWIE  (5U)          /*!< Bit position for PMC_LVDSC2_LVWIE. */
00351 #define BM_PMC_LVDSC2_LVWIE  (0x20U)       /*!< Bit mask for PMC_LVDSC2_LVWIE. */
00352 #define BS_PMC_LVDSC2_LVWIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
00353 
00354 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
00355 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
00356 
00357 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
00358 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
00359 
00360 /*! @brief Set the LVWIE field to a new value. */
00361 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
00362 /*@}*/
00363 
00364 /*!
00365  * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
00366  *
00367  * This write-only field is used to acknowledge low voltage warning errors.
00368  * Write 1 to clear LVWF. Reads always return 0.
00369  */
00370 /*@{*/
00371 #define BP_PMC_LVDSC2_LVWACK (6U)          /*!< Bit position for PMC_LVDSC2_LVWACK. */
00372 #define BM_PMC_LVDSC2_LVWACK (0x40U)       /*!< Bit mask for PMC_LVDSC2_LVWACK. */
00373 #define BS_PMC_LVDSC2_LVWACK (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
00374 
00375 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
00376 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
00377 
00378 /*! @brief Set the LVWACK field to a new value. */
00379 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
00380 /*@}*/
00381 
00382 /*!
00383  * @name Register PMC_LVDSC2, field LVWF[7] (RO)
00384  *
00385  * This read-only status field indicates a low-voltage warning event. LVWF is
00386  * set when VSupply transitions below the trip point, or after reset and VSupply is
00387  * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
00388  * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
00389  * LVWACK first.
00390  *
00391  * Values:
00392  * - 0 - Low-voltage warning event not detected
00393  * - 1 - Low-voltage warning event detected
00394  */
00395 /*@{*/
00396 #define BP_PMC_LVDSC2_LVWF   (7U)          /*!< Bit position for PMC_LVDSC2_LVWF. */
00397 #define BM_PMC_LVDSC2_LVWF   (0x80U)       /*!< Bit mask for PMC_LVDSC2_LVWF. */
00398 #define BS_PMC_LVDSC2_LVWF   (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
00399 
00400 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
00401 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
00402 /*@}*/
00403 
00404 /*******************************************************************************
00405  * HW_PMC_REGSC - Regulator Status And Control register
00406  ******************************************************************************/
00407 
00408 /*!
00409  * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
00410  *
00411  * Reset value: 0x04U
00412  *
00413  * The PMC contains an internal voltage regulator. The voltage regulator design
00414  * uses a bandgap reference that is also available through a buffer as input to
00415  * certain internal peripherals, such as the CMP and ADC. The internal regulator
00416  * provides a status bit (REGONS) indicating the regulator is in run regulation.
00417  * This register is reset on Chip Reset Not VLLS and by reset types that trigger
00418  * Chip Reset not VLLS. See the Reset section details for more information.
00419  */
00420 typedef union _hw_pmc_regsc
00421 {
00422     uint8_t U;
00423     struct _hw_pmc_regsc_bitfields
00424     {
00425         uint8_t BGBE : 1;              /*!< [0] Bandgap Buffer Enable */
00426         uint8_t RESERVED0 : 1;         /*!< [1]  */
00427         uint8_t REGONS : 1;            /*!< [2] Regulator In Run Regulation Status */
00428         uint8_t ACKISO : 1;            /*!< [3] Acknowledge Isolation */
00429         uint8_t BGEN : 1;              /*!< [4] Bandgap Enable In VLPx Operation */
00430         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
00431     } B;
00432 } hw_pmc_regsc_t;
00433 
00434 /*!
00435  * @name Constants and macros for entire PMC_REGSC register
00436  */
00437 /*@{*/
00438 #define HW_PMC_REGSC_ADDR(x)     ((x) + 0x2U)
00439 
00440 #define HW_PMC_REGSC(x)          (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
00441 #define HW_PMC_REGSC_RD(x)       (HW_PMC_REGSC(x).U)
00442 #define HW_PMC_REGSC_WR(x, v)    (HW_PMC_REGSC(x).U = (v))
00443 #define HW_PMC_REGSC_SET(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) |  (v)))
00444 #define HW_PMC_REGSC_CLR(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
00445 #define HW_PMC_REGSC_TOG(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^  (v)))
00446 /*@}*/
00447 
00448 /*
00449  * Constants & macros for individual PMC_REGSC bitfields
00450  */
00451 
00452 /*!
00453  * @name Register PMC_REGSC, field BGBE[0] (RW)
00454  *
00455  * Enables the bandgap buffer.
00456  *
00457  * Values:
00458  * - 0 - Bandgap buffer not enabled
00459  * - 1 - Bandgap buffer enabled
00460  */
00461 /*@{*/
00462 #define BP_PMC_REGSC_BGBE    (0U)          /*!< Bit position for PMC_REGSC_BGBE. */
00463 #define BM_PMC_REGSC_BGBE    (0x01U)       /*!< Bit mask for PMC_REGSC_BGBE. */
00464 #define BS_PMC_REGSC_BGBE    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGBE. */
00465 
00466 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
00467 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
00468 
00469 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
00470 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
00471 
00472 /*! @brief Set the BGBE field to a new value. */
00473 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
00474 /*@}*/
00475 
00476 /*!
00477  * @name Register PMC_REGSC, field REGONS[2] (RO)
00478  *
00479  * This read-only field provides the current status of the internal voltage
00480  * regulator.
00481  *
00482  * Values:
00483  * - 0 - Regulator is in stop regulation or in transition to/from it
00484  * - 1 - Regulator is in run regulation
00485  */
00486 /*@{*/
00487 #define BP_PMC_REGSC_REGONS  (2U)          /*!< Bit position for PMC_REGSC_REGONS. */
00488 #define BM_PMC_REGSC_REGONS  (0x04U)       /*!< Bit mask for PMC_REGSC_REGONS. */
00489 #define BS_PMC_REGSC_REGONS  (1U)          /*!< Bit field size in bits for PMC_REGSC_REGONS. */
00490 
00491 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
00492 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
00493 /*@}*/
00494 
00495 /*!
00496  * @name Register PMC_REGSC, field ACKISO[3] (W1C)
00497  *
00498  * Reading this field indicates whether certain peripherals and the I/O pads are
00499  * in a latched state as a result of having been in a VLLS mode. Writing 1 to
00500  * this field when it is set releases the I/O pads and certain peripherals to their
00501  * normal run mode state. After recovering from a VLLS mode, user should restore
00502  * chip configuration before clearing ACKISO. In particular, pin configuration
00503  * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
00504  * being falsely set when ACKISO is cleared.
00505  *
00506  * Values:
00507  * - 0 - Peripherals and I/O pads are in normal run state.
00508  * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
00509  */
00510 /*@{*/
00511 #define BP_PMC_REGSC_ACKISO  (3U)          /*!< Bit position for PMC_REGSC_ACKISO. */
00512 #define BM_PMC_REGSC_ACKISO  (0x08U)       /*!< Bit mask for PMC_REGSC_ACKISO. */
00513 #define BS_PMC_REGSC_ACKISO  (1U)          /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
00514 
00515 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
00516 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
00517 
00518 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
00519 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
00520 
00521 /*! @brief Set the ACKISO field to a new value. */
00522 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
00523 /*@}*/
00524 
00525 /*!
00526  * @name Register PMC_REGSC, field BGEN[4] (RW)
00527  *
00528  * BGEN controls whether the bandgap is enabled in lower power modes of
00529  * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
00530  * reference in low power modes of operation, set BGEN to continue to enable the
00531  * bandgap operation. When the bandgap voltage reference is not needed in low
00532  * power modes, clear BGEN to avoid excess power consumption.
00533  *
00534  * Values:
00535  * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
00536  * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
00537  */
00538 /*@{*/
00539 #define BP_PMC_REGSC_BGEN    (4U)          /*!< Bit position for PMC_REGSC_BGEN. */
00540 #define BM_PMC_REGSC_BGEN    (0x10U)       /*!< Bit mask for PMC_REGSC_BGEN. */
00541 #define BS_PMC_REGSC_BGEN    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGEN. */
00542 
00543 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
00544 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
00545 
00546 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
00547 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
00548 
00549 /*! @brief Set the BGEN field to a new value. */
00550 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
00551 /*@}*/
00552 
00553 /*******************************************************************************
00554  * hw_pmc_t - module struct
00555  ******************************************************************************/
00556 /*!
00557  * @brief All PMC module registers.
00558  */
00559 #pragma pack(1)
00560 typedef struct _hw_pmc
00561 {
00562     __IO hw_pmc_lvdsc1_t LVDSC1 ;           /*!< [0x0] Low Voltage Detect Status And Control 1 register */
00563     __IO hw_pmc_lvdsc2_t LVDSC2 ;           /*!< [0x1] Low Voltage Detect Status And Control 2 register */
00564     __IO hw_pmc_regsc_t REGSC ;             /*!< [0x2] Regulator Status And Control register */
00565 } hw_pmc_t;
00566 #pragma pack()
00567 
00568 /*! @brief Macro to access all PMC registers. */
00569 /*! @param x PMC module instance base address. */
00570 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00571  *     use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
00572 #define HW_PMC(x)      (*(hw_pmc_t *)(x))
00573 
00574 #endif /* __HW_PMC_REGISTERS_H__ */
00575 /* EOF */