MK64F12_pdb.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_PDB_REGISTERS_H__
00081 #define __HW_PDB_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 PDB
00088  *
00089  * Programmable Delay Block
00090  *
00091  * Registers defined in this header file:
00092  * - HW_PDB_SC - Status and Control register
00093  * - HW_PDB_MOD - Modulus register
00094  * - HW_PDB_CNT - Counter register
00095  * - HW_PDB_IDLY - Interrupt Delay register
00096  * - HW_PDB_CHnC1 - Channel n Control register 1
00097  * - HW_PDB_CHnS - Channel n Status register
00098  * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
00099  * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
00100  * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
00101  * - HW_PDB_DACINTn - DAC Interval n register
00102  * - HW_PDB_POEN - Pulse-Out n Enable register
00103  * - HW_PDB_POnDLY - Pulse-Out n Delay register
00104  *
00105  * - hw_pdb_t - Struct containing all module registers.
00106  */
00107 
00108 #define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
00109 
00110 /*******************************************************************************
00111  * HW_PDB_SC - Status and Control register
00112  ******************************************************************************/
00113 
00114 /*!
00115  * @brief HW_PDB_SC - Status and Control register (RW)
00116  *
00117  * Reset value: 0x00000000U
00118  */
00119 typedef union _hw_pdb_sc
00120 {
00121     uint32_t U;
00122     struct _hw_pdb_sc_bitfields
00123     {
00124         uint32_t LDOK : 1;             /*!< [0] Load OK */
00125         uint32_t CONT : 1;             /*!< [1] Continuous Mode Enable */
00126         uint32_t MULT : 2;             /*!< [3:2] Multiplication Factor Select for
00127                                         * Prescaler */
00128         uint32_t RESERVED0 : 1;        /*!< [4]  */
00129         uint32_t PDBIE : 1;            /*!< [5] PDB Interrupt Enable */
00130         uint32_t PDBIF : 1;            /*!< [6] PDB Interrupt Flag */
00131         uint32_t PDBEN : 1;            /*!< [7] PDB Enable */
00132         uint32_t TRGSEL : 4;           /*!< [11:8] Trigger Input Source Select */
00133         uint32_t PRESCALER : 3;        /*!< [14:12] Prescaler Divider Select */
00134         uint32_t DMAEN : 1;            /*!< [15] DMA Enable */
00135         uint32_t SWTRIG : 1;           /*!< [16] Software Trigger */
00136         uint32_t PDBEIE : 1;           /*!< [17] PDB Sequence Error Interrupt Enable */
00137         uint32_t LDMOD : 2;            /*!< [19:18] Load Mode Select */
00138         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
00139     } B;
00140 } hw_pdb_sc_t;
00141 
00142 /*!
00143  * @name Constants and macros for entire PDB_SC register
00144  */
00145 /*@{*/
00146 #define HW_PDB_SC_ADDR(x)        ((x) + 0x0U)
00147 
00148 #define HW_PDB_SC(x)             (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x))
00149 #define HW_PDB_SC_RD(x)          (HW_PDB_SC(x).U)
00150 #define HW_PDB_SC_WR(x, v)       (HW_PDB_SC(x).U = (v))
00151 #define HW_PDB_SC_SET(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) |  (v)))
00152 #define HW_PDB_SC_CLR(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
00153 #define HW_PDB_SC_TOG(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^  (v)))
00154 /*@}*/
00155 
00156 /*
00157  * Constants & macros for individual PDB_SC bitfields
00158  */
00159 
00160 /*!
00161  * @name Register PDB_SC, field LDOK[0] (RW)
00162  *
00163  * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
00164  * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
00165  * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
00166  * written to the LDOK field, the values in the buffers of above registers are
00167  * not effective and the buffers cannot be written until the values in buffers are
00168  * loaded into their internal registers. LDOK can be written only when PDBEN is
00169  * set or it can be written at the same time with PDBEN being written to 1. It is
00170  * automatically cleared when the values in buffers are loaded into the internal
00171  * registers or the PDBEN is cleared. Writing 0 to it has no effect.
00172  */
00173 /*@{*/
00174 #define BP_PDB_SC_LDOK       (0U)          /*!< Bit position for PDB_SC_LDOK. */
00175 #define BM_PDB_SC_LDOK       (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */
00176 #define BS_PDB_SC_LDOK       (1U)          /*!< Bit field size in bits for PDB_SC_LDOK. */
00177 
00178 /*! @brief Read current value of the PDB_SC_LDOK field. */
00179 #define BR_PDB_SC_LDOK(x)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK))
00180 
00181 /*! @brief Format value for bitfield PDB_SC_LDOK. */
00182 #define BF_PDB_SC_LDOK(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
00183 
00184 /*! @brief Set the LDOK field to a new value. */
00185 #define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v))
00186 /*@}*/
00187 
00188 /*!
00189  * @name Register PDB_SC, field CONT[1] (RW)
00190  *
00191  * Enables the PDB operation in Continuous mode.
00192  *
00193  * Values:
00194  * - 0 - PDB operation in One-Shot mode
00195  * - 1 - PDB operation in Continuous mode
00196  */
00197 /*@{*/
00198 #define BP_PDB_SC_CONT       (1U)          /*!< Bit position for PDB_SC_CONT. */
00199 #define BM_PDB_SC_CONT       (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */
00200 #define BS_PDB_SC_CONT       (1U)          /*!< Bit field size in bits for PDB_SC_CONT. */
00201 
00202 /*! @brief Read current value of the PDB_SC_CONT field. */
00203 #define BR_PDB_SC_CONT(x)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT))
00204 
00205 /*! @brief Format value for bitfield PDB_SC_CONT. */
00206 #define BF_PDB_SC_CONT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
00207 
00208 /*! @brief Set the CONT field to a new value. */
00209 #define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v))
00210 /*@}*/
00211 
00212 /*!
00213  * @name Register PDB_SC, field MULT[3:2] (RW)
00214  *
00215  * Selects the multiplication factor of the prescaler divider for the counter
00216  * clock.
00217  *
00218  * Values:
00219  * - 00 - Multiplication factor is 1.
00220  * - 01 - Multiplication factor is 10.
00221  * - 10 - Multiplication factor is 20.
00222  * - 11 - Multiplication factor is 40.
00223  */
00224 /*@{*/
00225 #define BP_PDB_SC_MULT       (2U)          /*!< Bit position for PDB_SC_MULT. */
00226 #define BM_PDB_SC_MULT       (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */
00227 #define BS_PDB_SC_MULT       (2U)          /*!< Bit field size in bits for PDB_SC_MULT. */
00228 
00229 /*! @brief Read current value of the PDB_SC_MULT field. */
00230 #define BR_PDB_SC_MULT(x)    (HW_PDB_SC(x).B.MULT)
00231 
00232 /*! @brief Format value for bitfield PDB_SC_MULT. */
00233 #define BF_PDB_SC_MULT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
00234 
00235 /*! @brief Set the MULT field to a new value. */
00236 #define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
00237 /*@}*/
00238 
00239 /*!
00240  * @name Register PDB_SC, field PDBIE[5] (RW)
00241  *
00242  * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
00243  * generates a PDB interrupt.
00244  *
00245  * Values:
00246  * - 0 - PDB interrupt disabled.
00247  * - 1 - PDB interrupt enabled.
00248  */
00249 /*@{*/
00250 #define BP_PDB_SC_PDBIE      (5U)          /*!< Bit position for PDB_SC_PDBIE. */
00251 #define BM_PDB_SC_PDBIE      (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */
00252 #define BS_PDB_SC_PDBIE      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIE. */
00253 
00254 /*! @brief Read current value of the PDB_SC_PDBIE field. */
00255 #define BR_PDB_SC_PDBIE(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE))
00256 
00257 /*! @brief Format value for bitfield PDB_SC_PDBIE. */
00258 #define BF_PDB_SC_PDBIE(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
00259 
00260 /*! @brief Set the PDBIE field to a new value. */
00261 #define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v))
00262 /*@}*/
00263 
00264 /*!
00265  * @name Register PDB_SC, field PDBIF[6] (RW)
00266  *
00267  * This field is set when the counter value is equal to the IDLY register.
00268  * Writing zero clears this field.
00269  */
00270 /*@{*/
00271 #define BP_PDB_SC_PDBIF      (6U)          /*!< Bit position for PDB_SC_PDBIF. */
00272 #define BM_PDB_SC_PDBIF      (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */
00273 #define BS_PDB_SC_PDBIF      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIF. */
00274 
00275 /*! @brief Read current value of the PDB_SC_PDBIF field. */
00276 #define BR_PDB_SC_PDBIF(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF))
00277 
00278 /*! @brief Format value for bitfield PDB_SC_PDBIF. */
00279 #define BF_PDB_SC_PDBIF(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
00280 
00281 /*! @brief Set the PDBIF field to a new value. */
00282 #define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v))
00283 /*@}*/
00284 
00285 /*!
00286  * @name Register PDB_SC, field PDBEN[7] (RW)
00287  *
00288  * Values:
00289  * - 0 - PDB disabled. Counter is off.
00290  * - 1 - PDB enabled.
00291  */
00292 /*@{*/
00293 #define BP_PDB_SC_PDBEN      (7U)          /*!< Bit position for PDB_SC_PDBEN. */
00294 #define BM_PDB_SC_PDBEN      (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */
00295 #define BS_PDB_SC_PDBEN      (1U)          /*!< Bit field size in bits for PDB_SC_PDBEN. */
00296 
00297 /*! @brief Read current value of the PDB_SC_PDBEN field. */
00298 #define BR_PDB_SC_PDBEN(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN))
00299 
00300 /*! @brief Format value for bitfield PDB_SC_PDBEN. */
00301 #define BF_PDB_SC_PDBEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
00302 
00303 /*! @brief Set the PDBEN field to a new value. */
00304 #define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v))
00305 /*@}*/
00306 
00307 /*!
00308  * @name Register PDB_SC, field TRGSEL[11:8] (RW)
00309  *
00310  * Selects the trigger input source for the PDB. The trigger input source can be
00311  * internal or external (EXTRG pin), or the software trigger. Refer to chip
00312  * configuration details for the actual PDB input trigger connections.
00313  *
00314  * Values:
00315  * - 0000 - Trigger-In 0 is selected.
00316  * - 0001 - Trigger-In 1 is selected.
00317  * - 0010 - Trigger-In 2 is selected.
00318  * - 0011 - Trigger-In 3 is selected.
00319  * - 0100 - Trigger-In 4 is selected.
00320  * - 0101 - Trigger-In 5 is selected.
00321  * - 0110 - Trigger-In 6 is selected.
00322  * - 0111 - Trigger-In 7 is selected.
00323  * - 1000 - Trigger-In 8 is selected.
00324  * - 1001 - Trigger-In 9 is selected.
00325  * - 1010 - Trigger-In 10 is selected.
00326  * - 1011 - Trigger-In 11 is selected.
00327  * - 1100 - Trigger-In 12 is selected.
00328  * - 1101 - Trigger-In 13 is selected.
00329  * - 1110 - Trigger-In 14 is selected.
00330  * - 1111 - Software trigger is selected.
00331  */
00332 /*@{*/
00333 #define BP_PDB_SC_TRGSEL     (8U)          /*!< Bit position for PDB_SC_TRGSEL. */
00334 #define BM_PDB_SC_TRGSEL     (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */
00335 #define BS_PDB_SC_TRGSEL     (4U)          /*!< Bit field size in bits for PDB_SC_TRGSEL. */
00336 
00337 /*! @brief Read current value of the PDB_SC_TRGSEL field. */
00338 #define BR_PDB_SC_TRGSEL(x)  (HW_PDB_SC(x).B.TRGSEL)
00339 
00340 /*! @brief Format value for bitfield PDB_SC_TRGSEL. */
00341 #define BF_PDB_SC_TRGSEL(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
00342 
00343 /*! @brief Set the TRGSEL field to a new value. */
00344 #define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
00345 /*@}*/
00346 
00347 /*!
00348  * @name Register PDB_SC, field PRESCALER[14:12] (RW)
00349  *
00350  * Values:
00351  * - 000 - Counting uses the peripheral clock divided by multiplication factor
00352  *     selected by MULT.
00353  * - 001 - Counting uses the peripheral clock divided by twice of the
00354  *     multiplication factor selected by MULT.
00355  * - 010 - Counting uses the peripheral clock divided by four times of the
00356  *     multiplication factor selected by MULT.
00357  * - 011 - Counting uses the peripheral clock divided by eight times of the
00358  *     multiplication factor selected by MULT.
00359  * - 100 - Counting uses the peripheral clock divided by 16 times of the
00360  *     multiplication factor selected by MULT.
00361  * - 101 - Counting uses the peripheral clock divided by 32 times of the
00362  *     multiplication factor selected by MULT.
00363  * - 110 - Counting uses the peripheral clock divided by 64 times of the
00364  *     multiplication factor selected by MULT.
00365  * - 111 - Counting uses the peripheral clock divided by 128 times of the
00366  *     multiplication factor selected by MULT.
00367  */
00368 /*@{*/
00369 #define BP_PDB_SC_PRESCALER  (12U)         /*!< Bit position for PDB_SC_PRESCALER. */
00370 #define BM_PDB_SC_PRESCALER  (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */
00371 #define BS_PDB_SC_PRESCALER  (3U)          /*!< Bit field size in bits for PDB_SC_PRESCALER. */
00372 
00373 /*! @brief Read current value of the PDB_SC_PRESCALER field. */
00374 #define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER)
00375 
00376 /*! @brief Format value for bitfield PDB_SC_PRESCALER. */
00377 #define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
00378 
00379 /*! @brief Set the PRESCALER field to a new value. */
00380 #define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
00381 /*@}*/
00382 
00383 /*!
00384  * @name Register PDB_SC, field DMAEN[15] (RW)
00385  *
00386  * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
00387  * interrupt.
00388  *
00389  * Values:
00390  * - 0 - DMA disabled.
00391  * - 1 - DMA enabled.
00392  */
00393 /*@{*/
00394 #define BP_PDB_SC_DMAEN      (15U)         /*!< Bit position for PDB_SC_DMAEN. */
00395 #define BM_PDB_SC_DMAEN      (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */
00396 #define BS_PDB_SC_DMAEN      (1U)          /*!< Bit field size in bits for PDB_SC_DMAEN. */
00397 
00398 /*! @brief Read current value of the PDB_SC_DMAEN field. */
00399 #define BR_PDB_SC_DMAEN(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN))
00400 
00401 /*! @brief Format value for bitfield PDB_SC_DMAEN. */
00402 #define BF_PDB_SC_DMAEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
00403 
00404 /*! @brief Set the DMAEN field to a new value. */
00405 #define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v))
00406 /*@}*/
00407 
00408 /*!
00409  * @name Register PDB_SC, field SWTRIG[16] (WORZ)
00410  *
00411  * When PDB is enabled and the software trigger is selected as the trigger input
00412  * source, writing 1 to this field resets and restarts the counter. Writing 0 to
00413  * this field has no effect. Reading this field results 0.
00414  */
00415 /*@{*/
00416 #define BP_PDB_SC_SWTRIG     (16U)         /*!< Bit position for PDB_SC_SWTRIG. */
00417 #define BM_PDB_SC_SWTRIG     (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */
00418 #define BS_PDB_SC_SWTRIG     (1U)          /*!< Bit field size in bits for PDB_SC_SWTRIG. */
00419 
00420 /*! @brief Format value for bitfield PDB_SC_SWTRIG. */
00421 #define BF_PDB_SC_SWTRIG(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
00422 
00423 /*! @brief Set the SWTRIG field to a new value. */
00424 #define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v))
00425 /*@}*/
00426 
00427 /*!
00428  * @name Register PDB_SC, field PDBEIE[17] (RW)
00429  *
00430  * Enables the PDB sequence error interrupt. When this field is set, any of the
00431  * PDB channel sequence error flags generates a PDB sequence error interrupt.
00432  *
00433  * Values:
00434  * - 0 - PDB sequence error interrupt disabled.
00435  * - 1 - PDB sequence error interrupt enabled.
00436  */
00437 /*@{*/
00438 #define BP_PDB_SC_PDBEIE     (17U)         /*!< Bit position for PDB_SC_PDBEIE. */
00439 #define BM_PDB_SC_PDBEIE     (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */
00440 #define BS_PDB_SC_PDBEIE     (1U)          /*!< Bit field size in bits for PDB_SC_PDBEIE. */
00441 
00442 /*! @brief Read current value of the PDB_SC_PDBEIE field. */
00443 #define BR_PDB_SC_PDBEIE(x)  (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE))
00444 
00445 /*! @brief Format value for bitfield PDB_SC_PDBEIE. */
00446 #define BF_PDB_SC_PDBEIE(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
00447 
00448 /*! @brief Set the PDBEIE field to a new value. */
00449 #define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v))
00450 /*@}*/
00451 
00452 /*!
00453  * @name Register PDB_SC, field LDMOD[19:18] (RW)
00454  *
00455  * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
00456  * after 1 is written to LDOK.
00457  *
00458  * Values:
00459  * - 00 - The internal registers are loaded with the values from their buffers
00460  *     immediately after 1 is written to LDOK.
00461  * - 01 - The internal registers are loaded with the values from their buffers
00462  *     when the PDB counter reaches the MOD register value after 1 is written to
00463  *     LDOK.
00464  * - 10 - The internal registers are loaded with the values from their buffers
00465  *     when a trigger input event is detected after 1 is written to LDOK.
00466  * - 11 - The internal registers are loaded with the values from their buffers
00467  *     when either the PDB counter reaches the MOD register value or a trigger
00468  *     input event is detected, after 1 is written to LDOK.
00469  */
00470 /*@{*/
00471 #define BP_PDB_SC_LDMOD      (18U)         /*!< Bit position for PDB_SC_LDMOD. */
00472 #define BM_PDB_SC_LDMOD      (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */
00473 #define BS_PDB_SC_LDMOD      (2U)          /*!< Bit field size in bits for PDB_SC_LDMOD. */
00474 
00475 /*! @brief Read current value of the PDB_SC_LDMOD field. */
00476 #define BR_PDB_SC_LDMOD(x)   (HW_PDB_SC(x).B.LDMOD)
00477 
00478 /*! @brief Format value for bitfield PDB_SC_LDMOD. */
00479 #define BF_PDB_SC_LDMOD(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
00480 
00481 /*! @brief Set the LDMOD field to a new value. */
00482 #define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
00483 /*@}*/
00484 
00485 /*******************************************************************************
00486  * HW_PDB_MOD - Modulus register
00487  ******************************************************************************/
00488 
00489 /*!
00490  * @brief HW_PDB_MOD - Modulus register (RW)
00491  *
00492  * Reset value: 0x0000FFFFU
00493  */
00494 typedef union _hw_pdb_mod
00495 {
00496     uint32_t U;
00497     struct _hw_pdb_mod_bitfields
00498     {
00499         uint32_t MOD : 16;             /*!< [15:0] PDB Modulus */
00500         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00501     } B;
00502 } hw_pdb_mod_t;
00503 
00504 /*!
00505  * @name Constants and macros for entire PDB_MOD register
00506  */
00507 /*@{*/
00508 #define HW_PDB_MOD_ADDR(x)       ((x) + 0x4U)
00509 
00510 #define HW_PDB_MOD(x)            (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x))
00511 #define HW_PDB_MOD_RD(x)         (HW_PDB_MOD(x).U)
00512 #define HW_PDB_MOD_WR(x, v)      (HW_PDB_MOD(x).U = (v))
00513 #define HW_PDB_MOD_SET(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) |  (v)))
00514 #define HW_PDB_MOD_CLR(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
00515 #define HW_PDB_MOD_TOG(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^  (v)))
00516 /*@}*/
00517 
00518 /*
00519  * Constants & macros for individual PDB_MOD bitfields
00520  */
00521 
00522 /*!
00523  * @name Register PDB_MOD, field MOD[15:0] (RW)
00524  *
00525  * Specifies the period of the counter. When the counter reaches this value, it
00526  * will be reset back to zero. If the PDB is in Continuous mode, the count begins
00527  * anew. Reading this field returns the value of the internal register that is
00528  * effective for the current cycle of PDB.
00529  */
00530 /*@{*/
00531 #define BP_PDB_MOD_MOD       (0U)          /*!< Bit position for PDB_MOD_MOD. */
00532 #define BM_PDB_MOD_MOD       (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */
00533 #define BS_PDB_MOD_MOD       (16U)         /*!< Bit field size in bits for PDB_MOD_MOD. */
00534 
00535 /*! @brief Read current value of the PDB_MOD_MOD field. */
00536 #define BR_PDB_MOD_MOD(x)    (HW_PDB_MOD(x).B.MOD)
00537 
00538 /*! @brief Format value for bitfield PDB_MOD_MOD. */
00539 #define BF_PDB_MOD_MOD(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
00540 
00541 /*! @brief Set the MOD field to a new value. */
00542 #define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
00543 /*@}*/
00544 
00545 /*******************************************************************************
00546  * HW_PDB_CNT - Counter register
00547  ******************************************************************************/
00548 
00549 /*!
00550  * @brief HW_PDB_CNT - Counter register (RO)
00551  *
00552  * Reset value: 0x00000000U
00553  */
00554 typedef union _hw_pdb_cnt
00555 {
00556     uint32_t U;
00557     struct _hw_pdb_cnt_bitfields
00558     {
00559         uint32_t CNT : 16;             /*!< [15:0] PDB Counter */
00560         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00561     } B;
00562 } hw_pdb_cnt_t;
00563 
00564 /*!
00565  * @name Constants and macros for entire PDB_CNT register
00566  */
00567 /*@{*/
00568 #define HW_PDB_CNT_ADDR(x)       ((x) + 0x8U)
00569 
00570 #define HW_PDB_CNT(x)            (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x))
00571 #define HW_PDB_CNT_RD(x)         (HW_PDB_CNT(x).U)
00572 /*@}*/
00573 
00574 /*
00575  * Constants & macros for individual PDB_CNT bitfields
00576  */
00577 
00578 /*!
00579  * @name Register PDB_CNT, field CNT[15:0] (RO)
00580  *
00581  * Contains the current value of the counter.
00582  */
00583 /*@{*/
00584 #define BP_PDB_CNT_CNT       (0U)          /*!< Bit position for PDB_CNT_CNT. */
00585 #define BM_PDB_CNT_CNT       (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */
00586 #define BS_PDB_CNT_CNT       (16U)         /*!< Bit field size in bits for PDB_CNT_CNT. */
00587 
00588 /*! @brief Read current value of the PDB_CNT_CNT field. */
00589 #define BR_PDB_CNT_CNT(x)    (HW_PDB_CNT(x).B.CNT)
00590 /*@}*/
00591 
00592 /*******************************************************************************
00593  * HW_PDB_IDLY - Interrupt Delay register
00594  ******************************************************************************/
00595 
00596 /*!
00597  * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
00598  *
00599  * Reset value: 0x0000FFFFU
00600  */
00601 typedef union _hw_pdb_idly
00602 {
00603     uint32_t U;
00604     struct _hw_pdb_idly_bitfields
00605     {
00606         uint32_t IDLY : 16;            /*!< [15:0] PDB Interrupt Delay */
00607         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00608     } B;
00609 } hw_pdb_idly_t;
00610 
00611 /*!
00612  * @name Constants and macros for entire PDB_IDLY register
00613  */
00614 /*@{*/
00615 #define HW_PDB_IDLY_ADDR(x)      ((x) + 0xCU)
00616 
00617 #define HW_PDB_IDLY(x)           (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x))
00618 #define HW_PDB_IDLY_RD(x)        (HW_PDB_IDLY(x).U)
00619 #define HW_PDB_IDLY_WR(x, v)     (HW_PDB_IDLY(x).U = (v))
00620 #define HW_PDB_IDLY_SET(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) |  (v)))
00621 #define HW_PDB_IDLY_CLR(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
00622 #define HW_PDB_IDLY_TOG(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^  (v)))
00623 /*@}*/
00624 
00625 /*
00626  * Constants & macros for individual PDB_IDLY bitfields
00627  */
00628 
00629 /*!
00630  * @name Register PDB_IDLY, field IDLY[15:0] (RW)
00631  *
00632  * Specifies the delay value to schedule the PDB interrupt. It can be used to
00633  * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
00634  * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
00635  * this field returns the value of internal register that is effective for the
00636  * current cycle of the PDB.
00637  */
00638 /*@{*/
00639 #define BP_PDB_IDLY_IDLY     (0U)          /*!< Bit position for PDB_IDLY_IDLY. */
00640 #define BM_PDB_IDLY_IDLY     (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */
00641 #define BS_PDB_IDLY_IDLY     (16U)         /*!< Bit field size in bits for PDB_IDLY_IDLY. */
00642 
00643 /*! @brief Read current value of the PDB_IDLY_IDLY field. */
00644 #define BR_PDB_IDLY_IDLY(x)  (HW_PDB_IDLY(x).B.IDLY)
00645 
00646 /*! @brief Format value for bitfield PDB_IDLY_IDLY. */
00647 #define BF_PDB_IDLY_IDLY(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
00648 
00649 /*! @brief Set the IDLY field to a new value. */
00650 #define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
00651 /*@}*/
00652 
00653 /*******************************************************************************
00654  * HW_PDB_CHnC1 - Channel n Control register 1
00655  ******************************************************************************/
00656 
00657 /*!
00658  * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
00659  *
00660  * Reset value: 0x00000000U
00661  *
00662  * Each PDB channel has one control register, CHnC1. The bits in this register
00663  * control the functionality of each PDB channel operation.
00664  */
00665 typedef union _hw_pdb_chnc1
00666 {
00667     uint32_t U;
00668     struct _hw_pdb_chnc1_bitfields
00669     {
00670         uint32_t EN : 8;               /*!< [7:0] PDB Channel Pre-Trigger Enable */
00671         uint32_t TOS : 8;              /*!< [15:8] PDB Channel Pre-Trigger Output Select */
00672         uint32_t BB : 8;               /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
00673                                         * Operation Enable */
00674         uint32_t RESERVED0 : 8;        /*!< [31:24]  */
00675     } B;
00676 } hw_pdb_chnc1_t;
00677 
00678 /*!
00679  * @name Constants and macros for entire PDB_CHnC1 register
00680  */
00681 /*@{*/
00682 #define HW_PDB_CHnC1_COUNT (2U)
00683 
00684 #define HW_PDB_CHnC1_ADDR(x, n)  ((x) + 0x10U + (0x28U * (n)))
00685 
00686 #define HW_PDB_CHnC1(x, n)       (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n))
00687 #define HW_PDB_CHnC1_RD(x, n)    (HW_PDB_CHnC1(x, n).U)
00688 #define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v))
00689 #define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) |  (v)))
00690 #define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
00691 #define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^  (v)))
00692 /*@}*/
00693 
00694 /*
00695  * Constants & macros for individual PDB_CHnC1 bitfields
00696  */
00697 
00698 /*!
00699  * @name Register PDB_CHnC1, field EN[7:0] (RW)
00700  *
00701  * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
00702  * bits are implemented in this MCU.
00703  *
00704  * Values:
00705  * - 0 - PDB channel's corresponding pre-trigger disabled.
00706  * - 1 - PDB channel's corresponding pre-trigger enabled.
00707  */
00708 /*@{*/
00709 #define BP_PDB_CHnC1_EN      (0U)          /*!< Bit position for PDB_CHnC1_EN. */
00710 #define BM_PDB_CHnC1_EN      (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */
00711 #define BS_PDB_CHnC1_EN      (8U)          /*!< Bit field size in bits for PDB_CHnC1_EN. */
00712 
00713 /*! @brief Read current value of the PDB_CHnC1_EN field. */
00714 #define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN)
00715 
00716 /*! @brief Format value for bitfield PDB_CHnC1_EN. */
00717 #define BF_PDB_CHnC1_EN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
00718 
00719 /*! @brief Set the EN field to a new value. */
00720 #define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
00721 /*@}*/
00722 
00723 /*!
00724  * @name Register PDB_CHnC1, field TOS[15:8] (RW)
00725  *
00726  * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
00727  * implemented in this MCU.
00728  *
00729  * Values:
00730  * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
00731  *     pre-trigger asserts one peripheral clock cycle after a rising edge is detected
00732  *     on selected trigger input source or software trigger is selected and SWTRIG
00733  *     is written with 1.
00734  * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
00735  *     reaches the channel delay register and one peripheral clock cycle after a rising
00736  *     edge is detected on selected trigger input source or software trigger is
00737  *     selected and SETRIG is written with 1.
00738  */
00739 /*@{*/
00740 #define BP_PDB_CHnC1_TOS     (8U)          /*!< Bit position for PDB_CHnC1_TOS. */
00741 #define BM_PDB_CHnC1_TOS     (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */
00742 #define BS_PDB_CHnC1_TOS     (8U)          /*!< Bit field size in bits for PDB_CHnC1_TOS. */
00743 
00744 /*! @brief Read current value of the PDB_CHnC1_TOS field. */
00745 #define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS)
00746 
00747 /*! @brief Format value for bitfield PDB_CHnC1_TOS. */
00748 #define BF_PDB_CHnC1_TOS(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
00749 
00750 /*! @brief Set the TOS field to a new value. */
00751 #define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
00752 /*@}*/
00753 
00754 /*!
00755  * @name Register PDB_CHnC1, field BB[23:16] (RW)
00756  *
00757  * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
00758  * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
00759  * enables the ADC conversions complete to trigger the next PDB channel
00760  * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
00761  * set of configuration and results registers. Application code must only enable
00762  * the back-to-back operation of the PDB pre-triggers at the leading of the
00763  * back-to-back connection chain.
00764  *
00765  * Values:
00766  * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
00767  * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
00768  */
00769 /*@{*/
00770 #define BP_PDB_CHnC1_BB      (16U)         /*!< Bit position for PDB_CHnC1_BB. */
00771 #define BM_PDB_CHnC1_BB      (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */
00772 #define BS_PDB_CHnC1_BB      (8U)          /*!< Bit field size in bits for PDB_CHnC1_BB. */
00773 
00774 /*! @brief Read current value of the PDB_CHnC1_BB field. */
00775 #define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB)
00776 
00777 /*! @brief Format value for bitfield PDB_CHnC1_BB. */
00778 #define BF_PDB_CHnC1_BB(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
00779 
00780 /*! @brief Set the BB field to a new value. */
00781 #define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
00782 /*@}*/
00783 /*******************************************************************************
00784  * HW_PDB_CHnS - Channel n Status register
00785  ******************************************************************************/
00786 
00787 /*!
00788  * @brief HW_PDB_CHnS - Channel n Status register (RW)
00789  *
00790  * Reset value: 0x00000000U
00791  */
00792 typedef union _hw_pdb_chns
00793 {
00794     uint32_t U;
00795     struct _hw_pdb_chns_bitfields
00796     {
00797         uint32_t ERR : 8;              /*!< [7:0] PDB Channel Sequence Error Flags */
00798         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
00799         uint32_t CF : 8;               /*!< [23:16] PDB Channel Flags */
00800         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
00801     } B;
00802 } hw_pdb_chns_t;
00803 
00804 /*!
00805  * @name Constants and macros for entire PDB_CHnS register
00806  */
00807 /*@{*/
00808 #define HW_PDB_CHnS_COUNT (2U)
00809 
00810 #define HW_PDB_CHnS_ADDR(x, n)   ((x) + 0x14U + (0x28U * (n)))
00811 
00812 #define HW_PDB_CHnS(x, n)        (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n))
00813 #define HW_PDB_CHnS_RD(x, n)     (HW_PDB_CHnS(x, n).U)
00814 #define HW_PDB_CHnS_WR(x, n, v)  (HW_PDB_CHnS(x, n).U = (v))
00815 #define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) |  (v)))
00816 #define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
00817 #define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^  (v)))
00818 /*@}*/
00819 
00820 /*
00821  * Constants & macros for individual PDB_CHnS bitfields
00822  */
00823 
00824 /*!
00825  * @name Register PDB_CHnS, field ERR[7:0] (RW)
00826  *
00827  * Only the lower M bits are implemented in this MCU.
00828  *
00829  * Values:
00830  * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
00831  * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
00832  *     ADCn block can be triggered for a conversion by one pre-trigger from PDB
00833  *     channel n. When one conversion, which is triggered by one of the pre-triggers
00834  *     from PDB channel n, is in progress, new trigger from PDB channel's
00835  *     corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
00836  *     Writing 0's to clear the sequence error flags.
00837  */
00838 /*@{*/
00839 #define BP_PDB_CHnS_ERR      (0U)          /*!< Bit position for PDB_CHnS_ERR. */
00840 #define BM_PDB_CHnS_ERR      (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */
00841 #define BS_PDB_CHnS_ERR      (8U)          /*!< Bit field size in bits for PDB_CHnS_ERR. */
00842 
00843 /*! @brief Read current value of the PDB_CHnS_ERR field. */
00844 #define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR)
00845 
00846 /*! @brief Format value for bitfield PDB_CHnS_ERR. */
00847 #define BF_PDB_CHnS_ERR(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
00848 
00849 /*! @brief Set the ERR field to a new value. */
00850 #define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
00851 /*@}*/
00852 
00853 /*!
00854  * @name Register PDB_CHnS, field CF[23:16] (RW)
00855  *
00856  * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
00857  * clear these bits.
00858  */
00859 /*@{*/
00860 #define BP_PDB_CHnS_CF       (16U)         /*!< Bit position for PDB_CHnS_CF. */
00861 #define BM_PDB_CHnS_CF       (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */
00862 #define BS_PDB_CHnS_CF       (8U)          /*!< Bit field size in bits for PDB_CHnS_CF. */
00863 
00864 /*! @brief Read current value of the PDB_CHnS_CF field. */
00865 #define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF)
00866 
00867 /*! @brief Format value for bitfield PDB_CHnS_CF. */
00868 #define BF_PDB_CHnS_CF(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
00869 
00870 /*! @brief Set the CF field to a new value. */
00871 #define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
00872 /*@}*/
00873 /*******************************************************************************
00874  * HW_PDB_CHnDLY0 - Channel n Delay 0 register
00875  ******************************************************************************/
00876 
00877 /*!
00878  * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
00879  *
00880  * Reset value: 0x00000000U
00881  */
00882 typedef union _hw_pdb_chndly0
00883 {
00884     uint32_t U;
00885     struct _hw_pdb_chndly0_bitfields
00886     {
00887         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
00888         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00889     } B;
00890 } hw_pdb_chndly0_t;
00891 
00892 /*!
00893  * @name Constants and macros for entire PDB_CHnDLY0 register
00894  */
00895 /*@{*/
00896 #define HW_PDB_CHnDLY0_COUNT (2U)
00897 
00898 #define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
00899 
00900 #define HW_PDB_CHnDLY0(x, n)     (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n))
00901 #define HW_PDB_CHnDLY0_RD(x, n)  (HW_PDB_CHnDLY0(x, n).U)
00902 #define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v))
00903 #define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) |  (v)))
00904 #define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
00905 #define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^  (v)))
00906 /*@}*/
00907 
00908 /*
00909  * Constants & macros for individual PDB_CHnDLY0 bitfields
00910  */
00911 
00912 /*!
00913  * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
00914  *
00915  * Specifies the delay value for the channel's corresponding pre-trigger. The
00916  * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
00917  * the value of internal register that is effective for the current PDB cycle.
00918  */
00919 /*@{*/
00920 #define BP_PDB_CHnDLY0_DLY   (0U)          /*!< Bit position for PDB_CHnDLY0_DLY. */
00921 #define BM_PDB_CHnDLY0_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */
00922 #define BS_PDB_CHnDLY0_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */
00923 
00924 /*! @brief Read current value of the PDB_CHnDLY0_DLY field. */
00925 #define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY)
00926 
00927 /*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */
00928 #define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
00929 
00930 /*! @brief Set the DLY field to a new value. */
00931 #define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
00932 /*@}*/
00933 /*******************************************************************************
00934  * HW_PDB_CHnDLY1 - Channel n Delay 1 register
00935  ******************************************************************************/
00936 
00937 /*!
00938  * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
00939  *
00940  * Reset value: 0x00000000U
00941  */
00942 typedef union _hw_pdb_chndly1
00943 {
00944     uint32_t U;
00945     struct _hw_pdb_chndly1_bitfields
00946     {
00947         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
00948         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00949     } B;
00950 } hw_pdb_chndly1_t;
00951 
00952 /*!
00953  * @name Constants and macros for entire PDB_CHnDLY1 register
00954  */
00955 /*@{*/
00956 #define HW_PDB_CHnDLY1_COUNT (2U)
00957 
00958 #define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
00959 
00960 #define HW_PDB_CHnDLY1(x, n)     (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n))
00961 #define HW_PDB_CHnDLY1_RD(x, n)  (HW_PDB_CHnDLY1(x, n).U)
00962 #define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v))
00963 #define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) |  (v)))
00964 #define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
00965 #define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^  (v)))
00966 /*@}*/
00967 
00968 /*
00969  * Constants & macros for individual PDB_CHnDLY1 bitfields
00970  */
00971 
00972 /*!
00973  * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
00974  *
00975  * These bits specify the delay value for the channel's corresponding
00976  * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
00977  * bits returns the value of internal register that is effective for the current PDB
00978  * cycle.
00979  */
00980 /*@{*/
00981 #define BP_PDB_CHnDLY1_DLY   (0U)          /*!< Bit position for PDB_CHnDLY1_DLY. */
00982 #define BM_PDB_CHnDLY1_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */
00983 #define BS_PDB_CHnDLY1_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */
00984 
00985 /*! @brief Read current value of the PDB_CHnDLY1_DLY field. */
00986 #define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY)
00987 
00988 /*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */
00989 #define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
00990 
00991 /*! @brief Set the DLY field to a new value. */
00992 #define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
00993 /*@}*/
00994 
00995 /*******************************************************************************
00996  * HW_PDB_DACINTCn - DAC Interval Trigger n Control register
00997  ******************************************************************************/
00998 
00999 /*!
01000  * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
01001  *
01002  * Reset value: 0x00000000U
01003  */
01004 typedef union _hw_pdb_dacintcn
01005 {
01006     uint32_t U;
01007     struct _hw_pdb_dacintcn_bitfields
01008     {
01009         uint32_t TOE : 1;              /*!< [0] DAC Interval Trigger Enable */
01010         uint32_t EXT : 1;              /*!< [1] DAC External Trigger Input Enable */
01011         uint32_t RESERVED0 : 30;       /*!< [31:2]  */
01012     } B;
01013 } hw_pdb_dacintcn_t;
01014 
01015 /*!
01016  * @name Constants and macros for entire PDB_DACINTCn register
01017  */
01018 /*@{*/
01019 #define HW_PDB_DACINTCn_COUNT (2U)
01020 
01021 #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
01022 
01023 #define HW_PDB_DACINTCn(x, n)    (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n))
01024 #define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U)
01025 #define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v))
01026 #define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) |  (v)))
01027 #define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
01028 #define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^  (v)))
01029 /*@}*/
01030 
01031 /*
01032  * Constants & macros for individual PDB_DACINTCn bitfields
01033  */
01034 
01035 /*!
01036  * @name Register PDB_DACINTCn, field TOE[0] (RW)
01037  *
01038  * This bit enables the DAC interval trigger.
01039  *
01040  * Values:
01041  * - 0 - DAC interval trigger disabled.
01042  * - 1 - DAC interval trigger enabled.
01043  */
01044 /*@{*/
01045 #define BP_PDB_DACINTCn_TOE  (0U)          /*!< Bit position for PDB_DACINTCn_TOE. */
01046 #define BM_PDB_DACINTCn_TOE  (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */
01047 #define BS_PDB_DACINTCn_TOE  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_TOE. */
01048 
01049 /*! @brief Read current value of the PDB_DACINTCn_TOE field. */
01050 #define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE))
01051 
01052 /*! @brief Format value for bitfield PDB_DACINTCn_TOE. */
01053 #define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
01054 
01055 /*! @brief Set the TOE field to a new value. */
01056 #define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v))
01057 /*@}*/
01058 
01059 /*!
01060  * @name Register PDB_DACINTCn, field EXT[1] (RW)
01061  *
01062  * Enables the external trigger for DAC interval counter.
01063  *
01064  * Values:
01065  * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
01066  *     counting starts when a rising edge is detected on selected trigger input
01067  *     source or software trigger is selected and SWTRIG is written with 1.
01068  * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
01069  *     and DAC external trigger input triggers the DAC interval trigger.
01070  */
01071 /*@{*/
01072 #define BP_PDB_DACINTCn_EXT  (1U)          /*!< Bit position for PDB_DACINTCn_EXT. */
01073 #define BM_PDB_DACINTCn_EXT  (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */
01074 #define BS_PDB_DACINTCn_EXT  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_EXT. */
01075 
01076 /*! @brief Read current value of the PDB_DACINTCn_EXT field. */
01077 #define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT))
01078 
01079 /*! @brief Format value for bitfield PDB_DACINTCn_EXT. */
01080 #define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
01081 
01082 /*! @brief Set the EXT field to a new value. */
01083 #define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v))
01084 /*@}*/
01085 /*******************************************************************************
01086  * HW_PDB_DACINTn - DAC Interval n register
01087  ******************************************************************************/
01088 
01089 /*!
01090  * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
01091  *
01092  * Reset value: 0x00000000U
01093  */
01094 typedef union _hw_pdb_dacintn
01095 {
01096     uint32_t U;
01097     struct _hw_pdb_dacintn_bitfields
01098     {
01099         uint32_t INT : 16;             /*!< [15:0] DAC Interval */
01100         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01101     } B;
01102 } hw_pdb_dacintn_t;
01103 
01104 /*!
01105  * @name Constants and macros for entire PDB_DACINTn register
01106  */
01107 /*@{*/
01108 #define HW_PDB_DACINTn_COUNT (2U)
01109 
01110 #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
01111 
01112 #define HW_PDB_DACINTn(x, n)     (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n))
01113 #define HW_PDB_DACINTn_RD(x, n)  (HW_PDB_DACINTn(x, n).U)
01114 #define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v))
01115 #define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) |  (v)))
01116 #define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
01117 #define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^  (v)))
01118 /*@}*/
01119 
01120 /*
01121  * Constants & macros for individual PDB_DACINTn bitfields
01122  */
01123 
01124 /*!
01125  * @name Register PDB_DACINTn, field INT[15:0] (RW)
01126  *
01127  * Specifies the interval value for DAC interval trigger. DAC interval trigger
01128  * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
01129  * Reading this field returns the value of internal register that is effective
01130  * for the current PDB cycle.
01131  */
01132 /*@{*/
01133 #define BP_PDB_DACINTn_INT   (0U)          /*!< Bit position for PDB_DACINTn_INT. */
01134 #define BM_PDB_DACINTn_INT   (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */
01135 #define BS_PDB_DACINTn_INT   (16U)         /*!< Bit field size in bits for PDB_DACINTn_INT. */
01136 
01137 /*! @brief Read current value of the PDB_DACINTn_INT field. */
01138 #define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT)
01139 
01140 /*! @brief Format value for bitfield PDB_DACINTn_INT. */
01141 #define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
01142 
01143 /*! @brief Set the INT field to a new value. */
01144 #define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
01145 /*@}*/
01146 
01147 /*******************************************************************************
01148  * HW_PDB_POEN - Pulse-Out n Enable register
01149  ******************************************************************************/
01150 
01151 /*!
01152  * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
01153  *
01154  * Reset value: 0x00000000U
01155  */
01156 typedef union _hw_pdb_poen
01157 {
01158     uint32_t U;
01159     struct _hw_pdb_poen_bitfields
01160     {
01161         uint32_t POEN : 8;             /*!< [7:0] PDB Pulse-Out Enable */
01162         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01163     } B;
01164 } hw_pdb_poen_t;
01165 
01166 /*!
01167  * @name Constants and macros for entire PDB_POEN register
01168  */
01169 /*@{*/
01170 #define HW_PDB_POEN_ADDR(x)      ((x) + 0x190U)
01171 
01172 #define HW_PDB_POEN(x)           (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x))
01173 #define HW_PDB_POEN_RD(x)        (HW_PDB_POEN(x).U)
01174 #define HW_PDB_POEN_WR(x, v)     (HW_PDB_POEN(x).U = (v))
01175 #define HW_PDB_POEN_SET(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) |  (v)))
01176 #define HW_PDB_POEN_CLR(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
01177 #define HW_PDB_POEN_TOG(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^  (v)))
01178 /*@}*/
01179 
01180 /*
01181  * Constants & macros for individual PDB_POEN bitfields
01182  */
01183 
01184 /*!
01185  * @name Register PDB_POEN, field POEN[7:0] (RW)
01186  *
01187  * Enables the pulse output. Only lower Y bits are implemented in this MCU.
01188  *
01189  * Values:
01190  * - 0 - PDB Pulse-Out disabled
01191  * - 1 - PDB Pulse-Out enabled
01192  */
01193 /*@{*/
01194 #define BP_PDB_POEN_POEN     (0U)          /*!< Bit position for PDB_POEN_POEN. */
01195 #define BM_PDB_POEN_POEN     (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */
01196 #define BS_PDB_POEN_POEN     (8U)          /*!< Bit field size in bits for PDB_POEN_POEN. */
01197 
01198 /*! @brief Read current value of the PDB_POEN_POEN field. */
01199 #define BR_PDB_POEN_POEN(x)  (HW_PDB_POEN(x).B.POEN)
01200 
01201 /*! @brief Format value for bitfield PDB_POEN_POEN. */
01202 #define BF_PDB_POEN_POEN(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
01203 
01204 /*! @brief Set the POEN field to a new value. */
01205 #define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
01206 /*@}*/
01207 
01208 /*******************************************************************************
01209  * HW_PDB_POnDLY - Pulse-Out n Delay register
01210  ******************************************************************************/
01211 
01212 /*!
01213  * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
01214  *
01215  * Reset value: 0x00000000U
01216  */
01217 typedef union _hw_pdb_pondly
01218 {
01219     uint32_t U;
01220     struct _hw_pdb_pondly_bitfields
01221     {
01222         uint32_t DLY2 : 16;            /*!< [15:0] PDB Pulse-Out Delay 2 */
01223         uint32_t DLY1 : 16;            /*!< [31:16] PDB Pulse-Out Delay 1 */
01224     } B;
01225 } hw_pdb_pondly_t;
01226 
01227 /*!
01228  * @name Constants and macros for entire PDB_POnDLY register
01229  */
01230 /*@{*/
01231 #define HW_PDB_POnDLY_COUNT (3U)
01232 
01233 #define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
01234 
01235 #define HW_PDB_POnDLY(x, n)      (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n))
01236 #define HW_PDB_POnDLY_RD(x, n)   (HW_PDB_POnDLY(x, n).U)
01237 #define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v))
01238 #define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) |  (v)))
01239 #define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
01240 #define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^  (v)))
01241 /*@}*/
01242 
01243 /*
01244  * Constants & macros for individual PDB_POnDLY bitfields
01245  */
01246 
01247 /*!
01248  * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
01249  *
01250  * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
01251  * low when the PDB counter is equal to the DLY2. Reading these bits returns the
01252  * value of internal register that is effective for the current PDB cycle.
01253  */
01254 /*@{*/
01255 #define BP_PDB_POnDLY_DLY2   (0U)          /*!< Bit position for PDB_POnDLY_DLY2. */
01256 #define BM_PDB_POnDLY_DLY2   (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */
01257 #define BS_PDB_POnDLY_DLY2   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY2. */
01258 
01259 /*! @brief Read current value of the PDB_POnDLY_DLY2 field. */
01260 #define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2)
01261 
01262 /*! @brief Format value for bitfield PDB_POnDLY_DLY2. */
01263 #define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
01264 
01265 /*! @brief Set the DLY2 field to a new value. */
01266 #define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
01267 /*@}*/
01268 
01269 /*!
01270  * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
01271  *
01272  * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
01273  * high when the PDB counter is equal to the DLY1. Reading these bits returns the
01274  * value of internal register that is effective for the current PDB cycle.
01275  */
01276 /*@{*/
01277 #define BP_PDB_POnDLY_DLY1   (16U)         /*!< Bit position for PDB_POnDLY_DLY1. */
01278 #define BM_PDB_POnDLY_DLY1   (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */
01279 #define BS_PDB_POnDLY_DLY1   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY1. */
01280 
01281 /*! @brief Read current value of the PDB_POnDLY_DLY1 field. */
01282 #define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1)
01283 
01284 /*! @brief Format value for bitfield PDB_POnDLY_DLY1. */
01285 #define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
01286 
01287 /*! @brief Set the DLY1 field to a new value. */
01288 #define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
01289 /*@}*/
01290 
01291 /*******************************************************************************
01292  * hw_pdb_t - module struct
01293  ******************************************************************************/
01294 /*!
01295  * @brief All PDB module registers.
01296  */
01297 #pragma pack(1)
01298 typedef struct _hw_pdb
01299 {
01300     __IO hw_pdb_sc_t SC ;                   /*!< [0x0] Status and Control register */
01301     __IO hw_pdb_mod_t MOD ;                 /*!< [0x4] Modulus register */
01302     __I hw_pdb_cnt_t CNT ;                  /*!< [0x8] Counter register */
01303     __IO hw_pdb_idly_t IDLY ;               /*!< [0xC] Interrupt Delay register */
01304     struct {
01305         __IO hw_pdb_chnc1_t CHnC1 ;         /*!< [0x10] Channel n Control register 1 */
01306         __IO hw_pdb_chns_t CHnS ;           /*!< [0x14] Channel n Status register */
01307         __IO hw_pdb_chndly0_t CHnDLY0 ;     /*!< [0x18] Channel n Delay 0 register */
01308         __IO hw_pdb_chndly1_t CHnDLY1 ;     /*!< [0x1C] Channel n Delay 1 register */
01309         uint8_t _reserved0[24];
01310     } CH[2];
01311     uint8_t _reserved0[240];
01312     struct {
01313         __IO hw_pdb_dacintcn_t DACINTCn ;   /*!< [0x150] DAC Interval Trigger n Control register */
01314         __IO hw_pdb_dacintn_t DACINTn ;     /*!< [0x154] DAC Interval n register */
01315     } DAC[2];
01316     uint8_t _reserved1[48];
01317     __IO hw_pdb_poen_t POEN ;               /*!< [0x190] Pulse-Out n Enable register */
01318     __IO hw_pdb_pondly_t POnDLY [3];        /*!< [0x194] Pulse-Out n Delay register */
01319 } hw_pdb_t;
01320 #pragma pack()
01321 
01322 /*! @brief Macro to access all PDB registers. */
01323 /*! @param x PDB module instance base address. */
01324 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01325  *     use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
01326 #define HW_PDB(x)      (*(hw_pdb_t *)(x))
01327 
01328 #endif /* __HW_PDB_REGISTERS_H__ */
01329 /* EOF */