MK64F12_osc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_OSC_REGISTERS_H__
00081 #define __HW_OSC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 OSC
00088  *
00089  * Oscillator
00090  *
00091  * Registers defined in this header file:
00092  * - HW_OSC_CR - OSC Control Register
00093  *
00094  * - hw_osc_t - Struct containing all module registers.
00095  */
00096 
00097 #define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
00098 
00099 /*******************************************************************************
00100  * HW_OSC_CR - OSC Control Register
00101  ******************************************************************************/
00102 
00103 /*!
00104  * @brief HW_OSC_CR - OSC Control Register (RW)
00105  *
00106  * Reset value: 0x00U
00107  *
00108  * After OSC is enabled and starts generating the clocks, the configurations
00109  * such as low power and frequency range, must not be changed.
00110  */
00111 typedef union _hw_osc_cr
00112 {
00113     uint8_t U;
00114     struct _hw_osc_cr_bitfields
00115     {
00116         uint8_t SC16P : 1;             /*!< [0] Oscillator 16 pF Capacitor Load Configure
00117                                         * */
00118         uint8_t SC8P : 1;              /*!< [1] Oscillator 8 pF Capacitor Load Configure */
00119         uint8_t SC4P : 1;              /*!< [2] Oscillator 4 pF Capacitor Load Configure */
00120         uint8_t SC2P : 1;              /*!< [3] Oscillator 2 pF Capacitor Load Configure */
00121         uint8_t RESERVED0 : 1;         /*!< [4]  */
00122         uint8_t EREFSTEN : 1;          /*!< [5] External Reference Stop Enable */
00123         uint8_t RESERVED1 : 1;         /*!< [6]  */
00124         uint8_t ERCLKEN : 1;           /*!< [7] External Reference Enable */
00125     } B;
00126 } hw_osc_cr_t;
00127 
00128 /*!
00129  * @name Constants and macros for entire OSC_CR register
00130  */
00131 /*@{*/
00132 #define HW_OSC_CR_ADDR(x)        ((x) + 0x0U)
00133 
00134 #define HW_OSC_CR(x)             (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
00135 #define HW_OSC_CR_RD(x)          (HW_OSC_CR(x).U)
00136 #define HW_OSC_CR_WR(x, v)       (HW_OSC_CR(x).U = (v))
00137 #define HW_OSC_CR_SET(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) |  (v)))
00138 #define HW_OSC_CR_CLR(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
00139 #define HW_OSC_CR_TOG(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^  (v)))
00140 /*@}*/
00141 
00142 /*
00143  * Constants & macros for individual OSC_CR bitfields
00144  */
00145 
00146 /*!
00147  * @name Register OSC_CR, field SC16P[0] (RW)
00148  *
00149  * Configures the oscillator load.
00150  *
00151  * Values:
00152  * - 0 - Disable the selection.
00153  * - 1 - Add 16 pF capacitor to the oscillator load.
00154  */
00155 /*@{*/
00156 #define BP_OSC_CR_SC16P      (0U)          /*!< Bit position for OSC_CR_SC16P. */
00157 #define BM_OSC_CR_SC16P      (0x01U)       /*!< Bit mask for OSC_CR_SC16P. */
00158 #define BS_OSC_CR_SC16P      (1U)          /*!< Bit field size in bits for OSC_CR_SC16P. */
00159 
00160 /*! @brief Read current value of the OSC_CR_SC16P field. */
00161 #define BR_OSC_CR_SC16P(x)   (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
00162 
00163 /*! @brief Format value for bitfield OSC_CR_SC16P. */
00164 #define BF_OSC_CR_SC16P(v)   ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P)
00165 
00166 /*! @brief Set the SC16P field to a new value. */
00167 #define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
00168 /*@}*/
00169 
00170 /*!
00171  * @name Register OSC_CR, field SC8P[1] (RW)
00172  *
00173  * Configures the oscillator load.
00174  *
00175  * Values:
00176  * - 0 - Disable the selection.
00177  * - 1 - Add 8 pF capacitor to the oscillator load.
00178  */
00179 /*@{*/
00180 #define BP_OSC_CR_SC8P       (1U)          /*!< Bit position for OSC_CR_SC8P. */
00181 #define BM_OSC_CR_SC8P       (0x02U)       /*!< Bit mask for OSC_CR_SC8P. */
00182 #define BS_OSC_CR_SC8P       (1U)          /*!< Bit field size in bits for OSC_CR_SC8P. */
00183 
00184 /*! @brief Read current value of the OSC_CR_SC8P field. */
00185 #define BR_OSC_CR_SC8P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
00186 
00187 /*! @brief Format value for bitfield OSC_CR_SC8P. */
00188 #define BF_OSC_CR_SC8P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P)
00189 
00190 /*! @brief Set the SC8P field to a new value. */
00191 #define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
00192 /*@}*/
00193 
00194 /*!
00195  * @name Register OSC_CR, field SC4P[2] (RW)
00196  *
00197  * Configures the oscillator load.
00198  *
00199  * Values:
00200  * - 0 - Disable the selection.
00201  * - 1 - Add 4 pF capacitor to the oscillator load.
00202  */
00203 /*@{*/
00204 #define BP_OSC_CR_SC4P       (2U)          /*!< Bit position for OSC_CR_SC4P. */
00205 #define BM_OSC_CR_SC4P       (0x04U)       /*!< Bit mask for OSC_CR_SC4P. */
00206 #define BS_OSC_CR_SC4P       (1U)          /*!< Bit field size in bits for OSC_CR_SC4P. */
00207 
00208 /*! @brief Read current value of the OSC_CR_SC4P field. */
00209 #define BR_OSC_CR_SC4P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
00210 
00211 /*! @brief Format value for bitfield OSC_CR_SC4P. */
00212 #define BF_OSC_CR_SC4P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P)
00213 
00214 /*! @brief Set the SC4P field to a new value. */
00215 #define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
00216 /*@}*/
00217 
00218 /*!
00219  * @name Register OSC_CR, field SC2P[3] (RW)
00220  *
00221  * Configures the oscillator load.
00222  *
00223  * Values:
00224  * - 0 - Disable the selection.
00225  * - 1 - Add 2 pF capacitor to the oscillator load.
00226  */
00227 /*@{*/
00228 #define BP_OSC_CR_SC2P       (3U)          /*!< Bit position for OSC_CR_SC2P. */
00229 #define BM_OSC_CR_SC2P       (0x08U)       /*!< Bit mask for OSC_CR_SC2P. */
00230 #define BS_OSC_CR_SC2P       (1U)          /*!< Bit field size in bits for OSC_CR_SC2P. */
00231 
00232 /*! @brief Read current value of the OSC_CR_SC2P field. */
00233 #define BR_OSC_CR_SC2P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
00234 
00235 /*! @brief Format value for bitfield OSC_CR_SC2P. */
00236 #define BF_OSC_CR_SC2P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P)
00237 
00238 /*! @brief Set the SC2P field to a new value. */
00239 #define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
00240 /*@}*/
00241 
00242 /*!
00243  * @name Register OSC_CR, field EREFSTEN[5] (RW)
00244  *
00245  * Controls whether or not the external reference clock (OSCERCLK) remains
00246  * enabled when MCU enters Stop mode.
00247  *
00248  * Values:
00249  * - 0 - External reference clock is disabled in Stop mode.
00250  * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
00251  *     before entering Stop mode.
00252  */
00253 /*@{*/
00254 #define BP_OSC_CR_EREFSTEN   (5U)          /*!< Bit position for OSC_CR_EREFSTEN. */
00255 #define BM_OSC_CR_EREFSTEN   (0x20U)       /*!< Bit mask for OSC_CR_EREFSTEN. */
00256 #define BS_OSC_CR_EREFSTEN   (1U)          /*!< Bit field size in bits for OSC_CR_EREFSTEN. */
00257 
00258 /*! @brief Read current value of the OSC_CR_EREFSTEN field. */
00259 #define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
00260 
00261 /*! @brief Format value for bitfield OSC_CR_EREFSTEN. */
00262 #define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN)
00263 
00264 /*! @brief Set the EREFSTEN field to a new value. */
00265 #define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
00266 /*@}*/
00267 
00268 /*!
00269  * @name Register OSC_CR, field ERCLKEN[7] (RW)
00270  *
00271  * Enables external reference clock (OSCERCLK).
00272  *
00273  * Values:
00274  * - 0 - External reference clock is inactive.
00275  * - 1 - External reference clock is enabled.
00276  */
00277 /*@{*/
00278 #define BP_OSC_CR_ERCLKEN    (7U)          /*!< Bit position for OSC_CR_ERCLKEN. */
00279 #define BM_OSC_CR_ERCLKEN    (0x80U)       /*!< Bit mask for OSC_CR_ERCLKEN. */
00280 #define BS_OSC_CR_ERCLKEN    (1U)          /*!< Bit field size in bits for OSC_CR_ERCLKEN. */
00281 
00282 /*! @brief Read current value of the OSC_CR_ERCLKEN field. */
00283 #define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
00284 
00285 /*! @brief Format value for bitfield OSC_CR_ERCLKEN. */
00286 #define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN)
00287 
00288 /*! @brief Set the ERCLKEN field to a new value. */
00289 #define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
00290 /*@}*/
00291 
00292 /*******************************************************************************
00293  * hw_osc_t - module struct
00294  ******************************************************************************/
00295 /*!
00296  * @brief All OSC module registers.
00297  */
00298 #pragma pack(1)
00299 typedef struct _hw_osc
00300 {
00301     __IO hw_osc_cr_t CR ;                   /*!< [0x0] OSC Control Register */
00302 } hw_osc_t;
00303 #pragma pack()
00304 
00305 /*! @brief Macro to access all OSC registers. */
00306 /*! @param x OSC module instance base address. */
00307 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00308  *     use the '&' operator, like <code>&HW_OSC(OSC_BASE)</code>. */
00309 #define HW_OSC(x)      (*(hw_osc_t *)(x))
00310 
00311 #endif /* __HW_OSC_REGISTERS_H__ */
00312 /* EOF */