MK64F12_mcm.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_MCM_REGISTERS_H__
00081 #define __HW_MCM_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 MCM
00088  *
00089  * Core Platform Miscellaneous Control Module
00090  *
00091  * Registers defined in this header file:
00092  * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
00093  * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
00094  * - HW_MCM_CR - Control Register
00095  * - HW_MCM_ISCR - Interrupt Status Register
00096  * - HW_MCM_ETBCC - ETB Counter Control register
00097  * - HW_MCM_ETBRL - ETB Reload register
00098  * - HW_MCM_ETBCNT - ETB Counter Value register
00099  * - HW_MCM_PID - Process ID register
00100  *
00101  * - hw_mcm_t - Struct containing all module registers.
00102  */
00103 
00104 #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
00105 
00106 /*******************************************************************************
00107  * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
00112  *
00113  * Reset value: 0x001FU
00114  *
00115  * PLASC is a 16-bit read-only register identifying the presence/absence of bus
00116  * slave connections to the device's crossbar switch.
00117  */
00118 typedef union _hw_mcm_plasc
00119 {
00120     uint16_t U;
00121     struct _hw_mcm_plasc_bitfields
00122     {
00123         uint16_t ASC : 8;              /*!< [7:0] Each bit in the ASC field indicates
00124                                         * whether there is a corresponding connection to the crossbar switch's slave
00125                                         * input port. */
00126         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
00127     } B;
00128 } hw_mcm_plasc_t;
00129 
00130 /*!
00131  * @name Constants and macros for entire MCM_PLASC register
00132  */
00133 /*@{*/
00134 #define HW_MCM_PLASC_ADDR(x)     ((x) + 0x8U)
00135 
00136 #define HW_MCM_PLASC(x)          (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
00137 #define HW_MCM_PLASC_RD(x)       (HW_MCM_PLASC(x).U)
00138 /*@}*/
00139 
00140 /*
00141  * Constants & macros for individual MCM_PLASC bitfields
00142  */
00143 
00144 /*!
00145  * @name Register MCM_PLASC, field ASC[7:0] (RO)
00146  *
00147  * Values:
00148  * - 0 - A bus slave connection to AXBS input port n is absent
00149  * - 1 - A bus slave connection to AXBS input port n is present
00150  */
00151 /*@{*/
00152 #define BP_MCM_PLASC_ASC     (0U)          /*!< Bit position for MCM_PLASC_ASC. */
00153 #define BM_MCM_PLASC_ASC     (0x00FFU)     /*!< Bit mask for MCM_PLASC_ASC. */
00154 #define BS_MCM_PLASC_ASC     (8U)          /*!< Bit field size in bits for MCM_PLASC_ASC. */
00155 
00156 /*! @brief Read current value of the MCM_PLASC_ASC field. */
00157 #define BR_MCM_PLASC_ASC(x)  (HW_MCM_PLASC(x).B.ASC)
00158 /*@}*/
00159 
00160 /*******************************************************************************
00161  * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
00162  ******************************************************************************/
00163 
00164 /*!
00165  * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
00166  *
00167  * Reset value: 0x0037U
00168  *
00169  * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
00170  * master connections to the device's crossbar switch.
00171  */
00172 typedef union _hw_mcm_plamc
00173 {
00174     uint16_t U;
00175     struct _hw_mcm_plamc_bitfields
00176     {
00177         uint16_t AMC : 8;              /*!< [7:0] Each bit in the AMC field indicates
00178                                         * whether there is a corresponding connection to the AXBS master input port. */
00179         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
00180     } B;
00181 } hw_mcm_plamc_t;
00182 
00183 /*!
00184  * @name Constants and macros for entire MCM_PLAMC register
00185  */
00186 /*@{*/
00187 #define HW_MCM_PLAMC_ADDR(x)     ((x) + 0xAU)
00188 
00189 #define HW_MCM_PLAMC(x)          (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
00190 #define HW_MCM_PLAMC_RD(x)       (HW_MCM_PLAMC(x).U)
00191 /*@}*/
00192 
00193 /*
00194  * Constants & macros for individual MCM_PLAMC bitfields
00195  */
00196 
00197 /*!
00198  * @name Register MCM_PLAMC, field AMC[7:0] (RO)
00199  *
00200  * Values:
00201  * - 0 - A bus master connection to AXBS input port n is absent
00202  * - 1 - A bus master connection to AXBS input port n is present
00203  */
00204 /*@{*/
00205 #define BP_MCM_PLAMC_AMC     (0U)          /*!< Bit position for MCM_PLAMC_AMC. */
00206 #define BM_MCM_PLAMC_AMC     (0x00FFU)     /*!< Bit mask for MCM_PLAMC_AMC. */
00207 #define BS_MCM_PLAMC_AMC     (8U)          /*!< Bit field size in bits for MCM_PLAMC_AMC. */
00208 
00209 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
00210 #define BR_MCM_PLAMC_AMC(x)  (HW_MCM_PLAMC(x).B.AMC)
00211 /*@}*/
00212 
00213 /*******************************************************************************
00214  * HW_MCM_CR - Control Register
00215  ******************************************************************************/
00216 
00217 /*!
00218  * @brief HW_MCM_CR - Control Register (RW)
00219  *
00220  * Reset value: 0x00000000U
00221  *
00222  * CR defines the arbitration and protection schemes for the two system RAM
00223  * arrays.
00224  */
00225 typedef union _hw_mcm_cr
00226 {
00227     uint32_t U;
00228     struct _hw_mcm_cr_bitfields
00229     {
00230         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
00231         uint32_t SRAMUAP : 2;          /*!< [25:24] SRAM_U arbitration priority */
00232         uint32_t SRAMUWP : 1;          /*!< [26] SRAM_U write protect */
00233         uint32_t RESERVED1 : 1;        /*!< [27]  */
00234         uint32_t SRAMLAP : 2;          /*!< [29:28] SRAM_L arbitration priority */
00235         uint32_t SRAMLWP : 1;          /*!< [30] SRAM_L Write Protect */
00236         uint32_t RESERVED2 : 1;        /*!< [31]  */
00237     } B;
00238 } hw_mcm_cr_t;
00239 
00240 /*!
00241  * @name Constants and macros for entire MCM_CR register
00242  */
00243 /*@{*/
00244 #define HW_MCM_CR_ADDR(x)        ((x) + 0xCU)
00245 
00246 #define HW_MCM_CR(x)             (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR(x))
00247 #define HW_MCM_CR_RD(x)          (HW_MCM_CR(x).U)
00248 #define HW_MCM_CR_WR(x, v)       (HW_MCM_CR(x).U = (v))
00249 #define HW_MCM_CR_SET(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) |  (v)))
00250 #define HW_MCM_CR_CLR(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) & ~(v)))
00251 #define HW_MCM_CR_TOG(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) ^  (v)))
00252 /*@}*/
00253 
00254 /*
00255  * Constants & macros for individual MCM_CR bitfields
00256  */
00257 
00258 /*!
00259  * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
00260  *
00261  * Defines the arbitration scheme and priority for the processor and SRAM
00262  * backdoor accesses to the SRAM_U array.
00263  *
00264  * Values:
00265  * - 00 - Round robin
00266  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
00267  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
00268  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
00269  */
00270 /*@{*/
00271 #define BP_MCM_CR_SRAMUAP    (24U)         /*!< Bit position for MCM_CR_SRAMUAP. */
00272 #define BM_MCM_CR_SRAMUAP    (0x03000000U) /*!< Bit mask for MCM_CR_SRAMUAP. */
00273 #define BS_MCM_CR_SRAMUAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMUAP. */
00274 
00275 /*! @brief Read current value of the MCM_CR_SRAMUAP field. */
00276 #define BR_MCM_CR_SRAMUAP(x) (HW_MCM_CR(x).B.SRAMUAP)
00277 
00278 /*! @brief Format value for bitfield MCM_CR_SRAMUAP. */
00279 #define BF_MCM_CR_SRAMUAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUAP) & BM_MCM_CR_SRAMUAP)
00280 
00281 /*! @brief Set the SRAMUAP field to a new value. */
00282 #define BW_MCM_CR_SRAMUAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
00283 /*@}*/
00284 
00285 /*!
00286  * @name Register MCM_CR, field SRAMUWP[26] (RW)
00287  *
00288  * When this bit is set, writes to SRAM_U array generates a bus error.
00289  */
00290 /*@{*/
00291 #define BP_MCM_CR_SRAMUWP    (26U)         /*!< Bit position for MCM_CR_SRAMUWP. */
00292 #define BM_MCM_CR_SRAMUWP    (0x04000000U) /*!< Bit mask for MCM_CR_SRAMUWP. */
00293 #define BS_MCM_CR_SRAMUWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMUWP. */
00294 
00295 /*! @brief Read current value of the MCM_CR_SRAMUWP field. */
00296 #define BR_MCM_CR_SRAMUWP(x) (HW_MCM_CR(x).B.SRAMUWP)
00297 
00298 /*! @brief Format value for bitfield MCM_CR_SRAMUWP. */
00299 #define BF_MCM_CR_SRAMUWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUWP) & BM_MCM_CR_SRAMUWP)
00300 
00301 /*! @brief Set the SRAMUWP field to a new value. */
00302 #define BW_MCM_CR_SRAMUWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUWP) | BF_MCM_CR_SRAMUWP(v)))
00303 /*@}*/
00304 
00305 /*!
00306  * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
00307  *
00308  * Defines the arbitration scheme and priority for the processor and SRAM
00309  * backdoor accesses to the SRAM_L array.
00310  *
00311  * Values:
00312  * - 00 - Round robin
00313  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
00314  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
00315  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
00316  */
00317 /*@{*/
00318 #define BP_MCM_CR_SRAMLAP    (28U)         /*!< Bit position for MCM_CR_SRAMLAP. */
00319 #define BM_MCM_CR_SRAMLAP    (0x30000000U) /*!< Bit mask for MCM_CR_SRAMLAP. */
00320 #define BS_MCM_CR_SRAMLAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMLAP. */
00321 
00322 /*! @brief Read current value of the MCM_CR_SRAMLAP field. */
00323 #define BR_MCM_CR_SRAMLAP(x) (HW_MCM_CR(x).B.SRAMLAP)
00324 
00325 /*! @brief Format value for bitfield MCM_CR_SRAMLAP. */
00326 #define BF_MCM_CR_SRAMLAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLAP) & BM_MCM_CR_SRAMLAP)
00327 
00328 /*! @brief Set the SRAMLAP field to a new value. */
00329 #define BW_MCM_CR_SRAMLAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
00330 /*@}*/
00331 
00332 /*!
00333  * @name Register MCM_CR, field SRAMLWP[30] (RW)
00334  *
00335  * When this bit is set, writes to SRAM_L array generates a bus error.
00336  */
00337 /*@{*/
00338 #define BP_MCM_CR_SRAMLWP    (30U)         /*!< Bit position for MCM_CR_SRAMLWP. */
00339 #define BM_MCM_CR_SRAMLWP    (0x40000000U) /*!< Bit mask for MCM_CR_SRAMLWP. */
00340 #define BS_MCM_CR_SRAMLWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMLWP. */
00341 
00342 /*! @brief Read current value of the MCM_CR_SRAMLWP field. */
00343 #define BR_MCM_CR_SRAMLWP(x) (HW_MCM_CR(x).B.SRAMLWP)
00344 
00345 /*! @brief Format value for bitfield MCM_CR_SRAMLWP. */
00346 #define BF_MCM_CR_SRAMLWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLWP) & BM_MCM_CR_SRAMLWP)
00347 
00348 /*! @brief Set the SRAMLWP field to a new value. */
00349 #define BW_MCM_CR_SRAMLWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLWP) | BF_MCM_CR_SRAMLWP(v)))
00350 /*@}*/
00351 
00352 /*******************************************************************************
00353  * HW_MCM_ISCR - Interrupt Status Register
00354  ******************************************************************************/
00355 
00356 /*!
00357  * @brief HW_MCM_ISCR - Interrupt Status Register (RW)
00358  *
00359  * Reset value: 0x00000000U
00360  */
00361 typedef union _hw_mcm_iscr
00362 {
00363     uint32_t U;
00364     struct _hw_mcm_iscr_bitfields
00365     {
00366         uint32_t RESERVED0 : 1;        /*!< [0]  */
00367         uint32_t IRQ : 1;              /*!< [1] Normal Interrupt Pending */
00368         uint32_t NMI : 1;              /*!< [2] Non-maskable Interrupt Pending */
00369         uint32_t DHREQ : 1;            /*!< [3] Debug Halt Request Indicator */
00370         uint32_t RESERVED1 : 4;        /*!< [7:4]  */
00371         uint32_t FIOC : 1;             /*!< [8] FPU invalid operation interrupt status */
00372         uint32_t FDZC : 1;             /*!< [9] FPU divide-by-zero interrupt status */
00373         uint32_t FOFC : 1;             /*!< [10] FPU overflow interrupt status */
00374         uint32_t FUFC : 1;             /*!< [11] FPU underflow interrupt status */
00375         uint32_t FIXC : 1;             /*!< [12] FPU inexact interrupt status */
00376         uint32_t RESERVED2 : 2;        /*!< [14:13]  */
00377         uint32_t FIDC : 1;             /*!< [15] FPU input denormal interrupt status */
00378         uint32_t RESERVED3 : 8;        /*!< [23:16]  */
00379         uint32_t FIOCE : 1;            /*!< [24] FPU invalid operation interrupt enable
00380                                         * */
00381         uint32_t FDZCE : 1;            /*!< [25] FPU divide-by-zero interrupt enable */
00382         uint32_t FOFCE : 1;            /*!< [26] FPU overflow interrupt enable */
00383         uint32_t FUFCE : 1;            /*!< [27] FPU underflow interrupt enable */
00384         uint32_t FIXCE : 1;            /*!< [28] FPU inexact interrupt enable */
00385         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
00386         uint32_t FIDCE : 1;            /*!< [31] FPU input denormal interrupt enable */
00387     } B;
00388 } hw_mcm_iscr_t;
00389 
00390 /*!
00391  * @name Constants and macros for entire MCM_ISCR register
00392  */
00393 /*@{*/
00394 #define HW_MCM_ISCR_ADDR(x)      ((x) + 0x10U)
00395 
00396 #define HW_MCM_ISCR(x)           (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
00397 #define HW_MCM_ISCR_RD(x)        (HW_MCM_ISCR(x).U)
00398 #define HW_MCM_ISCR_WR(x, v)     (HW_MCM_ISCR(x).U = (v))
00399 #define HW_MCM_ISCR_SET(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) |  (v)))
00400 #define HW_MCM_ISCR_CLR(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
00401 #define HW_MCM_ISCR_TOG(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^  (v)))
00402 /*@}*/
00403 
00404 /*
00405  * Constants & macros for individual MCM_ISCR bitfields
00406  */
00407 
00408 /*!
00409  * @name Register MCM_ISCR, field IRQ[1] (W1C)
00410  *
00411  * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
00412  *
00413  * Values:
00414  * - 0 - No pending interrupt
00415  * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
00416  */
00417 /*@{*/
00418 #define BP_MCM_ISCR_IRQ      (1U)          /*!< Bit position for MCM_ISCR_IRQ. */
00419 #define BM_MCM_ISCR_IRQ      (0x00000002U) /*!< Bit mask for MCM_ISCR_IRQ. */
00420 #define BS_MCM_ISCR_IRQ      (1U)          /*!< Bit field size in bits for MCM_ISCR_IRQ. */
00421 
00422 /*! @brief Read current value of the MCM_ISCR_IRQ field. */
00423 #define BR_MCM_ISCR_IRQ(x)   (HW_MCM_ISCR(x).B.IRQ)
00424 
00425 /*! @brief Format value for bitfield MCM_ISCR_IRQ. */
00426 #define BF_MCM_ISCR_IRQ(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_IRQ) & BM_MCM_ISCR_IRQ)
00427 
00428 /*! @brief Set the IRQ field to a new value. */
00429 #define BW_MCM_ISCR_IRQ(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_IRQ) | BF_MCM_ISCR_IRQ(v)))
00430 /*@}*/
00431 
00432 /*!
00433  * @name Register MCM_ISCR, field NMI[2] (W1C)
00434  *
00435  * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
00436  *
00437  * Values:
00438  * - 0 - No pending NMI
00439  * - 1 - Due to the ETB counter expiring, an NMI is pending
00440  */
00441 /*@{*/
00442 #define BP_MCM_ISCR_NMI      (2U)          /*!< Bit position for MCM_ISCR_NMI. */
00443 #define BM_MCM_ISCR_NMI      (0x00000004U) /*!< Bit mask for MCM_ISCR_NMI. */
00444 #define BS_MCM_ISCR_NMI      (1U)          /*!< Bit field size in bits for MCM_ISCR_NMI. */
00445 
00446 /*! @brief Read current value of the MCM_ISCR_NMI field. */
00447 #define BR_MCM_ISCR_NMI(x)   (HW_MCM_ISCR(x).B.NMI)
00448 
00449 /*! @brief Format value for bitfield MCM_ISCR_NMI. */
00450 #define BF_MCM_ISCR_NMI(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_NMI) & BM_MCM_ISCR_NMI)
00451 
00452 /*! @brief Set the NMI field to a new value. */
00453 #define BW_MCM_ISCR_NMI(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_NMI) | BF_MCM_ISCR_NMI(v)))
00454 /*@}*/
00455 
00456 /*!
00457  * @name Register MCM_ISCR, field DHREQ[3] (RO)
00458  *
00459  * Indicates that a debug halt request is initiated due to a ETB counter
00460  * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
00461  * counter is disabled or when the ETB counter is reloaded.
00462  *
00463  * Values:
00464  * - 0 - No debug halt request
00465  * - 1 - Debug halt request initiated
00466  */
00467 /*@{*/
00468 #define BP_MCM_ISCR_DHREQ    (3U)          /*!< Bit position for MCM_ISCR_DHREQ. */
00469 #define BM_MCM_ISCR_DHREQ    (0x00000008U) /*!< Bit mask for MCM_ISCR_DHREQ. */
00470 #define BS_MCM_ISCR_DHREQ    (1U)          /*!< Bit field size in bits for MCM_ISCR_DHREQ. */
00471 
00472 /*! @brief Read current value of the MCM_ISCR_DHREQ field. */
00473 #define BR_MCM_ISCR_DHREQ(x) (HW_MCM_ISCR(x).B.DHREQ)
00474 /*@}*/
00475 
00476 /*!
00477  * @name Register MCM_ISCR, field FIOC[8] (RO)
00478  *
00479  * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
00480  * illegal operation has been detected in the processor's FPU. Once set, this bit
00481  * remains set until software clears the FPSCR[IOC] bit.
00482  *
00483  * Values:
00484  * - 0 - No interrupt
00485  * - 1 - Interrupt occurred
00486  */
00487 /*@{*/
00488 #define BP_MCM_ISCR_FIOC     (8U)          /*!< Bit position for MCM_ISCR_FIOC. */
00489 #define BM_MCM_ISCR_FIOC     (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
00490 #define BS_MCM_ISCR_FIOC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOC. */
00491 
00492 /*! @brief Read current value of the MCM_ISCR_FIOC field. */
00493 #define BR_MCM_ISCR_FIOC(x)  (HW_MCM_ISCR(x).B.FIOC)
00494 /*@}*/
00495 
00496 /*!
00497  * @name Register MCM_ISCR, field FDZC[9] (RO)
00498  *
00499  * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
00500  * divide by zero has been detected in the processor's FPU. Once set, this bit remains
00501  * set until software clears the FPSCR[DZC] bit.
00502  *
00503  * Values:
00504  * - 0 - No interrupt
00505  * - 1 - Interrupt occurred
00506  */
00507 /*@{*/
00508 #define BP_MCM_ISCR_FDZC     (9U)          /*!< Bit position for MCM_ISCR_FDZC. */
00509 #define BM_MCM_ISCR_FDZC     (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
00510 #define BS_MCM_ISCR_FDZC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZC. */
00511 
00512 /*! @brief Read current value of the MCM_ISCR_FDZC field. */
00513 #define BR_MCM_ISCR_FDZC(x)  (HW_MCM_ISCR(x).B.FDZC)
00514 /*@}*/
00515 
00516 /*!
00517  * @name Register MCM_ISCR, field FOFC[10] (RO)
00518  *
00519  * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
00520  * overflow has been detected in the processor's FPU. Once set, this bit remains set
00521  * until software clears the FPSCR[OFC] bit.
00522  *
00523  * Values:
00524  * - 0 - No interrupt
00525  * - 1 - Interrupt occurred
00526  */
00527 /*@{*/
00528 #define BP_MCM_ISCR_FOFC     (10U)         /*!< Bit position for MCM_ISCR_FOFC. */
00529 #define BM_MCM_ISCR_FOFC     (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
00530 #define BS_MCM_ISCR_FOFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFC. */
00531 
00532 /*! @brief Read current value of the MCM_ISCR_FOFC field. */
00533 #define BR_MCM_ISCR_FOFC(x)  (HW_MCM_ISCR(x).B.FOFC)
00534 /*@}*/
00535 
00536 /*!
00537  * @name Register MCM_ISCR, field FUFC[11] (RO)
00538  *
00539  * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
00540  * underflow has been detected in the processor's FPU. Once set, this bit remains set
00541  * until software clears the FPSCR[UFC] bit.
00542  *
00543  * Values:
00544  * - 0 - No interrupt
00545  * - 1 - Interrupt occurred
00546  */
00547 /*@{*/
00548 #define BP_MCM_ISCR_FUFC     (11U)         /*!< Bit position for MCM_ISCR_FUFC. */
00549 #define BM_MCM_ISCR_FUFC     (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
00550 #define BS_MCM_ISCR_FUFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFC. */
00551 
00552 /*! @brief Read current value of the MCM_ISCR_FUFC field. */
00553 #define BR_MCM_ISCR_FUFC(x)  (HW_MCM_ISCR(x).B.FUFC)
00554 /*@}*/
00555 
00556 /*!
00557  * @name Register MCM_ISCR, field FIXC[12] (RO)
00558  *
00559  * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
00560  * inexact number has been detected in the processor's FPU. Once set, this bit
00561  * remains set until software clears the FPSCR[IXC] bit.
00562  *
00563  * Values:
00564  * - 0 - No interrupt
00565  * - 1 - Interrupt occurred
00566  */
00567 /*@{*/
00568 #define BP_MCM_ISCR_FIXC     (12U)         /*!< Bit position for MCM_ISCR_FIXC. */
00569 #define BM_MCM_ISCR_FIXC     (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
00570 #define BS_MCM_ISCR_FIXC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXC. */
00571 
00572 /*! @brief Read current value of the MCM_ISCR_FIXC field. */
00573 #define BR_MCM_ISCR_FIXC(x)  (HW_MCM_ISCR(x).B.FIXC)
00574 /*@}*/
00575 
00576 /*!
00577  * @name Register MCM_ISCR, field FIDC[15] (RO)
00578  *
00579  * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
00580  * denormalized number has been detected in the processor's FPU. Once set, this
00581  * bit remains set until software clears the FPSCR[IDC] bit.
00582  *
00583  * Values:
00584  * - 0 - No interrupt
00585  * - 1 - Interrupt occurred
00586  */
00587 /*@{*/
00588 #define BP_MCM_ISCR_FIDC     (15U)         /*!< Bit position for MCM_ISCR_FIDC. */
00589 #define BM_MCM_ISCR_FIDC     (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
00590 #define BS_MCM_ISCR_FIDC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDC. */
00591 
00592 /*! @brief Read current value of the MCM_ISCR_FIDC field. */
00593 #define BR_MCM_ISCR_FIDC(x)  (HW_MCM_ISCR(x).B.FIDC)
00594 /*@}*/
00595 
00596 /*!
00597  * @name Register MCM_ISCR, field FIOCE[24] (RW)
00598  *
00599  * Values:
00600  * - 0 - Disable interrupt
00601  * - 1 - Enable interrupt
00602  */
00603 /*@{*/
00604 #define BP_MCM_ISCR_FIOCE    (24U)         /*!< Bit position for MCM_ISCR_FIOCE. */
00605 #define BM_MCM_ISCR_FIOCE    (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
00606 #define BS_MCM_ISCR_FIOCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
00607 
00608 /*! @brief Read current value of the MCM_ISCR_FIOCE field. */
00609 #define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
00610 
00611 /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
00612 #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
00613 
00614 /*! @brief Set the FIOCE field to a new value. */
00615 #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
00616 /*@}*/
00617 
00618 /*!
00619  * @name Register MCM_ISCR, field FDZCE[25] (RW)
00620  *
00621  * Values:
00622  * - 0 - Disable interrupt
00623  * - 1 - Enable interrupt
00624  */
00625 /*@{*/
00626 #define BP_MCM_ISCR_FDZCE    (25U)         /*!< Bit position for MCM_ISCR_FDZCE. */
00627 #define BM_MCM_ISCR_FDZCE    (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
00628 #define BS_MCM_ISCR_FDZCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
00629 
00630 /*! @brief Read current value of the MCM_ISCR_FDZCE field. */
00631 #define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
00632 
00633 /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
00634 #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
00635 
00636 /*! @brief Set the FDZCE field to a new value. */
00637 #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
00638 /*@}*/
00639 
00640 /*!
00641  * @name Register MCM_ISCR, field FOFCE[26] (RW)
00642  *
00643  * Values:
00644  * - 0 - Disable interrupt
00645  * - 1 - Enable interrupt
00646  */
00647 /*@{*/
00648 #define BP_MCM_ISCR_FOFCE    (26U)         /*!< Bit position for MCM_ISCR_FOFCE. */
00649 #define BM_MCM_ISCR_FOFCE    (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
00650 #define BS_MCM_ISCR_FOFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
00651 
00652 /*! @brief Read current value of the MCM_ISCR_FOFCE field. */
00653 #define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
00654 
00655 /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
00656 #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
00657 
00658 /*! @brief Set the FOFCE field to a new value. */
00659 #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
00660 /*@}*/
00661 
00662 /*!
00663  * @name Register MCM_ISCR, field FUFCE[27] (RW)
00664  *
00665  * Values:
00666  * - 0 - Disable interrupt
00667  * - 1 - Enable interrupt
00668  */
00669 /*@{*/
00670 #define BP_MCM_ISCR_FUFCE    (27U)         /*!< Bit position for MCM_ISCR_FUFCE. */
00671 #define BM_MCM_ISCR_FUFCE    (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
00672 #define BS_MCM_ISCR_FUFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
00673 
00674 /*! @brief Read current value of the MCM_ISCR_FUFCE field. */
00675 #define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
00676 
00677 /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
00678 #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
00679 
00680 /*! @brief Set the FUFCE field to a new value. */
00681 #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
00682 /*@}*/
00683 
00684 /*!
00685  * @name Register MCM_ISCR, field FIXCE[28] (RW)
00686  *
00687  * Values:
00688  * - 0 - Disable interrupt
00689  * - 1 - Enable interrupt
00690  */
00691 /*@{*/
00692 #define BP_MCM_ISCR_FIXCE    (28U)         /*!< Bit position for MCM_ISCR_FIXCE. */
00693 #define BM_MCM_ISCR_FIXCE    (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
00694 #define BS_MCM_ISCR_FIXCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
00695 
00696 /*! @brief Read current value of the MCM_ISCR_FIXCE field. */
00697 #define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
00698 
00699 /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
00700 #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
00701 
00702 /*! @brief Set the FIXCE field to a new value. */
00703 #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
00704 /*@}*/
00705 
00706 /*!
00707  * @name Register MCM_ISCR, field FIDCE[31] (RW)
00708  *
00709  * Values:
00710  * - 0 - Disable interrupt
00711  * - 1 - Enable interrupt
00712  */
00713 /*@{*/
00714 #define BP_MCM_ISCR_FIDCE    (31U)         /*!< Bit position for MCM_ISCR_FIDCE. */
00715 #define BM_MCM_ISCR_FIDCE    (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
00716 #define BS_MCM_ISCR_FIDCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
00717 
00718 /*! @brief Read current value of the MCM_ISCR_FIDCE field. */
00719 #define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
00720 
00721 /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
00722 #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
00723 
00724 /*! @brief Set the FIDCE field to a new value. */
00725 #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
00726 /*@}*/
00727 
00728 /*******************************************************************************
00729  * HW_MCM_ETBCC - ETB Counter Control register
00730  ******************************************************************************/
00731 
00732 /*!
00733  * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
00734  *
00735  * Reset value: 0x00000000U
00736  */
00737 typedef union _hw_mcm_etbcc
00738 {
00739     uint32_t U;
00740     struct _hw_mcm_etbcc_bitfields
00741     {
00742         uint32_t CNTEN : 1;            /*!< [0] Counter Enable */
00743         uint32_t RSPT : 2;             /*!< [2:1] Response Type */
00744         uint32_t RLRQ : 1;             /*!< [3] Reload Request */
00745         uint32_t ETDIS : 1;            /*!< [4] ETM-To-TPIU Disable */
00746         uint32_t ITDIS : 1;            /*!< [5] ITM-To-TPIU Disable */
00747         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
00748     } B;
00749 } hw_mcm_etbcc_t;
00750 
00751 /*!
00752  * @name Constants and macros for entire MCM_ETBCC register
00753  */
00754 /*@{*/
00755 #define HW_MCM_ETBCC_ADDR(x)     ((x) + 0x14U)
00756 
00757 #define HW_MCM_ETBCC(x)          (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR(x))
00758 #define HW_MCM_ETBCC_RD(x)       (HW_MCM_ETBCC(x).U)
00759 #define HW_MCM_ETBCC_WR(x, v)    (HW_MCM_ETBCC(x).U = (v))
00760 #define HW_MCM_ETBCC_SET(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) |  (v)))
00761 #define HW_MCM_ETBCC_CLR(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) & ~(v)))
00762 #define HW_MCM_ETBCC_TOG(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) ^  (v)))
00763 /*@}*/
00764 
00765 /*
00766  * Constants & macros for individual MCM_ETBCC bitfields
00767  */
00768 
00769 /*!
00770  * @name Register MCM_ETBCC, field CNTEN[0] (RW)
00771  *
00772  * Enables the ETB counter.
00773  *
00774  * Values:
00775  * - 0 - ETB counter disabled
00776  * - 1 - ETB counter enabled
00777  */
00778 /*@{*/
00779 #define BP_MCM_ETBCC_CNTEN   (0U)          /*!< Bit position for MCM_ETBCC_CNTEN. */
00780 #define BM_MCM_ETBCC_CNTEN   (0x00000001U) /*!< Bit mask for MCM_ETBCC_CNTEN. */
00781 #define BS_MCM_ETBCC_CNTEN   (1U)          /*!< Bit field size in bits for MCM_ETBCC_CNTEN. */
00782 
00783 /*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
00784 #define BR_MCM_ETBCC_CNTEN(x) (HW_MCM_ETBCC(x).B.CNTEN)
00785 
00786 /*! @brief Format value for bitfield MCM_ETBCC_CNTEN. */
00787 #define BF_MCM_ETBCC_CNTEN(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_CNTEN) & BM_MCM_ETBCC_CNTEN)
00788 
00789 /*! @brief Set the CNTEN field to a new value. */
00790 #define BW_MCM_ETBCC_CNTEN(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_CNTEN) | BF_MCM_ETBCC_CNTEN(v)))
00791 /*@}*/
00792 
00793 /*!
00794  * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
00795  *
00796  * Values:
00797  * - 00 - No response when the ETB count expires
00798  * - 01 - Generate a normal interrupt when the ETB count expires
00799  * - 10 - Generate an NMI when the ETB count expires
00800  * - 11 - Generate a debug halt when the ETB count expires
00801  */
00802 /*@{*/
00803 #define BP_MCM_ETBCC_RSPT    (1U)          /*!< Bit position for MCM_ETBCC_RSPT. */
00804 #define BM_MCM_ETBCC_RSPT    (0x00000006U) /*!< Bit mask for MCM_ETBCC_RSPT. */
00805 #define BS_MCM_ETBCC_RSPT    (2U)          /*!< Bit field size in bits for MCM_ETBCC_RSPT. */
00806 
00807 /*! @brief Read current value of the MCM_ETBCC_RSPT field. */
00808 #define BR_MCM_ETBCC_RSPT(x) (HW_MCM_ETBCC(x).B.RSPT)
00809 
00810 /*! @brief Format value for bitfield MCM_ETBCC_RSPT. */
00811 #define BF_MCM_ETBCC_RSPT(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RSPT) & BM_MCM_ETBCC_RSPT)
00812 
00813 /*! @brief Set the RSPT field to a new value. */
00814 #define BW_MCM_ETBCC_RSPT(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
00815 /*@}*/
00816 
00817 /*!
00818  * @name Register MCM_ETBCC, field RLRQ[3] (RW)
00819  *
00820  * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
00821  * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
00822  * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
00823  * If debug halt was enabled and a debug halt request was asserted on counter
00824  * expiration, setting this bit clears the debug halt request.
00825  *
00826  * Values:
00827  * - 0 - No effect
00828  * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
00829  */
00830 /*@{*/
00831 #define BP_MCM_ETBCC_RLRQ    (3U)          /*!< Bit position for MCM_ETBCC_RLRQ. */
00832 #define BM_MCM_ETBCC_RLRQ    (0x00000008U) /*!< Bit mask for MCM_ETBCC_RLRQ. */
00833 #define BS_MCM_ETBCC_RLRQ    (1U)          /*!< Bit field size in bits for MCM_ETBCC_RLRQ. */
00834 
00835 /*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
00836 #define BR_MCM_ETBCC_RLRQ(x) (HW_MCM_ETBCC(x).B.RLRQ)
00837 
00838 /*! @brief Format value for bitfield MCM_ETBCC_RLRQ. */
00839 #define BF_MCM_ETBCC_RLRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RLRQ) & BM_MCM_ETBCC_RLRQ)
00840 
00841 /*! @brief Set the RLRQ field to a new value. */
00842 #define BW_MCM_ETBCC_RLRQ(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RLRQ) | BF_MCM_ETBCC_RLRQ(v)))
00843 /*@}*/
00844 
00845 /*!
00846  * @name Register MCM_ETBCC, field ETDIS[4] (RW)
00847  *
00848  * Disables the trace path from ETM to TPIU.
00849  *
00850  * Values:
00851  * - 0 - ETM-to-TPIU trace path enabled
00852  * - 1 - ETM-to-TPIU trace path disabled
00853  */
00854 /*@{*/
00855 #define BP_MCM_ETBCC_ETDIS   (4U)          /*!< Bit position for MCM_ETBCC_ETDIS. */
00856 #define BM_MCM_ETBCC_ETDIS   (0x00000010U) /*!< Bit mask for MCM_ETBCC_ETDIS. */
00857 #define BS_MCM_ETBCC_ETDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ETDIS. */
00858 
00859 /*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
00860 #define BR_MCM_ETBCC_ETDIS(x) (HW_MCM_ETBCC(x).B.ETDIS)
00861 
00862 /*! @brief Format value for bitfield MCM_ETBCC_ETDIS. */
00863 #define BF_MCM_ETBCC_ETDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ETDIS) & BM_MCM_ETBCC_ETDIS)
00864 
00865 /*! @brief Set the ETDIS field to a new value. */
00866 #define BW_MCM_ETBCC_ETDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ETDIS) | BF_MCM_ETBCC_ETDIS(v)))
00867 /*@}*/
00868 
00869 /*!
00870  * @name Register MCM_ETBCC, field ITDIS[5] (RW)
00871  *
00872  * Disables the trace path from ITM to TPIU.
00873  *
00874  * Values:
00875  * - 0 - ITM-to-TPIU trace path enabled
00876  * - 1 - ITM-to-TPIU trace path disabled
00877  */
00878 /*@{*/
00879 #define BP_MCM_ETBCC_ITDIS   (5U)          /*!< Bit position for MCM_ETBCC_ITDIS. */
00880 #define BM_MCM_ETBCC_ITDIS   (0x00000020U) /*!< Bit mask for MCM_ETBCC_ITDIS. */
00881 #define BS_MCM_ETBCC_ITDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ITDIS. */
00882 
00883 /*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
00884 #define BR_MCM_ETBCC_ITDIS(x) (HW_MCM_ETBCC(x).B.ITDIS)
00885 
00886 /*! @brief Format value for bitfield MCM_ETBCC_ITDIS. */
00887 #define BF_MCM_ETBCC_ITDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ITDIS) & BM_MCM_ETBCC_ITDIS)
00888 
00889 /*! @brief Set the ITDIS field to a new value. */
00890 #define BW_MCM_ETBCC_ITDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ITDIS) | BF_MCM_ETBCC_ITDIS(v)))
00891 /*@}*/
00892 
00893 /*******************************************************************************
00894  * HW_MCM_ETBRL - ETB Reload register
00895  ******************************************************************************/
00896 
00897 /*!
00898  * @brief HW_MCM_ETBRL - ETB Reload register (RW)
00899  *
00900  * Reset value: 0x00000000U
00901  */
00902 typedef union _hw_mcm_etbrl
00903 {
00904     uint32_t U;
00905     struct _hw_mcm_etbrl_bitfields
00906     {
00907         uint32_t RELOAD : 11;          /*!< [10:0] Byte Count Reload Value */
00908         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
00909     } B;
00910 } hw_mcm_etbrl_t;
00911 
00912 /*!
00913  * @name Constants and macros for entire MCM_ETBRL register
00914  */
00915 /*@{*/
00916 #define HW_MCM_ETBRL_ADDR(x)     ((x) + 0x18U)
00917 
00918 #define HW_MCM_ETBRL(x)          (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR(x))
00919 #define HW_MCM_ETBRL_RD(x)       (HW_MCM_ETBRL(x).U)
00920 #define HW_MCM_ETBRL_WR(x, v)    (HW_MCM_ETBRL(x).U = (v))
00921 #define HW_MCM_ETBRL_SET(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) |  (v)))
00922 #define HW_MCM_ETBRL_CLR(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) & ~(v)))
00923 #define HW_MCM_ETBRL_TOG(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) ^  (v)))
00924 /*@}*/
00925 
00926 /*
00927  * Constants & macros for individual MCM_ETBRL bitfields
00928  */
00929 
00930 /*!
00931  * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
00932  *
00933  * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
00934  * value to this field results in a bus error.
00935  */
00936 /*@{*/
00937 #define BP_MCM_ETBRL_RELOAD  (0U)          /*!< Bit position for MCM_ETBRL_RELOAD. */
00938 #define BM_MCM_ETBRL_RELOAD  (0x000007FFU) /*!< Bit mask for MCM_ETBRL_RELOAD. */
00939 #define BS_MCM_ETBRL_RELOAD  (11U)         /*!< Bit field size in bits for MCM_ETBRL_RELOAD. */
00940 
00941 /*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
00942 #define BR_MCM_ETBRL_RELOAD(x) (HW_MCM_ETBRL(x).B.RELOAD)
00943 
00944 /*! @brief Format value for bitfield MCM_ETBRL_RELOAD. */
00945 #define BF_MCM_ETBRL_RELOAD(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBRL_RELOAD) & BM_MCM_ETBRL_RELOAD)
00946 
00947 /*! @brief Set the RELOAD field to a new value. */
00948 #define BW_MCM_ETBRL_RELOAD(x, v) (HW_MCM_ETBRL_WR(x, (HW_MCM_ETBRL_RD(x) & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
00949 /*@}*/
00950 
00951 /*******************************************************************************
00952  * HW_MCM_ETBCNT - ETB Counter Value register
00953  ******************************************************************************/
00954 
00955 /*!
00956  * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
00957  *
00958  * Reset value: 0x00000000U
00959  */
00960 typedef union _hw_mcm_etbcnt
00961 {
00962     uint32_t U;
00963     struct _hw_mcm_etbcnt_bitfields
00964     {
00965         uint32_t COUNTER : 11;         /*!< [10:0] Byte Count Counter Value */
00966         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
00967     } B;
00968 } hw_mcm_etbcnt_t;
00969 
00970 /*!
00971  * @name Constants and macros for entire MCM_ETBCNT register
00972  */
00973 /*@{*/
00974 #define HW_MCM_ETBCNT_ADDR(x)    ((x) + 0x1CU)
00975 
00976 #define HW_MCM_ETBCNT(x)         (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR(x))
00977 #define HW_MCM_ETBCNT_RD(x)      (HW_MCM_ETBCNT(x).U)
00978 /*@}*/
00979 
00980 /*
00981  * Constants & macros for individual MCM_ETBCNT bitfields
00982  */
00983 
00984 /*!
00985  * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
00986  *
00987  * Indicates the current 0-mod-4 value of the counter.
00988  */
00989 /*@{*/
00990 #define BP_MCM_ETBCNT_COUNTER (0U)         /*!< Bit position for MCM_ETBCNT_COUNTER. */
00991 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) /*!< Bit mask for MCM_ETBCNT_COUNTER. */
00992 #define BS_MCM_ETBCNT_COUNTER (11U)        /*!< Bit field size in bits for MCM_ETBCNT_COUNTER. */
00993 
00994 /*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
00995 #define BR_MCM_ETBCNT_COUNTER(x) (HW_MCM_ETBCNT(x).B.COUNTER)
00996 /*@}*/
00997 
00998 /*******************************************************************************
00999  * HW_MCM_PID - Process ID register
01000  ******************************************************************************/
01001 
01002 /*!
01003  * @brief HW_MCM_PID - Process ID register (RW)
01004  *
01005  * Reset value: 0x00000000U
01006  *
01007  * This register drives the M0_PID and M1_PID values in the Memory Protection
01008  * Unit(MPU). System software loads this register before passing control to a given
01009  * user mode process. If the PID of the process does not match the value in this
01010  * register, a bus error occurs. See the MPU chapter for more details.
01011  */
01012 typedef union _hw_mcm_pid
01013 {
01014     uint32_t U;
01015     struct _hw_mcm_pid_bitfields
01016     {
01017         uint32_t PID : 8;              /*!< [7:0] M0_PID And M1_PID For MPU */
01018         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01019     } B;
01020 } hw_mcm_pid_t;
01021 
01022 /*!
01023  * @name Constants and macros for entire MCM_PID register
01024  */
01025 /*@{*/
01026 #define HW_MCM_PID_ADDR(x)       ((x) + 0x30U)
01027 
01028 #define HW_MCM_PID(x)            (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR(x))
01029 #define HW_MCM_PID_RD(x)         (HW_MCM_PID(x).U)
01030 #define HW_MCM_PID_WR(x, v)      (HW_MCM_PID(x).U = (v))
01031 #define HW_MCM_PID_SET(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) |  (v)))
01032 #define HW_MCM_PID_CLR(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) & ~(v)))
01033 #define HW_MCM_PID_TOG(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) ^  (v)))
01034 /*@}*/
01035 
01036 /*
01037  * Constants & macros for individual MCM_PID bitfields
01038  */
01039 
01040 /*!
01041  * @name Register MCM_PID, field PID[7:0] (RW)
01042  *
01043  * Drives the M0_PID and M1_PID values in the MPU.
01044  */
01045 /*@{*/
01046 #define BP_MCM_PID_PID       (0U)          /*!< Bit position for MCM_PID_PID. */
01047 #define BM_MCM_PID_PID       (0x000000FFU) /*!< Bit mask for MCM_PID_PID. */
01048 #define BS_MCM_PID_PID       (8U)          /*!< Bit field size in bits for MCM_PID_PID. */
01049 
01050 /*! @brief Read current value of the MCM_PID_PID field. */
01051 #define BR_MCM_PID_PID(x)    (HW_MCM_PID(x).B.PID)
01052 
01053 /*! @brief Format value for bitfield MCM_PID_PID. */
01054 #define BF_MCM_PID_PID(v)    ((uint32_t)((uint32_t)(v) << BP_MCM_PID_PID) & BM_MCM_PID_PID)
01055 
01056 /*! @brief Set the PID field to a new value. */
01057 #define BW_MCM_PID_PID(x, v) (HW_MCM_PID_WR(x, (HW_MCM_PID_RD(x) & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
01058 /*@}*/
01059 
01060 /*******************************************************************************
01061  * hw_mcm_t - module struct
01062  ******************************************************************************/
01063 /*!
01064  * @brief All MCM module registers.
01065  */
01066 #pragma pack(1)
01067 typedef struct _hw_mcm
01068 {
01069     uint8_t _reserved0[8];
01070     __I hw_mcm_plasc_t PLASC ;              /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
01071     __I hw_mcm_plamc_t PLAMC ;              /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
01072     __IO hw_mcm_cr_t CR ;                   /*!< [0xC] Control Register */
01073     __IO hw_mcm_iscr_t ISCR ;               /*!< [0x10] Interrupt Status Register */
01074     __IO hw_mcm_etbcc_t ETBCC ;             /*!< [0x14] ETB Counter Control register */
01075     __IO hw_mcm_etbrl_t ETBRL ;             /*!< [0x18] ETB Reload register */
01076     __I hw_mcm_etbcnt_t ETBCNT ;            /*!< [0x1C] ETB Counter Value register */
01077     uint8_t _reserved1[16];
01078     __IO hw_mcm_pid_t PID ;                 /*!< [0x30] Process ID register */
01079 } hw_mcm_t;
01080 #pragma pack()
01081 
01082 /*! @brief Macro to access all MCM registers. */
01083 /*! @param x MCM module instance base address. */
01084 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01085  *     use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
01086 #define HW_MCM(x)      (*(hw_mcm_t *)(x))
01087 
01088 #endif /* __HW_MCM_REGISTERS_H__ */
01089 /* EOF */