MK64F12_i2s.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_I2S_REGISTERS_H__
00081 #define __HW_I2S_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 I2S
00088  *
00089  * Inter-IC Sound / Synchronous Audio Interface
00090  *
00091  * Registers defined in this header file:
00092  * - HW_I2S_TCSR - SAI Transmit Control Register
00093  * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
00094  * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
00095  * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
00096  * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
00097  * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
00098  * - HW_I2S_TDRn - SAI Transmit Data Register
00099  * - HW_I2S_TFRn - SAI Transmit FIFO Register
00100  * - HW_I2S_TMR - SAI Transmit Mask Register
00101  * - HW_I2S_RCSR - SAI Receive Control Register
00102  * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
00103  * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
00104  * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
00105  * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
00106  * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
00107  * - HW_I2S_RDRn - SAI Receive Data Register
00108  * - HW_I2S_RFRn - SAI Receive FIFO Register
00109  * - HW_I2S_RMR - SAI Receive Mask Register
00110  * - HW_I2S_MCR - SAI MCLK Control Register
00111  * - HW_I2S_MDR - SAI MCLK Divide Register
00112  *
00113  * - hw_i2s_t - Struct containing all module registers.
00114  */
00115 
00116 #define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
00117 
00118 /*******************************************************************************
00119  * HW_I2S_TCSR - SAI Transmit Control Register
00120  ******************************************************************************/
00121 
00122 /*!
00123  * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
00124  *
00125  * Reset value: 0x00000000U
00126  */
00127 typedef union _hw_i2s_tcsr
00128 {
00129     uint32_t U;
00130     struct _hw_i2s_tcsr_bitfields
00131     {
00132         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
00133         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
00134         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
00135         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
00136         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
00137         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
00138         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
00139         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
00140         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
00141         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
00142         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
00143         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
00144         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
00145         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
00146         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
00147         uint32_t SR : 1;               /*!< [24] Software Reset */
00148         uint32_t FR : 1;               /*!< [25] FIFO Reset */
00149         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
00150         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
00151         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
00152         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
00153         uint32_t TE : 1;               /*!< [31] Transmitter Enable */
00154     } B;
00155 } hw_i2s_tcsr_t;
00156 
00157 /*!
00158  * @name Constants and macros for entire I2S_TCSR register
00159  */
00160 /*@{*/
00161 #define HW_I2S_TCSR_ADDR(x)      ((x) + 0x0U)
00162 
00163 #define HW_I2S_TCSR(x)           (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
00164 #define HW_I2S_TCSR_RD(x)        (HW_I2S_TCSR(x).U)
00165 #define HW_I2S_TCSR_WR(x, v)     (HW_I2S_TCSR(x).U = (v))
00166 #define HW_I2S_TCSR_SET(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) |  (v)))
00167 #define HW_I2S_TCSR_CLR(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
00168 #define HW_I2S_TCSR_TOG(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^  (v)))
00169 /*@}*/
00170 
00171 /*
00172  * Constants & macros for individual I2S_TCSR bitfields
00173  */
00174 
00175 /*!
00176  * @name Register I2S_TCSR, field FRDE[0] (RW)
00177  *
00178  * Enables/disables DMA requests.
00179  *
00180  * Values:
00181  * - 0 - Disables the DMA request.
00182  * - 1 - Enables the DMA request.
00183  */
00184 /*@{*/
00185 #define BP_I2S_TCSR_FRDE     (0U)          /*!< Bit position for I2S_TCSR_FRDE. */
00186 #define BM_I2S_TCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */
00187 #define BS_I2S_TCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRDE. */
00188 
00189 /*! @brief Read current value of the I2S_TCSR_FRDE field. */
00190 #define BR_I2S_TCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
00191 
00192 /*! @brief Format value for bitfield I2S_TCSR_FRDE. */
00193 #define BF_I2S_TCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
00194 
00195 /*! @brief Set the FRDE field to a new value. */
00196 #define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
00197 /*@}*/
00198 
00199 /*!
00200  * @name Register I2S_TCSR, field FWDE[1] (RW)
00201  *
00202  * Enables/disables DMA requests.
00203  *
00204  * Values:
00205  * - 0 - Disables the DMA request.
00206  * - 1 - Enables the DMA request.
00207  */
00208 /*@{*/
00209 #define BP_I2S_TCSR_FWDE     (1U)          /*!< Bit position for I2S_TCSR_FWDE. */
00210 #define BM_I2S_TCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */
00211 #define BS_I2S_TCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWDE. */
00212 
00213 /*! @brief Read current value of the I2S_TCSR_FWDE field. */
00214 #define BR_I2S_TCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
00215 
00216 /*! @brief Format value for bitfield I2S_TCSR_FWDE. */
00217 #define BF_I2S_TCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
00218 
00219 /*! @brief Set the FWDE field to a new value. */
00220 #define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
00221 /*@}*/
00222 
00223 /*!
00224  * @name Register I2S_TCSR, field FRIE[8] (RW)
00225  *
00226  * Enables/disables FIFO request interrupts.
00227  *
00228  * Values:
00229  * - 0 - Disables the interrupt.
00230  * - 1 - Enables the interrupt.
00231  */
00232 /*@{*/
00233 #define BP_I2S_TCSR_FRIE     (8U)          /*!< Bit position for I2S_TCSR_FRIE. */
00234 #define BM_I2S_TCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */
00235 #define BS_I2S_TCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRIE. */
00236 
00237 /*! @brief Read current value of the I2S_TCSR_FRIE field. */
00238 #define BR_I2S_TCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
00239 
00240 /*! @brief Format value for bitfield I2S_TCSR_FRIE. */
00241 #define BF_I2S_TCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
00242 
00243 /*! @brief Set the FRIE field to a new value. */
00244 #define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
00245 /*@}*/
00246 
00247 /*!
00248  * @name Register I2S_TCSR, field FWIE[9] (RW)
00249  *
00250  * Enables/disables FIFO warning interrupts.
00251  *
00252  * Values:
00253  * - 0 - Disables the interrupt.
00254  * - 1 - Enables the interrupt.
00255  */
00256 /*@{*/
00257 #define BP_I2S_TCSR_FWIE     (9U)          /*!< Bit position for I2S_TCSR_FWIE. */
00258 #define BM_I2S_TCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */
00259 #define BS_I2S_TCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWIE. */
00260 
00261 /*! @brief Read current value of the I2S_TCSR_FWIE field. */
00262 #define BR_I2S_TCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
00263 
00264 /*! @brief Format value for bitfield I2S_TCSR_FWIE. */
00265 #define BF_I2S_TCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
00266 
00267 /*! @brief Set the FWIE field to a new value. */
00268 #define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
00269 /*@}*/
00270 
00271 /*!
00272  * @name Register I2S_TCSR, field FEIE[10] (RW)
00273  *
00274  * Enables/disables FIFO error interrupts.
00275  *
00276  * Values:
00277  * - 0 - Disables the interrupt.
00278  * - 1 - Enables the interrupt.
00279  */
00280 /*@{*/
00281 #define BP_I2S_TCSR_FEIE     (10U)         /*!< Bit position for I2S_TCSR_FEIE. */
00282 #define BM_I2S_TCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */
00283 #define BS_I2S_TCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FEIE. */
00284 
00285 /*! @brief Read current value of the I2S_TCSR_FEIE field. */
00286 #define BR_I2S_TCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
00287 
00288 /*! @brief Format value for bitfield I2S_TCSR_FEIE. */
00289 #define BF_I2S_TCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
00290 
00291 /*! @brief Set the FEIE field to a new value. */
00292 #define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
00293 /*@}*/
00294 
00295 /*!
00296  * @name Register I2S_TCSR, field SEIE[11] (RW)
00297  *
00298  * Enables/disables sync error interrupts.
00299  *
00300  * Values:
00301  * - 0 - Disables interrupt.
00302  * - 1 - Enables interrupt.
00303  */
00304 /*@{*/
00305 #define BP_I2S_TCSR_SEIE     (11U)         /*!< Bit position for I2S_TCSR_SEIE. */
00306 #define BM_I2S_TCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */
00307 #define BS_I2S_TCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_SEIE. */
00308 
00309 /*! @brief Read current value of the I2S_TCSR_SEIE field. */
00310 #define BR_I2S_TCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
00311 
00312 /*! @brief Format value for bitfield I2S_TCSR_SEIE. */
00313 #define BF_I2S_TCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
00314 
00315 /*! @brief Set the SEIE field to a new value. */
00316 #define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
00317 /*@}*/
00318 
00319 /*!
00320  * @name Register I2S_TCSR, field WSIE[12] (RW)
00321  *
00322  * Enables/disables word start interrupts.
00323  *
00324  * Values:
00325  * - 0 - Disables interrupt.
00326  * - 1 - Enables interrupt.
00327  */
00328 /*@{*/
00329 #define BP_I2S_TCSR_WSIE     (12U)         /*!< Bit position for I2S_TCSR_WSIE. */
00330 #define BM_I2S_TCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */
00331 #define BS_I2S_TCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_WSIE. */
00332 
00333 /*! @brief Read current value of the I2S_TCSR_WSIE field. */
00334 #define BR_I2S_TCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
00335 
00336 /*! @brief Format value for bitfield I2S_TCSR_WSIE. */
00337 #define BF_I2S_TCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
00338 
00339 /*! @brief Set the WSIE field to a new value. */
00340 #define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
00341 /*@}*/
00342 
00343 /*!
00344  * @name Register I2S_TCSR, field FRF[16] (RO)
00345  *
00346  * Indicates that the number of words in an enabled transmit channel FIFO is
00347  * less than or equal to the transmit FIFO watermark.
00348  *
00349  * Values:
00350  * - 0 - Transmit FIFO watermark has not been reached.
00351  * - 1 - Transmit FIFO watermark has been reached.
00352  */
00353 /*@{*/
00354 #define BP_I2S_TCSR_FRF      (16U)         /*!< Bit position for I2S_TCSR_FRF. */
00355 #define BM_I2S_TCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */
00356 #define BS_I2S_TCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FRF. */
00357 
00358 /*! @brief Read current value of the I2S_TCSR_FRF field. */
00359 #define BR_I2S_TCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
00360 /*@}*/
00361 
00362 /*!
00363  * @name Register I2S_TCSR, field FWF[17] (RO)
00364  *
00365  * Indicates that an enabled transmit FIFO is empty.
00366  *
00367  * Values:
00368  * - 0 - No enabled transmit FIFO is empty.
00369  * - 1 - Enabled transmit FIFO is empty.
00370  */
00371 /*@{*/
00372 #define BP_I2S_TCSR_FWF      (17U)         /*!< Bit position for I2S_TCSR_FWF. */
00373 #define BM_I2S_TCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */
00374 #define BS_I2S_TCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FWF. */
00375 
00376 /*! @brief Read current value of the I2S_TCSR_FWF field. */
00377 #define BR_I2S_TCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
00378 /*@}*/
00379 
00380 /*!
00381  * @name Register I2S_TCSR, field FEF[18] (W1C)
00382  *
00383  * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
00384  * field to clear this flag.
00385  *
00386  * Values:
00387  * - 0 - Transmit underrun not detected.
00388  * - 1 - Transmit underrun detected.
00389  */
00390 /*@{*/
00391 #define BP_I2S_TCSR_FEF      (18U)         /*!< Bit position for I2S_TCSR_FEF. */
00392 #define BM_I2S_TCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */
00393 #define BS_I2S_TCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FEF. */
00394 
00395 /*! @brief Read current value of the I2S_TCSR_FEF field. */
00396 #define BR_I2S_TCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
00397 
00398 /*! @brief Format value for bitfield I2S_TCSR_FEF. */
00399 #define BF_I2S_TCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
00400 
00401 /*! @brief Set the FEF field to a new value. */
00402 #define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
00403 /*@}*/
00404 
00405 /*!
00406  * @name Register I2S_TCSR, field SEF[19] (W1C)
00407  *
00408  * Indicates that an error in the externally-generated frame sync has been
00409  * detected. Write a logic 1 to this field to clear this flag.
00410  *
00411  * Values:
00412  * - 0 - Sync error not detected.
00413  * - 1 - Frame sync error detected.
00414  */
00415 /*@{*/
00416 #define BP_I2S_TCSR_SEF      (19U)         /*!< Bit position for I2S_TCSR_SEF. */
00417 #define BM_I2S_TCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */
00418 #define BS_I2S_TCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_SEF. */
00419 
00420 /*! @brief Read current value of the I2S_TCSR_SEF field. */
00421 #define BR_I2S_TCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
00422 
00423 /*! @brief Format value for bitfield I2S_TCSR_SEF. */
00424 #define BF_I2S_TCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
00425 
00426 /*! @brief Set the SEF field to a new value. */
00427 #define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
00428 /*@}*/
00429 
00430 /*!
00431  * @name Register I2S_TCSR, field WSF[20] (W1C)
00432  *
00433  * Indicates that the start of the configured word has been detected. Write a
00434  * logic 1 to this field to clear this flag.
00435  *
00436  * Values:
00437  * - 0 - Start of word not detected.
00438  * - 1 - Start of word detected.
00439  */
00440 /*@{*/
00441 #define BP_I2S_TCSR_WSF      (20U)         /*!< Bit position for I2S_TCSR_WSF. */
00442 #define BM_I2S_TCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */
00443 #define BS_I2S_TCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_TCSR_WSF. */
00444 
00445 /*! @brief Read current value of the I2S_TCSR_WSF field. */
00446 #define BR_I2S_TCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
00447 
00448 /*! @brief Format value for bitfield I2S_TCSR_WSF. */
00449 #define BF_I2S_TCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
00450 
00451 /*! @brief Set the WSF field to a new value. */
00452 #define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
00453 /*@}*/
00454 
00455 /*!
00456  * @name Register I2S_TCSR, field SR[24] (RW)
00457  *
00458  * When set, resets the internal transmitter logic including the FIFO pointers.
00459  * Software-visible registers are not affected, except for the status registers.
00460  *
00461  * Values:
00462  * - 0 - No effect.
00463  * - 1 - Software reset.
00464  */
00465 /*@{*/
00466 #define BP_I2S_TCSR_SR       (24U)         /*!< Bit position for I2S_TCSR_SR. */
00467 #define BM_I2S_TCSR_SR       (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */
00468 #define BS_I2S_TCSR_SR       (1U)          /*!< Bit field size in bits for I2S_TCSR_SR. */
00469 
00470 /*! @brief Read current value of the I2S_TCSR_SR field. */
00471 #define BR_I2S_TCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
00472 
00473 /*! @brief Format value for bitfield I2S_TCSR_SR. */
00474 #define BF_I2S_TCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
00475 
00476 /*! @brief Set the SR field to a new value. */
00477 #define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
00478 /*@}*/
00479 
00480 /*!
00481  * @name Register I2S_TCSR, field FR[25] (WORZ)
00482  *
00483  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
00484  * pointers should only be reset when the transmitter is disabled or the FIFO error
00485  * flag is set.
00486  *
00487  * Values:
00488  * - 0 - No effect.
00489  * - 1 - FIFO reset.
00490  */
00491 /*@{*/
00492 #define BP_I2S_TCSR_FR       (25U)         /*!< Bit position for I2S_TCSR_FR. */
00493 #define BM_I2S_TCSR_FR       (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */
00494 #define BS_I2S_TCSR_FR       (1U)          /*!< Bit field size in bits for I2S_TCSR_FR. */
00495 
00496 /*! @brief Format value for bitfield I2S_TCSR_FR. */
00497 #define BF_I2S_TCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
00498 
00499 /*! @brief Set the FR field to a new value. */
00500 #define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register I2S_TCSR, field BCE[28] (RW)
00505  *
00506  * Enables the transmit bit clock, separately from the TE. This field is
00507  * automatically set whenever TE is set. When software clears this field, the transmit
00508  * bit clock remains enabled, and this bit remains set, until the end of the
00509  * current frame.
00510  *
00511  * Values:
00512  * - 0 - Transmit bit clock is disabled.
00513  * - 1 - Transmit bit clock is enabled.
00514  */
00515 /*@{*/
00516 #define BP_I2S_TCSR_BCE      (28U)         /*!< Bit position for I2S_TCSR_BCE. */
00517 #define BM_I2S_TCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */
00518 #define BS_I2S_TCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_TCSR_BCE. */
00519 
00520 /*! @brief Read current value of the I2S_TCSR_BCE field. */
00521 #define BR_I2S_TCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
00522 
00523 /*! @brief Format value for bitfield I2S_TCSR_BCE. */
00524 #define BF_I2S_TCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
00525 
00526 /*! @brief Set the BCE field to a new value. */
00527 #define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
00528 /*@}*/
00529 
00530 /*!
00531  * @name Register I2S_TCSR, field DBGE[29] (RW)
00532  *
00533  * Enables/disables transmitter operation in Debug mode. The transmit bit clock
00534  * is not affected by debug mode.
00535  *
00536  * Values:
00537  * - 0 - Transmitter is disabled in Debug mode, after completing the current
00538  *     frame.
00539  * - 1 - Transmitter is enabled in Debug mode.
00540  */
00541 /*@{*/
00542 #define BP_I2S_TCSR_DBGE     (29U)         /*!< Bit position for I2S_TCSR_DBGE. */
00543 #define BM_I2S_TCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */
00544 #define BS_I2S_TCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_TCSR_DBGE. */
00545 
00546 /*! @brief Read current value of the I2S_TCSR_DBGE field. */
00547 #define BR_I2S_TCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
00548 
00549 /*! @brief Format value for bitfield I2S_TCSR_DBGE. */
00550 #define BF_I2S_TCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
00551 
00552 /*! @brief Set the DBGE field to a new value. */
00553 #define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
00554 /*@}*/
00555 
00556 /*!
00557  * @name Register I2S_TCSR, field STOPE[30] (RW)
00558  *
00559  * Configures transmitter operation in Stop mode. This field is ignored and the
00560  * transmitter is disabled in all low-leakage stop modes.
00561  *
00562  * Values:
00563  * - 0 - Transmitter disabled in Stop mode.
00564  * - 1 - Transmitter enabled in Stop mode.
00565  */
00566 /*@{*/
00567 #define BP_I2S_TCSR_STOPE    (30U)         /*!< Bit position for I2S_TCSR_STOPE. */
00568 #define BM_I2S_TCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */
00569 #define BS_I2S_TCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_TCSR_STOPE. */
00570 
00571 /*! @brief Read current value of the I2S_TCSR_STOPE field. */
00572 #define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
00573 
00574 /*! @brief Format value for bitfield I2S_TCSR_STOPE. */
00575 #define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
00576 
00577 /*! @brief Set the STOPE field to a new value. */
00578 #define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
00579 /*@}*/
00580 
00581 /*!
00582  * @name Register I2S_TCSR, field TE[31] (RW)
00583  *
00584  * Enables/disables the transmitter. When software clears this field, the
00585  * transmitter remains enabled, and this bit remains set, until the end of the current
00586  * frame.
00587  *
00588  * Values:
00589  * - 0 - Transmitter is disabled.
00590  * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
00591  *     yet reached end of frame.
00592  */
00593 /*@{*/
00594 #define BP_I2S_TCSR_TE       (31U)         /*!< Bit position for I2S_TCSR_TE. */
00595 #define BM_I2S_TCSR_TE       (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */
00596 #define BS_I2S_TCSR_TE       (1U)          /*!< Bit field size in bits for I2S_TCSR_TE. */
00597 
00598 /*! @brief Read current value of the I2S_TCSR_TE field. */
00599 #define BR_I2S_TCSR_TE(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
00600 
00601 /*! @brief Format value for bitfield I2S_TCSR_TE. */
00602 #define BF_I2S_TCSR_TE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
00603 
00604 /*! @brief Set the TE field to a new value. */
00605 #define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
00606 /*@}*/
00607 
00608 /*******************************************************************************
00609  * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
00610  ******************************************************************************/
00611 
00612 /*!
00613  * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
00614  *
00615  * Reset value: 0x00000000U
00616  */
00617 typedef union _hw_i2s_tcr1
00618 {
00619     uint32_t U;
00620     struct _hw_i2s_tcr1_bitfields
00621     {
00622         uint32_t TFW : 3;              /*!< [2:0] Transmit FIFO Watermark */
00623         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00624     } B;
00625 } hw_i2s_tcr1_t;
00626 
00627 /*!
00628  * @name Constants and macros for entire I2S_TCR1 register
00629  */
00630 /*@{*/
00631 #define HW_I2S_TCR1_ADDR(x)      ((x) + 0x4U)
00632 
00633 #define HW_I2S_TCR1(x)           (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
00634 #define HW_I2S_TCR1_RD(x)        (HW_I2S_TCR1(x).U)
00635 #define HW_I2S_TCR1_WR(x, v)     (HW_I2S_TCR1(x).U = (v))
00636 #define HW_I2S_TCR1_SET(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) |  (v)))
00637 #define HW_I2S_TCR1_CLR(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
00638 #define HW_I2S_TCR1_TOG(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^  (v)))
00639 /*@}*/
00640 
00641 /*
00642  * Constants & macros for individual I2S_TCR1 bitfields
00643  */
00644 
00645 /*!
00646  * @name Register I2S_TCR1, field TFW[2:0] (RW)
00647  *
00648  * Configures the watermark level for all enabled transmit channels.
00649  */
00650 /*@{*/
00651 #define BP_I2S_TCR1_TFW      (0U)          /*!< Bit position for I2S_TCR1_TFW. */
00652 #define BM_I2S_TCR1_TFW      (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */
00653 #define BS_I2S_TCR1_TFW      (3U)          /*!< Bit field size in bits for I2S_TCR1_TFW. */
00654 
00655 /*! @brief Read current value of the I2S_TCR1_TFW field. */
00656 #define BR_I2S_TCR1_TFW(x)   (HW_I2S_TCR1(x).B.TFW)
00657 
00658 /*! @brief Format value for bitfield I2S_TCR1_TFW. */
00659 #define BF_I2S_TCR1_TFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
00660 
00661 /*! @brief Set the TFW field to a new value. */
00662 #define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
00663 /*@}*/
00664 
00665 /*******************************************************************************
00666  * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
00667  ******************************************************************************/
00668 
00669 /*!
00670  * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
00671  *
00672  * Reset value: 0x00000000U
00673  *
00674  * This register must not be altered when TCSR[TE] is set.
00675  */
00676 typedef union _hw_i2s_tcr2
00677 {
00678     uint32_t U;
00679     struct _hw_i2s_tcr2_bitfields
00680     {
00681         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
00682         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
00683         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
00684         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
00685         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
00686         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
00687         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
00688         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
00689     } B;
00690 } hw_i2s_tcr2_t;
00691 
00692 /*!
00693  * @name Constants and macros for entire I2S_TCR2 register
00694  */
00695 /*@{*/
00696 #define HW_I2S_TCR2_ADDR(x)      ((x) + 0x8U)
00697 
00698 #define HW_I2S_TCR2(x)           (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
00699 #define HW_I2S_TCR2_RD(x)        (HW_I2S_TCR2(x).U)
00700 #define HW_I2S_TCR2_WR(x, v)     (HW_I2S_TCR2(x).U = (v))
00701 #define HW_I2S_TCR2_SET(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) |  (v)))
00702 #define HW_I2S_TCR2_CLR(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
00703 #define HW_I2S_TCR2_TOG(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^  (v)))
00704 /*@}*/
00705 
00706 /*
00707  * Constants & macros for individual I2S_TCR2 bitfields
00708  */
00709 
00710 /*!
00711  * @name Register I2S_TCR2, field DIV[7:0] (RW)
00712  *
00713  * Divides down the audio master clock to generate the bit clock when configured
00714  * for an internal bit clock. The division value is (DIV + 1) * 2.
00715  */
00716 /*@{*/
00717 #define BP_I2S_TCR2_DIV      (0U)          /*!< Bit position for I2S_TCR2_DIV. */
00718 #define BM_I2S_TCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */
00719 #define BS_I2S_TCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_TCR2_DIV. */
00720 
00721 /*! @brief Read current value of the I2S_TCR2_DIV field. */
00722 #define BR_I2S_TCR2_DIV(x)   (HW_I2S_TCR2(x).B.DIV)
00723 
00724 /*! @brief Format value for bitfield I2S_TCR2_DIV. */
00725 #define BF_I2S_TCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
00726 
00727 /*! @brief Set the DIV field to a new value. */
00728 #define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
00729 /*@}*/
00730 
00731 /*!
00732  * @name Register I2S_TCR2, field BCD[24] (RW)
00733  *
00734  * Configures the direction of the bit clock.
00735  *
00736  * Values:
00737  * - 0 - Bit clock is generated externally in Slave mode.
00738  * - 1 - Bit clock is generated internally in Master mode.
00739  */
00740 /*@{*/
00741 #define BP_I2S_TCR2_BCD      (24U)         /*!< Bit position for I2S_TCR2_BCD. */
00742 #define BM_I2S_TCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */
00743 #define BS_I2S_TCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCD. */
00744 
00745 /*! @brief Read current value of the I2S_TCR2_BCD field. */
00746 #define BR_I2S_TCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
00747 
00748 /*! @brief Format value for bitfield I2S_TCR2_BCD. */
00749 #define BF_I2S_TCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
00750 
00751 /*! @brief Set the BCD field to a new value. */
00752 #define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
00753 /*@}*/
00754 
00755 /*!
00756  * @name Register I2S_TCR2, field BCP[25] (RW)
00757  *
00758  * Configures the polarity of the bit clock.
00759  *
00760  * Values:
00761  * - 0 - Bit clock is active high with drive outputs on rising edge and sample
00762  *     inputs on falling edge.
00763  * - 1 - Bit clock is active low with drive outputs on falling edge and sample
00764  *     inputs on rising edge.
00765  */
00766 /*@{*/
00767 #define BP_I2S_TCR2_BCP      (25U)         /*!< Bit position for I2S_TCR2_BCP. */
00768 #define BM_I2S_TCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */
00769 #define BS_I2S_TCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCP. */
00770 
00771 /*! @brief Read current value of the I2S_TCR2_BCP field. */
00772 #define BR_I2S_TCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
00773 
00774 /*! @brief Format value for bitfield I2S_TCR2_BCP. */
00775 #define BF_I2S_TCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
00776 
00777 /*! @brief Set the BCP field to a new value. */
00778 #define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
00779 /*@}*/
00780 
00781 /*!
00782  * @name Register I2S_TCR2, field MSEL[27:26] (RW)
00783  *
00784  * Selects the audio Master Clock option used to generate an internally
00785  * generated bit clock. This field has no effect when configured for an externally
00786  * generated bit clock. Depending on the device, some Master Clock options might not be
00787  * available. See the chip configuration details for the availability and
00788  * chip-specific meaning of each option.
00789  *
00790  * Values:
00791  * - 00 - Bus Clock selected.
00792  * - 01 - Master Clock (MCLK) 1 option selected.
00793  * - 10 - Master Clock (MCLK) 2 option selected.
00794  * - 11 - Master Clock (MCLK) 3 option selected.
00795  */
00796 /*@{*/
00797 #define BP_I2S_TCR2_MSEL     (26U)         /*!< Bit position for I2S_TCR2_MSEL. */
00798 #define BM_I2S_TCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */
00799 #define BS_I2S_TCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_TCR2_MSEL. */
00800 
00801 /*! @brief Read current value of the I2S_TCR2_MSEL field. */
00802 #define BR_I2S_TCR2_MSEL(x)  (HW_I2S_TCR2(x).B.MSEL)
00803 
00804 /*! @brief Format value for bitfield I2S_TCR2_MSEL. */
00805 #define BF_I2S_TCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
00806 
00807 /*! @brief Set the MSEL field to a new value. */
00808 #define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
00809 /*@}*/
00810 
00811 /*!
00812  * @name Register I2S_TCR2, field BCI[28] (RW)
00813  *
00814  * When this field is set and using an internally generated bit clock in either
00815  * synchronous or asynchronous mode, the bit clock actually used by the
00816  * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
00817  * input as if the clock was externally generated). This has the effect of
00818  * decreasing the data input setup time, but increasing the data output valid time. The
00819  * slave mode timing from the datasheet should be used for the transmitter when
00820  * this bit is set. In synchronous mode, this bit allows the transmitter to use
00821  * the slave mode timing from the datasheet, while the receiver uses the master
00822  * mode timing. This field has no effect when configured for an externally generated
00823  * bit clock or when synchronous to another SAI peripheral .
00824  *
00825  * Values:
00826  * - 0 - No effect.
00827  * - 1 - Internal logic is clocked as if bit clock was externally generated.
00828  */
00829 /*@{*/
00830 #define BP_I2S_TCR2_BCI      (28U)         /*!< Bit position for I2S_TCR2_BCI. */
00831 #define BM_I2S_TCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */
00832 #define BS_I2S_TCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCI. */
00833 
00834 /*! @brief Read current value of the I2S_TCR2_BCI field. */
00835 #define BR_I2S_TCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
00836 
00837 /*! @brief Format value for bitfield I2S_TCR2_BCI. */
00838 #define BF_I2S_TCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
00839 
00840 /*! @brief Set the BCI field to a new value. */
00841 #define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
00842 /*@}*/
00843 
00844 /*!
00845  * @name Register I2S_TCR2, field BCS[29] (RW)
00846  *
00847  * This field swaps the bit clock used by the transmitter. When the transmitter
00848  * is configured in asynchronous mode and this bit is set, the transmitter is
00849  * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
00850  * receiver to share the same bit clock, but the transmitter continues to use the
00851  * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
00852  * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
00853  * the same value. When both are set, the transmitter and receiver are both
00854  * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
00855  * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
00856  * peripheral.
00857  *
00858  * Values:
00859  * - 0 - Use the normal bit clock source.
00860  * - 1 - Swap the bit clock source.
00861  */
00862 /*@{*/
00863 #define BP_I2S_TCR2_BCS      (29U)         /*!< Bit position for I2S_TCR2_BCS. */
00864 #define BM_I2S_TCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */
00865 #define BS_I2S_TCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCS. */
00866 
00867 /*! @brief Read current value of the I2S_TCR2_BCS field. */
00868 #define BR_I2S_TCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
00869 
00870 /*! @brief Format value for bitfield I2S_TCR2_BCS. */
00871 #define BF_I2S_TCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
00872 
00873 /*! @brief Set the BCS field to a new value. */
00874 #define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
00875 /*@}*/
00876 
00877 /*!
00878  * @name Register I2S_TCR2, field SYNC[31:30] (RW)
00879  *
00880  * Configures between asynchronous and synchronous modes of operation. When
00881  * configured for a synchronous mode of operation, the receiver or other SAI
00882  * peripheral must be configured for asynchronous operation.
00883  *
00884  * Values:
00885  * - 00 - Asynchronous mode.
00886  * - 01 - Synchronous with receiver.
00887  * - 10 - Synchronous with another SAI transmitter.
00888  * - 11 - Synchronous with another SAI receiver.
00889  */
00890 /*@{*/
00891 #define BP_I2S_TCR2_SYNC     (30U)         /*!< Bit position for I2S_TCR2_SYNC. */
00892 #define BM_I2S_TCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */
00893 #define BS_I2S_TCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_TCR2_SYNC. */
00894 
00895 /*! @brief Read current value of the I2S_TCR2_SYNC field. */
00896 #define BR_I2S_TCR2_SYNC(x)  (HW_I2S_TCR2(x).B.SYNC)
00897 
00898 /*! @brief Format value for bitfield I2S_TCR2_SYNC. */
00899 #define BF_I2S_TCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
00900 
00901 /*! @brief Set the SYNC field to a new value. */
00902 #define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
00903 /*@}*/
00904 
00905 /*******************************************************************************
00906  * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
00907  ******************************************************************************/
00908 
00909 /*!
00910  * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
00911  *
00912  * Reset value: 0x00000000U
00913  *
00914  * This register must not be altered when TCSR[TE] is set.
00915  */
00916 typedef union _hw_i2s_tcr3
00917 {
00918     uint32_t U;
00919     struct _hw_i2s_tcr3_bitfields
00920     {
00921         uint32_t WDFL : 5;             /*!< [4:0] Word Flag Configuration */
00922         uint32_t RESERVED0 : 11;       /*!< [15:5]  */
00923         uint32_t TCE : 2;              /*!< [17:16] Transmit Channel Enable */
00924         uint32_t RESERVED1 : 14;       /*!< [31:18]  */
00925     } B;
00926 } hw_i2s_tcr3_t;
00927 
00928 /*!
00929  * @name Constants and macros for entire I2S_TCR3 register
00930  */
00931 /*@{*/
00932 #define HW_I2S_TCR3_ADDR(x)      ((x) + 0xCU)
00933 
00934 #define HW_I2S_TCR3(x)           (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
00935 #define HW_I2S_TCR3_RD(x)        (HW_I2S_TCR3(x).U)
00936 #define HW_I2S_TCR3_WR(x, v)     (HW_I2S_TCR3(x).U = (v))
00937 #define HW_I2S_TCR3_SET(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) |  (v)))
00938 #define HW_I2S_TCR3_CLR(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
00939 #define HW_I2S_TCR3_TOG(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^  (v)))
00940 /*@}*/
00941 
00942 /*
00943  * Constants & macros for individual I2S_TCR3 bitfields
00944  */
00945 
00946 /*!
00947  * @name Register I2S_TCR3, field WDFL[4:0] (RW)
00948  *
00949  * Configures which word sets the start of word flag. The value written must be
00950  * one less than the word number. For example, writing 0 configures the first
00951  * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
00952  * start of word flag is never set.
00953  */
00954 /*@{*/
00955 #define BP_I2S_TCR3_WDFL     (0U)          /*!< Bit position for I2S_TCR3_WDFL. */
00956 #define BM_I2S_TCR3_WDFL     (0x0000001FU) /*!< Bit mask for I2S_TCR3_WDFL. */
00957 #define BS_I2S_TCR3_WDFL     (5U)          /*!< Bit field size in bits for I2S_TCR3_WDFL. */
00958 
00959 /*! @brief Read current value of the I2S_TCR3_WDFL field. */
00960 #define BR_I2S_TCR3_WDFL(x)  (HW_I2S_TCR3(x).B.WDFL)
00961 
00962 /*! @brief Format value for bitfield I2S_TCR3_WDFL. */
00963 #define BF_I2S_TCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
00964 
00965 /*! @brief Set the WDFL field to a new value. */
00966 #define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
00967 /*@}*/
00968 
00969 /*!
00970  * @name Register I2S_TCR3, field TCE[17:16] (RW)
00971  *
00972  * Enables the corresponding data channel for transmit operation. A channel must
00973  * be enabled before its FIFO is accessed.
00974  *
00975  * Values:
00976  * - 0 - Transmit data channel N is disabled.
00977  * - 1 - Transmit data channel N is enabled.
00978  */
00979 /*@{*/
00980 #define BP_I2S_TCR3_TCE      (16U)         /*!< Bit position for I2S_TCR3_TCE. */
00981 #define BM_I2S_TCR3_TCE      (0x00030000U) /*!< Bit mask for I2S_TCR3_TCE. */
00982 #define BS_I2S_TCR3_TCE      (2U)          /*!< Bit field size in bits for I2S_TCR3_TCE. */
00983 
00984 /*! @brief Read current value of the I2S_TCR3_TCE field. */
00985 #define BR_I2S_TCR3_TCE(x)   (HW_I2S_TCR3(x).B.TCE)
00986 
00987 /*! @brief Format value for bitfield I2S_TCR3_TCE. */
00988 #define BF_I2S_TCR3_TCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
00989 
00990 /*! @brief Set the TCE field to a new value. */
00991 #define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
00992 /*@}*/
00993 
00994 /*******************************************************************************
00995  * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
00996  ******************************************************************************/
00997 
00998 /*!
00999  * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
01000  *
01001  * Reset value: 0x00000000U
01002  *
01003  * This register must not be altered when TCSR[TE] is set.
01004  */
01005 typedef union _hw_i2s_tcr4
01006 {
01007     uint32_t U;
01008     struct _hw_i2s_tcr4_bitfields
01009     {
01010         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
01011         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
01012         uint32_t RESERVED0 : 1;        /*!< [2]  */
01013         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
01014         uint32_t MF : 1;               /*!< [4] MSB First */
01015         uint32_t RESERVED1 : 3;        /*!< [7:5]  */
01016         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
01017         uint32_t RESERVED2 : 3;        /*!< [15:13]  */
01018         uint32_t FRSZ : 5;             /*!< [20:16] Frame size */
01019         uint32_t RESERVED3 : 11;       /*!< [31:21]  */
01020     } B;
01021 } hw_i2s_tcr4_t;
01022 
01023 /*!
01024  * @name Constants and macros for entire I2S_TCR4 register
01025  */
01026 /*@{*/
01027 #define HW_I2S_TCR4_ADDR(x)      ((x) + 0x10U)
01028 
01029 #define HW_I2S_TCR4(x)           (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
01030 #define HW_I2S_TCR4_RD(x)        (HW_I2S_TCR4(x).U)
01031 #define HW_I2S_TCR4_WR(x, v)     (HW_I2S_TCR4(x).U = (v))
01032 #define HW_I2S_TCR4_SET(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) |  (v)))
01033 #define HW_I2S_TCR4_CLR(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
01034 #define HW_I2S_TCR4_TOG(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^  (v)))
01035 /*@}*/
01036 
01037 /*
01038  * Constants & macros for individual I2S_TCR4 bitfields
01039  */
01040 
01041 /*!
01042  * @name Register I2S_TCR4, field FSD[0] (RW)
01043  *
01044  * Configures the direction of the frame sync.
01045  *
01046  * Values:
01047  * - 0 - Frame sync is generated externally in Slave mode.
01048  * - 1 - Frame sync is generated internally in Master mode.
01049  */
01050 /*@{*/
01051 #define BP_I2S_TCR4_FSD      (0U)          /*!< Bit position for I2S_TCR4_FSD. */
01052 #define BM_I2S_TCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */
01053 #define BS_I2S_TCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSD. */
01054 
01055 /*! @brief Read current value of the I2S_TCR4_FSD field. */
01056 #define BR_I2S_TCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
01057 
01058 /*! @brief Format value for bitfield I2S_TCR4_FSD. */
01059 #define BF_I2S_TCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
01060 
01061 /*! @brief Set the FSD field to a new value. */
01062 #define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
01063 /*@}*/
01064 
01065 /*!
01066  * @name Register I2S_TCR4, field FSP[1] (RW)
01067  *
01068  * Configures the polarity of the frame sync.
01069  *
01070  * Values:
01071  * - 0 - Frame sync is active high.
01072  * - 1 - Frame sync is active low.
01073  */
01074 /*@{*/
01075 #define BP_I2S_TCR4_FSP      (1U)          /*!< Bit position for I2S_TCR4_FSP. */
01076 #define BM_I2S_TCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */
01077 #define BS_I2S_TCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSP. */
01078 
01079 /*! @brief Read current value of the I2S_TCR4_FSP field. */
01080 #define BR_I2S_TCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
01081 
01082 /*! @brief Format value for bitfield I2S_TCR4_FSP. */
01083 #define BF_I2S_TCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
01084 
01085 /*! @brief Set the FSP field to a new value. */
01086 #define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
01087 /*@}*/
01088 
01089 /*!
01090  * @name Register I2S_TCR4, field FSE[3] (RW)
01091  *
01092  * Values:
01093  * - 0 - Frame sync asserts with the first bit of the frame.
01094  * - 1 - Frame sync asserts one bit before the first bit of the frame.
01095  */
01096 /*@{*/
01097 #define BP_I2S_TCR4_FSE      (3U)          /*!< Bit position for I2S_TCR4_FSE. */
01098 #define BM_I2S_TCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */
01099 #define BS_I2S_TCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSE. */
01100 
01101 /*! @brief Read current value of the I2S_TCR4_FSE field. */
01102 #define BR_I2S_TCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
01103 
01104 /*! @brief Format value for bitfield I2S_TCR4_FSE. */
01105 #define BF_I2S_TCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
01106 
01107 /*! @brief Set the FSE field to a new value. */
01108 #define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
01109 /*@}*/
01110 
01111 /*!
01112  * @name Register I2S_TCR4, field MF[4] (RW)
01113  *
01114  * Configures whether the LSB or the MSB is transmitted first.
01115  *
01116  * Values:
01117  * - 0 - LSB is transmitted first.
01118  * - 1 - MSB is transmitted first.
01119  */
01120 /*@{*/
01121 #define BP_I2S_TCR4_MF       (4U)          /*!< Bit position for I2S_TCR4_MF. */
01122 #define BM_I2S_TCR4_MF       (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */
01123 #define BS_I2S_TCR4_MF       (1U)          /*!< Bit field size in bits for I2S_TCR4_MF. */
01124 
01125 /*! @brief Read current value of the I2S_TCR4_MF field. */
01126 #define BR_I2S_TCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
01127 
01128 /*! @brief Format value for bitfield I2S_TCR4_MF. */
01129 #define BF_I2S_TCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
01130 
01131 /*! @brief Set the MF field to a new value. */
01132 #define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
01133 /*@}*/
01134 
01135 /*!
01136  * @name Register I2S_TCR4, field SYWD[12:8] (RW)
01137  *
01138  * Configures the length of the frame sync in number of bit clocks. The value
01139  * written must be one less than the number of bit clocks. For example, write 0 for
01140  * the frame sync to assert for one bit clock only. The sync width cannot be
01141  * configured longer than the first word of the frame.
01142  */
01143 /*@{*/
01144 #define BP_I2S_TCR4_SYWD     (8U)          /*!< Bit position for I2S_TCR4_SYWD. */
01145 #define BM_I2S_TCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */
01146 #define BS_I2S_TCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_TCR4_SYWD. */
01147 
01148 /*! @brief Read current value of the I2S_TCR4_SYWD field. */
01149 #define BR_I2S_TCR4_SYWD(x)  (HW_I2S_TCR4(x).B.SYWD)
01150 
01151 /*! @brief Format value for bitfield I2S_TCR4_SYWD. */
01152 #define BF_I2S_TCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
01153 
01154 /*! @brief Set the SYWD field to a new value. */
01155 #define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
01156 /*@}*/
01157 
01158 /*!
01159  * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
01160  *
01161  * Configures the number of words in each frame. The value written must be one
01162  * less than the number of words in the frame. For example, write 0 for one word
01163  * per frame. The maximum supported frame size is 32 words.
01164  */
01165 /*@{*/
01166 #define BP_I2S_TCR4_FRSZ     (16U)         /*!< Bit position for I2S_TCR4_FRSZ. */
01167 #define BM_I2S_TCR4_FRSZ     (0x001F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */
01168 #define BS_I2S_TCR4_FRSZ     (5U)          /*!< Bit field size in bits for I2S_TCR4_FRSZ. */
01169 
01170 /*! @brief Read current value of the I2S_TCR4_FRSZ field. */
01171 #define BR_I2S_TCR4_FRSZ(x)  (HW_I2S_TCR4(x).B.FRSZ)
01172 
01173 /*! @brief Format value for bitfield I2S_TCR4_FRSZ. */
01174 #define BF_I2S_TCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
01175 
01176 /*! @brief Set the FRSZ field to a new value. */
01177 #define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
01178 /*@}*/
01179 
01180 /*******************************************************************************
01181  * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
01182  ******************************************************************************/
01183 
01184 /*!
01185  * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
01186  *
01187  * Reset value: 0x00000000U
01188  *
01189  * This register must not be altered when TCSR[TE] is set.
01190  */
01191 typedef union _hw_i2s_tcr5
01192 {
01193     uint32_t U;
01194     struct _hw_i2s_tcr5_bitfields
01195     {
01196         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
01197         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
01198         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
01199         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
01200         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
01201         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
01202         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
01203     } B;
01204 } hw_i2s_tcr5_t;
01205 
01206 /*!
01207  * @name Constants and macros for entire I2S_TCR5 register
01208  */
01209 /*@{*/
01210 #define HW_I2S_TCR5_ADDR(x)      ((x) + 0x14U)
01211 
01212 #define HW_I2S_TCR5(x)           (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
01213 #define HW_I2S_TCR5_RD(x)        (HW_I2S_TCR5(x).U)
01214 #define HW_I2S_TCR5_WR(x, v)     (HW_I2S_TCR5(x).U = (v))
01215 #define HW_I2S_TCR5_SET(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) |  (v)))
01216 #define HW_I2S_TCR5_CLR(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
01217 #define HW_I2S_TCR5_TOG(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^  (v)))
01218 /*@}*/
01219 
01220 /*
01221  * Constants & macros for individual I2S_TCR5 bitfields
01222  */
01223 
01224 /*!
01225  * @name Register I2S_TCR5, field FBT[12:8] (RW)
01226  *
01227  * Configures the bit index for the first bit transmitted for each word in the
01228  * frame. If configured for MSB First, the index of the next bit transmitted is
01229  * one less than the current bit transmitted. If configured for LSB First, the
01230  * index of the next bit transmitted is one more than the current bit transmitted.
01231  * The value written must be greater than or equal to the word width when
01232  * configured for MSB First. The value written must be less than or equal to 31-word width
01233  * when configured for LSB First.
01234  */
01235 /*@{*/
01236 #define BP_I2S_TCR5_FBT      (8U)          /*!< Bit position for I2S_TCR5_FBT. */
01237 #define BM_I2S_TCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */
01238 #define BS_I2S_TCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_TCR5_FBT. */
01239 
01240 /*! @brief Read current value of the I2S_TCR5_FBT field. */
01241 #define BR_I2S_TCR5_FBT(x)   (HW_I2S_TCR5(x).B.FBT)
01242 
01243 /*! @brief Format value for bitfield I2S_TCR5_FBT. */
01244 #define BF_I2S_TCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
01245 
01246 /*! @brief Set the FBT field to a new value. */
01247 #define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
01248 /*@}*/
01249 
01250 /*!
01251  * @name Register I2S_TCR5, field W0W[20:16] (RW)
01252  *
01253  * Configures the number of bits in the first word in each frame. The value
01254  * written must be one less than the number of bits in the first word. Word width of
01255  * less than 8 bits is not supported if there is only one word per frame.
01256  */
01257 /*@{*/
01258 #define BP_I2S_TCR5_W0W      (16U)         /*!< Bit position for I2S_TCR5_W0W. */
01259 #define BM_I2S_TCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */
01260 #define BS_I2S_TCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_TCR5_W0W. */
01261 
01262 /*! @brief Read current value of the I2S_TCR5_W0W field. */
01263 #define BR_I2S_TCR5_W0W(x)   (HW_I2S_TCR5(x).B.W0W)
01264 
01265 /*! @brief Format value for bitfield I2S_TCR5_W0W. */
01266 #define BF_I2S_TCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
01267 
01268 /*! @brief Set the W0W field to a new value. */
01269 #define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
01270 /*@}*/
01271 
01272 /*!
01273  * @name Register I2S_TCR5, field WNW[28:24] (RW)
01274  *
01275  * Configures the number of bits in each word, for each word except the first in
01276  * the frame. The value written must be one less than the number of bits per
01277  * word. Word width of less than 8 bits is not supported.
01278  */
01279 /*@{*/
01280 #define BP_I2S_TCR5_WNW      (24U)         /*!< Bit position for I2S_TCR5_WNW. */
01281 #define BM_I2S_TCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */
01282 #define BS_I2S_TCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_TCR5_WNW. */
01283 
01284 /*! @brief Read current value of the I2S_TCR5_WNW field. */
01285 #define BR_I2S_TCR5_WNW(x)   (HW_I2S_TCR5(x).B.WNW)
01286 
01287 /*! @brief Format value for bitfield I2S_TCR5_WNW. */
01288 #define BF_I2S_TCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
01289 
01290 /*! @brief Set the WNW field to a new value. */
01291 #define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
01292 /*@}*/
01293 
01294 /*******************************************************************************
01295  * HW_I2S_TDRn - SAI Transmit Data Register
01296  ******************************************************************************/
01297 
01298 /*!
01299  * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
01300  *
01301  * Reset value: 0x00000000U
01302  */
01303 typedef union _hw_i2s_tdrn
01304 {
01305     uint32_t U;
01306     struct _hw_i2s_tdrn_bitfields
01307     {
01308         uint32_t TDR : 32;             /*!< [31:0] Transmit Data Register */
01309     } B;
01310 } hw_i2s_tdrn_t;
01311 
01312 /*!
01313  * @name Constants and macros for entire I2S_TDRn register
01314  */
01315 /*@{*/
01316 #define HW_I2S_TDRn_COUNT (2U)
01317 
01318 #define HW_I2S_TDRn_ADDR(x, n)   ((x) + 0x20U + (0x4U * (n)))
01319 
01320 #define HW_I2S_TDRn(x, n)        (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
01321 #define HW_I2S_TDRn_RD(x, n)     (HW_I2S_TDRn(x, n).U)
01322 #define HW_I2S_TDRn_WR(x, n, v)  (HW_I2S_TDRn(x, n).U = (v))
01323 /*@}*/
01324 
01325 /*
01326  * Constants & macros for individual I2S_TDRn bitfields
01327  */
01328 
01329 /*!
01330  * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
01331  *
01332  * The corresponding TCR3[TCE] bit must be set before accessing the channel's
01333  * transmit data register. Writes to this register when the transmit FIFO is not
01334  * full will push the data written into the transmit data FIFO. Writes to this
01335  * register when the transmit FIFO is full are ignored.
01336  */
01337 /*@{*/
01338 #define BP_I2S_TDRn_TDR      (0U)          /*!< Bit position for I2S_TDRn_TDR. */
01339 #define BM_I2S_TDRn_TDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */
01340 #define BS_I2S_TDRn_TDR      (32U)         /*!< Bit field size in bits for I2S_TDRn_TDR. */
01341 
01342 /*! @brief Format value for bitfield I2S_TDRn_TDR. */
01343 #define BF_I2S_TDRn_TDR(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
01344 
01345 /*! @brief Set the TDR field to a new value. */
01346 #define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
01347 /*@}*/
01348 
01349 /*******************************************************************************
01350  * HW_I2S_TFRn - SAI Transmit FIFO Register
01351  ******************************************************************************/
01352 
01353 /*!
01354  * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
01355  *
01356  * Reset value: 0x00000000U
01357  *
01358  * The MSB of the read and write pointers is used to distinguish between FIFO
01359  * full and empty conditions. If the read and write pointers are identical, then
01360  * the FIFO is empty. If the read and write pointers are identical except for the
01361  * MSB, then the FIFO is full.
01362  */
01363 typedef union _hw_i2s_tfrn
01364 {
01365     uint32_t U;
01366     struct _hw_i2s_tfrn_bitfields
01367     {
01368         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
01369         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
01370         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
01371         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
01372     } B;
01373 } hw_i2s_tfrn_t;
01374 
01375 /*!
01376  * @name Constants and macros for entire I2S_TFRn register
01377  */
01378 /*@{*/
01379 #define HW_I2S_TFRn_COUNT (2U)
01380 
01381 #define HW_I2S_TFRn_ADDR(x, n)   ((x) + 0x40U + (0x4U * (n)))
01382 
01383 #define HW_I2S_TFRn(x, n)        (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
01384 #define HW_I2S_TFRn_RD(x, n)     (HW_I2S_TFRn(x, n).U)
01385 /*@}*/
01386 
01387 /*
01388  * Constants & macros for individual I2S_TFRn bitfields
01389  */
01390 
01391 /*!
01392  * @name Register I2S_TFRn, field RFP[3:0] (RO)
01393  *
01394  * FIFO read pointer for transmit data channel.
01395  */
01396 /*@{*/
01397 #define BP_I2S_TFRn_RFP      (0U)          /*!< Bit position for I2S_TFRn_RFP. */
01398 #define BM_I2S_TFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */
01399 #define BS_I2S_TFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_RFP. */
01400 
01401 /*! @brief Read current value of the I2S_TFRn_RFP field. */
01402 #define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
01403 /*@}*/
01404 
01405 /*!
01406  * @name Register I2S_TFRn, field WFP[19:16] (RO)
01407  *
01408  * FIFO write pointer for transmit data channel.
01409  */
01410 /*@{*/
01411 #define BP_I2S_TFRn_WFP      (16U)         /*!< Bit position for I2S_TFRn_WFP. */
01412 #define BM_I2S_TFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */
01413 #define BS_I2S_TFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_WFP. */
01414 
01415 /*! @brief Read current value of the I2S_TFRn_WFP field. */
01416 #define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
01417 /*@}*/
01418 
01419 /*******************************************************************************
01420  * HW_I2S_TMR - SAI Transmit Mask Register
01421  ******************************************************************************/
01422 
01423 /*!
01424  * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
01425  *
01426  * Reset value: 0x00000000U
01427  *
01428  * This register is double-buffered and updates: When TCSR[TE] is first set At
01429  * the end of each frame. This allows the masked words in each frame to change
01430  * from frame to frame.
01431  */
01432 typedef union _hw_i2s_tmr
01433 {
01434     uint32_t U;
01435     struct _hw_i2s_tmr_bitfields
01436     {
01437         uint32_t TWM : 32;             /*!< [31:0] Transmit Word Mask */
01438     } B;
01439 } hw_i2s_tmr_t;
01440 
01441 /*!
01442  * @name Constants and macros for entire I2S_TMR register
01443  */
01444 /*@{*/
01445 #define HW_I2S_TMR_ADDR(x)       ((x) + 0x60U)
01446 
01447 #define HW_I2S_TMR(x)            (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
01448 #define HW_I2S_TMR_RD(x)         (HW_I2S_TMR(x).U)
01449 #define HW_I2S_TMR_WR(x, v)      (HW_I2S_TMR(x).U = (v))
01450 #define HW_I2S_TMR_SET(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) |  (v)))
01451 #define HW_I2S_TMR_CLR(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
01452 #define HW_I2S_TMR_TOG(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^  (v)))
01453 /*@}*/
01454 
01455 /*
01456  * Constants & macros for individual I2S_TMR bitfields
01457  */
01458 
01459 /*!
01460  * @name Register I2S_TMR, field TWM[31:0] (RW)
01461  *
01462  * Configures whether the transmit word is masked (transmit data pin tristated
01463  * and transmit data not read from FIFO) for the corresponding word in the frame.
01464  *
01465  * Values:
01466  * - 0 - Word N is enabled.
01467  * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
01468  */
01469 /*@{*/
01470 #define BP_I2S_TMR_TWM       (0U)          /*!< Bit position for I2S_TMR_TWM. */
01471 #define BM_I2S_TMR_TWM       (0xFFFFFFFFU) /*!< Bit mask for I2S_TMR_TWM. */
01472 #define BS_I2S_TMR_TWM       (32U)         /*!< Bit field size in bits for I2S_TMR_TWM. */
01473 
01474 /*! @brief Read current value of the I2S_TMR_TWM field. */
01475 #define BR_I2S_TMR_TWM(x)    (HW_I2S_TMR(x).U)
01476 
01477 /*! @brief Format value for bitfield I2S_TMR_TWM. */
01478 #define BF_I2S_TMR_TWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
01479 
01480 /*! @brief Set the TWM field to a new value. */
01481 #define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
01482 /*@}*/
01483 
01484 /*******************************************************************************
01485  * HW_I2S_RCSR - SAI Receive Control Register
01486  ******************************************************************************/
01487 
01488 /*!
01489  * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
01490  *
01491  * Reset value: 0x00000000U
01492  */
01493 typedef union _hw_i2s_rcsr
01494 {
01495     uint32_t U;
01496     struct _hw_i2s_rcsr_bitfields
01497     {
01498         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
01499         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
01500         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
01501         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
01502         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
01503         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
01504         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
01505         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
01506         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
01507         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
01508         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
01509         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
01510         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
01511         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
01512         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
01513         uint32_t SR : 1;               /*!< [24] Software Reset */
01514         uint32_t FR : 1;               /*!< [25] FIFO Reset */
01515         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
01516         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
01517         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
01518         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
01519         uint32_t RE : 1;               /*!< [31] Receiver Enable */
01520     } B;
01521 } hw_i2s_rcsr_t;
01522 
01523 /*!
01524  * @name Constants and macros for entire I2S_RCSR register
01525  */
01526 /*@{*/
01527 #define HW_I2S_RCSR_ADDR(x)      ((x) + 0x80U)
01528 
01529 #define HW_I2S_RCSR(x)           (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
01530 #define HW_I2S_RCSR_RD(x)        (HW_I2S_RCSR(x).U)
01531 #define HW_I2S_RCSR_WR(x, v)     (HW_I2S_RCSR(x).U = (v))
01532 #define HW_I2S_RCSR_SET(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) |  (v)))
01533 #define HW_I2S_RCSR_CLR(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
01534 #define HW_I2S_RCSR_TOG(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^  (v)))
01535 /*@}*/
01536 
01537 /*
01538  * Constants & macros for individual I2S_RCSR bitfields
01539  */
01540 
01541 /*!
01542  * @name Register I2S_RCSR, field FRDE[0] (RW)
01543  *
01544  * Enables/disables DMA requests.
01545  *
01546  * Values:
01547  * - 0 - Disables the DMA request.
01548  * - 1 - Enables the DMA request.
01549  */
01550 /*@{*/
01551 #define BP_I2S_RCSR_FRDE     (0U)          /*!< Bit position for I2S_RCSR_FRDE. */
01552 #define BM_I2S_RCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */
01553 #define BS_I2S_RCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRDE. */
01554 
01555 /*! @brief Read current value of the I2S_RCSR_FRDE field. */
01556 #define BR_I2S_RCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
01557 
01558 /*! @brief Format value for bitfield I2S_RCSR_FRDE. */
01559 #define BF_I2S_RCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
01560 
01561 /*! @brief Set the FRDE field to a new value. */
01562 #define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
01563 /*@}*/
01564 
01565 /*!
01566  * @name Register I2S_RCSR, field FWDE[1] (RW)
01567  *
01568  * Enables/disables DMA requests.
01569  *
01570  * Values:
01571  * - 0 - Disables the DMA request.
01572  * - 1 - Enables the DMA request.
01573  */
01574 /*@{*/
01575 #define BP_I2S_RCSR_FWDE     (1U)          /*!< Bit position for I2S_RCSR_FWDE. */
01576 #define BM_I2S_RCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */
01577 #define BS_I2S_RCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWDE. */
01578 
01579 /*! @brief Read current value of the I2S_RCSR_FWDE field. */
01580 #define BR_I2S_RCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
01581 
01582 /*! @brief Format value for bitfield I2S_RCSR_FWDE. */
01583 #define BF_I2S_RCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
01584 
01585 /*! @brief Set the FWDE field to a new value. */
01586 #define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
01587 /*@}*/
01588 
01589 /*!
01590  * @name Register I2S_RCSR, field FRIE[8] (RW)
01591  *
01592  * Enables/disables FIFO request interrupts.
01593  *
01594  * Values:
01595  * - 0 - Disables the interrupt.
01596  * - 1 - Enables the interrupt.
01597  */
01598 /*@{*/
01599 #define BP_I2S_RCSR_FRIE     (8U)          /*!< Bit position for I2S_RCSR_FRIE. */
01600 #define BM_I2S_RCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */
01601 #define BS_I2S_RCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRIE. */
01602 
01603 /*! @brief Read current value of the I2S_RCSR_FRIE field. */
01604 #define BR_I2S_RCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
01605 
01606 /*! @brief Format value for bitfield I2S_RCSR_FRIE. */
01607 #define BF_I2S_RCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
01608 
01609 /*! @brief Set the FRIE field to a new value. */
01610 #define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
01611 /*@}*/
01612 
01613 /*!
01614  * @name Register I2S_RCSR, field FWIE[9] (RW)
01615  *
01616  * Enables/disables FIFO warning interrupts.
01617  *
01618  * Values:
01619  * - 0 - Disables the interrupt.
01620  * - 1 - Enables the interrupt.
01621  */
01622 /*@{*/
01623 #define BP_I2S_RCSR_FWIE     (9U)          /*!< Bit position for I2S_RCSR_FWIE. */
01624 #define BM_I2S_RCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */
01625 #define BS_I2S_RCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWIE. */
01626 
01627 /*! @brief Read current value of the I2S_RCSR_FWIE field. */
01628 #define BR_I2S_RCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
01629 
01630 /*! @brief Format value for bitfield I2S_RCSR_FWIE. */
01631 #define BF_I2S_RCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
01632 
01633 /*! @brief Set the FWIE field to a new value. */
01634 #define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
01635 /*@}*/
01636 
01637 /*!
01638  * @name Register I2S_RCSR, field FEIE[10] (RW)
01639  *
01640  * Enables/disables FIFO error interrupts.
01641  *
01642  * Values:
01643  * - 0 - Disables the interrupt.
01644  * - 1 - Enables the interrupt.
01645  */
01646 /*@{*/
01647 #define BP_I2S_RCSR_FEIE     (10U)         /*!< Bit position for I2S_RCSR_FEIE. */
01648 #define BM_I2S_RCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */
01649 #define BS_I2S_RCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FEIE. */
01650 
01651 /*! @brief Read current value of the I2S_RCSR_FEIE field. */
01652 #define BR_I2S_RCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
01653 
01654 /*! @brief Format value for bitfield I2S_RCSR_FEIE. */
01655 #define BF_I2S_RCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
01656 
01657 /*! @brief Set the FEIE field to a new value. */
01658 #define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
01659 /*@}*/
01660 
01661 /*!
01662  * @name Register I2S_RCSR, field SEIE[11] (RW)
01663  *
01664  * Enables/disables sync error interrupts.
01665  *
01666  * Values:
01667  * - 0 - Disables interrupt.
01668  * - 1 - Enables interrupt.
01669  */
01670 /*@{*/
01671 #define BP_I2S_RCSR_SEIE     (11U)         /*!< Bit position for I2S_RCSR_SEIE. */
01672 #define BM_I2S_RCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */
01673 #define BS_I2S_RCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_SEIE. */
01674 
01675 /*! @brief Read current value of the I2S_RCSR_SEIE field. */
01676 #define BR_I2S_RCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
01677 
01678 /*! @brief Format value for bitfield I2S_RCSR_SEIE. */
01679 #define BF_I2S_RCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
01680 
01681 /*! @brief Set the SEIE field to a new value. */
01682 #define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
01683 /*@}*/
01684 
01685 /*!
01686  * @name Register I2S_RCSR, field WSIE[12] (RW)
01687  *
01688  * Enables/disables word start interrupts.
01689  *
01690  * Values:
01691  * - 0 - Disables interrupt.
01692  * - 1 - Enables interrupt.
01693  */
01694 /*@{*/
01695 #define BP_I2S_RCSR_WSIE     (12U)         /*!< Bit position for I2S_RCSR_WSIE. */
01696 #define BM_I2S_RCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */
01697 #define BS_I2S_RCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_WSIE. */
01698 
01699 /*! @brief Read current value of the I2S_RCSR_WSIE field. */
01700 #define BR_I2S_RCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
01701 
01702 /*! @brief Format value for bitfield I2S_RCSR_WSIE. */
01703 #define BF_I2S_RCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
01704 
01705 /*! @brief Set the WSIE field to a new value. */
01706 #define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
01707 /*@}*/
01708 
01709 /*!
01710  * @name Register I2S_RCSR, field FRF[16] (RO)
01711  *
01712  * Indicates that the number of words in an enabled receive channel FIFO is
01713  * greater than the receive FIFO watermark.
01714  *
01715  * Values:
01716  * - 0 - Receive FIFO watermark not reached.
01717  * - 1 - Receive FIFO watermark has been reached.
01718  */
01719 /*@{*/
01720 #define BP_I2S_RCSR_FRF      (16U)         /*!< Bit position for I2S_RCSR_FRF. */
01721 #define BM_I2S_RCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */
01722 #define BS_I2S_RCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FRF. */
01723 
01724 /*! @brief Read current value of the I2S_RCSR_FRF field. */
01725 #define BR_I2S_RCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
01726 /*@}*/
01727 
01728 /*!
01729  * @name Register I2S_RCSR, field FWF[17] (RO)
01730  *
01731  * Indicates that an enabled receive FIFO is full.
01732  *
01733  * Values:
01734  * - 0 - No enabled receive FIFO is full.
01735  * - 1 - Enabled receive FIFO is full.
01736  */
01737 /*@{*/
01738 #define BP_I2S_RCSR_FWF      (17U)         /*!< Bit position for I2S_RCSR_FWF. */
01739 #define BM_I2S_RCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */
01740 #define BS_I2S_RCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FWF. */
01741 
01742 /*! @brief Read current value of the I2S_RCSR_FWF field. */
01743 #define BR_I2S_RCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
01744 /*@}*/
01745 
01746 /*!
01747  * @name Register I2S_RCSR, field FEF[18] (W1C)
01748  *
01749  * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
01750  * this field to clear this flag.
01751  *
01752  * Values:
01753  * - 0 - Receive overflow not detected.
01754  * - 1 - Receive overflow detected.
01755  */
01756 /*@{*/
01757 #define BP_I2S_RCSR_FEF      (18U)         /*!< Bit position for I2S_RCSR_FEF. */
01758 #define BM_I2S_RCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */
01759 #define BS_I2S_RCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FEF. */
01760 
01761 /*! @brief Read current value of the I2S_RCSR_FEF field. */
01762 #define BR_I2S_RCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
01763 
01764 /*! @brief Format value for bitfield I2S_RCSR_FEF. */
01765 #define BF_I2S_RCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
01766 
01767 /*! @brief Set the FEF field to a new value. */
01768 #define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
01769 /*@}*/
01770 
01771 /*!
01772  * @name Register I2S_RCSR, field SEF[19] (W1C)
01773  *
01774  * Indicates that an error in the externally-generated frame sync has been
01775  * detected. Write a logic 1 to this field to clear this flag.
01776  *
01777  * Values:
01778  * - 0 - Sync error not detected.
01779  * - 1 - Frame sync error detected.
01780  */
01781 /*@{*/
01782 #define BP_I2S_RCSR_SEF      (19U)         /*!< Bit position for I2S_RCSR_SEF. */
01783 #define BM_I2S_RCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */
01784 #define BS_I2S_RCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_SEF. */
01785 
01786 /*! @brief Read current value of the I2S_RCSR_SEF field. */
01787 #define BR_I2S_RCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
01788 
01789 /*! @brief Format value for bitfield I2S_RCSR_SEF. */
01790 #define BF_I2S_RCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
01791 
01792 /*! @brief Set the SEF field to a new value. */
01793 #define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
01794 /*@}*/
01795 
01796 /*!
01797  * @name Register I2S_RCSR, field WSF[20] (W1C)
01798  *
01799  * Indicates that the start of the configured word has been detected. Write a
01800  * logic 1 to this field to clear this flag.
01801  *
01802  * Values:
01803  * - 0 - Start of word not detected.
01804  * - 1 - Start of word detected.
01805  */
01806 /*@{*/
01807 #define BP_I2S_RCSR_WSF      (20U)         /*!< Bit position for I2S_RCSR_WSF. */
01808 #define BM_I2S_RCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */
01809 #define BS_I2S_RCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_RCSR_WSF. */
01810 
01811 /*! @brief Read current value of the I2S_RCSR_WSF field. */
01812 #define BR_I2S_RCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
01813 
01814 /*! @brief Format value for bitfield I2S_RCSR_WSF. */
01815 #define BF_I2S_RCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
01816 
01817 /*! @brief Set the WSF field to a new value. */
01818 #define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
01819 /*@}*/
01820 
01821 /*!
01822  * @name Register I2S_RCSR, field SR[24] (RW)
01823  *
01824  * Resets the internal receiver logic including the FIFO pointers.
01825  * Software-visible registers are not affected, except for the status registers.
01826  *
01827  * Values:
01828  * - 0 - No effect.
01829  * - 1 - Software reset.
01830  */
01831 /*@{*/
01832 #define BP_I2S_RCSR_SR       (24U)         /*!< Bit position for I2S_RCSR_SR. */
01833 #define BM_I2S_RCSR_SR       (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */
01834 #define BS_I2S_RCSR_SR       (1U)          /*!< Bit field size in bits for I2S_RCSR_SR. */
01835 
01836 /*! @brief Read current value of the I2S_RCSR_SR field. */
01837 #define BR_I2S_RCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
01838 
01839 /*! @brief Format value for bitfield I2S_RCSR_SR. */
01840 #define BF_I2S_RCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
01841 
01842 /*! @brief Set the SR field to a new value. */
01843 #define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
01844 /*@}*/
01845 
01846 /*!
01847  * @name Register I2S_RCSR, field FR[25] (WORZ)
01848  *
01849  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
01850  * pointers should only be reset when the receiver is disabled or the FIFO error
01851  * flag is set.
01852  *
01853  * Values:
01854  * - 0 - No effect.
01855  * - 1 - FIFO reset.
01856  */
01857 /*@{*/
01858 #define BP_I2S_RCSR_FR       (25U)         /*!< Bit position for I2S_RCSR_FR. */
01859 #define BM_I2S_RCSR_FR       (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */
01860 #define BS_I2S_RCSR_FR       (1U)          /*!< Bit field size in bits for I2S_RCSR_FR. */
01861 
01862 /*! @brief Format value for bitfield I2S_RCSR_FR. */
01863 #define BF_I2S_RCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
01864 
01865 /*! @brief Set the FR field to a new value. */
01866 #define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
01867 /*@}*/
01868 
01869 /*!
01870  * @name Register I2S_RCSR, field BCE[28] (RW)
01871  *
01872  * Enables the receive bit clock, separately from RE. This field is
01873  * automatically set whenever RE is set. When software clears this field, the receive bit
01874  * clock remains enabled, and this field remains set, until the end of the current
01875  * frame.
01876  *
01877  * Values:
01878  * - 0 - Receive bit clock is disabled.
01879  * - 1 - Receive bit clock is enabled.
01880  */
01881 /*@{*/
01882 #define BP_I2S_RCSR_BCE      (28U)         /*!< Bit position for I2S_RCSR_BCE. */
01883 #define BM_I2S_RCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */
01884 #define BS_I2S_RCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_RCSR_BCE. */
01885 
01886 /*! @brief Read current value of the I2S_RCSR_BCE field. */
01887 #define BR_I2S_RCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
01888 
01889 /*! @brief Format value for bitfield I2S_RCSR_BCE. */
01890 #define BF_I2S_RCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
01891 
01892 /*! @brief Set the BCE field to a new value. */
01893 #define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
01894 /*@}*/
01895 
01896 /*!
01897  * @name Register I2S_RCSR, field DBGE[29] (RW)
01898  *
01899  * Enables/disables receiver operation in Debug mode. The receive bit clock is
01900  * not affected by Debug mode.
01901  *
01902  * Values:
01903  * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
01904  * - 1 - Receiver is enabled in Debug mode.
01905  */
01906 /*@{*/
01907 #define BP_I2S_RCSR_DBGE     (29U)         /*!< Bit position for I2S_RCSR_DBGE. */
01908 #define BM_I2S_RCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */
01909 #define BS_I2S_RCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_RCSR_DBGE. */
01910 
01911 /*! @brief Read current value of the I2S_RCSR_DBGE field. */
01912 #define BR_I2S_RCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
01913 
01914 /*! @brief Format value for bitfield I2S_RCSR_DBGE. */
01915 #define BF_I2S_RCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
01916 
01917 /*! @brief Set the DBGE field to a new value. */
01918 #define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
01919 /*@}*/
01920 
01921 /*!
01922  * @name Register I2S_RCSR, field STOPE[30] (RW)
01923  *
01924  * Configures receiver operation in Stop mode. This bit is ignored and the
01925  * receiver is disabled in all low-leakage stop modes.
01926  *
01927  * Values:
01928  * - 0 - Receiver disabled in Stop mode.
01929  * - 1 - Receiver enabled in Stop mode.
01930  */
01931 /*@{*/
01932 #define BP_I2S_RCSR_STOPE    (30U)         /*!< Bit position for I2S_RCSR_STOPE. */
01933 #define BM_I2S_RCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */
01934 #define BS_I2S_RCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_RCSR_STOPE. */
01935 
01936 /*! @brief Read current value of the I2S_RCSR_STOPE field. */
01937 #define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
01938 
01939 /*! @brief Format value for bitfield I2S_RCSR_STOPE. */
01940 #define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
01941 
01942 /*! @brief Set the STOPE field to a new value. */
01943 #define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
01944 /*@}*/
01945 
01946 /*!
01947  * @name Register I2S_RCSR, field RE[31] (RW)
01948  *
01949  * Enables/disables the receiver. When software clears this field, the receiver
01950  * remains enabled, and this bit remains set, until the end of the current frame.
01951  *
01952  * Values:
01953  * - 0 - Receiver is disabled.
01954  * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
01955  *     reached end of frame.
01956  */
01957 /*@{*/
01958 #define BP_I2S_RCSR_RE       (31U)         /*!< Bit position for I2S_RCSR_RE. */
01959 #define BM_I2S_RCSR_RE       (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */
01960 #define BS_I2S_RCSR_RE       (1U)          /*!< Bit field size in bits for I2S_RCSR_RE. */
01961 
01962 /*! @brief Read current value of the I2S_RCSR_RE field. */
01963 #define BR_I2S_RCSR_RE(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
01964 
01965 /*! @brief Format value for bitfield I2S_RCSR_RE. */
01966 #define BF_I2S_RCSR_RE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
01967 
01968 /*! @brief Set the RE field to a new value. */
01969 #define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
01970 /*@}*/
01971 
01972 /*******************************************************************************
01973  * HW_I2S_RCR1 - SAI Receive Configuration 1 Register
01974  ******************************************************************************/
01975 
01976 /*!
01977  * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
01978  *
01979  * Reset value: 0x00000000U
01980  */
01981 typedef union _hw_i2s_rcr1
01982 {
01983     uint32_t U;
01984     struct _hw_i2s_rcr1_bitfields
01985     {
01986         uint32_t RFW : 3;              /*!< [2:0] Receive FIFO Watermark */
01987         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
01988     } B;
01989 } hw_i2s_rcr1_t;
01990 
01991 /*!
01992  * @name Constants and macros for entire I2S_RCR1 register
01993  */
01994 /*@{*/
01995 #define HW_I2S_RCR1_ADDR(x)      ((x) + 0x84U)
01996 
01997 #define HW_I2S_RCR1(x)           (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
01998 #define HW_I2S_RCR1_RD(x)        (HW_I2S_RCR1(x).U)
01999 #define HW_I2S_RCR1_WR(x, v)     (HW_I2S_RCR1(x).U = (v))
02000 #define HW_I2S_RCR1_SET(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) |  (v)))
02001 #define HW_I2S_RCR1_CLR(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
02002 #define HW_I2S_RCR1_TOG(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^  (v)))
02003 /*@}*/
02004 
02005 /*
02006  * Constants & macros for individual I2S_RCR1 bitfields
02007  */
02008 
02009 /*!
02010  * @name Register I2S_RCR1, field RFW[2:0] (RW)
02011  *
02012  * Configures the watermark level for all enabled receiver channels.
02013  */
02014 /*@{*/
02015 #define BP_I2S_RCR1_RFW      (0U)          /*!< Bit position for I2S_RCR1_RFW. */
02016 #define BM_I2S_RCR1_RFW      (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */
02017 #define BS_I2S_RCR1_RFW      (3U)          /*!< Bit field size in bits for I2S_RCR1_RFW. */
02018 
02019 /*! @brief Read current value of the I2S_RCR1_RFW field. */
02020 #define BR_I2S_RCR1_RFW(x)   (HW_I2S_RCR1(x).B.RFW)
02021 
02022 /*! @brief Format value for bitfield I2S_RCR1_RFW. */
02023 #define BF_I2S_RCR1_RFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
02024 
02025 /*! @brief Set the RFW field to a new value. */
02026 #define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
02027 /*@}*/
02028 
02029 /*******************************************************************************
02030  * HW_I2S_RCR2 - SAI Receive Configuration 2 Register
02031  ******************************************************************************/
02032 
02033 /*!
02034  * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
02035  *
02036  * Reset value: 0x00000000U
02037  *
02038  * This register must not be altered when RCSR[RE] is set.
02039  */
02040 typedef union _hw_i2s_rcr2
02041 {
02042     uint32_t U;
02043     struct _hw_i2s_rcr2_bitfields
02044     {
02045         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
02046         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
02047         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
02048         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
02049         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
02050         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
02051         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
02052         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
02053     } B;
02054 } hw_i2s_rcr2_t;
02055 
02056 /*!
02057  * @name Constants and macros for entire I2S_RCR2 register
02058  */
02059 /*@{*/
02060 #define HW_I2S_RCR2_ADDR(x)      ((x) + 0x88U)
02061 
02062 #define HW_I2S_RCR2(x)           (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
02063 #define HW_I2S_RCR2_RD(x)        (HW_I2S_RCR2(x).U)
02064 #define HW_I2S_RCR2_WR(x, v)     (HW_I2S_RCR2(x).U = (v))
02065 #define HW_I2S_RCR2_SET(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) |  (v)))
02066 #define HW_I2S_RCR2_CLR(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
02067 #define HW_I2S_RCR2_TOG(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^  (v)))
02068 /*@}*/
02069 
02070 /*
02071  * Constants & macros for individual I2S_RCR2 bitfields
02072  */
02073 
02074 /*!
02075  * @name Register I2S_RCR2, field DIV[7:0] (RW)
02076  *
02077  * Divides down the audio master clock to generate the bit clock when configured
02078  * for an internal bit clock. The division value is (DIV + 1) * 2.
02079  */
02080 /*@{*/
02081 #define BP_I2S_RCR2_DIV      (0U)          /*!< Bit position for I2S_RCR2_DIV. */
02082 #define BM_I2S_RCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */
02083 #define BS_I2S_RCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_RCR2_DIV. */
02084 
02085 /*! @brief Read current value of the I2S_RCR2_DIV field. */
02086 #define BR_I2S_RCR2_DIV(x)   (HW_I2S_RCR2(x).B.DIV)
02087 
02088 /*! @brief Format value for bitfield I2S_RCR2_DIV. */
02089 #define BF_I2S_RCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
02090 
02091 /*! @brief Set the DIV field to a new value. */
02092 #define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
02093 /*@}*/
02094 
02095 /*!
02096  * @name Register I2S_RCR2, field BCD[24] (RW)
02097  *
02098  * Configures the direction of the bit clock.
02099  *
02100  * Values:
02101  * - 0 - Bit clock is generated externally in Slave mode.
02102  * - 1 - Bit clock is generated internally in Master mode.
02103  */
02104 /*@{*/
02105 #define BP_I2S_RCR2_BCD      (24U)         /*!< Bit position for I2S_RCR2_BCD. */
02106 #define BM_I2S_RCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */
02107 #define BS_I2S_RCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCD. */
02108 
02109 /*! @brief Read current value of the I2S_RCR2_BCD field. */
02110 #define BR_I2S_RCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
02111 
02112 /*! @brief Format value for bitfield I2S_RCR2_BCD. */
02113 #define BF_I2S_RCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
02114 
02115 /*! @brief Set the BCD field to a new value. */
02116 #define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
02117 /*@}*/
02118 
02119 /*!
02120  * @name Register I2S_RCR2, field BCP[25] (RW)
02121  *
02122  * Configures the polarity of the bit clock.
02123  *
02124  * Values:
02125  * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
02126  *     inputs on falling edge.
02127  * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
02128  *     inputs on rising edge.
02129  */
02130 /*@{*/
02131 #define BP_I2S_RCR2_BCP      (25U)         /*!< Bit position for I2S_RCR2_BCP. */
02132 #define BM_I2S_RCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */
02133 #define BS_I2S_RCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCP. */
02134 
02135 /*! @brief Read current value of the I2S_RCR2_BCP field. */
02136 #define BR_I2S_RCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
02137 
02138 /*! @brief Format value for bitfield I2S_RCR2_BCP. */
02139 #define BF_I2S_RCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
02140 
02141 /*! @brief Set the BCP field to a new value. */
02142 #define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
02143 /*@}*/
02144 
02145 /*!
02146  * @name Register I2S_RCR2, field MSEL[27:26] (RW)
02147  *
02148  * Selects the audio Master Clock option used to generate an internally
02149  * generated bit clock. This field has no effect when configured for an externally
02150  * generated bit clock. Depending on the device, some Master Clock options might not be
02151  * available. See the chip configuration details for the availability and
02152  * chip-specific meaning of each option.
02153  *
02154  * Values:
02155  * - 00 - Bus Clock selected.
02156  * - 01 - Master Clock (MCLK) 1 option selected.
02157  * - 10 - Master Clock (MCLK) 2 option selected.
02158  * - 11 - Master Clock (MCLK) 3 option selected.
02159  */
02160 /*@{*/
02161 #define BP_I2S_RCR2_MSEL     (26U)         /*!< Bit position for I2S_RCR2_MSEL. */
02162 #define BM_I2S_RCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */
02163 #define BS_I2S_RCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_RCR2_MSEL. */
02164 
02165 /*! @brief Read current value of the I2S_RCR2_MSEL field. */
02166 #define BR_I2S_RCR2_MSEL(x)  (HW_I2S_RCR2(x).B.MSEL)
02167 
02168 /*! @brief Format value for bitfield I2S_RCR2_MSEL. */
02169 #define BF_I2S_RCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
02170 
02171 /*! @brief Set the MSEL field to a new value. */
02172 #define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
02173 /*@}*/
02174 
02175 /*!
02176  * @name Register I2S_RCR2, field BCI[28] (RW)
02177  *
02178  * When this field is set and using an internally generated bit clock in either
02179  * synchronous or asynchronous mode, the bit clock actually used by the receiver
02180  * is delayed by the pad output delay (the receiver is clocked by the pad input
02181  * as if the clock was externally generated). This has the effect of decreasing
02182  * the data input setup time, but increasing the data output valid time. The slave
02183  * mode timing from the datasheet should be used for the receiver when this bit
02184  * is set. In synchronous mode, this bit allows the receiver to use the slave mode
02185  * timing from the datasheet, while the transmitter uses the master mode timing.
02186  * This field has no effect when configured for an externally generated bit
02187  * clock or when synchronous to another SAI peripheral .
02188  *
02189  * Values:
02190  * - 0 - No effect.
02191  * - 1 - Internal logic is clocked as if bit clock was externally generated.
02192  */
02193 /*@{*/
02194 #define BP_I2S_RCR2_BCI      (28U)         /*!< Bit position for I2S_RCR2_BCI. */
02195 #define BM_I2S_RCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */
02196 #define BS_I2S_RCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCI. */
02197 
02198 /*! @brief Read current value of the I2S_RCR2_BCI field. */
02199 #define BR_I2S_RCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
02200 
02201 /*! @brief Format value for bitfield I2S_RCR2_BCI. */
02202 #define BF_I2S_RCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
02203 
02204 /*! @brief Set the BCI field to a new value. */
02205 #define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
02206 /*@}*/
02207 
02208 /*!
02209  * @name Register I2S_RCR2, field BCS[29] (RW)
02210  *
02211  * This field swaps the bit clock used by the receiver. When the receiver is
02212  * configured in asynchronous mode and this bit is set, the receiver is clocked by
02213  * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
02214  * receiver to share the same bit clock, but the receiver continues to use the receiver
02215  * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
02216  * mode, the transmitter BCS field and receiver BCS field must be set to the same
02217  * value. When both are set, the transmitter and receiver are both clocked by the
02218  * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
02219  * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
02220  *
02221  * Values:
02222  * - 0 - Use the normal bit clock source.
02223  * - 1 - Swap the bit clock source.
02224  */
02225 /*@{*/
02226 #define BP_I2S_RCR2_BCS      (29U)         /*!< Bit position for I2S_RCR2_BCS. */
02227 #define BM_I2S_RCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */
02228 #define BS_I2S_RCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCS. */
02229 
02230 /*! @brief Read current value of the I2S_RCR2_BCS field. */
02231 #define BR_I2S_RCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
02232 
02233 /*! @brief Format value for bitfield I2S_RCR2_BCS. */
02234 #define BF_I2S_RCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
02235 
02236 /*! @brief Set the BCS field to a new value. */
02237 #define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
02238 /*@}*/
02239 
02240 /*!
02241  * @name Register I2S_RCR2, field SYNC[31:30] (RW)
02242  *
02243  * Configures between asynchronous and synchronous modes of operation. When
02244  * configured for a synchronous mode of operation, the transmitter or other SAI
02245  * peripheral must be configured for asynchronous operation.
02246  *
02247  * Values:
02248  * - 00 - Asynchronous mode.
02249  * - 01 - Synchronous with transmitter.
02250  * - 10 - Synchronous with another SAI receiver.
02251  * - 11 - Synchronous with another SAI transmitter.
02252  */
02253 /*@{*/
02254 #define BP_I2S_RCR2_SYNC     (30U)         /*!< Bit position for I2S_RCR2_SYNC. */
02255 #define BM_I2S_RCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */
02256 #define BS_I2S_RCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_RCR2_SYNC. */
02257 
02258 /*! @brief Read current value of the I2S_RCR2_SYNC field. */
02259 #define BR_I2S_RCR2_SYNC(x)  (HW_I2S_RCR2(x).B.SYNC)
02260 
02261 /*! @brief Format value for bitfield I2S_RCR2_SYNC. */
02262 #define BF_I2S_RCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
02263 
02264 /*! @brief Set the SYNC field to a new value. */
02265 #define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
02266 /*@}*/
02267 
02268 /*******************************************************************************
02269  * HW_I2S_RCR3 - SAI Receive Configuration 3 Register
02270  ******************************************************************************/
02271 
02272 /*!
02273  * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
02274  *
02275  * Reset value: 0x00000000U
02276  *
02277  * This register must not be altered when RCSR[RE] is set.
02278  */
02279 typedef union _hw_i2s_rcr3
02280 {
02281     uint32_t U;
02282     struct _hw_i2s_rcr3_bitfields
02283     {
02284         uint32_t WDFL : 5;             /*!< [4:0] Word Flag Configuration */
02285         uint32_t RESERVED0 : 11;       /*!< [15:5]  */
02286         uint32_t RCE : 2;              /*!< [17:16] Receive Channel Enable */
02287         uint32_t RESERVED1 : 14;       /*!< [31:18]  */
02288     } B;
02289 } hw_i2s_rcr3_t;
02290 
02291 /*!
02292  * @name Constants and macros for entire I2S_RCR3 register
02293  */
02294 /*@{*/
02295 #define HW_I2S_RCR3_ADDR(x)      ((x) + 0x8CU)
02296 
02297 #define HW_I2S_RCR3(x)           (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
02298 #define HW_I2S_RCR3_RD(x)        (HW_I2S_RCR3(x).U)
02299 #define HW_I2S_RCR3_WR(x, v)     (HW_I2S_RCR3(x).U = (v))
02300 #define HW_I2S_RCR3_SET(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) |  (v)))
02301 #define HW_I2S_RCR3_CLR(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
02302 #define HW_I2S_RCR3_TOG(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^  (v)))
02303 /*@}*/
02304 
02305 /*
02306  * Constants & macros for individual I2S_RCR3 bitfields
02307  */
02308 
02309 /*!
02310  * @name Register I2S_RCR3, field WDFL[4:0] (RW)
02311  *
02312  * Configures which word the start of word flag is set. The value written should
02313  * be one less than the word number (for example, write zero to configure for
02314  * the first word in the frame). When configured to a value greater than the Frame
02315  * Size field, then the start of word flag is never set.
02316  */
02317 /*@{*/
02318 #define BP_I2S_RCR3_WDFL     (0U)          /*!< Bit position for I2S_RCR3_WDFL. */
02319 #define BM_I2S_RCR3_WDFL     (0x0000001FU) /*!< Bit mask for I2S_RCR3_WDFL. */
02320 #define BS_I2S_RCR3_WDFL     (5U)          /*!< Bit field size in bits for I2S_RCR3_WDFL. */
02321 
02322 /*! @brief Read current value of the I2S_RCR3_WDFL field. */
02323 #define BR_I2S_RCR3_WDFL(x)  (HW_I2S_RCR3(x).B.WDFL)
02324 
02325 /*! @brief Format value for bitfield I2S_RCR3_WDFL. */
02326 #define BF_I2S_RCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
02327 
02328 /*! @brief Set the WDFL field to a new value. */
02329 #define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
02330 /*@}*/
02331 
02332 /*!
02333  * @name Register I2S_RCR3, field RCE[17:16] (RW)
02334  *
02335  * Enables the corresponding data channel for receive operation. A channel must
02336  * be enabled before its FIFO is accessed.
02337  *
02338  * Values:
02339  * - 0 - Receive data channel N is disabled.
02340  * - 1 - Receive data channel N is enabled.
02341  */
02342 /*@{*/
02343 #define BP_I2S_RCR3_RCE      (16U)         /*!< Bit position for I2S_RCR3_RCE. */
02344 #define BM_I2S_RCR3_RCE      (0x00030000U) /*!< Bit mask for I2S_RCR3_RCE. */
02345 #define BS_I2S_RCR3_RCE      (2U)          /*!< Bit field size in bits for I2S_RCR3_RCE. */
02346 
02347 /*! @brief Read current value of the I2S_RCR3_RCE field. */
02348 #define BR_I2S_RCR3_RCE(x)   (HW_I2S_RCR3(x).B.RCE)
02349 
02350 /*! @brief Format value for bitfield I2S_RCR3_RCE. */
02351 #define BF_I2S_RCR3_RCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
02352 
02353 /*! @brief Set the RCE field to a new value. */
02354 #define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
02355 /*@}*/
02356 
02357 /*******************************************************************************
02358  * HW_I2S_RCR4 - SAI Receive Configuration 4 Register
02359  ******************************************************************************/
02360 
02361 /*!
02362  * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
02363  *
02364  * Reset value: 0x00000000U
02365  *
02366  * This register must not be altered when RCSR[RE] is set.
02367  */
02368 typedef union _hw_i2s_rcr4
02369 {
02370     uint32_t U;
02371     struct _hw_i2s_rcr4_bitfields
02372     {
02373         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
02374         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
02375         uint32_t RESERVED0 : 1;        /*!< [2]  */
02376         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
02377         uint32_t MF : 1;               /*!< [4] MSB First */
02378         uint32_t RESERVED1 : 3;        /*!< [7:5]  */
02379         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
02380         uint32_t RESERVED2 : 3;        /*!< [15:13]  */
02381         uint32_t FRSZ : 5;             /*!< [20:16] Frame Size */
02382         uint32_t RESERVED3 : 11;       /*!< [31:21]  */
02383     } B;
02384 } hw_i2s_rcr4_t;
02385 
02386 /*!
02387  * @name Constants and macros for entire I2S_RCR4 register
02388  */
02389 /*@{*/
02390 #define HW_I2S_RCR4_ADDR(x)      ((x) + 0x90U)
02391 
02392 #define HW_I2S_RCR4(x)           (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
02393 #define HW_I2S_RCR4_RD(x)        (HW_I2S_RCR4(x).U)
02394 #define HW_I2S_RCR4_WR(x, v)     (HW_I2S_RCR4(x).U = (v))
02395 #define HW_I2S_RCR4_SET(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) |  (v)))
02396 #define HW_I2S_RCR4_CLR(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
02397 #define HW_I2S_RCR4_TOG(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^  (v)))
02398 /*@}*/
02399 
02400 /*
02401  * Constants & macros for individual I2S_RCR4 bitfields
02402  */
02403 
02404 /*!
02405  * @name Register I2S_RCR4, field FSD[0] (RW)
02406  *
02407  * Configures the direction of the frame sync.
02408  *
02409  * Values:
02410  * - 0 - Frame Sync is generated externally in Slave mode.
02411  * - 1 - Frame Sync is generated internally in Master mode.
02412  */
02413 /*@{*/
02414 #define BP_I2S_RCR4_FSD      (0U)          /*!< Bit position for I2S_RCR4_FSD. */
02415 #define BM_I2S_RCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */
02416 #define BS_I2S_RCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSD. */
02417 
02418 /*! @brief Read current value of the I2S_RCR4_FSD field. */
02419 #define BR_I2S_RCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
02420 
02421 /*! @brief Format value for bitfield I2S_RCR4_FSD. */
02422 #define BF_I2S_RCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
02423 
02424 /*! @brief Set the FSD field to a new value. */
02425 #define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
02426 /*@}*/
02427 
02428 /*!
02429  * @name Register I2S_RCR4, field FSP[1] (RW)
02430  *
02431  * Configures the polarity of the frame sync.
02432  *
02433  * Values:
02434  * - 0 - Frame sync is active high.
02435  * - 1 - Frame sync is active low.
02436  */
02437 /*@{*/
02438 #define BP_I2S_RCR4_FSP      (1U)          /*!< Bit position for I2S_RCR4_FSP. */
02439 #define BM_I2S_RCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */
02440 #define BS_I2S_RCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSP. */
02441 
02442 /*! @brief Read current value of the I2S_RCR4_FSP field. */
02443 #define BR_I2S_RCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
02444 
02445 /*! @brief Format value for bitfield I2S_RCR4_FSP. */
02446 #define BF_I2S_RCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
02447 
02448 /*! @brief Set the FSP field to a new value. */
02449 #define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
02450 /*@}*/
02451 
02452 /*!
02453  * @name Register I2S_RCR4, field FSE[3] (RW)
02454  *
02455  * Values:
02456  * - 0 - Frame sync asserts with the first bit of the frame.
02457  * - 1 - Frame sync asserts one bit before the first bit of the frame.
02458  */
02459 /*@{*/
02460 #define BP_I2S_RCR4_FSE      (3U)          /*!< Bit position for I2S_RCR4_FSE. */
02461 #define BM_I2S_RCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */
02462 #define BS_I2S_RCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSE. */
02463 
02464 /*! @brief Read current value of the I2S_RCR4_FSE field. */
02465 #define BR_I2S_RCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
02466 
02467 /*! @brief Format value for bitfield I2S_RCR4_FSE. */
02468 #define BF_I2S_RCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
02469 
02470 /*! @brief Set the FSE field to a new value. */
02471 #define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
02472 /*@}*/
02473 
02474 /*!
02475  * @name Register I2S_RCR4, field MF[4] (RW)
02476  *
02477  * Configures whether the LSB or the MSB is received first.
02478  *
02479  * Values:
02480  * - 0 - LSB is received first.
02481  * - 1 - MSB is received first.
02482  */
02483 /*@{*/
02484 #define BP_I2S_RCR4_MF       (4U)          /*!< Bit position for I2S_RCR4_MF. */
02485 #define BM_I2S_RCR4_MF       (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */
02486 #define BS_I2S_RCR4_MF       (1U)          /*!< Bit field size in bits for I2S_RCR4_MF. */
02487 
02488 /*! @brief Read current value of the I2S_RCR4_MF field. */
02489 #define BR_I2S_RCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
02490 
02491 /*! @brief Format value for bitfield I2S_RCR4_MF. */
02492 #define BF_I2S_RCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
02493 
02494 /*! @brief Set the MF field to a new value. */
02495 #define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
02496 /*@}*/
02497 
02498 /*!
02499  * @name Register I2S_RCR4, field SYWD[12:8] (RW)
02500  *
02501  * Configures the length of the frame sync in number of bit clocks. The value
02502  * written must be one less than the number of bit clocks. For example, write 0 for
02503  * the frame sync to assert for one bit clock only. The sync width cannot be
02504  * configured longer than the first word of the frame.
02505  */
02506 /*@{*/
02507 #define BP_I2S_RCR4_SYWD     (8U)          /*!< Bit position for I2S_RCR4_SYWD. */
02508 #define BM_I2S_RCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */
02509 #define BS_I2S_RCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_RCR4_SYWD. */
02510 
02511 /*! @brief Read current value of the I2S_RCR4_SYWD field. */
02512 #define BR_I2S_RCR4_SYWD(x)  (HW_I2S_RCR4(x).B.SYWD)
02513 
02514 /*! @brief Format value for bitfield I2S_RCR4_SYWD. */
02515 #define BF_I2S_RCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
02516 
02517 /*! @brief Set the SYWD field to a new value. */
02518 #define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
02519 /*@}*/
02520 
02521 /*!
02522  * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
02523  *
02524  * Configures the number of words in each frame. The value written must be one
02525  * less than the number of words in the frame. For example, write 0 for one word
02526  * per frame. The maximum supported frame size is 32 words.
02527  */
02528 /*@{*/
02529 #define BP_I2S_RCR4_FRSZ     (16U)         /*!< Bit position for I2S_RCR4_FRSZ. */
02530 #define BM_I2S_RCR4_FRSZ     (0x001F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */
02531 #define BS_I2S_RCR4_FRSZ     (5U)          /*!< Bit field size in bits for I2S_RCR4_FRSZ. */
02532 
02533 /*! @brief Read current value of the I2S_RCR4_FRSZ field. */
02534 #define BR_I2S_RCR4_FRSZ(x)  (HW_I2S_RCR4(x).B.FRSZ)
02535 
02536 /*! @brief Format value for bitfield I2S_RCR4_FRSZ. */
02537 #define BF_I2S_RCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
02538 
02539 /*! @brief Set the FRSZ field to a new value. */
02540 #define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
02541 /*@}*/
02542 
02543 /*******************************************************************************
02544  * HW_I2S_RCR5 - SAI Receive Configuration 5 Register
02545  ******************************************************************************/
02546 
02547 /*!
02548  * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
02549  *
02550  * Reset value: 0x00000000U
02551  *
02552  * This register must not be altered when RCSR[RE] is set.
02553  */
02554 typedef union _hw_i2s_rcr5
02555 {
02556     uint32_t U;
02557     struct _hw_i2s_rcr5_bitfields
02558     {
02559         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
02560         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
02561         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
02562         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
02563         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
02564         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
02565         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02566     } B;
02567 } hw_i2s_rcr5_t;
02568 
02569 /*!
02570  * @name Constants and macros for entire I2S_RCR5 register
02571  */
02572 /*@{*/
02573 #define HW_I2S_RCR5_ADDR(x)      ((x) + 0x94U)
02574 
02575 #define HW_I2S_RCR5(x)           (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
02576 #define HW_I2S_RCR5_RD(x)        (HW_I2S_RCR5(x).U)
02577 #define HW_I2S_RCR5_WR(x, v)     (HW_I2S_RCR5(x).U = (v))
02578 #define HW_I2S_RCR5_SET(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) |  (v)))
02579 #define HW_I2S_RCR5_CLR(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
02580 #define HW_I2S_RCR5_TOG(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^  (v)))
02581 /*@}*/
02582 
02583 /*
02584  * Constants & macros for individual I2S_RCR5 bitfields
02585  */
02586 
02587 /*!
02588  * @name Register I2S_RCR5, field FBT[12:8] (RW)
02589  *
02590  * Configures the bit index for the first bit received for each word in the
02591  * frame. If configured for MSB First, the index of the next bit received is one less
02592  * than the current bit received. If configured for LSB First, the index of the
02593  * next bit received is one more than the current bit received. The value written
02594  * must be greater than or equal to the word width when configured for MSB
02595  * First. The value written must be less than or equal to 31-word width when
02596  * configured for LSB First.
02597  */
02598 /*@{*/
02599 #define BP_I2S_RCR5_FBT      (8U)          /*!< Bit position for I2S_RCR5_FBT. */
02600 #define BM_I2S_RCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */
02601 #define BS_I2S_RCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_RCR5_FBT. */
02602 
02603 /*! @brief Read current value of the I2S_RCR5_FBT field. */
02604 #define BR_I2S_RCR5_FBT(x)   (HW_I2S_RCR5(x).B.FBT)
02605 
02606 /*! @brief Format value for bitfield I2S_RCR5_FBT. */
02607 #define BF_I2S_RCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
02608 
02609 /*! @brief Set the FBT field to a new value. */
02610 #define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
02611 /*@}*/
02612 
02613 /*!
02614  * @name Register I2S_RCR5, field W0W[20:16] (RW)
02615  *
02616  * Configures the number of bits in the first word in each frame. The value
02617  * written must be one less than the number of bits in the first word. Word width of
02618  * less than 8 bits is not supported if there is only one word per frame.
02619  */
02620 /*@{*/
02621 #define BP_I2S_RCR5_W0W      (16U)         /*!< Bit position for I2S_RCR5_W0W. */
02622 #define BM_I2S_RCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */
02623 #define BS_I2S_RCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_RCR5_W0W. */
02624 
02625 /*! @brief Read current value of the I2S_RCR5_W0W field. */
02626 #define BR_I2S_RCR5_W0W(x)   (HW_I2S_RCR5(x).B.W0W)
02627 
02628 /*! @brief Format value for bitfield I2S_RCR5_W0W. */
02629 #define BF_I2S_RCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
02630 
02631 /*! @brief Set the W0W field to a new value. */
02632 #define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
02633 /*@}*/
02634 
02635 /*!
02636  * @name Register I2S_RCR5, field WNW[28:24] (RW)
02637  *
02638  * Configures the number of bits in each word, for each word except the first in
02639  * the frame. The value written must be one less than the number of bits per
02640  * word. Word width of less than 8 bits is not supported.
02641  */
02642 /*@{*/
02643 #define BP_I2S_RCR5_WNW      (24U)         /*!< Bit position for I2S_RCR5_WNW. */
02644 #define BM_I2S_RCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */
02645 #define BS_I2S_RCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_RCR5_WNW. */
02646 
02647 /*! @brief Read current value of the I2S_RCR5_WNW field. */
02648 #define BR_I2S_RCR5_WNW(x)   (HW_I2S_RCR5(x).B.WNW)
02649 
02650 /*! @brief Format value for bitfield I2S_RCR5_WNW. */
02651 #define BF_I2S_RCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
02652 
02653 /*! @brief Set the WNW field to a new value. */
02654 #define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
02655 /*@}*/
02656 
02657 /*******************************************************************************
02658  * HW_I2S_RDRn - SAI Receive Data Register
02659  ******************************************************************************/
02660 
02661 /*!
02662  * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
02663  *
02664  * Reset value: 0x00000000U
02665  *
02666  * Reading this register introduces one additional peripheral clock wait state
02667  * on each read.
02668  */
02669 typedef union _hw_i2s_rdrn
02670 {
02671     uint32_t U;
02672     struct _hw_i2s_rdrn_bitfields
02673     {
02674         uint32_t RDR : 32;             /*!< [31:0] Receive Data Register */
02675     } B;
02676 } hw_i2s_rdrn_t;
02677 
02678 /*!
02679  * @name Constants and macros for entire I2S_RDRn register
02680  */
02681 /*@{*/
02682 #define HW_I2S_RDRn_COUNT (2U)
02683 
02684 #define HW_I2S_RDRn_ADDR(x, n)   ((x) + 0xA0U + (0x4U * (n)))
02685 
02686 #define HW_I2S_RDRn(x, n)        (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
02687 #define HW_I2S_RDRn_RD(x, n)     (HW_I2S_RDRn(x, n).U)
02688 /*@}*/
02689 
02690 /*
02691  * Constants & macros for individual I2S_RDRn bitfields
02692  */
02693 
02694 /*!
02695  * @name Register I2S_RDRn, field RDR[31:0] (RO)
02696  *
02697  * The corresponding RCR3[RCE] bit must be set before accessing the channel's
02698  * receive data register. Reads from this register when the receive FIFO is not
02699  * empty will return the data from the top of the receive FIFO. Reads from this
02700  * register when the receive FIFO is empty are ignored.
02701  */
02702 /*@{*/
02703 #define BP_I2S_RDRn_RDR      (0U)          /*!< Bit position for I2S_RDRn_RDR. */
02704 #define BM_I2S_RDRn_RDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */
02705 #define BS_I2S_RDRn_RDR      (32U)         /*!< Bit field size in bits for I2S_RDRn_RDR. */
02706 
02707 /*! @brief Read current value of the I2S_RDRn_RDR field. */
02708 #define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
02709 /*@}*/
02710 
02711 /*******************************************************************************
02712  * HW_I2S_RFRn - SAI Receive FIFO Register
02713  ******************************************************************************/
02714 
02715 /*!
02716  * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
02717  *
02718  * Reset value: 0x00000000U
02719  *
02720  * The MSB of the read and write pointers is used to distinguish between FIFO
02721  * full and empty conditions. If the read and write pointers are identical, then
02722  * the FIFO is empty. If the read and write pointers are identical except for the
02723  * MSB, then the FIFO is full.
02724  */
02725 typedef union _hw_i2s_rfrn
02726 {
02727     uint32_t U;
02728     struct _hw_i2s_rfrn_bitfields
02729     {
02730         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
02731         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
02732         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
02733         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
02734     } B;
02735 } hw_i2s_rfrn_t;
02736 
02737 /*!
02738  * @name Constants and macros for entire I2S_RFRn register
02739  */
02740 /*@{*/
02741 #define HW_I2S_RFRn_COUNT (2U)
02742 
02743 #define HW_I2S_RFRn_ADDR(x, n)   ((x) + 0xC0U + (0x4U * (n)))
02744 
02745 #define HW_I2S_RFRn(x, n)        (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
02746 #define HW_I2S_RFRn_RD(x, n)     (HW_I2S_RFRn(x, n).U)
02747 /*@}*/
02748 
02749 /*
02750  * Constants & macros for individual I2S_RFRn bitfields
02751  */
02752 
02753 /*!
02754  * @name Register I2S_RFRn, field RFP[3:0] (RO)
02755  *
02756  * FIFO read pointer for receive data channel.
02757  */
02758 /*@{*/
02759 #define BP_I2S_RFRn_RFP      (0U)          /*!< Bit position for I2S_RFRn_RFP. */
02760 #define BM_I2S_RFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */
02761 #define BS_I2S_RFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_RFP. */
02762 
02763 /*! @brief Read current value of the I2S_RFRn_RFP field. */
02764 #define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
02765 /*@}*/
02766 
02767 /*!
02768  * @name Register I2S_RFRn, field WFP[19:16] (RO)
02769  *
02770  * FIFO write pointer for receive data channel.
02771  */
02772 /*@{*/
02773 #define BP_I2S_RFRn_WFP      (16U)         /*!< Bit position for I2S_RFRn_WFP. */
02774 #define BM_I2S_RFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */
02775 #define BS_I2S_RFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_WFP. */
02776 
02777 /*! @brief Read current value of the I2S_RFRn_WFP field. */
02778 #define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
02779 /*@}*/
02780 
02781 /*******************************************************************************
02782  * HW_I2S_RMR - SAI Receive Mask Register
02783  ******************************************************************************/
02784 
02785 /*!
02786  * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
02787  *
02788  * Reset value: 0x00000000U
02789  *
02790  * This register is double-buffered and updates: When RCSR[RE] is first set At
02791  * the end of each frame This allows the masked words in each frame to change from
02792  * frame to frame.
02793  */
02794 typedef union _hw_i2s_rmr
02795 {
02796     uint32_t U;
02797     struct _hw_i2s_rmr_bitfields
02798     {
02799         uint32_t RWM : 32;             /*!< [31:0] Receive Word Mask */
02800     } B;
02801 } hw_i2s_rmr_t;
02802 
02803 /*!
02804  * @name Constants and macros for entire I2S_RMR register
02805  */
02806 /*@{*/
02807 #define HW_I2S_RMR_ADDR(x)       ((x) + 0xE0U)
02808 
02809 #define HW_I2S_RMR(x)            (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
02810 #define HW_I2S_RMR_RD(x)         (HW_I2S_RMR(x).U)
02811 #define HW_I2S_RMR_WR(x, v)      (HW_I2S_RMR(x).U = (v))
02812 #define HW_I2S_RMR_SET(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) |  (v)))
02813 #define HW_I2S_RMR_CLR(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
02814 #define HW_I2S_RMR_TOG(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^  (v)))
02815 /*@}*/
02816 
02817 /*
02818  * Constants & macros for individual I2S_RMR bitfields
02819  */
02820 
02821 /*!
02822  * @name Register I2S_RMR, field RWM[31:0] (RW)
02823  *
02824  * Configures whether the receive word is masked (received data ignored and not
02825  * written to receive FIFO) for the corresponding word in the frame.
02826  *
02827  * Values:
02828  * - 0 - Word N is enabled.
02829  * - 1 - Word N is masked.
02830  */
02831 /*@{*/
02832 #define BP_I2S_RMR_RWM       (0U)          /*!< Bit position for I2S_RMR_RWM. */
02833 #define BM_I2S_RMR_RWM       (0xFFFFFFFFU) /*!< Bit mask for I2S_RMR_RWM. */
02834 #define BS_I2S_RMR_RWM       (32U)         /*!< Bit field size in bits for I2S_RMR_RWM. */
02835 
02836 /*! @brief Read current value of the I2S_RMR_RWM field. */
02837 #define BR_I2S_RMR_RWM(x)    (HW_I2S_RMR(x).U)
02838 
02839 /*! @brief Format value for bitfield I2S_RMR_RWM. */
02840 #define BF_I2S_RMR_RWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
02841 
02842 /*! @brief Set the RWM field to a new value. */
02843 #define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
02844 /*@}*/
02845 
02846 /*******************************************************************************
02847  * HW_I2S_MCR - SAI MCLK Control Register
02848  ******************************************************************************/
02849 
02850 /*!
02851  * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
02852  *
02853  * Reset value: 0x00000000U
02854  *
02855  * The MCLK Control Register (MCR) controls the clock source and direction of
02856  * the audio master clock.
02857  */
02858 typedef union _hw_i2s_mcr
02859 {
02860     uint32_t U;
02861     struct _hw_i2s_mcr_bitfields
02862     {
02863         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
02864         uint32_t MICS : 2;             /*!< [25:24] MCLK Input Clock Select */
02865         uint32_t RESERVED1 : 4;        /*!< [29:26]  */
02866         uint32_t MOE : 1;              /*!< [30] MCLK Output Enable */
02867         uint32_t DUF : 1;              /*!< [31] Divider Update Flag */
02868     } B;
02869 } hw_i2s_mcr_t;
02870 
02871 /*!
02872  * @name Constants and macros for entire I2S_MCR register
02873  */
02874 /*@{*/
02875 #define HW_I2S_MCR_ADDR(x)       ((x) + 0x100U)
02876 
02877 #define HW_I2S_MCR(x)            (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
02878 #define HW_I2S_MCR_RD(x)         (HW_I2S_MCR(x).U)
02879 #define HW_I2S_MCR_WR(x, v)      (HW_I2S_MCR(x).U = (v))
02880 #define HW_I2S_MCR_SET(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) |  (v)))
02881 #define HW_I2S_MCR_CLR(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
02882 #define HW_I2S_MCR_TOG(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^  (v)))
02883 /*@}*/
02884 
02885 /*
02886  * Constants & macros for individual I2S_MCR bitfields
02887  */
02888 
02889 /*!
02890  * @name Register I2S_MCR, field MICS[25:24] (RW)
02891  *
02892  * Selects the clock input to the MCLK divider. This field cannot be changed
02893  * while the MCLK divider is enabled. See the chip configuration details for
02894  * information about the connections to these inputs.
02895  *
02896  * Values:
02897  * - 00 - MCLK divider input clock 0 selected.
02898  * - 01 - MCLK divider input clock 1 selected.
02899  * - 10 - MCLK divider input clock 2 selected.
02900  * - 11 - MCLK divider input clock 3 selected.
02901  */
02902 /*@{*/
02903 #define BP_I2S_MCR_MICS      (24U)         /*!< Bit position for I2S_MCR_MICS. */
02904 #define BM_I2S_MCR_MICS      (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */
02905 #define BS_I2S_MCR_MICS      (2U)          /*!< Bit field size in bits for I2S_MCR_MICS. */
02906 
02907 /*! @brief Read current value of the I2S_MCR_MICS field. */
02908 #define BR_I2S_MCR_MICS(x)   (HW_I2S_MCR(x).B.MICS)
02909 
02910 /*! @brief Format value for bitfield I2S_MCR_MICS. */
02911 #define BF_I2S_MCR_MICS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
02912 
02913 /*! @brief Set the MICS field to a new value. */
02914 #define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
02915 /*@}*/
02916 
02917 /*!
02918  * @name Register I2S_MCR, field MOE[30] (RW)
02919  *
02920  * Enables the MCLK divider and configures the MCLK signal pin as an output.
02921  * When software clears this field, it remains set until the MCLK divider is fully
02922  * disabled.
02923  *
02924  * Values:
02925  * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
02926  *     divider.
02927  * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
02928  *     the MCLK divider is enabled.
02929  */
02930 /*@{*/
02931 #define BP_I2S_MCR_MOE       (30U)         /*!< Bit position for I2S_MCR_MOE. */
02932 #define BM_I2S_MCR_MOE       (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */
02933 #define BS_I2S_MCR_MOE       (1U)          /*!< Bit field size in bits for I2S_MCR_MOE. */
02934 
02935 /*! @brief Read current value of the I2S_MCR_MOE field. */
02936 #define BR_I2S_MCR_MOE(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
02937 
02938 /*! @brief Format value for bitfield I2S_MCR_MOE. */
02939 #define BF_I2S_MCR_MOE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
02940 
02941 /*! @brief Set the MOE field to a new value. */
02942 #define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
02943 /*@}*/
02944 
02945 /*!
02946  * @name Register I2S_MCR, field DUF[31] (RO)
02947  *
02948  * Provides the status of on-the-fly updates to the MCLK divider ratio.
02949  *
02950  * Values:
02951  * - 0 - MCLK divider ratio is not being updated currently.
02952  * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
02953  *     divider ratio are blocked while this flag remains set.
02954  */
02955 /*@{*/
02956 #define BP_I2S_MCR_DUF       (31U)         /*!< Bit position for I2S_MCR_DUF. */
02957 #define BM_I2S_MCR_DUF       (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */
02958 #define BS_I2S_MCR_DUF       (1U)          /*!< Bit field size in bits for I2S_MCR_DUF. */
02959 
02960 /*! @brief Read current value of the I2S_MCR_DUF field. */
02961 #define BR_I2S_MCR_DUF(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
02962 /*@}*/
02963 
02964 /*******************************************************************************
02965  * HW_I2S_MDR - SAI MCLK Divide Register
02966  ******************************************************************************/
02967 
02968 /*!
02969  * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
02970  *
02971  * Reset value: 0x00000000U
02972  *
02973  * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
02974  * MDR can be changed when the MCLK divider clock is enabled, additional writes
02975  * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
02976  * divided clock is disabled do not set MCR[DUF].
02977  */
02978 typedef union _hw_i2s_mdr
02979 {
02980     uint32_t U;
02981     struct _hw_i2s_mdr_bitfields
02982     {
02983         uint32_t DIVIDE : 12;          /*!< [11:0] MCLK Divide */
02984         uint32_t FRACT : 8;            /*!< [19:12] MCLK Fraction */
02985         uint32_t RESERVED0 : 12;       /*!< [31:20]  */
02986     } B;
02987 } hw_i2s_mdr_t;
02988 
02989 /*!
02990  * @name Constants and macros for entire I2S_MDR register
02991  */
02992 /*@{*/
02993 #define HW_I2S_MDR_ADDR(x)       ((x) + 0x104U)
02994 
02995 #define HW_I2S_MDR(x)            (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
02996 #define HW_I2S_MDR_RD(x)         (HW_I2S_MDR(x).U)
02997 #define HW_I2S_MDR_WR(x, v)      (HW_I2S_MDR(x).U = (v))
02998 #define HW_I2S_MDR_SET(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) |  (v)))
02999 #define HW_I2S_MDR_CLR(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
03000 #define HW_I2S_MDR_TOG(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^  (v)))
03001 /*@}*/
03002 
03003 /*
03004  * Constants & macros for individual I2S_MDR bitfields
03005  */
03006 
03007 /*!
03008  * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
03009  *
03010  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
03011  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
03012  * DIVIDE field.
03013  */
03014 /*@{*/
03015 #define BP_I2S_MDR_DIVIDE    (0U)          /*!< Bit position for I2S_MDR_DIVIDE. */
03016 #define BM_I2S_MDR_DIVIDE    (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */
03017 #define BS_I2S_MDR_DIVIDE    (12U)         /*!< Bit field size in bits for I2S_MDR_DIVIDE. */
03018 
03019 /*! @brief Read current value of the I2S_MDR_DIVIDE field. */
03020 #define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
03021 
03022 /*! @brief Format value for bitfield I2S_MDR_DIVIDE. */
03023 #define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
03024 
03025 /*! @brief Set the DIVIDE field to a new value. */
03026 #define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
03027 /*@}*/
03028 
03029 /*!
03030  * @name Register I2S_MDR, field FRACT[19:12] (RW)
03031  *
03032  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
03033  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
03034  * DIVIDE field.
03035  */
03036 /*@{*/
03037 #define BP_I2S_MDR_FRACT     (12U)         /*!< Bit position for I2S_MDR_FRACT. */
03038 #define BM_I2S_MDR_FRACT     (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */
03039 #define BS_I2S_MDR_FRACT     (8U)          /*!< Bit field size in bits for I2S_MDR_FRACT. */
03040 
03041 /*! @brief Read current value of the I2S_MDR_FRACT field. */
03042 #define BR_I2S_MDR_FRACT(x)  (HW_I2S_MDR(x).B.FRACT)
03043 
03044 /*! @brief Format value for bitfield I2S_MDR_FRACT. */
03045 #define BF_I2S_MDR_FRACT(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
03046 
03047 /*! @brief Set the FRACT field to a new value. */
03048 #define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
03049 /*@}*/
03050 
03051 /*******************************************************************************
03052  * hw_i2s_t - module struct
03053  ******************************************************************************/
03054 /*!
03055  * @brief All I2S module registers.
03056  */
03057 #pragma pack(1)
03058 typedef struct _hw_i2s
03059 {
03060     __IO hw_i2s_tcsr_t TCSR ;               /*!< [0x0] SAI Transmit Control Register */
03061     __IO hw_i2s_tcr1_t TCR1 ;               /*!< [0x4] SAI Transmit Configuration 1 Register */
03062     __IO hw_i2s_tcr2_t TCR2 ;               /*!< [0x8] SAI Transmit Configuration 2 Register */
03063     __IO hw_i2s_tcr3_t TCR3 ;               /*!< [0xC] SAI Transmit Configuration 3 Register */
03064     __IO hw_i2s_tcr4_t TCR4 ;               /*!< [0x10] SAI Transmit Configuration 4 Register */
03065     __IO hw_i2s_tcr5_t TCR5 ;               /*!< [0x14] SAI Transmit Configuration 5 Register */
03066     uint8_t _reserved0[8];
03067     __O hw_i2s_tdrn_t TDRn [2];             /*!< [0x20] SAI Transmit Data Register */
03068     uint8_t _reserved1[24];
03069     __I hw_i2s_tfrn_t TFRn [2];             /*!< [0x40] SAI Transmit FIFO Register */
03070     uint8_t _reserved2[24];
03071     __IO hw_i2s_tmr_t TMR ;                 /*!< [0x60] SAI Transmit Mask Register */
03072     uint8_t _reserved3[28];
03073     __IO hw_i2s_rcsr_t RCSR ;               /*!< [0x80] SAI Receive Control Register */
03074     __IO hw_i2s_rcr1_t RCR1 ;               /*!< [0x84] SAI Receive Configuration 1 Register */
03075     __IO hw_i2s_rcr2_t RCR2 ;               /*!< [0x88] SAI Receive Configuration 2 Register */
03076     __IO hw_i2s_rcr3_t RCR3 ;               /*!< [0x8C] SAI Receive Configuration 3 Register */
03077     __IO hw_i2s_rcr4_t RCR4 ;               /*!< [0x90] SAI Receive Configuration 4 Register */
03078     __IO hw_i2s_rcr5_t RCR5 ;               /*!< [0x94] SAI Receive Configuration 5 Register */
03079     uint8_t _reserved4[8];
03080     __I hw_i2s_rdrn_t RDRn [2];             /*!< [0xA0] SAI Receive Data Register */
03081     uint8_t _reserved5[24];
03082     __I hw_i2s_rfrn_t RFRn [2];             /*!< [0xC0] SAI Receive FIFO Register */
03083     uint8_t _reserved6[24];
03084     __IO hw_i2s_rmr_t RMR ;                 /*!< [0xE0] SAI Receive Mask Register */
03085     uint8_t _reserved7[28];
03086     __IO hw_i2s_mcr_t MCR ;                 /*!< [0x100] SAI MCLK Control Register */
03087     __IO hw_i2s_mdr_t MDR ;                 /*!< [0x104] SAI MCLK Divide Register */
03088 } hw_i2s_t;
03089 #pragma pack()
03090 
03091 /*! @brief Macro to access all I2S registers. */
03092 /*! @param x I2S module instance base address. */
03093 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
03094  *     use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
03095 #define HW_I2S(x)      (*(hw_i2s_t *)(x))
03096 
03097 #endif /* __HW_I2S_REGISTERS_H__ */
03098 /* EOF */