MK64F12_gpio.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_GPIO_REGISTERS_H__
00081 #define __HW_GPIO_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 GPIO
00088  *
00089  * General Purpose Input/Output
00090  *
00091  * Registers defined in this header file:
00092  * - HW_GPIO_PDOR - Port Data Output Register
00093  * - HW_GPIO_PSOR - Port Set Output Register
00094  * - HW_GPIO_PCOR - Port Clear Output Register
00095  * - HW_GPIO_PTOR - Port Toggle Output Register
00096  * - HW_GPIO_PDIR - Port Data Input Register
00097  * - HW_GPIO_PDDR - Port Data Direction Register
00098  *
00099  * - hw_gpio_t - Struct containing all module registers.
00100  */
00101 
00102 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
00103 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
00104 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
00105 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
00106 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
00107 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
00108 
00109 /*******************************************************************************
00110  * HW_GPIO_PDOR - Port Data Output Register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
00115  *
00116  * Reset value: 0x00000000U
00117  *
00118  * This register configures the logic levels that are driven on each
00119  * general-purpose output pins. Do not modify pin configuration registers associated with
00120  * pins not available in your selected package. All unbonded pins not available in
00121  * your package will default to DISABLE state for lowest power consumption.
00122  */
00123 typedef union _hw_gpio_pdor
00124 {
00125     uint32_t U;
00126     struct _hw_gpio_pdor_bitfields
00127     {
00128         uint32_t PDO : 32;             /*!< [31:0] Port Data Output */
00129     } B;
00130 } hw_gpio_pdor_t;
00131 
00132 /*!
00133  * @name Constants and macros for entire GPIO_PDOR register
00134  */
00135 /*@{*/
00136 #define HW_GPIO_PDOR_ADDR(x)     ((x) + 0x0U)
00137 
00138 #define HW_GPIO_PDOR(x)          (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
00139 #define HW_GPIO_PDOR_RD(x)       (HW_GPIO_PDOR(x).U)
00140 #define HW_GPIO_PDOR_WR(x, v)    (HW_GPIO_PDOR(x).U = (v))
00141 #define HW_GPIO_PDOR_SET(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) |  (v)))
00142 #define HW_GPIO_PDOR_CLR(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
00143 #define HW_GPIO_PDOR_TOG(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^  (v)))
00144 /*@}*/
00145 
00146 /*
00147  * Constants & macros for individual GPIO_PDOR bitfields
00148  */
00149 
00150 /*!
00151  * @name Register GPIO_PDOR, field PDO[31:0] (RW)
00152  *
00153  * Register bits for unbonded pins return a undefined value when read.
00154  *
00155  * Values:
00156  * - 0 - Logic level 0 is driven on pin, provided pin is configured for
00157  *     general-purpose output.
00158  * - 1 - Logic level 1 is driven on pin, provided pin is configured for
00159  *     general-purpose output.
00160  */
00161 /*@{*/
00162 #define BP_GPIO_PDOR_PDO     (0U)          /*!< Bit position for GPIO_PDOR_PDO. */
00163 #define BM_GPIO_PDOR_PDO     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
00164 #define BS_GPIO_PDOR_PDO     (32U)         /*!< Bit field size in bits for GPIO_PDOR_PDO. */
00165 
00166 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
00167 #define BR_GPIO_PDOR_PDO(x)  (HW_GPIO_PDOR(x).U)
00168 
00169 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
00170 #define BF_GPIO_PDOR_PDO(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
00171 
00172 /*! @brief Set the PDO field to a new value. */
00173 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
00174 /*@}*/
00175 
00176 /*******************************************************************************
00177  * HW_GPIO_PSOR - Port Set Output Register
00178  ******************************************************************************/
00179 
00180 /*!
00181  * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
00182  *
00183  * Reset value: 0x00000000U
00184  *
00185  * This register configures whether to set the fields of the PDOR.
00186  */
00187 typedef union _hw_gpio_psor
00188 {
00189     uint32_t U;
00190     struct _hw_gpio_psor_bitfields
00191     {
00192         uint32_t PTSO : 32;            /*!< [31:0] Port Set Output */
00193     } B;
00194 } hw_gpio_psor_t;
00195 
00196 /*!
00197  * @name Constants and macros for entire GPIO_PSOR register
00198  */
00199 /*@{*/
00200 #define HW_GPIO_PSOR_ADDR(x)     ((x) + 0x4U)
00201 
00202 #define HW_GPIO_PSOR(x)          (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
00203 #define HW_GPIO_PSOR_RD(x)       (HW_GPIO_PSOR(x).U)
00204 #define HW_GPIO_PSOR_WR(x, v)    (HW_GPIO_PSOR(x).U = (v))
00205 /*@}*/
00206 
00207 /*
00208  * Constants & macros for individual GPIO_PSOR bitfields
00209  */
00210 
00211 /*!
00212  * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
00213  *
00214  * Writing to this register will update the contents of the corresponding bit in
00215  * the PDOR as follows:
00216  *
00217  * Values:
00218  * - 0 - Corresponding bit in PDORn does not change.
00219  * - 1 - Corresponding bit in PDORn is set to logic 1.
00220  */
00221 /*@{*/
00222 #define BP_GPIO_PSOR_PTSO    (0U)          /*!< Bit position for GPIO_PSOR_PTSO. */
00223 #define BM_GPIO_PSOR_PTSO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
00224 #define BS_GPIO_PSOR_PTSO    (32U)         /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
00225 
00226 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
00227 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
00228 
00229 /*! @brief Set the PTSO field to a new value. */
00230 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
00231 /*@}*/
00232 
00233 /*******************************************************************************
00234  * HW_GPIO_PCOR - Port Clear Output Register
00235  ******************************************************************************/
00236 
00237 /*!
00238  * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
00239  *
00240  * Reset value: 0x00000000U
00241  *
00242  * This register configures whether to clear the fields of PDOR.
00243  */
00244 typedef union _hw_gpio_pcor
00245 {
00246     uint32_t U;
00247     struct _hw_gpio_pcor_bitfields
00248     {
00249         uint32_t PTCO : 32;            /*!< [31:0] Port Clear Output */
00250     } B;
00251 } hw_gpio_pcor_t;
00252 
00253 /*!
00254  * @name Constants and macros for entire GPIO_PCOR register
00255  */
00256 /*@{*/
00257 #define HW_GPIO_PCOR_ADDR(x)     ((x) + 0x8U)
00258 
00259 #define HW_GPIO_PCOR(x)          (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
00260 #define HW_GPIO_PCOR_RD(x)       (HW_GPIO_PCOR(x).U)
00261 #define HW_GPIO_PCOR_WR(x, v)    (HW_GPIO_PCOR(x).U = (v))
00262 /*@}*/
00263 
00264 /*
00265  * Constants & macros for individual GPIO_PCOR bitfields
00266  */
00267 
00268 /*!
00269  * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
00270  *
00271  * Writing to this register will update the contents of the corresponding bit in
00272  * the Port Data Output Register (PDOR) as follows:
00273  *
00274  * Values:
00275  * - 0 - Corresponding bit in PDORn does not change.
00276  * - 1 - Corresponding bit in PDORn is cleared to logic 0.
00277  */
00278 /*@{*/
00279 #define BP_GPIO_PCOR_PTCO    (0U)          /*!< Bit position for GPIO_PCOR_PTCO. */
00280 #define BM_GPIO_PCOR_PTCO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
00281 #define BS_GPIO_PCOR_PTCO    (32U)         /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
00282 
00283 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
00284 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
00285 
00286 /*! @brief Set the PTCO field to a new value. */
00287 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
00288 /*@}*/
00289 
00290 /*******************************************************************************
00291  * HW_GPIO_PTOR - Port Toggle Output Register
00292  ******************************************************************************/
00293 
00294 /*!
00295  * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
00296  *
00297  * Reset value: 0x00000000U
00298  */
00299 typedef union _hw_gpio_ptor
00300 {
00301     uint32_t U;
00302     struct _hw_gpio_ptor_bitfields
00303     {
00304         uint32_t PTTO : 32;            /*!< [31:0] Port Toggle Output */
00305     } B;
00306 } hw_gpio_ptor_t;
00307 
00308 /*!
00309  * @name Constants and macros for entire GPIO_PTOR register
00310  */
00311 /*@{*/
00312 #define HW_GPIO_PTOR_ADDR(x)     ((x) + 0xCU)
00313 
00314 #define HW_GPIO_PTOR(x)          (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
00315 #define HW_GPIO_PTOR_RD(x)       (HW_GPIO_PTOR(x).U)
00316 #define HW_GPIO_PTOR_WR(x, v)    (HW_GPIO_PTOR(x).U = (v))
00317 /*@}*/
00318 
00319 /*
00320  * Constants & macros for individual GPIO_PTOR bitfields
00321  */
00322 
00323 /*!
00324  * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
00325  *
00326  * Writing to this register will update the contents of the corresponding bit in
00327  * the PDOR as follows:
00328  *
00329  * Values:
00330  * - 0 - Corresponding bit in PDORn does not change.
00331  * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
00332  *     state.
00333  */
00334 /*@{*/
00335 #define BP_GPIO_PTOR_PTTO    (0U)          /*!< Bit position for GPIO_PTOR_PTTO. */
00336 #define BM_GPIO_PTOR_PTTO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
00337 #define BS_GPIO_PTOR_PTTO    (32U)         /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
00338 
00339 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
00340 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
00341 
00342 /*! @brief Set the PTTO field to a new value. */
00343 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
00344 /*@}*/
00345 
00346 /*******************************************************************************
00347  * HW_GPIO_PDIR - Port Data Input Register
00348  ******************************************************************************/
00349 
00350 /*!
00351  * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
00352  *
00353  * Reset value: 0x00000000U
00354  *
00355  * Do not modify pin configuration registers associated with pins not available
00356  * in your selected package. All unbonded pins not available in your package will
00357  * default to DISABLE state for lowest power consumption.
00358  */
00359 typedef union _hw_gpio_pdir
00360 {
00361     uint32_t U;
00362     struct _hw_gpio_pdir_bitfields
00363     {
00364         uint32_t PDI : 32;             /*!< [31:0] Port Data Input */
00365     } B;
00366 } hw_gpio_pdir_t;
00367 
00368 /*!
00369  * @name Constants and macros for entire GPIO_PDIR register
00370  */
00371 /*@{*/
00372 #define HW_GPIO_PDIR_ADDR(x)     ((x) + 0x10U)
00373 
00374 #define HW_GPIO_PDIR(x)          (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
00375 #define HW_GPIO_PDIR_RD(x)       (HW_GPIO_PDIR(x).U)
00376 /*@}*/
00377 
00378 /*
00379  * Constants & macros for individual GPIO_PDIR bitfields
00380  */
00381 
00382 /*!
00383  * @name Register GPIO_PDIR, field PDI[31:0] (RO)
00384  *
00385  * Reads 0 at the unimplemented pins for a particular device. Pins that are not
00386  * configured for a digital function read 0. If the Port Control and Interrupt
00387  * module is disabled, then the corresponding bit in PDIR does not update.
00388  *
00389  * Values:
00390  * - 0 - Pin logic level is logic 0, or is not configured for use by digital
00391  *     function.
00392  * - 1 - Pin logic level is logic 1.
00393  */
00394 /*@{*/
00395 #define BP_GPIO_PDIR_PDI     (0U)          /*!< Bit position for GPIO_PDIR_PDI. */
00396 #define BM_GPIO_PDIR_PDI     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
00397 #define BS_GPIO_PDIR_PDI     (32U)         /*!< Bit field size in bits for GPIO_PDIR_PDI. */
00398 
00399 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
00400 #define BR_GPIO_PDIR_PDI(x)  (HW_GPIO_PDIR(x).U)
00401 /*@}*/
00402 
00403 /*******************************************************************************
00404  * HW_GPIO_PDDR - Port Data Direction Register
00405  ******************************************************************************/
00406 
00407 /*!
00408  * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
00409  *
00410  * Reset value: 0x00000000U
00411  *
00412  * The PDDR configures the individual port pins for input or output.
00413  */
00414 typedef union _hw_gpio_pddr
00415 {
00416     uint32_t U;
00417     struct _hw_gpio_pddr_bitfields
00418     {
00419         uint32_t PDD : 32;             /*!< [31:0] Port Data Direction */
00420     } B;
00421 } hw_gpio_pddr_t;
00422 
00423 /*!
00424  * @name Constants and macros for entire GPIO_PDDR register
00425  */
00426 /*@{*/
00427 #define HW_GPIO_PDDR_ADDR(x)     ((x) + 0x14U)
00428 
00429 #define HW_GPIO_PDDR(x)          (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
00430 #define HW_GPIO_PDDR_RD(x)       (HW_GPIO_PDDR(x).U)
00431 #define HW_GPIO_PDDR_WR(x, v)    (HW_GPIO_PDDR(x).U = (v))
00432 #define HW_GPIO_PDDR_SET(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) |  (v)))
00433 #define HW_GPIO_PDDR_CLR(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
00434 #define HW_GPIO_PDDR_TOG(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^  (v)))
00435 /*@}*/
00436 
00437 /*
00438  * Constants & macros for individual GPIO_PDDR bitfields
00439  */
00440 
00441 /*!
00442  * @name Register GPIO_PDDR, field PDD[31:0] (RW)
00443  *
00444  * Configures individual port pins for input or output.
00445  *
00446  * Values:
00447  * - 0 - Pin is configured as general-purpose input, for the GPIO function.
00448  * - 1 - Pin is configured as general-purpose output, for the GPIO function.
00449  */
00450 /*@{*/
00451 #define BP_GPIO_PDDR_PDD     (0U)          /*!< Bit position for GPIO_PDDR_PDD. */
00452 #define BM_GPIO_PDDR_PDD     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
00453 #define BS_GPIO_PDDR_PDD     (32U)         /*!< Bit field size in bits for GPIO_PDDR_PDD. */
00454 
00455 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
00456 #define BR_GPIO_PDDR_PDD(x)  (HW_GPIO_PDDR(x).U)
00457 
00458 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
00459 #define BF_GPIO_PDDR_PDD(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
00460 
00461 /*! @brief Set the PDD field to a new value. */
00462 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
00463 /*@}*/
00464 
00465 /*******************************************************************************
00466  * hw_gpio_t - module struct
00467  ******************************************************************************/
00468 /*!
00469  * @brief All GPIO module registers.
00470  */
00471 #pragma pack(1)
00472 typedef struct _hw_gpio
00473 {
00474     __IO hw_gpio_pdor_t PDOR ;              /*!< [0x0] Port Data Output Register */
00475     __O hw_gpio_psor_t PSOR ;               /*!< [0x4] Port Set Output Register */
00476     __O hw_gpio_pcor_t PCOR ;               /*!< [0x8] Port Clear Output Register */
00477     __O hw_gpio_ptor_t PTOR ;               /*!< [0xC] Port Toggle Output Register */
00478     __I hw_gpio_pdir_t PDIR ;               /*!< [0x10] Port Data Input Register */
00479     __IO hw_gpio_pddr_t PDDR ;              /*!< [0x14] Port Data Direction Register */
00480 } hw_gpio_t;
00481 #pragma pack()
00482 
00483 /*! @brief Macro to access all GPIO registers. */
00484 /*! @param x GPIO module instance base address. */
00485 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00486  *     use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
00487 #define HW_GPIO(x)     (*(hw_gpio_t *)(x))
00488 
00489 #endif /* __HW_GPIO_REGISTERS_H__ */
00490 /* EOF */