MK64F12_fmc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_FMC_REGISTERS_H__
00081 #define __HW_FMC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 FMC
00088  *
00089  * Flash Memory Controller
00090  *
00091  * Registers defined in this header file:
00092  * - HW_FMC_PFAPR - Flash Access Protection Register
00093  * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
00094  * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
00095  * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
00096  * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
00097  * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
00098  * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
00099  * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
00100  * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
00101  * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
00102  * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
00103  * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
00104  * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
00105  * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
00106  * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
00107  *
00108  * - hw_fmc_t - Struct containing all module registers.
00109  */
00110 
00111 #define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
00112 
00113 /*******************************************************************************
00114  * HW_FMC_PFAPR - Flash Access Protection Register
00115  ******************************************************************************/
00116 
00117 /*!
00118  * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
00119  *
00120  * Reset value: 0x00F8003FU
00121  */
00122 typedef union _hw_fmc_pfapr
00123 {
00124     uint32_t U;
00125     struct _hw_fmc_pfapr_bitfields
00126     {
00127         uint32_t M0AP : 2;             /*!< [1:0] Master 0 Access Protection */
00128         uint32_t M1AP : 2;             /*!< [3:2] Master 1 Access Protection */
00129         uint32_t M2AP : 2;             /*!< [5:4] Master 2 Access Protection */
00130         uint32_t M3AP : 2;             /*!< [7:6] Master 3 Access Protection */
00131         uint32_t M4AP : 2;             /*!< [9:8] Master 4 Access Protection */
00132         uint32_t M5AP : 2;             /*!< [11:10] Master 5 Access Protection */
00133         uint32_t M6AP : 2;             /*!< [13:12] Master 6 Access Protection */
00134         uint32_t M7AP : 2;             /*!< [15:14] Master 7 Access Protection */
00135         uint32_t M0PFD : 1;            /*!< [16] Master 0 Prefetch Disable */
00136         uint32_t M1PFD : 1;            /*!< [17] Master 1 Prefetch Disable */
00137         uint32_t M2PFD : 1;            /*!< [18] Master 2 Prefetch Disable */
00138         uint32_t M3PFD : 1;            /*!< [19] Master 3 Prefetch Disable */
00139         uint32_t M4PFD : 1;            /*!< [20] Master 4 Prefetch Disable */
00140         uint32_t M5PFD : 1;            /*!< [21] Master 5 Prefetch Disable */
00141         uint32_t M6PFD : 1;            /*!< [22] Master 6 Prefetch Disable */
00142         uint32_t M7PFD : 1;            /*!< [23] Master 7 Prefetch Disable */
00143         uint32_t RESERVED0 : 8;        /*!< [31:24]  */
00144     } B;
00145 } hw_fmc_pfapr_t;
00146 
00147 /*!
00148  * @name Constants and macros for entire FMC_PFAPR register
00149  */
00150 /*@{*/
00151 #define HW_FMC_PFAPR_ADDR(x)     ((x) + 0x0U)
00152 
00153 #define HW_FMC_PFAPR(x)          (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x))
00154 #define HW_FMC_PFAPR_RD(x)       (HW_FMC_PFAPR(x).U)
00155 #define HW_FMC_PFAPR_WR(x, v)    (HW_FMC_PFAPR(x).U = (v))
00156 #define HW_FMC_PFAPR_SET(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) |  (v)))
00157 #define HW_FMC_PFAPR_CLR(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v)))
00158 #define HW_FMC_PFAPR_TOG(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^  (v)))
00159 /*@}*/
00160 
00161 /*
00162  * Constants & macros for individual FMC_PFAPR bitfields
00163  */
00164 
00165 /*!
00166  * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
00167  *
00168  * This field controls whether read and write access to the flash are allowed
00169  * based on the logical master number of the requesting crossbar switch master.
00170  *
00171  * Values:
00172  * - 00 - No access may be performed by this master
00173  * - 01 - Only read accesses may be performed by this master
00174  * - 10 - Only write accesses may be performed by this master
00175  * - 11 - Both read and write accesses may be performed by this master
00176  */
00177 /*@{*/
00178 #define BP_FMC_PFAPR_M0AP    (0U)          /*!< Bit position for FMC_PFAPR_M0AP. */
00179 #define BM_FMC_PFAPR_M0AP    (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */
00180 #define BS_FMC_PFAPR_M0AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M0AP. */
00181 
00182 /*! @brief Read current value of the FMC_PFAPR_M0AP field. */
00183 #define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP)
00184 
00185 /*! @brief Format value for bitfield FMC_PFAPR_M0AP. */
00186 #define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP)
00187 
00188 /*! @brief Set the M0AP field to a new value. */
00189 #define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
00190 /*@}*/
00191 
00192 /*!
00193  * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
00194  *
00195  * This field controls whether read and write access to the flash are allowed
00196  * based on the logical master number of the requesting crossbar switch master.
00197  *
00198  * Values:
00199  * - 00 - No access may be performed by this master
00200  * - 01 - Only read accesses may be performed by this master
00201  * - 10 - Only write accesses may be performed by this master
00202  * - 11 - Both read and write accesses may be performed by this master
00203  */
00204 /*@{*/
00205 #define BP_FMC_PFAPR_M1AP    (2U)          /*!< Bit position for FMC_PFAPR_M1AP. */
00206 #define BM_FMC_PFAPR_M1AP    (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */
00207 #define BS_FMC_PFAPR_M1AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M1AP. */
00208 
00209 /*! @brief Read current value of the FMC_PFAPR_M1AP field. */
00210 #define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP)
00211 
00212 /*! @brief Format value for bitfield FMC_PFAPR_M1AP. */
00213 #define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP)
00214 
00215 /*! @brief Set the M1AP field to a new value. */
00216 #define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
00217 /*@}*/
00218 
00219 /*!
00220  * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
00221  *
00222  * This field controls whether read and write access to the flash are allowed
00223  * based on the logical master number of the requesting crossbar switch master.
00224  *
00225  * Values:
00226  * - 00 - No access may be performed by this master
00227  * - 01 - Only read accesses may be performed by this master
00228  * - 10 - Only write accesses may be performed by this master
00229  * - 11 - Both read and write accesses may be performed by this master
00230  */
00231 /*@{*/
00232 #define BP_FMC_PFAPR_M2AP    (4U)          /*!< Bit position for FMC_PFAPR_M2AP. */
00233 #define BM_FMC_PFAPR_M2AP    (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */
00234 #define BS_FMC_PFAPR_M2AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M2AP. */
00235 
00236 /*! @brief Read current value of the FMC_PFAPR_M2AP field. */
00237 #define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP)
00238 
00239 /*! @brief Format value for bitfield FMC_PFAPR_M2AP. */
00240 #define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP)
00241 
00242 /*! @brief Set the M2AP field to a new value. */
00243 #define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
00244 /*@}*/
00245 
00246 /*!
00247  * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
00248  *
00249  * This field controls whether read and write access to the flash are allowed
00250  * based on the logical master number of the requesting crossbar switch master.
00251  *
00252  * Values:
00253  * - 00 - No access may be performed by this master
00254  * - 01 - Only read accesses may be performed by this master
00255  * - 10 - Only write accesses may be performed by this master
00256  * - 11 - Both read and write accesses may be performed by this master
00257  */
00258 /*@{*/
00259 #define BP_FMC_PFAPR_M3AP    (6U)          /*!< Bit position for FMC_PFAPR_M3AP. */
00260 #define BM_FMC_PFAPR_M3AP    (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */
00261 #define BS_FMC_PFAPR_M3AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M3AP. */
00262 
00263 /*! @brief Read current value of the FMC_PFAPR_M3AP field. */
00264 #define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP)
00265 
00266 /*! @brief Format value for bitfield FMC_PFAPR_M3AP. */
00267 #define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP)
00268 
00269 /*! @brief Set the M3AP field to a new value. */
00270 #define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
00271 /*@}*/
00272 
00273 /*!
00274  * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
00275  *
00276  * This field controls whether read and write access to the flash are allowed
00277  * based on the logical master number of the requesting crossbar switch master.
00278  *
00279  * Values:
00280  * - 00 - No access may be performed by this master
00281  * - 01 - Only read accesses may be performed by this master
00282  * - 10 - Only write accesses may be performed by this master
00283  * - 11 - Both read and write accesses may be performed by this master
00284  */
00285 /*@{*/
00286 #define BP_FMC_PFAPR_M4AP    (8U)          /*!< Bit position for FMC_PFAPR_M4AP. */
00287 #define BM_FMC_PFAPR_M4AP    (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */
00288 #define BS_FMC_PFAPR_M4AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M4AP. */
00289 
00290 /*! @brief Read current value of the FMC_PFAPR_M4AP field. */
00291 #define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP)
00292 
00293 /*! @brief Format value for bitfield FMC_PFAPR_M4AP. */
00294 #define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP)
00295 
00296 /*! @brief Set the M4AP field to a new value. */
00297 #define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
00298 /*@}*/
00299 
00300 /*!
00301  * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
00302  *
00303  * This field controls whether read and write access to the flash are allowed
00304  * based on the logical master number of the requesting crossbar switch master.
00305  *
00306  * Values:
00307  * - 00 - No access may be performed by this master
00308  * - 01 - Only read accesses may be performed by this master
00309  * - 10 - Only write accesses may be performed by this master
00310  * - 11 - Both read and write accesses may be performed by this master
00311  */
00312 /*@{*/
00313 #define BP_FMC_PFAPR_M5AP    (10U)         /*!< Bit position for FMC_PFAPR_M5AP. */
00314 #define BM_FMC_PFAPR_M5AP    (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */
00315 #define BS_FMC_PFAPR_M5AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M5AP. */
00316 
00317 /*! @brief Read current value of the FMC_PFAPR_M5AP field. */
00318 #define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP)
00319 
00320 /*! @brief Format value for bitfield FMC_PFAPR_M5AP. */
00321 #define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP)
00322 
00323 /*! @brief Set the M5AP field to a new value. */
00324 #define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
00325 /*@}*/
00326 
00327 /*!
00328  * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
00329  *
00330  * This field controls whether read and write access to the flash are allowed
00331  * based on the logical master number of the requesting crossbar switch master.
00332  *
00333  * Values:
00334  * - 00 - No access may be performed by this master
00335  * - 01 - Only read accesses may be performed by this master
00336  * - 10 - Only write accesses may be performed by this master
00337  * - 11 - Both read and write accesses may be performed by this master
00338  */
00339 /*@{*/
00340 #define BP_FMC_PFAPR_M6AP    (12U)         /*!< Bit position for FMC_PFAPR_M6AP. */
00341 #define BM_FMC_PFAPR_M6AP    (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */
00342 #define BS_FMC_PFAPR_M6AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M6AP. */
00343 
00344 /*! @brief Read current value of the FMC_PFAPR_M6AP field. */
00345 #define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP)
00346 
00347 /*! @brief Format value for bitfield FMC_PFAPR_M6AP. */
00348 #define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP)
00349 
00350 /*! @brief Set the M6AP field to a new value. */
00351 #define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
00352 /*@}*/
00353 
00354 /*!
00355  * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
00356  *
00357  * This field controls whether read and write access to the flash are allowed
00358  * based on the logical master number of the requesting crossbar switch master.
00359  *
00360  * Values:
00361  * - 00 - No access may be performed by this master.
00362  * - 01 - Only read accesses may be performed by this master.
00363  * - 10 - Only write accesses may be performed by this master.
00364  * - 11 - Both read and write accesses may be performed by this master.
00365  */
00366 /*@{*/
00367 #define BP_FMC_PFAPR_M7AP    (14U)         /*!< Bit position for FMC_PFAPR_M7AP. */
00368 #define BM_FMC_PFAPR_M7AP    (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */
00369 #define BS_FMC_PFAPR_M7AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M7AP. */
00370 
00371 /*! @brief Read current value of the FMC_PFAPR_M7AP field. */
00372 #define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP)
00373 
00374 /*! @brief Format value for bitfield FMC_PFAPR_M7AP. */
00375 #define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP)
00376 
00377 /*! @brief Set the M7AP field to a new value. */
00378 #define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
00379 /*@}*/
00380 
00381 /*!
00382  * @name Register FMC_PFAPR, field M0PFD[16] (RW)
00383  *
00384  * These bits control whether prefetching is enabled based on the logical number
00385  * of the requesting crossbar switch master. This field is further qualified by
00386  * the PFBnCR[BxDPE,BxIPE] bits.
00387  *
00388  * Values:
00389  * - 0 - Prefetching for this master is enabled.
00390  * - 1 - Prefetching for this master is disabled.
00391  */
00392 /*@{*/
00393 #define BP_FMC_PFAPR_M0PFD   (16U)         /*!< Bit position for FMC_PFAPR_M0PFD. */
00394 #define BM_FMC_PFAPR_M0PFD   (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */
00395 #define BS_FMC_PFAPR_M0PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */
00396 
00397 /*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
00398 #define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD))
00399 
00400 /*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */
00401 #define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD)
00402 
00403 /*! @brief Set the M0PFD field to a new value. */
00404 #define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v))
00405 /*@}*/
00406 
00407 /*!
00408  * @name Register FMC_PFAPR, field M1PFD[17] (RW)
00409  *
00410  * These bits control whether prefetching is enabled based on the logical number
00411  * of the requesting crossbar switch master. This field is further qualified by
00412  * the PFBnCR[BxDPE,BxIPE] bits.
00413  *
00414  * Values:
00415  * - 0 - Prefetching for this master is enabled.
00416  * - 1 - Prefetching for this master is disabled.
00417  */
00418 /*@{*/
00419 #define BP_FMC_PFAPR_M1PFD   (17U)         /*!< Bit position for FMC_PFAPR_M1PFD. */
00420 #define BM_FMC_PFAPR_M1PFD   (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */
00421 #define BS_FMC_PFAPR_M1PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */
00422 
00423 /*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
00424 #define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD))
00425 
00426 /*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */
00427 #define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD)
00428 
00429 /*! @brief Set the M1PFD field to a new value. */
00430 #define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v))
00431 /*@}*/
00432 
00433 /*!
00434  * @name Register FMC_PFAPR, field M2PFD[18] (RW)
00435  *
00436  * These bits control whether prefetching is enabled based on the logical number
00437  * of the requesting crossbar switch master. This field is further qualified by
00438  * the PFBnCR[BxDPE,BxIPE] bits.
00439  *
00440  * Values:
00441  * - 0 - Prefetching for this master is enabled.
00442  * - 1 - Prefetching for this master is disabled.
00443  */
00444 /*@{*/
00445 #define BP_FMC_PFAPR_M2PFD   (18U)         /*!< Bit position for FMC_PFAPR_M2PFD. */
00446 #define BM_FMC_PFAPR_M2PFD   (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */
00447 #define BS_FMC_PFAPR_M2PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */
00448 
00449 /*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
00450 #define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD))
00451 
00452 /*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */
00453 #define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD)
00454 
00455 /*! @brief Set the M2PFD field to a new value. */
00456 #define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v))
00457 /*@}*/
00458 
00459 /*!
00460  * @name Register FMC_PFAPR, field M3PFD[19] (RW)
00461  *
00462  * These bits control whether prefetching is enabled based on the logical number
00463  * of the requesting crossbar switch master. This field is further qualified by
00464  * the PFBnCR[BxDPE,BxIPE] bits.
00465  *
00466  * Values:
00467  * - 0 - Prefetching for this master is enabled.
00468  * - 1 - Prefetching for this master is disabled.
00469  */
00470 /*@{*/
00471 #define BP_FMC_PFAPR_M3PFD   (19U)         /*!< Bit position for FMC_PFAPR_M3PFD. */
00472 #define BM_FMC_PFAPR_M3PFD   (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */
00473 #define BS_FMC_PFAPR_M3PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */
00474 
00475 /*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
00476 #define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD))
00477 
00478 /*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */
00479 #define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD)
00480 
00481 /*! @brief Set the M3PFD field to a new value. */
00482 #define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v))
00483 /*@}*/
00484 
00485 /*!
00486  * @name Register FMC_PFAPR, field M4PFD[20] (RW)
00487  *
00488  * These bits control whether prefetching is enabled based on the logical number
00489  * of the requesting crossbar switch master. This field is further qualified by
00490  * the PFBnCR[BxDPE,BxIPE] bits.
00491  *
00492  * Values:
00493  * - 0 - Prefetching for this master is enabled.
00494  * - 1 - Prefetching for this master is disabled.
00495  */
00496 /*@{*/
00497 #define BP_FMC_PFAPR_M4PFD   (20U)         /*!< Bit position for FMC_PFAPR_M4PFD. */
00498 #define BM_FMC_PFAPR_M4PFD   (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */
00499 #define BS_FMC_PFAPR_M4PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */
00500 
00501 /*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
00502 #define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD))
00503 
00504 /*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */
00505 #define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD)
00506 
00507 /*! @brief Set the M4PFD field to a new value. */
00508 #define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v))
00509 /*@}*/
00510 
00511 /*!
00512  * @name Register FMC_PFAPR, field M5PFD[21] (RW)
00513  *
00514  * These bits control whether prefetching is enabled based on the logical number
00515  * of the requesting crossbar switch master. This field is further qualified by
00516  * the PFBnCR[BxDPE,BxIPE] bits.
00517  *
00518  * Values:
00519  * - 0 - Prefetching for this master is enabled.
00520  * - 1 - Prefetching for this master is disabled.
00521  */
00522 /*@{*/
00523 #define BP_FMC_PFAPR_M5PFD   (21U)         /*!< Bit position for FMC_PFAPR_M5PFD. */
00524 #define BM_FMC_PFAPR_M5PFD   (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */
00525 #define BS_FMC_PFAPR_M5PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */
00526 
00527 /*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
00528 #define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD))
00529 
00530 /*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */
00531 #define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD)
00532 
00533 /*! @brief Set the M5PFD field to a new value. */
00534 #define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v))
00535 /*@}*/
00536 
00537 /*!
00538  * @name Register FMC_PFAPR, field M6PFD[22] (RW)
00539  *
00540  * These bits control whether prefetching is enabled based on the logical number
00541  * of the requesting crossbar switch master. This field is further qualified by
00542  * the PFBnCR[BxDPE,BxIPE] bits.
00543  *
00544  * Values:
00545  * - 0 - Prefetching for this master is enabled.
00546  * - 1 - Prefetching for this master is disabled.
00547  */
00548 /*@{*/
00549 #define BP_FMC_PFAPR_M6PFD   (22U)         /*!< Bit position for FMC_PFAPR_M6PFD. */
00550 #define BM_FMC_PFAPR_M6PFD   (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */
00551 #define BS_FMC_PFAPR_M6PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */
00552 
00553 /*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
00554 #define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD))
00555 
00556 /*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */
00557 #define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD)
00558 
00559 /*! @brief Set the M6PFD field to a new value. */
00560 #define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v))
00561 /*@}*/
00562 
00563 /*!
00564  * @name Register FMC_PFAPR, field M7PFD[23] (RW)
00565  *
00566  * These bits control whether prefetching is enabled based on the logical number
00567  * of the requesting crossbar switch master. This field is further qualified by
00568  * the PFBnCR[BxDPE,BxIPE] bits.
00569  *
00570  * Values:
00571  * - 0 - Prefetching for this master is enabled.
00572  * - 1 - Prefetching for this master is disabled.
00573  */
00574 /*@{*/
00575 #define BP_FMC_PFAPR_M7PFD   (23U)         /*!< Bit position for FMC_PFAPR_M7PFD. */
00576 #define BM_FMC_PFAPR_M7PFD   (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */
00577 #define BS_FMC_PFAPR_M7PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */
00578 
00579 /*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
00580 #define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD))
00581 
00582 /*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */
00583 #define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD)
00584 
00585 /*! @brief Set the M7PFD field to a new value. */
00586 #define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v))
00587 /*@}*/
00588 
00589 /*******************************************************************************
00590  * HW_FMC_PFB0CR - Flash Bank 0 Control Register
00591  ******************************************************************************/
00592 
00593 /*!
00594  * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
00595  *
00596  * Reset value: 0x3004001FU
00597  */
00598 typedef union _hw_fmc_pfb0cr
00599 {
00600     uint32_t U;
00601     struct _hw_fmc_pfb0cr_bitfields
00602     {
00603         uint32_t B0SEBE : 1;           /*!< [0] Bank 0 Single Entry Buffer Enable */
00604         uint32_t B0IPE : 1;            /*!< [1] Bank 0 Instruction Prefetch Enable */
00605         uint32_t B0DPE : 1;            /*!< [2] Bank 0 Data Prefetch Enable */
00606         uint32_t B0ICE : 1;            /*!< [3] Bank 0 Instruction Cache Enable */
00607         uint32_t B0DCE : 1;            /*!< [4] Bank 0 Data Cache Enable */
00608         uint32_t CRC : 3;              /*!< [7:5] Cache Replacement Control */
00609         uint32_t RESERVED0 : 9;        /*!< [16:8]  */
00610         uint32_t B0MW : 2;             /*!< [18:17] Bank 0 Memory Width */
00611         uint32_t S_B_INV : 1;          /*!< [19] Invalidate Prefetch Speculation
00612                                         * Buffer */
00613         uint32_t CINV_WAY : 4;         /*!< [23:20] Cache Invalidate Way x */
00614         uint32_t CLCK_WAY : 4;         /*!< [27:24] Cache Lock Way x */
00615         uint32_t B0RWSC : 4;           /*!< [31:28] Bank 0 Read Wait State Control */
00616     } B;
00617 } hw_fmc_pfb0cr_t;
00618 
00619 /*!
00620  * @name Constants and macros for entire FMC_PFB0CR register
00621  */
00622 /*@{*/
00623 #define HW_FMC_PFB0CR_ADDR(x)    ((x) + 0x4U)
00624 
00625 #define HW_FMC_PFB0CR(x)         (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x))
00626 #define HW_FMC_PFB0CR_RD(x)      (HW_FMC_PFB0CR(x).U)
00627 #define HW_FMC_PFB0CR_WR(x, v)   (HW_FMC_PFB0CR(x).U = (v))
00628 #define HW_FMC_PFB0CR_SET(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) |  (v)))
00629 #define HW_FMC_PFB0CR_CLR(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v)))
00630 #define HW_FMC_PFB0CR_TOG(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^  (v)))
00631 /*@}*/
00632 
00633 /*
00634  * Constants & macros for individual FMC_PFB0CR bitfields
00635  */
00636 
00637 /*!
00638  * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
00639  *
00640  * This bit controls whether the single entry page buffer is enabled in response
00641  * to flash read accesses. Its operation is independent from bank 1's cache. A
00642  * high-to-low transition of this enable forces the page buffer to be invalidated.
00643  *
00644  * Values:
00645  * - 0 - Single entry buffer is disabled.
00646  * - 1 - Single entry buffer is enabled.
00647  */
00648 /*@{*/
00649 #define BP_FMC_PFB0CR_B0SEBE (0U)          /*!< Bit position for FMC_PFB0CR_B0SEBE. */
00650 #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */
00651 #define BS_FMC_PFB0CR_B0SEBE (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */
00652 
00653 /*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
00654 #define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE))
00655 
00656 /*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */
00657 #define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE)
00658 
00659 /*! @brief Set the B0SEBE field to a new value. */
00660 #define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v))
00661 /*@}*/
00662 
00663 /*!
00664  * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
00665  *
00666  * This bit controls whether prefetches (or speculative accesses) are initiated
00667  * in response to instruction fetches.
00668  *
00669  * Values:
00670  * - 0 - Do not prefetch in response to instruction fetches.
00671  * - 1 - Enable prefetches in response to instruction fetches.
00672  */
00673 /*@{*/
00674 #define BP_FMC_PFB0CR_B0IPE  (1U)          /*!< Bit position for FMC_PFB0CR_B0IPE. */
00675 #define BM_FMC_PFB0CR_B0IPE  (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */
00676 #define BS_FMC_PFB0CR_B0IPE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */
00677 
00678 /*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
00679 #define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE))
00680 
00681 /*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */
00682 #define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE)
00683 
00684 /*! @brief Set the B0IPE field to a new value. */
00685 #define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v))
00686 /*@}*/
00687 
00688 /*!
00689  * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
00690  *
00691  * This bit controls whether prefetches (or speculative accesses) are initiated
00692  * in response to data references.
00693  *
00694  * Values:
00695  * - 0 - Do not prefetch in response to data references.
00696  * - 1 - Enable prefetches in response to data references.
00697  */
00698 /*@{*/
00699 #define BP_FMC_PFB0CR_B0DPE  (2U)          /*!< Bit position for FMC_PFB0CR_B0DPE. */
00700 #define BM_FMC_PFB0CR_B0DPE  (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */
00701 #define BS_FMC_PFB0CR_B0DPE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */
00702 
00703 /*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
00704 #define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE))
00705 
00706 /*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */
00707 #define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE)
00708 
00709 /*! @brief Set the B0DPE field to a new value. */
00710 #define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v))
00711 /*@}*/
00712 
00713 /*!
00714  * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
00715  *
00716  * This bit controls whether instruction fetches are loaded into the cache.
00717  *
00718  * Values:
00719  * - 0 - Do not cache instruction fetches.
00720  * - 1 - Cache instruction fetches.
00721  */
00722 /*@{*/
00723 #define BP_FMC_PFB0CR_B0ICE  (3U)          /*!< Bit position for FMC_PFB0CR_B0ICE. */
00724 #define BM_FMC_PFB0CR_B0ICE  (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */
00725 #define BS_FMC_PFB0CR_B0ICE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */
00726 
00727 /*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
00728 #define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE))
00729 
00730 /*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */
00731 #define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE)
00732 
00733 /*! @brief Set the B0ICE field to a new value. */
00734 #define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v))
00735 /*@}*/
00736 
00737 /*!
00738  * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
00739  *
00740  * This bit controls whether data references are loaded into the cache.
00741  *
00742  * Values:
00743  * - 0 - Do not cache data references.
00744  * - 1 - Cache data references.
00745  */
00746 /*@{*/
00747 #define BP_FMC_PFB0CR_B0DCE  (4U)          /*!< Bit position for FMC_PFB0CR_B0DCE. */
00748 #define BM_FMC_PFB0CR_B0DCE  (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */
00749 #define BS_FMC_PFB0CR_B0DCE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */
00750 
00751 /*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
00752 #define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE))
00753 
00754 /*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */
00755 #define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE)
00756 
00757 /*! @brief Set the B0DCE field to a new value. */
00758 #define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v))
00759 /*@}*/
00760 
00761 /*!
00762  * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
00763  *
00764  * This 3-bit field defines the replacement algorithm for accesses that are
00765  * cached.
00766  *
00767  * Values:
00768  * - 000 - LRU replacement algorithm per set across all four ways
00769  * - 001 - Reserved
00770  * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
00771  * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
00772  * - 1xx - Reserved
00773  */
00774 /*@{*/
00775 #define BP_FMC_PFB0CR_CRC    (5U)          /*!< Bit position for FMC_PFB0CR_CRC. */
00776 #define BM_FMC_PFB0CR_CRC    (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */
00777 #define BS_FMC_PFB0CR_CRC    (3U)          /*!< Bit field size in bits for FMC_PFB0CR_CRC. */
00778 
00779 /*! @brief Read current value of the FMC_PFB0CR_CRC field. */
00780 #define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC)
00781 
00782 /*! @brief Format value for bitfield FMC_PFB0CR_CRC. */
00783 #define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC)
00784 
00785 /*! @brief Set the CRC field to a new value. */
00786 #define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
00787 /*@}*/
00788 
00789 /*!
00790  * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
00791  *
00792  * This read-only field defines the width of the bank 0 memory.
00793  *
00794  * Values:
00795  * - 00 - 32 bits
00796  * - 01 - 64 bits
00797  * - 10 - 128 bits
00798  * - 11 - Reserved
00799  */
00800 /*@{*/
00801 #define BP_FMC_PFB0CR_B0MW   (17U)         /*!< Bit position for FMC_PFB0CR_B0MW. */
00802 #define BM_FMC_PFB0CR_B0MW   (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */
00803 #define BS_FMC_PFB0CR_B0MW   (2U)          /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */
00804 
00805 /*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
00806 #define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW)
00807 /*@}*/
00808 
00809 /*!
00810  * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
00811  *
00812  * This bit determines if the FMC's prefetch speculation buffer and the single
00813  * entry page buffer are to be invalidated (cleared). When this bit is written,
00814  * the speculation buffer and single entry buffer are immediately cleared. This bit
00815  * always reads as zero.
00816  *
00817  * Values:
00818  * - 0 - Speculation buffer and single entry buffer are not affected.
00819  * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
00820  */
00821 /*@{*/
00822 #define BP_FMC_PFB0CR_S_B_INV (19U)        /*!< Bit position for FMC_PFB0CR_S_B_INV. */
00823 #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */
00824 #define BS_FMC_PFB0CR_S_B_INV (1U)         /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */
00825 
00826 /*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */
00827 #define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV)
00828 
00829 /*! @brief Set the S_B_INV field to a new value. */
00830 #define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v))
00831 /*@}*/
00832 
00833 /*!
00834  * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
00835  *
00836  * These bits determine if the given cache way is to be invalidated (cleared).
00837  * When a bit within this field is written, the corresponding cache way is
00838  * immediately invalidated: the way's tag, data, and valid contents are cleared. This
00839  * field always reads as zero. Cache invalidation takes precedence over locking.
00840  * The cache is invalidated by system reset. System software is required to
00841  * maintain memory coherency when any segment of the flash memory is programmed or
00842  * erased. Accordingly, cache invalidations must occur after a programming or erase
00843  * event is completed and before the new memory image is accessed. The bit setting
00844  * definitions are for each bit in the field.
00845  *
00846  * Values:
00847  * - 0 - No cache way invalidation for the corresponding cache
00848  * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
00849  *     and vld bits of ways selected
00850  */
00851 /*@{*/
00852 #define BP_FMC_PFB0CR_CINV_WAY (20U)       /*!< Bit position for FMC_PFB0CR_CINV_WAY. */
00853 #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */
00854 #define BS_FMC_PFB0CR_CINV_WAY (4U)        /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */
00855 
00856 /*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */
00857 #define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY)
00858 
00859 /*! @brief Set the CINV_WAY field to a new value. */
00860 #define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
00861 /*@}*/
00862 
00863 /*!
00864  * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
00865  *
00866  * These bits determine if the given cache way is locked such that its contents
00867  * will not be displaced by future misses. The bit setting definitions are for
00868  * each bit in the field.
00869  *
00870  * Values:
00871  * - 0 - Cache way is unlocked and may be displaced
00872  * - 1 - Cache way is locked and its contents are not displaced
00873  */
00874 /*@{*/
00875 #define BP_FMC_PFB0CR_CLCK_WAY (24U)       /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */
00876 #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */
00877 #define BS_FMC_PFB0CR_CLCK_WAY (4U)        /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */
00878 
00879 /*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
00880 #define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY)
00881 
00882 /*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */
00883 #define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY)
00884 
00885 /*! @brief Set the CLCK_WAY field to a new value. */
00886 #define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
00887 /*@}*/
00888 
00889 /*!
00890  * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
00891  *
00892  * This read-only field defines the number of wait states required to access the
00893  * bank 0 flash memory. The relationship between the read access time of the
00894  * flash array (expressed in system clock cycles) and RWSC is defined as: Access
00895  * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
00896  * this value based on the ratio of the system clock speed to the flash clock
00897  * speed. For example, when this ratio is 4:1, the field's value is 3h.
00898  */
00899 /*@{*/
00900 #define BP_FMC_PFB0CR_B0RWSC (28U)         /*!< Bit position for FMC_PFB0CR_B0RWSC. */
00901 #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */
00902 #define BS_FMC_PFB0CR_B0RWSC (4U)          /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */
00903 
00904 /*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
00905 #define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC)
00906 /*@}*/
00907 
00908 /*******************************************************************************
00909  * HW_FMC_PFB1CR - Flash Bank 1 Control Register
00910  ******************************************************************************/
00911 
00912 /*!
00913  * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
00914  *
00915  * Reset value: 0x3004001FU
00916  *
00917  * This register has a format similar to that for PFB0CR, except it controls the
00918  * operation of flash bank 1, and the "global" cache control fields are empty.
00919  */
00920 typedef union _hw_fmc_pfb1cr
00921 {
00922     uint32_t U;
00923     struct _hw_fmc_pfb1cr_bitfields
00924     {
00925         uint32_t B1SEBE : 1;           /*!< [0] Bank 1 Single Entry Buffer Enable */
00926         uint32_t B1IPE : 1;            /*!< [1] Bank 1 Instruction Prefetch Enable */
00927         uint32_t B1DPE : 1;            /*!< [2] Bank 1 Data Prefetch Enable */
00928         uint32_t B1ICE : 1;            /*!< [3] Bank 1 Instruction Cache Enable */
00929         uint32_t B1DCE : 1;            /*!< [4] Bank 1 Data Cache Enable */
00930         uint32_t RESERVED0 : 12;       /*!< [16:5]  */
00931         uint32_t B1MW : 2;             /*!< [18:17] Bank 1 Memory Width */
00932         uint32_t RESERVED1 : 9;        /*!< [27:19]  */
00933         uint32_t B1RWSC : 4;           /*!< [31:28] Bank 1 Read Wait State Control */
00934     } B;
00935 } hw_fmc_pfb1cr_t;
00936 
00937 /*!
00938  * @name Constants and macros for entire FMC_PFB1CR register
00939  */
00940 /*@{*/
00941 #define HW_FMC_PFB1CR_ADDR(x)    ((x) + 0x8U)
00942 
00943 #define HW_FMC_PFB1CR(x)         (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x))
00944 #define HW_FMC_PFB1CR_RD(x)      (HW_FMC_PFB1CR(x).U)
00945 #define HW_FMC_PFB1CR_WR(x, v)   (HW_FMC_PFB1CR(x).U = (v))
00946 #define HW_FMC_PFB1CR_SET(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) |  (v)))
00947 #define HW_FMC_PFB1CR_CLR(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v)))
00948 #define HW_FMC_PFB1CR_TOG(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^  (v)))
00949 /*@}*/
00950 
00951 /*
00952  * Constants & macros for individual FMC_PFB1CR bitfields
00953  */
00954 
00955 /*!
00956  * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
00957  *
00958  * This bit controls whether the single entry buffer is enabled in response to
00959  * flash read accesses. Its operation is independent from bank 0's cache. A
00960  * high-to-low transition of this enable forces the page buffer to be invalidated.
00961  *
00962  * Values:
00963  * - 0 - Single entry buffer is disabled.
00964  * - 1 - Single entry buffer is enabled.
00965  */
00966 /*@{*/
00967 #define BP_FMC_PFB1CR_B1SEBE (0U)          /*!< Bit position for FMC_PFB1CR_B1SEBE. */
00968 #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */
00969 #define BS_FMC_PFB1CR_B1SEBE (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */
00970 
00971 /*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
00972 #define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE))
00973 
00974 /*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */
00975 #define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE)
00976 
00977 /*! @brief Set the B1SEBE field to a new value. */
00978 #define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v))
00979 /*@}*/
00980 
00981 /*!
00982  * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
00983  *
00984  * This bit controls whether prefetches (or speculative accesses) are initiated
00985  * in response to instruction fetches.
00986  *
00987  * Values:
00988  * - 0 - Do not prefetch in response to instruction fetches.
00989  * - 1 - Enable prefetches in response to instruction fetches.
00990  */
00991 /*@{*/
00992 #define BP_FMC_PFB1CR_B1IPE  (1U)          /*!< Bit position for FMC_PFB1CR_B1IPE. */
00993 #define BM_FMC_PFB1CR_B1IPE  (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */
00994 #define BS_FMC_PFB1CR_B1IPE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */
00995 
00996 /*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
00997 #define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE))
00998 
00999 /*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */
01000 #define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE)
01001 
01002 /*! @brief Set the B1IPE field to a new value. */
01003 #define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v))
01004 /*@}*/
01005 
01006 /*!
01007  * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
01008  *
01009  * This bit controls whether prefetches (or speculative accesses) are initiated
01010  * in response to data references.
01011  *
01012  * Values:
01013  * - 0 - Do not prefetch in response to data references.
01014  * - 1 - Enable prefetches in response to data references.
01015  */
01016 /*@{*/
01017 #define BP_FMC_PFB1CR_B1DPE  (2U)          /*!< Bit position for FMC_PFB1CR_B1DPE. */
01018 #define BM_FMC_PFB1CR_B1DPE  (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */
01019 #define BS_FMC_PFB1CR_B1DPE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */
01020 
01021 /*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
01022 #define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE))
01023 
01024 /*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */
01025 #define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE)
01026 
01027 /*! @brief Set the B1DPE field to a new value. */
01028 #define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v))
01029 /*@}*/
01030 
01031 /*!
01032  * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
01033  *
01034  * This bit controls whether instruction fetches are loaded into the cache.
01035  *
01036  * Values:
01037  * - 0 - Do not cache instruction fetches.
01038  * - 1 - Cache instruction fetches.
01039  */
01040 /*@{*/
01041 #define BP_FMC_PFB1CR_B1ICE  (3U)          /*!< Bit position for FMC_PFB1CR_B1ICE. */
01042 #define BM_FMC_PFB1CR_B1ICE  (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */
01043 #define BS_FMC_PFB1CR_B1ICE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */
01044 
01045 /*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
01046 #define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE))
01047 
01048 /*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */
01049 #define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE)
01050 
01051 /*! @brief Set the B1ICE field to a new value. */
01052 #define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v))
01053 /*@}*/
01054 
01055 /*!
01056  * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
01057  *
01058  * This bit controls whether data references are loaded into the cache.
01059  *
01060  * Values:
01061  * - 0 - Do not cache data references.
01062  * - 1 - Cache data references.
01063  */
01064 /*@{*/
01065 #define BP_FMC_PFB1CR_B1DCE  (4U)          /*!< Bit position for FMC_PFB1CR_B1DCE. */
01066 #define BM_FMC_PFB1CR_B1DCE  (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */
01067 #define BS_FMC_PFB1CR_B1DCE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */
01068 
01069 /*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
01070 #define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE))
01071 
01072 /*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */
01073 #define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE)
01074 
01075 /*! @brief Set the B1DCE field to a new value. */
01076 #define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v))
01077 /*@}*/
01078 
01079 /*!
01080  * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
01081  *
01082  * This read-only field defines the width of the bank 1 memory.
01083  *
01084  * Values:
01085  * - 00 - 32 bits
01086  * - 01 - 64 bits
01087  * - 10 - 128 bits
01088  * - 11 - Reserved
01089  */
01090 /*@{*/
01091 #define BP_FMC_PFB1CR_B1MW   (17U)         /*!< Bit position for FMC_PFB1CR_B1MW. */
01092 #define BM_FMC_PFB1CR_B1MW   (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */
01093 #define BS_FMC_PFB1CR_B1MW   (2U)          /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */
01094 
01095 /*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
01096 #define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW)
01097 /*@}*/
01098 
01099 /*!
01100  * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
01101  *
01102  * This read-only field defines the number of wait states required to access the
01103  * bank 1 flash memory. The relationship between the read access time of the
01104  * flash array (expressed in system clock cycles) and RWSC is defined as: Access
01105  * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
01106  * this value based on the ratio of the system clock speed to the flash clock
01107  * speed. For example, when this ratio is 4:1, the field's value is 3h.
01108  */
01109 /*@{*/
01110 #define BP_FMC_PFB1CR_B1RWSC (28U)         /*!< Bit position for FMC_PFB1CR_B1RWSC. */
01111 #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */
01112 #define BS_FMC_PFB1CR_B1RWSC (4U)          /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */
01113 
01114 /*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
01115 #define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC)
01116 /*@}*/
01117 
01118 /*******************************************************************************
01119  * HW_FMC_TAGVDW0Sn - Cache Tag Storage
01120  ******************************************************************************/
01121 
01122 /*!
01123  * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
01124  *
01125  * Reset value: 0x00000000U
01126  *
01127  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01128  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01129  * denotes the set. This section represents tag/vld information for all sets in the
01130  * indicated way.
01131  */
01132 typedef union _hw_fmc_tagvdw0sn
01133 {
01134     uint32_t U;
01135     struct _hw_fmc_tagvdw0sn_bitfields
01136     {
01137         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01138         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01139         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01140         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01141     } B;
01142 } hw_fmc_tagvdw0sn_t;
01143 
01144 /*!
01145  * @name Constants and macros for entire FMC_TAGVDW0Sn register
01146  */
01147 /*@{*/
01148 #define HW_FMC_TAGVDW0Sn_COUNT (4U)
01149 
01150 #define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n)))
01151 
01152 #define HW_FMC_TAGVDW0Sn(x, n)   (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n))
01153 #define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U)
01154 #define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v))
01155 #define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) |  (v)))
01156 #define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v)))
01157 #define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^  (v)))
01158 /*@}*/
01159 
01160 /*
01161  * Constants & macros for individual FMC_TAGVDW0Sn bitfields
01162  */
01163 
01164 /*!
01165  * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
01166  */
01167 /*@{*/
01168 #define BP_FMC_TAGVDW0Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW0Sn_valid. */
01169 #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */
01170 #define BS_FMC_TAGVDW0Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */
01171 
01172 /*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */
01173 #define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid))
01174 
01175 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */
01176 #define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid)
01177 
01178 /*! @brief Set the valid field to a new value. */
01179 #define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v))
01180 /*@}*/
01181 
01182 /*!
01183  * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
01184  */
01185 /*@{*/
01186 #define BP_FMC_TAGVDW0Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW0Sn_tag. */
01187 #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */
01188 #define BS_FMC_TAGVDW0Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */
01189 
01190 /*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */
01191 #define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag)
01192 
01193 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */
01194 #define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag)
01195 
01196 /*! @brief Set the tag field to a new value. */
01197 #define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
01198 /*@}*/
01199 
01200 /*******************************************************************************
01201  * HW_FMC_TAGVDW1Sn - Cache Tag Storage
01202  ******************************************************************************/
01203 
01204 /*!
01205  * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
01206  *
01207  * Reset value: 0x00000000U
01208  *
01209  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01210  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01211  * denotes the set. This section represents tag/vld information for all sets in the
01212  * indicated way.
01213  */
01214 typedef union _hw_fmc_tagvdw1sn
01215 {
01216     uint32_t U;
01217     struct _hw_fmc_tagvdw1sn_bitfields
01218     {
01219         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01220         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01221         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01222         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01223     } B;
01224 } hw_fmc_tagvdw1sn_t;
01225 
01226 /*!
01227  * @name Constants and macros for entire FMC_TAGVDW1Sn register
01228  */
01229 /*@{*/
01230 #define HW_FMC_TAGVDW1Sn_COUNT (4U)
01231 
01232 #define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n)))
01233 
01234 #define HW_FMC_TAGVDW1Sn(x, n)   (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n))
01235 #define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U)
01236 #define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v))
01237 #define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) |  (v)))
01238 #define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v)))
01239 #define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^  (v)))
01240 /*@}*/
01241 
01242 /*
01243  * Constants & macros for individual FMC_TAGVDW1Sn bitfields
01244  */
01245 
01246 /*!
01247  * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
01248  */
01249 /*@{*/
01250 #define BP_FMC_TAGVDW1Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW1Sn_valid. */
01251 #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */
01252 #define BS_FMC_TAGVDW1Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */
01253 
01254 /*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */
01255 #define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid))
01256 
01257 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */
01258 #define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid)
01259 
01260 /*! @brief Set the valid field to a new value. */
01261 #define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v))
01262 /*@}*/
01263 
01264 /*!
01265  * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
01266  */
01267 /*@{*/
01268 #define BP_FMC_TAGVDW1Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW1Sn_tag. */
01269 #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */
01270 #define BS_FMC_TAGVDW1Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */
01271 
01272 /*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */
01273 #define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag)
01274 
01275 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */
01276 #define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag)
01277 
01278 /*! @brief Set the tag field to a new value. */
01279 #define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
01280 /*@}*/
01281 
01282 /*******************************************************************************
01283  * HW_FMC_TAGVDW2Sn - Cache Tag Storage
01284  ******************************************************************************/
01285 
01286 /*!
01287  * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
01288  *
01289  * Reset value: 0x00000000U
01290  *
01291  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01292  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01293  * denotes the set. This section represents tag/vld information for all sets in the
01294  * indicated way.
01295  */
01296 typedef union _hw_fmc_tagvdw2sn
01297 {
01298     uint32_t U;
01299     struct _hw_fmc_tagvdw2sn_bitfields
01300     {
01301         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01302         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01303         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01304         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01305     } B;
01306 } hw_fmc_tagvdw2sn_t;
01307 
01308 /*!
01309  * @name Constants and macros for entire FMC_TAGVDW2Sn register
01310  */
01311 /*@{*/
01312 #define HW_FMC_TAGVDW2Sn_COUNT (4U)
01313 
01314 #define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n)))
01315 
01316 #define HW_FMC_TAGVDW2Sn(x, n)   (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n))
01317 #define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U)
01318 #define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v))
01319 #define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) |  (v)))
01320 #define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v)))
01321 #define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^  (v)))
01322 /*@}*/
01323 
01324 /*
01325  * Constants & macros for individual FMC_TAGVDW2Sn bitfields
01326  */
01327 
01328 /*!
01329  * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
01330  */
01331 /*@{*/
01332 #define BP_FMC_TAGVDW2Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW2Sn_valid. */
01333 #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */
01334 #define BS_FMC_TAGVDW2Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */
01335 
01336 /*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */
01337 #define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid))
01338 
01339 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */
01340 #define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid)
01341 
01342 /*! @brief Set the valid field to a new value. */
01343 #define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v))
01344 /*@}*/
01345 
01346 /*!
01347  * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
01348  */
01349 /*@{*/
01350 #define BP_FMC_TAGVDW2Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW2Sn_tag. */
01351 #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */
01352 #define BS_FMC_TAGVDW2Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */
01353 
01354 /*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */
01355 #define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag)
01356 
01357 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */
01358 #define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag)
01359 
01360 /*! @brief Set the tag field to a new value. */
01361 #define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
01362 /*@}*/
01363 
01364 /*******************************************************************************
01365  * HW_FMC_TAGVDW3Sn - Cache Tag Storage
01366  ******************************************************************************/
01367 
01368 /*!
01369  * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
01370  *
01371  * Reset value: 0x00000000U
01372  *
01373  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01374  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01375  * denotes the set. This section represents tag/vld information for all sets in the
01376  * indicated way.
01377  */
01378 typedef union _hw_fmc_tagvdw3sn
01379 {
01380     uint32_t U;
01381     struct _hw_fmc_tagvdw3sn_bitfields
01382     {
01383         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01384         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01385         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01386         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01387     } B;
01388 } hw_fmc_tagvdw3sn_t;
01389 
01390 /*!
01391  * @name Constants and macros for entire FMC_TAGVDW3Sn register
01392  */
01393 /*@{*/
01394 #define HW_FMC_TAGVDW3Sn_COUNT (4U)
01395 
01396 #define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n)))
01397 
01398 #define HW_FMC_TAGVDW3Sn(x, n)   (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n))
01399 #define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U)
01400 #define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v))
01401 #define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) |  (v)))
01402 #define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v)))
01403 #define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^  (v)))
01404 /*@}*/
01405 
01406 /*
01407  * Constants & macros for individual FMC_TAGVDW3Sn bitfields
01408  */
01409 
01410 /*!
01411  * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
01412  */
01413 /*@{*/
01414 #define BP_FMC_TAGVDW3Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW3Sn_valid. */
01415 #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */
01416 #define BS_FMC_TAGVDW3Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */
01417 
01418 /*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */
01419 #define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid))
01420 
01421 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */
01422 #define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid)
01423 
01424 /*! @brief Set the valid field to a new value. */
01425 #define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v))
01426 /*@}*/
01427 
01428 /*!
01429  * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
01430  */
01431 /*@{*/
01432 #define BP_FMC_TAGVDW3Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW3Sn_tag. */
01433 #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */
01434 #define BS_FMC_TAGVDW3Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */
01435 
01436 /*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */
01437 #define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag)
01438 
01439 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */
01440 #define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag)
01441 
01442 /*! @brief Set the tag field to a new value. */
01443 #define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
01444 /*@}*/
01445 
01446 /*******************************************************************************
01447  * HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
01448  ******************************************************************************/
01449 
01450 /*!
01451  * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
01452  *
01453  * Reset value: 0x00000000U
01454  *
01455  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01456  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01457  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01458  * lower word, respectively. This section represents data for the upper word (bits
01459  * [63:32]) of all sets in the indicated way.
01460  */
01461 typedef union _hw_fmc_dataw0snu
01462 {
01463     uint32_t U;
01464     struct _hw_fmc_dataw0snu_bitfields
01465     {
01466         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01467     } B;
01468 } hw_fmc_dataw0snu_t;
01469 
01470 /*!
01471  * @name Constants and macros for entire FMC_DATAW0SnU register
01472  */
01473 /*@{*/
01474 #define HW_FMC_DATAW0SnU_COUNT (4U)
01475 
01476 #define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n)))
01477 
01478 #define HW_FMC_DATAW0SnU(x, n)   (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n))
01479 #define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U)
01480 #define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v))
01481 #define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) |  (v)))
01482 #define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v)))
01483 #define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^  (v)))
01484 /*@}*/
01485 
01486 /*
01487  * Constants & macros for individual FMC_DATAW0SnU bitfields
01488  */
01489 
01490 /*!
01491  * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
01492  */
01493 /*@{*/
01494 #define BP_FMC_DATAW0SnU_data (0U)         /*!< Bit position for FMC_DATAW0SnU_data. */
01495 #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */
01496 #define BS_FMC_DATAW0SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW0SnU_data. */
01497 
01498 /*! @brief Read current value of the FMC_DATAW0SnU_data field. */
01499 #define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U)
01500 
01501 /*! @brief Format value for bitfield FMC_DATAW0SnU_data. */
01502 #define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data)
01503 
01504 /*! @brief Set the data field to a new value. */
01505 #define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v))
01506 /*@}*/
01507 /*******************************************************************************
01508  * HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
01509  ******************************************************************************/
01510 
01511 /*!
01512  * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
01513  *
01514  * Reset value: 0x00000000U
01515  *
01516  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01517  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01518  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01519  * lower word, respectively. This section represents data for the lower word (bits
01520  * [31:0]) of all sets in the indicated way.
01521  */
01522 typedef union _hw_fmc_dataw0snl
01523 {
01524     uint32_t U;
01525     struct _hw_fmc_dataw0snl_bitfields
01526     {
01527         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01528     } B;
01529 } hw_fmc_dataw0snl_t;
01530 
01531 /*!
01532  * @name Constants and macros for entire FMC_DATAW0SnL register
01533  */
01534 /*@{*/
01535 #define HW_FMC_DATAW0SnL_COUNT (4U)
01536 
01537 #define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n)))
01538 
01539 #define HW_FMC_DATAW0SnL(x, n)   (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n))
01540 #define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U)
01541 #define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v))
01542 #define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) |  (v)))
01543 #define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v)))
01544 #define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^  (v)))
01545 /*@}*/
01546 
01547 /*
01548  * Constants & macros for individual FMC_DATAW0SnL bitfields
01549  */
01550 
01551 /*!
01552  * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
01553  */
01554 /*@{*/
01555 #define BP_FMC_DATAW0SnL_data (0U)         /*!< Bit position for FMC_DATAW0SnL_data. */
01556 #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */
01557 #define BS_FMC_DATAW0SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW0SnL_data. */
01558 
01559 /*! @brief Read current value of the FMC_DATAW0SnL_data field. */
01560 #define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U)
01561 
01562 /*! @brief Format value for bitfield FMC_DATAW0SnL_data. */
01563 #define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data)
01564 
01565 /*! @brief Set the data field to a new value. */
01566 #define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v))
01567 /*@}*/
01568 
01569 /*******************************************************************************
01570  * HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
01571  ******************************************************************************/
01572 
01573 /*!
01574  * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
01575  *
01576  * Reset value: 0x00000000U
01577  *
01578  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01579  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01580  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01581  * lower word, respectively. This section represents data for the upper word (bits
01582  * [63:32]) of all sets in the indicated way.
01583  */
01584 typedef union _hw_fmc_dataw1snu
01585 {
01586     uint32_t U;
01587     struct _hw_fmc_dataw1snu_bitfields
01588     {
01589         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01590     } B;
01591 } hw_fmc_dataw1snu_t;
01592 
01593 /*!
01594  * @name Constants and macros for entire FMC_DATAW1SnU register
01595  */
01596 /*@{*/
01597 #define HW_FMC_DATAW1SnU_COUNT (4U)
01598 
01599 #define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x220U + (0x8U * (n)))
01600 
01601 #define HW_FMC_DATAW1SnU(x, n)   (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n))
01602 #define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U)
01603 #define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v))
01604 #define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) |  (v)))
01605 #define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v)))
01606 #define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^  (v)))
01607 /*@}*/
01608 
01609 /*
01610  * Constants & macros for individual FMC_DATAW1SnU bitfields
01611  */
01612 
01613 /*!
01614  * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
01615  */
01616 /*@{*/
01617 #define BP_FMC_DATAW1SnU_data (0U)         /*!< Bit position for FMC_DATAW1SnU_data. */
01618 #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */
01619 #define BS_FMC_DATAW1SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW1SnU_data. */
01620 
01621 /*! @brief Read current value of the FMC_DATAW1SnU_data field. */
01622 #define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U)
01623 
01624 /*! @brief Format value for bitfield FMC_DATAW1SnU_data. */
01625 #define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data)
01626 
01627 /*! @brief Set the data field to a new value. */
01628 #define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v))
01629 /*@}*/
01630 /*******************************************************************************
01631  * HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
01632  ******************************************************************************/
01633 
01634 /*!
01635  * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
01636  *
01637  * Reset value: 0x00000000U
01638  *
01639  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01640  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01641  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01642  * lower word, respectively. This section represents data for the lower word (bits
01643  * [31:0]) of all sets in the indicated way.
01644  */
01645 typedef union _hw_fmc_dataw1snl
01646 {
01647     uint32_t U;
01648     struct _hw_fmc_dataw1snl_bitfields
01649     {
01650         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01651     } B;
01652 } hw_fmc_dataw1snl_t;
01653 
01654 /*!
01655  * @name Constants and macros for entire FMC_DATAW1SnL register
01656  */
01657 /*@{*/
01658 #define HW_FMC_DATAW1SnL_COUNT (4U)
01659 
01660 #define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x224U + (0x8U * (n)))
01661 
01662 #define HW_FMC_DATAW1SnL(x, n)   (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n))
01663 #define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U)
01664 #define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v))
01665 #define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) |  (v)))
01666 #define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v)))
01667 #define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^  (v)))
01668 /*@}*/
01669 
01670 /*
01671  * Constants & macros for individual FMC_DATAW1SnL bitfields
01672  */
01673 
01674 /*!
01675  * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
01676  */
01677 /*@{*/
01678 #define BP_FMC_DATAW1SnL_data (0U)         /*!< Bit position for FMC_DATAW1SnL_data. */
01679 #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */
01680 #define BS_FMC_DATAW1SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW1SnL_data. */
01681 
01682 /*! @brief Read current value of the FMC_DATAW1SnL_data field. */
01683 #define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U)
01684 
01685 /*! @brief Format value for bitfield FMC_DATAW1SnL_data. */
01686 #define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data)
01687 
01688 /*! @brief Set the data field to a new value. */
01689 #define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v))
01690 /*@}*/
01691 
01692 /*******************************************************************************
01693  * HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
01694  ******************************************************************************/
01695 
01696 /*!
01697  * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
01698  *
01699  * Reset value: 0x00000000U
01700  *
01701  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01702  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01703  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01704  * lower word, respectively. This section represents data for the upper word (bits
01705  * [63:32]) of all sets in the indicated way.
01706  */
01707 typedef union _hw_fmc_dataw2snu
01708 {
01709     uint32_t U;
01710     struct _hw_fmc_dataw2snu_bitfields
01711     {
01712         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01713     } B;
01714 } hw_fmc_dataw2snu_t;
01715 
01716 /*!
01717  * @name Constants and macros for entire FMC_DATAW2SnU register
01718  */
01719 /*@{*/
01720 #define HW_FMC_DATAW2SnU_COUNT (4U)
01721 
01722 #define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n)))
01723 
01724 #define HW_FMC_DATAW2SnU(x, n)   (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n))
01725 #define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U)
01726 #define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v))
01727 #define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) |  (v)))
01728 #define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v)))
01729 #define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^  (v)))
01730 /*@}*/
01731 
01732 /*
01733  * Constants & macros for individual FMC_DATAW2SnU bitfields
01734  */
01735 
01736 /*!
01737  * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
01738  */
01739 /*@{*/
01740 #define BP_FMC_DATAW2SnU_data (0U)         /*!< Bit position for FMC_DATAW2SnU_data. */
01741 #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */
01742 #define BS_FMC_DATAW2SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW2SnU_data. */
01743 
01744 /*! @brief Read current value of the FMC_DATAW2SnU_data field. */
01745 #define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U)
01746 
01747 /*! @brief Format value for bitfield FMC_DATAW2SnU_data. */
01748 #define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data)
01749 
01750 /*! @brief Set the data field to a new value. */
01751 #define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v))
01752 /*@}*/
01753 /*******************************************************************************
01754  * HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
01755  ******************************************************************************/
01756 
01757 /*!
01758  * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
01759  *
01760  * Reset value: 0x00000000U
01761  *
01762  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01763  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01764  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01765  * lower word, respectively. This section represents data for the lower word (bits
01766  * [31:0]) of all sets in the indicated way.
01767  */
01768 typedef union _hw_fmc_dataw2snl
01769 {
01770     uint32_t U;
01771     struct _hw_fmc_dataw2snl_bitfields
01772     {
01773         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01774     } B;
01775 } hw_fmc_dataw2snl_t;
01776 
01777 /*!
01778  * @name Constants and macros for entire FMC_DATAW2SnL register
01779  */
01780 /*@{*/
01781 #define HW_FMC_DATAW2SnL_COUNT (4U)
01782 
01783 #define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n)))
01784 
01785 #define HW_FMC_DATAW2SnL(x, n)   (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n))
01786 #define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U)
01787 #define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v))
01788 #define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) |  (v)))
01789 #define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v)))
01790 #define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^  (v)))
01791 /*@}*/
01792 
01793 /*
01794  * Constants & macros for individual FMC_DATAW2SnL bitfields
01795  */
01796 
01797 /*!
01798  * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
01799  */
01800 /*@{*/
01801 #define BP_FMC_DATAW2SnL_data (0U)         /*!< Bit position for FMC_DATAW2SnL_data. */
01802 #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */
01803 #define BS_FMC_DATAW2SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW2SnL_data. */
01804 
01805 /*! @brief Read current value of the FMC_DATAW2SnL_data field. */
01806 #define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U)
01807 
01808 /*! @brief Format value for bitfield FMC_DATAW2SnL_data. */
01809 #define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data)
01810 
01811 /*! @brief Set the data field to a new value. */
01812 #define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v))
01813 /*@}*/
01814 
01815 /*******************************************************************************
01816  * HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
01817  ******************************************************************************/
01818 
01819 /*!
01820  * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
01821  *
01822  * Reset value: 0x00000000U
01823  *
01824  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01825  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01826  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01827  * lower word, respectively. This section represents data for the upper word (bits
01828  * [63:32]) of all sets in the indicated way.
01829  */
01830 typedef union _hw_fmc_dataw3snu
01831 {
01832     uint32_t U;
01833     struct _hw_fmc_dataw3snu_bitfields
01834     {
01835         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01836     } B;
01837 } hw_fmc_dataw3snu_t;
01838 
01839 /*!
01840  * @name Constants and macros for entire FMC_DATAW3SnU register
01841  */
01842 /*@{*/
01843 #define HW_FMC_DATAW3SnU_COUNT (4U)
01844 
01845 #define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x260U + (0x8U * (n)))
01846 
01847 #define HW_FMC_DATAW3SnU(x, n)   (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n))
01848 #define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U)
01849 #define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v))
01850 #define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) |  (v)))
01851 #define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v)))
01852 #define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^  (v)))
01853 /*@}*/
01854 
01855 /*
01856  * Constants & macros for individual FMC_DATAW3SnU bitfields
01857  */
01858 
01859 /*!
01860  * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
01861  */
01862 /*@{*/
01863 #define BP_FMC_DATAW3SnU_data (0U)         /*!< Bit position for FMC_DATAW3SnU_data. */
01864 #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */
01865 #define BS_FMC_DATAW3SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW3SnU_data. */
01866 
01867 /*! @brief Read current value of the FMC_DATAW3SnU_data field. */
01868 #define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U)
01869 
01870 /*! @brief Format value for bitfield FMC_DATAW3SnU_data. */
01871 #define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data)
01872 
01873 /*! @brief Set the data field to a new value. */
01874 #define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v))
01875 /*@}*/
01876 /*******************************************************************************
01877  * HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
01878  ******************************************************************************/
01879 
01880 /*!
01881  * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
01882  *
01883  * Reset value: 0x00000000U
01884  *
01885  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01886  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01887  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01888  * lower word, respectively. This section represents data for the lower word (bits
01889  * [31:0]) of all sets in the indicated way.
01890  */
01891 typedef union _hw_fmc_dataw3snl
01892 {
01893     uint32_t U;
01894     struct _hw_fmc_dataw3snl_bitfields
01895     {
01896         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01897     } B;
01898 } hw_fmc_dataw3snl_t;
01899 
01900 /*!
01901  * @name Constants and macros for entire FMC_DATAW3SnL register
01902  */
01903 /*@{*/
01904 #define HW_FMC_DATAW3SnL_COUNT (4U)
01905 
01906 #define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x264U + (0x8U * (n)))
01907 
01908 #define HW_FMC_DATAW3SnL(x, n)   (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n))
01909 #define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U)
01910 #define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v))
01911 #define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) |  (v)))
01912 #define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v)))
01913 #define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^  (v)))
01914 /*@}*/
01915 
01916 /*
01917  * Constants & macros for individual FMC_DATAW3SnL bitfields
01918  */
01919 
01920 /*!
01921  * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
01922  */
01923 /*@{*/
01924 #define BP_FMC_DATAW3SnL_data (0U)         /*!< Bit position for FMC_DATAW3SnL_data. */
01925 #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */
01926 #define BS_FMC_DATAW3SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW3SnL_data. */
01927 
01928 /*! @brief Read current value of the FMC_DATAW3SnL_data field. */
01929 #define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U)
01930 
01931 /*! @brief Format value for bitfield FMC_DATAW3SnL_data. */
01932 #define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data)
01933 
01934 /*! @brief Set the data field to a new value. */
01935 #define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v))
01936 /*@}*/
01937 
01938 /*******************************************************************************
01939  * hw_fmc_t - module struct
01940  ******************************************************************************/
01941 /*!
01942  * @brief All FMC module registers.
01943  */
01944 #pragma pack(1)
01945 typedef struct _hw_fmc
01946 {
01947     __IO hw_fmc_pfapr_t PFAPR ;             /*!< [0x0] Flash Access Protection Register */
01948     __IO hw_fmc_pfb0cr_t PFB0CR ;           /*!< [0x4] Flash Bank 0 Control Register */
01949     __IO hw_fmc_pfb1cr_t PFB1CR ;           /*!< [0x8] Flash Bank 1 Control Register */
01950     uint8_t _reserved0[244];
01951     __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn [4];  /*!< [0x100] Cache Tag Storage */
01952     __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn [4];  /*!< [0x110] Cache Tag Storage */
01953     __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn [4];  /*!< [0x120] Cache Tag Storage */
01954     __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn [4];  /*!< [0x130] Cache Tag Storage */
01955     uint8_t _reserved1[192];
01956     struct {
01957         __IO hw_fmc_dataw0snu_t DATAW0SnU ; /*!< [0x200] Cache Data Storage (upper word) */
01958         __IO hw_fmc_dataw0snl_t DATAW0SnL ; /*!< [0x204] Cache Data Storage (lower word) */
01959     } DATAW0Sn[4];
01960     struct {
01961         __IO hw_fmc_dataw1snu_t DATAW1SnU ; /*!< [0x220] Cache Data Storage (upper word) */
01962         __IO hw_fmc_dataw1snl_t DATAW1SnL ; /*!< [0x224] Cache Data Storage (lower word) */
01963     } DATAW1Sn[4];
01964     struct {
01965         __IO hw_fmc_dataw2snu_t DATAW2SnU ; /*!< [0x240] Cache Data Storage (upper word) */
01966         __IO hw_fmc_dataw2snl_t DATAW2SnL ; /*!< [0x244] Cache Data Storage (lower word) */
01967     } DATAW2Sn[4];
01968     struct {
01969         __IO hw_fmc_dataw3snu_t DATAW3SnU ; /*!< [0x260] Cache Data Storage (upper word) */
01970         __IO hw_fmc_dataw3snl_t DATAW3SnL ; /*!< [0x264] Cache Data Storage (lower word) */
01971     } DATAW3Sn[4];
01972 } hw_fmc_t;
01973 #pragma pack()
01974 
01975 /*! @brief Macro to access all FMC registers. */
01976 /*! @param x FMC module instance base address. */
01977 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01978  *     use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */
01979 #define HW_FMC(x)      (*(hw_fmc_t *)(x))
01980 
01981 #endif /* __HW_FMC_REGISTERS_H__ */
01982 /* EOF */