MK64F12_fb.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_FB_REGISTERS_H__
00081 #define __HW_FB_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 FB
00088  *
00089  * FlexBus external bus interface
00090  *
00091  * Registers defined in this header file:
00092  * - HW_FB_CSARn - Chip Select Address Register
00093  * - HW_FB_CSMRn - Chip Select Mask Register
00094  * - HW_FB_CSCRn - Chip Select Control Register
00095  * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
00096  *
00097  * - hw_fb_t - Struct containing all module registers.
00098  */
00099 
00100 #define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
00101 
00102 /*******************************************************************************
00103  * HW_FB_CSARn - Chip Select Address Register
00104  ******************************************************************************/
00105 
00106 /*!
00107  * @brief HW_FB_CSARn - Chip Select Address Register (RW)
00108  *
00109  * Reset value: 0x00000000U
00110  *
00111  * Specifies the associated chip-select's base address.
00112  */
00113 typedef union _hw_fb_csarn
00114 {
00115     uint32_t U;
00116     struct _hw_fb_csarn_bitfields
00117     {
00118         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
00119         uint32_t BA : 16;              /*!< [31:16] Base Address */
00120     } B;
00121 } hw_fb_csarn_t;
00122 
00123 /*!
00124  * @name Constants and macros for entire FB_CSARn register
00125  */
00126 /*@{*/
00127 #define HW_FB_CSARn_COUNT (6U)
00128 
00129 #define HW_FB_CSARn_ADDR(x, n)   ((x) + 0x0U + (0xCU * (n)))
00130 
00131 #define HW_FB_CSARn(x, n)        (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
00132 #define HW_FB_CSARn_RD(x, n)     (HW_FB_CSARn(x, n).U)
00133 #define HW_FB_CSARn_WR(x, n, v)  (HW_FB_CSARn(x, n).U = (v))
00134 #define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) |  (v)))
00135 #define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
00136 #define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^  (v)))
00137 /*@}*/
00138 
00139 /*
00140  * Constants & macros for individual FB_CSARn bitfields
00141  */
00142 
00143 /*!
00144  * @name Register FB_CSARn, field BA[31:16] (RW)
00145  *
00146  * Defines the base address for memory dedicated to the associated chip-select.
00147  * BA is compared to bits 31-16 on the internal address bus to determine if the
00148  * associated chip-select's memory is being accessed. Because the FlexBus module
00149  * is one of the slaves connected to the crossbar switch, it is only accessible
00150  * within a certain memory range. See the chip memory map for the applicable
00151  * FlexBus "expansion" address range for which the chip-selects can be active. Set the
00152  * CSARn and CSMRn registers appropriately before accessing this region.
00153  */
00154 /*@{*/
00155 #define BP_FB_CSARn_BA       (16U)         /*!< Bit position for FB_CSARn_BA. */
00156 #define BM_FB_CSARn_BA       (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
00157 #define BS_FB_CSARn_BA       (16U)         /*!< Bit field size in bits for FB_CSARn_BA. */
00158 
00159 /*! @brief Read current value of the FB_CSARn_BA field. */
00160 #define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
00161 
00162 /*! @brief Format value for bitfield FB_CSARn_BA. */
00163 #define BF_FB_CSARn_BA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
00164 
00165 /*! @brief Set the BA field to a new value. */
00166 #define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
00167 /*@}*/
00168 /*******************************************************************************
00169  * HW_FB_CSMRn - Chip Select Mask Register
00170  ******************************************************************************/
00171 
00172 /*!
00173  * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
00174  *
00175  * Reset value: 0x00000000U
00176  *
00177  * Specifies the address mask and allowable access types for the associated
00178  * chip-select.
00179  */
00180 typedef union _hw_fb_csmrn
00181 {
00182     uint32_t U;
00183     struct _hw_fb_csmrn_bitfields
00184     {
00185         uint32_t V : 1;                /*!< [0] Valid */
00186         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
00187         uint32_t WP : 1;               /*!< [8] Write Protect */
00188         uint32_t RESERVED1 : 7;        /*!< [15:9]  */
00189         uint32_t BAM : 16;             /*!< [31:16] Base Address Mask */
00190     } B;
00191 } hw_fb_csmrn_t;
00192 
00193 /*!
00194  * @name Constants and macros for entire FB_CSMRn register
00195  */
00196 /*@{*/
00197 #define HW_FB_CSMRn_COUNT (6U)
00198 
00199 #define HW_FB_CSMRn_ADDR(x, n)   ((x) + 0x4U + (0xCU * (n)))
00200 
00201 #define HW_FB_CSMRn(x, n)        (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
00202 #define HW_FB_CSMRn_RD(x, n)     (HW_FB_CSMRn(x, n).U)
00203 #define HW_FB_CSMRn_WR(x, n, v)  (HW_FB_CSMRn(x, n).U = (v))
00204 #define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) |  (v)))
00205 #define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
00206 #define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^  (v)))
00207 /*@}*/
00208 
00209 /*
00210  * Constants & macros for individual FB_CSMRn bitfields
00211  */
00212 
00213 /*!
00214  * @name Register FB_CSMRn, field V[0] (RW)
00215  *
00216  * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
00217  * Programmed chip-selects do not assert until the V bit is 1b (except for
00218  * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
00219  * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
00220  * select initialization sequence to allow other chip selects to function as
00221  * programmed.
00222  *
00223  * Values:
00224  * - 0 - Chip-select is invalid.
00225  * - 1 - Chip-select is valid.
00226  */
00227 /*@{*/
00228 #define BP_FB_CSMRn_V        (0U)          /*!< Bit position for FB_CSMRn_V. */
00229 #define BM_FB_CSMRn_V        (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
00230 #define BS_FB_CSMRn_V        (1U)          /*!< Bit field size in bits for FB_CSMRn_V. */
00231 
00232 /*! @brief Read current value of the FB_CSMRn_V field. */
00233 #define BR_FB_CSMRn_V(x, n)  (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
00234 
00235 /*! @brief Format value for bitfield FB_CSMRn_V. */
00236 #define BF_FB_CSMRn_V(v)     ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
00237 
00238 /*! @brief Set the V field to a new value. */
00239 #define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
00240 /*@}*/
00241 
00242 /*!
00243  * @name Register FB_CSMRn, field WP[8] (RW)
00244  *
00245  * Controls write accesses to the address range in the corresponding CSAR.
00246  *
00247  * Values:
00248  * - 0 - Write accesses are allowed.
00249  * - 1 - Write accesses are not allowed. Attempting to write to the range of
00250  *     addresses for which the WP bit is set results in a bus error termination of
00251  *     the internal cycle and no external cycle.
00252  */
00253 /*@{*/
00254 #define BP_FB_CSMRn_WP       (8U)          /*!< Bit position for FB_CSMRn_WP. */
00255 #define BM_FB_CSMRn_WP       (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
00256 #define BS_FB_CSMRn_WP       (1U)          /*!< Bit field size in bits for FB_CSMRn_WP. */
00257 
00258 /*! @brief Read current value of the FB_CSMRn_WP field. */
00259 #define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
00260 
00261 /*! @brief Format value for bitfield FB_CSMRn_WP. */
00262 #define BF_FB_CSMRn_WP(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
00263 
00264 /*! @brief Set the WP field to a new value. */
00265 #define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
00266 /*@}*/
00267 
00268 /*!
00269  * @name Register FB_CSMRn, field BAM[31:16] (RW)
00270  *
00271  * Defines the associated chip-select's block size by masking address bits.
00272  *
00273  * Values:
00274  * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
00275  * - 1 - The corresponding address bit in CSAR is a don't care in the
00276  *     chip-select decode.
00277  */
00278 /*@{*/
00279 #define BP_FB_CSMRn_BAM      (16U)         /*!< Bit position for FB_CSMRn_BAM. */
00280 #define BM_FB_CSMRn_BAM      (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
00281 #define BS_FB_CSMRn_BAM      (16U)         /*!< Bit field size in bits for FB_CSMRn_BAM. */
00282 
00283 /*! @brief Read current value of the FB_CSMRn_BAM field. */
00284 #define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
00285 
00286 /*! @brief Format value for bitfield FB_CSMRn_BAM. */
00287 #define BF_FB_CSMRn_BAM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
00288 
00289 /*! @brief Set the BAM field to a new value. */
00290 #define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
00291 /*@}*/
00292 /*******************************************************************************
00293  * HW_FB_CSCRn - Chip Select Control Register
00294  ******************************************************************************/
00295 
00296 /*!
00297  * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
00298  *
00299  * Reset value: 0x003FFC00U
00300  *
00301  * Controls the auto-acknowledge, address setup and hold times, port size, burst
00302  * capability, and number of wait states for the associated chip select. To
00303  * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
00304  * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
00305  * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
00306  * particular chip for information on the exact CSCR0 reset value.
00307  */
00308 typedef union _hw_fb_cscrn
00309 {
00310     uint32_t U;
00311     struct _hw_fb_cscrn_bitfields
00312     {
00313         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
00314         uint32_t BSTW : 1;             /*!< [3] Burst-Write Enable */
00315         uint32_t BSTR : 1;             /*!< [4] Burst-Read Enable */
00316         uint32_t BEM : 1;              /*!< [5] Byte-Enable Mode */
00317         uint32_t PS : 2;               /*!< [7:6] Port Size */
00318         uint32_t AA : 1;               /*!< [8] Auto-Acknowledge Enable */
00319         uint32_t BLS : 1;              /*!< [9] Byte-Lane Shift */
00320         uint32_t WS : 6;               /*!< [15:10] Wait States */
00321         uint32_t WRAH : 2;             /*!< [17:16] Write Address Hold or Deselect */
00322         uint32_t RDAH : 2;             /*!< [19:18] Read Address Hold or Deselect */
00323         uint32_t ASET : 2;             /*!< [21:20] Address Setup */
00324         uint32_t EXTS : 1;             /*!< [22]  */
00325         uint32_t SWSEN : 1;            /*!< [23] Secondary Wait State Enable */
00326         uint32_t RESERVED1 : 2;        /*!< [25:24]  */
00327         uint32_t SWS : 6;              /*!< [31:26] Secondary Wait States */
00328     } B;
00329 } hw_fb_cscrn_t;
00330 
00331 /*!
00332  * @name Constants and macros for entire FB_CSCRn register
00333  */
00334 /*@{*/
00335 #define HW_FB_CSCRn_COUNT (6U)
00336 
00337 #define HW_FB_CSCRn_ADDR(x, n)   ((x) + 0x8U + (0xCU * (n)))
00338 
00339 #define HW_FB_CSCRn(x, n)        (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
00340 #define HW_FB_CSCRn_RD(x, n)     (HW_FB_CSCRn(x, n).U)
00341 #define HW_FB_CSCRn_WR(x, n, v)  (HW_FB_CSCRn(x, n).U = (v))
00342 #define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) |  (v)))
00343 #define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
00344 #define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^  (v)))
00345 /*@}*/
00346 
00347 /*
00348  * Constants & macros for individual FB_CSCRn bitfields
00349  */
00350 
00351 /*!
00352  * @name Register FB_CSCRn, field BSTW[3] (RW)
00353  *
00354  * Specifies whether burst writes are enabled for memory associated with each
00355  * chip select.
00356  *
00357  * Values:
00358  * - 0 - Disabled. Data exceeding the specified port size is broken into
00359  *     individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
00360  *     port takes four byte writes.
00361  * - 1 - Enabled. Enables burst write of data larger than the specified port
00362  *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
00363  *     ports, and line writes to 8-, 16-, and 32-bit ports.
00364  */
00365 /*@{*/
00366 #define BP_FB_CSCRn_BSTW     (3U)          /*!< Bit position for FB_CSCRn_BSTW. */
00367 #define BM_FB_CSCRn_BSTW     (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
00368 #define BS_FB_CSCRn_BSTW     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTW. */
00369 
00370 /*! @brief Read current value of the FB_CSCRn_BSTW field. */
00371 #define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
00372 
00373 /*! @brief Format value for bitfield FB_CSCRn_BSTW. */
00374 #define BF_FB_CSCRn_BSTW(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
00375 
00376 /*! @brief Set the BSTW field to a new value. */
00377 #define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
00378 /*@}*/
00379 
00380 /*!
00381  * @name Register FB_CSCRn, field BSTR[4] (RW)
00382  *
00383  * Specifies whether burst reads are enabled for memory associated with each
00384  * chip select.
00385  *
00386  * Values:
00387  * - 0 - Disabled. Data exceeding the specified port size is broken into
00388  *     individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
00389  *     port is broken into four 8-bit reads.
00390  * - 1 - Enabled. Enables data burst reads larger than the specified port size,
00391  *     including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
00392  *     ports, and line reads from 8-, 16-, and 32-bit ports.
00393  */
00394 /*@{*/
00395 #define BP_FB_CSCRn_BSTR     (4U)          /*!< Bit position for FB_CSCRn_BSTR. */
00396 #define BM_FB_CSCRn_BSTR     (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
00397 #define BS_FB_CSCRn_BSTR     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTR. */
00398 
00399 /*! @brief Read current value of the FB_CSCRn_BSTR field. */
00400 #define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
00401 
00402 /*! @brief Format value for bitfield FB_CSCRn_BSTR. */
00403 #define BF_FB_CSCRn_BSTR(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
00404 
00405 /*! @brief Set the BSTR field to a new value. */
00406 #define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
00407 /*@}*/
00408 
00409 /*!
00410  * @name Register FB_CSCRn, field BEM[5] (RW)
00411  *
00412  * Specifies whether the corresponding FB_BE is asserted for read accesses.
00413  * Certain memories have byte enables that must be asserted during reads and writes.
00414  * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
00415  * of byte enable support for these SRAMs.
00416  *
00417  * Values:
00418  * - 0 - FB_BE is asserted for data write only.
00419  * - 1 - FB_BE is asserted for data read and write accesses.
00420  */
00421 /*@{*/
00422 #define BP_FB_CSCRn_BEM      (5U)          /*!< Bit position for FB_CSCRn_BEM. */
00423 #define BM_FB_CSCRn_BEM      (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
00424 #define BS_FB_CSCRn_BEM      (1U)          /*!< Bit field size in bits for FB_CSCRn_BEM. */
00425 
00426 /*! @brief Read current value of the FB_CSCRn_BEM field. */
00427 #define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
00428 
00429 /*! @brief Format value for bitfield FB_CSCRn_BEM. */
00430 #define BF_FB_CSCRn_BEM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
00431 
00432 /*! @brief Set the BEM field to a new value. */
00433 #define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
00434 /*@}*/
00435 
00436 /*!
00437  * @name Register FB_CSCRn, field PS[7:6] (RW)
00438  *
00439  * Specifies the data port width of the associated chip-select, and determines
00440  * where data is driven during write cycles and where data is sampled during read
00441  * cycles.
00442  *
00443  * Values:
00444  * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
00445  * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
00446  *     BLS is 0b, or FB_D[7:0] when BLS is 1b.
00447  */
00448 /*@{*/
00449 #define BP_FB_CSCRn_PS       (6U)          /*!< Bit position for FB_CSCRn_PS. */
00450 #define BM_FB_CSCRn_PS       (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
00451 #define BS_FB_CSCRn_PS       (2U)          /*!< Bit field size in bits for FB_CSCRn_PS. */
00452 
00453 /*! @brief Read current value of the FB_CSCRn_PS field. */
00454 #define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
00455 
00456 /*! @brief Format value for bitfield FB_CSCRn_PS. */
00457 #define BF_FB_CSCRn_PS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
00458 
00459 /*! @brief Set the PS field to a new value. */
00460 #define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
00461 /*@}*/
00462 
00463 /*!
00464  * @name Register FB_CSCRn, field AA[8] (RW)
00465  *
00466  * Asserts the internal transfer acknowledge for accesses specified by the
00467  * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
00468  * asserts an external FB_TA before the wait-state countdown asserts the
00469  * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
00470  * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
00471  *
00472  * Values:
00473  * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
00474  *     terminated externally.
00475  * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
00476  */
00477 /*@{*/
00478 #define BP_FB_CSCRn_AA       (8U)          /*!< Bit position for FB_CSCRn_AA. */
00479 #define BM_FB_CSCRn_AA       (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
00480 #define BS_FB_CSCRn_AA       (1U)          /*!< Bit field size in bits for FB_CSCRn_AA. */
00481 
00482 /*! @brief Read current value of the FB_CSCRn_AA field. */
00483 #define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
00484 
00485 /*! @brief Format value for bitfield FB_CSCRn_AA. */
00486 #define BF_FB_CSCRn_AA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
00487 
00488 /*! @brief Set the AA field to a new value. */
00489 #define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
00490 /*@}*/
00491 
00492 /*!
00493  * @name Register FB_CSCRn, field BLS[9] (RW)
00494  *
00495  * Specifies if data on FB_AD appears left-aligned or right-aligned during the
00496  * data phase of a FlexBus access.
00497  *
00498  * Values:
00499  * - 0 - Not shifted. Data is left-aligned on FB_AD.
00500  * - 1 - Shifted. Data is right-aligned on FB_AD.
00501  */
00502 /*@{*/
00503 #define BP_FB_CSCRn_BLS      (9U)          /*!< Bit position for FB_CSCRn_BLS. */
00504 #define BM_FB_CSCRn_BLS      (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
00505 #define BS_FB_CSCRn_BLS      (1U)          /*!< Bit field size in bits for FB_CSCRn_BLS. */
00506 
00507 /*! @brief Read current value of the FB_CSCRn_BLS field. */
00508 #define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
00509 
00510 /*! @brief Format value for bitfield FB_CSCRn_BLS. */
00511 #define BF_FB_CSCRn_BLS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
00512 
00513 /*! @brief Set the BLS field to a new value. */
00514 #define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
00515 /*@}*/
00516 
00517 /*!
00518  * @name Register FB_CSCRn, field WS[15:10] (RW)
00519  *
00520  * Specifies the number of wait states inserted after FlexBus asserts the
00521  * associated chip-select and before an internal transfer acknowledge is generated (WS
00522  * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
00523  */
00524 /*@{*/
00525 #define BP_FB_CSCRn_WS       (10U)         /*!< Bit position for FB_CSCRn_WS. */
00526 #define BM_FB_CSCRn_WS       (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
00527 #define BS_FB_CSCRn_WS       (6U)          /*!< Bit field size in bits for FB_CSCRn_WS. */
00528 
00529 /*! @brief Read current value of the FB_CSCRn_WS field. */
00530 #define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
00531 
00532 /*! @brief Format value for bitfield FB_CSCRn_WS. */
00533 #define BF_FB_CSCRn_WS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
00534 
00535 /*! @brief Set the WS field to a new value. */
00536 #define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
00537 /*@}*/
00538 
00539 /*!
00540  * @name Register FB_CSCRn, field WRAH[17:16] (RW)
00541  *
00542  * Controls the address, data, and attribute hold time after the termination of
00543  * a write cycle that hits in the associated chip-select's address space. The
00544  * hold time applies only at the end of a transfer. Therefore, during a burst
00545  * transfer or a transfer to a port size smaller than the transfer size, the hold time
00546  * is only added after the last bus cycle.
00547  *
00548  * Values:
00549  * - 00 - 1 cycle (default for all but FB_CS0 )
00550  * - 01 - 2 cycles
00551  * - 10 - 3 cycles
00552  * - 11 - 4 cycles (default for FB_CS0 )
00553  */
00554 /*@{*/
00555 #define BP_FB_CSCRn_WRAH     (16U)         /*!< Bit position for FB_CSCRn_WRAH. */
00556 #define BM_FB_CSCRn_WRAH     (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
00557 #define BS_FB_CSCRn_WRAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_WRAH. */
00558 
00559 /*! @brief Read current value of the FB_CSCRn_WRAH field. */
00560 #define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
00561 
00562 /*! @brief Format value for bitfield FB_CSCRn_WRAH. */
00563 #define BF_FB_CSCRn_WRAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
00564 
00565 /*! @brief Set the WRAH field to a new value. */
00566 #define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
00567 /*@}*/
00568 
00569 /*!
00570  * @name Register FB_CSCRn, field RDAH[19:18] (RW)
00571  *
00572  * Controls the address and attribute hold time after the termination during a
00573  * read cycle that hits in the associated chip-select's address space. The hold
00574  * time applies only at the end of a transfer. Therefore, during a burst transfer
00575  * or a transfer to a port size smaller than the transfer size, the hold time is
00576  * only added after the last bus cycle. The number of cycles the address and
00577  * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
00578  *
00579  * Values:
00580  * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
00581  * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
00582  * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
00583  * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
00584  */
00585 /*@{*/
00586 #define BP_FB_CSCRn_RDAH     (18U)         /*!< Bit position for FB_CSCRn_RDAH. */
00587 #define BM_FB_CSCRn_RDAH     (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
00588 #define BS_FB_CSCRn_RDAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_RDAH. */
00589 
00590 /*! @brief Read current value of the FB_CSCRn_RDAH field. */
00591 #define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
00592 
00593 /*! @brief Format value for bitfield FB_CSCRn_RDAH. */
00594 #define BF_FB_CSCRn_RDAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
00595 
00596 /*! @brief Set the RDAH field to a new value. */
00597 #define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
00598 /*@}*/
00599 
00600 /*!
00601  * @name Register FB_CSCRn, field ASET[21:20] (RW)
00602  *
00603  * Controls when the chip-select is asserted with respect to assertion of a
00604  * valid address and attributes.
00605  *
00606  * Values:
00607  * - 00 - Assert FB_CSn on the first rising clock edge after the address is
00608  *     asserted (default for all but FB_CS0 ).
00609  * - 01 - Assert FB_CSn on the second rising clock edge after the address is
00610  *     asserted.
00611  * - 10 - Assert FB_CSn on the third rising clock edge after the address is
00612  *     asserted.
00613  * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
00614  *     asserted (default for FB_CS0 ).
00615  */
00616 /*@{*/
00617 #define BP_FB_CSCRn_ASET     (20U)         /*!< Bit position for FB_CSCRn_ASET. */
00618 #define BM_FB_CSCRn_ASET     (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
00619 #define BS_FB_CSCRn_ASET     (2U)          /*!< Bit field size in bits for FB_CSCRn_ASET. */
00620 
00621 /*! @brief Read current value of the FB_CSCRn_ASET field. */
00622 #define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
00623 
00624 /*! @brief Format value for bitfield FB_CSCRn_ASET. */
00625 #define BF_FB_CSCRn_ASET(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
00626 
00627 /*! @brief Set the ASET field to a new value. */
00628 #define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
00629 /*@}*/
00630 
00631 /*!
00632  * @name Register FB_CSCRn, field EXTS[22] (RW)
00633  *
00634  * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
00635  * /FB_ALE is asserted.
00636  *
00637  * Values:
00638  * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
00639  * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
00640  *     edge after FB_CSn asserts.
00641  */
00642 /*@{*/
00643 #define BP_FB_CSCRn_EXTS     (22U)         /*!< Bit position for FB_CSCRn_EXTS. */
00644 #define BM_FB_CSCRn_EXTS     (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
00645 #define BS_FB_CSCRn_EXTS     (1U)          /*!< Bit field size in bits for FB_CSCRn_EXTS. */
00646 
00647 /*! @brief Read current value of the FB_CSCRn_EXTS field. */
00648 #define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
00649 
00650 /*! @brief Format value for bitfield FB_CSCRn_EXTS. */
00651 #define BF_FB_CSCRn_EXTS(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
00652 
00653 /*! @brief Set the EXTS field to a new value. */
00654 #define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
00655 /*@}*/
00656 
00657 /*!
00658  * @name Register FB_CSCRn, field SWSEN[23] (RW)
00659  *
00660  * Values:
00661  * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
00662  *     an internal transfer acknowledge is generated for all transfers.
00663  * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
00664  *     an internal transfer acknowledge is generated for burst transfer
00665  *     secondary terminations.
00666  */
00667 /*@{*/
00668 #define BP_FB_CSCRn_SWSEN    (23U)         /*!< Bit position for FB_CSCRn_SWSEN. */
00669 #define BM_FB_CSCRn_SWSEN    (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
00670 #define BS_FB_CSCRn_SWSEN    (1U)          /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
00671 
00672 /*! @brief Read current value of the FB_CSCRn_SWSEN field. */
00673 #define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
00674 
00675 /*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
00676 #define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
00677 
00678 /*! @brief Set the SWSEN field to a new value. */
00679 #define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
00680 /*@}*/
00681 
00682 /*!
00683  * @name Register FB_CSCRn, field SWS[31:26] (RW)
00684  *
00685  * Used only when the SWSEN bit is 1b. Specifies the number of wait states
00686  * inserted before an internal transfer acknowledge is generated for a burst transfer
00687  * (except for the first termination, which is controlled by WS).
00688  */
00689 /*@{*/
00690 #define BP_FB_CSCRn_SWS      (26U)         /*!< Bit position for FB_CSCRn_SWS. */
00691 #define BM_FB_CSCRn_SWS      (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
00692 #define BS_FB_CSCRn_SWS      (6U)          /*!< Bit field size in bits for FB_CSCRn_SWS. */
00693 
00694 /*! @brief Read current value of the FB_CSCRn_SWS field. */
00695 #define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
00696 
00697 /*! @brief Format value for bitfield FB_CSCRn_SWS. */
00698 #define BF_FB_CSCRn_SWS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
00699 
00700 /*! @brief Set the SWS field to a new value. */
00701 #define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
00702 /*@}*/
00703 
00704 /*******************************************************************************
00705  * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
00706  ******************************************************************************/
00707 
00708 /*!
00709  * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
00710  *
00711  * Reset value: 0x00000000U
00712  *
00713  * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
00714  * do any of the following: Write to a reserved address Write to a reserved
00715  * field in this register, or Access this register using a size other than 32 bits.
00716  */
00717 typedef union _hw_fb_cspmcr
00718 {
00719     uint32_t U;
00720     struct _hw_fb_cspmcr_bitfields
00721     {
00722         uint32_t RESERVED0 : 12;       /*!< [11:0]  */
00723         uint32_t GROUP5 : 4;           /*!< [15:12] FlexBus Signal Group 5 Multiplex
00724                                         * control */
00725         uint32_t GROUP4 : 4;           /*!< [19:16] FlexBus Signal Group 4 Multiplex
00726                                         * control */
00727         uint32_t GROUP3 : 4;           /*!< [23:20] FlexBus Signal Group 3 Multiplex
00728                                         * control */
00729         uint32_t GROUP2 : 4;           /*!< [27:24] FlexBus Signal Group 2 Multiplex
00730                                         * control */
00731         uint32_t GROUP1 : 4;           /*!< [31:28] FlexBus Signal Group 1 Multiplex
00732                                         * control */
00733     } B;
00734 } hw_fb_cspmcr_t;
00735 
00736 /*!
00737  * @name Constants and macros for entire FB_CSPMCR register
00738  */
00739 /*@{*/
00740 #define HW_FB_CSPMCR_ADDR(x)     ((x) + 0x60U)
00741 
00742 #define HW_FB_CSPMCR(x)          (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
00743 #define HW_FB_CSPMCR_RD(x)       (HW_FB_CSPMCR(x).U)
00744 #define HW_FB_CSPMCR_WR(x, v)    (HW_FB_CSPMCR(x).U = (v))
00745 #define HW_FB_CSPMCR_SET(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) |  (v)))
00746 #define HW_FB_CSPMCR_CLR(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
00747 #define HW_FB_CSPMCR_TOG(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^  (v)))
00748 /*@}*/
00749 
00750 /*
00751  * Constants & macros for individual FB_CSPMCR bitfields
00752  */
00753 
00754 /*!
00755  * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
00756  *
00757  * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
00758  * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
00759  * bus hangs during a transfer.
00760  *
00761  * Values:
00762  * - 0000 - FB_TA
00763  * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
00764  * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
00765  */
00766 /*@{*/
00767 #define BP_FB_CSPMCR_GROUP5  (12U)         /*!< Bit position for FB_CSPMCR_GROUP5. */
00768 #define BM_FB_CSPMCR_GROUP5  (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
00769 #define BS_FB_CSPMCR_GROUP5  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
00770 
00771 /*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
00772 #define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
00773 
00774 /*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
00775 #define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
00776 
00777 /*! @brief Set the GROUP5 field to a new value. */
00778 #define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
00779 /*@}*/
00780 
00781 /*!
00782  * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
00783  *
00784  * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
00785  *
00786  * Values:
00787  * - 0000 - FB_TBST
00788  * - 0001 - FB_CS2
00789  * - 0010 - FB_BE_15_8
00790  */
00791 /*@{*/
00792 #define BP_FB_CSPMCR_GROUP4  (16U)         /*!< Bit position for FB_CSPMCR_GROUP4. */
00793 #define BM_FB_CSPMCR_GROUP4  (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
00794 #define BS_FB_CSPMCR_GROUP4  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
00795 
00796 /*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
00797 #define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
00798 
00799 /*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
00800 #define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
00801 
00802 /*! @brief Set the GROUP4 field to a new value. */
00803 #define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
00804 /*@}*/
00805 
00806 /*!
00807  * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
00808  *
00809  * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
00810  *
00811  * Values:
00812  * - 0000 - FB_CS5
00813  * - 0001 - FB_TSIZ1
00814  * - 0010 - FB_BE_23_16
00815  */
00816 /*@{*/
00817 #define BP_FB_CSPMCR_GROUP3  (20U)         /*!< Bit position for FB_CSPMCR_GROUP3. */
00818 #define BM_FB_CSPMCR_GROUP3  (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
00819 #define BS_FB_CSPMCR_GROUP3  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
00820 
00821 /*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
00822 #define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
00823 
00824 /*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
00825 #define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
00826 
00827 /*! @brief Set the GROUP3 field to a new value. */
00828 #define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
00829 /*@}*/
00830 
00831 /*!
00832  * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
00833  *
00834  * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
00835  *
00836  * Values:
00837  * - 0000 - FB_CS4
00838  * - 0001 - FB_TSIZ0
00839  * - 0010 - FB_BE_31_24
00840  */
00841 /*@{*/
00842 #define BP_FB_CSPMCR_GROUP2  (24U)         /*!< Bit position for FB_CSPMCR_GROUP2. */
00843 #define BM_FB_CSPMCR_GROUP2  (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
00844 #define BS_FB_CSPMCR_GROUP2  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
00845 
00846 /*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
00847 #define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
00848 
00849 /*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
00850 #define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
00851 
00852 /*! @brief Set the GROUP2 field to a new value. */
00853 #define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
00854 /*@}*/
00855 
00856 /*!
00857  * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
00858  *
00859  * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
00860  *
00861  * Values:
00862  * - 0000 - FB_ALE
00863  * - 0001 - FB_CS1
00864  * - 0010 - FB_TS
00865  */
00866 /*@{*/
00867 #define BP_FB_CSPMCR_GROUP1  (28U)         /*!< Bit position for FB_CSPMCR_GROUP1. */
00868 #define BM_FB_CSPMCR_GROUP1  (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
00869 #define BS_FB_CSPMCR_GROUP1  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
00870 
00871 /*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
00872 #define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
00873 
00874 /*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
00875 #define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
00876 
00877 /*! @brief Set the GROUP1 field to a new value. */
00878 #define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
00879 /*@}*/
00880 
00881 /*******************************************************************************
00882  * hw_fb_t - module struct
00883  ******************************************************************************/
00884 /*!
00885  * @brief All FB module registers.
00886  */
00887 #pragma pack(1)
00888 typedef struct _hw_fb
00889 {
00890     struct {
00891         __IO hw_fb_csarn_t CSARn ;          /*!< [0x0] Chip Select Address Register */
00892         __IO hw_fb_csmrn_t CSMRn ;          /*!< [0x4] Chip Select Mask Register */
00893         __IO hw_fb_cscrn_t CSCRn ;          /*!< [0x8] Chip Select Control Register */
00894     } CS[6];
00895     uint8_t _reserved0[24];
00896     __IO hw_fb_cspmcr_t CSPMCR ;            /*!< [0x60] Chip Select port Multiplexing Control Register */
00897 } hw_fb_t;
00898 #pragma pack()
00899 
00900 /*! @brief Macro to access all FB registers. */
00901 /*! @param x FB module instance base address. */
00902 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00903  *     use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
00904 #define HW_FB(x)       (*(hw_fb_t *)(x))
00905 
00906 #endif /* __HW_FB_REGISTERS_H__ */
00907 /* EOF */