MK64F12_enet.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_ENET_REGISTERS_H__
00081 #define __HW_ENET_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 ENET
00088  *
00089  * Ethernet MAC-NET Core
00090  *
00091  * Registers defined in this header file:
00092  * - HW_ENET_EIR - Interrupt Event Register
00093  * - HW_ENET_EIMR - Interrupt Mask Register
00094  * - HW_ENET_RDAR - Receive Descriptor Active Register
00095  * - HW_ENET_TDAR - Transmit Descriptor Active Register
00096  * - HW_ENET_ECR - Ethernet Control Register
00097  * - HW_ENET_MMFR - MII Management Frame Register
00098  * - HW_ENET_MSCR - MII Speed Control Register
00099  * - HW_ENET_MIBC - MIB Control Register
00100  * - HW_ENET_RCR - Receive Control Register
00101  * - HW_ENET_TCR - Transmit Control Register
00102  * - HW_ENET_PALR - Physical Address Lower Register
00103  * - HW_ENET_PAUR - Physical Address Upper Register
00104  * - HW_ENET_OPD - Opcode/Pause Duration Register
00105  * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
00106  * - HW_ENET_IALR - Descriptor Individual Lower Address Register
00107  * - HW_ENET_GAUR - Descriptor Group Upper Address Register
00108  * - HW_ENET_GALR - Descriptor Group Lower Address Register
00109  * - HW_ENET_TFWR - Transmit FIFO Watermark Register
00110  * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
00111  * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
00112  * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
00113  * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
00114  * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
00115  * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
00116  * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
00117  * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
00118  * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
00119  * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
00120  * - HW_ENET_TIPG - Transmit Inter-Packet Gap
00121  * - HW_ENET_FTRL - Frame Truncation Length
00122  * - HW_ENET_TACC - Transmit Accelerator Function Configuration
00123  * - HW_ENET_RACC - Receive Accelerator Function Configuration
00124  * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
00125  * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
00126  * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
00127  * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
00128  * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
00129  * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
00130  * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
00131  * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
00132  * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
00133  * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
00134  * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
00135  * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
00136  * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
00137  * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
00138  * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
00139  * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
00140  * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
00141  * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
00142  * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
00143  * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
00144  * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
00145  * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
00146  * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
00147  * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
00148  * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
00149  * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
00150  * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
00151  * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
00152  * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
00153  * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
00154  * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
00155  * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
00156  * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
00157  * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
00158  * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
00159  * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
00160  * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
00161  * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
00162  * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
00163  * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
00164  * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
00165  * - HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
00166  * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
00167  * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
00168  * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
00169  * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
00170  * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
00171  * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
00172  * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
00173  * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
00174  * - HW_ENET_ATCR - Adjustable Timer Control Register
00175  * - HW_ENET_ATVR - Timer Value Register
00176  * - HW_ENET_ATOFF - Timer Offset Register
00177  * - HW_ENET_ATPER - Timer Period Register
00178  * - HW_ENET_ATCOR - Timer Correction Register
00179  * - HW_ENET_ATINC - Time-Stamping Clock Period Register
00180  * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
00181  * - HW_ENET_TGSR - Timer Global Status Register
00182  * - HW_ENET_TCSRn - Timer Control Status Register
00183  * - HW_ENET_TCCRn - Timer Compare Capture Register
00184  *
00185  * - hw_enet_t - Struct containing all module registers.
00186  */
00187 
00188 #define HW_ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
00189 
00190 /*******************************************************************************
00191  * HW_ENET_EIR - Interrupt Event Register
00192  ******************************************************************************/
00193 
00194 /*!
00195  * @brief HW_ENET_EIR - Interrupt Event Register (RW)
00196  *
00197  * Reset value: 0x00000000U
00198  *
00199  * When an event occurs that sets a bit in EIR, an interrupt occurs if the
00200  * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
00201  * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
00202  * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
00203  * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
00204  * Legacy mode does not require these flags to be enabled.
00205  */
00206 typedef union _hw_enet_eir
00207 {
00208     uint32_t U;
00209     struct _hw_enet_eir_bitfields
00210     {
00211         uint32_t RESERVED0 : 15;       /*!< [14:0]  */
00212         uint32_t TS_TIMER : 1;         /*!< [15] Timestamp Timer */
00213         uint32_t TS_AVAIL : 1;         /*!< [16] Transmit Timestamp Available */
00214         uint32_t WAKEUP : 1;           /*!< [17] Node Wakeup Request Indication */
00215         uint32_t PLR : 1;              /*!< [18] Payload Receive Error */
00216         uint32_t UN : 1;               /*!< [19] Transmit FIFO Underrun */
00217         uint32_t RL : 1;               /*!< [20] Collision Retry Limit */
00218         uint32_t LC : 1;               /*!< [21] Late Collision */
00219         uint32_t EBERR : 1;            /*!< [22] Ethernet Bus Error */
00220         uint32_t MII : 1;              /*!< [23] MII Interrupt. */
00221         uint32_t RXB : 1;              /*!< [24] Receive Buffer Interrupt */
00222         uint32_t RXF : 1;              /*!< [25] Receive Frame Interrupt */
00223         uint32_t TXB : 1;              /*!< [26] Transmit Buffer Interrupt */
00224         uint32_t TXF : 1;              /*!< [27] Transmit Frame Interrupt */
00225         uint32_t GRA : 1;              /*!< [28] Graceful Stop Complete */
00226         uint32_t BABT : 1;             /*!< [29] Babbling Transmit Error */
00227         uint32_t BABR : 1;             /*!< [30] Babbling Receive Error */
00228         uint32_t RESERVED1 : 1;        /*!< [31]  */
00229     } B;
00230 } hw_enet_eir_t;
00231 
00232 /*!
00233  * @name Constants and macros for entire ENET_EIR register
00234  */
00235 /*@{*/
00236 #define HW_ENET_EIR_ADDR(x)      ((x) + 0x4U)
00237 
00238 #define HW_ENET_EIR(x)           (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
00239 #define HW_ENET_EIR_RD(x)        (HW_ENET_EIR(x).U)
00240 #define HW_ENET_EIR_WR(x, v)     (HW_ENET_EIR(x).U = (v))
00241 #define HW_ENET_EIR_SET(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) |  (v)))
00242 #define HW_ENET_EIR_CLR(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
00243 #define HW_ENET_EIR_TOG(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^  (v)))
00244 /*@}*/
00245 
00246 /*
00247  * Constants & macros for individual ENET_EIR bitfields
00248  */
00249 
00250 /*!
00251  * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
00252  *
00253  * The adjustable timer reached the period event. A period event interrupt can
00254  * be generated if ATCR[PEREN] is set and the timer wraps according to the
00255  * periodic setting in the ATPER register. Set the timer period value before setting
00256  * ATCR[PEREN].
00257  */
00258 /*@{*/
00259 #define BP_ENET_EIR_TS_TIMER (15U)         /*!< Bit position for ENET_EIR_TS_TIMER. */
00260 #define BM_ENET_EIR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIR_TS_TIMER. */
00261 #define BS_ENET_EIR_TS_TIMER (1U)          /*!< Bit field size in bits for ENET_EIR_TS_TIMER. */
00262 
00263 /*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
00264 #define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
00265 
00266 /*! @brief Format value for bitfield ENET_EIR_TS_TIMER. */
00267 #define BF_ENET_EIR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER)
00268 
00269 /*! @brief Set the TS_TIMER field to a new value. */
00270 #define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
00271 /*@}*/
00272 
00273 /*!
00274  * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
00275  *
00276  * Indicates that the timestamp of the last transmitted timing frame is
00277  * available in the ATSTMP register.
00278  */
00279 /*@{*/
00280 #define BP_ENET_EIR_TS_AVAIL (16U)         /*!< Bit position for ENET_EIR_TS_AVAIL. */
00281 #define BM_ENET_EIR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIR_TS_AVAIL. */
00282 #define BS_ENET_EIR_TS_AVAIL (1U)          /*!< Bit field size in bits for ENET_EIR_TS_AVAIL. */
00283 
00284 /*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
00285 #define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
00286 
00287 /*! @brief Format value for bitfield ENET_EIR_TS_AVAIL. */
00288 #define BF_ENET_EIR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL)
00289 
00290 /*! @brief Set the TS_AVAIL field to a new value. */
00291 #define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
00292 /*@}*/
00293 
00294 /*!
00295  * @name Register ENET_EIR, field WAKEUP[17] (W1C)
00296  *
00297  * Read-only status bit to indicate that a magic packet has been detected. Will
00298  * act only if ECR[MAGICEN] is set.
00299  */
00300 /*@{*/
00301 #define BP_ENET_EIR_WAKEUP   (17U)         /*!< Bit position for ENET_EIR_WAKEUP. */
00302 #define BM_ENET_EIR_WAKEUP   (0x00020000U) /*!< Bit mask for ENET_EIR_WAKEUP. */
00303 #define BS_ENET_EIR_WAKEUP   (1U)          /*!< Bit field size in bits for ENET_EIR_WAKEUP. */
00304 
00305 /*! @brief Read current value of the ENET_EIR_WAKEUP field. */
00306 #define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
00307 
00308 /*! @brief Format value for bitfield ENET_EIR_WAKEUP. */
00309 #define BF_ENET_EIR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP)
00310 
00311 /*! @brief Set the WAKEUP field to a new value. */
00312 #define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
00313 /*@}*/
00314 
00315 /*!
00316  * @name Register ENET_EIR, field PLR[18] (W1C)
00317  *
00318  * Indicates a frame was received with a payload length error. See Frame
00319  * Length/Type Verification: Payload Length Check for more information.
00320  */
00321 /*@{*/
00322 #define BP_ENET_EIR_PLR      (18U)         /*!< Bit position for ENET_EIR_PLR. */
00323 #define BM_ENET_EIR_PLR      (0x00040000U) /*!< Bit mask for ENET_EIR_PLR. */
00324 #define BS_ENET_EIR_PLR      (1U)          /*!< Bit field size in bits for ENET_EIR_PLR. */
00325 
00326 /*! @brief Read current value of the ENET_EIR_PLR field. */
00327 #define BR_ENET_EIR_PLR(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
00328 
00329 /*! @brief Format value for bitfield ENET_EIR_PLR. */
00330 #define BF_ENET_EIR_PLR(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR)
00331 
00332 /*! @brief Set the PLR field to a new value. */
00333 #define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
00334 /*@}*/
00335 
00336 /*!
00337  * @name Register ENET_EIR, field UN[19] (W1C)
00338  *
00339  * Indicates the transmit FIFO became empty before the complete frame was
00340  * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
00341  * frame is discarded.
00342  */
00343 /*@{*/
00344 #define BP_ENET_EIR_UN       (19U)         /*!< Bit position for ENET_EIR_UN. */
00345 #define BM_ENET_EIR_UN       (0x00080000U) /*!< Bit mask for ENET_EIR_UN. */
00346 #define BS_ENET_EIR_UN       (1U)          /*!< Bit field size in bits for ENET_EIR_UN. */
00347 
00348 /*! @brief Read current value of the ENET_EIR_UN field. */
00349 #define BR_ENET_EIR_UN(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
00350 
00351 /*! @brief Format value for bitfield ENET_EIR_UN. */
00352 #define BF_ENET_EIR_UN(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN)
00353 
00354 /*! @brief Set the UN field to a new value. */
00355 #define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
00356 /*@}*/
00357 
00358 /*!
00359  * @name Register ENET_EIR, field RL[20] (W1C)
00360  *
00361  * Indicates a collision occurred on each of 16 successive attempts to transmit
00362  * the frame. The frame is discarded without being transmitted and transmission
00363  * of the next frame commences. This error can only occur in half-duplex mode.
00364  */
00365 /*@{*/
00366 #define BP_ENET_EIR_RL       (20U)         /*!< Bit position for ENET_EIR_RL. */
00367 #define BM_ENET_EIR_RL       (0x00100000U) /*!< Bit mask for ENET_EIR_RL. */
00368 #define BS_ENET_EIR_RL       (1U)          /*!< Bit field size in bits for ENET_EIR_RL. */
00369 
00370 /*! @brief Read current value of the ENET_EIR_RL field. */
00371 #define BR_ENET_EIR_RL(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
00372 
00373 /*! @brief Format value for bitfield ENET_EIR_RL. */
00374 #define BF_ENET_EIR_RL(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL)
00375 
00376 /*! @brief Set the RL field to a new value. */
00377 #define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
00378 /*@}*/
00379 
00380 /*!
00381  * @name Register ENET_EIR, field LC[21] (W1C)
00382  *
00383  * Indicates a collision occurred beyond the collision window (slot time) in
00384  * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
00385  * frame is discarded.
00386  */
00387 /*@{*/
00388 #define BP_ENET_EIR_LC       (21U)         /*!< Bit position for ENET_EIR_LC. */
00389 #define BM_ENET_EIR_LC       (0x00200000U) /*!< Bit mask for ENET_EIR_LC. */
00390 #define BS_ENET_EIR_LC       (1U)          /*!< Bit field size in bits for ENET_EIR_LC. */
00391 
00392 /*! @brief Read current value of the ENET_EIR_LC field. */
00393 #define BR_ENET_EIR_LC(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
00394 
00395 /*! @brief Format value for bitfield ENET_EIR_LC. */
00396 #define BF_ENET_EIR_LC(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC)
00397 
00398 /*! @brief Set the LC field to a new value. */
00399 #define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
00400 /*@}*/
00401 
00402 /*!
00403  * @name Register ENET_EIR, field EBERR[22] (W1C)
00404  *
00405  * Indicates a system bus error occurred when a uDMA transaction is underway.
00406  * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
00407  * MAC. When this occurs, software must ensure proper actions, possibly resetting
00408  * the system, to resume normal operation.
00409  */
00410 /*@{*/
00411 #define BP_ENET_EIR_EBERR    (22U)         /*!< Bit position for ENET_EIR_EBERR. */
00412 #define BM_ENET_EIR_EBERR    (0x00400000U) /*!< Bit mask for ENET_EIR_EBERR. */
00413 #define BS_ENET_EIR_EBERR    (1U)          /*!< Bit field size in bits for ENET_EIR_EBERR. */
00414 
00415 /*! @brief Read current value of the ENET_EIR_EBERR field. */
00416 #define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
00417 
00418 /*! @brief Format value for bitfield ENET_EIR_EBERR. */
00419 #define BF_ENET_EIR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR)
00420 
00421 /*! @brief Set the EBERR field to a new value. */
00422 #define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
00423 /*@}*/
00424 
00425 /*!
00426  * @name Register ENET_EIR, field MII[23] (W1C)
00427  *
00428  * Indicates that the MII has completed the data transfer requested.
00429  */
00430 /*@{*/
00431 #define BP_ENET_EIR_MII      (23U)         /*!< Bit position for ENET_EIR_MII. */
00432 #define BM_ENET_EIR_MII      (0x00800000U) /*!< Bit mask for ENET_EIR_MII. */
00433 #define BS_ENET_EIR_MII      (1U)          /*!< Bit field size in bits for ENET_EIR_MII. */
00434 
00435 /*! @brief Read current value of the ENET_EIR_MII field. */
00436 #define BR_ENET_EIR_MII(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
00437 
00438 /*! @brief Format value for bitfield ENET_EIR_MII. */
00439 #define BF_ENET_EIR_MII(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII)
00440 
00441 /*! @brief Set the MII field to a new value. */
00442 #define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
00443 /*@}*/
00444 
00445 /*!
00446  * @name Register ENET_EIR, field RXB[24] (W1C)
00447  *
00448  * Indicates a receive buffer descriptor is not the last in the frame has been
00449  * updated.
00450  */
00451 /*@{*/
00452 #define BP_ENET_EIR_RXB      (24U)         /*!< Bit position for ENET_EIR_RXB. */
00453 #define BM_ENET_EIR_RXB      (0x01000000U) /*!< Bit mask for ENET_EIR_RXB. */
00454 #define BS_ENET_EIR_RXB      (1U)          /*!< Bit field size in bits for ENET_EIR_RXB. */
00455 
00456 /*! @brief Read current value of the ENET_EIR_RXB field. */
00457 #define BR_ENET_EIR_RXB(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
00458 
00459 /*! @brief Format value for bitfield ENET_EIR_RXB. */
00460 #define BF_ENET_EIR_RXB(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB)
00461 
00462 /*! @brief Set the RXB field to a new value. */
00463 #define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
00464 /*@}*/
00465 
00466 /*!
00467  * @name Register ENET_EIR, field RXF[25] (W1C)
00468  *
00469  * Indicates a frame has been received and the last corresponding buffer
00470  * descriptor has been updated.
00471  */
00472 /*@{*/
00473 #define BP_ENET_EIR_RXF      (25U)         /*!< Bit position for ENET_EIR_RXF. */
00474 #define BM_ENET_EIR_RXF      (0x02000000U) /*!< Bit mask for ENET_EIR_RXF. */
00475 #define BS_ENET_EIR_RXF      (1U)          /*!< Bit field size in bits for ENET_EIR_RXF. */
00476 
00477 /*! @brief Read current value of the ENET_EIR_RXF field. */
00478 #define BR_ENET_EIR_RXF(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
00479 
00480 /*! @brief Format value for bitfield ENET_EIR_RXF. */
00481 #define BF_ENET_EIR_RXF(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF)
00482 
00483 /*! @brief Set the RXF field to a new value. */
00484 #define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
00485 /*@}*/
00486 
00487 /*!
00488  * @name Register ENET_EIR, field TXB[26] (W1C)
00489  *
00490  * Indicates a transmit buffer descriptor has been updated.
00491  */
00492 /*@{*/
00493 #define BP_ENET_EIR_TXB      (26U)         /*!< Bit position for ENET_EIR_TXB. */
00494 #define BM_ENET_EIR_TXB      (0x04000000U) /*!< Bit mask for ENET_EIR_TXB. */
00495 #define BS_ENET_EIR_TXB      (1U)          /*!< Bit field size in bits for ENET_EIR_TXB. */
00496 
00497 /*! @brief Read current value of the ENET_EIR_TXB field. */
00498 #define BR_ENET_EIR_TXB(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
00499 
00500 /*! @brief Format value for bitfield ENET_EIR_TXB. */
00501 #define BF_ENET_EIR_TXB(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB)
00502 
00503 /*! @brief Set the TXB field to a new value. */
00504 #define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
00505 /*@}*/
00506 
00507 /*!
00508  * @name Register ENET_EIR, field TXF[27] (W1C)
00509  *
00510  * Indicates a frame has been transmitted and the last corresponding buffer
00511  * descriptor has been updated.
00512  */
00513 /*@{*/
00514 #define BP_ENET_EIR_TXF      (27U)         /*!< Bit position for ENET_EIR_TXF. */
00515 #define BM_ENET_EIR_TXF      (0x08000000U) /*!< Bit mask for ENET_EIR_TXF. */
00516 #define BS_ENET_EIR_TXF      (1U)          /*!< Bit field size in bits for ENET_EIR_TXF. */
00517 
00518 /*! @brief Read current value of the ENET_EIR_TXF field. */
00519 #define BR_ENET_EIR_TXF(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
00520 
00521 /*! @brief Format value for bitfield ENET_EIR_TXF. */
00522 #define BF_ENET_EIR_TXF(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF)
00523 
00524 /*! @brief Set the TXF field to a new value. */
00525 #define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
00526 /*@}*/
00527 
00528 /*!
00529  * @name Register ENET_EIR, field GRA[28] (W1C)
00530  *
00531  * This interrupt is asserted after the transmitter is put into a pause state
00532  * after completion of the frame currently being transmitted. See Graceful Transmit
00533  * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
00534  * asserted only when the TX transitions into the stopped state. If this bit is
00535  * cleared by writing 1 and the TX is still stopped, the bit is not set again.
00536  */
00537 /*@{*/
00538 #define BP_ENET_EIR_GRA      (28U)         /*!< Bit position for ENET_EIR_GRA. */
00539 #define BM_ENET_EIR_GRA      (0x10000000U) /*!< Bit mask for ENET_EIR_GRA. */
00540 #define BS_ENET_EIR_GRA      (1U)          /*!< Bit field size in bits for ENET_EIR_GRA. */
00541 
00542 /*! @brief Read current value of the ENET_EIR_GRA field. */
00543 #define BR_ENET_EIR_GRA(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
00544 
00545 /*! @brief Format value for bitfield ENET_EIR_GRA. */
00546 #define BF_ENET_EIR_GRA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA)
00547 
00548 /*! @brief Set the GRA field to a new value. */
00549 #define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
00550 /*@}*/
00551 
00552 /*!
00553  * @name Register ENET_EIR, field BABT[29] (W1C)
00554  *
00555  * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
00556  * this condition is caused when a frame that is too long is placed into the
00557  * transmit data buffer(s). Truncation does not occur.
00558  */
00559 /*@{*/
00560 #define BP_ENET_EIR_BABT     (29U)         /*!< Bit position for ENET_EIR_BABT. */
00561 #define BM_ENET_EIR_BABT     (0x20000000U) /*!< Bit mask for ENET_EIR_BABT. */
00562 #define BS_ENET_EIR_BABT     (1U)          /*!< Bit field size in bits for ENET_EIR_BABT. */
00563 
00564 /*! @brief Read current value of the ENET_EIR_BABT field. */
00565 #define BR_ENET_EIR_BABT(x)  (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
00566 
00567 /*! @brief Format value for bitfield ENET_EIR_BABT. */
00568 #define BF_ENET_EIR_BABT(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT)
00569 
00570 /*! @brief Set the BABT field to a new value. */
00571 #define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
00572 /*@}*/
00573 
00574 /*!
00575  * @name Register ENET_EIR, field BABR[30] (W1C)
00576  *
00577  * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
00578  */
00579 /*@{*/
00580 #define BP_ENET_EIR_BABR     (30U)         /*!< Bit position for ENET_EIR_BABR. */
00581 #define BM_ENET_EIR_BABR     (0x40000000U) /*!< Bit mask for ENET_EIR_BABR. */
00582 #define BS_ENET_EIR_BABR     (1U)          /*!< Bit field size in bits for ENET_EIR_BABR. */
00583 
00584 /*! @brief Read current value of the ENET_EIR_BABR field. */
00585 #define BR_ENET_EIR_BABR(x)  (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
00586 
00587 /*! @brief Format value for bitfield ENET_EIR_BABR. */
00588 #define BF_ENET_EIR_BABR(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR)
00589 
00590 /*! @brief Set the BABR field to a new value. */
00591 #define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
00592 /*@}*/
00593 
00594 /*******************************************************************************
00595  * HW_ENET_EIMR - Interrupt Mask Register
00596  ******************************************************************************/
00597 
00598 /*!
00599  * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
00600  *
00601  * Reset value: 0x00000000U
00602  *
00603  * EIMR controls which interrupt events are allowed to generate actual
00604  * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
00605  * and EIMR registers are set, an interrupt is generated. The interrupt signal
00606  * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
00607  * 0 is written to the EIMR field.
00608  */
00609 typedef union _hw_enet_eimr
00610 {
00611     uint32_t U;
00612     struct _hw_enet_eimr_bitfields
00613     {
00614         uint32_t RESERVED0 : 15;       /*!< [14:0]  */
00615         uint32_t TS_TIMER : 1;         /*!< [15] TS_TIMER Interrupt Mask */
00616         uint32_t TS_AVAIL : 1;         /*!< [16] TS_AVAIL Interrupt Mask */
00617         uint32_t WAKEUP : 1;           /*!< [17] WAKEUP Interrupt Mask */
00618         uint32_t PLR : 1;              /*!< [18] PLR Interrupt Mask */
00619         uint32_t UN : 1;               /*!< [19] UN Interrupt Mask */
00620         uint32_t RL : 1;               /*!< [20] RL Interrupt Mask */
00621         uint32_t LC : 1;               /*!< [21] LC Interrupt Mask */
00622         uint32_t EBERR : 1;            /*!< [22] EBERR Interrupt Mask */
00623         uint32_t MII : 1;              /*!< [23] MII Interrupt Mask */
00624         uint32_t RXB : 1;              /*!< [24] RXB Interrupt Mask */
00625         uint32_t RXF : 1;              /*!< [25] RXF Interrupt Mask */
00626         uint32_t TXB : 1;              /*!< [26] TXB Interrupt Mask */
00627         uint32_t TXF : 1;              /*!< [27] TXF Interrupt Mask */
00628         uint32_t GRA : 1;              /*!< [28] GRA Interrupt Mask */
00629         uint32_t BABT : 1;             /*!< [29] BABT Interrupt Mask */
00630         uint32_t BABR : 1;             /*!< [30] BABR Interrupt Mask */
00631         uint32_t RESERVED1 : 1;        /*!< [31]  */
00632     } B;
00633 } hw_enet_eimr_t;
00634 
00635 /*!
00636  * @name Constants and macros for entire ENET_EIMR register
00637  */
00638 /*@{*/
00639 #define HW_ENET_EIMR_ADDR(x)     ((x) + 0x8U)
00640 
00641 #define HW_ENET_EIMR(x)          (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
00642 #define HW_ENET_EIMR_RD(x)       (HW_ENET_EIMR(x).U)
00643 #define HW_ENET_EIMR_WR(x, v)    (HW_ENET_EIMR(x).U = (v))
00644 #define HW_ENET_EIMR_SET(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) |  (v)))
00645 #define HW_ENET_EIMR_CLR(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
00646 #define HW_ENET_EIMR_TOG(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^  (v)))
00647 /*@}*/
00648 
00649 /*
00650  * Constants & macros for individual ENET_EIMR bitfields
00651  */
00652 
00653 /*!
00654  * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
00655  *
00656  * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
00657  * an interrupt condition can generate an interrupt. At every module clock, the
00658  * EIR samples the signal generated by the interrupting source. The corresponding
00659  * EIR TS_TIMER field reflects the state of the interrupt signal even if the
00660  * corresponding EIMR field is cleared.
00661  */
00662 /*@{*/
00663 #define BP_ENET_EIMR_TS_TIMER (15U)        /*!< Bit position for ENET_EIMR_TS_TIMER. */
00664 #define BM_ENET_EIMR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIMR_TS_TIMER. */
00665 #define BS_ENET_EIMR_TS_TIMER (1U)         /*!< Bit field size in bits for ENET_EIMR_TS_TIMER. */
00666 
00667 /*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
00668 #define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
00669 
00670 /*! @brief Format value for bitfield ENET_EIMR_TS_TIMER. */
00671 #define BF_ENET_EIMR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER)
00672 
00673 /*! @brief Set the TS_TIMER field to a new value. */
00674 #define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
00675 /*@}*/
00676 
00677 /*!
00678  * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
00679  *
00680  * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
00681  * an interrupt condition can generate an interrupt. At every module clock, the
00682  * EIR samples the signal generated by the interrupting source. The corresponding
00683  * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
00684  * corresponding EIMR field is cleared.
00685  */
00686 /*@{*/
00687 #define BP_ENET_EIMR_TS_AVAIL (16U)        /*!< Bit position for ENET_EIMR_TS_AVAIL. */
00688 #define BM_ENET_EIMR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIMR_TS_AVAIL. */
00689 #define BS_ENET_EIMR_TS_AVAIL (1U)         /*!< Bit field size in bits for ENET_EIMR_TS_AVAIL. */
00690 
00691 /*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
00692 #define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
00693 
00694 /*! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. */
00695 #define BF_ENET_EIMR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL)
00696 
00697 /*! @brief Set the TS_AVAIL field to a new value. */
00698 #define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
00699 /*@}*/
00700 
00701 /*!
00702  * @name Register ENET_EIMR, field WAKEUP[17] (RW)
00703  *
00704  * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
00705  * an interrupt condition can generate an interrupt. At every module clock, the
00706  * EIR samples the signal generated by the interrupting source. The corresponding
00707  * EIR WAKEUP field reflects the state of the interrupt signal even if the
00708  * corresponding EIMR field is cleared.
00709  */
00710 /*@{*/
00711 #define BP_ENET_EIMR_WAKEUP  (17U)         /*!< Bit position for ENET_EIMR_WAKEUP. */
00712 #define BM_ENET_EIMR_WAKEUP  (0x00020000U) /*!< Bit mask for ENET_EIMR_WAKEUP. */
00713 #define BS_ENET_EIMR_WAKEUP  (1U)          /*!< Bit field size in bits for ENET_EIMR_WAKEUP. */
00714 
00715 /*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
00716 #define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
00717 
00718 /*! @brief Format value for bitfield ENET_EIMR_WAKEUP. */
00719 #define BF_ENET_EIMR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP)
00720 
00721 /*! @brief Set the WAKEUP field to a new value. */
00722 #define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
00723 /*@}*/
00724 
00725 /*!
00726  * @name Register ENET_EIMR, field PLR[18] (RW)
00727  *
00728  * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
00729  * condition can generate an interrupt. At every module clock, the EIR samples
00730  * the signal generated by the interrupting source. The corresponding EIR PLR field
00731  * reflects the state of the interrupt signal even if the corresponding EIMR
00732  * field is cleared.
00733  */
00734 /*@{*/
00735 #define BP_ENET_EIMR_PLR     (18U)         /*!< Bit position for ENET_EIMR_PLR. */
00736 #define BM_ENET_EIMR_PLR     (0x00040000U) /*!< Bit mask for ENET_EIMR_PLR. */
00737 #define BS_ENET_EIMR_PLR     (1U)          /*!< Bit field size in bits for ENET_EIMR_PLR. */
00738 
00739 /*! @brief Read current value of the ENET_EIMR_PLR field. */
00740 #define BR_ENET_EIMR_PLR(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
00741 
00742 /*! @brief Format value for bitfield ENET_EIMR_PLR. */
00743 #define BF_ENET_EIMR_PLR(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR)
00744 
00745 /*! @brief Set the PLR field to a new value. */
00746 #define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
00747 /*@}*/
00748 
00749 /*!
00750  * @name Register ENET_EIMR, field UN[19] (RW)
00751  *
00752  * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
00753  * condition can generate an interrupt. At every module clock, the EIR samples the
00754  * signal generated by the interrupting source. The corresponding EIR UN field
00755  * reflects the state of the interrupt signal even if the corresponding EIMR field
00756  * is cleared.
00757  */
00758 /*@{*/
00759 #define BP_ENET_EIMR_UN      (19U)         /*!< Bit position for ENET_EIMR_UN. */
00760 #define BM_ENET_EIMR_UN      (0x00080000U) /*!< Bit mask for ENET_EIMR_UN. */
00761 #define BS_ENET_EIMR_UN      (1U)          /*!< Bit field size in bits for ENET_EIMR_UN. */
00762 
00763 /*! @brief Read current value of the ENET_EIMR_UN field. */
00764 #define BR_ENET_EIMR_UN(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
00765 
00766 /*! @brief Format value for bitfield ENET_EIMR_UN. */
00767 #define BF_ENET_EIMR_UN(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN)
00768 
00769 /*! @brief Set the UN field to a new value. */
00770 #define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
00771 /*@}*/
00772 
00773 /*!
00774  * @name Register ENET_EIMR, field RL[20] (RW)
00775  *
00776  * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
00777  * condition can generate an interrupt. At every module clock, the EIR samples the
00778  * signal generated by the interrupting source. The corresponding EIR RL field
00779  * reflects the state of the interrupt signal even if the corresponding EIMR field
00780  * is cleared.
00781  */
00782 /*@{*/
00783 #define BP_ENET_EIMR_RL      (20U)         /*!< Bit position for ENET_EIMR_RL. */
00784 #define BM_ENET_EIMR_RL      (0x00100000U) /*!< Bit mask for ENET_EIMR_RL. */
00785 #define BS_ENET_EIMR_RL      (1U)          /*!< Bit field size in bits for ENET_EIMR_RL. */
00786 
00787 /*! @brief Read current value of the ENET_EIMR_RL field. */
00788 #define BR_ENET_EIMR_RL(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
00789 
00790 /*! @brief Format value for bitfield ENET_EIMR_RL. */
00791 #define BF_ENET_EIMR_RL(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL)
00792 
00793 /*! @brief Set the RL field to a new value. */
00794 #define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
00795 /*@}*/
00796 
00797 /*!
00798  * @name Register ENET_EIMR, field LC[21] (RW)
00799  *
00800  * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
00801  * condition can generate an interrupt. At every module clock, the EIR samples the
00802  * signal generated by the interrupting source. The corresponding EIR LC field
00803  * reflects the state of the interrupt signal even if the corresponding EIMR field
00804  * is cleared.
00805  */
00806 /*@{*/
00807 #define BP_ENET_EIMR_LC      (21U)         /*!< Bit position for ENET_EIMR_LC. */
00808 #define BM_ENET_EIMR_LC      (0x00200000U) /*!< Bit mask for ENET_EIMR_LC. */
00809 #define BS_ENET_EIMR_LC      (1U)          /*!< Bit field size in bits for ENET_EIMR_LC. */
00810 
00811 /*! @brief Read current value of the ENET_EIMR_LC field. */
00812 #define BR_ENET_EIMR_LC(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
00813 
00814 /*! @brief Format value for bitfield ENET_EIMR_LC. */
00815 #define BF_ENET_EIMR_LC(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC)
00816 
00817 /*! @brief Set the LC field to a new value. */
00818 #define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
00819 /*@}*/
00820 
00821 /*!
00822  * @name Register ENET_EIMR, field EBERR[22] (RW)
00823  *
00824  * Corresponds to interrupt source EIR[EBERR] and determines whether an
00825  * interrupt condition can generate an interrupt. At every module clock, the EIR samples
00826  * the signal generated by the interrupting source. The corresponding EIR EBERR
00827  * field reflects the state of the interrupt signal even if the corresponding EIMR
00828  * field is cleared.
00829  */
00830 /*@{*/
00831 #define BP_ENET_EIMR_EBERR   (22U)         /*!< Bit position for ENET_EIMR_EBERR. */
00832 #define BM_ENET_EIMR_EBERR   (0x00400000U) /*!< Bit mask for ENET_EIMR_EBERR. */
00833 #define BS_ENET_EIMR_EBERR   (1U)          /*!< Bit field size in bits for ENET_EIMR_EBERR. */
00834 
00835 /*! @brief Read current value of the ENET_EIMR_EBERR field. */
00836 #define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
00837 
00838 /*! @brief Format value for bitfield ENET_EIMR_EBERR. */
00839 #define BF_ENET_EIMR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR)
00840 
00841 /*! @brief Set the EBERR field to a new value. */
00842 #define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
00843 /*@}*/
00844 
00845 /*!
00846  * @name Register ENET_EIMR, field MII[23] (RW)
00847  *
00848  * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
00849  * condition can generate an interrupt. At every module clock, the EIR samples
00850  * the signal generated by the interrupting source. The corresponding EIR MII field
00851  * reflects the state of the interrupt signal even if the corresponding EIMR
00852  * field is cleared.
00853  */
00854 /*@{*/
00855 #define BP_ENET_EIMR_MII     (23U)         /*!< Bit position for ENET_EIMR_MII. */
00856 #define BM_ENET_EIMR_MII     (0x00800000U) /*!< Bit mask for ENET_EIMR_MII. */
00857 #define BS_ENET_EIMR_MII     (1U)          /*!< Bit field size in bits for ENET_EIMR_MII. */
00858 
00859 /*! @brief Read current value of the ENET_EIMR_MII field. */
00860 #define BR_ENET_EIMR_MII(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
00861 
00862 /*! @brief Format value for bitfield ENET_EIMR_MII. */
00863 #define BF_ENET_EIMR_MII(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII)
00864 
00865 /*! @brief Set the MII field to a new value. */
00866 #define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
00867 /*@}*/
00868 
00869 /*!
00870  * @name Register ENET_EIMR, field RXB[24] (RW)
00871  *
00872  * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
00873  * condition can generate an interrupt. At every module clock, the EIR samples
00874  * the signal generated by the interrupting source. The corresponding EIR RXB field
00875  * reflects the state of the interrupt signal even if the corresponding EIMR
00876  * field is cleared.
00877  */
00878 /*@{*/
00879 #define BP_ENET_EIMR_RXB     (24U)         /*!< Bit position for ENET_EIMR_RXB. */
00880 #define BM_ENET_EIMR_RXB     (0x01000000U) /*!< Bit mask for ENET_EIMR_RXB. */
00881 #define BS_ENET_EIMR_RXB     (1U)          /*!< Bit field size in bits for ENET_EIMR_RXB. */
00882 
00883 /*! @brief Read current value of the ENET_EIMR_RXB field. */
00884 #define BR_ENET_EIMR_RXB(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
00885 
00886 /*! @brief Format value for bitfield ENET_EIMR_RXB. */
00887 #define BF_ENET_EIMR_RXB(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB)
00888 
00889 /*! @brief Set the RXB field to a new value. */
00890 #define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
00891 /*@}*/
00892 
00893 /*!
00894  * @name Register ENET_EIMR, field RXF[25] (RW)
00895  *
00896  * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
00897  * condition can generate an interrupt. At every module clock, the EIR samples
00898  * the signal generated by the interrupting source. The corresponding EIR RXF field
00899  * reflects the state of the interrupt signal even if the corresponding EIMR
00900  * field is cleared.
00901  */
00902 /*@{*/
00903 #define BP_ENET_EIMR_RXF     (25U)         /*!< Bit position for ENET_EIMR_RXF. */
00904 #define BM_ENET_EIMR_RXF     (0x02000000U) /*!< Bit mask for ENET_EIMR_RXF. */
00905 #define BS_ENET_EIMR_RXF     (1U)          /*!< Bit field size in bits for ENET_EIMR_RXF. */
00906 
00907 /*! @brief Read current value of the ENET_EIMR_RXF field. */
00908 #define BR_ENET_EIMR_RXF(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
00909 
00910 /*! @brief Format value for bitfield ENET_EIMR_RXF. */
00911 #define BF_ENET_EIMR_RXF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF)
00912 
00913 /*! @brief Set the RXF field to a new value. */
00914 #define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
00915 /*@}*/
00916 
00917 /*!
00918  * @name Register ENET_EIMR, field TXB[26] (RW)
00919  *
00920  * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
00921  * condition can generate an interrupt. At every module clock, the EIR samples
00922  * the signal generated by the interrupting source. The corresponding EIR TXF field
00923  * reflects the state of the interrupt signal even if the corresponding EIMR
00924  * field is cleared.
00925  *
00926  * Values:
00927  * - 0 - The corresponding interrupt source is masked.
00928  * - 1 - The corresponding interrupt source is not masked.
00929  */
00930 /*@{*/
00931 #define BP_ENET_EIMR_TXB     (26U)         /*!< Bit position for ENET_EIMR_TXB. */
00932 #define BM_ENET_EIMR_TXB     (0x04000000U) /*!< Bit mask for ENET_EIMR_TXB. */
00933 #define BS_ENET_EIMR_TXB     (1U)          /*!< Bit field size in bits for ENET_EIMR_TXB. */
00934 
00935 /*! @brief Read current value of the ENET_EIMR_TXB field. */
00936 #define BR_ENET_EIMR_TXB(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
00937 
00938 /*! @brief Format value for bitfield ENET_EIMR_TXB. */
00939 #define BF_ENET_EIMR_TXB(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB)
00940 
00941 /*! @brief Set the TXB field to a new value. */
00942 #define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
00943 /*@}*/
00944 
00945 /*!
00946  * @name Register ENET_EIMR, field TXF[27] (RW)
00947  *
00948  * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
00949  * condition can generate an interrupt. At every module clock, the EIR samples
00950  * the signal generated by the interrupting source. The corresponding EIR TXF field
00951  * reflects the state of the interrupt signal even if the corresponding EIMR
00952  * field is cleared.
00953  *
00954  * Values:
00955  * - 0 - The corresponding interrupt source is masked.
00956  * - 1 - The corresponding interrupt source is not masked.
00957  */
00958 /*@{*/
00959 #define BP_ENET_EIMR_TXF     (27U)         /*!< Bit position for ENET_EIMR_TXF. */
00960 #define BM_ENET_EIMR_TXF     (0x08000000U) /*!< Bit mask for ENET_EIMR_TXF. */
00961 #define BS_ENET_EIMR_TXF     (1U)          /*!< Bit field size in bits for ENET_EIMR_TXF. */
00962 
00963 /*! @brief Read current value of the ENET_EIMR_TXF field. */
00964 #define BR_ENET_EIMR_TXF(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
00965 
00966 /*! @brief Format value for bitfield ENET_EIMR_TXF. */
00967 #define BF_ENET_EIMR_TXF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF)
00968 
00969 /*! @brief Set the TXF field to a new value. */
00970 #define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
00971 /*@}*/
00972 
00973 /*!
00974  * @name Register ENET_EIMR, field GRA[28] (RW)
00975  *
00976  * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
00977  * condition can generate an interrupt. At every module clock, the EIR samples
00978  * the signal generated by the interrupting source. The corresponding EIR GRA field
00979  * reflects the state of the interrupt signal even if the corresponding EIMR
00980  * field is cleared.
00981  *
00982  * Values:
00983  * - 0 - The corresponding interrupt source is masked.
00984  * - 1 - The corresponding interrupt source is not masked.
00985  */
00986 /*@{*/
00987 #define BP_ENET_EIMR_GRA     (28U)         /*!< Bit position for ENET_EIMR_GRA. */
00988 #define BM_ENET_EIMR_GRA     (0x10000000U) /*!< Bit mask for ENET_EIMR_GRA. */
00989 #define BS_ENET_EIMR_GRA     (1U)          /*!< Bit field size in bits for ENET_EIMR_GRA. */
00990 
00991 /*! @brief Read current value of the ENET_EIMR_GRA field. */
00992 #define BR_ENET_EIMR_GRA(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
00993 
00994 /*! @brief Format value for bitfield ENET_EIMR_GRA. */
00995 #define BF_ENET_EIMR_GRA(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA)
00996 
00997 /*! @brief Set the GRA field to a new value. */
00998 #define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
00999 /*@}*/
01000 
01001 /*!
01002  * @name Register ENET_EIMR, field BABT[29] (RW)
01003  *
01004  * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
01005  * condition can generate an interrupt. At every module clock, the EIR samples
01006  * the signal generated by the interrupting source. The corresponding EIR BABT
01007  * field reflects the state of the interrupt signal even if the corresponding EIMR
01008  * field is cleared.
01009  *
01010  * Values:
01011  * - 0 - The corresponding interrupt source is masked.
01012  * - 1 - The corresponding interrupt source is not masked.
01013  */
01014 /*@{*/
01015 #define BP_ENET_EIMR_BABT    (29U)         /*!< Bit position for ENET_EIMR_BABT. */
01016 #define BM_ENET_EIMR_BABT    (0x20000000U) /*!< Bit mask for ENET_EIMR_BABT. */
01017 #define BS_ENET_EIMR_BABT    (1U)          /*!< Bit field size in bits for ENET_EIMR_BABT. */
01018 
01019 /*! @brief Read current value of the ENET_EIMR_BABT field. */
01020 #define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
01021 
01022 /*! @brief Format value for bitfield ENET_EIMR_BABT. */
01023 #define BF_ENET_EIMR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT)
01024 
01025 /*! @brief Set the BABT field to a new value. */
01026 #define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
01027 /*@}*/
01028 
01029 /*!
01030  * @name Register ENET_EIMR, field BABR[30] (RW)
01031  *
01032  * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
01033  * condition can generate an interrupt. At every module clock, the EIR samples
01034  * the signal generated by the interrupting source. The corresponding EIR BABR
01035  * field reflects the state of the interrupt signal even if the corresponding EIMR
01036  * field is cleared.
01037  *
01038  * Values:
01039  * - 0 - The corresponding interrupt source is masked.
01040  * - 1 - The corresponding interrupt source is not masked.
01041  */
01042 /*@{*/
01043 #define BP_ENET_EIMR_BABR    (30U)         /*!< Bit position for ENET_EIMR_BABR. */
01044 #define BM_ENET_EIMR_BABR    (0x40000000U) /*!< Bit mask for ENET_EIMR_BABR. */
01045 #define BS_ENET_EIMR_BABR    (1U)          /*!< Bit field size in bits for ENET_EIMR_BABR. */
01046 
01047 /*! @brief Read current value of the ENET_EIMR_BABR field. */
01048 #define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
01049 
01050 /*! @brief Format value for bitfield ENET_EIMR_BABR. */
01051 #define BF_ENET_EIMR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR)
01052 
01053 /*! @brief Set the BABR field to a new value. */
01054 #define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
01055 /*@}*/
01056 
01057 /*******************************************************************************
01058  * HW_ENET_RDAR - Receive Descriptor Active Register
01059  ******************************************************************************/
01060 
01061 /*!
01062  * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
01063  *
01064  * Reset value: 0x00000000U
01065  *
01066  * RDAR is a command register, written by the user, to indicate that the receive
01067  * descriptor ring has been updated, that is, that the driver produced empty
01068  * receive buffers with the empty bit set.
01069  */
01070 typedef union _hw_enet_rdar
01071 {
01072     uint32_t U;
01073     struct _hw_enet_rdar_bitfields
01074     {
01075         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
01076         uint32_t RDAR : 1;             /*!< [24] Receive Descriptor Active */
01077         uint32_t RESERVED1 : 7;        /*!< [31:25]  */
01078     } B;
01079 } hw_enet_rdar_t;
01080 
01081 /*!
01082  * @name Constants and macros for entire ENET_RDAR register
01083  */
01084 /*@{*/
01085 #define HW_ENET_RDAR_ADDR(x)     ((x) + 0x10U)
01086 
01087 #define HW_ENET_RDAR(x)          (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
01088 #define HW_ENET_RDAR_RD(x)       (HW_ENET_RDAR(x).U)
01089 #define HW_ENET_RDAR_WR(x, v)    (HW_ENET_RDAR(x).U = (v))
01090 #define HW_ENET_RDAR_SET(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) |  (v)))
01091 #define HW_ENET_RDAR_CLR(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
01092 #define HW_ENET_RDAR_TOG(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^  (v)))
01093 /*@}*/
01094 
01095 /*
01096  * Constants & macros for individual ENET_RDAR bitfields
01097  */
01098 
01099 /*!
01100  * @name Register ENET_RDAR, field RDAR[24] (RW)
01101  *
01102  * Always set to 1 when this register is written, regardless of the value
01103  * written. This field is cleared by the MAC device when no additional empty
01104  * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
01105  * from set to cleared or when ECR[RESET] is set.
01106  */
01107 /*@{*/
01108 #define BP_ENET_RDAR_RDAR    (24U)         /*!< Bit position for ENET_RDAR_RDAR. */
01109 #define BM_ENET_RDAR_RDAR    (0x01000000U) /*!< Bit mask for ENET_RDAR_RDAR. */
01110 #define BS_ENET_RDAR_RDAR    (1U)          /*!< Bit field size in bits for ENET_RDAR_RDAR. */
01111 
01112 /*! @brief Read current value of the ENET_RDAR_RDAR field. */
01113 #define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
01114 
01115 /*! @brief Format value for bitfield ENET_RDAR_RDAR. */
01116 #define BF_ENET_RDAR_RDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR)
01117 
01118 /*! @brief Set the RDAR field to a new value. */
01119 #define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
01120 /*@}*/
01121 
01122 /*******************************************************************************
01123  * HW_ENET_TDAR - Transmit Descriptor Active Register
01124  ******************************************************************************/
01125 
01126 /*!
01127  * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
01128  *
01129  * Reset value: 0x00000000U
01130  *
01131  * The TDAR is a command register that the user writes to indicate that the
01132  * transmit descriptor ring has been updated, that is, that transmit buffers have
01133  * been produced by the driver with the ready bit set in the buffer descriptor. The
01134  * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
01135  * cleared, or when ECR[RESET] is set.
01136  */
01137 typedef union _hw_enet_tdar
01138 {
01139     uint32_t U;
01140     struct _hw_enet_tdar_bitfields
01141     {
01142         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
01143         uint32_t TDAR : 1;             /*!< [24] Transmit Descriptor Active */
01144         uint32_t RESERVED1 : 7;        /*!< [31:25]  */
01145     } B;
01146 } hw_enet_tdar_t;
01147 
01148 /*!
01149  * @name Constants and macros for entire ENET_TDAR register
01150  */
01151 /*@{*/
01152 #define HW_ENET_TDAR_ADDR(x)     ((x) + 0x14U)
01153 
01154 #define HW_ENET_TDAR(x)          (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
01155 #define HW_ENET_TDAR_RD(x)       (HW_ENET_TDAR(x).U)
01156 #define HW_ENET_TDAR_WR(x, v)    (HW_ENET_TDAR(x).U = (v))
01157 #define HW_ENET_TDAR_SET(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) |  (v)))
01158 #define HW_ENET_TDAR_CLR(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
01159 #define HW_ENET_TDAR_TOG(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^  (v)))
01160 /*@}*/
01161 
01162 /*
01163  * Constants & macros for individual ENET_TDAR bitfields
01164  */
01165 
01166 /*!
01167  * @name Register ENET_TDAR, field TDAR[24] (RW)
01168  *
01169  * Always set to 1 when this register is written, regardless of the value
01170  * written. This bit is cleared by the MAC device when no additional ready descriptors
01171  * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
01172  * set to cleared or when ECR[RESET] is set.
01173  */
01174 /*@{*/
01175 #define BP_ENET_TDAR_TDAR    (24U)         /*!< Bit position for ENET_TDAR_TDAR. */
01176 #define BM_ENET_TDAR_TDAR    (0x01000000U) /*!< Bit mask for ENET_TDAR_TDAR. */
01177 #define BS_ENET_TDAR_TDAR    (1U)          /*!< Bit field size in bits for ENET_TDAR_TDAR. */
01178 
01179 /*! @brief Read current value of the ENET_TDAR_TDAR field. */
01180 #define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
01181 
01182 /*! @brief Format value for bitfield ENET_TDAR_TDAR. */
01183 #define BF_ENET_TDAR_TDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR)
01184 
01185 /*! @brief Set the TDAR field to a new value. */
01186 #define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
01187 /*@}*/
01188 
01189 /*******************************************************************************
01190  * HW_ENET_ECR - Ethernet Control Register
01191  ******************************************************************************/
01192 
01193 /*!
01194  * @brief HW_ENET_ECR - Ethernet Control Register (RW)
01195  *
01196  * Reset value: 0xF0000000U
01197  *
01198  * ECR is a read/write user register, though hardware may also alter fields in
01199  * this register. It controls many of the high level features of the Ethernet MAC,
01200  * including legacy FEC support through the EN1588 field.
01201  */
01202 typedef union _hw_enet_ecr
01203 {
01204     uint32_t U;
01205     struct _hw_enet_ecr_bitfields
01206     {
01207         uint32_t RESET : 1;            /*!< [0] Ethernet MAC Reset */
01208         uint32_t ETHEREN : 1;          /*!< [1] Ethernet Enable */
01209         uint32_t MAGICEN : 1;          /*!< [2] Magic Packet Detection Enable */
01210         uint32_t SLEEP : 1;            /*!< [3] Sleep Mode Enable */
01211         uint32_t EN1588 : 1;           /*!< [4] EN1588 Enable */
01212         uint32_t RESERVED0 : 1;        /*!< [5]  */
01213         uint32_t DBGEN : 1;            /*!< [6] Debug Enable */
01214         uint32_t STOPEN : 1;           /*!< [7] STOPEN Signal Control */
01215         uint32_t DBSWP : 1;            /*!< [8] Descriptor Byte Swapping Enable */
01216         uint32_t RESERVED1 : 23;       /*!< [31:9]  */
01217     } B;
01218 } hw_enet_ecr_t;
01219 
01220 /*!
01221  * @name Constants and macros for entire ENET_ECR register
01222  */
01223 /*@{*/
01224 #define HW_ENET_ECR_ADDR(x)      ((x) + 0x24U)
01225 
01226 #define HW_ENET_ECR(x)           (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
01227 #define HW_ENET_ECR_RD(x)        (HW_ENET_ECR(x).U)
01228 #define HW_ENET_ECR_WR(x, v)     (HW_ENET_ECR(x).U = (v))
01229 #define HW_ENET_ECR_SET(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) |  (v)))
01230 #define HW_ENET_ECR_CLR(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
01231 #define HW_ENET_ECR_TOG(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^  (v)))
01232 /*@}*/
01233 
01234 /*
01235  * Constants & macros for individual ENET_ECR bitfields
01236  */
01237 
01238 /*!
01239  * @name Register ENET_ECR, field RESET[0] (RW)
01240  *
01241  * When this field is set, it clears the ETHEREN field.
01242  */
01243 /*@{*/
01244 #define BP_ENET_ECR_RESET    (0U)          /*!< Bit position for ENET_ECR_RESET. */
01245 #define BM_ENET_ECR_RESET    (0x00000001U) /*!< Bit mask for ENET_ECR_RESET. */
01246 #define BS_ENET_ECR_RESET    (1U)          /*!< Bit field size in bits for ENET_ECR_RESET. */
01247 
01248 /*! @brief Read current value of the ENET_ECR_RESET field. */
01249 #define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
01250 
01251 /*! @brief Format value for bitfield ENET_ECR_RESET. */
01252 #define BF_ENET_ECR_RESET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET)
01253 
01254 /*! @brief Set the RESET field to a new value. */
01255 #define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
01256 /*@}*/
01257 
01258 /*!
01259  * @name Register ENET_ECR, field ETHEREN[1] (RW)
01260  *
01261  * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
01262  * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
01263  * descriptor, and FIFO control logic are reset, including the buffer descriptor and
01264  * FIFO pointers. Hardware clears this field under the following conditions: RESET
01265  * is set by software An error condition causes the EBERR field to set. ETHEREN
01266  * must be set at the very last step during ENET
01267  * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
01268  * is cleared to 0 by software then then next time ETHEREN is set, the EIR
01269  * interrupts must cleared to 0 due to previous pending interrupts.
01270  *
01271  * Values:
01272  * - 0 - Reception immediately stops and transmission stops after a bad CRC is
01273  *     appended to any currently transmitted frame.
01274  * - 1 - MAC is enabled, and reception and transmission are possible.
01275  */
01276 /*@{*/
01277 #define BP_ENET_ECR_ETHEREN  (1U)          /*!< Bit position for ENET_ECR_ETHEREN. */
01278 #define BM_ENET_ECR_ETHEREN  (0x00000002U) /*!< Bit mask for ENET_ECR_ETHEREN. */
01279 #define BS_ENET_ECR_ETHEREN  (1U)          /*!< Bit field size in bits for ENET_ECR_ETHEREN. */
01280 
01281 /*! @brief Read current value of the ENET_ECR_ETHEREN field. */
01282 #define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
01283 
01284 /*! @brief Format value for bitfield ENET_ECR_ETHEREN. */
01285 #define BF_ENET_ECR_ETHEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN)
01286 
01287 /*! @brief Set the ETHEREN field to a new value. */
01288 #define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
01289 /*@}*/
01290 
01291 /*!
01292  * @name Register ENET_ECR, field MAGICEN[2] (RW)
01293  *
01294  * Enables/disables magic packet detection. MAGICEN is relevant only if the
01295  * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
01296  * sleep mode and magic packet detection.
01297  *
01298  * Values:
01299  * - 0 - Magic detection logic disabled.
01300  * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
01301  *     is detected.
01302  */
01303 /*@{*/
01304 #define BP_ENET_ECR_MAGICEN  (2U)          /*!< Bit position for ENET_ECR_MAGICEN. */
01305 #define BM_ENET_ECR_MAGICEN  (0x00000004U) /*!< Bit mask for ENET_ECR_MAGICEN. */
01306 #define BS_ENET_ECR_MAGICEN  (1U)          /*!< Bit field size in bits for ENET_ECR_MAGICEN. */
01307 
01308 /*! @brief Read current value of the ENET_ECR_MAGICEN field. */
01309 #define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
01310 
01311 /*! @brief Format value for bitfield ENET_ECR_MAGICEN. */
01312 #define BF_ENET_ECR_MAGICEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN)
01313 
01314 /*! @brief Set the MAGICEN field to a new value. */
01315 #define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
01316 /*@}*/
01317 
01318 /*!
01319  * @name Register ENET_ECR, field SLEEP[3] (RW)
01320  *
01321  * Values:
01322  * - 0 - Normal operating mode.
01323  * - 1 - Sleep mode.
01324  */
01325 /*@{*/
01326 #define BP_ENET_ECR_SLEEP    (3U)          /*!< Bit position for ENET_ECR_SLEEP. */
01327 #define BM_ENET_ECR_SLEEP    (0x00000008U) /*!< Bit mask for ENET_ECR_SLEEP. */
01328 #define BS_ENET_ECR_SLEEP    (1U)          /*!< Bit field size in bits for ENET_ECR_SLEEP. */
01329 
01330 /*! @brief Read current value of the ENET_ECR_SLEEP field. */
01331 #define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
01332 
01333 /*! @brief Format value for bitfield ENET_ECR_SLEEP. */
01334 #define BF_ENET_ECR_SLEEP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP)
01335 
01336 /*! @brief Set the SLEEP field to a new value. */
01337 #define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
01338 /*@}*/
01339 
01340 /*!
01341  * @name Register ENET_ECR, field EN1588[4] (RW)
01342  *
01343  * Enables enhanced functionality of the MAC.
01344  *
01345  * Values:
01346  * - 0 - Legacy FEC buffer descriptors and functions enabled.
01347  * - 1 - Enhanced frame time-stamping functions enabled.
01348  */
01349 /*@{*/
01350 #define BP_ENET_ECR_EN1588   (4U)          /*!< Bit position for ENET_ECR_EN1588. */
01351 #define BM_ENET_ECR_EN1588   (0x00000010U) /*!< Bit mask for ENET_ECR_EN1588. */
01352 #define BS_ENET_ECR_EN1588   (1U)          /*!< Bit field size in bits for ENET_ECR_EN1588. */
01353 
01354 /*! @brief Read current value of the ENET_ECR_EN1588 field. */
01355 #define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
01356 
01357 /*! @brief Format value for bitfield ENET_ECR_EN1588. */
01358 #define BF_ENET_ECR_EN1588(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588)
01359 
01360 /*! @brief Set the EN1588 field to a new value. */
01361 #define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
01362 /*@}*/
01363 
01364 /*!
01365  * @name Register ENET_ECR, field DBGEN[6] (RW)
01366  *
01367  * Enables the MAC to enter hardware freeze mode when the device enters debug
01368  * mode.
01369  *
01370  * Values:
01371  * - 0 - MAC continues operation in debug mode.
01372  * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
01373  */
01374 /*@{*/
01375 #define BP_ENET_ECR_DBGEN    (6U)          /*!< Bit position for ENET_ECR_DBGEN. */
01376 #define BM_ENET_ECR_DBGEN    (0x00000040U) /*!< Bit mask for ENET_ECR_DBGEN. */
01377 #define BS_ENET_ECR_DBGEN    (1U)          /*!< Bit field size in bits for ENET_ECR_DBGEN. */
01378 
01379 /*! @brief Read current value of the ENET_ECR_DBGEN field. */
01380 #define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
01381 
01382 /*! @brief Format value for bitfield ENET_ECR_DBGEN. */
01383 #define BF_ENET_ECR_DBGEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN)
01384 
01385 /*! @brief Set the DBGEN field to a new value. */
01386 #define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
01387 /*@}*/
01388 
01389 /*!
01390  * @name Register ENET_ECR, field STOPEN[7] (RW)
01391  *
01392  * Controls device behavior in doze mode. In doze mode, if this field is set
01393  * then all the clocks of the ENET assembly are disabled, except the RMII /MII
01394  * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
01395  * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
01396  * can still wake the system after receiving a magic packet in stop mode. MAGICEN
01397  * must be set prior to entering sleep/stop mode.
01398  */
01399 /*@{*/
01400 #define BP_ENET_ECR_STOPEN   (7U)          /*!< Bit position for ENET_ECR_STOPEN. */
01401 #define BM_ENET_ECR_STOPEN   (0x00000080U) /*!< Bit mask for ENET_ECR_STOPEN. */
01402 #define BS_ENET_ECR_STOPEN   (1U)          /*!< Bit field size in bits for ENET_ECR_STOPEN. */
01403 
01404 /*! @brief Read current value of the ENET_ECR_STOPEN field. */
01405 #define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
01406 
01407 /*! @brief Format value for bitfield ENET_ECR_STOPEN. */
01408 #define BF_ENET_ECR_STOPEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN)
01409 
01410 /*! @brief Set the STOPEN field to a new value. */
01411 #define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
01412 /*@}*/
01413 
01414 /*!
01415  * @name Register ENET_ECR, field DBSWP[8] (RW)
01416  *
01417  * Swaps the byte locations of the buffer descriptors. This field must be
01418  * written to 1 after reset.
01419  *
01420  * Values:
01421  * - 0 - The buffer descriptor bytes are not swapped to support big-endian
01422  *     devices.
01423  * - 1 - The buffer descriptor bytes are swapped to support little-endian
01424  *     devices.
01425  */
01426 /*@{*/
01427 #define BP_ENET_ECR_DBSWP    (8U)          /*!< Bit position for ENET_ECR_DBSWP. */
01428 #define BM_ENET_ECR_DBSWP    (0x00000100U) /*!< Bit mask for ENET_ECR_DBSWP. */
01429 #define BS_ENET_ECR_DBSWP    (1U)          /*!< Bit field size in bits for ENET_ECR_DBSWP. */
01430 
01431 /*! @brief Read current value of the ENET_ECR_DBSWP field. */
01432 #define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
01433 
01434 /*! @brief Format value for bitfield ENET_ECR_DBSWP. */
01435 #define BF_ENET_ECR_DBSWP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBSWP) & BM_ENET_ECR_DBSWP)
01436 
01437 /*! @brief Set the DBSWP field to a new value. */
01438 #define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
01439 /*@}*/
01440 
01441 /*******************************************************************************
01442  * HW_ENET_MMFR - MII Management Frame Register
01443  ******************************************************************************/
01444 
01445 /*!
01446  * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
01447  *
01448  * Reset value: 0x00000000U
01449  *
01450  * Writing to MMFR triggers a management frame transaction to the PHY device
01451  * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
01452  * during a write to MMFR, an MII frame is generated with the data previously written
01453  * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
01454  * MSCR is currently zero. If the MMFR register is written while frame generation is
01455  * in progress, the frame contents are altered. Software must use the EIR[MII]
01456  * interrupt indication to avoid writing to the MMFR register while frame
01457  * generation is in progress.
01458  */
01459 typedef union _hw_enet_mmfr
01460 {
01461     uint32_t U;
01462     struct _hw_enet_mmfr_bitfields
01463     {
01464         uint32_t DATA : 16;            /*!< [15:0] Management Frame Data */
01465         uint32_t TA : 2;               /*!< [17:16] Turn Around */
01466         uint32_t RA : 5;               /*!< [22:18] Register Address */
01467         uint32_t PA : 5;               /*!< [27:23] PHY Address */
01468         uint32_t OP : 2;               /*!< [29:28] Operation Code */
01469         uint32_t ST : 2;               /*!< [31:30] Start Of Frame Delimiter */
01470     } B;
01471 } hw_enet_mmfr_t;
01472 
01473 /*!
01474  * @name Constants and macros for entire ENET_MMFR register
01475  */
01476 /*@{*/
01477 #define HW_ENET_MMFR_ADDR(x)     ((x) + 0x40U)
01478 
01479 #define HW_ENET_MMFR(x)          (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
01480 #define HW_ENET_MMFR_RD(x)       (HW_ENET_MMFR(x).U)
01481 #define HW_ENET_MMFR_WR(x, v)    (HW_ENET_MMFR(x).U = (v))
01482 #define HW_ENET_MMFR_SET(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) |  (v)))
01483 #define HW_ENET_MMFR_CLR(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
01484 #define HW_ENET_MMFR_TOG(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^  (v)))
01485 /*@}*/
01486 
01487 /*
01488  * Constants & macros for individual ENET_MMFR bitfields
01489  */
01490 
01491 /*!
01492  * @name Register ENET_MMFR, field DATA[15:0] (RW)
01493  *
01494  * This is the field for data to be written to or read from the PHY register.
01495  */
01496 /*@{*/
01497 #define BP_ENET_MMFR_DATA    (0U)          /*!< Bit position for ENET_MMFR_DATA. */
01498 #define BM_ENET_MMFR_DATA    (0x0000FFFFU) /*!< Bit mask for ENET_MMFR_DATA. */
01499 #define BS_ENET_MMFR_DATA    (16U)         /*!< Bit field size in bits for ENET_MMFR_DATA. */
01500 
01501 /*! @brief Read current value of the ENET_MMFR_DATA field. */
01502 #define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
01503 
01504 /*! @brief Format value for bitfield ENET_MMFR_DATA. */
01505 #define BF_ENET_MMFR_DATA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA)
01506 
01507 /*! @brief Set the DATA field to a new value. */
01508 #define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
01509 /*@}*/
01510 
01511 /*!
01512  * @name Register ENET_MMFR, field TA[17:16] (RW)
01513  *
01514  * This field must be programmed to 10 to generate a valid MII management frame.
01515  */
01516 /*@{*/
01517 #define BP_ENET_MMFR_TA      (16U)         /*!< Bit position for ENET_MMFR_TA. */
01518 #define BM_ENET_MMFR_TA      (0x00030000U) /*!< Bit mask for ENET_MMFR_TA. */
01519 #define BS_ENET_MMFR_TA      (2U)          /*!< Bit field size in bits for ENET_MMFR_TA. */
01520 
01521 /*! @brief Read current value of the ENET_MMFR_TA field. */
01522 #define BR_ENET_MMFR_TA(x)   (HW_ENET_MMFR(x).B.TA)
01523 
01524 /*! @brief Format value for bitfield ENET_MMFR_TA. */
01525 #define BF_ENET_MMFR_TA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA)
01526 
01527 /*! @brief Set the TA field to a new value. */
01528 #define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
01529 /*@}*/
01530 
01531 /*!
01532  * @name Register ENET_MMFR, field RA[22:18] (RW)
01533  *
01534  * Specifies one of up to 32 registers within the specified PHY device.
01535  */
01536 /*@{*/
01537 #define BP_ENET_MMFR_RA      (18U)         /*!< Bit position for ENET_MMFR_RA. */
01538 #define BM_ENET_MMFR_RA      (0x007C0000U) /*!< Bit mask for ENET_MMFR_RA. */
01539 #define BS_ENET_MMFR_RA      (5U)          /*!< Bit field size in bits for ENET_MMFR_RA. */
01540 
01541 /*! @brief Read current value of the ENET_MMFR_RA field. */
01542 #define BR_ENET_MMFR_RA(x)   (HW_ENET_MMFR(x).B.RA)
01543 
01544 /*! @brief Format value for bitfield ENET_MMFR_RA. */
01545 #define BF_ENET_MMFR_RA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA)
01546 
01547 /*! @brief Set the RA field to a new value. */
01548 #define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
01549 /*@}*/
01550 
01551 /*!
01552  * @name Register ENET_MMFR, field PA[27:23] (RW)
01553  *
01554  * Specifies one of up to 32 attached PHY devices.
01555  */
01556 /*@{*/
01557 #define BP_ENET_MMFR_PA      (23U)         /*!< Bit position for ENET_MMFR_PA. */
01558 #define BM_ENET_MMFR_PA      (0x0F800000U) /*!< Bit mask for ENET_MMFR_PA. */
01559 #define BS_ENET_MMFR_PA      (5U)          /*!< Bit field size in bits for ENET_MMFR_PA. */
01560 
01561 /*! @brief Read current value of the ENET_MMFR_PA field. */
01562 #define BR_ENET_MMFR_PA(x)   (HW_ENET_MMFR(x).B.PA)
01563 
01564 /*! @brief Format value for bitfield ENET_MMFR_PA. */
01565 #define BF_ENET_MMFR_PA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA)
01566 
01567 /*! @brief Set the PA field to a new value. */
01568 #define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
01569 /*@}*/
01570 
01571 /*!
01572  * @name Register ENET_MMFR, field OP[29:28] (RW)
01573  *
01574  * Determines the frame operation.
01575  *
01576  * Values:
01577  * - 00 - Write frame operation, but not MII compliant.
01578  * - 01 - Write frame operation for a valid MII management frame.
01579  * - 10 - Read frame operation for a valid MII management frame.
01580  * - 11 - Read frame operation, but not MII compliant.
01581  */
01582 /*@{*/
01583 #define BP_ENET_MMFR_OP      (28U)         /*!< Bit position for ENET_MMFR_OP. */
01584 #define BM_ENET_MMFR_OP      (0x30000000U) /*!< Bit mask for ENET_MMFR_OP. */
01585 #define BS_ENET_MMFR_OP      (2U)          /*!< Bit field size in bits for ENET_MMFR_OP. */
01586 
01587 /*! @brief Read current value of the ENET_MMFR_OP field. */
01588 #define BR_ENET_MMFR_OP(x)   (HW_ENET_MMFR(x).B.OP)
01589 
01590 /*! @brief Format value for bitfield ENET_MMFR_OP. */
01591 #define BF_ENET_MMFR_OP(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP)
01592 
01593 /*! @brief Set the OP field to a new value. */
01594 #define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
01595 /*@}*/
01596 
01597 /*!
01598  * @name Register ENET_MMFR, field ST[31:30] (RW)
01599  *
01600  * These fields must be programmed to 01 for a valid MII management frame.
01601  */
01602 /*@{*/
01603 #define BP_ENET_MMFR_ST      (30U)         /*!< Bit position for ENET_MMFR_ST. */
01604 #define BM_ENET_MMFR_ST      (0xC0000000U) /*!< Bit mask for ENET_MMFR_ST. */
01605 #define BS_ENET_MMFR_ST      (2U)          /*!< Bit field size in bits for ENET_MMFR_ST. */
01606 
01607 /*! @brief Read current value of the ENET_MMFR_ST field. */
01608 #define BR_ENET_MMFR_ST(x)   (HW_ENET_MMFR(x).B.ST)
01609 
01610 /*! @brief Format value for bitfield ENET_MMFR_ST. */
01611 #define BF_ENET_MMFR_ST(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST)
01612 
01613 /*! @brief Set the ST field to a new value. */
01614 #define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
01615 /*@}*/
01616 
01617 /*******************************************************************************
01618  * HW_ENET_MSCR - MII Speed Control Register
01619  ******************************************************************************/
01620 
01621 /*!
01622  * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
01623  *
01624  * Reset value: 0x00000000U
01625  *
01626  * MSCR provides control of the MII clock (MDC pin) frequency and allows a
01627  * preamble drop on the MII management frame. The MII_SPEED field must be programmed
01628  * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
01629  * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
01630  * a non-zero value to source a read or write management frame. After the
01631  * management frame is complete, the MSCR register may optionally be cleared to turn
01632  * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
01633  * changes during operation. This change takes effect following a rising or falling
01634  * edge of MDC. If the internal module clock is 25 MHz, programming this register
01635  * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
01636  * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
01637  * MII_SPEED as a function of internal module clock frequency. Programming Examples
01638  * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
01639  * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
01640  * 0xD 2.36 MHz
01641  */
01642 typedef union _hw_enet_mscr
01643 {
01644     uint32_t U;
01645     struct _hw_enet_mscr_bitfields
01646     {
01647         uint32_t RESERVED0 : 1;        /*!< [0]  */
01648         uint32_t MII_SPEED : 6;        /*!< [6:1] MII Speed */
01649         uint32_t DIS_PRE : 1;          /*!< [7] Disable Preamble */
01650         uint32_t HOLDTIME : 3;         /*!< [10:8] Hold time On MDIO Output */
01651         uint32_t RESERVED1 : 21;       /*!< [31:11]  */
01652     } B;
01653 } hw_enet_mscr_t;
01654 
01655 /*!
01656  * @name Constants and macros for entire ENET_MSCR register
01657  */
01658 /*@{*/
01659 #define HW_ENET_MSCR_ADDR(x)     ((x) + 0x44U)
01660 
01661 #define HW_ENET_MSCR(x)          (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
01662 #define HW_ENET_MSCR_RD(x)       (HW_ENET_MSCR(x).U)
01663 #define HW_ENET_MSCR_WR(x, v)    (HW_ENET_MSCR(x).U = (v))
01664 #define HW_ENET_MSCR_SET(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) |  (v)))
01665 #define HW_ENET_MSCR_CLR(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
01666 #define HW_ENET_MSCR_TOG(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^  (v)))
01667 /*@}*/
01668 
01669 /*
01670  * Constants & macros for individual ENET_MSCR bitfields
01671  */
01672 
01673 /*!
01674  * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
01675  *
01676  * Controls the frequency of the MII management interface clock (MDC) relative
01677  * to the internal module clock. A value of 0 in this field turns off MDC and
01678  * leaves it in low voltage state. Any non-zero value results in the MDC frequency
01679  * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
01680  */
01681 /*@{*/
01682 #define BP_ENET_MSCR_MII_SPEED (1U)        /*!< Bit position for ENET_MSCR_MII_SPEED. */
01683 #define BM_ENET_MSCR_MII_SPEED (0x0000007EU) /*!< Bit mask for ENET_MSCR_MII_SPEED. */
01684 #define BS_ENET_MSCR_MII_SPEED (6U)        /*!< Bit field size in bits for ENET_MSCR_MII_SPEED. */
01685 
01686 /*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
01687 #define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
01688 
01689 /*! @brief Format value for bitfield ENET_MSCR_MII_SPEED. */
01690 #define BF_ENET_MSCR_MII_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED)
01691 
01692 /*! @brief Set the MII_SPEED field to a new value. */
01693 #define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
01694 /*@}*/
01695 
01696 /*!
01697  * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
01698  *
01699  * Enables/disables prepending a preamble to the MII management frame. The MII
01700  * standard allows the preamble to be dropped if the attached PHY devices do not
01701  * require it.
01702  *
01703  * Values:
01704  * - 0 - Preamble enabled.
01705  * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
01706  */
01707 /*@{*/
01708 #define BP_ENET_MSCR_DIS_PRE (7U)          /*!< Bit position for ENET_MSCR_DIS_PRE. */
01709 #define BM_ENET_MSCR_DIS_PRE (0x00000080U) /*!< Bit mask for ENET_MSCR_DIS_PRE. */
01710 #define BS_ENET_MSCR_DIS_PRE (1U)          /*!< Bit field size in bits for ENET_MSCR_DIS_PRE. */
01711 
01712 /*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
01713 #define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
01714 
01715 /*! @brief Format value for bitfield ENET_MSCR_DIS_PRE. */
01716 #define BF_ENET_MSCR_DIS_PRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE)
01717 
01718 /*! @brief Set the DIS_PRE field to a new value. */
01719 #define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
01720 /*@}*/
01721 
01722 /*!
01723  * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
01724  *
01725  * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
01726  * output. Depending on the host bus frequency, the setting may need to be
01727  * increased.
01728  *
01729  * Values:
01730  * - 000 - 1 internal module clock cycle
01731  * - 001 - 2 internal module clock cycles
01732  * - 010 - 3 internal module clock cycles
01733  * - 111 - 8 internal module clock cycles
01734  */
01735 /*@{*/
01736 #define BP_ENET_MSCR_HOLDTIME (8U)         /*!< Bit position for ENET_MSCR_HOLDTIME. */
01737 #define BM_ENET_MSCR_HOLDTIME (0x00000700U) /*!< Bit mask for ENET_MSCR_HOLDTIME. */
01738 #define BS_ENET_MSCR_HOLDTIME (3U)         /*!< Bit field size in bits for ENET_MSCR_HOLDTIME. */
01739 
01740 /*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
01741 #define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
01742 
01743 /*! @brief Format value for bitfield ENET_MSCR_HOLDTIME. */
01744 #define BF_ENET_MSCR_HOLDTIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME)
01745 
01746 /*! @brief Set the HOLDTIME field to a new value. */
01747 #define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
01748 /*@}*/
01749 
01750 /*******************************************************************************
01751  * HW_ENET_MIBC - MIB Control Register
01752  ******************************************************************************/
01753 
01754 /*!
01755  * @brief HW_ENET_MIBC - MIB Control Register (RW)
01756  *
01757  * Reset value: 0xC0000000U
01758  *
01759  * MIBC is a read/write register controlling and observing the state of the MIB
01760  * block. Access this register to disable the MIB block operation or clear the
01761  * MIB counters. The MIB_DIS field resets to 1.
01762  */
01763 typedef union _hw_enet_mibc
01764 {
01765     uint32_t U;
01766     struct _hw_enet_mibc_bitfields
01767     {
01768         uint32_t RESERVED0 : 29;       /*!< [28:0]  */
01769         uint32_t MIB_CLEAR : 1;        /*!< [29] MIB Clear */
01770         uint32_t MIB_IDLE : 1;         /*!< [30] MIB Idle */
01771         uint32_t MIB_DIS : 1;          /*!< [31] Disable MIB Logic */
01772     } B;
01773 } hw_enet_mibc_t;
01774 
01775 /*!
01776  * @name Constants and macros for entire ENET_MIBC register
01777  */
01778 /*@{*/
01779 #define HW_ENET_MIBC_ADDR(x)     ((x) + 0x64U)
01780 
01781 #define HW_ENET_MIBC(x)          (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
01782 #define HW_ENET_MIBC_RD(x)       (HW_ENET_MIBC(x).U)
01783 #define HW_ENET_MIBC_WR(x, v)    (HW_ENET_MIBC(x).U = (v))
01784 #define HW_ENET_MIBC_SET(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) |  (v)))
01785 #define HW_ENET_MIBC_CLR(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
01786 #define HW_ENET_MIBC_TOG(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^  (v)))
01787 /*@}*/
01788 
01789 /*
01790  * Constants & macros for individual ENET_MIBC bitfields
01791  */
01792 
01793 /*!
01794  * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
01795  *
01796  * If set, all statistics counters are reset to 0. This field is not
01797  * self-clearing. To clear the MIB counters set and then clear the field.
01798  */
01799 /*@{*/
01800 #define BP_ENET_MIBC_MIB_CLEAR (29U)       /*!< Bit position for ENET_MIBC_MIB_CLEAR. */
01801 #define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) /*!< Bit mask for ENET_MIBC_MIB_CLEAR. */
01802 #define BS_ENET_MIBC_MIB_CLEAR (1U)        /*!< Bit field size in bits for ENET_MIBC_MIB_CLEAR. */
01803 
01804 /*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
01805 #define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
01806 
01807 /*! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. */
01808 #define BF_ENET_MIBC_MIB_CLEAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR)
01809 
01810 /*! @brief Set the MIB_CLEAR field to a new value. */
01811 #define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
01812 /*@}*/
01813 
01814 /*!
01815  * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
01816  *
01817  * If this status field is set, the MIB block is not currently updating any MIB
01818  * counters.
01819  */
01820 /*@{*/
01821 #define BP_ENET_MIBC_MIB_IDLE (30U)        /*!< Bit position for ENET_MIBC_MIB_IDLE. */
01822 #define BM_ENET_MIBC_MIB_IDLE (0x40000000U) /*!< Bit mask for ENET_MIBC_MIB_IDLE. */
01823 #define BS_ENET_MIBC_MIB_IDLE (1U)         /*!< Bit field size in bits for ENET_MIBC_MIB_IDLE. */
01824 
01825 /*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
01826 #define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
01827 /*@}*/
01828 
01829 /*!
01830  * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
01831  *
01832  * If this control field is set, the MIB logic halts and does not update any MIB
01833  * counters.
01834  */
01835 /*@{*/
01836 #define BP_ENET_MIBC_MIB_DIS (31U)         /*!< Bit position for ENET_MIBC_MIB_DIS. */
01837 #define BM_ENET_MIBC_MIB_DIS (0x80000000U) /*!< Bit mask for ENET_MIBC_MIB_DIS. */
01838 #define BS_ENET_MIBC_MIB_DIS (1U)          /*!< Bit field size in bits for ENET_MIBC_MIB_DIS. */
01839 
01840 /*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
01841 #define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
01842 
01843 /*! @brief Format value for bitfield ENET_MIBC_MIB_DIS. */
01844 #define BF_ENET_MIBC_MIB_DIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS)
01845 
01846 /*! @brief Set the MIB_DIS field to a new value. */
01847 #define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
01848 /*@}*/
01849 
01850 /*******************************************************************************
01851  * HW_ENET_RCR - Receive Control Register
01852  ******************************************************************************/
01853 
01854 /*!
01855  * @brief HW_ENET_RCR - Receive Control Register (RW)
01856  *
01857  * Reset value: 0x05EE0001U
01858  */
01859 typedef union _hw_enet_rcr
01860 {
01861     uint32_t U;
01862     struct _hw_enet_rcr_bitfields
01863     {
01864         uint32_t LOOP : 1;             /*!< [0] Internal Loopback */
01865         uint32_t DRT : 1;              /*!< [1] Disable Receive On Transmit */
01866         uint32_t MII_MODE : 1;         /*!< [2] Media Independent Interface Mode */
01867         uint32_t PROM : 1;             /*!< [3] Promiscuous Mode */
01868         uint32_t BC_REJ : 1;           /*!< [4] Broadcast Frame Reject */
01869         uint32_t FCE : 1;              /*!< [5] Flow Control Enable */
01870         uint32_t RESERVED0 : 2;        /*!< [7:6]  */
01871         uint32_t RMII_MODE : 1;        /*!< [8] RMII Mode Enable */
01872         uint32_t RMII_10T : 1;         /*!< [9]  */
01873         uint32_t RESERVED1 : 2;        /*!< [11:10]  */
01874         uint32_t PADEN : 1;            /*!< [12] Enable Frame Padding Remove On Receive
01875                                         * */
01876         uint32_t PAUFWD : 1;           /*!< [13] Terminate/Forward Pause Frames */
01877         uint32_t CRCFWD : 1;           /*!< [14] Terminate/Forward Received CRC */
01878         uint32_t CFEN : 1;             /*!< [15] MAC Control Frame Enable */
01879         uint32_t MAX_FL : 14;          /*!< [29:16] Maximum Frame Length */
01880         uint32_t NLC : 1;              /*!< [30] Payload Length Check Disable */
01881         uint32_t GRS : 1;              /*!< [31] Graceful Receive Stopped */
01882     } B;
01883 } hw_enet_rcr_t;
01884 
01885 /*!
01886  * @name Constants and macros for entire ENET_RCR register
01887  */
01888 /*@{*/
01889 #define HW_ENET_RCR_ADDR(x)      ((x) + 0x84U)
01890 
01891 #define HW_ENET_RCR(x)           (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
01892 #define HW_ENET_RCR_RD(x)        (HW_ENET_RCR(x).U)
01893 #define HW_ENET_RCR_WR(x, v)     (HW_ENET_RCR(x).U = (v))
01894 #define HW_ENET_RCR_SET(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) |  (v)))
01895 #define HW_ENET_RCR_CLR(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
01896 #define HW_ENET_RCR_TOG(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^  (v)))
01897 /*@}*/
01898 
01899 /*
01900  * Constants & macros for individual ENET_RCR bitfields
01901  */
01902 
01903 /*!
01904  * @name Register ENET_RCR, field LOOP[0] (RW)
01905  *
01906  * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
01907  * RMII_MODE must be written to 0.
01908  *
01909  * Values:
01910  * - 0 - Loopback disabled.
01911  * - 1 - Transmitted frames are looped back internal to the device and transmit
01912  *     MII output signals are not asserted. DRT must be cleared.
01913  */
01914 /*@{*/
01915 #define BP_ENET_RCR_LOOP     (0U)          /*!< Bit position for ENET_RCR_LOOP. */
01916 #define BM_ENET_RCR_LOOP     (0x00000001U) /*!< Bit mask for ENET_RCR_LOOP. */
01917 #define BS_ENET_RCR_LOOP     (1U)          /*!< Bit field size in bits for ENET_RCR_LOOP. */
01918 
01919 /*! @brief Read current value of the ENET_RCR_LOOP field. */
01920 #define BR_ENET_RCR_LOOP(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
01921 
01922 /*! @brief Format value for bitfield ENET_RCR_LOOP. */
01923 #define BF_ENET_RCR_LOOP(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP)
01924 
01925 /*! @brief Set the LOOP field to a new value. */
01926 #define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
01927 /*@}*/
01928 
01929 /*!
01930  * @name Register ENET_RCR, field DRT[1] (RW)
01931  *
01932  * Values:
01933  * - 0 - Receive path operates independently of transmit. Used for full-duplex
01934  *     or to monitor transmit activity in half-duplex mode.
01935  * - 1 - Disable reception of frames while transmitting. Normally used for
01936  *     half-duplex mode.
01937  */
01938 /*@{*/
01939 #define BP_ENET_RCR_DRT      (1U)          /*!< Bit position for ENET_RCR_DRT. */
01940 #define BM_ENET_RCR_DRT      (0x00000002U) /*!< Bit mask for ENET_RCR_DRT. */
01941 #define BS_ENET_RCR_DRT      (1U)          /*!< Bit field size in bits for ENET_RCR_DRT. */
01942 
01943 /*! @brief Read current value of the ENET_RCR_DRT field. */
01944 #define BR_ENET_RCR_DRT(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
01945 
01946 /*! @brief Format value for bitfield ENET_RCR_DRT. */
01947 #define BF_ENET_RCR_DRT(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT)
01948 
01949 /*! @brief Set the DRT field to a new value. */
01950 #define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
01951 /*@}*/
01952 
01953 /*!
01954  * @name Register ENET_RCR, field MII_MODE[2] (RW)
01955  *
01956  * This field must always be set.
01957  *
01958  * Values:
01959  * - 0 - Reserved.
01960  * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
01961  */
01962 /*@{*/
01963 #define BP_ENET_RCR_MII_MODE (2U)          /*!< Bit position for ENET_RCR_MII_MODE. */
01964 #define BM_ENET_RCR_MII_MODE (0x00000004U) /*!< Bit mask for ENET_RCR_MII_MODE. */
01965 #define BS_ENET_RCR_MII_MODE (1U)          /*!< Bit field size in bits for ENET_RCR_MII_MODE. */
01966 
01967 /*! @brief Read current value of the ENET_RCR_MII_MODE field. */
01968 #define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
01969 
01970 /*! @brief Format value for bitfield ENET_RCR_MII_MODE. */
01971 #define BF_ENET_RCR_MII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE)
01972 
01973 /*! @brief Set the MII_MODE field to a new value. */
01974 #define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
01975 /*@}*/
01976 
01977 /*!
01978  * @name Register ENET_RCR, field PROM[3] (RW)
01979  *
01980  * All frames are accepted regardless of address matching.
01981  *
01982  * Values:
01983  * - 0 - Disabled.
01984  * - 1 - Enabled.
01985  */
01986 /*@{*/
01987 #define BP_ENET_RCR_PROM     (3U)          /*!< Bit position for ENET_RCR_PROM. */
01988 #define BM_ENET_RCR_PROM     (0x00000008U) /*!< Bit mask for ENET_RCR_PROM. */
01989 #define BS_ENET_RCR_PROM     (1U)          /*!< Bit field size in bits for ENET_RCR_PROM. */
01990 
01991 /*! @brief Read current value of the ENET_RCR_PROM field. */
01992 #define BR_ENET_RCR_PROM(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
01993 
01994 /*! @brief Format value for bitfield ENET_RCR_PROM. */
01995 #define BF_ENET_RCR_PROM(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM)
01996 
01997 /*! @brief Set the PROM field to a new value. */
01998 #define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
01999 /*@}*/
02000 
02001 /*!
02002  * @name Register ENET_RCR, field BC_REJ[4] (RW)
02003  *
02004  * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
02005  * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
02006  * broadcast DA are accepted and the MISS (M) is set in the receive buffer
02007  * descriptor.
02008  */
02009 /*@{*/
02010 #define BP_ENET_RCR_BC_REJ   (4U)          /*!< Bit position for ENET_RCR_BC_REJ. */
02011 #define BM_ENET_RCR_BC_REJ   (0x00000010U) /*!< Bit mask for ENET_RCR_BC_REJ. */
02012 #define BS_ENET_RCR_BC_REJ   (1U)          /*!< Bit field size in bits for ENET_RCR_BC_REJ. */
02013 
02014 /*! @brief Read current value of the ENET_RCR_BC_REJ field. */
02015 #define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
02016 
02017 /*! @brief Format value for bitfield ENET_RCR_BC_REJ. */
02018 #define BF_ENET_RCR_BC_REJ(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ)
02019 
02020 /*! @brief Set the BC_REJ field to a new value. */
02021 #define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
02022 /*@}*/
02023 
02024 /*!
02025  * @name Register ENET_RCR, field FCE[5] (RW)
02026  *
02027  * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
02028  * transmitter stops transmitting data frames for a given duration.
02029  */
02030 /*@{*/
02031 #define BP_ENET_RCR_FCE      (5U)          /*!< Bit position for ENET_RCR_FCE. */
02032 #define BM_ENET_RCR_FCE      (0x00000020U) /*!< Bit mask for ENET_RCR_FCE. */
02033 #define BS_ENET_RCR_FCE      (1U)          /*!< Bit field size in bits for ENET_RCR_FCE. */
02034 
02035 /*! @brief Read current value of the ENET_RCR_FCE field. */
02036 #define BR_ENET_RCR_FCE(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
02037 
02038 /*! @brief Format value for bitfield ENET_RCR_FCE. */
02039 #define BF_ENET_RCR_FCE(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE)
02040 
02041 /*! @brief Set the FCE field to a new value. */
02042 #define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
02043 /*@}*/
02044 
02045 /*!
02046  * @name Register ENET_RCR, field RMII_MODE[8] (RW)
02047  *
02048  * Specifies whether the MAC is configured for MII mode or RMII operation .
02049  *
02050  * Values:
02051  * - 0 - MAC configured for MII mode.
02052  * - 1 - MAC configured for RMII operation.
02053  */
02054 /*@{*/
02055 #define BP_ENET_RCR_RMII_MODE (8U)         /*!< Bit position for ENET_RCR_RMII_MODE. */
02056 #define BM_ENET_RCR_RMII_MODE (0x00000100U) /*!< Bit mask for ENET_RCR_RMII_MODE. */
02057 #define BS_ENET_RCR_RMII_MODE (1U)         /*!< Bit field size in bits for ENET_RCR_RMII_MODE. */
02058 
02059 /*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
02060 #define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
02061 
02062 /*! @brief Format value for bitfield ENET_RCR_RMII_MODE. */
02063 #define BF_ENET_RCR_RMII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE)
02064 
02065 /*! @brief Set the RMII_MODE field to a new value. */
02066 #define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
02067 /*@}*/
02068 
02069 /*!
02070  * @name Register ENET_RCR, field RMII_10T[9] (RW)
02071  *
02072  * Enables 10-Mbps mode of the RMII .
02073  *
02074  * Values:
02075  * - 0 - 100 Mbps operation.
02076  * - 1 - 10 Mbps operation.
02077  */
02078 /*@{*/
02079 #define BP_ENET_RCR_RMII_10T (9U)          /*!< Bit position for ENET_RCR_RMII_10T. */
02080 #define BM_ENET_RCR_RMII_10T (0x00000200U) /*!< Bit mask for ENET_RCR_RMII_10T. */
02081 #define BS_ENET_RCR_RMII_10T (1U)          /*!< Bit field size in bits for ENET_RCR_RMII_10T. */
02082 
02083 /*! @brief Read current value of the ENET_RCR_RMII_10T field. */
02084 #define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
02085 
02086 /*! @brief Format value for bitfield ENET_RCR_RMII_10T. */
02087 #define BF_ENET_RCR_RMII_10T(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T)
02088 
02089 /*! @brief Set the RMII_10T field to a new value. */
02090 #define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
02091 /*@}*/
02092 
02093 /*!
02094  * @name Register ENET_RCR, field PADEN[12] (RW)
02095  *
02096  * Specifies whether the MAC removes padding from received frames.
02097  *
02098  * Values:
02099  * - 0 - No padding is removed on receive by the MAC.
02100  * - 1 - Padding is removed from received frames.
02101  */
02102 /*@{*/
02103 #define BP_ENET_RCR_PADEN    (12U)         /*!< Bit position for ENET_RCR_PADEN. */
02104 #define BM_ENET_RCR_PADEN    (0x00001000U) /*!< Bit mask for ENET_RCR_PADEN. */
02105 #define BS_ENET_RCR_PADEN    (1U)          /*!< Bit field size in bits for ENET_RCR_PADEN. */
02106 
02107 /*! @brief Read current value of the ENET_RCR_PADEN field. */
02108 #define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
02109 
02110 /*! @brief Format value for bitfield ENET_RCR_PADEN. */
02111 #define BF_ENET_RCR_PADEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN)
02112 
02113 /*! @brief Set the PADEN field to a new value. */
02114 #define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
02115 /*@}*/
02116 
02117 /*!
02118  * @name Register ENET_RCR, field PAUFWD[13] (RW)
02119  *
02120  * Specifies whether pause frames are terminated or forwarded.
02121  *
02122  * Values:
02123  * - 0 - Pause frames are terminated and discarded in the MAC.
02124  * - 1 - Pause frames are forwarded to the user application.
02125  */
02126 /*@{*/
02127 #define BP_ENET_RCR_PAUFWD   (13U)         /*!< Bit position for ENET_RCR_PAUFWD. */
02128 #define BM_ENET_RCR_PAUFWD   (0x00002000U) /*!< Bit mask for ENET_RCR_PAUFWD. */
02129 #define BS_ENET_RCR_PAUFWD   (1U)          /*!< Bit field size in bits for ENET_RCR_PAUFWD. */
02130 
02131 /*! @brief Read current value of the ENET_RCR_PAUFWD field. */
02132 #define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
02133 
02134 /*! @brief Format value for bitfield ENET_RCR_PAUFWD. */
02135 #define BF_ENET_RCR_PAUFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD)
02136 
02137 /*! @brief Set the PAUFWD field to a new value. */
02138 #define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
02139 /*@}*/
02140 
02141 /*!
02142  * @name Register ENET_RCR, field CRCFWD[14] (RW)
02143  *
02144  * Specifies whether the CRC field of received frames is transmitted or
02145  * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
02146  * field is checked and always terminated and removed.
02147  *
02148  * Values:
02149  * - 0 - The CRC field of received frames is transmitted to the user application.
02150  * - 1 - The CRC field is stripped from the frame.
02151  */
02152 /*@{*/
02153 #define BP_ENET_RCR_CRCFWD   (14U)         /*!< Bit position for ENET_RCR_CRCFWD. */
02154 #define BM_ENET_RCR_CRCFWD   (0x00004000U) /*!< Bit mask for ENET_RCR_CRCFWD. */
02155 #define BS_ENET_RCR_CRCFWD   (1U)          /*!< Bit field size in bits for ENET_RCR_CRCFWD. */
02156 
02157 /*! @brief Read current value of the ENET_RCR_CRCFWD field. */
02158 #define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
02159 
02160 /*! @brief Format value for bitfield ENET_RCR_CRCFWD. */
02161 #define BF_ENET_RCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD)
02162 
02163 /*! @brief Set the CRCFWD field to a new value. */
02164 #define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
02165 /*@}*/
02166 
02167 /*!
02168  * @name Register ENET_RCR, field CFEN[15] (RW)
02169  *
02170  * Enables/disables the MAC control frame.
02171  *
02172  * Values:
02173  * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
02174  *     accepted and forwarded to the client interface.
02175  * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
02176  *     silently discarded.
02177  */
02178 /*@{*/
02179 #define BP_ENET_RCR_CFEN     (15U)         /*!< Bit position for ENET_RCR_CFEN. */
02180 #define BM_ENET_RCR_CFEN     (0x00008000U) /*!< Bit mask for ENET_RCR_CFEN. */
02181 #define BS_ENET_RCR_CFEN     (1U)          /*!< Bit field size in bits for ENET_RCR_CFEN. */
02182 
02183 /*! @brief Read current value of the ENET_RCR_CFEN field. */
02184 #define BR_ENET_RCR_CFEN(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
02185 
02186 /*! @brief Format value for bitfield ENET_RCR_CFEN. */
02187 #define BF_ENET_RCR_CFEN(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN)
02188 
02189 /*! @brief Set the CFEN field to a new value. */
02190 #define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
02191 /*@}*/
02192 
02193 /*!
02194  * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
02195  *
02196  * Resets to decimal 1518. Length is measured starting at DA and includes the
02197  * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
02198  * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
02199  * to occur and set the LG field in the end of frame receive buffer descriptor.
02200  * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
02201  * supported.
02202  */
02203 /*@{*/
02204 #define BP_ENET_RCR_MAX_FL   (16U)         /*!< Bit position for ENET_RCR_MAX_FL. */
02205 #define BM_ENET_RCR_MAX_FL   (0x3FFF0000U) /*!< Bit mask for ENET_RCR_MAX_FL. */
02206 #define BS_ENET_RCR_MAX_FL   (14U)         /*!< Bit field size in bits for ENET_RCR_MAX_FL. */
02207 
02208 /*! @brief Read current value of the ENET_RCR_MAX_FL field. */
02209 #define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
02210 
02211 /*! @brief Format value for bitfield ENET_RCR_MAX_FL. */
02212 #define BF_ENET_RCR_MAX_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL)
02213 
02214 /*! @brief Set the MAX_FL field to a new value. */
02215 #define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
02216 /*@}*/
02217 
02218 /*!
02219  * @name Register ENET_RCR, field NLC[30] (RW)
02220  *
02221  * Enables/disables a payload length check.
02222  *
02223  * Values:
02224  * - 0 - The payload length check is disabled.
02225  * - 1 - The core checks the frame's payload length with the frame length/type
02226  *     field. Errors are indicated in the EIR[PLC] field.
02227  */
02228 /*@{*/
02229 #define BP_ENET_RCR_NLC      (30U)         /*!< Bit position for ENET_RCR_NLC. */
02230 #define BM_ENET_RCR_NLC      (0x40000000U) /*!< Bit mask for ENET_RCR_NLC. */
02231 #define BS_ENET_RCR_NLC      (1U)          /*!< Bit field size in bits for ENET_RCR_NLC. */
02232 
02233 /*! @brief Read current value of the ENET_RCR_NLC field. */
02234 #define BR_ENET_RCR_NLC(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
02235 
02236 /*! @brief Format value for bitfield ENET_RCR_NLC. */
02237 #define BF_ENET_RCR_NLC(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC)
02238 
02239 /*! @brief Set the NLC field to a new value. */
02240 #define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
02241 /*@}*/
02242 
02243 /*!
02244  * @name Register ENET_RCR, field GRS[31] (RO)
02245  *
02246  * Read-only status indicating that the MAC receive datapath is stopped.
02247  */
02248 /*@{*/
02249 #define BP_ENET_RCR_GRS      (31U)         /*!< Bit position for ENET_RCR_GRS. */
02250 #define BM_ENET_RCR_GRS      (0x80000000U) /*!< Bit mask for ENET_RCR_GRS. */
02251 #define BS_ENET_RCR_GRS      (1U)          /*!< Bit field size in bits for ENET_RCR_GRS. */
02252 
02253 /*! @brief Read current value of the ENET_RCR_GRS field. */
02254 #define BR_ENET_RCR_GRS(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
02255 /*@}*/
02256 
02257 /*******************************************************************************
02258  * HW_ENET_TCR - Transmit Control Register
02259  ******************************************************************************/
02260 
02261 /*!
02262  * @brief HW_ENET_TCR - Transmit Control Register (RW)
02263  *
02264  * Reset value: 0x00000000U
02265  *
02266  * TCR is read/write and configures the transmit block. This register is cleared
02267  * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
02268  */
02269 typedef union _hw_enet_tcr
02270 {
02271     uint32_t U;
02272     struct _hw_enet_tcr_bitfields
02273     {
02274         uint32_t GTS : 1;              /*!< [0] Graceful Transmit Stop */
02275         uint32_t RESERVED0 : 1;        /*!< [1]  */
02276         uint32_t FDEN : 1;             /*!< [2] Full-Duplex Enable */
02277         uint32_t TFC_PAUSE : 1;        /*!< [3] Transmit Frame Control Pause */
02278         uint32_t RFC_PAUSE : 1;        /*!< [4] Receive Frame Control Pause */
02279         uint32_t ADDSEL : 3;           /*!< [7:5] Source MAC Address Select On Transmit
02280                                         * */
02281         uint32_t ADDINS : 1;           /*!< [8] Set MAC Address On Transmit */
02282         uint32_t CRCFWD : 1;           /*!< [9] Forward Frame From Application With CRC
02283                                         * */
02284         uint32_t RESERVED1 : 22;       /*!< [31:10]  */
02285     } B;
02286 } hw_enet_tcr_t;
02287 
02288 /*!
02289  * @name Constants and macros for entire ENET_TCR register
02290  */
02291 /*@{*/
02292 #define HW_ENET_TCR_ADDR(x)      ((x) + 0xC4U)
02293 
02294 #define HW_ENET_TCR(x)           (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
02295 #define HW_ENET_TCR_RD(x)        (HW_ENET_TCR(x).U)
02296 #define HW_ENET_TCR_WR(x, v)     (HW_ENET_TCR(x).U = (v))
02297 #define HW_ENET_TCR_SET(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) |  (v)))
02298 #define HW_ENET_TCR_CLR(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
02299 #define HW_ENET_TCR_TOG(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^  (v)))
02300 /*@}*/
02301 
02302 /*
02303  * Constants & macros for individual ENET_TCR bitfields
02304  */
02305 
02306 /*!
02307  * @name Register ENET_TCR, field GTS[0] (RW)
02308  *
02309  * When this field is set, MAC stops transmission after any frame currently
02310  * transmitted is complete and EIR[GRA] is set. If frame transmission is not
02311  * currently underway, the GRA interrupt is asserted immediately. After transmission
02312  * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
02313  * transmitted. If an early collision occurs during transmission when GTS is set,
02314  * transmission stops after the collision. The frame is transmitted again after GTS is
02315  * cleared. There may be old frames in the transmit FIFO that transmit when GTS
02316  * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
02317  */
02318 /*@{*/
02319 #define BP_ENET_TCR_GTS      (0U)          /*!< Bit position for ENET_TCR_GTS. */
02320 #define BM_ENET_TCR_GTS      (0x00000001U) /*!< Bit mask for ENET_TCR_GTS. */
02321 #define BS_ENET_TCR_GTS      (1U)          /*!< Bit field size in bits for ENET_TCR_GTS. */
02322 
02323 /*! @brief Read current value of the ENET_TCR_GTS field. */
02324 #define BR_ENET_TCR_GTS(x)   (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
02325 
02326 /*! @brief Format value for bitfield ENET_TCR_GTS. */
02327 #define BF_ENET_TCR_GTS(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS)
02328 
02329 /*! @brief Set the GTS field to a new value. */
02330 #define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
02331 /*@}*/
02332 
02333 /*!
02334  * @name Register ENET_TCR, field FDEN[2] (RW)
02335  *
02336  * If this field is set, frames transmit independent of carrier sense and
02337  * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
02338  */
02339 /*@{*/
02340 #define BP_ENET_TCR_FDEN     (2U)          /*!< Bit position for ENET_TCR_FDEN. */
02341 #define BM_ENET_TCR_FDEN     (0x00000004U) /*!< Bit mask for ENET_TCR_FDEN. */
02342 #define BS_ENET_TCR_FDEN     (1U)          /*!< Bit field size in bits for ENET_TCR_FDEN. */
02343 
02344 /*! @brief Read current value of the ENET_TCR_FDEN field. */
02345 #define BR_ENET_TCR_FDEN(x)  (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
02346 
02347 /*! @brief Format value for bitfield ENET_TCR_FDEN. */
02348 #define BF_ENET_TCR_FDEN(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN)
02349 
02350 /*! @brief Set the FDEN field to a new value. */
02351 #define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
02352 /*@}*/
02353 
02354 /*!
02355  * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
02356  *
02357  * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
02358  * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
02359  * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
02360  * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
02361  * the MAC may continue transmitting a MAC control PAUSE frame.
02362  *
02363  * Values:
02364  * - 0 - No PAUSE frame transmitted.
02365  * - 1 - The MAC stops transmission of data frames after the current
02366  *     transmission is complete.
02367  */
02368 /*@{*/
02369 #define BP_ENET_TCR_TFC_PAUSE (3U)         /*!< Bit position for ENET_TCR_TFC_PAUSE. */
02370 #define BM_ENET_TCR_TFC_PAUSE (0x00000008U) /*!< Bit mask for ENET_TCR_TFC_PAUSE. */
02371 #define BS_ENET_TCR_TFC_PAUSE (1U)         /*!< Bit field size in bits for ENET_TCR_TFC_PAUSE. */
02372 
02373 /*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
02374 #define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
02375 
02376 /*! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. */
02377 #define BF_ENET_TCR_TFC_PAUSE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE)
02378 
02379 /*! @brief Set the TFC_PAUSE field to a new value. */
02380 #define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
02381 /*@}*/
02382 
02383 /*!
02384  * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
02385  *
02386  * This status field is set when a full-duplex flow control pause frame is
02387  * received and the transmitter pauses for the duration defined in this pause frame.
02388  * This field automatically clears when the pause duration is complete.
02389  */
02390 /*@{*/
02391 #define BP_ENET_TCR_RFC_PAUSE (4U)         /*!< Bit position for ENET_TCR_RFC_PAUSE. */
02392 #define BM_ENET_TCR_RFC_PAUSE (0x00000010U) /*!< Bit mask for ENET_TCR_RFC_PAUSE. */
02393 #define BS_ENET_TCR_RFC_PAUSE (1U)         /*!< Bit field size in bits for ENET_TCR_RFC_PAUSE. */
02394 
02395 /*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
02396 #define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
02397 /*@}*/
02398 
02399 /*!
02400  * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
02401  *
02402  * If ADDINS is set, indicates the MAC address that overwrites the source MAC
02403  * address.
02404  *
02405  * Values:
02406  * - 000 - Node MAC address programmed on PADDR1/2 registers.
02407  * - 100 - Reserved.
02408  * - 101 - Reserved.
02409  * - 110 - Reserved.
02410  */
02411 /*@{*/
02412 #define BP_ENET_TCR_ADDSEL   (5U)          /*!< Bit position for ENET_TCR_ADDSEL. */
02413 #define BM_ENET_TCR_ADDSEL   (0x000000E0U) /*!< Bit mask for ENET_TCR_ADDSEL. */
02414 #define BS_ENET_TCR_ADDSEL   (3U)          /*!< Bit field size in bits for ENET_TCR_ADDSEL. */
02415 
02416 /*! @brief Read current value of the ENET_TCR_ADDSEL field. */
02417 #define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
02418 
02419 /*! @brief Format value for bitfield ENET_TCR_ADDSEL. */
02420 #define BF_ENET_TCR_ADDSEL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL)
02421 
02422 /*! @brief Set the ADDSEL field to a new value. */
02423 #define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
02424 /*@}*/
02425 
02426 /*!
02427  * @name Register ENET_TCR, field ADDINS[8] (RW)
02428  *
02429  * Values:
02430  * - 0 - The source MAC address is not modified by the MAC.
02431  * - 1 - The MAC overwrites the source MAC address with the programmed MAC
02432  *     address according to ADDSEL.
02433  */
02434 /*@{*/
02435 #define BP_ENET_TCR_ADDINS   (8U)          /*!< Bit position for ENET_TCR_ADDINS. */
02436 #define BM_ENET_TCR_ADDINS   (0x00000100U) /*!< Bit mask for ENET_TCR_ADDINS. */
02437 #define BS_ENET_TCR_ADDINS   (1U)          /*!< Bit field size in bits for ENET_TCR_ADDINS. */
02438 
02439 /*! @brief Read current value of the ENET_TCR_ADDINS field. */
02440 #define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
02441 
02442 /*! @brief Format value for bitfield ENET_TCR_ADDINS. */
02443 #define BF_ENET_TCR_ADDINS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS)
02444 
02445 /*! @brief Set the ADDINS field to a new value. */
02446 #define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
02447 /*@}*/
02448 
02449 /*!
02450  * @name Register ENET_TCR, field CRCFWD[9] (RW)
02451  *
02452  * Values:
02453  * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
02454  * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
02455  *     expecting a frame with CRC from the application.
02456  */
02457 /*@{*/
02458 #define BP_ENET_TCR_CRCFWD   (9U)          /*!< Bit position for ENET_TCR_CRCFWD. */
02459 #define BM_ENET_TCR_CRCFWD   (0x00000200U) /*!< Bit mask for ENET_TCR_CRCFWD. */
02460 #define BS_ENET_TCR_CRCFWD   (1U)          /*!< Bit field size in bits for ENET_TCR_CRCFWD. */
02461 
02462 /*! @brief Read current value of the ENET_TCR_CRCFWD field. */
02463 #define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
02464 
02465 /*! @brief Format value for bitfield ENET_TCR_CRCFWD. */
02466 #define BF_ENET_TCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD)
02467 
02468 /*! @brief Set the CRCFWD field to a new value. */
02469 #define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
02470 /*@}*/
02471 
02472 /*******************************************************************************
02473  * HW_ENET_PALR - Physical Address Lower Register
02474  ******************************************************************************/
02475 
02476 /*!
02477  * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
02478  *
02479  * Reset value: 0x00000000U
02480  *
02481  * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
02482  * in the address recognition process to compare with the destination address
02483  * (DA) field of receive frames with an individual DA. In addition, this register
02484  * is used in bytes 0 through 3 of the six-byte source address field when
02485  * transmitting PAUSE frames. This register is not reset and you must initialize it.
02486  */
02487 typedef union _hw_enet_palr
02488 {
02489     uint32_t U;
02490     struct _hw_enet_palr_bitfields
02491     {
02492         uint32_t PADDR1 : 32;          /*!< [31:0] Pause Address */
02493     } B;
02494 } hw_enet_palr_t;
02495 
02496 /*!
02497  * @name Constants and macros for entire ENET_PALR register
02498  */
02499 /*@{*/
02500 #define HW_ENET_PALR_ADDR(x)     ((x) + 0xE4U)
02501 
02502 #define HW_ENET_PALR(x)          (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
02503 #define HW_ENET_PALR_RD(x)       (HW_ENET_PALR(x).U)
02504 #define HW_ENET_PALR_WR(x, v)    (HW_ENET_PALR(x).U = (v))
02505 #define HW_ENET_PALR_SET(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) |  (v)))
02506 #define HW_ENET_PALR_CLR(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
02507 #define HW_ENET_PALR_TOG(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^  (v)))
02508 /*@}*/
02509 
02510 /*
02511  * Constants & macros for individual ENET_PALR bitfields
02512  */
02513 
02514 /*!
02515  * @name Register ENET_PALR, field PADDR1[31:0] (RW)
02516  *
02517  * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
02518  * 6-byte individual address are used for exact match and the source address
02519  * field in PAUSE frames.
02520  */
02521 /*@{*/
02522 #define BP_ENET_PALR_PADDR1  (0U)          /*!< Bit position for ENET_PALR_PADDR1. */
02523 #define BM_ENET_PALR_PADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_PALR_PADDR1. */
02524 #define BS_ENET_PALR_PADDR1  (32U)         /*!< Bit field size in bits for ENET_PALR_PADDR1. */
02525 
02526 /*! @brief Read current value of the ENET_PALR_PADDR1 field. */
02527 #define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
02528 
02529 /*! @brief Format value for bitfield ENET_PALR_PADDR1. */
02530 #define BF_ENET_PALR_PADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1)
02531 
02532 /*! @brief Set the PADDR1 field to a new value. */
02533 #define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
02534 /*@}*/
02535 
02536 /*******************************************************************************
02537  * HW_ENET_PAUR - Physical Address Upper Register
02538  ******************************************************************************/
02539 
02540 /*!
02541  * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
02542  *
02543  * Reset value: 0x00008808U
02544  *
02545  * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
02546  * the address recognition process to compare with the destination address (DA)
02547  * field of receive frames with an individual DA. In addition, this register is
02548  * used in bytes 4 and 5 of the six-byte source address field when transmitting
02549  * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
02550  * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
02551  * you must initialize it.
02552  */
02553 typedef union _hw_enet_paur
02554 {
02555     uint32_t U;
02556     struct _hw_enet_paur_bitfields
02557     {
02558         uint32_t TYPE : 16;            /*!< [15:0] Type Field In PAUSE Frames */
02559         uint32_t PADDR2 : 16;          /*!< [31:16]  */
02560     } B;
02561 } hw_enet_paur_t;
02562 
02563 /*!
02564  * @name Constants and macros for entire ENET_PAUR register
02565  */
02566 /*@{*/
02567 #define HW_ENET_PAUR_ADDR(x)     ((x) + 0xE8U)
02568 
02569 #define HW_ENET_PAUR(x)          (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
02570 #define HW_ENET_PAUR_RD(x)       (HW_ENET_PAUR(x).U)
02571 #define HW_ENET_PAUR_WR(x, v)    (HW_ENET_PAUR(x).U = (v))
02572 #define HW_ENET_PAUR_SET(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) |  (v)))
02573 #define HW_ENET_PAUR_CLR(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
02574 #define HW_ENET_PAUR_TOG(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^  (v)))
02575 /*@}*/
02576 
02577 /*
02578  * Constants & macros for individual ENET_PAUR bitfields
02579  */
02580 
02581 /*!
02582  * @name Register ENET_PAUR, field TYPE[15:0] (RO)
02583  *
02584  * These fields have a constant value of 0x8808.
02585  */
02586 /*@{*/
02587 #define BP_ENET_PAUR_TYPE    (0U)          /*!< Bit position for ENET_PAUR_TYPE. */
02588 #define BM_ENET_PAUR_TYPE    (0x0000FFFFU) /*!< Bit mask for ENET_PAUR_TYPE. */
02589 #define BS_ENET_PAUR_TYPE    (16U)         /*!< Bit field size in bits for ENET_PAUR_TYPE. */
02590 
02591 /*! @brief Read current value of the ENET_PAUR_TYPE field. */
02592 #define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
02593 /*@}*/
02594 
02595 /*!
02596  * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
02597  *
02598  * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
02599  * for exact match, and the source address field in PAUSE frames.
02600  */
02601 /*@{*/
02602 #define BP_ENET_PAUR_PADDR2  (16U)         /*!< Bit position for ENET_PAUR_PADDR2. */
02603 #define BM_ENET_PAUR_PADDR2  (0xFFFF0000U) /*!< Bit mask for ENET_PAUR_PADDR2. */
02604 #define BS_ENET_PAUR_PADDR2  (16U)         /*!< Bit field size in bits for ENET_PAUR_PADDR2. */
02605 
02606 /*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
02607 #define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
02608 
02609 /*! @brief Format value for bitfield ENET_PAUR_PADDR2. */
02610 #define BF_ENET_PAUR_PADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2)
02611 
02612 /*! @brief Set the PADDR2 field to a new value. */
02613 #define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
02614 /*@}*/
02615 
02616 /*******************************************************************************
02617  * HW_ENET_OPD - Opcode/Pause Duration Register
02618  ******************************************************************************/
02619 
02620 /*!
02621  * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
02622  *
02623  * Reset value: 0x00010000U
02624  *
02625  * OPD is read/write accessible. This register contains the 16-bit opcode and
02626  * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
02627  * field is a constant value, 0x0001. When another node detects a PAUSE frame,
02628  * that node pauses transmission for the duration specified in the pause duration
02629  * field. The lower 16 bits of this register are not reset and you must initialize
02630  * it.
02631  */
02632 typedef union _hw_enet_opd
02633 {
02634     uint32_t U;
02635     struct _hw_enet_opd_bitfields
02636     {
02637         uint32_t PAUSE_DUR : 16;       /*!< [15:0] Pause Duration */
02638         uint32_t OPCODE : 16;          /*!< [31:16] Opcode Field In PAUSE Frames */
02639     } B;
02640 } hw_enet_opd_t;
02641 
02642 /*!
02643  * @name Constants and macros for entire ENET_OPD register
02644  */
02645 /*@{*/
02646 #define HW_ENET_OPD_ADDR(x)      ((x) + 0xECU)
02647 
02648 #define HW_ENET_OPD(x)           (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
02649 #define HW_ENET_OPD_RD(x)        (HW_ENET_OPD(x).U)
02650 #define HW_ENET_OPD_WR(x, v)     (HW_ENET_OPD(x).U = (v))
02651 #define HW_ENET_OPD_SET(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) |  (v)))
02652 #define HW_ENET_OPD_CLR(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
02653 #define HW_ENET_OPD_TOG(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^  (v)))
02654 /*@}*/
02655 
02656 /*
02657  * Constants & macros for individual ENET_OPD bitfields
02658  */
02659 
02660 /*!
02661  * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
02662  *
02663  * Pause duration field used in PAUSE frames.
02664  */
02665 /*@{*/
02666 #define BP_ENET_OPD_PAUSE_DUR (0U)         /*!< Bit position for ENET_OPD_PAUSE_DUR. */
02667 #define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) /*!< Bit mask for ENET_OPD_PAUSE_DUR. */
02668 #define BS_ENET_OPD_PAUSE_DUR (16U)        /*!< Bit field size in bits for ENET_OPD_PAUSE_DUR. */
02669 
02670 /*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
02671 #define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
02672 
02673 /*! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. */
02674 #define BF_ENET_OPD_PAUSE_DUR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR)
02675 
02676 /*! @brief Set the PAUSE_DUR field to a new value. */
02677 #define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
02678 /*@}*/
02679 
02680 /*!
02681  * @name Register ENET_OPD, field OPCODE[31:16] (RO)
02682  *
02683  * These fields have a constant value of 0x0001.
02684  */
02685 /*@{*/
02686 #define BP_ENET_OPD_OPCODE   (16U)         /*!< Bit position for ENET_OPD_OPCODE. */
02687 #define BM_ENET_OPD_OPCODE   (0xFFFF0000U) /*!< Bit mask for ENET_OPD_OPCODE. */
02688 #define BS_ENET_OPD_OPCODE   (16U)         /*!< Bit field size in bits for ENET_OPD_OPCODE. */
02689 
02690 /*! @brief Read current value of the ENET_OPD_OPCODE field. */
02691 #define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
02692 /*@}*/
02693 
02694 /*******************************************************************************
02695  * HW_ENET_IAUR - Descriptor Individual Upper Address Register
02696  ******************************************************************************/
02697 
02698 /*!
02699  * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
02700  *
02701  * Reset value: 0x00000000U
02702  *
02703  * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
02704  * The address recognition process uses this table to check for a possible match
02705  * with the destination address (DA) field of receive frames with an individual
02706  * DA. This register is not reset and you must initialize it.
02707  */
02708 typedef union _hw_enet_iaur
02709 {
02710     uint32_t U;
02711     struct _hw_enet_iaur_bitfields
02712     {
02713         uint32_t IADDR1 : 32;          /*!< [31:0]  */
02714     } B;
02715 } hw_enet_iaur_t;
02716 
02717 /*!
02718  * @name Constants and macros for entire ENET_IAUR register
02719  */
02720 /*@{*/
02721 #define HW_ENET_IAUR_ADDR(x)     ((x) + 0x118U)
02722 
02723 #define HW_ENET_IAUR(x)          (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
02724 #define HW_ENET_IAUR_RD(x)       (HW_ENET_IAUR(x).U)
02725 #define HW_ENET_IAUR_WR(x, v)    (HW_ENET_IAUR(x).U = (v))
02726 #define HW_ENET_IAUR_SET(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) |  (v)))
02727 #define HW_ENET_IAUR_CLR(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
02728 #define HW_ENET_IAUR_TOG(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^  (v)))
02729 /*@}*/
02730 
02731 /*
02732  * Constants & macros for individual ENET_IAUR bitfields
02733  */
02734 
02735 /*!
02736  * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
02737  *
02738  * Contains the upper 32 bits of the 64-bit hash table used in the address
02739  * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
02740  * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
02741  */
02742 /*@{*/
02743 #define BP_ENET_IAUR_IADDR1  (0U)          /*!< Bit position for ENET_IAUR_IADDR1. */
02744 #define BM_ENET_IAUR_IADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_IAUR_IADDR1. */
02745 #define BS_ENET_IAUR_IADDR1  (32U)         /*!< Bit field size in bits for ENET_IAUR_IADDR1. */
02746 
02747 /*! @brief Read current value of the ENET_IAUR_IADDR1 field. */
02748 #define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
02749 
02750 /*! @brief Format value for bitfield ENET_IAUR_IADDR1. */
02751 #define BF_ENET_IAUR_IADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1)
02752 
02753 /*! @brief Set the IADDR1 field to a new value. */
02754 #define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
02755 /*@}*/
02756 
02757 /*******************************************************************************
02758  * HW_ENET_IALR - Descriptor Individual Lower Address Register
02759  ******************************************************************************/
02760 
02761 /*!
02762  * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
02763  *
02764  * Reset value: 0x00000000U
02765  *
02766  * IALR contains the lower 32 bits of the 64-bit individual address hash table.
02767  * The address recognition process uses this table to check for a possible match
02768  * with the DA field of receive frames with an individual DA. This register is
02769  * not reset and you must initialize it.
02770  */
02771 typedef union _hw_enet_ialr
02772 {
02773     uint32_t U;
02774     struct _hw_enet_ialr_bitfields
02775     {
02776         uint32_t IADDR2 : 32;          /*!< [31:0]  */
02777     } B;
02778 } hw_enet_ialr_t;
02779 
02780 /*!
02781  * @name Constants and macros for entire ENET_IALR register
02782  */
02783 /*@{*/
02784 #define HW_ENET_IALR_ADDR(x)     ((x) + 0x11CU)
02785 
02786 #define HW_ENET_IALR(x)          (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
02787 #define HW_ENET_IALR_RD(x)       (HW_ENET_IALR(x).U)
02788 #define HW_ENET_IALR_WR(x, v)    (HW_ENET_IALR(x).U = (v))
02789 #define HW_ENET_IALR_SET(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) |  (v)))
02790 #define HW_ENET_IALR_CLR(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
02791 #define HW_ENET_IALR_TOG(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^  (v)))
02792 /*@}*/
02793 
02794 /*
02795  * Constants & macros for individual ENET_IALR bitfields
02796  */
02797 
02798 /*!
02799  * @name Register ENET_IALR, field IADDR2[31:0] (RW)
02800  *
02801  * Contains the lower 32 bits of the 64-bit hash table used in the address
02802  * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
02803  * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
02804  */
02805 /*@{*/
02806 #define BP_ENET_IALR_IADDR2  (0U)          /*!< Bit position for ENET_IALR_IADDR2. */
02807 #define BM_ENET_IALR_IADDR2  (0xFFFFFFFFU) /*!< Bit mask for ENET_IALR_IADDR2. */
02808 #define BS_ENET_IALR_IADDR2  (32U)         /*!< Bit field size in bits for ENET_IALR_IADDR2. */
02809 
02810 /*! @brief Read current value of the ENET_IALR_IADDR2 field. */
02811 #define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
02812 
02813 /*! @brief Format value for bitfield ENET_IALR_IADDR2. */
02814 #define BF_ENET_IALR_IADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2)
02815 
02816 /*! @brief Set the IADDR2 field to a new value. */
02817 #define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
02818 /*@}*/
02819 
02820 /*******************************************************************************
02821  * HW_ENET_GAUR - Descriptor Group Upper Address Register
02822  ******************************************************************************/
02823 
02824 /*!
02825  * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
02826  *
02827  * Reset value: 0x00000000U
02828  *
02829  * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
02830  * recognition process for receive frames with a multicast address. You must
02831  * initialize this register.
02832  */
02833 typedef union _hw_enet_gaur
02834 {
02835     uint32_t U;
02836     struct _hw_enet_gaur_bitfields
02837     {
02838         uint32_t GADDR1 : 32;          /*!< [31:0]  */
02839     } B;
02840 } hw_enet_gaur_t;
02841 
02842 /*!
02843  * @name Constants and macros for entire ENET_GAUR register
02844  */
02845 /*@{*/
02846 #define HW_ENET_GAUR_ADDR(x)     ((x) + 0x120U)
02847 
02848 #define HW_ENET_GAUR(x)          (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
02849 #define HW_ENET_GAUR_RD(x)       (HW_ENET_GAUR(x).U)
02850 #define HW_ENET_GAUR_WR(x, v)    (HW_ENET_GAUR(x).U = (v))
02851 #define HW_ENET_GAUR_SET(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) |  (v)))
02852 #define HW_ENET_GAUR_CLR(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
02853 #define HW_ENET_GAUR_TOG(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^  (v)))
02854 /*@}*/
02855 
02856 /*
02857  * Constants & macros for individual ENET_GAUR bitfields
02858  */
02859 
02860 /*!
02861  * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
02862  *
02863  * Contains the upper 32 bits of the 64-bit hash table used in the address
02864  * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
02865  * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
02866  */
02867 /*@{*/
02868 #define BP_ENET_GAUR_GADDR1  (0U)          /*!< Bit position for ENET_GAUR_GADDR1. */
02869 #define BM_ENET_GAUR_GADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_GAUR_GADDR1. */
02870 #define BS_ENET_GAUR_GADDR1  (32U)         /*!< Bit field size in bits for ENET_GAUR_GADDR1. */
02871 
02872 /*! @brief Read current value of the ENET_GAUR_GADDR1 field. */
02873 #define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
02874 
02875 /*! @brief Format value for bitfield ENET_GAUR_GADDR1. */
02876 #define BF_ENET_GAUR_GADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1)
02877 
02878 /*! @brief Set the GADDR1 field to a new value. */
02879 #define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
02880 /*@}*/
02881 
02882 /*******************************************************************************
02883  * HW_ENET_GALR - Descriptor Group Lower Address Register
02884  ******************************************************************************/
02885 
02886 /*!
02887  * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
02888  *
02889  * Reset value: 0x00000000U
02890  *
02891  * GALR contains the lower 32 bits of the 64-bit hash table used in the address
02892  * recognition process for receive frames with a multicast address. You must
02893  * initialize this register.
02894  */
02895 typedef union _hw_enet_galr
02896 {
02897     uint32_t U;
02898     struct _hw_enet_galr_bitfields
02899     {
02900         uint32_t GADDR2 : 32;          /*!< [31:0]  */
02901     } B;
02902 } hw_enet_galr_t;
02903 
02904 /*!
02905  * @name Constants and macros for entire ENET_GALR register
02906  */
02907 /*@{*/
02908 #define HW_ENET_GALR_ADDR(x)     ((x) + 0x124U)
02909 
02910 #define HW_ENET_GALR(x)          (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
02911 #define HW_ENET_GALR_RD(x)       (HW_ENET_GALR(x).U)
02912 #define HW_ENET_GALR_WR(x, v)    (HW_ENET_GALR(x).U = (v))
02913 #define HW_ENET_GALR_SET(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) |  (v)))
02914 #define HW_ENET_GALR_CLR(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
02915 #define HW_ENET_GALR_TOG(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^  (v)))
02916 /*@}*/
02917 
02918 /*
02919  * Constants & macros for individual ENET_GALR bitfields
02920  */
02921 
02922 /*!
02923  * @name Register ENET_GALR, field GADDR2[31:0] (RW)
02924  *
02925  * Contains the lower 32 bits of the 64-bit hash table used in the address
02926  * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
02927  * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
02928  */
02929 /*@{*/
02930 #define BP_ENET_GALR_GADDR2  (0U)          /*!< Bit position for ENET_GALR_GADDR2. */
02931 #define BM_ENET_GALR_GADDR2  (0xFFFFFFFFU) /*!< Bit mask for ENET_GALR_GADDR2. */
02932 #define BS_ENET_GALR_GADDR2  (32U)         /*!< Bit field size in bits for ENET_GALR_GADDR2. */
02933 
02934 /*! @brief Read current value of the ENET_GALR_GADDR2 field. */
02935 #define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
02936 
02937 /*! @brief Format value for bitfield ENET_GALR_GADDR2. */
02938 #define BF_ENET_GALR_GADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2)
02939 
02940 /*! @brief Set the GADDR2 field to a new value. */
02941 #define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
02942 /*@}*/
02943 
02944 /*******************************************************************************
02945  * HW_ENET_TFWR - Transmit FIFO Watermark Register
02946  ******************************************************************************/
02947 
02948 /*!
02949  * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
02950  *
02951  * Reset value: 0x00000000U
02952  *
02953  * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
02954  * in the transmit FIFO before transmission of a frame can begin. This allows you
02955  * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
02956  * latency (TFWR = 11) due to contention for the system bus. Setting the
02957  * watermark to a high value minimizes the risk of transmit FIFO underrun due to
02958  * contention for the system bus. The byte counts associated with the TFWR field may need
02959  * to be modified to match a given system requirement. For example, worst case
02960  * bus access latency by the transmit data DMA channel. When the FIFO level
02961  * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
02962  * transmit control logic starts frame transmission even before the end-of-frame is
02963  * available in the FIFO (cut-through operation). If a complete frame has a size
02964  * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
02965  * to the line. To enable store and forward on the Transmit path, set STR_FWD to
02966  * '1'. In this case, the MAC starts to transmit data only when a complete frame
02967  * is stored in the Transmit FIFO.
02968  */
02969 typedef union _hw_enet_tfwr
02970 {
02971     uint32_t U;
02972     struct _hw_enet_tfwr_bitfields
02973     {
02974         uint32_t TFWR : 6;             /*!< [5:0] Transmit FIFO Write */
02975         uint32_t RESERVED0 : 2;        /*!< [7:6]  */
02976         uint32_t STRFWD : 1;           /*!< [8] Store And Forward Enable */
02977         uint32_t RESERVED1 : 23;       /*!< [31:9]  */
02978     } B;
02979 } hw_enet_tfwr_t;
02980 
02981 /*!
02982  * @name Constants and macros for entire ENET_TFWR register
02983  */
02984 /*@{*/
02985 #define HW_ENET_TFWR_ADDR(x)     ((x) + 0x144U)
02986 
02987 #define HW_ENET_TFWR(x)          (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
02988 #define HW_ENET_TFWR_RD(x)       (HW_ENET_TFWR(x).U)
02989 #define HW_ENET_TFWR_WR(x, v)    (HW_ENET_TFWR(x).U = (v))
02990 #define HW_ENET_TFWR_SET(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) |  (v)))
02991 #define HW_ENET_TFWR_CLR(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
02992 #define HW_ENET_TFWR_TOG(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^  (v)))
02993 /*@}*/
02994 
02995 /*
02996  * Constants & macros for individual ENET_TFWR bitfields
02997  */
02998 
02999 /*!
03000  * @name Register ENET_TFWR, field TFWR[5:0] (RW)
03001  *
03002  * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
03003  * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
03004  * begins. If a frame with less than the threshold is written, it is still sent
03005  * independently of this threshold setting. The threshold is relevant only if the
03006  * frame is larger than the threshold given. This chip may not support the maximum
03007  * number of bytes written shown below. See the chip-specific information for the
03008  * ENET module for this value.
03009  *
03010  * Values:
03011  * - 000000 - 64 bytes written.
03012  * - 000001 - 64 bytes written.
03013  * - 000010 - 128 bytes written.
03014  * - 000011 - 192 bytes written.
03015  * - 111110 - 3968 bytes written.
03016  * - 111111 - 4032 bytes written.
03017  */
03018 /*@{*/
03019 #define BP_ENET_TFWR_TFWR    (0U)          /*!< Bit position for ENET_TFWR_TFWR. */
03020 #define BM_ENET_TFWR_TFWR    (0x0000003FU) /*!< Bit mask for ENET_TFWR_TFWR. */
03021 #define BS_ENET_TFWR_TFWR    (6U)          /*!< Bit field size in bits for ENET_TFWR_TFWR. */
03022 
03023 /*! @brief Read current value of the ENET_TFWR_TFWR field. */
03024 #define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
03025 
03026 /*! @brief Format value for bitfield ENET_TFWR_TFWR. */
03027 #define BF_ENET_TFWR_TFWR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR)
03028 
03029 /*! @brief Set the TFWR field to a new value. */
03030 #define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
03031 /*@}*/
03032 
03033 /*!
03034  * @name Register ENET_TFWR, field STRFWD[8] (RW)
03035  *
03036  * Values:
03037  * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
03038  * - 1 - Enabled.
03039  */
03040 /*@{*/
03041 #define BP_ENET_TFWR_STRFWD  (8U)          /*!< Bit position for ENET_TFWR_STRFWD. */
03042 #define BM_ENET_TFWR_STRFWD  (0x00000100U) /*!< Bit mask for ENET_TFWR_STRFWD. */
03043 #define BS_ENET_TFWR_STRFWD  (1U)          /*!< Bit field size in bits for ENET_TFWR_STRFWD. */
03044 
03045 /*! @brief Read current value of the ENET_TFWR_STRFWD field. */
03046 #define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
03047 
03048 /*! @brief Format value for bitfield ENET_TFWR_STRFWD. */
03049 #define BF_ENET_TFWR_STRFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD)
03050 
03051 /*! @brief Set the STRFWD field to a new value. */
03052 #define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
03053 /*@}*/
03054 
03055 /*******************************************************************************
03056  * HW_ENET_RDSR - Receive Descriptor Ring Start Register
03057  ******************************************************************************/
03058 
03059 /*!
03060  * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
03061  *
03062  * Reset value: 0x00000000U
03063  *
03064  * RDSR points to the beginning of the circular receive buffer descriptor queue
03065  * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
03066  * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
03067  * by 16. This register must be initialized prior to operation
03068  */
03069 typedef union _hw_enet_rdsr
03070 {
03071     uint32_t U;
03072     struct _hw_enet_rdsr_bitfields
03073     {
03074         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
03075         uint32_t R_DES_START : 29;     /*!< [31:3]  */
03076     } B;
03077 } hw_enet_rdsr_t;
03078 
03079 /*!
03080  * @name Constants and macros for entire ENET_RDSR register
03081  */
03082 /*@{*/
03083 #define HW_ENET_RDSR_ADDR(x)     ((x) + 0x180U)
03084 
03085 #define HW_ENET_RDSR(x)          (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
03086 #define HW_ENET_RDSR_RD(x)       (HW_ENET_RDSR(x).U)
03087 #define HW_ENET_RDSR_WR(x, v)    (HW_ENET_RDSR(x).U = (v))
03088 #define HW_ENET_RDSR_SET(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) |  (v)))
03089 #define HW_ENET_RDSR_CLR(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
03090 #define HW_ENET_RDSR_TOG(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^  (v)))
03091 /*@}*/
03092 
03093 /*
03094  * Constants & macros for individual ENET_RDSR bitfields
03095  */
03096 
03097 /*!
03098  * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
03099  *
03100  * Pointer to the beginning of the receive buffer descriptor queue.
03101  */
03102 /*@{*/
03103 #define BP_ENET_RDSR_R_DES_START (3U)      /*!< Bit position for ENET_RDSR_R_DES_START. */
03104 #define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_RDSR_R_DES_START. */
03105 #define BS_ENET_RDSR_R_DES_START (29U)     /*!< Bit field size in bits for ENET_RDSR_R_DES_START. */
03106 
03107 /*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
03108 #define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
03109 
03110 /*! @brief Format value for bitfield ENET_RDSR_R_DES_START. */
03111 #define BF_ENET_RDSR_R_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START)
03112 
03113 /*! @brief Set the R_DES_START field to a new value. */
03114 #define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
03115 /*@}*/
03116 
03117 /*******************************************************************************
03118  * HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
03119  ******************************************************************************/
03120 
03121 /*!
03122  * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
03123  *
03124  * Reset value: 0x00000000U
03125  *
03126  * TDSR provides a pointer to the beginning of the circular transmit buffer
03127  * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
03128  * must be zero); however, it is recommended to be 128-bit aligned, that is,
03129  * evenly divisible by 16. This register must be initialized prior to operation.
03130  */
03131 typedef union _hw_enet_tdsr
03132 {
03133     uint32_t U;
03134     struct _hw_enet_tdsr_bitfields
03135     {
03136         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
03137         uint32_t X_DES_START : 29;     /*!< [31:3]  */
03138     } B;
03139 } hw_enet_tdsr_t;
03140 
03141 /*!
03142  * @name Constants and macros for entire ENET_TDSR register
03143  */
03144 /*@{*/
03145 #define HW_ENET_TDSR_ADDR(x)     ((x) + 0x184U)
03146 
03147 #define HW_ENET_TDSR(x)          (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
03148 #define HW_ENET_TDSR_RD(x)       (HW_ENET_TDSR(x).U)
03149 #define HW_ENET_TDSR_WR(x, v)    (HW_ENET_TDSR(x).U = (v))
03150 #define HW_ENET_TDSR_SET(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) |  (v)))
03151 #define HW_ENET_TDSR_CLR(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
03152 #define HW_ENET_TDSR_TOG(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^  (v)))
03153 /*@}*/
03154 
03155 /*
03156  * Constants & macros for individual ENET_TDSR bitfields
03157  */
03158 
03159 /*!
03160  * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
03161  *
03162  * Pointer to the beginning of the transmit buffer descriptor queue.
03163  */
03164 /*@{*/
03165 #define BP_ENET_TDSR_X_DES_START (3U)      /*!< Bit position for ENET_TDSR_X_DES_START. */
03166 #define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_TDSR_X_DES_START. */
03167 #define BS_ENET_TDSR_X_DES_START (29U)     /*!< Bit field size in bits for ENET_TDSR_X_DES_START. */
03168 
03169 /*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
03170 #define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
03171 
03172 /*! @brief Format value for bitfield ENET_TDSR_X_DES_START. */
03173 #define BF_ENET_TDSR_X_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START)
03174 
03175 /*! @brief Set the X_DES_START field to a new value. */
03176 #define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
03177 /*@}*/
03178 
03179 /*******************************************************************************
03180  * HW_ENET_MRBR - Maximum Receive Buffer Size Register
03181  ******************************************************************************/
03182 
03183 /*!
03184  * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
03185  *
03186  * Reset value: 0x00000000U
03187  *
03188  * The MRBR is a user-programmable register that dictates the maximum size of
03189  * all receive buffers. This value should take into consideration that the receive
03190  * CRC is always written into the last receive buffer. To allow one maximum size
03191  * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
03192  * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
03193  * set to zero by the device. To minimize bus usage (descriptor fetches), set
03194  * MRBR greater than or equal to 256 bytes. This register must be initialized
03195  * before operation.
03196  */
03197 typedef union _hw_enet_mrbr
03198 {
03199     uint32_t U;
03200     struct _hw_enet_mrbr_bitfields
03201     {
03202         uint32_t RESERVED0 : 4;        /*!< [3:0]  */
03203         uint32_t R_BUF_SIZE : 10;      /*!< [13:4]  */
03204         uint32_t RESERVED1 : 18;       /*!< [31:14]  */
03205     } B;
03206 } hw_enet_mrbr_t;
03207 
03208 /*!
03209  * @name Constants and macros for entire ENET_MRBR register
03210  */
03211 /*@{*/
03212 #define HW_ENET_MRBR_ADDR(x)     ((x) + 0x188U)
03213 
03214 #define HW_ENET_MRBR(x)          (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
03215 #define HW_ENET_MRBR_RD(x)       (HW_ENET_MRBR(x).U)
03216 #define HW_ENET_MRBR_WR(x, v)    (HW_ENET_MRBR(x).U = (v))
03217 #define HW_ENET_MRBR_SET(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) |  (v)))
03218 #define HW_ENET_MRBR_CLR(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
03219 #define HW_ENET_MRBR_TOG(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^  (v)))
03220 /*@}*/
03221 
03222 /*
03223  * Constants & macros for individual ENET_MRBR bitfields
03224  */
03225 
03226 /*!
03227  * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
03228  *
03229  * Receive buffer size in bytes.
03230  */
03231 /*@{*/
03232 #define BP_ENET_MRBR_R_BUF_SIZE (4U)       /*!< Bit position for ENET_MRBR_R_BUF_SIZE. */
03233 #define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) /*!< Bit mask for ENET_MRBR_R_BUF_SIZE. */
03234 #define BS_ENET_MRBR_R_BUF_SIZE (10U)      /*!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE. */
03235 
03236 /*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
03237 #define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
03238 
03239 /*! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. */
03240 #define BF_ENET_MRBR_R_BUF_SIZE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE)
03241 
03242 /*! @brief Set the R_BUF_SIZE field to a new value. */
03243 #define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
03244 /*@}*/
03245 
03246 /*******************************************************************************
03247  * HW_ENET_RSFL - Receive FIFO Section Full Threshold
03248  ******************************************************************************/
03249 
03250 /*!
03251  * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
03252  *
03253  * Reset value: 0x00000000U
03254  */
03255 typedef union _hw_enet_rsfl
03256 {
03257     uint32_t U;
03258     struct _hw_enet_rsfl_bitfields
03259     {
03260         uint32_t RX_SECTION_FULL : 8;  /*!< [7:0] Value Of Receive FIFO
03261                                         * Section Full Threshold */
03262         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03263     } B;
03264 } hw_enet_rsfl_t;
03265 
03266 /*!
03267  * @name Constants and macros for entire ENET_RSFL register
03268  */
03269 /*@{*/
03270 #define HW_ENET_RSFL_ADDR(x)     ((x) + 0x190U)
03271 
03272 #define HW_ENET_RSFL(x)          (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
03273 #define HW_ENET_RSFL_RD(x)       (HW_ENET_RSFL(x).U)
03274 #define HW_ENET_RSFL_WR(x, v)    (HW_ENET_RSFL(x).U = (v))
03275 #define HW_ENET_RSFL_SET(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) |  (v)))
03276 #define HW_ENET_RSFL_CLR(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
03277 #define HW_ENET_RSFL_TOG(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^  (v)))
03278 /*@}*/
03279 
03280 /*
03281  * Constants & macros for individual ENET_RSFL bitfields
03282  */
03283 
03284 /*!
03285  * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
03286  *
03287  * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
03288  * this field to enable store and forward on the RX FIFO. When programming a value
03289  * greater than 0 (cut-through operation), it must be greater than
03290  * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
03291  * in the Receive FIFO (cut-through operation).
03292  */
03293 /*@{*/
03294 #define BP_ENET_RSFL_RX_SECTION_FULL (0U)  /*!< Bit position for ENET_RSFL_RX_SECTION_FULL. */
03295 #define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) /*!< Bit mask for ENET_RSFL_RX_SECTION_FULL. */
03296 #define BS_ENET_RSFL_RX_SECTION_FULL (8U)  /*!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL. */
03297 
03298 /*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
03299 #define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
03300 
03301 /*! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL. */
03302 #define BF_ENET_RSFL_RX_SECTION_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSFL_RX_SECTION_FULL) & BM_ENET_RSFL_RX_SECTION_FULL)
03303 
03304 /*! @brief Set the RX_SECTION_FULL field to a new value. */
03305 #define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
03306 /*@}*/
03307 
03308 /*******************************************************************************
03309  * HW_ENET_RSEM - Receive FIFO Section Empty Threshold
03310  ******************************************************************************/
03311 
03312 /*!
03313  * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
03314  *
03315  * Reset value: 0x00000000U
03316  */
03317 typedef union _hw_enet_rsem
03318 {
03319     uint32_t U;
03320     struct _hw_enet_rsem_bitfields
03321     {
03322         uint32_t RX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
03323                                         * Section Empty Threshold */
03324         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
03325         uint32_t STAT_SECTION_EMPTY : 5; /*!< [20:16] RX Status FIFO Section
03326                                         * Empty Threshold */
03327         uint32_t RESERVED1 : 11;       /*!< [31:21]  */
03328     } B;
03329 } hw_enet_rsem_t;
03330 
03331 /*!
03332  * @name Constants and macros for entire ENET_RSEM register
03333  */
03334 /*@{*/
03335 #define HW_ENET_RSEM_ADDR(x)     ((x) + 0x194U)
03336 
03337 #define HW_ENET_RSEM(x)          (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
03338 #define HW_ENET_RSEM_RD(x)       (HW_ENET_RSEM(x).U)
03339 #define HW_ENET_RSEM_WR(x, v)    (HW_ENET_RSEM(x).U = (v))
03340 #define HW_ENET_RSEM_SET(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) |  (v)))
03341 #define HW_ENET_RSEM_CLR(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
03342 #define HW_ENET_RSEM_TOG(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^  (v)))
03343 /*@}*/
03344 
03345 /*
03346  * Constants & macros for individual ENET_RSEM bitfields
03347  */
03348 
03349 /*!
03350  * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
03351  *
03352  * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
03353  * FIFO has reached this level, a pause frame will be issued. A value of 0
03354  * disables automatic pause frame generation. When the FIFO level goes below the value
03355  * programmed in this field, an XON pause frame is issued to indicate the FIFO
03356  * congestion is cleared to the remote Ethernet client. The section-empty
03357  * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
03358  */
03359 /*@{*/
03360 #define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) /*!< Bit position for ENET_RSEM_RX_SECTION_EMPTY. */
03361 #define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY. */
03362 #define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY. */
03363 
03364 /*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
03365 #define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
03366 
03367 /*! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY. */
03368 #define BF_ENET_RSEM_RX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_RX_SECTION_EMPTY) & BM_ENET_RSEM_RX_SECTION_EMPTY)
03369 
03370 /*! @brief Set the RX_SECTION_EMPTY field to a new value. */
03371 #define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
03372 /*@}*/
03373 
03374 /*!
03375  * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
03376  *
03377  * Defines number of frames in the receive FIFO, independent of its size, that
03378  * can be accepted. If the limit is reached, reception will continue normally,
03379  * however a pause frame will be triggered to indicate a possible congestion to the
03380  * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
03381  * frame generation
03382  */
03383 /*@{*/
03384 #define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) /*!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY. */
03385 #define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) /*!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY. */
03386 #define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) /*!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY. */
03387 
03388 /*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
03389 #define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
03390 
03391 /*! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY. */
03392 #define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_STAT_SECTION_EMPTY) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
03393 
03394 /*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
03395 #define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
03396 /*@}*/
03397 
03398 /*******************************************************************************
03399  * HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
03400  ******************************************************************************/
03401 
03402 /*!
03403  * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
03404  *
03405  * Reset value: 0x00000004U
03406  */
03407 typedef union _hw_enet_raem
03408 {
03409     uint32_t U;
03410     struct _hw_enet_raem_bitfields
03411     {
03412         uint32_t RX_ALMOST_EMPTY : 8;  /*!< [7:0] Value Of The Receive FIFO
03413                                         * Almost Empty Threshold */
03414         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03415     } B;
03416 } hw_enet_raem_t;
03417 
03418 /*!
03419  * @name Constants and macros for entire ENET_RAEM register
03420  */
03421 /*@{*/
03422 #define HW_ENET_RAEM_ADDR(x)     ((x) + 0x198U)
03423 
03424 #define HW_ENET_RAEM(x)          (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
03425 #define HW_ENET_RAEM_RD(x)       (HW_ENET_RAEM(x).U)
03426 #define HW_ENET_RAEM_WR(x, v)    (HW_ENET_RAEM(x).U = (v))
03427 #define HW_ENET_RAEM_SET(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) |  (v)))
03428 #define HW_ENET_RAEM_CLR(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
03429 #define HW_ENET_RAEM_TOG(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^  (v)))
03430 /*@}*/
03431 
03432 /*
03433  * Constants & macros for individual ENET_RAEM bitfields
03434  */
03435 
03436 /*!
03437  * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
03438  *
03439  * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
03440  * FIFO level reaches the value programmed in this field and the end-of-frame has
03441  * not been received for the frame yet, the core receive read control stops FIFO
03442  * read (and subsequently stops transferring data to the MAC client
03443  * application). It continues to deliver the frame, if again more data than the threshold or
03444  * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
03445  */
03446 /*@{*/
03447 #define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U)  /*!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY. */
03448 #define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY. */
03449 #define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U)  /*!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY. */
03450 
03451 /*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
03452 #define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
03453 
03454 /*! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY. */
03455 #define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAEM_RX_ALMOST_EMPTY) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
03456 
03457 /*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
03458 #define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
03459 /*@}*/
03460 
03461 /*******************************************************************************
03462  * HW_ENET_RAFL - Receive FIFO Almost Full Threshold
03463  ******************************************************************************/
03464 
03465 /*!
03466  * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
03467  *
03468  * Reset value: 0x00000004U
03469  */
03470 typedef union _hw_enet_rafl
03471 {
03472     uint32_t U;
03473     struct _hw_enet_rafl_bitfields
03474     {
03475         uint32_t RX_ALMOST_FULL : 8;   /*!< [7:0] Value Of The Receive FIFO
03476                                         * Almost Full Threshold */
03477         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03478     } B;
03479 } hw_enet_rafl_t;
03480 
03481 /*!
03482  * @name Constants and macros for entire ENET_RAFL register
03483  */
03484 /*@{*/
03485 #define HW_ENET_RAFL_ADDR(x)     ((x) + 0x19CU)
03486 
03487 #define HW_ENET_RAFL(x)          (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
03488 #define HW_ENET_RAFL_RD(x)       (HW_ENET_RAFL(x).U)
03489 #define HW_ENET_RAFL_WR(x, v)    (HW_ENET_RAFL(x).U = (v))
03490 #define HW_ENET_RAFL_SET(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) |  (v)))
03491 #define HW_ENET_RAFL_CLR(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
03492 #define HW_ENET_RAFL_TOG(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^  (v)))
03493 /*@}*/
03494 
03495 /*
03496  * Constants & macros for individual ENET_RAFL bitfields
03497  */
03498 
03499 /*!
03500  * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
03501  *
03502  * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
03503  * FIFO level comes close to the maximum, so that there is no more space for at
03504  * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
03505  * truncates the received frame to avoid FIFO overflow. The corresponding error
03506  * status will be set when the frame is delivered to the application. A minimum
03507  * value of 4 should be set.
03508  */
03509 /*@{*/
03510 #define BP_ENET_RAFL_RX_ALMOST_FULL (0U)   /*!< Bit position for ENET_RAFL_RX_ALMOST_FULL. */
03511 #define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_RAFL_RX_ALMOST_FULL. */
03512 #define BS_ENET_RAFL_RX_ALMOST_FULL (8U)   /*!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL. */
03513 
03514 /*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
03515 #define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
03516 
03517 /*! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL. */
03518 #define BF_ENET_RAFL_RX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAFL_RX_ALMOST_FULL) & BM_ENET_RAFL_RX_ALMOST_FULL)
03519 
03520 /*! @brief Set the RX_ALMOST_FULL field to a new value. */
03521 #define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
03522 /*@}*/
03523 
03524 /*******************************************************************************
03525  * HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
03526  ******************************************************************************/
03527 
03528 /*!
03529  * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
03530  *
03531  * Reset value: 0x00000000U
03532  */
03533 typedef union _hw_enet_tsem
03534 {
03535     uint32_t U;
03536     struct _hw_enet_tsem_bitfields
03537     {
03538         uint32_t TX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Transmit FIFO
03539                                         * Section Empty Threshold */
03540         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03541     } B;
03542 } hw_enet_tsem_t;
03543 
03544 /*!
03545  * @name Constants and macros for entire ENET_TSEM register
03546  */
03547 /*@{*/
03548 #define HW_ENET_TSEM_ADDR(x)     ((x) + 0x1A0U)
03549 
03550 #define HW_ENET_TSEM(x)          (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
03551 #define HW_ENET_TSEM_RD(x)       (HW_ENET_TSEM(x).U)
03552 #define HW_ENET_TSEM_WR(x, v)    (HW_ENET_TSEM(x).U = (v))
03553 #define HW_ENET_TSEM_SET(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) |  (v)))
03554 #define HW_ENET_TSEM_CLR(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
03555 #define HW_ENET_TSEM_TOG(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^  (v)))
03556 /*@}*/
03557 
03558 /*
03559  * Constants & macros for individual ENET_TSEM bitfields
03560  */
03561 
03562 /*!
03563  * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
03564  *
03565  * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
03566  * Transmit FIFOFour programmable thresholds are available which control the core
03567  * operation. for more information.
03568  */
03569 /*@{*/
03570 #define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) /*!< Bit position for ENET_TSEM_TX_SECTION_EMPTY. */
03571 #define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY. */
03572 #define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY. */
03573 
03574 /*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
03575 #define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
03576 
03577 /*! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY. */
03578 #define BF_ENET_TSEM_TX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TSEM_TX_SECTION_EMPTY) & BM_ENET_TSEM_TX_SECTION_EMPTY)
03579 
03580 /*! @brief Set the TX_SECTION_EMPTY field to a new value. */
03581 #define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
03582 /*@}*/
03583 
03584 /*******************************************************************************
03585  * HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
03586  ******************************************************************************/
03587 
03588 /*!
03589  * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
03590  *
03591  * Reset value: 0x00000004U
03592  */
03593 typedef union _hw_enet_taem
03594 {
03595     uint32_t U;
03596     struct _hw_enet_taem_bitfields
03597     {
03598         uint32_t TX_ALMOST_EMPTY : 8;  /*!< [7:0] Value of Transmit FIFO
03599                                         * Almost Empty Threshold */
03600         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03601     } B;
03602 } hw_enet_taem_t;
03603 
03604 /*!
03605  * @name Constants and macros for entire ENET_TAEM register
03606  */
03607 /*@{*/
03608 #define HW_ENET_TAEM_ADDR(x)     ((x) + 0x1A4U)
03609 
03610 #define HW_ENET_TAEM(x)          (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
03611 #define HW_ENET_TAEM_RD(x)       (HW_ENET_TAEM(x).U)
03612 #define HW_ENET_TAEM_WR(x, v)    (HW_ENET_TAEM(x).U = (v))
03613 #define HW_ENET_TAEM_SET(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) |  (v)))
03614 #define HW_ENET_TAEM_CLR(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
03615 #define HW_ENET_TAEM_TOG(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^  (v)))
03616 /*@}*/
03617 
03618 /*
03619  * Constants & macros for individual ENET_TAEM bitfields
03620  */
03621 
03622 /*!
03623  * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
03624  *
03625  * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
03626  * FIFO level reaches the value programmed in this field, and no end-of-frame is
03627  * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
03628  * stops reading the FIFO and transmits a frame with an MII error indication. See
03629  * Transmit FIFOFour programmable thresholds are available which control the core
03630  * operation. for more information. A minimum value of 4 should be set.
03631  */
03632 /*@{*/
03633 #define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U)  /*!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY. */
03634 #define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY. */
03635 #define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U)  /*!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY. */
03636 
03637 /*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
03638 #define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
03639 
03640 /*! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY. */
03641 #define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAEM_TX_ALMOST_EMPTY) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
03642 
03643 /*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
03644 #define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
03645 /*@}*/
03646 
03647 /*******************************************************************************
03648  * HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
03649  ******************************************************************************/
03650 
03651 /*!
03652  * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
03653  *
03654  * Reset value: 0x00000008U
03655  */
03656 typedef union _hw_enet_tafl
03657 {
03658     uint32_t U;
03659     struct _hw_enet_tafl_bitfields
03660     {
03661         uint32_t TX_ALMOST_FULL : 8;   /*!< [7:0] Value Of The Transmit FIFO
03662                                         * Almost Full Threshold */
03663         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03664     } B;
03665 } hw_enet_tafl_t;
03666 
03667 /*!
03668  * @name Constants and macros for entire ENET_TAFL register
03669  */
03670 /*@{*/
03671 #define HW_ENET_TAFL_ADDR(x)     ((x) + 0x1A8U)
03672 
03673 #define HW_ENET_TAFL(x)          (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
03674 #define HW_ENET_TAFL_RD(x)       (HW_ENET_TAFL(x).U)
03675 #define HW_ENET_TAFL_WR(x, v)    (HW_ENET_TAFL(x).U = (v))
03676 #define HW_ENET_TAFL_SET(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) |  (v)))
03677 #define HW_ENET_TAFL_CLR(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
03678 #define HW_ENET_TAFL_TOG(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^  (v)))
03679 /*@}*/
03680 
03681 /*
03682  * Constants & macros for individual ENET_TAFL bitfields
03683  */
03684 
03685 /*!
03686  * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
03687  *
03688  * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
03689  * value of six is required . A recommended value of at least 8 should be set
03690  * allowing a latency of two clock cycles to the application. If more latency is
03691  * required the value can be increased as necessary (latency = TAFL - 5). When the
03692  * FIFO level comes close to the maximum, so that there is no more space for at
03693  * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
03694  * application does not react on this signal, the FIFO write control logic, to
03695  * avoid FIFO overflow, truncates the current frame and sets the error status. As a
03696  * result, the frame will be transmitted with an GMII/MII error indication. See
03697  * Transmit FIFOFour programmable thresholds are available which control the core
03698  * operation. for more information. A FIFO overflow is a fatal error and requires
03699  * a global reset on the transmit datapath or at least deassertion of ETHEREN.
03700  */
03701 /*@{*/
03702 #define BP_ENET_TAFL_TX_ALMOST_FULL (0U)   /*!< Bit position for ENET_TAFL_TX_ALMOST_FULL. */
03703 #define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_TAFL_TX_ALMOST_FULL. */
03704 #define BS_ENET_TAFL_TX_ALMOST_FULL (8U)   /*!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL. */
03705 
03706 /*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
03707 #define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
03708 
03709 /*! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL. */
03710 #define BF_ENET_TAFL_TX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAFL_TX_ALMOST_FULL) & BM_ENET_TAFL_TX_ALMOST_FULL)
03711 
03712 /*! @brief Set the TX_ALMOST_FULL field to a new value. */
03713 #define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
03714 /*@}*/
03715 
03716 /*******************************************************************************
03717  * HW_ENET_TIPG - Transmit Inter-Packet Gap
03718  ******************************************************************************/
03719 
03720 /*!
03721  * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
03722  *
03723  * Reset value: 0x0000000CU
03724  */
03725 typedef union _hw_enet_tipg
03726 {
03727     uint32_t U;
03728     struct _hw_enet_tipg_bitfields
03729     {
03730         uint32_t IPG : 5;              /*!< [4:0] Transmit Inter-Packet Gap */
03731         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
03732     } B;
03733 } hw_enet_tipg_t;
03734 
03735 /*!
03736  * @name Constants and macros for entire ENET_TIPG register
03737  */
03738 /*@{*/
03739 #define HW_ENET_TIPG_ADDR(x)     ((x) + 0x1ACU)
03740 
03741 #define HW_ENET_TIPG(x)          (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
03742 #define HW_ENET_TIPG_RD(x)       (HW_ENET_TIPG(x).U)
03743 #define HW_ENET_TIPG_WR(x, v)    (HW_ENET_TIPG(x).U = (v))
03744 #define HW_ENET_TIPG_SET(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) |  (v)))
03745 #define HW_ENET_TIPG_CLR(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
03746 #define HW_ENET_TIPG_TOG(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^  (v)))
03747 /*@}*/
03748 
03749 /*
03750  * Constants & macros for individual ENET_TIPG bitfields
03751  */
03752 
03753 /*!
03754  * @name Register ENET_TIPG, field IPG[4:0] (RW)
03755  *
03756  * Indicates the IPG, in bytes, between transmitted frames. Valid values range
03757  * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
03758  * 27, the IPG is 27.
03759  */
03760 /*@{*/
03761 #define BP_ENET_TIPG_IPG     (0U)          /*!< Bit position for ENET_TIPG_IPG. */
03762 #define BM_ENET_TIPG_IPG     (0x0000001FU) /*!< Bit mask for ENET_TIPG_IPG. */
03763 #define BS_ENET_TIPG_IPG     (5U)          /*!< Bit field size in bits for ENET_TIPG_IPG. */
03764 
03765 /*! @brief Read current value of the ENET_TIPG_IPG field. */
03766 #define BR_ENET_TIPG_IPG(x)  (HW_ENET_TIPG(x).B.IPG)
03767 
03768 /*! @brief Format value for bitfield ENET_TIPG_IPG. */
03769 #define BF_ENET_TIPG_IPG(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG)
03770 
03771 /*! @brief Set the IPG field to a new value. */
03772 #define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
03773 /*@}*/
03774 
03775 /*******************************************************************************
03776  * HW_ENET_FTRL - Frame Truncation Length
03777  ******************************************************************************/
03778 
03779 /*!
03780  * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
03781  *
03782  * Reset value: 0x000007FFU
03783  */
03784 typedef union _hw_enet_ftrl
03785 {
03786     uint32_t U;
03787     struct _hw_enet_ftrl_bitfields
03788     {
03789         uint32_t TRUNC_FL : 14;        /*!< [13:0] Frame Truncation Length */
03790         uint32_t RESERVED0 : 18;       /*!< [31:14]  */
03791     } B;
03792 } hw_enet_ftrl_t;
03793 
03794 /*!
03795  * @name Constants and macros for entire ENET_FTRL register
03796  */
03797 /*@{*/
03798 #define HW_ENET_FTRL_ADDR(x)     ((x) + 0x1B0U)
03799 
03800 #define HW_ENET_FTRL(x)          (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
03801 #define HW_ENET_FTRL_RD(x)       (HW_ENET_FTRL(x).U)
03802 #define HW_ENET_FTRL_WR(x, v)    (HW_ENET_FTRL(x).U = (v))
03803 #define HW_ENET_FTRL_SET(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) |  (v)))
03804 #define HW_ENET_FTRL_CLR(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
03805 #define HW_ENET_FTRL_TOG(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^  (v)))
03806 /*@}*/
03807 
03808 /*
03809  * Constants & macros for individual ENET_FTRL bitfields
03810  */
03811 
03812 /*!
03813  * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
03814  *
03815  * Indicates the value a receive frame is truncated, if it is greater than this
03816  * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
03817  * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
03818  * less data, guaranteeing that it never receives more than the set limit.
03819  */
03820 /*@{*/
03821 #define BP_ENET_FTRL_TRUNC_FL (0U)         /*!< Bit position for ENET_FTRL_TRUNC_FL. */
03822 #define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) /*!< Bit mask for ENET_FTRL_TRUNC_FL. */
03823 #define BS_ENET_FTRL_TRUNC_FL (14U)        /*!< Bit field size in bits for ENET_FTRL_TRUNC_FL. */
03824 
03825 /*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
03826 #define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
03827 
03828 /*! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. */
03829 #define BF_ENET_FTRL_TRUNC_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL)
03830 
03831 /*! @brief Set the TRUNC_FL field to a new value. */
03832 #define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
03833 /*@}*/
03834 
03835 /*******************************************************************************
03836  * HW_ENET_TACC - Transmit Accelerator Function Configuration
03837  ******************************************************************************/
03838 
03839 /*!
03840  * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
03841  *
03842  * Reset value: 0x00000000U
03843  *
03844  * TACC controls accelerator actions when sending frames. The register can be
03845  * changed before or after each frame, but it must remain unmodified during frame
03846  * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
03847  * checksum feature.
03848  */
03849 typedef union _hw_enet_tacc
03850 {
03851     uint32_t U;
03852     struct _hw_enet_tacc_bitfields
03853     {
03854         uint32_t SHIFT16 : 1;          /*!< [0] TX FIFO Shift-16 */
03855         uint32_t RESERVED0 : 2;        /*!< [2:1]  */
03856         uint32_t IPCHK : 1;            /*!< [3]  */
03857         uint32_t PROCHK : 1;           /*!< [4]  */
03858         uint32_t RESERVED1 : 27;       /*!< [31:5]  */
03859     } B;
03860 } hw_enet_tacc_t;
03861 
03862 /*!
03863  * @name Constants and macros for entire ENET_TACC register
03864  */
03865 /*@{*/
03866 #define HW_ENET_TACC_ADDR(x)     ((x) + 0x1C0U)
03867 
03868 #define HW_ENET_TACC(x)          (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
03869 #define HW_ENET_TACC_RD(x)       (HW_ENET_TACC(x).U)
03870 #define HW_ENET_TACC_WR(x, v)    (HW_ENET_TACC(x).U = (v))
03871 #define HW_ENET_TACC_SET(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) |  (v)))
03872 #define HW_ENET_TACC_CLR(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
03873 #define HW_ENET_TACC_TOG(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^  (v)))
03874 /*@}*/
03875 
03876 /*
03877  * Constants & macros for individual ENET_TACC bitfields
03878  */
03879 
03880 /*!
03881  * @name Register ENET_TACC, field SHIFT16[0] (RW)
03882  *
03883  * Values:
03884  * - 0 - Disabled.
03885  * - 1 - Indicates to the transmit data FIFO that the written frames contain two
03886  *     additional octets before the frame data. This means the actual frame
03887  *     begins at bit 16 of the first word written into the FIFO. This function allows
03888  *     putting the frame payload on a 32-bit boundary in memory, as the 14-byte
03889  *     Ethernet header is extended to a 16-byte header.
03890  */
03891 /*@{*/
03892 #define BP_ENET_TACC_SHIFT16 (0U)          /*!< Bit position for ENET_TACC_SHIFT16. */
03893 #define BM_ENET_TACC_SHIFT16 (0x00000001U) /*!< Bit mask for ENET_TACC_SHIFT16. */
03894 #define BS_ENET_TACC_SHIFT16 (1U)          /*!< Bit field size in bits for ENET_TACC_SHIFT16. */
03895 
03896 /*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
03897 #define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
03898 
03899 /*! @brief Format value for bitfield ENET_TACC_SHIFT16. */
03900 #define BF_ENET_TACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16)
03901 
03902 /*! @brief Set the SHIFT16 field to a new value. */
03903 #define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
03904 /*@}*/
03905 
03906 /*!
03907  * @name Register ENET_TACC, field IPCHK[3] (RW)
03908  *
03909  * Enables insertion of IP header checksum.
03910  *
03911  * Values:
03912  * - 0 - Checksum is not inserted.
03913  * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
03914  *     The IP header checksum field must be cleared. If a non-IP frame is
03915  *     transmitted the frame is not modified.
03916  */
03917 /*@{*/
03918 #define BP_ENET_TACC_IPCHK   (3U)          /*!< Bit position for ENET_TACC_IPCHK. */
03919 #define BM_ENET_TACC_IPCHK   (0x00000008U) /*!< Bit mask for ENET_TACC_IPCHK. */
03920 #define BS_ENET_TACC_IPCHK   (1U)          /*!< Bit field size in bits for ENET_TACC_IPCHK. */
03921 
03922 /*! @brief Read current value of the ENET_TACC_IPCHK field. */
03923 #define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
03924 
03925 /*! @brief Format value for bitfield ENET_TACC_IPCHK. */
03926 #define BF_ENET_TACC_IPCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK)
03927 
03928 /*! @brief Set the IPCHK field to a new value. */
03929 #define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
03930 /*@}*/
03931 
03932 /*!
03933  * @name Register ENET_TACC, field PROCHK[4] (RW)
03934  *
03935  * Enables insertion of protocol checksum.
03936  *
03937  * Values:
03938  * - 0 - Checksum not inserted.
03939  * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
03940  *     inserted automatically into the frame. The checksum field must be cleared.
03941  *     The other frames are not modified.
03942  */
03943 /*@{*/
03944 #define BP_ENET_TACC_PROCHK  (4U)          /*!< Bit position for ENET_TACC_PROCHK. */
03945 #define BM_ENET_TACC_PROCHK  (0x00000010U) /*!< Bit mask for ENET_TACC_PROCHK. */
03946 #define BS_ENET_TACC_PROCHK  (1U)          /*!< Bit field size in bits for ENET_TACC_PROCHK. */
03947 
03948 /*! @brief Read current value of the ENET_TACC_PROCHK field. */
03949 #define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
03950 
03951 /*! @brief Format value for bitfield ENET_TACC_PROCHK. */
03952 #define BF_ENET_TACC_PROCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK)
03953 
03954 /*! @brief Set the PROCHK field to a new value. */
03955 #define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
03956 /*@}*/
03957 
03958 /*******************************************************************************
03959  * HW_ENET_RACC - Receive Accelerator Function Configuration
03960  ******************************************************************************/
03961 
03962 /*!
03963  * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
03964  *
03965  * Reset value: 0x00000000U
03966  */
03967 typedef union _hw_enet_racc
03968 {
03969     uint32_t U;
03970     struct _hw_enet_racc_bitfields
03971     {
03972         uint32_t PADREM : 1;           /*!< [0] Enable Padding Removal For Short IP
03973                                         * Frames */
03974         uint32_t IPDIS : 1;            /*!< [1] Enable Discard Of Frames With Wrong IPv4
03975                                         * Header Checksum */
03976         uint32_t PRODIS : 1;           /*!< [2] Enable Discard Of Frames With Wrong
03977                                         * Protocol Checksum */
03978         uint32_t RESERVED0 : 3;        /*!< [5:3]  */
03979         uint32_t LINEDIS : 1;          /*!< [6] Enable Discard Of Frames With MAC
03980                                         * Layer Errors */
03981         uint32_t SHIFT16 : 1;          /*!< [7] RX FIFO Shift-16 */
03982         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
03983     } B;
03984 } hw_enet_racc_t;
03985 
03986 /*!
03987  * @name Constants and macros for entire ENET_RACC register
03988  */
03989 /*@{*/
03990 #define HW_ENET_RACC_ADDR(x)     ((x) + 0x1C4U)
03991 
03992 #define HW_ENET_RACC(x)          (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
03993 #define HW_ENET_RACC_RD(x)       (HW_ENET_RACC(x).U)
03994 #define HW_ENET_RACC_WR(x, v)    (HW_ENET_RACC(x).U = (v))
03995 #define HW_ENET_RACC_SET(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) |  (v)))
03996 #define HW_ENET_RACC_CLR(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
03997 #define HW_ENET_RACC_TOG(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^  (v)))
03998 /*@}*/
03999 
04000 /*
04001  * Constants & macros for individual ENET_RACC bitfields
04002  */
04003 
04004 /*!
04005  * @name Register ENET_RACC, field PADREM[0] (RW)
04006  *
04007  * Values:
04008  * - 0 - Padding not removed.
04009  * - 1 - Any bytes following the IP payload section of the frame are removed
04010  *     from the frame.
04011  */
04012 /*@{*/
04013 #define BP_ENET_RACC_PADREM  (0U)          /*!< Bit position for ENET_RACC_PADREM. */
04014 #define BM_ENET_RACC_PADREM  (0x00000001U) /*!< Bit mask for ENET_RACC_PADREM. */
04015 #define BS_ENET_RACC_PADREM  (1U)          /*!< Bit field size in bits for ENET_RACC_PADREM. */
04016 
04017 /*! @brief Read current value of the ENET_RACC_PADREM field. */
04018 #define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
04019 
04020 /*! @brief Format value for bitfield ENET_RACC_PADREM. */
04021 #define BF_ENET_RACC_PADREM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM)
04022 
04023 /*! @brief Set the PADREM field to a new value. */
04024 #define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
04025 /*@}*/
04026 
04027 /*!
04028  * @name Register ENET_RACC, field IPDIS[1] (RW)
04029  *
04030  * Values:
04031  * - 0 - Frames with wrong IPv4 header checksum are not discarded.
04032  * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
04033  *     frame is discarded. IPv6 has no header checksum and is not affected by this
04034  *     setting. Discarding is only available when the RX FIFO operates in store
04035  *     and forward mode (RSFL cleared).
04036  */
04037 /*@{*/
04038 #define BP_ENET_RACC_IPDIS   (1U)          /*!< Bit position for ENET_RACC_IPDIS. */
04039 #define BM_ENET_RACC_IPDIS   (0x00000002U) /*!< Bit mask for ENET_RACC_IPDIS. */
04040 #define BS_ENET_RACC_IPDIS   (1U)          /*!< Bit field size in bits for ENET_RACC_IPDIS. */
04041 
04042 /*! @brief Read current value of the ENET_RACC_IPDIS field. */
04043 #define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
04044 
04045 /*! @brief Format value for bitfield ENET_RACC_IPDIS. */
04046 #define BF_ENET_RACC_IPDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS)
04047 
04048 /*! @brief Set the IPDIS field to a new value. */
04049 #define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
04050 /*@}*/
04051 
04052 /*!
04053  * @name Register ENET_RACC, field PRODIS[2] (RW)
04054  *
04055  * Values:
04056  * - 0 - Frames with wrong checksum are not discarded.
04057  * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
04058  *     UDP, or ICMP checksum, the frame is discarded. Discarding is only
04059  *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
04060  */
04061 /*@{*/
04062 #define BP_ENET_RACC_PRODIS  (2U)          /*!< Bit position for ENET_RACC_PRODIS. */
04063 #define BM_ENET_RACC_PRODIS  (0x00000004U) /*!< Bit mask for ENET_RACC_PRODIS. */
04064 #define BS_ENET_RACC_PRODIS  (1U)          /*!< Bit field size in bits for ENET_RACC_PRODIS. */
04065 
04066 /*! @brief Read current value of the ENET_RACC_PRODIS field. */
04067 #define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
04068 
04069 /*! @brief Format value for bitfield ENET_RACC_PRODIS. */
04070 #define BF_ENET_RACC_PRODIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS)
04071 
04072 /*! @brief Set the PRODIS field to a new value. */
04073 #define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
04074 /*@}*/
04075 
04076 /*!
04077  * @name Register ENET_RACC, field LINEDIS[6] (RW)
04078  *
04079  * Values:
04080  * - 0 - Frames with errors are not discarded.
04081  * - 1 - Any frame received with a CRC, length, or PHY error is automatically
04082  *     discarded and not forwarded to the user application interface.
04083  */
04084 /*@{*/
04085 #define BP_ENET_RACC_LINEDIS (6U)          /*!< Bit position for ENET_RACC_LINEDIS. */
04086 #define BM_ENET_RACC_LINEDIS (0x00000040U) /*!< Bit mask for ENET_RACC_LINEDIS. */
04087 #define BS_ENET_RACC_LINEDIS (1U)          /*!< Bit field size in bits for ENET_RACC_LINEDIS. */
04088 
04089 /*! @brief Read current value of the ENET_RACC_LINEDIS field. */
04090 #define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
04091 
04092 /*! @brief Format value for bitfield ENET_RACC_LINEDIS. */
04093 #define BF_ENET_RACC_LINEDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS)
04094 
04095 /*! @brief Set the LINEDIS field to a new value. */
04096 #define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
04097 /*@}*/
04098 
04099 /*!
04100  * @name Register ENET_RACC, field SHIFT16[7] (RW)
04101  *
04102  * When this field is set, the actual frame data starts at bit 16 of the first
04103  * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
04104  * This function only affects the FIFO storage and has no influence on the
04105  * statistics, which use the actual length of the frame received.
04106  *
04107  * Values:
04108  * - 0 - Disabled.
04109  * - 1 - Instructs the MAC to write two additional bytes in front of each frame
04110  *     received into the RX FIFO.
04111  */
04112 /*@{*/
04113 #define BP_ENET_RACC_SHIFT16 (7U)          /*!< Bit position for ENET_RACC_SHIFT16. */
04114 #define BM_ENET_RACC_SHIFT16 (0x00000080U) /*!< Bit mask for ENET_RACC_SHIFT16. */
04115 #define BS_ENET_RACC_SHIFT16 (1U)          /*!< Bit field size in bits for ENET_RACC_SHIFT16. */
04116 
04117 /*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
04118 #define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
04119 
04120 /*! @brief Format value for bitfield ENET_RACC_SHIFT16. */
04121 #define BF_ENET_RACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16)
04122 
04123 /*! @brief Set the SHIFT16 field to a new value. */
04124 #define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
04125 /*@}*/
04126 
04127 /*******************************************************************************
04128  * HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
04129  ******************************************************************************/
04130 
04131 /*!
04132  * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
04133  *
04134  * Reset value: 0x00000000U
04135  */
04136 typedef union _hw_enet_rmon_t_packets
04137 {
04138     uint32_t U;
04139     struct _hw_enet_rmon_t_packets_bitfields
04140     {
04141         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04142         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04143     } B;
04144 } hw_enet_rmon_t_packets_t;
04145 
04146 /*!
04147  * @name Constants and macros for entire ENET_RMON_T_PACKETS register
04148  */
04149 /*@{*/
04150 #define HW_ENET_RMON_T_PACKETS_ADDR(x) ((x) + 0x204U)
04151 
04152 #define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
04153 #define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
04154 /*@}*/
04155 
04156 /*
04157  * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
04158  */
04159 
04160 /*!
04161  * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
04162  */
04163 /*@{*/
04164 #define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_PACKETS_TXPKTS. */
04165 #define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS. */
04166 #define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS. */
04167 
04168 /*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
04169 #define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
04170 /*@}*/
04171 
04172 /*******************************************************************************
04173  * HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
04174  ******************************************************************************/
04175 
04176 /*!
04177  * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
04178  *
04179  * Reset value: 0x00000000U
04180  *
04181  * RMON Tx Broadcast Packets
04182  */
04183 typedef union _hw_enet_rmon_t_bc_pkt
04184 {
04185     uint32_t U;
04186     struct _hw_enet_rmon_t_bc_pkt_bitfields
04187     {
04188         uint32_t TXPKTS : 16;          /*!< [15:0] Broadcast packets */
04189         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04190     } B;
04191 } hw_enet_rmon_t_bc_pkt_t;
04192 
04193 /*!
04194  * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
04195  */
04196 /*@{*/
04197 #define HW_ENET_RMON_T_BC_PKT_ADDR(x) ((x) + 0x208U)
04198 
04199 #define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
04200 #define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
04201 /*@}*/
04202 
04203 /*
04204  * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
04205  */
04206 
04207 /*!
04208  * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
04209  */
04210 /*@{*/
04211 #define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U)  /*!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS. */
04212 #define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS. */
04213 #define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS. */
04214 
04215 /*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
04216 #define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
04217 /*@}*/
04218 
04219 /*******************************************************************************
04220  * HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
04221  ******************************************************************************/
04222 
04223 /*!
04224  * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
04225  *
04226  * Reset value: 0x00000000U
04227  */
04228 typedef union _hw_enet_rmon_t_mc_pkt
04229 {
04230     uint32_t U;
04231     struct _hw_enet_rmon_t_mc_pkt_bitfields
04232     {
04233         uint32_t TXPKTS : 16;          /*!< [15:0] Multicast packets */
04234         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04235     } B;
04236 } hw_enet_rmon_t_mc_pkt_t;
04237 
04238 /*!
04239  * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
04240  */
04241 /*@{*/
04242 #define HW_ENET_RMON_T_MC_PKT_ADDR(x) ((x) + 0x20CU)
04243 
04244 #define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
04245 #define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
04246 /*@}*/
04247 
04248 /*
04249  * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
04250  */
04251 
04252 /*!
04253  * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
04254  */
04255 /*@{*/
04256 #define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U)  /*!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS. */
04257 #define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS. */
04258 #define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS. */
04259 
04260 /*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
04261 #define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
04262 /*@}*/
04263 
04264 /*******************************************************************************
04265  * HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
04266  ******************************************************************************/
04267 
04268 /*!
04269  * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
04270  *
04271  * Reset value: 0x00000000U
04272  */
04273 typedef union _hw_enet_rmon_t_crc_align
04274 {
04275     uint32_t U;
04276     struct _hw_enet_rmon_t_crc_align_bitfields
04277     {
04278         uint32_t TXPKTS : 16;          /*!< [15:0] Packets with CRC/align error */
04279         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04280     } B;
04281 } hw_enet_rmon_t_crc_align_t;
04282 
04283 /*!
04284  * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
04285  */
04286 /*@{*/
04287 #define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) ((x) + 0x210U)
04288 
04289 #define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
04290 #define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
04291 /*@}*/
04292 
04293 /*
04294  * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
04295  */
04296 
04297 /*!
04298  * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
04299  */
04300 /*@{*/
04301 #define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04302 #define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04303 #define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04304 
04305 /*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
04306 #define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
04307 /*@}*/
04308 
04309 /*******************************************************************************
04310  * HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
04311  ******************************************************************************/
04312 
04313 /*!
04314  * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
04315  *
04316  * Reset value: 0x00000000U
04317  */
04318 typedef union _hw_enet_rmon_t_undersize
04319 {
04320     uint32_t U;
04321     struct _hw_enet_rmon_t_undersize_bitfields
04322     {
04323         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04324         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04325     } B;
04326 } hw_enet_rmon_t_undersize_t;
04327 
04328 /*!
04329  * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
04330  */
04331 /*@{*/
04332 #define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) ((x) + 0x214U)
04333 
04334 #define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
04335 #define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
04336 /*@}*/
04337 
04338 /*
04339  * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
04340  */
04341 
04342 /*!
04343  * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
04344  */
04345 /*@{*/
04346 #define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04347 #define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04348 #define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04349 
04350 /*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
04351 #define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
04352 /*@}*/
04353 
04354 /*******************************************************************************
04355  * HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
04356  ******************************************************************************/
04357 
04358 /*!
04359  * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
04360  *
04361  * Reset value: 0x00000000U
04362  */
04363 typedef union _hw_enet_rmon_t_oversize
04364 {
04365     uint32_t U;
04366     struct _hw_enet_rmon_t_oversize_bitfields
04367     {
04368         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04369         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04370     } B;
04371 } hw_enet_rmon_t_oversize_t;
04372 
04373 /*!
04374  * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
04375  */
04376 /*@{*/
04377 #define HW_ENET_RMON_T_OVERSIZE_ADDR(x) ((x) + 0x218U)
04378 
04379 #define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
04380 #define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
04381 /*@}*/
04382 
04383 /*
04384  * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
04385  */
04386 
04387 /*!
04388  * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
04389  */
04390 /*@{*/
04391 #define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS. */
04392 #define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS. */
04393 #define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS. */
04394 
04395 /*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
04396 #define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
04397 /*@}*/
04398 
04399 /*******************************************************************************
04400  * HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
04401  ******************************************************************************/
04402 
04403 /*!
04404  * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
04405  *
04406  * Reset value: 0x00000000U
04407  *
04408  * .
04409  */
04410 typedef union _hw_enet_rmon_t_frag
04411 {
04412     uint32_t U;
04413     struct _hw_enet_rmon_t_frag_bitfields
04414     {
04415         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04416         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04417     } B;
04418 } hw_enet_rmon_t_frag_t;
04419 
04420 /*!
04421  * @name Constants and macros for entire ENET_RMON_T_FRAG register
04422  */
04423 /*@{*/
04424 #define HW_ENET_RMON_T_FRAG_ADDR(x) ((x) + 0x21CU)
04425 
04426 #define HW_ENET_RMON_T_FRAG(x)   (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
04427 #define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
04428 /*@}*/
04429 
04430 /*
04431  * Constants & macros for individual ENET_RMON_T_FRAG bitfields
04432  */
04433 
04434 /*!
04435  * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
04436  */
04437 /*@{*/
04438 #define BP_ENET_RMON_T_FRAG_TXPKTS (0U)    /*!< Bit position for ENET_RMON_T_FRAG_TXPKTS. */
04439 #define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_FRAG_TXPKTS. */
04440 #define BS_ENET_RMON_T_FRAG_TXPKTS (16U)   /*!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS. */
04441 
04442 /*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
04443 #define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
04444 /*@}*/
04445 
04446 /*******************************************************************************
04447  * HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
04448  ******************************************************************************/
04449 
04450 /*!
04451  * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
04452  *
04453  * Reset value: 0x00000000U
04454  */
04455 typedef union _hw_enet_rmon_t_jab
04456 {
04457     uint32_t U;
04458     struct _hw_enet_rmon_t_jab_bitfields
04459     {
04460         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04461         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04462     } B;
04463 } hw_enet_rmon_t_jab_t;
04464 
04465 /*!
04466  * @name Constants and macros for entire ENET_RMON_T_JAB register
04467  */
04468 /*@{*/
04469 #define HW_ENET_RMON_T_JAB_ADDR(x) ((x) + 0x220U)
04470 
04471 #define HW_ENET_RMON_T_JAB(x)    (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
04472 #define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
04473 /*@}*/
04474 
04475 /*
04476  * Constants & macros for individual ENET_RMON_T_JAB bitfields
04477  */
04478 
04479 /*!
04480  * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
04481  */
04482 /*@{*/
04483 #define BP_ENET_RMON_T_JAB_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_JAB_TXPKTS. */
04484 #define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_JAB_TXPKTS. */
04485 #define BS_ENET_RMON_T_JAB_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS. */
04486 
04487 /*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
04488 #define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
04489 /*@}*/
04490 
04491 /*******************************************************************************
04492  * HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
04493  ******************************************************************************/
04494 
04495 /*!
04496  * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
04497  *
04498  * Reset value: 0x00000000U
04499  */
04500 typedef union _hw_enet_rmon_t_col
04501 {
04502     uint32_t U;
04503     struct _hw_enet_rmon_t_col_bitfields
04504     {
04505         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04506         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04507     } B;
04508 } hw_enet_rmon_t_col_t;
04509 
04510 /*!
04511  * @name Constants and macros for entire ENET_RMON_T_COL register
04512  */
04513 /*@{*/
04514 #define HW_ENET_RMON_T_COL_ADDR(x) ((x) + 0x224U)
04515 
04516 #define HW_ENET_RMON_T_COL(x)    (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
04517 #define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
04518 /*@}*/
04519 
04520 /*
04521  * Constants & macros for individual ENET_RMON_T_COL bitfields
04522  */
04523 
04524 /*!
04525  * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
04526  */
04527 /*@{*/
04528 #define BP_ENET_RMON_T_COL_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_COL_TXPKTS. */
04529 #define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_COL_TXPKTS. */
04530 #define BS_ENET_RMON_T_COL_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS. */
04531 
04532 /*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
04533 #define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
04534 /*@}*/
04535 
04536 /*******************************************************************************
04537  * HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
04538  ******************************************************************************/
04539 
04540 /*!
04541  * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
04542  *
04543  * Reset value: 0x00000000U
04544  *
04545  * .
04546  */
04547 typedef union _hw_enet_rmon_t_p64
04548 {
04549     uint32_t U;
04550     struct _hw_enet_rmon_t_p64_bitfields
04551     {
04552         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04553         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04554     } B;
04555 } hw_enet_rmon_t_p64_t;
04556 
04557 /*!
04558  * @name Constants and macros for entire ENET_RMON_T_P64 register
04559  */
04560 /*@{*/
04561 #define HW_ENET_RMON_T_P64_ADDR(x) ((x) + 0x228U)
04562 
04563 #define HW_ENET_RMON_T_P64(x)    (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
04564 #define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
04565 /*@}*/
04566 
04567 /*
04568  * Constants & macros for individual ENET_RMON_T_P64 bitfields
04569  */
04570 
04571 /*!
04572  * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
04573  */
04574 /*@{*/
04575 #define BP_ENET_RMON_T_P64_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_P64_TXPKTS. */
04576 #define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P64_TXPKTS. */
04577 #define BS_ENET_RMON_T_P64_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS. */
04578 
04579 /*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
04580 #define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
04581 /*@}*/
04582 
04583 /*******************************************************************************
04584  * HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
04585  ******************************************************************************/
04586 
04587 /*!
04588  * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
04589  *
04590  * Reset value: 0x00000000U
04591  */
04592 typedef union _hw_enet_rmon_t_p65to127
04593 {
04594     uint32_t U;
04595     struct _hw_enet_rmon_t_p65to127_bitfields
04596     {
04597         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04598         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04599     } B;
04600 } hw_enet_rmon_t_p65to127_t;
04601 
04602 /*!
04603  * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
04604  */
04605 /*@{*/
04606 #define HW_ENET_RMON_T_P65TO127_ADDR(x) ((x) + 0x22CU)
04607 
04608 #define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
04609 #define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
04610 /*@}*/
04611 
04612 /*
04613  * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
04614  */
04615 
04616 /*!
04617  * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
04618  */
04619 /*@{*/
04620 #define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P65TO127_TXPKTS. */
04621 #define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS. */
04622 #define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS. */
04623 
04624 /*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
04625 #define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
04626 /*@}*/
04627 
04628 /*******************************************************************************
04629  * HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
04630  ******************************************************************************/
04631 
04632 /*!
04633  * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
04634  *
04635  * Reset value: 0x00000000U
04636  */
04637 typedef union _hw_enet_rmon_t_p128to255
04638 {
04639     uint32_t U;
04640     struct _hw_enet_rmon_t_p128to255_bitfields
04641     {
04642         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04643         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04644     } B;
04645 } hw_enet_rmon_t_p128to255_t;
04646 
04647 /*!
04648  * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
04649  */
04650 /*@{*/
04651 #define HW_ENET_RMON_T_P128TO255_ADDR(x) ((x) + 0x230U)
04652 
04653 #define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
04654 #define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
04655 /*@}*/
04656 
04657 /*
04658  * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
04659  */
04660 
04661 /*!
04662  * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
04663  */
04664 /*@{*/
04665 #define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P128TO255_TXPKTS. */
04666 #define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS. */
04667 #define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS. */
04668 
04669 /*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
04670 #define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
04671 /*@}*/
04672 
04673 /*******************************************************************************
04674  * HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
04675  ******************************************************************************/
04676 
04677 /*!
04678  * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
04679  *
04680  * Reset value: 0x00000000U
04681  */
04682 typedef union _hw_enet_rmon_t_p256to511
04683 {
04684     uint32_t U;
04685     struct _hw_enet_rmon_t_p256to511_bitfields
04686     {
04687         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04688         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04689     } B;
04690 } hw_enet_rmon_t_p256to511_t;
04691 
04692 /*!
04693  * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
04694  */
04695 /*@{*/
04696 #define HW_ENET_RMON_T_P256TO511_ADDR(x) ((x) + 0x234U)
04697 
04698 #define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
04699 #define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
04700 /*@}*/
04701 
04702 /*
04703  * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
04704  */
04705 
04706 /*!
04707  * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
04708  */
04709 /*@{*/
04710 #define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P256TO511_TXPKTS. */
04711 #define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS. */
04712 #define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS. */
04713 
04714 /*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
04715 #define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
04716 /*@}*/
04717 
04718 /*******************************************************************************
04719  * HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
04720  ******************************************************************************/
04721 
04722 /*!
04723  * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
04724  *
04725  * Reset value: 0x00000000U
04726  *
04727  * .
04728  */
04729 typedef union _hw_enet_rmon_t_p512to1023
04730 {
04731     uint32_t U;
04732     struct _hw_enet_rmon_t_p512to1023_bitfields
04733     {
04734         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04735         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04736     } B;
04737 } hw_enet_rmon_t_p512to1023_t;
04738 
04739 /*!
04740  * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
04741  */
04742 /*@{*/
04743 #define HW_ENET_RMON_T_P512TO1023_ADDR(x) ((x) + 0x238U)
04744 
04745 #define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
04746 #define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
04747 /*@}*/
04748 
04749 /*
04750  * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
04751  */
04752 
04753 /*!
04754  * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
04755  */
04756 /*@{*/
04757 #define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS. */
04758 #define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS. */
04759 #define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS. */
04760 
04761 /*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
04762 #define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
04763 /*@}*/
04764 
04765 /*******************************************************************************
04766  * HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
04767  ******************************************************************************/
04768 
04769 /*!
04770  * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
04771  *
04772  * Reset value: 0x00000000U
04773  */
04774 typedef union _hw_enet_rmon_t_p1024to2047
04775 {
04776     uint32_t U;
04777     struct _hw_enet_rmon_t_p1024to2047_bitfields
04778     {
04779         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04780         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04781     } B;
04782 } hw_enet_rmon_t_p1024to2047_t;
04783 
04784 /*!
04785  * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
04786  */
04787 /*@{*/
04788 #define HW_ENET_RMON_T_P1024TO2047_ADDR(x) ((x) + 0x23CU)
04789 
04790 #define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
04791 #define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
04792 /*@}*/
04793 
04794 /*
04795  * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
04796  */
04797 
04798 /*!
04799  * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
04800  */
04801 /*@{*/
04802 #define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS. */
04803 #define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS. */
04804 #define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS. */
04805 
04806 /*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
04807 #define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
04808 /*@}*/
04809 
04810 /*******************************************************************************
04811  * HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
04812  ******************************************************************************/
04813 
04814 /*!
04815  * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
04816  *
04817  * Reset value: 0x00000000U
04818  */
04819 typedef union _hw_enet_rmon_t_p_gte2048
04820 {
04821     uint32_t U;
04822     struct _hw_enet_rmon_t_p_gte2048_bitfields
04823     {
04824         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04825         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04826     } B;
04827 } hw_enet_rmon_t_p_gte2048_t;
04828 
04829 /*!
04830  * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
04831  */
04832 /*@{*/
04833 #define HW_ENET_RMON_T_P_GTE2048_ADDR(x) ((x) + 0x240U)
04834 
04835 #define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
04836 #define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
04837 /*@}*/
04838 
04839 /*
04840  * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
04841  */
04842 
04843 /*!
04844  * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
04845  */
04846 /*@{*/
04847 #define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS. */
04848 #define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS. */
04849 #define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS. */
04850 
04851 /*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
04852 #define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
04853 /*@}*/
04854 
04855 /*******************************************************************************
04856  * HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
04857  ******************************************************************************/
04858 
04859 /*!
04860  * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
04861  *
04862  * Reset value: 0x00000000U
04863  */
04864 typedef union _hw_enet_rmon_t_octets
04865 {
04866     uint32_t U;
04867     struct _hw_enet_rmon_t_octets_bitfields
04868     {
04869         uint32_t TXOCTS : 32;          /*!< [31:0] Octet count */
04870     } B;
04871 } hw_enet_rmon_t_octets_t;
04872 
04873 /*!
04874  * @name Constants and macros for entire ENET_RMON_T_OCTETS register
04875  */
04876 /*@{*/
04877 #define HW_ENET_RMON_T_OCTETS_ADDR(x) ((x) + 0x244U)
04878 
04879 #define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
04880 #define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
04881 /*@}*/
04882 
04883 /*
04884  * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
04885  */
04886 
04887 /*!
04888  * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
04889  */
04890 /*@{*/
04891 #define BP_ENET_RMON_T_OCTETS_TXOCTS (0U)  /*!< Bit position for ENET_RMON_T_OCTETS_TXOCTS. */
04892 #define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS. */
04893 #define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) /*!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS. */
04894 
04895 /*! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field. */
04896 #define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
04897 /*@}*/
04898 
04899 /*******************************************************************************
04900  * HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
04901  ******************************************************************************/
04902 
04903 /*!
04904  * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
04905  *
04906  * Reset value: 0x00000000U
04907  */
04908 typedef union _hw_enet_ieee_t_frame_ok
04909 {
04910     uint32_t U;
04911     struct _hw_enet_ieee_t_frame_ok_bitfields
04912     {
04913         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
04914         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04915     } B;
04916 } hw_enet_ieee_t_frame_ok_t;
04917 
04918 /*!
04919  * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
04920  */
04921 /*@{*/
04922 #define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) ((x) + 0x24CU)
04923 
04924 #define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
04925 #define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
04926 /*@}*/
04927 
04928 /*
04929  * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
04930  */
04931 
04932 /*!
04933  * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
04934  */
04935 /*@{*/
04936 #define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT. */
04937 #define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT. */
04938 #define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT. */
04939 
04940 /*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
04941 #define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
04942 /*@}*/
04943 
04944 /*******************************************************************************
04945  * HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
04946  ******************************************************************************/
04947 
04948 /*!
04949  * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
04950  *
04951  * Reset value: 0x00000000U
04952  */
04953 typedef union _hw_enet_ieee_t_1col
04954 {
04955     uint32_t U;
04956     struct _hw_enet_ieee_t_1col_bitfields
04957     {
04958         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
04959         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04960     } B;
04961 } hw_enet_ieee_t_1col_t;
04962 
04963 /*!
04964  * @name Constants and macros for entire ENET_IEEE_T_1COL register
04965  */
04966 /*@{*/
04967 #define HW_ENET_IEEE_T_1COL_ADDR(x) ((x) + 0x250U)
04968 
04969 #define HW_ENET_IEEE_T_1COL(x)   (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
04970 #define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
04971 /*@}*/
04972 
04973 /*
04974  * Constants & macros for individual ENET_IEEE_T_1COL bitfields
04975  */
04976 
04977 /*!
04978  * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
04979  */
04980 /*@{*/
04981 #define BP_ENET_IEEE_T_1COL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_1COL_COUNT. */
04982 #define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_1COL_COUNT. */
04983 #define BS_ENET_IEEE_T_1COL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT. */
04984 
04985 /*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
04986 #define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
04987 /*@}*/
04988 
04989 /*******************************************************************************
04990  * HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
04991  ******************************************************************************/
04992 
04993 /*!
04994  * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
04995  *
04996  * Reset value: 0x00000000U
04997  */
04998 typedef union _hw_enet_ieee_t_mcol
04999 {
05000     uint32_t U;
05001     struct _hw_enet_ieee_t_mcol_bitfields
05002     {
05003         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05004         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05005     } B;
05006 } hw_enet_ieee_t_mcol_t;
05007 
05008 /*!
05009  * @name Constants and macros for entire ENET_IEEE_T_MCOL register
05010  */
05011 /*@{*/
05012 #define HW_ENET_IEEE_T_MCOL_ADDR(x) ((x) + 0x254U)
05013 
05014 #define HW_ENET_IEEE_T_MCOL(x)   (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
05015 #define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
05016 /*@}*/
05017 
05018 /*
05019  * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
05020  */
05021 
05022 /*!
05023  * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
05024  */
05025 /*@{*/
05026 #define BP_ENET_IEEE_T_MCOL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_MCOL_COUNT. */
05027 #define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MCOL_COUNT. */
05028 #define BS_ENET_IEEE_T_MCOL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT. */
05029 
05030 /*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
05031 #define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
05032 /*@}*/
05033 
05034 /*******************************************************************************
05035  * HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
05036  ******************************************************************************/
05037 
05038 /*!
05039  * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
05040  *
05041  * Reset value: 0x00000000U
05042  */
05043 typedef union _hw_enet_ieee_t_def
05044 {
05045     uint32_t U;
05046     struct _hw_enet_ieee_t_def_bitfields
05047     {
05048         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05049         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05050     } B;
05051 } hw_enet_ieee_t_def_t;
05052 
05053 /*!
05054  * @name Constants and macros for entire ENET_IEEE_T_DEF register
05055  */
05056 /*@{*/
05057 #define HW_ENET_IEEE_T_DEF_ADDR(x) ((x) + 0x258U)
05058 
05059 #define HW_ENET_IEEE_T_DEF(x)    (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
05060 #define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
05061 /*@}*/
05062 
05063 /*
05064  * Constants & macros for individual ENET_IEEE_T_DEF bitfields
05065  */
05066 
05067 /*!
05068  * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
05069  */
05070 /*@{*/
05071 #define BP_ENET_IEEE_T_DEF_COUNT (0U)      /*!< Bit position for ENET_IEEE_T_DEF_COUNT. */
05072 #define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_DEF_COUNT. */
05073 #define BS_ENET_IEEE_T_DEF_COUNT (16U)     /*!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT. */
05074 
05075 /*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
05076 #define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
05077 /*@}*/
05078 
05079 /*******************************************************************************
05080  * HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
05081  ******************************************************************************/
05082 
05083 /*!
05084  * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
05085  *
05086  * Reset value: 0x00000000U
05087  */
05088 typedef union _hw_enet_ieee_t_lcol
05089 {
05090     uint32_t U;
05091     struct _hw_enet_ieee_t_lcol_bitfields
05092     {
05093         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05094         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05095     } B;
05096 } hw_enet_ieee_t_lcol_t;
05097 
05098 /*!
05099  * @name Constants and macros for entire ENET_IEEE_T_LCOL register
05100  */
05101 /*@{*/
05102 #define HW_ENET_IEEE_T_LCOL_ADDR(x) ((x) + 0x25CU)
05103 
05104 #define HW_ENET_IEEE_T_LCOL(x)   (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
05105 #define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
05106 /*@}*/
05107 
05108 /*
05109  * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
05110  */
05111 
05112 /*!
05113  * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
05114  */
05115 /*@{*/
05116 #define BP_ENET_IEEE_T_LCOL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_LCOL_COUNT. */
05117 #define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_LCOL_COUNT. */
05118 #define BS_ENET_IEEE_T_LCOL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT. */
05119 
05120 /*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
05121 #define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
05122 /*@}*/
05123 
05124 /*******************************************************************************
05125  * HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
05126  ******************************************************************************/
05127 
05128 /*!
05129  * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
05130  *
05131  * Reset value: 0x00000000U
05132  */
05133 typedef union _hw_enet_ieee_t_excol
05134 {
05135     uint32_t U;
05136     struct _hw_enet_ieee_t_excol_bitfields
05137     {
05138         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05139         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05140     } B;
05141 } hw_enet_ieee_t_excol_t;
05142 
05143 /*!
05144  * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
05145  */
05146 /*@{*/
05147 #define HW_ENET_IEEE_T_EXCOL_ADDR(x) ((x) + 0x260U)
05148 
05149 #define HW_ENET_IEEE_T_EXCOL(x)  (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
05150 #define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
05151 /*@}*/
05152 
05153 /*
05154  * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
05155  */
05156 
05157 /*!
05158  * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
05159  */
05160 /*@{*/
05161 #define BP_ENET_IEEE_T_EXCOL_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_EXCOL_COUNT. */
05162 #define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_EXCOL_COUNT. */
05163 #define BS_ENET_IEEE_T_EXCOL_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT. */
05164 
05165 /*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
05166 #define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
05167 /*@}*/
05168 
05169 /*******************************************************************************
05170  * HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
05171  ******************************************************************************/
05172 
05173 /*!
05174  * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
05175  *
05176  * Reset value: 0x00000000U
05177  */
05178 typedef union _hw_enet_ieee_t_macerr
05179 {
05180     uint32_t U;
05181     struct _hw_enet_ieee_t_macerr_bitfields
05182     {
05183         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05184         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05185     } B;
05186 } hw_enet_ieee_t_macerr_t;
05187 
05188 /*!
05189  * @name Constants and macros for entire ENET_IEEE_T_MACERR register
05190  */
05191 /*@{*/
05192 #define HW_ENET_IEEE_T_MACERR_ADDR(x) ((x) + 0x264U)
05193 
05194 #define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
05195 #define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
05196 /*@}*/
05197 
05198 /*
05199  * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
05200  */
05201 
05202 /*!
05203  * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
05204  */
05205 /*@{*/
05206 #define BP_ENET_IEEE_T_MACERR_COUNT (0U)   /*!< Bit position for ENET_IEEE_T_MACERR_COUNT. */
05207 #define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MACERR_COUNT. */
05208 #define BS_ENET_IEEE_T_MACERR_COUNT (16U)  /*!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT. */
05209 
05210 /*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
05211 #define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
05212 /*@}*/
05213 
05214 /*******************************************************************************
05215  * HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
05216  ******************************************************************************/
05217 
05218 /*!
05219  * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
05220  *
05221  * Reset value: 0x00000000U
05222  */
05223 typedef union _hw_enet_ieee_t_cserr
05224 {
05225     uint32_t U;
05226     struct _hw_enet_ieee_t_cserr_bitfields
05227     {
05228         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05229         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05230     } B;
05231 } hw_enet_ieee_t_cserr_t;
05232 
05233 /*!
05234  * @name Constants and macros for entire ENET_IEEE_T_CSERR register
05235  */
05236 /*@{*/
05237 #define HW_ENET_IEEE_T_CSERR_ADDR(x) ((x) + 0x268U)
05238 
05239 #define HW_ENET_IEEE_T_CSERR(x)  (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
05240 #define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
05241 /*@}*/
05242 
05243 /*
05244  * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
05245  */
05246 
05247 /*!
05248  * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
05249  */
05250 /*@{*/
05251 #define BP_ENET_IEEE_T_CSERR_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_CSERR_COUNT. */
05252 #define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_CSERR_COUNT. */
05253 #define BS_ENET_IEEE_T_CSERR_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT. */
05254 
05255 /*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
05256 #define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
05257 /*@}*/
05258 
05259 /*******************************************************************************
05260  * HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
05261  ******************************************************************************/
05262 
05263 /*!
05264  * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
05265  *
05266  * Reset value: 0x00000000U
05267  */
05268 typedef union _hw_enet_ieee_t_fdxfc
05269 {
05270     uint32_t U;
05271     struct _hw_enet_ieee_t_fdxfc_bitfields
05272     {
05273         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05274         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05275     } B;
05276 } hw_enet_ieee_t_fdxfc_t;
05277 
05278 /*!
05279  * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
05280  */
05281 /*@{*/
05282 #define HW_ENET_IEEE_T_FDXFC_ADDR(x) ((x) + 0x270U)
05283 
05284 #define HW_ENET_IEEE_T_FDXFC(x)  (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
05285 #define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
05286 /*@}*/
05287 
05288 /*
05289  * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
05290  */
05291 
05292 /*!
05293  * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
05294  */
05295 /*@{*/
05296 #define BP_ENET_IEEE_T_FDXFC_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_FDXFC_COUNT. */
05297 #define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FDXFC_COUNT. */
05298 #define BS_ENET_IEEE_T_FDXFC_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT. */
05299 
05300 /*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
05301 #define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
05302 /*@}*/
05303 
05304 /*******************************************************************************
05305  * HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
05306  ******************************************************************************/
05307 
05308 /*!
05309  * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
05310  *
05311  * Reset value: 0x00000000U
05312  *
05313  * Counts total octets (includes header and FCS fields).
05314  */
05315 typedef union _hw_enet_ieee_t_octets_ok
05316 {
05317     uint32_t U;
05318     struct _hw_enet_ieee_t_octets_ok_bitfields
05319     {
05320         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
05321     } B;
05322 } hw_enet_ieee_t_octets_ok_t;
05323 
05324 /*!
05325  * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
05326  */
05327 /*@{*/
05328 #define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) ((x) + 0x274U)
05329 
05330 #define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
05331 #define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
05332 /*@}*/
05333 
05334 /*
05335  * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
05336  */
05337 
05338 /*!
05339  * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
05340  */
05341 /*@{*/
05342 #define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT. */
05343 #define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT. */
05344 #define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT. */
05345 
05346 /*! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field. */
05347 #define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
05348 /*@}*/
05349 
05350 /*******************************************************************************
05351  * HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
05352  ******************************************************************************/
05353 
05354 /*!
05355  * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
05356  *
05357  * Reset value: 0x00000000U
05358  */
05359 typedef union _hw_enet_rmon_r_packets
05360 {
05361     uint32_t U;
05362     struct _hw_enet_rmon_r_packets_bitfields
05363     {
05364         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05365         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05366     } B;
05367 } hw_enet_rmon_r_packets_t;
05368 
05369 /*!
05370  * @name Constants and macros for entire ENET_RMON_R_PACKETS register
05371  */
05372 /*@{*/
05373 #define HW_ENET_RMON_R_PACKETS_ADDR(x) ((x) + 0x284U)
05374 
05375 #define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
05376 #define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
05377 /*@}*/
05378 
05379 /*
05380  * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
05381  */
05382 
05383 /*!
05384  * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
05385  */
05386 /*@{*/
05387 #define BP_ENET_RMON_R_PACKETS_COUNT (0U)  /*!< Bit position for ENET_RMON_R_PACKETS_COUNT. */
05388 #define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_PACKETS_COUNT. */
05389 #define BS_ENET_RMON_R_PACKETS_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT. */
05390 
05391 /*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
05392 #define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
05393 /*@}*/
05394 
05395 /*******************************************************************************
05396  * HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
05397  ******************************************************************************/
05398 
05399 /*!
05400  * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
05401  *
05402  * Reset value: 0x00000000U
05403  */
05404 typedef union _hw_enet_rmon_r_bc_pkt
05405 {
05406     uint32_t U;
05407     struct _hw_enet_rmon_r_bc_pkt_bitfields
05408     {
05409         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05410         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05411     } B;
05412 } hw_enet_rmon_r_bc_pkt_t;
05413 
05414 /*!
05415  * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
05416  */
05417 /*@{*/
05418 #define HW_ENET_RMON_R_BC_PKT_ADDR(x) ((x) + 0x288U)
05419 
05420 #define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
05421 #define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
05422 /*@}*/
05423 
05424 /*
05425  * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
05426  */
05427 
05428 /*!
05429  * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
05430  */
05431 /*@{*/
05432 #define BP_ENET_RMON_R_BC_PKT_COUNT (0U)   /*!< Bit position for ENET_RMON_R_BC_PKT_COUNT. */
05433 #define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_BC_PKT_COUNT. */
05434 #define BS_ENET_RMON_R_BC_PKT_COUNT (16U)  /*!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT. */
05435 
05436 /*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
05437 #define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
05438 /*@}*/
05439 
05440 /*******************************************************************************
05441  * HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
05442  ******************************************************************************/
05443 
05444 /*!
05445  * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
05446  *
05447  * Reset value: 0x00000000U
05448  */
05449 typedef union _hw_enet_rmon_r_mc_pkt
05450 {
05451     uint32_t U;
05452     struct _hw_enet_rmon_r_mc_pkt_bitfields
05453     {
05454         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05455         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05456     } B;
05457 } hw_enet_rmon_r_mc_pkt_t;
05458 
05459 /*!
05460  * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
05461  */
05462 /*@{*/
05463 #define HW_ENET_RMON_R_MC_PKT_ADDR(x) ((x) + 0x28CU)
05464 
05465 #define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
05466 #define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
05467 /*@}*/
05468 
05469 /*
05470  * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
05471  */
05472 
05473 /*!
05474  * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
05475  */
05476 /*@{*/
05477 #define BP_ENET_RMON_R_MC_PKT_COUNT (0U)   /*!< Bit position for ENET_RMON_R_MC_PKT_COUNT. */
05478 #define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_MC_PKT_COUNT. */
05479 #define BS_ENET_RMON_R_MC_PKT_COUNT (16U)  /*!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT. */
05480 
05481 /*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
05482 #define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
05483 /*@}*/
05484 
05485 /*******************************************************************************
05486  * HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
05487  ******************************************************************************/
05488 
05489 /*!
05490  * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
05491  *
05492  * Reset value: 0x00000000U
05493  */
05494 typedef union _hw_enet_rmon_r_crc_align
05495 {
05496     uint32_t U;
05497     struct _hw_enet_rmon_r_crc_align_bitfields
05498     {
05499         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05500         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05501     } B;
05502 } hw_enet_rmon_r_crc_align_t;
05503 
05504 /*!
05505  * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
05506  */
05507 /*@{*/
05508 #define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) ((x) + 0x290U)
05509 
05510 #define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
05511 #define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
05512 /*@}*/
05513 
05514 /*
05515  * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
05516  */
05517 
05518 /*!
05519  * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
05520  */
05521 /*@{*/
05522 #define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) /*!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT. */
05523 #define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT. */
05524 #define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT. */
05525 
05526 /*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
05527 #define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
05528 /*@}*/
05529 
05530 /*******************************************************************************
05531  * HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
05532  ******************************************************************************/
05533 
05534 /*!
05535  * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
05536  *
05537  * Reset value: 0x00000000U
05538  */
05539 typedef union _hw_enet_rmon_r_undersize
05540 {
05541     uint32_t U;
05542     struct _hw_enet_rmon_r_undersize_bitfields
05543     {
05544         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05545         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05546     } B;
05547 } hw_enet_rmon_r_undersize_t;
05548 
05549 /*!
05550  * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
05551  */
05552 /*@{*/
05553 #define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) ((x) + 0x294U)
05554 
05555 #define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
05556 #define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
05557 /*@}*/
05558 
05559 /*
05560  * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
05561  */
05562 
05563 /*!
05564  * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
05565  */
05566 /*@{*/
05567 #define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT. */
05568 #define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT. */
05569 #define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT. */
05570 
05571 /*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
05572 #define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
05573 /*@}*/
05574 
05575 /*******************************************************************************
05576  * HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
05577  ******************************************************************************/
05578 
05579 /*!
05580  * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
05581  *
05582  * Reset value: 0x00000000U
05583  */
05584 typedef union _hw_enet_rmon_r_oversize
05585 {
05586     uint32_t U;
05587     struct _hw_enet_rmon_r_oversize_bitfields
05588     {
05589         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05590         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05591     } B;
05592 } hw_enet_rmon_r_oversize_t;
05593 
05594 /*!
05595  * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
05596  */
05597 /*@{*/
05598 #define HW_ENET_RMON_R_OVERSIZE_ADDR(x) ((x) + 0x298U)
05599 
05600 #define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
05601 #define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
05602 /*@}*/
05603 
05604 /*
05605  * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
05606  */
05607 
05608 /*!
05609  * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
05610  */
05611 /*@{*/
05612 #define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_OVERSIZE_COUNT. */
05613 #define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT. */
05614 #define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT. */
05615 
05616 /*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
05617 #define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
05618 /*@}*/
05619 
05620 /*******************************************************************************
05621  * HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
05622  ******************************************************************************/
05623 
05624 /*!
05625  * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
05626  *
05627  * Reset value: 0x00000000U
05628  */
05629 typedef union _hw_enet_rmon_r_frag
05630 {
05631     uint32_t U;
05632     struct _hw_enet_rmon_r_frag_bitfields
05633     {
05634         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05635         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05636     } B;
05637 } hw_enet_rmon_r_frag_t;
05638 
05639 /*!
05640  * @name Constants and macros for entire ENET_RMON_R_FRAG register
05641  */
05642 /*@{*/
05643 #define HW_ENET_RMON_R_FRAG_ADDR(x) ((x) + 0x29CU)
05644 
05645 #define HW_ENET_RMON_R_FRAG(x)   (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
05646 #define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
05647 /*@}*/
05648 
05649 /*
05650  * Constants & macros for individual ENET_RMON_R_FRAG bitfields
05651  */
05652 
05653 /*!
05654  * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
05655  */
05656 /*@{*/
05657 #define BP_ENET_RMON_R_FRAG_COUNT (0U)     /*!< Bit position for ENET_RMON_R_FRAG_COUNT. */
05658 #define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_FRAG_COUNT. */
05659 #define BS_ENET_RMON_R_FRAG_COUNT (16U)    /*!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT. */
05660 
05661 /*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
05662 #define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
05663 /*@}*/
05664 
05665 /*******************************************************************************
05666  * HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
05667  ******************************************************************************/
05668 
05669 /*!
05670  * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
05671  *
05672  * Reset value: 0x00000000U
05673  */
05674 typedef union _hw_enet_rmon_r_jab
05675 {
05676     uint32_t U;
05677     struct _hw_enet_rmon_r_jab_bitfields
05678     {
05679         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05680         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05681     } B;
05682 } hw_enet_rmon_r_jab_t;
05683 
05684 /*!
05685  * @name Constants and macros for entire ENET_RMON_R_JAB register
05686  */
05687 /*@{*/
05688 #define HW_ENET_RMON_R_JAB_ADDR(x) ((x) + 0x2A0U)
05689 
05690 #define HW_ENET_RMON_R_JAB(x)    (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
05691 #define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
05692 /*@}*/
05693 
05694 /*
05695  * Constants & macros for individual ENET_RMON_R_JAB bitfields
05696  */
05697 
05698 /*!
05699  * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
05700  */
05701 /*@{*/
05702 #define BP_ENET_RMON_R_JAB_COUNT (0U)      /*!< Bit position for ENET_RMON_R_JAB_COUNT. */
05703 #define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_JAB_COUNT. */
05704 #define BS_ENET_RMON_R_JAB_COUNT (16U)     /*!< Bit field size in bits for ENET_RMON_R_JAB_COUNT. */
05705 
05706 /*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
05707 #define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
05708 /*@}*/
05709 
05710 /*******************************************************************************
05711  * HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
05712  ******************************************************************************/
05713 
05714 /*!
05715  * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
05716  *
05717  * Reset value: 0x00000000U
05718  */
05719 typedef union _hw_enet_rmon_r_p64
05720 {
05721     uint32_t U;
05722     struct _hw_enet_rmon_r_p64_bitfields
05723     {
05724         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05725         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05726     } B;
05727 } hw_enet_rmon_r_p64_t;
05728 
05729 /*!
05730  * @name Constants and macros for entire ENET_RMON_R_P64 register
05731  */
05732 /*@{*/
05733 #define HW_ENET_RMON_R_P64_ADDR(x) ((x) + 0x2A8U)
05734 
05735 #define HW_ENET_RMON_R_P64(x)    (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
05736 #define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
05737 /*@}*/
05738 
05739 /*
05740  * Constants & macros for individual ENET_RMON_R_P64 bitfields
05741  */
05742 
05743 /*!
05744  * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
05745  */
05746 /*@{*/
05747 #define BP_ENET_RMON_R_P64_COUNT (0U)      /*!< Bit position for ENET_RMON_R_P64_COUNT. */
05748 #define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P64_COUNT. */
05749 #define BS_ENET_RMON_R_P64_COUNT (16U)     /*!< Bit field size in bits for ENET_RMON_R_P64_COUNT. */
05750 
05751 /*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
05752 #define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
05753 /*@}*/
05754 
05755 /*******************************************************************************
05756  * HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
05757  ******************************************************************************/
05758 
05759 /*!
05760  * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
05761  *
05762  * Reset value: 0x00000000U
05763  */
05764 typedef union _hw_enet_rmon_r_p65to127
05765 {
05766     uint32_t U;
05767     struct _hw_enet_rmon_r_p65to127_bitfields
05768     {
05769         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05770         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05771     } B;
05772 } hw_enet_rmon_r_p65to127_t;
05773 
05774 /*!
05775  * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
05776  */
05777 /*@{*/
05778 #define HW_ENET_RMON_R_P65TO127_ADDR(x) ((x) + 0x2ACU)
05779 
05780 #define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
05781 #define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
05782 /*@}*/
05783 
05784 /*
05785  * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
05786  */
05787 
05788 /*!
05789  * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
05790  */
05791 /*@{*/
05792 #define BP_ENET_RMON_R_P65TO127_COUNT (0U) /*!< Bit position for ENET_RMON_R_P65TO127_COUNT. */
05793 #define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P65TO127_COUNT. */
05794 #define BS_ENET_RMON_R_P65TO127_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT. */
05795 
05796 /*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
05797 #define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
05798 /*@}*/
05799 
05800 /*******************************************************************************
05801  * HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
05802  ******************************************************************************/
05803 
05804 /*!
05805  * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
05806  *
05807  * Reset value: 0x00000000U
05808  */
05809 typedef union _hw_enet_rmon_r_p128to255
05810 {
05811     uint32_t U;
05812     struct _hw_enet_rmon_r_p128to255_bitfields
05813     {
05814         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05815         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05816     } B;
05817 } hw_enet_rmon_r_p128to255_t;
05818 
05819 /*!
05820  * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
05821  */
05822 /*@{*/
05823 #define HW_ENET_RMON_R_P128TO255_ADDR(x) ((x) + 0x2B0U)
05824 
05825 #define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
05826 #define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
05827 /*@}*/
05828 
05829 /*
05830  * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
05831  */
05832 
05833 /*!
05834  * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
05835  */
05836 /*@{*/
05837 #define BP_ENET_RMON_R_P128TO255_COUNT (0U) /*!< Bit position for ENET_RMON_R_P128TO255_COUNT. */
05838 #define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P128TO255_COUNT. */
05839 #define BS_ENET_RMON_R_P128TO255_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT. */
05840 
05841 /*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
05842 #define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
05843 /*@}*/
05844 
05845 /*******************************************************************************
05846  * HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
05847  ******************************************************************************/
05848 
05849 /*!
05850  * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
05851  *
05852  * Reset value: 0x00000000U
05853  */
05854 typedef union _hw_enet_rmon_r_p256to511
05855 {
05856     uint32_t U;
05857     struct _hw_enet_rmon_r_p256to511_bitfields
05858     {
05859         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05860         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05861     } B;
05862 } hw_enet_rmon_r_p256to511_t;
05863 
05864 /*!
05865  * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
05866  */
05867 /*@{*/
05868 #define HW_ENET_RMON_R_P256TO511_ADDR(x) ((x) + 0x2B4U)
05869 
05870 #define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
05871 #define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
05872 /*@}*/
05873 
05874 /*
05875  * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
05876  */
05877 
05878 /*!
05879  * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
05880  */
05881 /*@{*/
05882 #define BP_ENET_RMON_R_P256TO511_COUNT (0U) /*!< Bit position for ENET_RMON_R_P256TO511_COUNT. */
05883 #define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P256TO511_COUNT. */
05884 #define BS_ENET_RMON_R_P256TO511_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT. */
05885 
05886 /*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
05887 #define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
05888 /*@}*/
05889 
05890 /*******************************************************************************
05891  * HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
05892  ******************************************************************************/
05893 
05894 /*!
05895  * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
05896  *
05897  * Reset value: 0x00000000U
05898  */
05899 typedef union _hw_enet_rmon_r_p512to1023
05900 {
05901     uint32_t U;
05902     struct _hw_enet_rmon_r_p512to1023_bitfields
05903     {
05904         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05905         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05906     } B;
05907 } hw_enet_rmon_r_p512to1023_t;
05908 
05909 /*!
05910  * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
05911  */
05912 /*@{*/
05913 #define HW_ENET_RMON_R_P512TO1023_ADDR(x) ((x) + 0x2B8U)
05914 
05915 #define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
05916 #define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
05917 /*@}*/
05918 
05919 /*
05920  * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
05921  */
05922 
05923 /*!
05924  * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
05925  */
05926 /*@{*/
05927 #define BP_ENET_RMON_R_P512TO1023_COUNT (0U) /*!< Bit position for ENET_RMON_R_P512TO1023_COUNT. */
05928 #define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P512TO1023_COUNT. */
05929 #define BS_ENET_RMON_R_P512TO1023_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT. */
05930 
05931 /*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
05932 #define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
05933 /*@}*/
05934 
05935 /*******************************************************************************
05936  * HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
05937  ******************************************************************************/
05938 
05939 /*!
05940  * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
05941  *
05942  * Reset value: 0x00000000U
05943  */
05944 typedef union _hw_enet_rmon_r_p1024to2047
05945 {
05946     uint32_t U;
05947     struct _hw_enet_rmon_r_p1024to2047_bitfields
05948     {
05949         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05950         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05951     } B;
05952 } hw_enet_rmon_r_p1024to2047_t;
05953 
05954 /*!
05955  * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
05956  */
05957 /*@{*/
05958 #define HW_ENET_RMON_R_P1024TO2047_ADDR(x) ((x) + 0x2BCU)
05959 
05960 #define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
05961 #define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
05962 /*@}*/
05963 
05964 /*
05965  * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
05966  */
05967 
05968 /*!
05969  * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
05970  */
05971 /*@{*/
05972 #define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) /*!< Bit position for ENET_RMON_R_P1024TO2047_COUNT. */
05973 #define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT. */
05974 #define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT. */
05975 
05976 /*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
05977 #define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
05978 /*@}*/
05979 
05980 /*******************************************************************************
05981  * HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
05982  ******************************************************************************/
05983 
05984 /*!
05985  * @brief HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
05986  *
05987  * Reset value: 0x00000000U
05988  */
05989 typedef union _hw_enet_rmon_r_p_gte2048
05990 {
05991     uint32_t U;
05992     struct _hw_enet_rmon_r_p_gte2048_bitfields
05993     {
05994         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05995         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05996     } B;
05997 } hw_enet_rmon_r_p_gte2048_t;
05998 
05999 /*!
06000  * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
06001  */
06002 /*@{*/
06003 #define HW_ENET_RMON_R_P_GTE2048_ADDR(x) ((x) + 0x2C0U)
06004 
06005 #define HW_ENET_RMON_R_P_GTE2048(x) (*(__I hw_enet_rmon_r_p_gte2048_t *) HW_ENET_RMON_R_P_GTE2048_ADDR(x))
06006 #define HW_ENET_RMON_R_P_GTE2048_RD(x) (HW_ENET_RMON_R_P_GTE2048(x).U)
06007 /*@}*/
06008 
06009 /*
06010  * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
06011  */
06012 
06013 /*!
06014  * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
06015  */
06016 /*@{*/
06017 #define BP_ENET_RMON_R_P_GTE2048_COUNT (0U) /*!< Bit position for ENET_RMON_R_P_GTE2048_COUNT. */
06018 #define BM_ENET_RMON_R_P_GTE2048_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P_GTE2048_COUNT. */
06019 #define BS_ENET_RMON_R_P_GTE2048_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P_GTE2048_COUNT. */
06020 
06021 /*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
06022 #define BR_ENET_RMON_R_P_GTE2048_COUNT(x) (HW_ENET_RMON_R_P_GTE2048(x).B.COUNT)
06023 /*@}*/
06024 
06025 /*******************************************************************************
06026  * HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
06027  ******************************************************************************/
06028 
06029 /*!
06030  * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
06031  *
06032  * Reset value: 0x00000000U
06033  */
06034 typedef union _hw_enet_rmon_r_octets
06035 {
06036     uint32_t U;
06037     struct _hw_enet_rmon_r_octets_bitfields
06038     {
06039         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
06040     } B;
06041 } hw_enet_rmon_r_octets_t;
06042 
06043 /*!
06044  * @name Constants and macros for entire ENET_RMON_R_OCTETS register
06045  */
06046 /*@{*/
06047 #define HW_ENET_RMON_R_OCTETS_ADDR(x) ((x) + 0x2C4U)
06048 
06049 #define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
06050 #define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
06051 /*@}*/
06052 
06053 /*
06054  * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
06055  */
06056 
06057 /*!
06058  * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
06059  */
06060 /*@{*/
06061 #define BP_ENET_RMON_R_OCTETS_COUNT (0U)   /*!< Bit position for ENET_RMON_R_OCTETS_COUNT. */
06062 #define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_R_OCTETS_COUNT. */
06063 #define BS_ENET_RMON_R_OCTETS_COUNT (32U)  /*!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT. */
06064 
06065 /*! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field. */
06066 #define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
06067 /*@}*/
06068 
06069 /*******************************************************************************
06070  * HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
06071  ******************************************************************************/
06072 
06073 /*!
06074  * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
06075  *
06076  * Reset value: 0x00000000U
06077  *
06078  * Counter increments if a frame with invalid or missing SFD character is
06079  * detected and has been dropped. None of the other counters increments if this counter
06080  * increments.
06081  */
06082 typedef union _hw_enet_ieee_r_drop
06083 {
06084     uint32_t U;
06085     struct _hw_enet_ieee_r_drop_bitfields
06086     {
06087         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06088         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06089     } B;
06090 } hw_enet_ieee_r_drop_t;
06091 
06092 /*!
06093  * @name Constants and macros for entire ENET_IEEE_R_DROP register
06094  */
06095 /*@{*/
06096 #define HW_ENET_IEEE_R_DROP_ADDR(x) ((x) + 0x2C8U)
06097 
06098 #define HW_ENET_IEEE_R_DROP(x)   (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
06099 #define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
06100 /*@}*/
06101 
06102 /*
06103  * Constants & macros for individual ENET_IEEE_R_DROP bitfields
06104  */
06105 
06106 /*!
06107  * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
06108  */
06109 /*@{*/
06110 #define BP_ENET_IEEE_R_DROP_COUNT (0U)     /*!< Bit position for ENET_IEEE_R_DROP_COUNT. */
06111 #define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_DROP_COUNT. */
06112 #define BS_ENET_IEEE_R_DROP_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT. */
06113 
06114 /*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
06115 #define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
06116 /*@}*/
06117 
06118 /*******************************************************************************
06119  * HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
06120  ******************************************************************************/
06121 
06122 /*!
06123  * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
06124  *
06125  * Reset value: 0x00000000U
06126  */
06127 typedef union _hw_enet_ieee_r_frame_ok
06128 {
06129     uint32_t U;
06130     struct _hw_enet_ieee_r_frame_ok_bitfields
06131     {
06132         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06133         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06134     } B;
06135 } hw_enet_ieee_r_frame_ok_t;
06136 
06137 /*!
06138  * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
06139  */
06140 /*@{*/
06141 #define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) ((x) + 0x2CCU)
06142 
06143 #define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
06144 #define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
06145 /*@}*/
06146 
06147 /*
06148  * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
06149  */
06150 
06151 /*!
06152  * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
06153  */
06154 /*@{*/
06155 #define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT. */
06156 #define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT. */
06157 #define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT. */
06158 
06159 /*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
06160 #define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
06161 /*@}*/
06162 
06163 /*******************************************************************************
06164  * HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
06165  ******************************************************************************/
06166 
06167 /*!
06168  * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
06169  *
06170  * Reset value: 0x00000000U
06171  */
06172 typedef union _hw_enet_ieee_r_crc
06173 {
06174     uint32_t U;
06175     struct _hw_enet_ieee_r_crc_bitfields
06176     {
06177         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06178         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06179     } B;
06180 } hw_enet_ieee_r_crc_t;
06181 
06182 /*!
06183  * @name Constants and macros for entire ENET_IEEE_R_CRC register
06184  */
06185 /*@{*/
06186 #define HW_ENET_IEEE_R_CRC_ADDR(x) ((x) + 0x2D0U)
06187 
06188 #define HW_ENET_IEEE_R_CRC(x)    (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
06189 #define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
06190 /*@}*/
06191 
06192 /*
06193  * Constants & macros for individual ENET_IEEE_R_CRC bitfields
06194  */
06195 
06196 /*!
06197  * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
06198  */
06199 /*@{*/
06200 #define BP_ENET_IEEE_R_CRC_COUNT (0U)      /*!< Bit position for ENET_IEEE_R_CRC_COUNT. */
06201 #define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_CRC_COUNT. */
06202 #define BS_ENET_IEEE_R_CRC_COUNT (16U)     /*!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT. */
06203 
06204 /*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
06205 #define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
06206 /*@}*/
06207 
06208 /*******************************************************************************
06209  * HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
06210  ******************************************************************************/
06211 
06212 /*!
06213  * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
06214  *
06215  * Reset value: 0x00000000U
06216  */
06217 typedef union _hw_enet_ieee_r_align
06218 {
06219     uint32_t U;
06220     struct _hw_enet_ieee_r_align_bitfields
06221     {
06222         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06223         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06224     } B;
06225 } hw_enet_ieee_r_align_t;
06226 
06227 /*!
06228  * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
06229  */
06230 /*@{*/
06231 #define HW_ENET_IEEE_R_ALIGN_ADDR(x) ((x) + 0x2D4U)
06232 
06233 #define HW_ENET_IEEE_R_ALIGN(x)  (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
06234 #define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
06235 /*@}*/
06236 
06237 /*
06238  * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
06239  */
06240 
06241 /*!
06242  * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
06243  */
06244 /*@{*/
06245 #define BP_ENET_IEEE_R_ALIGN_COUNT (0U)    /*!< Bit position for ENET_IEEE_R_ALIGN_COUNT. */
06246 #define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_ALIGN_COUNT. */
06247 #define BS_ENET_IEEE_R_ALIGN_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT. */
06248 
06249 /*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
06250 #define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
06251 /*@}*/
06252 
06253 /*******************************************************************************
06254  * HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
06255  ******************************************************************************/
06256 
06257 /*!
06258  * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
06259  *
06260  * Reset value: 0x00000000U
06261  */
06262 typedef union _hw_enet_ieee_r_macerr
06263 {
06264     uint32_t U;
06265     struct _hw_enet_ieee_r_macerr_bitfields
06266     {
06267         uint32_t COUNT : 16;           /*!< [15:0] Count */
06268         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06269     } B;
06270 } hw_enet_ieee_r_macerr_t;
06271 
06272 /*!
06273  * @name Constants and macros for entire ENET_IEEE_R_MACERR register
06274  */
06275 /*@{*/
06276 #define HW_ENET_IEEE_R_MACERR_ADDR(x) ((x) + 0x2D8U)
06277 
06278 #define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
06279 #define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
06280 /*@}*/
06281 
06282 /*
06283  * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
06284  */
06285 
06286 /*!
06287  * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
06288  */
06289 /*@{*/
06290 #define BP_ENET_IEEE_R_MACERR_COUNT (0U)   /*!< Bit position for ENET_IEEE_R_MACERR_COUNT. */
06291 #define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_MACERR_COUNT. */
06292 #define BS_ENET_IEEE_R_MACERR_COUNT (16U)  /*!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT. */
06293 
06294 /*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
06295 #define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
06296 /*@}*/
06297 
06298 /*******************************************************************************
06299  * HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
06300  ******************************************************************************/
06301 
06302 /*!
06303  * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
06304  *
06305  * Reset value: 0x00000000U
06306  */
06307 typedef union _hw_enet_ieee_r_fdxfc
06308 {
06309     uint32_t U;
06310     struct _hw_enet_ieee_r_fdxfc_bitfields
06311     {
06312         uint32_t COUNT : 16;           /*!< [15:0] Pause frame count */
06313         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06314     } B;
06315 } hw_enet_ieee_r_fdxfc_t;
06316 
06317 /*!
06318  * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
06319  */
06320 /*@{*/
06321 #define HW_ENET_IEEE_R_FDXFC_ADDR(x) ((x) + 0x2DCU)
06322 
06323 #define HW_ENET_IEEE_R_FDXFC(x)  (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
06324 #define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
06325 /*@}*/
06326 
06327 /*
06328  * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
06329  */
06330 
06331 /*!
06332  * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
06333  */
06334 /*@{*/
06335 #define BP_ENET_IEEE_R_FDXFC_COUNT (0U)    /*!< Bit position for ENET_IEEE_R_FDXFC_COUNT. */
06336 #define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FDXFC_COUNT. */
06337 #define BS_ENET_IEEE_R_FDXFC_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT. */
06338 
06339 /*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
06340 #define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
06341 /*@}*/
06342 
06343 /*******************************************************************************
06344  * HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
06345  ******************************************************************************/
06346 
06347 /*!
06348  * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
06349  *
06350  * Reset value: 0x00000000U
06351  */
06352 typedef union _hw_enet_ieee_r_octets_ok
06353 {
06354     uint32_t U;
06355     struct _hw_enet_ieee_r_octets_ok_bitfields
06356     {
06357         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
06358     } B;
06359 } hw_enet_ieee_r_octets_ok_t;
06360 
06361 /*!
06362  * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
06363  */
06364 /*@{*/
06365 #define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) ((x) + 0x2E0U)
06366 
06367 #define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
06368 #define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
06369 /*@}*/
06370 
06371 /*
06372  * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
06373  */
06374 
06375 /*!
06376  * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
06377  */
06378 /*@{*/
06379 #define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT. */
06380 #define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT. */
06381 #define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT. */
06382 
06383 /*! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field. */
06384 #define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
06385 /*@}*/
06386 
06387 /*******************************************************************************
06388  * HW_ENET_ATCR - Adjustable Timer Control Register
06389  ******************************************************************************/
06390 
06391 /*!
06392  * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
06393  *
06394  * Reset value: 0x00000000U
06395  *
06396  * ATCR command fields can trigger the corresponding events directly. It is not
06397  * necessary to preserve any of the configuration fields when a command field is
06398  * set in the register, that is, no read-modify-write is required. The fields are
06399  * automatically cleared after the command completes.
06400  */
06401 typedef union _hw_enet_atcr
06402 {
06403     uint32_t U;
06404     struct _hw_enet_atcr_bitfields
06405     {
06406         uint32_t EN : 1;               /*!< [0] Enable Timer */
06407         uint32_t RESERVED0 : 1;        /*!< [1]  */
06408         uint32_t OFFEN : 1;            /*!< [2] Enable One-Shot Offset Event */
06409         uint32_t OFFRST : 1;           /*!< [3] Reset Timer On Offset Event */
06410         uint32_t PEREN : 1;            /*!< [4] Enable Periodical Event */
06411         uint32_t RESERVED1 : 2;        /*!< [6:5]  */
06412         uint32_t PINPER : 1;           /*!< [7]  */
06413         uint32_t RESERVED2 : 1;        /*!< [8]  */
06414         uint32_t RESTART : 1;          /*!< [9] Reset Timer */
06415         uint32_t RESERVED3 : 1;        /*!< [10]  */
06416         uint32_t CAPTURE : 1;          /*!< [11] Capture Timer Value */
06417         uint32_t RESERVED4 : 1;        /*!< [12]  */
06418         uint32_t SLAVE : 1;            /*!< [13] Enable Timer Slave Mode */
06419         uint32_t RESERVED5 : 18;       /*!< [31:14]  */
06420     } B;
06421 } hw_enet_atcr_t;
06422 
06423 /*!
06424  * @name Constants and macros for entire ENET_ATCR register
06425  */
06426 /*@{*/
06427 #define HW_ENET_ATCR_ADDR(x)     ((x) + 0x400U)
06428 
06429 #define HW_ENET_ATCR(x)          (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
06430 #define HW_ENET_ATCR_RD(x)       (HW_ENET_ATCR(x).U)
06431 #define HW_ENET_ATCR_WR(x, v)    (HW_ENET_ATCR(x).U = (v))
06432 #define HW_ENET_ATCR_SET(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) |  (v)))
06433 #define HW_ENET_ATCR_CLR(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
06434 #define HW_ENET_ATCR_TOG(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^  (v)))
06435 /*@}*/
06436 
06437 /*
06438  * Constants & macros for individual ENET_ATCR bitfields
06439  */
06440 
06441 /*!
06442  * @name Register ENET_ATCR, field EN[0] (RW)
06443  *
06444  * Values:
06445  * - 0 - The timer stops at the current value.
06446  * - 1 - The timer starts incrementing.
06447  */
06448 /*@{*/
06449 #define BP_ENET_ATCR_EN      (0U)          /*!< Bit position for ENET_ATCR_EN. */
06450 #define BM_ENET_ATCR_EN      (0x00000001U) /*!< Bit mask for ENET_ATCR_EN. */
06451 #define BS_ENET_ATCR_EN      (1U)          /*!< Bit field size in bits for ENET_ATCR_EN. */
06452 
06453 /*! @brief Read current value of the ENET_ATCR_EN field. */
06454 #define BR_ENET_ATCR_EN(x)   (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
06455 
06456 /*! @brief Format value for bitfield ENET_ATCR_EN. */
06457 #define BF_ENET_ATCR_EN(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN)
06458 
06459 /*! @brief Set the EN field to a new value. */
06460 #define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
06461 /*@}*/
06462 
06463 /*!
06464  * @name Register ENET_ATCR, field OFFEN[2] (RW)
06465  *
06466  * Values:
06467  * - 0 - Disable.
06468  * - 1 - The timer can be reset to zero when the given offset time is reached
06469  *     (offset event). The field is cleared when the offset event is reached, so no
06470  *     further event occurs until the field is set again. The timer offset value
06471  *     must be set before setting this field.
06472  */
06473 /*@{*/
06474 #define BP_ENET_ATCR_OFFEN   (2U)          /*!< Bit position for ENET_ATCR_OFFEN. */
06475 #define BM_ENET_ATCR_OFFEN   (0x00000004U) /*!< Bit mask for ENET_ATCR_OFFEN. */
06476 #define BS_ENET_ATCR_OFFEN   (1U)          /*!< Bit field size in bits for ENET_ATCR_OFFEN. */
06477 
06478 /*! @brief Read current value of the ENET_ATCR_OFFEN field. */
06479 #define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
06480 
06481 /*! @brief Format value for bitfield ENET_ATCR_OFFEN. */
06482 #define BF_ENET_ATCR_OFFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN)
06483 
06484 /*! @brief Set the OFFEN field to a new value. */
06485 #define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
06486 /*@}*/
06487 
06488 /*!
06489  * @name Register ENET_ATCR, field OFFRST[3] (RW)
06490  *
06491  * Values:
06492  * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
06493  *     when the offset is reached.
06494  * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
06495  *     reached. The offset event does not cause a timer interrupt.
06496  */
06497 /*@{*/
06498 #define BP_ENET_ATCR_OFFRST  (3U)          /*!< Bit position for ENET_ATCR_OFFRST. */
06499 #define BM_ENET_ATCR_OFFRST  (0x00000008U) /*!< Bit mask for ENET_ATCR_OFFRST. */
06500 #define BS_ENET_ATCR_OFFRST  (1U)          /*!< Bit field size in bits for ENET_ATCR_OFFRST. */
06501 
06502 /*! @brief Read current value of the ENET_ATCR_OFFRST field. */
06503 #define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
06504 
06505 /*! @brief Format value for bitfield ENET_ATCR_OFFRST. */
06506 #define BF_ENET_ATCR_OFFRST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST)
06507 
06508 /*! @brief Set the OFFRST field to a new value. */
06509 #define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
06510 /*@}*/
06511 
06512 /*!
06513  * @name Register ENET_ATCR, field PEREN[4] (RW)
06514  *
06515  * Values:
06516  * - 0 - Disable.
06517  * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
06518  *     signal output is asserted when the timer wraps around according to the
06519  *     periodic setting ATPER. The timer period value must be set before setting
06520  *     this bit. Not all devices contain the event signal output. See the chip
06521  *     configuration details.
06522  */
06523 /*@{*/
06524 #define BP_ENET_ATCR_PEREN   (4U)          /*!< Bit position for ENET_ATCR_PEREN. */
06525 #define BM_ENET_ATCR_PEREN   (0x00000010U) /*!< Bit mask for ENET_ATCR_PEREN. */
06526 #define BS_ENET_ATCR_PEREN   (1U)          /*!< Bit field size in bits for ENET_ATCR_PEREN. */
06527 
06528 /*! @brief Read current value of the ENET_ATCR_PEREN field. */
06529 #define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
06530 
06531 /*! @brief Format value for bitfield ENET_ATCR_PEREN. */
06532 #define BF_ENET_ATCR_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN)
06533 
06534 /*! @brief Set the PEREN field to a new value. */
06535 #define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
06536 /*@}*/
06537 
06538 /*!
06539  * @name Register ENET_ATCR, field PINPER[7] (RW)
06540  *
06541  * Enables event signal output assertion on period event. Not all devices
06542  * contain the event signal output. See the chip configuration details.
06543  *
06544  * Values:
06545  * - 0 - Disable.
06546  * - 1 - Enable.
06547  */
06548 /*@{*/
06549 #define BP_ENET_ATCR_PINPER  (7U)          /*!< Bit position for ENET_ATCR_PINPER. */
06550 #define BM_ENET_ATCR_PINPER  (0x00000080U) /*!< Bit mask for ENET_ATCR_PINPER. */
06551 #define BS_ENET_ATCR_PINPER  (1U)          /*!< Bit field size in bits for ENET_ATCR_PINPER. */
06552 
06553 /*! @brief Read current value of the ENET_ATCR_PINPER field. */
06554 #define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
06555 
06556 /*! @brief Format value for bitfield ENET_ATCR_PINPER. */
06557 #define BF_ENET_ATCR_PINPER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER)
06558 
06559 /*! @brief Set the PINPER field to a new value. */
06560 #define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
06561 /*@}*/
06562 
06563 /*!
06564  * @name Register ENET_ATCR, field RESTART[9] (RW)
06565  *
06566  * Resets the timer to zero. This has no effect on the counter enable. If the
06567  * counter is enabled when this field is set, the timer is reset to zero and starts
06568  * counting from there. When set, all other fields are ignored during a write.
06569  */
06570 /*@{*/
06571 #define BP_ENET_ATCR_RESTART (9U)          /*!< Bit position for ENET_ATCR_RESTART. */
06572 #define BM_ENET_ATCR_RESTART (0x00000200U) /*!< Bit mask for ENET_ATCR_RESTART. */
06573 #define BS_ENET_ATCR_RESTART (1U)          /*!< Bit field size in bits for ENET_ATCR_RESTART. */
06574 
06575 /*! @brief Read current value of the ENET_ATCR_RESTART field. */
06576 #define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
06577 
06578 /*! @brief Format value for bitfield ENET_ATCR_RESTART. */
06579 #define BF_ENET_ATCR_RESTART(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART)
06580 
06581 /*! @brief Set the RESTART field to a new value. */
06582 #define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
06583 /*@}*/
06584 
06585 /*!
06586  * @name Register ENET_ATCR, field CAPTURE[11] (RW)
06587  *
06588  * Values:
06589  * - 0 - No effect.
06590  * - 1 - The current time is captured and can be read from the ATVR register.
06591  */
06592 /*@{*/
06593 #define BP_ENET_ATCR_CAPTURE (11U)         /*!< Bit position for ENET_ATCR_CAPTURE. */
06594 #define BM_ENET_ATCR_CAPTURE (0x00000800U) /*!< Bit mask for ENET_ATCR_CAPTURE. */
06595 #define BS_ENET_ATCR_CAPTURE (1U)          /*!< Bit field size in bits for ENET_ATCR_CAPTURE. */
06596 
06597 /*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
06598 #define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
06599 
06600 /*! @brief Format value for bitfield ENET_ATCR_CAPTURE. */
06601 #define BF_ENET_ATCR_CAPTURE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE)
06602 
06603 /*! @brief Set the CAPTURE field to a new value. */
06604 #define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
06605 /*@}*/
06606 
06607 /*!
06608  * @name Register ENET_ATCR, field SLAVE[13] (RW)
06609  *
06610  * Values:
06611  * - 0 - The timer is active and all configuration fields in this register are
06612  *     relevant.
06613  * - 1 - The internal timer is disabled and the externally provided timer value
06614  *     is used. All other fields, except CAPTURE, in this register have no
06615  *     effect. CAPTURE can still be used to capture the current timer value.
06616  */
06617 /*@{*/
06618 #define BP_ENET_ATCR_SLAVE   (13U)         /*!< Bit position for ENET_ATCR_SLAVE. */
06619 #define BM_ENET_ATCR_SLAVE   (0x00002000U) /*!< Bit mask for ENET_ATCR_SLAVE. */
06620 #define BS_ENET_ATCR_SLAVE   (1U)          /*!< Bit field size in bits for ENET_ATCR_SLAVE. */
06621 
06622 /*! @brief Read current value of the ENET_ATCR_SLAVE field. */
06623 #define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
06624 
06625 /*! @brief Format value for bitfield ENET_ATCR_SLAVE. */
06626 #define BF_ENET_ATCR_SLAVE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE)
06627 
06628 /*! @brief Set the SLAVE field to a new value. */
06629 #define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
06630 /*@}*/
06631 
06632 /*******************************************************************************
06633  * HW_ENET_ATVR - Timer Value Register
06634  ******************************************************************************/
06635 
06636 /*!
06637  * @brief HW_ENET_ATVR - Timer Value Register (RW)
06638  *
06639  * Reset value: 0x00000000U
06640  */
06641 typedef union _hw_enet_atvr
06642 {
06643     uint32_t U;
06644     struct _hw_enet_atvr_bitfields
06645     {
06646         uint32_t ATIME : 32;           /*!< [31:0]  */
06647     } B;
06648 } hw_enet_atvr_t;
06649 
06650 /*!
06651  * @name Constants and macros for entire ENET_ATVR register
06652  */
06653 /*@{*/
06654 #define HW_ENET_ATVR_ADDR(x)     ((x) + 0x404U)
06655 
06656 #define HW_ENET_ATVR(x)          (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
06657 #define HW_ENET_ATVR_RD(x)       (HW_ENET_ATVR(x).U)
06658 #define HW_ENET_ATVR_WR(x, v)    (HW_ENET_ATVR(x).U = (v))
06659 #define HW_ENET_ATVR_SET(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) |  (v)))
06660 #define HW_ENET_ATVR_CLR(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
06661 #define HW_ENET_ATVR_TOG(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^  (v)))
06662 /*@}*/
06663 
06664 /*
06665  * Constants & macros for individual ENET_ATVR bitfields
06666  */
06667 
06668 /*!
06669  * @name Register ENET_ATVR, field ATIME[31:0] (RW)
06670  *
06671  * A write sets the timer. A read returns the last captured value. To read the
06672  * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
06673  * this register.
06674  */
06675 /*@{*/
06676 #define BP_ENET_ATVR_ATIME   (0U)          /*!< Bit position for ENET_ATVR_ATIME. */
06677 #define BM_ENET_ATVR_ATIME   (0xFFFFFFFFU) /*!< Bit mask for ENET_ATVR_ATIME. */
06678 #define BS_ENET_ATVR_ATIME   (32U)         /*!< Bit field size in bits for ENET_ATVR_ATIME. */
06679 
06680 /*! @brief Read current value of the ENET_ATVR_ATIME field. */
06681 #define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
06682 
06683 /*! @brief Format value for bitfield ENET_ATVR_ATIME. */
06684 #define BF_ENET_ATVR_ATIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME)
06685 
06686 /*! @brief Set the ATIME field to a new value. */
06687 #define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
06688 /*@}*/
06689 
06690 /*******************************************************************************
06691  * HW_ENET_ATOFF - Timer Offset Register
06692  ******************************************************************************/
06693 
06694 /*!
06695  * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
06696  *
06697  * Reset value: 0x00000000U
06698  */
06699 typedef union _hw_enet_atoff
06700 {
06701     uint32_t U;
06702     struct _hw_enet_atoff_bitfields
06703     {
06704         uint32_t OFFSET : 32;          /*!< [31:0]  */
06705     } B;
06706 } hw_enet_atoff_t;
06707 
06708 /*!
06709  * @name Constants and macros for entire ENET_ATOFF register
06710  */
06711 /*@{*/
06712 #define HW_ENET_ATOFF_ADDR(x)    ((x) + 0x408U)
06713 
06714 #define HW_ENET_ATOFF(x)         (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
06715 #define HW_ENET_ATOFF_RD(x)      (HW_ENET_ATOFF(x).U)
06716 #define HW_ENET_ATOFF_WR(x, v)   (HW_ENET_ATOFF(x).U = (v))
06717 #define HW_ENET_ATOFF_SET(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) |  (v)))
06718 #define HW_ENET_ATOFF_CLR(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
06719 #define HW_ENET_ATOFF_TOG(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^  (v)))
06720 /*@}*/
06721 
06722 /*
06723  * Constants & macros for individual ENET_ATOFF bitfields
06724  */
06725 
06726 /*!
06727  * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
06728  *
06729  * Offset value for one-shot event generation. When the timer reaches the value,
06730  * an event can be generated to reset the counter. If the increment value in
06731  * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
06732  */
06733 /*@{*/
06734 #define BP_ENET_ATOFF_OFFSET (0U)          /*!< Bit position for ENET_ATOFF_OFFSET. */
06735 #define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) /*!< Bit mask for ENET_ATOFF_OFFSET. */
06736 #define BS_ENET_ATOFF_OFFSET (32U)         /*!< Bit field size in bits for ENET_ATOFF_OFFSET. */
06737 
06738 /*! @brief Read current value of the ENET_ATOFF_OFFSET field. */
06739 #define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
06740 
06741 /*! @brief Format value for bitfield ENET_ATOFF_OFFSET. */
06742 #define BF_ENET_ATOFF_OFFSET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET)
06743 
06744 /*! @brief Set the OFFSET field to a new value. */
06745 #define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
06746 /*@}*/
06747 
06748 /*******************************************************************************
06749  * HW_ENET_ATPER - Timer Period Register
06750  ******************************************************************************/
06751 
06752 /*!
06753  * @brief HW_ENET_ATPER - Timer Period Register (RW)
06754  *
06755  * Reset value: 0x3B9ACA00U
06756  */
06757 typedef union _hw_enet_atper
06758 {
06759     uint32_t U;
06760     struct _hw_enet_atper_bitfields
06761     {
06762         uint32_t PERIOD : 32;          /*!< [31:0]  */
06763     } B;
06764 } hw_enet_atper_t;
06765 
06766 /*!
06767  * @name Constants and macros for entire ENET_ATPER register
06768  */
06769 /*@{*/
06770 #define HW_ENET_ATPER_ADDR(x)    ((x) + 0x40CU)
06771 
06772 #define HW_ENET_ATPER(x)         (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
06773 #define HW_ENET_ATPER_RD(x)      (HW_ENET_ATPER(x).U)
06774 #define HW_ENET_ATPER_WR(x, v)   (HW_ENET_ATPER(x).U = (v))
06775 #define HW_ENET_ATPER_SET(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) |  (v)))
06776 #define HW_ENET_ATPER_CLR(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
06777 #define HW_ENET_ATPER_TOG(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^  (v)))
06778 /*@}*/
06779 
06780 /*
06781  * Constants & macros for individual ENET_ATPER bitfields
06782  */
06783 
06784 /*!
06785  * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
06786  *
06787  * Value for generating periodic events. Each instance the timer reaches this
06788  * value, the period event occurs and the timer restarts. If the increment value in
06789  * ATINC is given in true nanoseconds, this value is also given in true
06790  * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
06791  * a timer wrap around of one second. The increment value set in ATINC should be
06792  * set to the true nanoseconds of the period of clock ts_clk, hence implementing
06793  * a true 1 second counter.
06794  */
06795 /*@{*/
06796 #define BP_ENET_ATPER_PERIOD (0U)          /*!< Bit position for ENET_ATPER_PERIOD. */
06797 #define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) /*!< Bit mask for ENET_ATPER_PERIOD. */
06798 #define BS_ENET_ATPER_PERIOD (32U)         /*!< Bit field size in bits for ENET_ATPER_PERIOD. */
06799 
06800 /*! @brief Read current value of the ENET_ATPER_PERIOD field. */
06801 #define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
06802 
06803 /*! @brief Format value for bitfield ENET_ATPER_PERIOD. */
06804 #define BF_ENET_ATPER_PERIOD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD)
06805 
06806 /*! @brief Set the PERIOD field to a new value. */
06807 #define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
06808 /*@}*/
06809 
06810 /*******************************************************************************
06811  * HW_ENET_ATCOR - Timer Correction Register
06812  ******************************************************************************/
06813 
06814 /*!
06815  * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
06816  *
06817  * Reset value: 0x00000000U
06818  */
06819 typedef union _hw_enet_atcor
06820 {
06821     uint32_t U;
06822     struct _hw_enet_atcor_bitfields
06823     {
06824         uint32_t COR : 31;             /*!< [30:0] Correction Counter Wrap-Around Value */
06825         uint32_t RESERVED0 : 1;        /*!< [31]  */
06826     } B;
06827 } hw_enet_atcor_t;
06828 
06829 /*!
06830  * @name Constants and macros for entire ENET_ATCOR register
06831  */
06832 /*@{*/
06833 #define HW_ENET_ATCOR_ADDR(x)    ((x) + 0x410U)
06834 
06835 #define HW_ENET_ATCOR(x)         (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
06836 #define HW_ENET_ATCOR_RD(x)      (HW_ENET_ATCOR(x).U)
06837 #define HW_ENET_ATCOR_WR(x, v)   (HW_ENET_ATCOR(x).U = (v))
06838 #define HW_ENET_ATCOR_SET(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) |  (v)))
06839 #define HW_ENET_ATCOR_CLR(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
06840 #define HW_ENET_ATCOR_TOG(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^  (v)))
06841 /*@}*/
06842 
06843 /*
06844  * Constants & macros for individual ENET_ATCOR bitfields
06845  */
06846 
06847 /*!
06848  * @name Register ENET_ATCOR, field COR[30:0] (RW)
06849  *
06850  * Defines after how many timer clock cycles (ts_clk) the correction counter
06851  * should be reset and trigger a correction increment on the timer. The amount of
06852  * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
06853  * counter and no corrections occur. This value is given in clock cycles, not in
06854  * nanoseconds as all other values.
06855  */
06856 /*@{*/
06857 #define BP_ENET_ATCOR_COR    (0U)          /*!< Bit position for ENET_ATCOR_COR. */
06858 #define BM_ENET_ATCOR_COR    (0x7FFFFFFFU) /*!< Bit mask for ENET_ATCOR_COR. */
06859 #define BS_ENET_ATCOR_COR    (31U)         /*!< Bit field size in bits for ENET_ATCOR_COR. */
06860 
06861 /*! @brief Read current value of the ENET_ATCOR_COR field. */
06862 #define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
06863 
06864 /*! @brief Format value for bitfield ENET_ATCOR_COR. */
06865 #define BF_ENET_ATCOR_COR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR)
06866 
06867 /*! @brief Set the COR field to a new value. */
06868 #define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
06869 /*@}*/
06870 
06871 /*******************************************************************************
06872  * HW_ENET_ATINC - Time-Stamping Clock Period Register
06873  ******************************************************************************/
06874 
06875 /*!
06876  * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
06877  *
06878  * Reset value: 0x00000000U
06879  */
06880 typedef union _hw_enet_atinc
06881 {
06882     uint32_t U;
06883     struct _hw_enet_atinc_bitfields
06884     {
06885         uint32_t INC : 7;              /*!< [6:0] Clock Period Of The Timestamping Clock
06886                                         * (ts_clk) In Nanoseconds */
06887         uint32_t RESERVED0 : 1;        /*!< [7]  */
06888         uint32_t INC_CORR : 7;         /*!< [14:8] Correction Increment Value */
06889         uint32_t RESERVED1 : 17;       /*!< [31:15]  */
06890     } B;
06891 } hw_enet_atinc_t;
06892 
06893 /*!
06894  * @name Constants and macros for entire ENET_ATINC register
06895  */
06896 /*@{*/
06897 #define HW_ENET_ATINC_ADDR(x)    ((x) + 0x414U)
06898 
06899 #define HW_ENET_ATINC(x)         (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
06900 #define HW_ENET_ATINC_RD(x)      (HW_ENET_ATINC(x).U)
06901 #define HW_ENET_ATINC_WR(x, v)   (HW_ENET_ATINC(x).U = (v))
06902 #define HW_ENET_ATINC_SET(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) |  (v)))
06903 #define HW_ENET_ATINC_CLR(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
06904 #define HW_ENET_ATINC_TOG(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^  (v)))
06905 /*@}*/
06906 
06907 /*
06908  * Constants & macros for individual ENET_ATINC bitfields
06909  */
06910 
06911 /*!
06912  * @name Register ENET_ATINC, field INC[6:0] (RW)
06913  *
06914  * The timer increments by this amount each clock cycle. For example, set to 10
06915  * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
06916  * that is an integer fraction of the period set in ATPER.
06917  */
06918 /*@{*/
06919 #define BP_ENET_ATINC_INC    (0U)          /*!< Bit position for ENET_ATINC_INC. */
06920 #define BM_ENET_ATINC_INC    (0x0000007FU) /*!< Bit mask for ENET_ATINC_INC. */
06921 #define BS_ENET_ATINC_INC    (7U)          /*!< Bit field size in bits for ENET_ATINC_INC. */
06922 
06923 /*! @brief Read current value of the ENET_ATINC_INC field. */
06924 #define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
06925 
06926 /*! @brief Format value for bitfield ENET_ATINC_INC. */
06927 #define BF_ENET_ATINC_INC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC)
06928 
06929 /*! @brief Set the INC field to a new value. */
06930 #define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
06931 /*@}*/
06932 
06933 /*!
06934  * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
06935  *
06936  * This value is added every time the correction timer expires (every clock
06937  * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
06938  * than INC speeds up the timer.
06939  */
06940 /*@{*/
06941 #define BP_ENET_ATINC_INC_CORR (8U)        /*!< Bit position for ENET_ATINC_INC_CORR. */
06942 #define BM_ENET_ATINC_INC_CORR (0x00007F00U) /*!< Bit mask for ENET_ATINC_INC_CORR. */
06943 #define BS_ENET_ATINC_INC_CORR (7U)        /*!< Bit field size in bits for ENET_ATINC_INC_CORR. */
06944 
06945 /*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
06946 #define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
06947 
06948 /*! @brief Format value for bitfield ENET_ATINC_INC_CORR. */
06949 #define BF_ENET_ATINC_INC_CORR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR)
06950 
06951 /*! @brief Set the INC_CORR field to a new value. */
06952 #define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
06953 /*@}*/
06954 
06955 /*******************************************************************************
06956  * HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
06957  ******************************************************************************/
06958 
06959 /*!
06960  * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
06961  *
06962  * Reset value: 0x00000000U
06963  */
06964 typedef union _hw_enet_atstmp
06965 {
06966     uint32_t U;
06967     struct _hw_enet_atstmp_bitfields
06968     {
06969         uint32_t TIMESTAMP : 32;       /*!< [31:0]  */
06970     } B;
06971 } hw_enet_atstmp_t;
06972 
06973 /*!
06974  * @name Constants and macros for entire ENET_ATSTMP register
06975  */
06976 /*@{*/
06977 #define HW_ENET_ATSTMP_ADDR(x)   ((x) + 0x418U)
06978 
06979 #define HW_ENET_ATSTMP(x)        (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
06980 #define HW_ENET_ATSTMP_RD(x)     (HW_ENET_ATSTMP(x).U)
06981 /*@}*/
06982 
06983 /*
06984  * Constants & macros for individual ENET_ATSTMP bitfields
06985  */
06986 
06987 /*!
06988  * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
06989  *
06990  * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
06991  * This register is only valid when EIR[TS_AVAIL] is set.
06992  */
06993 /*@{*/
06994 #define BP_ENET_ATSTMP_TIMESTAMP (0U)      /*!< Bit position for ENET_ATSTMP_TIMESTAMP. */
06995 #define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) /*!< Bit mask for ENET_ATSTMP_TIMESTAMP. */
06996 #define BS_ENET_ATSTMP_TIMESTAMP (32U)     /*!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP. */
06997 
06998 /*! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field. */
06999 #define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
07000 /*@}*/
07001 
07002 /*******************************************************************************
07003  * HW_ENET_TGSR - Timer Global Status Register
07004  ******************************************************************************/
07005 
07006 /*!
07007  * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
07008  *
07009  * Reset value: 0x00000000U
07010  */
07011 typedef union _hw_enet_tgsr
07012 {
07013     uint32_t U;
07014     struct _hw_enet_tgsr_bitfields
07015     {
07016         uint32_t TF0 : 1;              /*!< [0] Copy Of Timer Flag For Channel 0 */
07017         uint32_t TF1 : 1;              /*!< [1] Copy Of Timer Flag For Channel 1 */
07018         uint32_t TF2 : 1;              /*!< [2] Copy Of Timer Flag For Channel 2 */
07019         uint32_t TF3 : 1;              /*!< [3] Copy Of Timer Flag For Channel 3 */
07020         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
07021     } B;
07022 } hw_enet_tgsr_t;
07023 
07024 /*!
07025  * @name Constants and macros for entire ENET_TGSR register
07026  */
07027 /*@{*/
07028 #define HW_ENET_TGSR_ADDR(x)     ((x) + 0x604U)
07029 
07030 #define HW_ENET_TGSR(x)          (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
07031 #define HW_ENET_TGSR_RD(x)       (HW_ENET_TGSR(x).U)
07032 #define HW_ENET_TGSR_WR(x, v)    (HW_ENET_TGSR(x).U = (v))
07033 #define HW_ENET_TGSR_SET(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) |  (v)))
07034 #define HW_ENET_TGSR_CLR(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
07035 #define HW_ENET_TGSR_TOG(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^  (v)))
07036 /*@}*/
07037 
07038 /*
07039  * Constants & macros for individual ENET_TGSR bitfields
07040  */
07041 
07042 /*!
07043  * @name Register ENET_TGSR, field TF0[0] (W1C)
07044  *
07045  * Values:
07046  * - 0 - Timer Flag for Channel 0 is clear
07047  * - 1 - Timer Flag for Channel 0 is set
07048  */
07049 /*@{*/
07050 #define BP_ENET_TGSR_TF0     (0U)          /*!< Bit position for ENET_TGSR_TF0. */
07051 #define BM_ENET_TGSR_TF0     (0x00000001U) /*!< Bit mask for ENET_TGSR_TF0. */
07052 #define BS_ENET_TGSR_TF0     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF0. */
07053 
07054 /*! @brief Read current value of the ENET_TGSR_TF0 field. */
07055 #define BR_ENET_TGSR_TF0(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
07056 
07057 /*! @brief Format value for bitfield ENET_TGSR_TF0. */
07058 #define BF_ENET_TGSR_TF0(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF0) & BM_ENET_TGSR_TF0)
07059 
07060 /*! @brief Set the TF0 field to a new value. */
07061 #define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
07062 /*@}*/
07063 
07064 /*!
07065  * @name Register ENET_TGSR, field TF1[1] (W1C)
07066  *
07067  * Values:
07068  * - 0 - Timer Flag for Channel 1 is clear
07069  * - 1 - Timer Flag for Channel 1 is set
07070  */
07071 /*@{*/
07072 #define BP_ENET_TGSR_TF1     (1U)          /*!< Bit position for ENET_TGSR_TF1. */
07073 #define BM_ENET_TGSR_TF1     (0x00000002U) /*!< Bit mask for ENET_TGSR_TF1. */
07074 #define BS_ENET_TGSR_TF1     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF1. */
07075 
07076 /*! @brief Read current value of the ENET_TGSR_TF1 field. */
07077 #define BR_ENET_TGSR_TF1(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
07078 
07079 /*! @brief Format value for bitfield ENET_TGSR_TF1. */
07080 #define BF_ENET_TGSR_TF1(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF1) & BM_ENET_TGSR_TF1)
07081 
07082 /*! @brief Set the TF1 field to a new value. */
07083 #define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
07084 /*@}*/
07085 
07086 /*!
07087  * @name Register ENET_TGSR, field TF2[2] (W1C)
07088  *
07089  * Values:
07090  * - 0 - Timer Flag for Channel 2 is clear
07091  * - 1 - Timer Flag for Channel 2 is set
07092  */
07093 /*@{*/
07094 #define BP_ENET_TGSR_TF2     (2U)          /*!< Bit position for ENET_TGSR_TF2. */
07095 #define BM_ENET_TGSR_TF2     (0x00000004U) /*!< Bit mask for ENET_TGSR_TF2. */
07096 #define BS_ENET_TGSR_TF2     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF2. */
07097 
07098 /*! @brief Read current value of the ENET_TGSR_TF2 field. */
07099 #define BR_ENET_TGSR_TF2(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
07100 
07101 /*! @brief Format value for bitfield ENET_TGSR_TF2. */
07102 #define BF_ENET_TGSR_TF2(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF2) & BM_ENET_TGSR_TF2)
07103 
07104 /*! @brief Set the TF2 field to a new value. */
07105 #define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
07106 /*@}*/
07107 
07108 /*!
07109  * @name Register ENET_TGSR, field TF3[3] (W1C)
07110  *
07111  * Values:
07112  * - 0 - Timer Flag for Channel 3 is clear
07113  * - 1 - Timer Flag for Channel 3 is set
07114  */
07115 /*@{*/
07116 #define BP_ENET_TGSR_TF3     (3U)          /*!< Bit position for ENET_TGSR_TF3. */
07117 #define BM_ENET_TGSR_TF3     (0x00000008U) /*!< Bit mask for ENET_TGSR_TF3. */
07118 #define BS_ENET_TGSR_TF3     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF3. */
07119 
07120 /*! @brief Read current value of the ENET_TGSR_TF3 field. */
07121 #define BR_ENET_TGSR_TF3(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
07122 
07123 /*! @brief Format value for bitfield ENET_TGSR_TF3. */
07124 #define BF_ENET_TGSR_TF3(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF3) & BM_ENET_TGSR_TF3)
07125 
07126 /*! @brief Set the TF3 field to a new value. */
07127 #define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
07128 /*@}*/
07129 
07130 /*******************************************************************************
07131  * HW_ENET_TCSRn - Timer Control Status Register
07132  ******************************************************************************/
07133 
07134 /*!
07135  * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
07136  *
07137  * Reset value: 0x00000000U
07138  */
07139 typedef union _hw_enet_tcsrn
07140 {
07141     uint32_t U;
07142     struct _hw_enet_tcsrn_bitfields
07143     {
07144         uint32_t TDRE : 1;             /*!< [0] Timer DMA Request Enable */
07145         uint32_t RESERVED0 : 1;        /*!< [1]  */
07146         uint32_t TMODE : 4;            /*!< [5:2] Timer Mode */
07147         uint32_t TIE : 1;              /*!< [6] Timer Interrupt Enable */
07148         uint32_t TF : 1;               /*!< [7] Timer Flag */
07149         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
07150     } B;
07151 } hw_enet_tcsrn_t;
07152 
07153 /*!
07154  * @name Constants and macros for entire ENET_TCSRn register
07155  */
07156 /*@{*/
07157 #define HW_ENET_TCSRn_COUNT (4U)
07158 
07159 #define HW_ENET_TCSRn_ADDR(x, n) ((x) + 0x608U + (0x8U * (n)))
07160 
07161 #define HW_ENET_TCSRn(x, n)      (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
07162 #define HW_ENET_TCSRn_RD(x, n)   (HW_ENET_TCSRn(x, n).U)
07163 #define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
07164 #define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) |  (v)))
07165 #define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
07166 #define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^  (v)))
07167 /*@}*/
07168 
07169 /*
07170  * Constants & macros for individual ENET_TCSRn bitfields
07171  */
07172 
07173 /*!
07174  * @name Register ENET_TCSRn, field TDRE[0] (RW)
07175  *
07176  * Values:
07177  * - 0 - DMA request is disabled
07178  * - 1 - DMA request is enabled
07179  */
07180 /*@{*/
07181 #define BP_ENET_TCSRn_TDRE   (0U)          /*!< Bit position for ENET_TCSRn_TDRE. */
07182 #define BM_ENET_TCSRn_TDRE   (0x00000001U) /*!< Bit mask for ENET_TCSRn_TDRE. */
07183 #define BS_ENET_TCSRn_TDRE   (1U)          /*!< Bit field size in bits for ENET_TCSRn_TDRE. */
07184 
07185 /*! @brief Read current value of the ENET_TCSRn_TDRE field. */
07186 #define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
07187 
07188 /*! @brief Format value for bitfield ENET_TCSRn_TDRE. */
07189 #define BF_ENET_TCSRn_TDRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TDRE) & BM_ENET_TCSRn_TDRE)
07190 
07191 /*! @brief Set the TDRE field to a new value. */
07192 #define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
07193 /*@}*/
07194 
07195 /*!
07196  * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
07197  *
07198  * Updating the Timer Mode field takes a few cycles to register because it is
07199  * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
07200  * from the 1588 clock domain. When changing Timer Mode, always disable the
07201  * channel and read this register to verify the channel is disabled first.
07202  *
07203  * Values:
07204  * - 0000 - Timer Channel is disabled.
07205  * - 0001 - Timer Channel is configured for Input Capture on rising edge
07206  * - 0010 - Timer Channel is configured for Input Capture on falling edge
07207  * - 0011 - Timer Channel is configured for Input Capture on both edges
07208  * - 0100 - Timer Channel is configured for Output Compare - software only
07209  * - 0101 - Timer Channel is configured for Output Compare - toggle output on
07210  *     compare
07211  * - 0110 - Timer Channel is configured for Output Compare - clear output on
07212  *     compare
07213  * - 0111 - Timer Channel is configured for Output Compare - set output on
07214  *     compare
07215  * - 1000 - Reserved
07216  * - 1010 - Timer Channel is configured for Output Compare - clear output on
07217  *     compare, set output on overflow
07218  * - 10x1 - Timer Channel is configured for Output Compare - set output on
07219  *     compare, clear output on overflow
07220  * - 1100 - Reserved
07221  * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
07222  *     compare for one 1588 clock cycle
07223  * - 1111 - Timer Channel is configured for Output Compare - pulse output high
07224  *     on compare for one 1588 clock cycle
07225  */
07226 /*@{*/
07227 #define BP_ENET_TCSRn_TMODE  (2U)          /*!< Bit position for ENET_TCSRn_TMODE. */
07228 #define BM_ENET_TCSRn_TMODE  (0x0000003CU) /*!< Bit mask for ENET_TCSRn_TMODE. */
07229 #define BS_ENET_TCSRn_TMODE  (4U)          /*!< Bit field size in bits for ENET_TCSRn_TMODE. */
07230 
07231 /*! @brief Read current value of the ENET_TCSRn_TMODE field. */
07232 #define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
07233 
07234 /*! @brief Format value for bitfield ENET_TCSRn_TMODE. */
07235 #define BF_ENET_TCSRn_TMODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TMODE) & BM_ENET_TCSRn_TMODE)
07236 
07237 /*! @brief Set the TMODE field to a new value. */
07238 #define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
07239 /*@}*/
07240 
07241 /*!
07242  * @name Register ENET_TCSRn, field TIE[6] (RW)
07243  *
07244  * Values:
07245  * - 0 - Interrupt is disabled
07246  * - 1 - Interrupt is enabled
07247  */
07248 /*@{*/
07249 #define BP_ENET_TCSRn_TIE    (6U)          /*!< Bit position for ENET_TCSRn_TIE. */
07250 #define BM_ENET_TCSRn_TIE    (0x00000040U) /*!< Bit mask for ENET_TCSRn_TIE. */
07251 #define BS_ENET_TCSRn_TIE    (1U)          /*!< Bit field size in bits for ENET_TCSRn_TIE. */
07252 
07253 /*! @brief Read current value of the ENET_TCSRn_TIE field. */
07254 #define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
07255 
07256 /*! @brief Format value for bitfield ENET_TCSRn_TIE. */
07257 #define BF_ENET_TCSRn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TIE) & BM_ENET_TCSRn_TIE)
07258 
07259 /*! @brief Set the TIE field to a new value. */
07260 #define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
07261 /*@}*/
07262 
07263 /*!
07264  * @name Register ENET_TCSRn, field TF[7] (W1C)
07265  *
07266  * Sets when input capture or output compare occurs. This flag is double
07267  * buffered between the module clock and 1588 clock domains. When this field is 1, it
07268  * can be cleared to 0 by writing 1 to it.
07269  *
07270  * Values:
07271  * - 0 - Input Capture or Output Compare has not occurred
07272  * - 1 - Input Capture or Output Compare has occurred
07273  */
07274 /*@{*/
07275 #define BP_ENET_TCSRn_TF     (7U)          /*!< Bit position for ENET_TCSRn_TF. */
07276 #define BM_ENET_TCSRn_TF     (0x00000080U) /*!< Bit mask for ENET_TCSRn_TF. */
07277 #define BS_ENET_TCSRn_TF     (1U)          /*!< Bit field size in bits for ENET_TCSRn_TF. */
07278 
07279 /*! @brief Read current value of the ENET_TCSRn_TF field. */
07280 #define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
07281 
07282 /*! @brief Format value for bitfield ENET_TCSRn_TF. */
07283 #define BF_ENET_TCSRn_TF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TF) & BM_ENET_TCSRn_TF)
07284 
07285 /*! @brief Set the TF field to a new value. */
07286 #define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
07287 /*@}*/
07288 /*******************************************************************************
07289  * HW_ENET_TCCRn - Timer Compare Capture Register
07290  ******************************************************************************/
07291 
07292 /*!
07293  * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
07294  *
07295  * Reset value: 0x00000000U
07296  */
07297 typedef union _hw_enet_tccrn
07298 {
07299     uint32_t U;
07300     struct _hw_enet_tccrn_bitfields
07301     {
07302         uint32_t TCC : 32;             /*!< [31:0] Timer Capture Compare */
07303     } B;
07304 } hw_enet_tccrn_t;
07305 
07306 /*!
07307  * @name Constants and macros for entire ENET_TCCRn register
07308  */
07309 /*@{*/
07310 #define HW_ENET_TCCRn_COUNT (4U)
07311 
07312 #define HW_ENET_TCCRn_ADDR(x, n) ((x) + 0x60CU + (0x8U * (n)))
07313 
07314 #define HW_ENET_TCCRn(x, n)      (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
07315 #define HW_ENET_TCCRn_RD(x, n)   (HW_ENET_TCCRn(x, n).U)
07316 #define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
07317 #define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) |  (v)))
07318 #define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
07319 #define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^  (v)))
07320 /*@}*/
07321 
07322 /*
07323  * Constants & macros for individual ENET_TCCRn bitfields
07324  */
07325 
07326 /*!
07327  * @name Register ENET_TCCRn, field TCC[31:0] (RW)
07328  *
07329  * This register is double buffered between the module clock and 1588 clock
07330  * domains. When configured for compare, the 1588 clock domain updates with the value
07331  * in the module clock domain whenever the Timer Channel is first enabled and on
07332  * each subsequent compare. Write to this register with the first compare value
07333  * before enabling the Timer Channel. When the Timer Channel is enabled, write
07334  * the second compare value either immediately, or at least before the first
07335  * compare occurs. After each compare, write the next compare value before the previous
07336  * compare occurs and before clearing the Timer Flag. The compare occurs one
07337  * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
07338  * the 1588 clock domain. If the compare value is less than the value of the
07339  * 1588 Counter when the Timer Channel is first enabled, then the compare does not
07340  * occur until following the next overflow of the 1588 Counter. If the compare
07341  * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
07342  * the compare value is less than the value of the IEEE 1588 Counter after the
07343  * overflow, then the compare occurs one 1588 clock cycle following the overflow.
07344  * When configured for Capture, the value of the IEEE 1588 Counter is captured into
07345  * the 1588 clock domain and then updated into the module clock domain, provided
07346  * the Timer Flag is clear. Always read the capture value before clearing the
07347  * Timer Flag.
07348  */
07349 /*@{*/
07350 #define BP_ENET_TCCRn_TCC    (0U)          /*!< Bit position for ENET_TCCRn_TCC. */
07351 #define BM_ENET_TCCRn_TCC    (0xFFFFFFFFU) /*!< Bit mask for ENET_TCCRn_TCC. */
07352 #define BS_ENET_TCCRn_TCC    (32U)         /*!< Bit field size in bits for ENET_TCCRn_TCC. */
07353 
07354 /*! @brief Read current value of the ENET_TCCRn_TCC field. */
07355 #define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
07356 
07357 /*! @brief Format value for bitfield ENET_TCCRn_TCC. */
07358 #define BF_ENET_TCCRn_TCC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCCRn_TCC) & BM_ENET_TCCRn_TCC)
07359 
07360 /*! @brief Set the TCC field to a new value. */
07361 #define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
07362 /*@}*/
07363 
07364 /*******************************************************************************
07365  * hw_enet_t - module struct
07366  ******************************************************************************/
07367 /*!
07368  * @brief All ENET module registers.
07369  */
07370 #pragma pack(1)
07371 typedef struct _hw_enet
07372 {
07373     uint8_t _reserved0[4];
07374     __IO hw_enet_eir_t EIR ;                /*!< [0x4] Interrupt Event Register */
07375     __IO hw_enet_eimr_t EIMR ;              /*!< [0x8] Interrupt Mask Register */
07376     uint8_t _reserved1[4];
07377     __IO hw_enet_rdar_t RDAR ;              /*!< [0x10] Receive Descriptor Active Register */
07378     __IO hw_enet_tdar_t TDAR ;              /*!< [0x14] Transmit Descriptor Active Register */
07379     uint8_t _reserved2[12];
07380     __IO hw_enet_ecr_t ECR ;                /*!< [0x24] Ethernet Control Register */
07381     uint8_t _reserved3[24];
07382     __IO hw_enet_mmfr_t MMFR ;              /*!< [0x40] MII Management Frame Register */
07383     __IO hw_enet_mscr_t MSCR ;              /*!< [0x44] MII Speed Control Register */
07384     uint8_t _reserved4[28];
07385     __IO hw_enet_mibc_t MIBC ;              /*!< [0x64] MIB Control Register */
07386     uint8_t _reserved5[28];
07387     __IO hw_enet_rcr_t RCR ;                /*!< [0x84] Receive Control Register */
07388     uint8_t _reserved6[60];
07389     __IO hw_enet_tcr_t TCR ;                /*!< [0xC4] Transmit Control Register */
07390     uint8_t _reserved7[28];
07391     __IO hw_enet_palr_t PALR ;              /*!< [0xE4] Physical Address Lower Register */
07392     __IO hw_enet_paur_t PAUR ;              /*!< [0xE8] Physical Address Upper Register */
07393     __IO hw_enet_opd_t OPD ;                /*!< [0xEC] Opcode/Pause Duration Register */
07394     uint8_t _reserved8[40];
07395     __IO hw_enet_iaur_t IAUR ;              /*!< [0x118] Descriptor Individual Upper Address Register */
07396     __IO hw_enet_ialr_t IALR ;              /*!< [0x11C] Descriptor Individual Lower Address Register */
07397     __IO hw_enet_gaur_t GAUR ;              /*!< [0x120] Descriptor Group Upper Address Register */
07398     __IO hw_enet_galr_t GALR ;              /*!< [0x124] Descriptor Group Lower Address Register */
07399     uint8_t _reserved9[28];
07400     __IO hw_enet_tfwr_t TFWR ;              /*!< [0x144] Transmit FIFO Watermark Register */
07401     uint8_t _reserved10[56];
07402     __IO hw_enet_rdsr_t RDSR ;              /*!< [0x180] Receive Descriptor Ring Start Register */
07403     __IO hw_enet_tdsr_t TDSR ;              /*!< [0x184] Transmit Buffer Descriptor Ring Start Register */
07404     __IO hw_enet_mrbr_t MRBR ;              /*!< [0x188] Maximum Receive Buffer Size Register */
07405     uint8_t _reserved11[4];
07406     __IO hw_enet_rsfl_t RSFL ;              /*!< [0x190] Receive FIFO Section Full Threshold */
07407     __IO hw_enet_rsem_t RSEM ;              /*!< [0x194] Receive FIFO Section Empty Threshold */
07408     __IO hw_enet_raem_t RAEM ;              /*!< [0x198] Receive FIFO Almost Empty Threshold */
07409     __IO hw_enet_rafl_t RAFL ;              /*!< [0x19C] Receive FIFO Almost Full Threshold */
07410     __IO hw_enet_tsem_t TSEM ;              /*!< [0x1A0] Transmit FIFO Section Empty Threshold */
07411     __IO hw_enet_taem_t TAEM ;              /*!< [0x1A4] Transmit FIFO Almost Empty Threshold */
07412     __IO hw_enet_tafl_t TAFL ;              /*!< [0x1A8] Transmit FIFO Almost Full Threshold */
07413     __IO hw_enet_tipg_t TIPG ;              /*!< [0x1AC] Transmit Inter-Packet Gap */
07414     __IO hw_enet_ftrl_t FTRL ;              /*!< [0x1B0] Frame Truncation Length */
07415     uint8_t _reserved12[12];
07416     __IO hw_enet_tacc_t TACC ;              /*!< [0x1C0] Transmit Accelerator Function Configuration */
07417     __IO hw_enet_racc_t RACC ;              /*!< [0x1C4] Receive Accelerator Function Configuration */
07418     uint8_t _reserved13[60];
07419     __I hw_enet_rmon_t_packets_t RMON_T_PACKETS ; /*!< [0x204] Tx Packet Count Statistic Register */
07420     __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT ; /*!< [0x208] Tx Broadcast Packets Statistic Register */
07421     __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT ; /*!< [0x20C] Tx Multicast Packets Statistic Register */
07422     __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN ; /*!< [0x210] Tx Packets with CRC/Align Error Statistic Register */
07423     __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE ; /*!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register */
07424     __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE ; /*!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
07425     __I hw_enet_rmon_t_frag_t RMON_T_FRAG ; /*!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
07426     __I hw_enet_rmon_t_jab_t RMON_T_JAB ;   /*!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
07427     __I hw_enet_rmon_t_col_t RMON_T_COL ;   /*!< [0x224] Tx Collision Count Statistic Register */
07428     __I hw_enet_rmon_t_p64_t RMON_T_P64 ;   /*!< [0x228] Tx 64-Byte Packets Statistic Register */
07429     __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127 ; /*!< [0x22C] Tx 65- to 127-byte Packets Statistic Register */
07430     __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255 ; /*!< [0x230] Tx 128- to 255-byte Packets Statistic Register */
07431     __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511 ; /*!< [0x234] Tx 256- to 511-byte Packets Statistic Register */
07432     __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023 ; /*!< [0x238] Tx 512- to 1023-byte Packets Statistic Register */
07433     __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047 ; /*!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register */
07434     __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048 ; /*!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register */
07435     __I hw_enet_rmon_t_octets_t RMON_T_OCTETS ; /*!< [0x244] Tx Octets Statistic Register */
07436     uint8_t _reserved14[4];
07437     __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK ; /*!< [0x24C] Frames Transmitted OK Statistic Register */
07438     __I hw_enet_ieee_t_1col_t IEEE_T_1COL ; /*!< [0x250] Frames Transmitted with Single Collision Statistic Register */
07439     __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL ; /*!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register */
07440     __I hw_enet_ieee_t_def_t IEEE_T_DEF ;   /*!< [0x258] Frames Transmitted after Deferral Delay Statistic Register */
07441     __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL ; /*!< [0x25C] Frames Transmitted with Late Collision Statistic Register */
07442     __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL ; /*!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register */
07443     __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR ; /*!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register */
07444     __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR ; /*!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register */
07445     uint8_t _reserved15[4];
07446     __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC ; /*!< [0x270] Flow Control Pause Frames Transmitted Statistic Register */
07447     __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK ; /*!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register */
07448     uint8_t _reserved16[12];
07449     __I hw_enet_rmon_r_packets_t RMON_R_PACKETS ; /*!< [0x284] Rx Packet Count Statistic Register */
07450     __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT ; /*!< [0x288] Rx Broadcast Packets Statistic Register */
07451     __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT ; /*!< [0x28C] Rx Multicast Packets Statistic Register */
07452     __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN ; /*!< [0x290] Rx Packets with CRC/Align Error Statistic Register */
07453     __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE ; /*!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
07454     __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE ; /*!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
07455     __I hw_enet_rmon_r_frag_t RMON_R_FRAG ; /*!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
07456     __I hw_enet_rmon_r_jab_t RMON_R_JAB ;   /*!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
07457     uint8_t _reserved17[4];
07458     __I hw_enet_rmon_r_p64_t RMON_R_P64 ;   /*!< [0x2A8] Rx 64-Byte Packets Statistic Register */
07459     __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127 ; /*!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register */
07460     __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255 ; /*!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register */
07461     __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511 ; /*!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register */
07462     __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023 ; /*!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register */
07463     __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047 ; /*!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register */
07464     __I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048 ; /*!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register */
07465     __I hw_enet_rmon_r_octets_t RMON_R_OCTETS ; /*!< [0x2C4] Rx Octets Statistic Register */
07466     __I hw_enet_ieee_r_drop_t IEEE_R_DROP ; /*!< [0x2C8] Frames not Counted Correctly Statistic Register */
07467     __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK ; /*!< [0x2CC] Frames Received OK Statistic Register */
07468     __I hw_enet_ieee_r_crc_t IEEE_R_CRC ;   /*!< [0x2D0] Frames Received with CRC Error Statistic Register */
07469     __I hw_enet_ieee_r_align_t IEEE_R_ALIGN ; /*!< [0x2D4] Frames Received with Alignment Error Statistic Register */
07470     __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR ; /*!< [0x2D8] Receive FIFO Overflow Count Statistic Register */
07471     __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC ; /*!< [0x2DC] Flow Control Pause Frames Received Statistic Register */
07472     __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK ; /*!< [0x2E0] Octet Count for Frames Received without Error Statistic Register */
07473     uint8_t _reserved18[284];
07474     __IO hw_enet_atcr_t ATCR ;              /*!< [0x400] Adjustable Timer Control Register */
07475     __IO hw_enet_atvr_t ATVR ;              /*!< [0x404] Timer Value Register */
07476     __IO hw_enet_atoff_t ATOFF ;            /*!< [0x408] Timer Offset Register */
07477     __IO hw_enet_atper_t ATPER ;            /*!< [0x40C] Timer Period Register */
07478     __IO hw_enet_atcor_t ATCOR ;            /*!< [0x410] Timer Correction Register */
07479     __IO hw_enet_atinc_t ATINC ;            /*!< [0x414] Time-Stamping Clock Period Register */
07480     __I hw_enet_atstmp_t ATSTMP ;           /*!< [0x418] Timestamp of Last Transmitted Frame */
07481     uint8_t _reserved19[488];
07482     __IO hw_enet_tgsr_t TGSR ;              /*!< [0x604] Timer Global Status Register */
07483     struct {
07484         __IO hw_enet_tcsrn_t TCSRn ;        /*!< [0x608] Timer Control Status Register */
07485         __IO hw_enet_tccrn_t TCCRn ;        /*!< [0x60C] Timer Compare Capture Register */
07486     } CHANNEL[4];
07487 } hw_enet_t;
07488 #pragma pack()
07489 
07490 /*! @brief Macro to access all ENET registers. */
07491 /*! @param x ENET module instance base address. */
07492 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
07493  *     use the '&' operator, like <code>&HW_ENET(ENET_BASE)</code>. */
07494 #define HW_ENET(x)     (*(hw_enet_t *)(x))
07495 
07496 #endif /* __HW_ENET_REGISTERS_H__ */
07497 /* EOF */