MK64F12_dmamux.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_DMAMUX_REGISTERS_H__
00081 #define __HW_DMAMUX_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 DMAMUX
00088  *
00089  * DMA channel multiplexor
00090  *
00091  * Registers defined in this header file:
00092  * - HW_DMAMUX_CHCFGn - Channel Configuration register
00093  *
00094  * - hw_dmamux_t - Struct containing all module registers.
00095  */
00096 
00097 #define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
00098 
00099 /*******************************************************************************
00100  * HW_DMAMUX_CHCFGn - Channel Configuration register
00101  ******************************************************************************/
00102 
00103 /*!
00104  * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
00105  *
00106  * Reset value: 0x00U
00107  *
00108  * Each of the DMA channels can be independently enabled/disabled and associated
00109  * with one of the DMA slots (peripheral slots or always-on slots) in the
00110  * system. Setting multiple CHCFG registers with the same source value will result in
00111  * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
00112  * Before changing the trigger or source settings, a DMA channel must be disabled
00113  * via CHCFGn[ENBL].
00114  */
00115 typedef union _hw_dmamux_chcfgn
00116 {
00117     uint8_t U;
00118     struct _hw_dmamux_chcfgn_bitfields
00119     {
00120         uint8_t SOURCE : 6;            /*!< [5:0] DMA Channel Source (Slot) */
00121         uint8_t TRIG : 1;              /*!< [6] DMA Channel Trigger Enable */
00122         uint8_t ENBL : 1;              /*!< [7] DMA Channel Enable */
00123     } B;
00124 } hw_dmamux_chcfgn_t;
00125 
00126 /*!
00127  * @name Constants and macros for entire DMAMUX_CHCFGn register
00128  */
00129 /*@{*/
00130 #define HW_DMAMUX_CHCFGn_COUNT (16U)
00131 
00132 #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
00133 
00134 #define HW_DMAMUX_CHCFGn(x, n)   (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
00135 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
00136 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
00137 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) |  (v)))
00138 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
00139 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^  (v)))
00140 /*@}*/
00141 
00142 /*
00143  * Constants & macros for individual DMAMUX_CHCFGn bitfields
00144  */
00145 
00146 /*!
00147  * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
00148  *
00149  * Specifies which DMA source, if any, is routed to a particular DMA channel.
00150  * See your device's chip configuration details for information about the
00151  * peripherals and their slot numbers.
00152  */
00153 /*@{*/
00154 #define BP_DMAMUX_CHCFGn_SOURCE (0U)       /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
00155 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU)    /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
00156 #define BS_DMAMUX_CHCFGn_SOURCE (6U)       /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
00157 
00158 /*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
00159 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
00160 
00161 /*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
00162 #define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
00163 
00164 /*! @brief Set the SOURCE field to a new value. */
00165 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
00166 /*@}*/
00167 
00168 /*!
00169  * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
00170  *
00171  * Enables the periodic trigger capability for the triggered DMA channel.
00172  *
00173  * Values:
00174  * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
00175  *     DMA Channel will simply route the specified source to the DMA channel.
00176  *     (Normal mode)
00177  * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
00178  *     DMAMUX is in Periodic Trigger mode.
00179  */
00180 /*@{*/
00181 #define BP_DMAMUX_CHCFGn_TRIG (6U)         /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
00182 #define BM_DMAMUX_CHCFGn_TRIG (0x40U)      /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
00183 #define BS_DMAMUX_CHCFGn_TRIG (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
00184 
00185 /*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
00186 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
00187 
00188 /*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
00189 #define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
00190 
00191 /*! @brief Set the TRIG field to a new value. */
00192 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
00193 /*@}*/
00194 
00195 /*!
00196  * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
00197  *
00198  * Enables the DMA channel.
00199  *
00200  * Values:
00201  * - 0 - DMA channel is disabled. This mode is primarily used during
00202  *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
00203  *     should be used to disable or reconfigure a DMA channel.
00204  * - 1 - DMA channel is enabled
00205  */
00206 /*@{*/
00207 #define BP_DMAMUX_CHCFGn_ENBL (7U)         /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
00208 #define BM_DMAMUX_CHCFGn_ENBL (0x80U)      /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
00209 #define BS_DMAMUX_CHCFGn_ENBL (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
00210 
00211 /*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
00212 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
00213 
00214 /*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
00215 #define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
00216 
00217 /*! @brief Set the ENBL field to a new value. */
00218 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
00219 /*@}*/
00220 
00221 /*******************************************************************************
00222  * hw_dmamux_t - module struct
00223  ******************************************************************************/
00224 /*!
00225  * @brief All DMAMUX module registers.
00226  */
00227 #pragma pack(1)
00228 typedef struct _hw_dmamux
00229 {
00230     __IO hw_dmamux_chcfgn_t CHCFGn [16];    /*!< [0x0] Channel Configuration register */
00231 } hw_dmamux_t;
00232 #pragma pack()
00233 
00234 /*! @brief Macro to access all DMAMUX registers. */
00235 /*! @param x DMAMUX module instance base address. */
00236 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00237  *     use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
00238 #define HW_DMAMUX(x)   (*(hw_dmamux_t *)(x))
00239 
00240 #endif /* __HW_DMAMUX_REGISTERS_H__ */
00241 /* EOF */