MK64F12_dac.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_DAC_REGISTERS_H__
00081 #define __HW_DAC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 DAC
00088  *
00089  * 12-Bit Digital-to-Analog Converter
00090  *
00091  * Registers defined in this header file:
00092  * - HW_DAC_DATnL - DAC Data Low Register
00093  * - HW_DAC_DATnH - DAC Data High Register
00094  * - HW_DAC_SR - DAC Status Register
00095  * - HW_DAC_C0 - DAC Control Register
00096  * - HW_DAC_C1 - DAC Control Register 1
00097  * - HW_DAC_C2 - DAC Control Register 2
00098  *
00099  * - hw_dac_t - Struct containing all module registers.
00100  */
00101 
00102 #define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
00103 #define HW_DAC0 (0U) /*!< Instance number for DAC0. */
00104 #define HW_DAC1 (1U) /*!< Instance number for DAC1. */
00105 
00106 /*******************************************************************************
00107  * HW_DAC_DATnL - DAC Data Low Register
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
00112  *
00113  * Reset value: 0x00U
00114  */
00115 typedef union _hw_dac_datnl
00116 {
00117     uint8_t U;
00118     struct _hw_dac_datnl_bitfields
00119     {
00120         uint8_t DATA0 : 8;             /*!< [7:0]  */
00121     } B;
00122 } hw_dac_datnl_t;
00123 
00124 /*!
00125  * @name Constants and macros for entire DAC_DATnL register
00126  */
00127 /*@{*/
00128 #define HW_DAC_DATnL_COUNT (16U)
00129 
00130 #define HW_DAC_DATnL_ADDR(x, n)  ((x) + 0x0U + (0x2U * (n)))
00131 
00132 #define HW_DAC_DATnL(x, n)       (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
00133 #define HW_DAC_DATnL_RD(x, n)    (HW_DAC_DATnL(x, n).U)
00134 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
00135 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) |  (v)))
00136 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
00137 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^  (v)))
00138 /*@}*/
00139 
00140 /*
00141  * Constants & macros for individual DAC_DATnL bitfields
00142  */
00143 
00144 /*!
00145  * @name Register DAC_DATnL, field DATA0[7:0] (RW)
00146  *
00147  * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
00148  * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
00149  * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
00150  */
00151 /*@{*/
00152 #define BP_DAC_DATnL_DATA0   (0U)          /*!< Bit position for DAC_DATnL_DATA0. */
00153 #define BM_DAC_DATnL_DATA0   (0xFFU)       /*!< Bit mask for DAC_DATnL_DATA0. */
00154 #define BS_DAC_DATnL_DATA0   (8U)          /*!< Bit field size in bits for DAC_DATnL_DATA0. */
00155 
00156 /*! @brief Read current value of the DAC_DATnL_DATA0 field. */
00157 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
00158 
00159 /*! @brief Format value for bitfield DAC_DATnL_DATA0. */
00160 #define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
00161 
00162 /*! @brief Set the DATA0 field to a new value. */
00163 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
00164 /*@}*/
00165 /*******************************************************************************
00166  * HW_DAC_DATnH - DAC Data High Register
00167  ******************************************************************************/
00168 
00169 /*!
00170  * @brief HW_DAC_DATnH - DAC Data High Register (RW)
00171  *
00172  * Reset value: 0x00U
00173  */
00174 typedef union _hw_dac_datnh
00175 {
00176     uint8_t U;
00177     struct _hw_dac_datnh_bitfields
00178     {
00179         uint8_t DATA1 : 4;             /*!< [3:0]  */
00180         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
00181     } B;
00182 } hw_dac_datnh_t;
00183 
00184 /*!
00185  * @name Constants and macros for entire DAC_DATnH register
00186  */
00187 /*@{*/
00188 #define HW_DAC_DATnH_COUNT (16U)
00189 
00190 #define HW_DAC_DATnH_ADDR(x, n)  ((x) + 0x1U + (0x2U * (n)))
00191 
00192 #define HW_DAC_DATnH(x, n)       (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
00193 #define HW_DAC_DATnH_RD(x, n)    (HW_DAC_DATnH(x, n).U)
00194 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
00195 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) |  (v)))
00196 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
00197 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^  (v)))
00198 /*@}*/
00199 
00200 /*
00201  * Constants & macros for individual DAC_DATnH bitfields
00202  */
00203 
00204 /*!
00205  * @name Register DAC_DATnH, field DATA1[3:0] (RW)
00206  *
00207  * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
00208  * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
00209  * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
00210  */
00211 /*@{*/
00212 #define BP_DAC_DATnH_DATA1   (0U)          /*!< Bit position for DAC_DATnH_DATA1. */
00213 #define BM_DAC_DATnH_DATA1   (0x0FU)       /*!< Bit mask for DAC_DATnH_DATA1. */
00214 #define BS_DAC_DATnH_DATA1   (4U)          /*!< Bit field size in bits for DAC_DATnH_DATA1. */
00215 
00216 /*! @brief Read current value of the DAC_DATnH_DATA1 field. */
00217 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
00218 
00219 /*! @brief Format value for bitfield DAC_DATnH_DATA1. */
00220 #define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
00221 
00222 /*! @brief Set the DATA1 field to a new value. */
00223 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
00224 /*@}*/
00225 
00226 /*******************************************************************************
00227  * HW_DAC_SR - DAC Status Register
00228  ******************************************************************************/
00229 
00230 /*!
00231  * @brief HW_DAC_SR - DAC Status Register (RW)
00232  *
00233  * Reset value: 0x02U
00234  *
00235  * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
00236  * request is done. Writing 0 to a field clears it whereas writing 1 has no
00237  * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
00238  * The flags are set only when the data buffer status is changed. Do not use
00239  * 32/16-bit accesses to this register.
00240  */
00241 typedef union _hw_dac_sr
00242 {
00243     uint8_t U;
00244     struct _hw_dac_sr_bitfields
00245     {
00246         uint8_t DACBFRPBF : 1;         /*!< [0] DAC Buffer Read Pointer Bottom
00247                                         * Position Flag */
00248         uint8_t DACBFRPTF : 1;         /*!< [1] DAC Buffer Read Pointer Top Position
00249                                         * Flag */
00250         uint8_t DACBFWMF : 1;          /*!< [2] DAC Buffer Watermark Flag */
00251         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
00252     } B;
00253 } hw_dac_sr_t;
00254 
00255 /*!
00256  * @name Constants and macros for entire DAC_SR register
00257  */
00258 /*@{*/
00259 #define HW_DAC_SR_ADDR(x)        ((x) + 0x20U)
00260 
00261 #define HW_DAC_SR(x)             (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
00262 #define HW_DAC_SR_RD(x)          (HW_DAC_SR(x).U)
00263 #define HW_DAC_SR_WR(x, v)       (HW_DAC_SR(x).U = (v))
00264 #define HW_DAC_SR_SET(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) |  (v)))
00265 #define HW_DAC_SR_CLR(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
00266 #define HW_DAC_SR_TOG(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^  (v)))
00267 /*@}*/
00268 
00269 /*
00270  * Constants & macros for individual DAC_SR bitfields
00271  */
00272 
00273 /*!
00274  * @name Register DAC_SR, field DACBFRPBF[0] (RW)
00275  *
00276  * Values:
00277  * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
00278  * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
00279  */
00280 /*@{*/
00281 #define BP_DAC_SR_DACBFRPBF  (0U)          /*!< Bit position for DAC_SR_DACBFRPBF. */
00282 #define BM_DAC_SR_DACBFRPBF  (0x01U)       /*!< Bit mask for DAC_SR_DACBFRPBF. */
00283 #define BS_DAC_SR_DACBFRPBF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
00284 
00285 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
00286 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
00287 
00288 /*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
00289 #define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
00290 
00291 /*! @brief Set the DACBFRPBF field to a new value. */
00292 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
00293 /*@}*/
00294 
00295 /*!
00296  * @name Register DAC_SR, field DACBFRPTF[1] (RW)
00297  *
00298  * Values:
00299  * - 0 - The DAC buffer read pointer is not zero.
00300  * - 1 - The DAC buffer read pointer is zero.
00301  */
00302 /*@{*/
00303 #define BP_DAC_SR_DACBFRPTF  (1U)          /*!< Bit position for DAC_SR_DACBFRPTF. */
00304 #define BM_DAC_SR_DACBFRPTF  (0x02U)       /*!< Bit mask for DAC_SR_DACBFRPTF. */
00305 #define BS_DAC_SR_DACBFRPTF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
00306 
00307 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
00308 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
00309 
00310 /*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
00311 #define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
00312 
00313 /*! @brief Set the DACBFRPTF field to a new value. */
00314 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
00315 /*@}*/
00316 
00317 /*!
00318  * @name Register DAC_SR, field DACBFWMF[2] (RW)
00319  *
00320  * Values:
00321  * - 0 - The DAC buffer read pointer has not reached the watermark level.
00322  * - 1 - The DAC buffer read pointer has reached the watermark level.
00323  */
00324 /*@{*/
00325 #define BP_DAC_SR_DACBFWMF   (2U)          /*!< Bit position for DAC_SR_DACBFWMF. */
00326 #define BM_DAC_SR_DACBFWMF   (0x04U)       /*!< Bit mask for DAC_SR_DACBFWMF. */
00327 #define BS_DAC_SR_DACBFWMF   (1U)          /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
00328 
00329 /*! @brief Read current value of the DAC_SR_DACBFWMF field. */
00330 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
00331 
00332 /*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
00333 #define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
00334 
00335 /*! @brief Set the DACBFWMF field to a new value. */
00336 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
00337 /*@}*/
00338 
00339 /*******************************************************************************
00340  * HW_DAC_C0 - DAC Control Register
00341  ******************************************************************************/
00342 
00343 /*!
00344  * @brief HW_DAC_C0 - DAC Control Register (RW)
00345  *
00346  * Reset value: 0x00U
00347  *
00348  * Do not use 32- or 16-bit accesses to this register.
00349  */
00350 typedef union _hw_dac_c0
00351 {
00352     uint8_t U;
00353     struct _hw_dac_c0_bitfields
00354     {
00355         uint8_t DACBBIEN : 1;          /*!< [0] DAC Buffer Read Pointer Bottom Flag
00356                                         * Interrupt Enable */
00357         uint8_t DACBTIEN : 1;          /*!< [1] DAC Buffer Read Pointer Top Flag
00358                                         * Interrupt Enable */
00359         uint8_t DACBWIEN : 1;          /*!< [2] DAC Buffer Watermark Interrupt Enable
00360                                         * */
00361         uint8_t LPEN : 1;              /*!< [3] DAC Low Power Control */
00362         uint8_t DACSWTRG : 1;          /*!< [4] DAC Software Trigger */
00363         uint8_t DACTRGSEL : 1;         /*!< [5] DAC Trigger Select */
00364         uint8_t DACRFS : 1;            /*!< [6] DAC Reference Select */
00365         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
00366     } B;
00367 } hw_dac_c0_t;
00368 
00369 /*!
00370  * @name Constants and macros for entire DAC_C0 register
00371  */
00372 /*@{*/
00373 #define HW_DAC_C0_ADDR(x)        ((x) + 0x21U)
00374 
00375 #define HW_DAC_C0(x)             (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
00376 #define HW_DAC_C0_RD(x)          (HW_DAC_C0(x).U)
00377 #define HW_DAC_C0_WR(x, v)       (HW_DAC_C0(x).U = (v))
00378 #define HW_DAC_C0_SET(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) |  (v)))
00379 #define HW_DAC_C0_CLR(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
00380 #define HW_DAC_C0_TOG(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^  (v)))
00381 /*@}*/
00382 
00383 /*
00384  * Constants & macros for individual DAC_C0 bitfields
00385  */
00386 
00387 /*!
00388  * @name Register DAC_C0, field DACBBIEN[0] (RW)
00389  *
00390  * Values:
00391  * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
00392  * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
00393  */
00394 /*@{*/
00395 #define BP_DAC_C0_DACBBIEN   (0U)          /*!< Bit position for DAC_C0_DACBBIEN. */
00396 #define BM_DAC_C0_DACBBIEN   (0x01U)       /*!< Bit mask for DAC_C0_DACBBIEN. */
00397 #define BS_DAC_C0_DACBBIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
00398 
00399 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
00400 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
00401 
00402 /*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
00403 #define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
00404 
00405 /*! @brief Set the DACBBIEN field to a new value. */
00406 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
00407 /*@}*/
00408 
00409 /*!
00410  * @name Register DAC_C0, field DACBTIEN[1] (RW)
00411  *
00412  * Values:
00413  * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
00414  * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
00415  */
00416 /*@{*/
00417 #define BP_DAC_C0_DACBTIEN   (1U)          /*!< Bit position for DAC_C0_DACBTIEN. */
00418 #define BM_DAC_C0_DACBTIEN   (0x02U)       /*!< Bit mask for DAC_C0_DACBTIEN. */
00419 #define BS_DAC_C0_DACBTIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
00420 
00421 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
00422 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
00423 
00424 /*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
00425 #define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
00426 
00427 /*! @brief Set the DACBTIEN field to a new value. */
00428 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
00429 /*@}*/
00430 
00431 /*!
00432  * @name Register DAC_C0, field DACBWIEN[2] (RW)
00433  *
00434  * Values:
00435  * - 0 - The DAC buffer watermark interrupt is disabled.
00436  * - 1 - The DAC buffer watermark interrupt is enabled.
00437  */
00438 /*@{*/
00439 #define BP_DAC_C0_DACBWIEN   (2U)          /*!< Bit position for DAC_C0_DACBWIEN. */
00440 #define BM_DAC_C0_DACBWIEN   (0x04U)       /*!< Bit mask for DAC_C0_DACBWIEN. */
00441 #define BS_DAC_C0_DACBWIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
00442 
00443 /*! @brief Read current value of the DAC_C0_DACBWIEN field. */
00444 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
00445 
00446 /*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
00447 #define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
00448 
00449 /*! @brief Set the DACBWIEN field to a new value. */
00450 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
00451 /*@}*/
00452 
00453 /*!
00454  * @name Register DAC_C0, field LPEN[3] (RW)
00455  *
00456  * See the 12-bit DAC electrical characteristics of the device data sheet for
00457  * details on the impact of the modes below.
00458  *
00459  * Values:
00460  * - 0 - High-Power mode
00461  * - 1 - Low-Power mode
00462  */
00463 /*@{*/
00464 #define BP_DAC_C0_LPEN       (3U)          /*!< Bit position for DAC_C0_LPEN. */
00465 #define BM_DAC_C0_LPEN       (0x08U)       /*!< Bit mask for DAC_C0_LPEN. */
00466 #define BS_DAC_C0_LPEN       (1U)          /*!< Bit field size in bits for DAC_C0_LPEN. */
00467 
00468 /*! @brief Read current value of the DAC_C0_LPEN field. */
00469 #define BR_DAC_C0_LPEN(x)    (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
00470 
00471 /*! @brief Format value for bitfield DAC_C0_LPEN. */
00472 #define BF_DAC_C0_LPEN(v)    ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
00473 
00474 /*! @brief Set the LPEN field to a new value. */
00475 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
00476 /*@}*/
00477 
00478 /*!
00479  * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
00480  *
00481  * Active high. This is a write-only field, which always reads 0. If DAC
00482  * software trigger is selected and buffer is enabled, writing 1 to this field will
00483  * advance the buffer read pointer once.
00484  *
00485  * Values:
00486  * - 0 - The DAC soft trigger is not valid.
00487  * - 1 - The DAC soft trigger is valid.
00488  */
00489 /*@{*/
00490 #define BP_DAC_C0_DACSWTRG   (4U)          /*!< Bit position for DAC_C0_DACSWTRG. */
00491 #define BM_DAC_C0_DACSWTRG   (0x10U)       /*!< Bit mask for DAC_C0_DACSWTRG. */
00492 #define BS_DAC_C0_DACSWTRG   (1U)          /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
00493 
00494 /*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
00495 #define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
00496 
00497 /*! @brief Set the DACSWTRG field to a new value. */
00498 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
00499 /*@}*/
00500 
00501 /*!
00502  * @name Register DAC_C0, field DACTRGSEL[5] (RW)
00503  *
00504  * Values:
00505  * - 0 - The DAC hardware trigger is selected.
00506  * - 1 - The DAC software trigger is selected.
00507  */
00508 /*@{*/
00509 #define BP_DAC_C0_DACTRGSEL  (5U)          /*!< Bit position for DAC_C0_DACTRGSEL. */
00510 #define BM_DAC_C0_DACTRGSEL  (0x20U)       /*!< Bit mask for DAC_C0_DACTRGSEL. */
00511 #define BS_DAC_C0_DACTRGSEL  (1U)          /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
00512 
00513 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
00514 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
00515 
00516 /*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
00517 #define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
00518 
00519 /*! @brief Set the DACTRGSEL field to a new value. */
00520 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
00521 /*@}*/
00522 
00523 /*!
00524  * @name Register DAC_C0, field DACRFS[6] (RW)
00525  *
00526  * Values:
00527  * - 0 - The DAC selects DACREF_1 as the reference voltage.
00528  * - 1 - The DAC selects DACREF_2 as the reference voltage.
00529  */
00530 /*@{*/
00531 #define BP_DAC_C0_DACRFS     (6U)          /*!< Bit position for DAC_C0_DACRFS. */
00532 #define BM_DAC_C0_DACRFS     (0x40U)       /*!< Bit mask for DAC_C0_DACRFS. */
00533 #define BS_DAC_C0_DACRFS     (1U)          /*!< Bit field size in bits for DAC_C0_DACRFS. */
00534 
00535 /*! @brief Read current value of the DAC_C0_DACRFS field. */
00536 #define BR_DAC_C0_DACRFS(x)  (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
00537 
00538 /*! @brief Format value for bitfield DAC_C0_DACRFS. */
00539 #define BF_DAC_C0_DACRFS(v)  ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
00540 
00541 /*! @brief Set the DACRFS field to a new value. */
00542 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
00543 /*@}*/
00544 
00545 /*!
00546  * @name Register DAC_C0, field DACEN[7] (RW)
00547  *
00548  * Starts the Programmable Reference Generator operation.
00549  *
00550  * Values:
00551  * - 0 - The DAC system is disabled.
00552  * - 1 - The DAC system is enabled.
00553  */
00554 /*@{*/
00555 #define BP_DAC_C0_DACEN      (7U)          /*!< Bit position for DAC_C0_DACEN. */
00556 #define BM_DAC_C0_DACEN      (0x80U)       /*!< Bit mask for DAC_C0_DACEN. */
00557 #define BS_DAC_C0_DACEN      (1U)          /*!< Bit field size in bits for DAC_C0_DACEN. */
00558 
00559 /*! @brief Read current value of the DAC_C0_DACEN field. */
00560 #define BR_DAC_C0_DACEN(x)   (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
00561 
00562 /*! @brief Format value for bitfield DAC_C0_DACEN. */
00563 #define BF_DAC_C0_DACEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
00564 
00565 /*! @brief Set the DACEN field to a new value. */
00566 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
00567 /*@}*/
00568 
00569 /*******************************************************************************
00570  * HW_DAC_C1 - DAC Control Register 1
00571  ******************************************************************************/
00572 
00573 /*!
00574  * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
00575  *
00576  * Reset value: 0x00U
00577  *
00578  * Do not use 32- or 16-bit accesses to this register.
00579  */
00580 typedef union _hw_dac_c1
00581 {
00582     uint8_t U;
00583     struct _hw_dac_c1_bitfields
00584     {
00585         uint8_t DACBFEN : 1;           /*!< [0] DAC Buffer Enable */
00586         uint8_t DACBFMD : 2;           /*!< [2:1] DAC Buffer Work Mode Select */
00587         uint8_t DACBFWM : 2;           /*!< [4:3] DAC Buffer Watermark Select */
00588         uint8_t RESERVED0 : 2;         /*!< [6:5]  */
00589         uint8_t DMAEN : 1;             /*!< [7] DMA Enable Select */
00590     } B;
00591 } hw_dac_c1_t;
00592 
00593 /*!
00594  * @name Constants and macros for entire DAC_C1 register
00595  */
00596 /*@{*/
00597 #define HW_DAC_C1_ADDR(x)        ((x) + 0x22U)
00598 
00599 #define HW_DAC_C1(x)             (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
00600 #define HW_DAC_C1_RD(x)          (HW_DAC_C1(x).U)
00601 #define HW_DAC_C1_WR(x, v)       (HW_DAC_C1(x).U = (v))
00602 #define HW_DAC_C1_SET(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) |  (v)))
00603 #define HW_DAC_C1_CLR(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
00604 #define HW_DAC_C1_TOG(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^  (v)))
00605 /*@}*/
00606 
00607 /*
00608  * Constants & macros for individual DAC_C1 bitfields
00609  */
00610 
00611 /*!
00612  * @name Register DAC_C1, field DACBFEN[0] (RW)
00613  *
00614  * Values:
00615  * - 0 - Buffer read pointer is disabled. The converted data is always the first
00616  *     word of the buffer.
00617  * - 1 - Buffer read pointer is enabled. The converted data is the word that the
00618  *     read pointer points to. It means converted data can be from any word of
00619  *     the buffer.
00620  */
00621 /*@{*/
00622 #define BP_DAC_C1_DACBFEN    (0U)          /*!< Bit position for DAC_C1_DACBFEN. */
00623 #define BM_DAC_C1_DACBFEN    (0x01U)       /*!< Bit mask for DAC_C1_DACBFEN. */
00624 #define BS_DAC_C1_DACBFEN    (1U)          /*!< Bit field size in bits for DAC_C1_DACBFEN. */
00625 
00626 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
00627 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
00628 
00629 /*! @brief Format value for bitfield DAC_C1_DACBFEN. */
00630 #define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
00631 
00632 /*! @brief Set the DACBFEN field to a new value. */
00633 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
00634 /*@}*/
00635 
00636 /*!
00637  * @name Register DAC_C1, field DACBFMD[2:1] (RW)
00638  *
00639  * Values:
00640  * - 00 - Normal mode
00641  * - 01 - Swing mode
00642  * - 10 - One-Time Scan mode
00643  * - 11 - Reserved
00644  */
00645 /*@{*/
00646 #define BP_DAC_C1_DACBFMD    (1U)          /*!< Bit position for DAC_C1_DACBFMD. */
00647 #define BM_DAC_C1_DACBFMD    (0x06U)       /*!< Bit mask for DAC_C1_DACBFMD. */
00648 #define BS_DAC_C1_DACBFMD    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFMD. */
00649 
00650 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
00651 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
00652 
00653 /*! @brief Format value for bitfield DAC_C1_DACBFMD. */
00654 #define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
00655 
00656 /*! @brief Set the DACBFMD field to a new value. */
00657 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
00658 /*@}*/
00659 
00660 /*!
00661  * @name Register DAC_C1, field DACBFWM[4:3] (RW)
00662  *
00663  * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
00664  * the word defined by this field, which is 1-4 words away from the upper limit
00665  * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
00666  * watermark interrupt.
00667  *
00668  * Values:
00669  * - 00 - 1 word
00670  * - 01 - 2 words
00671  * - 10 - 3 words
00672  * - 11 - 4 words
00673  */
00674 /*@{*/
00675 #define BP_DAC_C1_DACBFWM    (3U)          /*!< Bit position for DAC_C1_DACBFWM. */
00676 #define BM_DAC_C1_DACBFWM    (0x18U)       /*!< Bit mask for DAC_C1_DACBFWM. */
00677 #define BS_DAC_C1_DACBFWM    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFWM. */
00678 
00679 /*! @brief Read current value of the DAC_C1_DACBFWM field. */
00680 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
00681 
00682 /*! @brief Format value for bitfield DAC_C1_DACBFWM. */
00683 #define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
00684 
00685 /*! @brief Set the DACBFWM field to a new value. */
00686 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
00687 /*@}*/
00688 
00689 /*!
00690  * @name Register DAC_C1, field DMAEN[7] (RW)
00691  *
00692  * Values:
00693  * - 0 - DMA is disabled.
00694  * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
00695  *     by original interrupts. The interrupts will not be presented on this
00696  *     module at the same time.
00697  */
00698 /*@{*/
00699 #define BP_DAC_C1_DMAEN      (7U)          /*!< Bit position for DAC_C1_DMAEN. */
00700 #define BM_DAC_C1_DMAEN      (0x80U)       /*!< Bit mask for DAC_C1_DMAEN. */
00701 #define BS_DAC_C1_DMAEN      (1U)          /*!< Bit field size in bits for DAC_C1_DMAEN. */
00702 
00703 /*! @brief Read current value of the DAC_C1_DMAEN field. */
00704 #define BR_DAC_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
00705 
00706 /*! @brief Format value for bitfield DAC_C1_DMAEN. */
00707 #define BF_DAC_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
00708 
00709 /*! @brief Set the DMAEN field to a new value. */
00710 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
00711 /*@}*/
00712 
00713 /*******************************************************************************
00714  * HW_DAC_C2 - DAC Control Register 2
00715  ******************************************************************************/
00716 
00717 /*!
00718  * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
00719  *
00720  * Reset value: 0x0FU
00721  */
00722 typedef union _hw_dac_c2
00723 {
00724     uint8_t U;
00725     struct _hw_dac_c2_bitfields
00726     {
00727         uint8_t DACBFUP : 4;           /*!< [3:0] DAC Buffer Upper Limit */
00728         uint8_t DACBFRP : 4;           /*!< [7:4] DAC Buffer Read Pointer */
00729     } B;
00730 } hw_dac_c2_t;
00731 
00732 /*!
00733  * @name Constants and macros for entire DAC_C2 register
00734  */
00735 /*@{*/
00736 #define HW_DAC_C2_ADDR(x)        ((x) + 0x23U)
00737 
00738 #define HW_DAC_C2(x)             (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
00739 #define HW_DAC_C2_RD(x)          (HW_DAC_C2(x).U)
00740 #define HW_DAC_C2_WR(x, v)       (HW_DAC_C2(x).U = (v))
00741 #define HW_DAC_C2_SET(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) |  (v)))
00742 #define HW_DAC_C2_CLR(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
00743 #define HW_DAC_C2_TOG(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^  (v)))
00744 /*@}*/
00745 
00746 /*
00747  * Constants & macros for individual DAC_C2 bitfields
00748  */
00749 
00750 /*!
00751  * @name Register DAC_C2, field DACBFUP[3:0] (RW)
00752  *
00753  * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
00754  * exceed it.
00755  */
00756 /*@{*/
00757 #define BP_DAC_C2_DACBFUP    (0U)          /*!< Bit position for DAC_C2_DACBFUP. */
00758 #define BM_DAC_C2_DACBFUP    (0x0FU)       /*!< Bit mask for DAC_C2_DACBFUP. */
00759 #define BS_DAC_C2_DACBFUP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFUP. */
00760 
00761 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
00762 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
00763 
00764 /*! @brief Format value for bitfield DAC_C2_DACBFUP. */
00765 #define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
00766 
00767 /*! @brief Set the DACBFUP field to a new value. */
00768 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
00769 /*@}*/
00770 
00771 /*!
00772  * @name Register DAC_C2, field DACBFRP[7:4] (RW)
00773  *
00774  * Keeps the current value of the buffer read pointer.
00775  */
00776 /*@{*/
00777 #define BP_DAC_C2_DACBFRP    (4U)          /*!< Bit position for DAC_C2_DACBFRP. */
00778 #define BM_DAC_C2_DACBFRP    (0xF0U)       /*!< Bit mask for DAC_C2_DACBFRP. */
00779 #define BS_DAC_C2_DACBFRP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFRP. */
00780 
00781 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
00782 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
00783 
00784 /*! @brief Format value for bitfield DAC_C2_DACBFRP. */
00785 #define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
00786 
00787 /*! @brief Set the DACBFRP field to a new value. */
00788 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
00789 /*@}*/
00790 
00791 /*******************************************************************************
00792  * hw_dac_t - module struct
00793  ******************************************************************************/
00794 /*!
00795  * @brief All DAC module registers.
00796  */
00797 #pragma pack(1)
00798 typedef struct _hw_dac
00799 {
00800     struct {
00801         __IO hw_dac_datnl_t DATnL ;         /*!< [0x0] DAC Data Low Register */
00802         __IO hw_dac_datnh_t DATnH ;         /*!< [0x1] DAC Data High Register */
00803     } DAT[16];
00804     __IO hw_dac_sr_t SR ;                   /*!< [0x20] DAC Status Register */
00805     __IO hw_dac_c0_t C0 ;                   /*!< [0x21] DAC Control Register */
00806     __IO hw_dac_c1_t C1 ;                   /*!< [0x22] DAC Control Register 1 */
00807     __IO hw_dac_c2_t C2 ;                   /*!< [0x23] DAC Control Register 2 */
00808 } hw_dac_t;
00809 #pragma pack()
00810 
00811 /*! @brief Macro to access all DAC registers. */
00812 /*! @param x DAC module instance base address. */
00813 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00814  *     use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
00815 #define HW_DAC(x)      (*(hw_dac_t *)(x))
00816 
00817 #endif /* __HW_DAC_REGISTERS_H__ */
00818 /* EOF */