MK64F12_cmp.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_CMP_REGISTERS_H__
00081 #define __HW_CMP_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 CMP
00088  *
00089  * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
00090  *
00091  * Registers defined in this header file:
00092  * - HW_CMP_CR0 - CMP Control Register 0
00093  * - HW_CMP_CR1 - CMP Control Register 1
00094  * - HW_CMP_FPR - CMP Filter Period Register
00095  * - HW_CMP_SCR - CMP Status and Control Register
00096  * - HW_CMP_DACCR - DAC Control Register
00097  * - HW_CMP_MUXCR - MUX Control Register
00098  *
00099  * - hw_cmp_t - Struct containing all module registers.
00100  */
00101 
00102 #define HW_CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
00103 #define HW_CMP0 (0U) /*!< Instance number for CMP0. */
00104 #define HW_CMP1 (1U) /*!< Instance number for CMP1. */
00105 #define HW_CMP2 (2U) /*!< Instance number for CMP2. */
00106 
00107 /*******************************************************************************
00108  * HW_CMP_CR0 - CMP Control Register 0
00109  ******************************************************************************/
00110 
00111 /*!
00112  * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
00113  *
00114  * Reset value: 0x00U
00115  */
00116 typedef union _hw_cmp_cr0
00117 {
00118     uint8_t U;
00119     struct _hw_cmp_cr0_bitfields
00120     {
00121         uint8_t HYSTCTR : 2;           /*!< [1:0] Comparator hard block hysteresis
00122                                         * control */
00123         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
00124         uint8_t FILTER_CNT : 3;        /*!< [6:4] Filter Sample Count */
00125         uint8_t RESERVED1 : 1;         /*!< [7]  */
00126     } B;
00127 } hw_cmp_cr0_t;
00128 
00129 /*!
00130  * @name Constants and macros for entire CMP_CR0 register
00131  */
00132 /*@{*/
00133 #define HW_CMP_CR0_ADDR(x)       ((x) + 0x0U)
00134 
00135 #define HW_CMP_CR0(x)            (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
00136 #define HW_CMP_CR0_RD(x)         (HW_CMP_CR0(x).U)
00137 #define HW_CMP_CR0_WR(x, v)      (HW_CMP_CR0(x).U = (v))
00138 #define HW_CMP_CR0_SET(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) |  (v)))
00139 #define HW_CMP_CR0_CLR(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
00140 #define HW_CMP_CR0_TOG(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^  (v)))
00141 /*@}*/
00142 
00143 /*
00144  * Constants & macros for individual CMP_CR0 bitfields
00145  */
00146 
00147 /*!
00148  * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
00149  *
00150  * Defines the programmable hysteresis level. The hysteresis values associated
00151  * with each level are device-specific. See the Data Sheet of the device for the
00152  * exact values.
00153  *
00154  * Values:
00155  * - 00 - Level 0
00156  * - 01 - Level 1
00157  * - 10 - Level 2
00158  * - 11 - Level 3
00159  */
00160 /*@{*/
00161 #define BP_CMP_CR0_HYSTCTR   (0U)          /*!< Bit position for CMP_CR0_HYSTCTR. */
00162 #define BM_CMP_CR0_HYSTCTR   (0x03U)       /*!< Bit mask for CMP_CR0_HYSTCTR. */
00163 #define BS_CMP_CR0_HYSTCTR   (2U)          /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
00164 
00165 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
00166 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
00167 
00168 /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
00169 #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
00170 
00171 /*! @brief Set the HYSTCTR field to a new value. */
00172 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
00173 /*@}*/
00174 
00175 /*!
00176  * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
00177  *
00178  * Represents the number of consecutive samples that must agree prior to the
00179  * comparator ouput filter accepting a new output state. For information regarding
00180  * filter programming and latency, see the Functional descriptionThe CMP module
00181  * can be used to compare two analog input voltages applied to INP and INM. .
00182  *
00183  * Values:
00184  * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
00185  *     legal state, and is not recommended. If SE = 0, COUT = COUTA.
00186  * - 001 - One sample must agree. The comparator output is simply sampled.
00187  * - 010 - 2 consecutive samples must agree.
00188  * - 011 - 3 consecutive samples must agree.
00189  * - 100 - 4 consecutive samples must agree.
00190  * - 101 - 5 consecutive samples must agree.
00191  * - 110 - 6 consecutive samples must agree.
00192  * - 111 - 7 consecutive samples must agree.
00193  */
00194 /*@{*/
00195 #define BP_CMP_CR0_FILTER_CNT (4U)         /*!< Bit position for CMP_CR0_FILTER_CNT. */
00196 #define BM_CMP_CR0_FILTER_CNT (0x70U)      /*!< Bit mask for CMP_CR0_FILTER_CNT. */
00197 #define BS_CMP_CR0_FILTER_CNT (3U)         /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
00198 
00199 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
00200 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
00201 
00202 /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
00203 #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
00204 
00205 /*! @brief Set the FILTER_CNT field to a new value. */
00206 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
00207 /*@}*/
00208 
00209 /*******************************************************************************
00210  * HW_CMP_CR1 - CMP Control Register 1
00211  ******************************************************************************/
00212 
00213 /*!
00214  * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
00215  *
00216  * Reset value: 0x00U
00217  */
00218 typedef union _hw_cmp_cr1
00219 {
00220     uint8_t U;
00221     struct _hw_cmp_cr1_bitfields
00222     {
00223         uint8_t EN : 1;                /*!< [0] Comparator Module Enable */
00224         uint8_t OPE : 1;               /*!< [1] Comparator Output Pin Enable */
00225         uint8_t COS : 1;               /*!< [2] Comparator Output Select */
00226         uint8_t INV : 1;               /*!< [3] Comparator INVERT */
00227         uint8_t PMODE : 1;             /*!< [4] Power Mode Select */
00228         uint8_t RESERVED0 : 1;         /*!< [5]  */
00229         uint8_t WE : 1;                /*!< [6] Windowing Enable */
00230         uint8_t SE : 1;                /*!< [7] Sample Enable */
00231     } B;
00232 } hw_cmp_cr1_t;
00233 
00234 /*!
00235  * @name Constants and macros for entire CMP_CR1 register
00236  */
00237 /*@{*/
00238 #define HW_CMP_CR1_ADDR(x)       ((x) + 0x1U)
00239 
00240 #define HW_CMP_CR1(x)            (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
00241 #define HW_CMP_CR1_RD(x)         (HW_CMP_CR1(x).U)
00242 #define HW_CMP_CR1_WR(x, v)      (HW_CMP_CR1(x).U = (v))
00243 #define HW_CMP_CR1_SET(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) |  (v)))
00244 #define HW_CMP_CR1_CLR(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
00245 #define HW_CMP_CR1_TOG(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^  (v)))
00246 /*@}*/
00247 
00248 /*
00249  * Constants & macros for individual CMP_CR1 bitfields
00250  */
00251 
00252 /*!
00253  * @name Register CMP_CR1, field EN[0] (RW)
00254  *
00255  * Enables the Analog Comparator module. When the module is not enabled, it
00256  * remains in the off state, and consumes no power. When the user selects the same
00257  * input from analog mux to the positive and negative port, the comparator is
00258  * disabled automatically.
00259  *
00260  * Values:
00261  * - 0 - Analog Comparator is disabled.
00262  * - 1 - Analog Comparator is enabled.
00263  */
00264 /*@{*/
00265 #define BP_CMP_CR1_EN        (0U)          /*!< Bit position for CMP_CR1_EN. */
00266 #define BM_CMP_CR1_EN        (0x01U)       /*!< Bit mask for CMP_CR1_EN. */
00267 #define BS_CMP_CR1_EN        (1U)          /*!< Bit field size in bits for CMP_CR1_EN. */
00268 
00269 /*! @brief Read current value of the CMP_CR1_EN field. */
00270 #define BR_CMP_CR1_EN(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
00271 
00272 /*! @brief Format value for bitfield CMP_CR1_EN. */
00273 #define BF_CMP_CR1_EN(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
00274 
00275 /*! @brief Set the EN field to a new value. */
00276 #define BW_CMP_CR1_EN(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
00277 /*@}*/
00278 
00279 /*!
00280  * @name Register CMP_CR1, field OPE[1] (RW)
00281  *
00282  * Values:
00283  * - 0 - CMPO is not available on the associated CMPO output pin. If the
00284  *     comparator does not own the pin, this field has no effect.
00285  * - 1 - CMPO is available on the associated CMPO output pin. The comparator
00286  *     output (CMPO) is driven out on the associated CMPO output pin if the
00287  *     comparator owns the pin. If the comparator does not own the field, this bit has no
00288  *     effect.
00289  */
00290 /*@{*/
00291 #define BP_CMP_CR1_OPE       (1U)          /*!< Bit position for CMP_CR1_OPE. */
00292 #define BM_CMP_CR1_OPE       (0x02U)       /*!< Bit mask for CMP_CR1_OPE. */
00293 #define BS_CMP_CR1_OPE       (1U)          /*!< Bit field size in bits for CMP_CR1_OPE. */
00294 
00295 /*! @brief Read current value of the CMP_CR1_OPE field. */
00296 #define BR_CMP_CR1_OPE(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
00297 
00298 /*! @brief Format value for bitfield CMP_CR1_OPE. */
00299 #define BF_CMP_CR1_OPE(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
00300 
00301 /*! @brief Set the OPE field to a new value. */
00302 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
00303 /*@}*/
00304 
00305 /*!
00306  * @name Register CMP_CR1, field COS[2] (RW)
00307  *
00308  * Values:
00309  * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
00310  * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
00311  */
00312 /*@{*/
00313 #define BP_CMP_CR1_COS       (2U)          /*!< Bit position for CMP_CR1_COS. */
00314 #define BM_CMP_CR1_COS       (0x04U)       /*!< Bit mask for CMP_CR1_COS. */
00315 #define BS_CMP_CR1_COS       (1U)          /*!< Bit field size in bits for CMP_CR1_COS. */
00316 
00317 /*! @brief Read current value of the CMP_CR1_COS field. */
00318 #define BR_CMP_CR1_COS(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
00319 
00320 /*! @brief Format value for bitfield CMP_CR1_COS. */
00321 #define BF_CMP_CR1_COS(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
00322 
00323 /*! @brief Set the COS field to a new value. */
00324 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
00325 /*@}*/
00326 
00327 /*!
00328  * @name Register CMP_CR1, field INV[3] (RW)
00329  *
00330  * Allows selection of the polarity of the analog comparator function. It is
00331  * also driven to the COUT output, on both the device pin and as SCR[COUT], when
00332  * OPE=0.
00333  *
00334  * Values:
00335  * - 0 - Does not invert the comparator output.
00336  * - 1 - Inverts the comparator output.
00337  */
00338 /*@{*/
00339 #define BP_CMP_CR1_INV       (3U)          /*!< Bit position for CMP_CR1_INV. */
00340 #define BM_CMP_CR1_INV       (0x08U)       /*!< Bit mask for CMP_CR1_INV. */
00341 #define BS_CMP_CR1_INV       (1U)          /*!< Bit field size in bits for CMP_CR1_INV. */
00342 
00343 /*! @brief Read current value of the CMP_CR1_INV field. */
00344 #define BR_CMP_CR1_INV(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
00345 
00346 /*! @brief Format value for bitfield CMP_CR1_INV. */
00347 #define BF_CMP_CR1_INV(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
00348 
00349 /*! @brief Set the INV field to a new value. */
00350 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
00351 /*@}*/
00352 
00353 /*!
00354  * @name Register CMP_CR1, field PMODE[4] (RW)
00355  *
00356  * See the electrical specifications table in the device Data Sheet for details.
00357  *
00358  * Values:
00359  * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
00360  *     output propagation delay and lower current consumption.
00361  * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
00362  *     output propagation delay and higher current consumption.
00363  */
00364 /*@{*/
00365 #define BP_CMP_CR1_PMODE     (4U)          /*!< Bit position for CMP_CR1_PMODE. */
00366 #define BM_CMP_CR1_PMODE     (0x10U)       /*!< Bit mask for CMP_CR1_PMODE. */
00367 #define BS_CMP_CR1_PMODE     (1U)          /*!< Bit field size in bits for CMP_CR1_PMODE. */
00368 
00369 /*! @brief Read current value of the CMP_CR1_PMODE field. */
00370 #define BR_CMP_CR1_PMODE(x)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
00371 
00372 /*! @brief Format value for bitfield CMP_CR1_PMODE. */
00373 #define BF_CMP_CR1_PMODE(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
00374 
00375 /*! @brief Set the PMODE field to a new value. */
00376 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
00377 /*@}*/
00378 
00379 /*!
00380  * @name Register CMP_CR1, field WE[6] (RW)
00381  *
00382  * At any given time, either SE or WE can be set. If a write to this register
00383  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
00384  * 1s to both field locations because this "11" case is reserved and may change in
00385  * future implementations.
00386  *
00387  * Values:
00388  * - 0 - Windowing mode is not selected.
00389  * - 1 - Windowing mode is selected.
00390  */
00391 /*@{*/
00392 #define BP_CMP_CR1_WE        (6U)          /*!< Bit position for CMP_CR1_WE. */
00393 #define BM_CMP_CR1_WE        (0x40U)       /*!< Bit mask for CMP_CR1_WE. */
00394 #define BS_CMP_CR1_WE        (1U)          /*!< Bit field size in bits for CMP_CR1_WE. */
00395 
00396 /*! @brief Read current value of the CMP_CR1_WE field. */
00397 #define BR_CMP_CR1_WE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
00398 
00399 /*! @brief Format value for bitfield CMP_CR1_WE. */
00400 #define BF_CMP_CR1_WE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
00401 
00402 /*! @brief Set the WE field to a new value. */
00403 #define BW_CMP_CR1_WE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
00404 /*@}*/
00405 
00406 /*!
00407  * @name Register CMP_CR1, field SE[7] (RW)
00408  *
00409  * At any given time, either SE or WE can be set. If a write to this register
00410  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
00411  * 1s to both field locations because this "11" case is reserved and may change in
00412  * future implementations.
00413  *
00414  * Values:
00415  * - 0 - Sampling mode is not selected.
00416  * - 1 - Sampling mode is selected.
00417  */
00418 /*@{*/
00419 #define BP_CMP_CR1_SE        (7U)          /*!< Bit position for CMP_CR1_SE. */
00420 #define BM_CMP_CR1_SE        (0x80U)       /*!< Bit mask for CMP_CR1_SE. */
00421 #define BS_CMP_CR1_SE        (1U)          /*!< Bit field size in bits for CMP_CR1_SE. */
00422 
00423 /*! @brief Read current value of the CMP_CR1_SE field. */
00424 #define BR_CMP_CR1_SE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
00425 
00426 /*! @brief Format value for bitfield CMP_CR1_SE. */
00427 #define BF_CMP_CR1_SE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
00428 
00429 /*! @brief Set the SE field to a new value. */
00430 #define BW_CMP_CR1_SE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
00431 /*@}*/
00432 
00433 /*******************************************************************************
00434  * HW_CMP_FPR - CMP Filter Period Register
00435  ******************************************************************************/
00436 
00437 /*!
00438  * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
00439  *
00440  * Reset value: 0x00U
00441  */
00442 typedef union _hw_cmp_fpr
00443 {
00444     uint8_t U;
00445     struct _hw_cmp_fpr_bitfields
00446     {
00447         uint8_t FILT_PER : 8;          /*!< [7:0] Filter Sample Period */
00448     } B;
00449 } hw_cmp_fpr_t;
00450 
00451 /*!
00452  * @name Constants and macros for entire CMP_FPR register
00453  */
00454 /*@{*/
00455 #define HW_CMP_FPR_ADDR(x)       ((x) + 0x2U)
00456 
00457 #define HW_CMP_FPR(x)            (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
00458 #define HW_CMP_FPR_RD(x)         (HW_CMP_FPR(x).U)
00459 #define HW_CMP_FPR_WR(x, v)      (HW_CMP_FPR(x).U = (v))
00460 #define HW_CMP_FPR_SET(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) |  (v)))
00461 #define HW_CMP_FPR_CLR(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
00462 #define HW_CMP_FPR_TOG(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^  (v)))
00463 /*@}*/
00464 
00465 /*
00466  * Constants & macros for individual CMP_FPR bitfields
00467  */
00468 
00469 /*!
00470  * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
00471  *
00472  * Specifies the sampling period, in bus clock cycles, of the comparator output
00473  * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
00474  * programming and latency details appear in the Functional descriptionThe CMP
00475  * module can be used to compare two analog input voltages applied to INP and INM. .
00476  * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
00477  * signal is used to determine the sampling period.
00478  */
00479 /*@{*/
00480 #define BP_CMP_FPR_FILT_PER  (0U)          /*!< Bit position for CMP_FPR_FILT_PER. */
00481 #define BM_CMP_FPR_FILT_PER  (0xFFU)       /*!< Bit mask for CMP_FPR_FILT_PER. */
00482 #define BS_CMP_FPR_FILT_PER  (8U)          /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
00483 
00484 /*! @brief Read current value of the CMP_FPR_FILT_PER field. */
00485 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
00486 
00487 /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
00488 #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
00489 
00490 /*! @brief Set the FILT_PER field to a new value. */
00491 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
00492 /*@}*/
00493 
00494 /*******************************************************************************
00495  * HW_CMP_SCR - CMP Status and Control Register
00496  ******************************************************************************/
00497 
00498 /*!
00499  * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
00500  *
00501  * Reset value: 0x00U
00502  */
00503 typedef union _hw_cmp_scr
00504 {
00505     uint8_t U;
00506     struct _hw_cmp_scr_bitfields
00507     {
00508         uint8_t COUT : 1;              /*!< [0] Analog Comparator Output */
00509         uint8_t CFF : 1;               /*!< [1] Analog Comparator Flag Falling */
00510         uint8_t CFR : 1;               /*!< [2] Analog Comparator Flag Rising */
00511         uint8_t IEF : 1;               /*!< [3] Comparator Interrupt Enable Falling */
00512         uint8_t IER : 1;               /*!< [4] Comparator Interrupt Enable Rising */
00513         uint8_t RESERVED0 : 1;         /*!< [5]  */
00514         uint8_t DMAEN : 1;             /*!< [6] DMA Enable Control */
00515         uint8_t RESERVED1 : 1;         /*!< [7]  */
00516     } B;
00517 } hw_cmp_scr_t;
00518 
00519 /*!
00520  * @name Constants and macros for entire CMP_SCR register
00521  */
00522 /*@{*/
00523 #define HW_CMP_SCR_ADDR(x)       ((x) + 0x3U)
00524 
00525 #define HW_CMP_SCR(x)            (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
00526 #define HW_CMP_SCR_RD(x)         (HW_CMP_SCR(x).U)
00527 #define HW_CMP_SCR_WR(x, v)      (HW_CMP_SCR(x).U = (v))
00528 #define HW_CMP_SCR_SET(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) |  (v)))
00529 #define HW_CMP_SCR_CLR(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
00530 #define HW_CMP_SCR_TOG(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^  (v)))
00531 /*@}*/
00532 
00533 /*
00534  * Constants & macros for individual CMP_SCR bitfields
00535  */
00536 
00537 /*!
00538  * @name Register CMP_SCR, field COUT[0] (RO)
00539  *
00540  * Returns the current value of the Analog Comparator output, when read. The
00541  * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
00542  * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
00543  */
00544 /*@{*/
00545 #define BP_CMP_SCR_COUT      (0U)          /*!< Bit position for CMP_SCR_COUT. */
00546 #define BM_CMP_SCR_COUT      (0x01U)       /*!< Bit mask for CMP_SCR_COUT. */
00547 #define BS_CMP_SCR_COUT      (1U)          /*!< Bit field size in bits for CMP_SCR_COUT. */
00548 
00549 /*! @brief Read current value of the CMP_SCR_COUT field. */
00550 #define BR_CMP_SCR_COUT(x)   (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
00551 /*@}*/
00552 
00553 /*!
00554  * @name Register CMP_SCR, field CFF[1] (W1C)
00555  *
00556  * Detects a falling-edge on COUT, when set, during normal operation. CFF is
00557  * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
00558  * sensitive .
00559  *
00560  * Values:
00561  * - 0 - Falling-edge on COUT has not been detected.
00562  * - 1 - Falling-edge on COUT has occurred.
00563  */
00564 /*@{*/
00565 #define BP_CMP_SCR_CFF       (1U)          /*!< Bit position for CMP_SCR_CFF. */
00566 #define BM_CMP_SCR_CFF       (0x02U)       /*!< Bit mask for CMP_SCR_CFF. */
00567 #define BS_CMP_SCR_CFF       (1U)          /*!< Bit field size in bits for CMP_SCR_CFF. */
00568 
00569 /*! @brief Read current value of the CMP_SCR_CFF field. */
00570 #define BR_CMP_SCR_CFF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
00571 
00572 /*! @brief Format value for bitfield CMP_SCR_CFF. */
00573 #define BF_CMP_SCR_CFF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
00574 
00575 /*! @brief Set the CFF field to a new value. */
00576 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
00577 /*@}*/
00578 
00579 /*!
00580  * @name Register CMP_SCR, field CFR[2] (W1C)
00581  *
00582  * Detects a rising-edge on COUT, when set, during normal operation. CFR is
00583  * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
00584  * sensitive .
00585  *
00586  * Values:
00587  * - 0 - Rising-edge on COUT has not been detected.
00588  * - 1 - Rising-edge on COUT has occurred.
00589  */
00590 /*@{*/
00591 #define BP_CMP_SCR_CFR       (2U)          /*!< Bit position for CMP_SCR_CFR. */
00592 #define BM_CMP_SCR_CFR       (0x04U)       /*!< Bit mask for CMP_SCR_CFR. */
00593 #define BS_CMP_SCR_CFR       (1U)          /*!< Bit field size in bits for CMP_SCR_CFR. */
00594 
00595 /*! @brief Read current value of the CMP_SCR_CFR field. */
00596 #define BR_CMP_SCR_CFR(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
00597 
00598 /*! @brief Format value for bitfield CMP_SCR_CFR. */
00599 #define BF_CMP_SCR_CFR(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
00600 
00601 /*! @brief Set the CFR field to a new value. */
00602 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
00603 /*@}*/
00604 
00605 /*!
00606  * @name Register CMP_SCR, field IEF[3] (RW)
00607  *
00608  * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
00609  * will be asserted when CFF is set.
00610  *
00611  * Values:
00612  * - 0 - Interrupt is disabled.
00613  * - 1 - Interrupt is enabled.
00614  */
00615 /*@{*/
00616 #define BP_CMP_SCR_IEF       (3U)          /*!< Bit position for CMP_SCR_IEF. */
00617 #define BM_CMP_SCR_IEF       (0x08U)       /*!< Bit mask for CMP_SCR_IEF. */
00618 #define BS_CMP_SCR_IEF       (1U)          /*!< Bit field size in bits for CMP_SCR_IEF. */
00619 
00620 /*! @brief Read current value of the CMP_SCR_IEF field. */
00621 #define BR_CMP_SCR_IEF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
00622 
00623 /*! @brief Format value for bitfield CMP_SCR_IEF. */
00624 #define BF_CMP_SCR_IEF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
00625 
00626 /*! @brief Set the IEF field to a new value. */
00627 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
00628 /*@}*/
00629 
00630 /*!
00631  * @name Register CMP_SCR, field IER[4] (RW)
00632  *
00633  * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
00634  * will be asserted when CFR is set.
00635  *
00636  * Values:
00637  * - 0 - Interrupt is disabled.
00638  * - 1 - Interrupt is enabled.
00639  */
00640 /*@{*/
00641 #define BP_CMP_SCR_IER       (4U)          /*!< Bit position for CMP_SCR_IER. */
00642 #define BM_CMP_SCR_IER       (0x10U)       /*!< Bit mask for CMP_SCR_IER. */
00643 #define BS_CMP_SCR_IER       (1U)          /*!< Bit field size in bits for CMP_SCR_IER. */
00644 
00645 /*! @brief Read current value of the CMP_SCR_IER field. */
00646 #define BR_CMP_SCR_IER(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
00647 
00648 /*! @brief Format value for bitfield CMP_SCR_IER. */
00649 #define BF_CMP_SCR_IER(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
00650 
00651 /*! @brief Set the IER field to a new value. */
00652 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
00653 /*@}*/
00654 
00655 /*!
00656  * @name Register CMP_SCR, field DMAEN[6] (RW)
00657  *
00658  * Enables the DMA transfer triggered from the CMP module. When this field is
00659  * set, a DMA request is asserted when CFR or CFF is set.
00660  *
00661  * Values:
00662  * - 0 - DMA is disabled.
00663  * - 1 - DMA is enabled.
00664  */
00665 /*@{*/
00666 #define BP_CMP_SCR_DMAEN     (6U)          /*!< Bit position for CMP_SCR_DMAEN. */
00667 #define BM_CMP_SCR_DMAEN     (0x40U)       /*!< Bit mask for CMP_SCR_DMAEN. */
00668 #define BS_CMP_SCR_DMAEN     (1U)          /*!< Bit field size in bits for CMP_SCR_DMAEN. */
00669 
00670 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
00671 #define BR_CMP_SCR_DMAEN(x)  (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
00672 
00673 /*! @brief Format value for bitfield CMP_SCR_DMAEN. */
00674 #define BF_CMP_SCR_DMAEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
00675 
00676 /*! @brief Set the DMAEN field to a new value. */
00677 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
00678 /*@}*/
00679 
00680 /*******************************************************************************
00681  * HW_CMP_DACCR - DAC Control Register
00682  ******************************************************************************/
00683 
00684 /*!
00685  * @brief HW_CMP_DACCR - DAC Control Register (RW)
00686  *
00687  * Reset value: 0x00U
00688  */
00689 typedef union _hw_cmp_daccr
00690 {
00691     uint8_t U;
00692     struct _hw_cmp_daccr_bitfields
00693     {
00694         uint8_t VOSEL : 6;             /*!< [5:0] DAC Output Voltage Select */
00695         uint8_t VRSEL : 1;             /*!< [6] Supply Voltage Reference Source Select */
00696         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
00697     } B;
00698 } hw_cmp_daccr_t;
00699 
00700 /*!
00701  * @name Constants and macros for entire CMP_DACCR register
00702  */
00703 /*@{*/
00704 #define HW_CMP_DACCR_ADDR(x)     ((x) + 0x4U)
00705 
00706 #define HW_CMP_DACCR(x)          (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
00707 #define HW_CMP_DACCR_RD(x)       (HW_CMP_DACCR(x).U)
00708 #define HW_CMP_DACCR_WR(x, v)    (HW_CMP_DACCR(x).U = (v))
00709 #define HW_CMP_DACCR_SET(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) |  (v)))
00710 #define HW_CMP_DACCR_CLR(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
00711 #define HW_CMP_DACCR_TOG(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^  (v)))
00712 /*@}*/
00713 
00714 /*
00715  * Constants & macros for individual CMP_DACCR bitfields
00716  */
00717 
00718 /*!
00719  * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
00720  *
00721  * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
00722  * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
00723  */
00724 /*@{*/
00725 #define BP_CMP_DACCR_VOSEL   (0U)          /*!< Bit position for CMP_DACCR_VOSEL. */
00726 #define BM_CMP_DACCR_VOSEL   (0x3FU)       /*!< Bit mask for CMP_DACCR_VOSEL. */
00727 #define BS_CMP_DACCR_VOSEL   (6U)          /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
00728 
00729 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
00730 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
00731 
00732 /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
00733 #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
00734 
00735 /*! @brief Set the VOSEL field to a new value. */
00736 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
00737 /*@}*/
00738 
00739 /*!
00740  * @name Register CMP_DACCR, field VRSEL[6] (RW)
00741  *
00742  * Values:
00743  * - 0 - V is selected as resistor ladder network supply reference V. in1 in
00744  * - 1 - V is selected as resistor ladder network supply reference V. in2 in
00745  */
00746 /*@{*/
00747 #define BP_CMP_DACCR_VRSEL   (6U)          /*!< Bit position for CMP_DACCR_VRSEL. */
00748 #define BM_CMP_DACCR_VRSEL   (0x40U)       /*!< Bit mask for CMP_DACCR_VRSEL. */
00749 #define BS_CMP_DACCR_VRSEL   (1U)          /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
00750 
00751 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
00752 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
00753 
00754 /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
00755 #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
00756 
00757 /*! @brief Set the VRSEL field to a new value. */
00758 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
00759 /*@}*/
00760 
00761 /*!
00762  * @name Register CMP_DACCR, field DACEN[7] (RW)
00763  *
00764  * Enables the DAC. When the DAC is disabled, it is powered down to conserve
00765  * power.
00766  *
00767  * Values:
00768  * - 0 - DAC is disabled.
00769  * - 1 - DAC is enabled.
00770  */
00771 /*@{*/
00772 #define BP_CMP_DACCR_DACEN   (7U)          /*!< Bit position for CMP_DACCR_DACEN. */
00773 #define BM_CMP_DACCR_DACEN   (0x80U)       /*!< Bit mask for CMP_DACCR_DACEN. */
00774 #define BS_CMP_DACCR_DACEN   (1U)          /*!< Bit field size in bits for CMP_DACCR_DACEN. */
00775 
00776 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
00777 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
00778 
00779 /*! @brief Format value for bitfield CMP_DACCR_DACEN. */
00780 #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
00781 
00782 /*! @brief Set the DACEN field to a new value. */
00783 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
00784 /*@}*/
00785 
00786 /*******************************************************************************
00787  * HW_CMP_MUXCR - MUX Control Register
00788  ******************************************************************************/
00789 
00790 /*!
00791  * @brief HW_CMP_MUXCR - MUX Control Register (RW)
00792  *
00793  * Reset value: 0x00U
00794  */
00795 typedef union _hw_cmp_muxcr
00796 {
00797     uint8_t U;
00798     struct _hw_cmp_muxcr_bitfields
00799     {
00800         uint8_t MSEL : 3;              /*!< [2:0] Minus Input Mux Control */
00801         uint8_t PSEL : 3;              /*!< [5:3] Plus Input Mux Control */
00802         uint8_t RESERVED0 : 1;         /*!< [6]  */
00803         uint8_t PSTM : 1;              /*!< [7] Pass Through Mode Enable */
00804     } B;
00805 } hw_cmp_muxcr_t;
00806 
00807 /*!
00808  * @name Constants and macros for entire CMP_MUXCR register
00809  */
00810 /*@{*/
00811 #define HW_CMP_MUXCR_ADDR(x)     ((x) + 0x5U)
00812 
00813 #define HW_CMP_MUXCR(x)          (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
00814 #define HW_CMP_MUXCR_RD(x)       (HW_CMP_MUXCR(x).U)
00815 #define HW_CMP_MUXCR_WR(x, v)    (HW_CMP_MUXCR(x).U = (v))
00816 #define HW_CMP_MUXCR_SET(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) |  (v)))
00817 #define HW_CMP_MUXCR_CLR(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
00818 #define HW_CMP_MUXCR_TOG(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^  (v)))
00819 /*@}*/
00820 
00821 /*
00822  * Constants & macros for individual CMP_MUXCR bitfields
00823  */
00824 
00825 /*!
00826  * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
00827  *
00828  * Determines which input is selected for the minus input of the comparator. For
00829  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
00830  * operation selects the same input for both muxes, the comparator automatically
00831  * shuts down to prevent itself from becoming a noise generator.
00832  *
00833  * Values:
00834  * - 000 - IN0
00835  * - 001 - IN1
00836  * - 010 - IN2
00837  * - 011 - IN3
00838  * - 100 - IN4
00839  * - 101 - IN5
00840  * - 110 - IN6
00841  * - 111 - IN7
00842  */
00843 /*@{*/
00844 #define BP_CMP_MUXCR_MSEL    (0U)          /*!< Bit position for CMP_MUXCR_MSEL. */
00845 #define BM_CMP_MUXCR_MSEL    (0x07U)       /*!< Bit mask for CMP_MUXCR_MSEL. */
00846 #define BS_CMP_MUXCR_MSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
00847 
00848 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
00849 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
00850 
00851 /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
00852 #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
00853 
00854 /*! @brief Set the MSEL field to a new value. */
00855 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
00856 /*@}*/
00857 
00858 /*!
00859  * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
00860  *
00861  * Determines which input is selected for the plus input of the comparator. For
00862  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
00863  * operation selects the same input for both muxes, the comparator automatically
00864  * shuts down to prevent itself from becoming a noise generator.
00865  *
00866  * Values:
00867  * - 000 - IN0
00868  * - 001 - IN1
00869  * - 010 - IN2
00870  * - 011 - IN3
00871  * - 100 - IN4
00872  * - 101 - IN5
00873  * - 110 - IN6
00874  * - 111 - IN7
00875  */
00876 /*@{*/
00877 #define BP_CMP_MUXCR_PSEL    (3U)          /*!< Bit position for CMP_MUXCR_PSEL. */
00878 #define BM_CMP_MUXCR_PSEL    (0x38U)       /*!< Bit mask for CMP_MUXCR_PSEL. */
00879 #define BS_CMP_MUXCR_PSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
00880 
00881 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
00882 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
00883 
00884 /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
00885 #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
00886 
00887 /*! @brief Set the PSEL field to a new value. */
00888 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
00889 /*@}*/
00890 
00891 /*!
00892  * @name Register CMP_MUXCR, field PSTM[7] (RW)
00893  *
00894  * This bit is used to enable to MUX pass through mode. Pass through mode is
00895  * always available but for some devices this feature must be always disabled due to
00896  * the lack of package pins.
00897  *
00898  * Values:
00899  * - 0 - Pass Through Mode is disabled.
00900  * - 1 - Pass Through Mode is enabled.
00901  */
00902 /*@{*/
00903 #define BP_CMP_MUXCR_PSTM    (7U)          /*!< Bit position for CMP_MUXCR_PSTM. */
00904 #define BM_CMP_MUXCR_PSTM    (0x80U)       /*!< Bit mask for CMP_MUXCR_PSTM. */
00905 #define BS_CMP_MUXCR_PSTM    (1U)          /*!< Bit field size in bits for CMP_MUXCR_PSTM. */
00906 
00907 /*! @brief Read current value of the CMP_MUXCR_PSTM field. */
00908 #define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
00909 
00910 /*! @brief Format value for bitfield CMP_MUXCR_PSTM. */
00911 #define BF_CMP_MUXCR_PSTM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSTM) & BM_CMP_MUXCR_PSTM)
00912 
00913 /*! @brief Set the PSTM field to a new value. */
00914 #define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
00915 /*@}*/
00916 
00917 /*******************************************************************************
00918  * hw_cmp_t - module struct
00919  ******************************************************************************/
00920 /*!
00921  * @brief All CMP module registers.
00922  */
00923 #pragma pack(1)
00924 typedef struct _hw_cmp
00925 {
00926     __IO hw_cmp_cr0_t CR0 ;                 /*!< [0x0] CMP Control Register 0 */
00927     __IO hw_cmp_cr1_t CR1 ;                 /*!< [0x1] CMP Control Register 1 */
00928     __IO hw_cmp_fpr_t FPR ;                 /*!< [0x2] CMP Filter Period Register */
00929     __IO hw_cmp_scr_t SCR ;                 /*!< [0x3] CMP Status and Control Register */
00930     __IO hw_cmp_daccr_t DACCR ;             /*!< [0x4] DAC Control Register */
00931     __IO hw_cmp_muxcr_t MUXCR ;             /*!< [0x5] MUX Control Register */
00932 } hw_cmp_t;
00933 #pragma pack()
00934 
00935 /*! @brief Macro to access all CMP registers. */
00936 /*! @param x CMP module instance base address. */
00937 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00938  *     use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
00939 #define HW_CMP(x)      (*(hw_cmp_t *)(x))
00940 
00941 #endif /* __HW_CMP_REGISTERS_H__ */
00942 /* EOF */