MK64F12_can.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_CAN_REGISTERS_H__
00081 #define __HW_CAN_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 CAN
00088  *
00089  * Flex Controller Area Network module
00090  *
00091  * Registers defined in this header file:
00092  * - HW_CAN_MCR - Module Configuration Register
00093  * - HW_CAN_CTRL1 - Control 1 register
00094  * - HW_CAN_TIMER - Free Running Timer
00095  * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
00096  * - HW_CAN_RX14MASK - Rx 14 Mask register
00097  * - HW_CAN_RX15MASK - Rx 15 Mask register
00098  * - HW_CAN_ECR - Error Counter
00099  * - HW_CAN_ESR1 - Error and Status 1 register
00100  * - HW_CAN_IMASK1 - Interrupt Masks 1 register
00101  * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
00102  * - HW_CAN_CTRL2 - Control 2 register
00103  * - HW_CAN_ESR2 - Error and Status 2 register
00104  * - HW_CAN_CRCR - CRC Register
00105  * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
00106  * - HW_CAN_RXFIR - Rx FIFO Information Register
00107  * - HW_CAN_CSn - Message Buffer 0 CS Register
00108  * - HW_CAN_IDn - Message Buffer 0 ID Register
00109  * - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
00110  * - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
00111  * - HW_CAN_RXIMRn - Rx Individual Mask Registers
00112  *
00113  * - hw_can_t - Struct containing all module registers.
00114  */
00115 
00116 #define HW_CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
00117 
00118 /*******************************************************************************
00119  * HW_CAN_MCR - Module Configuration Register
00120  ******************************************************************************/
00121 
00122 /*!
00123  * @brief HW_CAN_MCR - Module Configuration Register (RW)
00124  *
00125  * Reset value: 0xD890000FU
00126  *
00127  * This register defines global system configurations, such as the module
00128  * operation modes and the maximum message buffer configuration.
00129  */
00130 typedef union _hw_can_mcr
00131 {
00132     uint32_t U;
00133     struct _hw_can_mcr_bitfields
00134     {
00135         uint32_t MAXMB : 7;            /*!< [6:0] Number Of The Last Message Buffer */
00136         uint32_t RESERVED0 : 1;        /*!< [7]  */
00137         uint32_t IDAM : 2;             /*!< [9:8] ID Acceptance Mode */
00138         uint32_t RESERVED1 : 2;        /*!< [11:10]  */
00139         uint32_t AEN : 1;              /*!< [12] Abort Enable */
00140         uint32_t LPRIOEN : 1;          /*!< [13] Local Priority Enable */
00141         uint32_t RESERVED2 : 2;        /*!< [15:14]  */
00142         uint32_t IRMQ : 1;             /*!< [16] Individual Rx Masking And Queue Enable */
00143         uint32_t SRXDIS : 1;           /*!< [17] Self Reception Disable */
00144         uint32_t RESERVED3 : 1;        /*!< [18]  */
00145         uint32_t WAKSRC : 1;           /*!< [19] Wake Up Source */
00146         uint32_t LPMACK : 1;           /*!< [20] Low-Power Mode Acknowledge */
00147         uint32_t WRNEN : 1;            /*!< [21] Warning Interrupt Enable */
00148         uint32_t SLFWAK : 1;           /*!< [22] Self Wake Up */
00149         uint32_t SUPV : 1;             /*!< [23] Supervisor Mode */
00150         uint32_t FRZACK : 1;           /*!< [24] Freeze Mode Acknowledge */
00151         uint32_t SOFTRST : 1;          /*!< [25] Soft Reset */
00152         uint32_t WAKMSK : 1;           /*!< [26] Wake Up Interrupt Mask */
00153         uint32_t NOTRDY : 1;           /*!< [27] FlexCAN Not Ready */
00154         uint32_t HALT : 1;             /*!< [28] Halt FlexCAN */
00155         uint32_t RFEN : 1;             /*!< [29] Rx FIFO Enable */
00156         uint32_t FRZ : 1;              /*!< [30] Freeze Enable */
00157         uint32_t MDIS : 1;             /*!< [31] Module Disable */
00158     } B;
00159 } hw_can_mcr_t;
00160 
00161 /*!
00162  * @name Constants and macros for entire CAN_MCR register
00163  */
00164 /*@{*/
00165 #define HW_CAN_MCR_ADDR(x)       ((x) + 0x0U)
00166 
00167 #define HW_CAN_MCR(x)            (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
00168 #define HW_CAN_MCR_RD(x)         (HW_CAN_MCR(x).U)
00169 #define HW_CAN_MCR_WR(x, v)      (HW_CAN_MCR(x).U = (v))
00170 #define HW_CAN_MCR_SET(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) |  (v)))
00171 #define HW_CAN_MCR_CLR(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
00172 #define HW_CAN_MCR_TOG(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^  (v)))
00173 /*@}*/
00174 
00175 /*
00176  * Constants & macros for individual CAN_MCR bitfields
00177  */
00178 
00179 /*!
00180  * @name Register CAN_MCR, field MAXMB[6:0] (RW)
00181  *
00182  * This 7-bit field defines the number of the last Message Buffers that will
00183  * take part in the matching and arbitration processes. The reset value (0x0F) is
00184  * equivalent to a 16 MB configuration. This field can be written only in Freeze
00185  * mode because it is blocked by hardware in other modes. Number of the last MB =
00186  * MAXMB MAXMB must be programmed with a value smaller than the parameter
00187  * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
00188  * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
00189  * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
00190  * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
00191  * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
00192  * Matching Timing").
00193  */
00194 /*@{*/
00195 #define BP_CAN_MCR_MAXMB     (0U)          /*!< Bit position for CAN_MCR_MAXMB. */
00196 #define BM_CAN_MCR_MAXMB     (0x0000007FU) /*!< Bit mask for CAN_MCR_MAXMB. */
00197 #define BS_CAN_MCR_MAXMB     (7U)          /*!< Bit field size in bits for CAN_MCR_MAXMB. */
00198 
00199 /*! @brief Read current value of the CAN_MCR_MAXMB field. */
00200 #define BR_CAN_MCR_MAXMB(x)  (HW_CAN_MCR(x).B.MAXMB)
00201 
00202 /*! @brief Format value for bitfield CAN_MCR_MAXMB. */
00203 #define BF_CAN_MCR_MAXMB(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB)
00204 
00205 /*! @brief Set the MAXMB field to a new value. */
00206 #define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
00207 /*@}*/
00208 
00209 /*!
00210  * @name Register CAN_MCR, field IDAM[9:8] (RW)
00211  *
00212  * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
00213  * elements. Note that all elements of the table are configured at the same time by this
00214  * field (they are all the same format). See Section "Rx FIFO Structure". This
00215  * field can be written only in Freeze mode because it is blocked by hardware in
00216  * other modes.
00217  *
00218  * Values:
00219  * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
00220  *     element.
00221  * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
00222  *     extended) IDs per ID Filter Table element.
00223  * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
00224  * - 11 - Format D: All frames rejected.
00225  */
00226 /*@{*/
00227 #define BP_CAN_MCR_IDAM      (8U)          /*!< Bit position for CAN_MCR_IDAM. */
00228 #define BM_CAN_MCR_IDAM      (0x00000300U) /*!< Bit mask for CAN_MCR_IDAM. */
00229 #define BS_CAN_MCR_IDAM      (2U)          /*!< Bit field size in bits for CAN_MCR_IDAM. */
00230 
00231 /*! @brief Read current value of the CAN_MCR_IDAM field. */
00232 #define BR_CAN_MCR_IDAM(x)   (HW_CAN_MCR(x).B.IDAM)
00233 
00234 /*! @brief Format value for bitfield CAN_MCR_IDAM. */
00235 #define BF_CAN_MCR_IDAM(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM)
00236 
00237 /*! @brief Set the IDAM field to a new value. */
00238 #define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
00239 /*@}*/
00240 
00241 /*!
00242  * @name Register CAN_MCR, field AEN[12] (RW)
00243  *
00244  * This bit is supplied for backwards compatibility with legacy applications.
00245  * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
00246  * safe procedure for aborting a pending transmission, so that no frame is sent in
00247  * the CAN bus without notification. This bit can be written only in Freeze mode
00248  * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
00249  * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
00250  * used for updating Mailboxes configured for transmission. Writing the Abort code
00251  * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
00252  * asserted.
00253  *
00254  * Values:
00255  * - 0 - Abort disabled.
00256  * - 1 - Abort enabled.
00257  */
00258 /*@{*/
00259 #define BP_CAN_MCR_AEN       (12U)         /*!< Bit position for CAN_MCR_AEN. */
00260 #define BM_CAN_MCR_AEN       (0x00001000U) /*!< Bit mask for CAN_MCR_AEN. */
00261 #define BS_CAN_MCR_AEN       (1U)          /*!< Bit field size in bits for CAN_MCR_AEN. */
00262 
00263 /*! @brief Read current value of the CAN_MCR_AEN field. */
00264 #define BR_CAN_MCR_AEN(x)    (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
00265 
00266 /*! @brief Format value for bitfield CAN_MCR_AEN. */
00267 #define BF_CAN_MCR_AEN(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN)
00268 
00269 /*! @brief Set the AEN field to a new value. */
00270 #define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
00271 /*@}*/
00272 
00273 /*!
00274  * @name Register CAN_MCR, field LPRIOEN[13] (RW)
00275  *
00276  * This bit is provided for backwards compatibility with legacy applications. It
00277  * controls whether the local priority feature is enabled or not. It is used to
00278  * expand the ID used during the arbitration process. With this expanded ID
00279  * concept, the arbitration process is done based on the full 32-bit word, but the
00280  * actual transmitted ID still has 11-bit for standard frames and 29-bit for
00281  * extended frames. This bit can be written only in Freeze mode because it is blocked by
00282  * hardware in other modes.
00283  *
00284  * Values:
00285  * - 0 - Local Priority disabled.
00286  * - 1 - Local Priority enabled.
00287  */
00288 /*@{*/
00289 #define BP_CAN_MCR_LPRIOEN   (13U)         /*!< Bit position for CAN_MCR_LPRIOEN. */
00290 #define BM_CAN_MCR_LPRIOEN   (0x00002000U) /*!< Bit mask for CAN_MCR_LPRIOEN. */
00291 #define BS_CAN_MCR_LPRIOEN   (1U)          /*!< Bit field size in bits for CAN_MCR_LPRIOEN. */
00292 
00293 /*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
00294 #define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
00295 
00296 /*! @brief Format value for bitfield CAN_MCR_LPRIOEN. */
00297 #define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN)
00298 
00299 /*! @brief Set the LPRIOEN field to a new value. */
00300 #define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
00301 /*@}*/
00302 
00303 /*!
00304  * @name Register CAN_MCR, field IRMQ[16] (RW)
00305  *
00306  * This bit indicates whether Rx matching process will be based either on
00307  * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
00308  * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
00309  * blocked by hardware in other modes.
00310  *
00311  * Values:
00312  * - 0 - Individual Rx masking and queue feature are disabled. For backward
00313  *     compatibility with legacy applications, the reading of C/S word locks the MB
00314  *     even if it is EMPTY.
00315  * - 1 - Individual Rx masking and queue feature are enabled.
00316  */
00317 /*@{*/
00318 #define BP_CAN_MCR_IRMQ      (16U)         /*!< Bit position for CAN_MCR_IRMQ. */
00319 #define BM_CAN_MCR_IRMQ      (0x00010000U) /*!< Bit mask for CAN_MCR_IRMQ. */
00320 #define BS_CAN_MCR_IRMQ      (1U)          /*!< Bit field size in bits for CAN_MCR_IRMQ. */
00321 
00322 /*! @brief Read current value of the CAN_MCR_IRMQ field. */
00323 #define BR_CAN_MCR_IRMQ(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
00324 
00325 /*! @brief Format value for bitfield CAN_MCR_IRMQ. */
00326 #define BF_CAN_MCR_IRMQ(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ)
00327 
00328 /*! @brief Set the IRMQ field to a new value. */
00329 #define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
00330 /*@}*/
00331 
00332 /*!
00333  * @name Register CAN_MCR, field SRXDIS[17] (RW)
00334  *
00335  * This bit defines whether FlexCAN is allowed to receive frames transmitted by
00336  * itself. If this bit is asserted, frames transmitted by the module will not be
00337  * stored in any MB, regardless if the MB is programmed with an ID that matches
00338  * the transmitted frame, and no interrupt flag or interrupt signal will be
00339  * generated due to the frame reception. This bit can be written only in Freeze mode
00340  * because it is blocked by hardware in other modes.
00341  *
00342  * Values:
00343  * - 0 - Self reception enabled.
00344  * - 1 - Self reception disabled.
00345  */
00346 /*@{*/
00347 #define BP_CAN_MCR_SRXDIS    (17U)         /*!< Bit position for CAN_MCR_SRXDIS. */
00348 #define BM_CAN_MCR_SRXDIS    (0x00020000U) /*!< Bit mask for CAN_MCR_SRXDIS. */
00349 #define BS_CAN_MCR_SRXDIS    (1U)          /*!< Bit field size in bits for CAN_MCR_SRXDIS. */
00350 
00351 /*! @brief Read current value of the CAN_MCR_SRXDIS field. */
00352 #define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
00353 
00354 /*! @brief Format value for bitfield CAN_MCR_SRXDIS. */
00355 #define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS)
00356 
00357 /*! @brief Set the SRXDIS field to a new value. */
00358 #define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
00359 /*@}*/
00360 
00361 /*!
00362  * @name Register CAN_MCR, field WAKSRC[19] (RW)
00363  *
00364  * This bit defines whether the integrated low-pass filter is applied to protect
00365  * the Rx CAN input from spurious wake up. This bit can be written only in
00366  * Freeze mode because it is blocked by hardware in other modes.
00367  *
00368  * Values:
00369  * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
00370  *     edges on the CAN bus.
00371  * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
00372  *     edges on the CAN bus.
00373  */
00374 /*@{*/
00375 #define BP_CAN_MCR_WAKSRC    (19U)         /*!< Bit position for CAN_MCR_WAKSRC. */
00376 #define BM_CAN_MCR_WAKSRC    (0x00080000U) /*!< Bit mask for CAN_MCR_WAKSRC. */
00377 #define BS_CAN_MCR_WAKSRC    (1U)          /*!< Bit field size in bits for CAN_MCR_WAKSRC. */
00378 
00379 /*! @brief Read current value of the CAN_MCR_WAKSRC field. */
00380 #define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
00381 
00382 /*! @brief Format value for bitfield CAN_MCR_WAKSRC. */
00383 #define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC)
00384 
00385 /*! @brief Set the WAKSRC field to a new value. */
00386 #define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
00387 /*@}*/
00388 
00389 /*!
00390  * @name Register CAN_MCR, field LPMACK[20] (RO)
00391  *
00392  * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
00393  * mode , Stop mode ). A low-power mode cannot be entered until all current
00394  * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
00395  * to know when FlexCAN has actually entered low power mode. LPMACK will be
00396  * asserted within 180 CAN bits from the low-power mode request by the CPU, and
00397  * negated within 2 CAN bits after the low-power mode request removal (see Section
00398  * "Protocol Timing").
00399  *
00400  * Values:
00401  * - 0 - FlexCAN is not in a low-power mode.
00402  * - 1 - FlexCAN is in a low-power mode.
00403  */
00404 /*@{*/
00405 #define BP_CAN_MCR_LPMACK    (20U)         /*!< Bit position for CAN_MCR_LPMACK. */
00406 #define BM_CAN_MCR_LPMACK    (0x00100000U) /*!< Bit mask for CAN_MCR_LPMACK. */
00407 #define BS_CAN_MCR_LPMACK    (1U)          /*!< Bit field size in bits for CAN_MCR_LPMACK. */
00408 
00409 /*! @brief Read current value of the CAN_MCR_LPMACK field. */
00410 #define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
00411 /*@}*/
00412 
00413 /*!
00414  * @name Register CAN_MCR, field WRNEN[21] (RW)
00415  *
00416  * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
00417  * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
00418  * RWRNINT flags will always be zero, independent of the values of the error
00419  * counters, and no warning interrupt will ever be generated. This bit can be written
00420  * only in Freeze mode because it is blocked by hardware in other modes.
00421  *
00422  * Values:
00423  * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
00424  *     error counters.
00425  * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
00426  *     transitions from less than 96 to greater than or equal to 96.
00427  */
00428 /*@{*/
00429 #define BP_CAN_MCR_WRNEN     (21U)         /*!< Bit position for CAN_MCR_WRNEN. */
00430 #define BM_CAN_MCR_WRNEN     (0x00200000U) /*!< Bit mask for CAN_MCR_WRNEN. */
00431 #define BS_CAN_MCR_WRNEN     (1U)          /*!< Bit field size in bits for CAN_MCR_WRNEN. */
00432 
00433 /*! @brief Read current value of the CAN_MCR_WRNEN field. */
00434 #define BR_CAN_MCR_WRNEN(x)  (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
00435 
00436 /*! @brief Format value for bitfield CAN_MCR_WRNEN. */
00437 #define BF_CAN_MCR_WRNEN(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN)
00438 
00439 /*! @brief Set the WRNEN field to a new value. */
00440 #define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
00441 /*@}*/
00442 
00443 /*!
00444  * @name Register CAN_MCR, field SLFWAK[22] (RW)
00445  *
00446  * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
00447  * other than Disable mode. When this feature is enabled, the FlexCAN module
00448  * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
00449  * If a wake up event is detected during Stop mode, then FlexCAN generates, if
00450  * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
00451  * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
00452  * low-power mode other than Disable mode, this bit cannot be written as it is
00453  * blocked by hardware.
00454  *
00455  * Values:
00456  * - 0 - FlexCAN Self Wake Up feature is disabled.
00457  * - 1 - FlexCAN Self Wake Up feature is enabled.
00458  */
00459 /*@{*/
00460 #define BP_CAN_MCR_SLFWAK    (22U)         /*!< Bit position for CAN_MCR_SLFWAK. */
00461 #define BM_CAN_MCR_SLFWAK    (0x00400000U) /*!< Bit mask for CAN_MCR_SLFWAK. */
00462 #define BS_CAN_MCR_SLFWAK    (1U)          /*!< Bit field size in bits for CAN_MCR_SLFWAK. */
00463 
00464 /*! @brief Read current value of the CAN_MCR_SLFWAK field. */
00465 #define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
00466 
00467 /*! @brief Format value for bitfield CAN_MCR_SLFWAK. */
00468 #define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK)
00469 
00470 /*! @brief Set the SLFWAK field to a new value. */
00471 #define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
00472 /*@}*/
00473 
00474 /*!
00475  * @name Register CAN_MCR, field SUPV[23] (RW)
00476  *
00477  * This bit configures the FlexCAN to be either in Supervisor or User mode. The
00478  * registers affected by this bit are marked as S/U in the Access Type column of
00479  * the module memory map. Reset value of this bit is 1, so the affected registers
00480  * start with Supervisor access allowance only . This bit can be written only in
00481  * Freeze mode because it is blocked by hardware in other modes.
00482  *
00483  * Values:
00484  * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
00485  *     Unrestricted accesses .
00486  * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
00487  *     access. Unrestricted access behaves as though the access was done to an
00488  *     unimplemented register location .
00489  */
00490 /*@{*/
00491 #define BP_CAN_MCR_SUPV      (23U)         /*!< Bit position for CAN_MCR_SUPV. */
00492 #define BM_CAN_MCR_SUPV      (0x00800000U) /*!< Bit mask for CAN_MCR_SUPV. */
00493 #define BS_CAN_MCR_SUPV      (1U)          /*!< Bit field size in bits for CAN_MCR_SUPV. */
00494 
00495 /*! @brief Read current value of the CAN_MCR_SUPV field. */
00496 #define BR_CAN_MCR_SUPV(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
00497 
00498 /*! @brief Format value for bitfield CAN_MCR_SUPV. */
00499 #define BF_CAN_MCR_SUPV(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV)
00500 
00501 /*! @brief Set the SUPV field to a new value. */
00502 #define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
00503 /*@}*/
00504 
00505 /*!
00506  * @name Register CAN_MCR, field FRZACK[24] (RO)
00507  *
00508  * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
00509  * is stopped. The Freeze mode request cannot be granted until current
00510  * transmission or reception processes have finished. Therefore the software can poll the
00511  * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
00512  * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
00513  * running again. If Freeze mode is requested while FlexCAN is in a low power
00514  * mode, then the FRZACK bit will be set only when the low-power mode is exited.
00515  * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
00516  * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
00517  * mode request removal (see Section "Protocol Timing").
00518  *
00519  * Values:
00520  * - 0 - FlexCAN not in Freeze mode, prescaler running.
00521  * - 1 - FlexCAN in Freeze mode, prescaler stopped.
00522  */
00523 /*@{*/
00524 #define BP_CAN_MCR_FRZACK    (24U)         /*!< Bit position for CAN_MCR_FRZACK. */
00525 #define BM_CAN_MCR_FRZACK    (0x01000000U) /*!< Bit mask for CAN_MCR_FRZACK. */
00526 #define BS_CAN_MCR_FRZACK    (1U)          /*!< Bit field size in bits for CAN_MCR_FRZACK. */
00527 
00528 /*! @brief Read current value of the CAN_MCR_FRZACK field. */
00529 #define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
00530 /*@}*/
00531 
00532 /*!
00533  * @name Register CAN_MCR, field SOFTRST[25] (RW)
00534  *
00535  * When this bit is asserted, FlexCAN resets its internal state machines and
00536  * some of the memory mapped registers. The following registers are reset: MCR
00537  * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
00538  * CRCR. Configuration registers that control the interface to the CAN bus are
00539  * not affected by soft reset. The following registers are unaffected: CTRL1,
00540  * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
00541  * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
00542  * writes to the MCR Register, but it is also asserted when global soft reset is
00543  * requested at MCU level . Because soft reset is synchronous and has to follow a
00544  * request/acknowledge procedure across clock domains, it may take some time to
00545  * fully propagate its effect. The SOFTRST bit remains asserted while reset is
00546  * pending, and is automatically negated when reset completes. Therefore, software can
00547  * poll this bit to know when the soft reset has completed. Soft reset cannot be
00548  * applied while clocks are shut down in a low power mode. The module should be
00549  * first removed from low power mode, and then soft reset can be applied.
00550  *
00551  * Values:
00552  * - 0 - No reset request.
00553  * - 1 - Resets the registers affected by soft reset.
00554  */
00555 /*@{*/
00556 #define BP_CAN_MCR_SOFTRST   (25U)         /*!< Bit position for CAN_MCR_SOFTRST. */
00557 #define BM_CAN_MCR_SOFTRST   (0x02000000U) /*!< Bit mask for CAN_MCR_SOFTRST. */
00558 #define BS_CAN_MCR_SOFTRST   (1U)          /*!< Bit field size in bits for CAN_MCR_SOFTRST. */
00559 
00560 /*! @brief Read current value of the CAN_MCR_SOFTRST field. */
00561 #define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
00562 
00563 /*! @brief Format value for bitfield CAN_MCR_SOFTRST. */
00564 #define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST)
00565 
00566 /*! @brief Set the SOFTRST field to a new value. */
00567 #define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
00568 /*@}*/
00569 
00570 /*!
00571  * @name Register CAN_MCR, field WAKMSK[26] (RW)
00572  *
00573  * This bit enables the Wake Up Interrupt generation under Self Wake Up
00574  * mechanism.
00575  *
00576  * Values:
00577  * - 0 - Wake Up Interrupt is disabled.
00578  * - 1 - Wake Up Interrupt is enabled.
00579  */
00580 /*@{*/
00581 #define BP_CAN_MCR_WAKMSK    (26U)         /*!< Bit position for CAN_MCR_WAKMSK. */
00582 #define BM_CAN_MCR_WAKMSK    (0x04000000U) /*!< Bit mask for CAN_MCR_WAKMSK. */
00583 #define BS_CAN_MCR_WAKMSK    (1U)          /*!< Bit field size in bits for CAN_MCR_WAKMSK. */
00584 
00585 /*! @brief Read current value of the CAN_MCR_WAKMSK field. */
00586 #define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
00587 
00588 /*! @brief Format value for bitfield CAN_MCR_WAKMSK. */
00589 #define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK)
00590 
00591 /*! @brief Set the WAKMSK field to a new value. */
00592 #define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
00593 /*@}*/
00594 
00595 /*!
00596  * @name Register CAN_MCR, field NOTRDY[27] (RO)
00597  *
00598  * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
00599  * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
00600  *
00601  * Values:
00602  * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
00603  *     mode.
00604  * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
00605  */
00606 /*@{*/
00607 #define BP_CAN_MCR_NOTRDY    (27U)         /*!< Bit position for CAN_MCR_NOTRDY. */
00608 #define BM_CAN_MCR_NOTRDY    (0x08000000U) /*!< Bit mask for CAN_MCR_NOTRDY. */
00609 #define BS_CAN_MCR_NOTRDY    (1U)          /*!< Bit field size in bits for CAN_MCR_NOTRDY. */
00610 
00611 /*! @brief Read current value of the CAN_MCR_NOTRDY field. */
00612 #define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
00613 /*@}*/
00614 
00615 /*!
00616  * @name Register CAN_MCR, field HALT[28] (RW)
00617  *
00618  * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
00619  * should clear it after initializing the Message Buffers and Control Register. No
00620  * reception or transmission is performed by FlexCAN before this bit is cleared.
00621  * Freeze mode cannot be entered while FlexCAN is in a low power mode.
00622  *
00623  * Values:
00624  * - 0 - No Freeze mode request.
00625  * - 1 - Enters Freeze mode if the FRZ bit is asserted.
00626  */
00627 /*@{*/
00628 #define BP_CAN_MCR_HALT      (28U)         /*!< Bit position for CAN_MCR_HALT. */
00629 #define BM_CAN_MCR_HALT      (0x10000000U) /*!< Bit mask for CAN_MCR_HALT. */
00630 #define BS_CAN_MCR_HALT      (1U)          /*!< Bit field size in bits for CAN_MCR_HALT. */
00631 
00632 /*! @brief Read current value of the CAN_MCR_HALT field. */
00633 #define BR_CAN_MCR_HALT(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
00634 
00635 /*! @brief Format value for bitfield CAN_MCR_HALT. */
00636 #define BF_CAN_MCR_HALT(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT)
00637 
00638 /*! @brief Set the HALT field to a new value. */
00639 #define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
00640 /*@}*/
00641 
00642 /*!
00643  * @name Register CAN_MCR, field RFEN[29] (RW)
00644  *
00645  * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
00646  * set, MBs 0 to 5 cannot be used for normal reception and transmission because
00647  * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
00648  * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
00649  * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
00650  * minimum number of peripheral clocks per CAN bit as described in the table
00651  * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
00652  * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
00653  * because it is blocked by hardware in other modes.
00654  *
00655  * Values:
00656  * - 0 - Rx FIFO not enabled.
00657  * - 1 - Rx FIFO enabled.
00658  */
00659 /*@{*/
00660 #define BP_CAN_MCR_RFEN      (29U)         /*!< Bit position for CAN_MCR_RFEN. */
00661 #define BM_CAN_MCR_RFEN      (0x20000000U) /*!< Bit mask for CAN_MCR_RFEN. */
00662 #define BS_CAN_MCR_RFEN      (1U)          /*!< Bit field size in bits for CAN_MCR_RFEN. */
00663 
00664 /*! @brief Read current value of the CAN_MCR_RFEN field. */
00665 #define BR_CAN_MCR_RFEN(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
00666 
00667 /*! @brief Format value for bitfield CAN_MCR_RFEN. */
00668 #define BF_CAN_MCR_RFEN(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN)
00669 
00670 /*! @brief Set the RFEN field to a new value. */
00671 #define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
00672 /*@}*/
00673 
00674 /*!
00675  * @name Register CAN_MCR, field FRZ[30] (RW)
00676  *
00677  * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
00678  * Register is set or when Debug mode is requested at MCU level . When FRZ is
00679  * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
00680  * FlexCAN to exit from Freeze mode.
00681  *
00682  * Values:
00683  * - 0 - Not enabled to enter Freeze mode.
00684  * - 1 - Enabled to enter Freeze mode.
00685  */
00686 /*@{*/
00687 #define BP_CAN_MCR_FRZ       (30U)         /*!< Bit position for CAN_MCR_FRZ. */
00688 #define BM_CAN_MCR_FRZ       (0x40000000U) /*!< Bit mask for CAN_MCR_FRZ. */
00689 #define BS_CAN_MCR_FRZ       (1U)          /*!< Bit field size in bits for CAN_MCR_FRZ. */
00690 
00691 /*! @brief Read current value of the CAN_MCR_FRZ field. */
00692 #define BR_CAN_MCR_FRZ(x)    (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
00693 
00694 /*! @brief Format value for bitfield CAN_MCR_FRZ. */
00695 #define BF_CAN_MCR_FRZ(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ)
00696 
00697 /*! @brief Set the FRZ field to a new value. */
00698 #define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
00699 /*@}*/
00700 
00701 /*!
00702  * @name Register CAN_MCR, field MDIS[31] (RW)
00703  *
00704  * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
00705  * disables the clocks to the CAN Protocol Engine and Controller Host Interface
00706  * sub-modules. This is the only bit within this register not affected by soft
00707  * reset.
00708  *
00709  * Values:
00710  * - 0 - Enable the FlexCAN module.
00711  * - 1 - Disable the FlexCAN module.
00712  */
00713 /*@{*/
00714 #define BP_CAN_MCR_MDIS      (31U)         /*!< Bit position for CAN_MCR_MDIS. */
00715 #define BM_CAN_MCR_MDIS      (0x80000000U) /*!< Bit mask for CAN_MCR_MDIS. */
00716 #define BS_CAN_MCR_MDIS      (1U)          /*!< Bit field size in bits for CAN_MCR_MDIS. */
00717 
00718 /*! @brief Read current value of the CAN_MCR_MDIS field. */
00719 #define BR_CAN_MCR_MDIS(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
00720 
00721 /*! @brief Format value for bitfield CAN_MCR_MDIS. */
00722 #define BF_CAN_MCR_MDIS(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS)
00723 
00724 /*! @brief Set the MDIS field to a new value. */
00725 #define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
00726 /*@}*/
00727 
00728 /*******************************************************************************
00729  * HW_CAN_CTRL1 - Control 1 register
00730  ******************************************************************************/
00731 
00732 /*!
00733  * @brief HW_CAN_CTRL1 - Control 1 register (RW)
00734  *
00735  * Reset value: 0x00000000U
00736  *
00737  * This register is defined for specific FlexCAN control features related to the
00738  * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
00739  * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
00740  * (Bus-Off, Error, Warning). It also determines the Division Factor for the
00741  * clock prescaler.
00742  */
00743 typedef union _hw_can_ctrl1
00744 {
00745     uint32_t U;
00746     struct _hw_can_ctrl1_bitfields
00747     {
00748         uint32_t PROPSEG : 3;          /*!< [2:0] Propagation Segment */
00749         uint32_t LOM : 1;              /*!< [3] Listen-Only Mode */
00750         uint32_t LBUF : 1;             /*!< [4] Lowest Buffer Transmitted First */
00751         uint32_t TSYN : 1;             /*!< [5] Timer Sync */
00752         uint32_t BOFFREC : 1;          /*!< [6] Bus Off Recovery */
00753         uint32_t SMP : 1;              /*!< [7] CAN Bit Sampling */
00754         uint32_t RESERVED0 : 2;        /*!< [9:8]  */
00755         uint32_t RWRNMSK : 1;          /*!< [10] Rx Warning Interrupt Mask */
00756         uint32_t TWRNMSK : 1;          /*!< [11] Tx Warning Interrupt Mask */
00757         uint32_t LPB : 1;              /*!< [12] Loop Back Mode */
00758         uint32_t CLKSRC : 1;           /*!< [13] CAN Engine Clock Source */
00759         uint32_t ERRMSK : 1;           /*!< [14] Error Mask */
00760         uint32_t BOFFMSK : 1;          /*!< [15] Bus Off Mask */
00761         uint32_t PSEG2 : 3;            /*!< [18:16] Phase Segment 2 */
00762         uint32_t PSEG1 : 3;            /*!< [21:19] Phase Segment 1 */
00763         uint32_t RJW : 2;              /*!< [23:22] Resync Jump Width */
00764         uint32_t PRESDIV : 8;          /*!< [31:24] Prescaler Division Factor */
00765     } B;
00766 } hw_can_ctrl1_t;
00767 
00768 /*!
00769  * @name Constants and macros for entire CAN_CTRL1 register
00770  */
00771 /*@{*/
00772 #define HW_CAN_CTRL1_ADDR(x)     ((x) + 0x4U)
00773 
00774 #define HW_CAN_CTRL1(x)          (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
00775 #define HW_CAN_CTRL1_RD(x)       (HW_CAN_CTRL1(x).U)
00776 #define HW_CAN_CTRL1_WR(x, v)    (HW_CAN_CTRL1(x).U = (v))
00777 #define HW_CAN_CTRL1_SET(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) |  (v)))
00778 #define HW_CAN_CTRL1_CLR(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
00779 #define HW_CAN_CTRL1_TOG(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^  (v)))
00780 /*@}*/
00781 
00782 /*
00783  * Constants & macros for individual CAN_CTRL1 bitfields
00784  */
00785 
00786 /*!
00787  * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
00788  *
00789  * This 3-bit field defines the length of the Propagation Segment in the bit
00790  * time. The valid programmable values are 0-7. This field can be written only in
00791  * Freeze mode because it is blocked by hardware in other modes. Propagation
00792  * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
00793  */
00794 /*@{*/
00795 #define BP_CAN_CTRL1_PROPSEG (0U)          /*!< Bit position for CAN_CTRL1_PROPSEG. */
00796 #define BM_CAN_CTRL1_PROPSEG (0x00000007U) /*!< Bit mask for CAN_CTRL1_PROPSEG. */
00797 #define BS_CAN_CTRL1_PROPSEG (3U)          /*!< Bit field size in bits for CAN_CTRL1_PROPSEG. */
00798 
00799 /*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
00800 #define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
00801 
00802 /*! @brief Format value for bitfield CAN_CTRL1_PROPSEG. */
00803 #define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG)
00804 
00805 /*! @brief Set the PROPSEG field to a new value. */
00806 #define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
00807 /*@}*/
00808 
00809 /*!
00810  * @name Register CAN_CTRL1, field LOM[3] (RW)
00811  *
00812  * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
00813  * transmission is disabled, all error counters are frozen and the module operates
00814  * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
00815  * will be received. If FlexCAN detects a message that has not been acknowledged,
00816  * it will flag a BIT0 error without changing the REC, as if it was trying to
00817  * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
00818  * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
00819  * entered. There can be some delay between the Listen-Only mode request and
00820  * acknowledge. This bit can be written only in Freeze mode because it is blocked by
00821  * hardware in other modes.
00822  *
00823  * Values:
00824  * - 0 - Listen-Only mode is deactivated.
00825  * - 1 - FlexCAN module operates in Listen-Only mode.
00826  */
00827 /*@{*/
00828 #define BP_CAN_CTRL1_LOM     (3U)          /*!< Bit position for CAN_CTRL1_LOM. */
00829 #define BM_CAN_CTRL1_LOM     (0x00000008U) /*!< Bit mask for CAN_CTRL1_LOM. */
00830 #define BS_CAN_CTRL1_LOM     (1U)          /*!< Bit field size in bits for CAN_CTRL1_LOM. */
00831 
00832 /*! @brief Read current value of the CAN_CTRL1_LOM field. */
00833 #define BR_CAN_CTRL1_LOM(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
00834 
00835 /*! @brief Format value for bitfield CAN_CTRL1_LOM. */
00836 #define BF_CAN_CTRL1_LOM(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM)
00837 
00838 /*! @brief Set the LOM field to a new value. */
00839 #define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
00840 /*@}*/
00841 
00842 /*!
00843  * @name Register CAN_CTRL1, field LBUF[4] (RW)
00844  *
00845  * This bit defines the ordering mechanism for Message Buffer transmission. When
00846  * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
00847  * can be written only in Freeze mode because it is blocked by hardware in other
00848  * modes.
00849  *
00850  * Values:
00851  * - 0 - Buffer with highest priority is transmitted first.
00852  * - 1 - Lowest number buffer is transmitted first.
00853  */
00854 /*@{*/
00855 #define BP_CAN_CTRL1_LBUF    (4U)          /*!< Bit position for CAN_CTRL1_LBUF. */
00856 #define BM_CAN_CTRL1_LBUF    (0x00000010U) /*!< Bit mask for CAN_CTRL1_LBUF. */
00857 #define BS_CAN_CTRL1_LBUF    (1U)          /*!< Bit field size in bits for CAN_CTRL1_LBUF. */
00858 
00859 /*! @brief Read current value of the CAN_CTRL1_LBUF field. */
00860 #define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
00861 
00862 /*! @brief Format value for bitfield CAN_CTRL1_LBUF. */
00863 #define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF)
00864 
00865 /*! @brief Set the LBUF field to a new value. */
00866 #define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
00867 /*@}*/
00868 
00869 /*!
00870  * @name Register CAN_CTRL1, field TSYN[5] (RW)
00871  *
00872  * This bit enables a mechanism that resets the free-running timer each time a
00873  * message is received in Message Buffer 0. This feature provides means to
00874  * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
00875  * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
00876  * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
00877  * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
00878  * blocked by hardware in other modes.
00879  *
00880  * Values:
00881  * - 0 - Timer Sync feature disabled
00882  * - 1 - Timer Sync feature enabled
00883  */
00884 /*@{*/
00885 #define BP_CAN_CTRL1_TSYN    (5U)          /*!< Bit position for CAN_CTRL1_TSYN. */
00886 #define BM_CAN_CTRL1_TSYN    (0x00000020U) /*!< Bit mask for CAN_CTRL1_TSYN. */
00887 #define BS_CAN_CTRL1_TSYN    (1U)          /*!< Bit field size in bits for CAN_CTRL1_TSYN. */
00888 
00889 /*! @brief Read current value of the CAN_CTRL1_TSYN field. */
00890 #define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
00891 
00892 /*! @brief Format value for bitfield CAN_CTRL1_TSYN. */
00893 #define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN)
00894 
00895 /*! @brief Set the TSYN field to a new value. */
00896 #define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
00897 /*@}*/
00898 
00899 /*!
00900  * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
00901  *
00902  * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
00903  * negated, automatic recovering from Bus Off state occurs according to the CAN
00904  * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
00905  * disabled and the module remains in Bus Off state until the bit is negated by the
00906  * user. If the negation occurs before 128 sequences of 11 recessive bits are
00907  * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
00908  * never been asserted. If the negation occurs after 128 sequences of 11
00909  * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
00910  * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
00911  * be re-asserted again during Bus Off, but it will be effective only the next
00912  * time the module enters Bus Off. If BOFFREC was negated when the module entered
00913  * Bus Off, asserting it during Bus Off will not be effective for the current Bus
00914  * Off recovery.
00915  *
00916  * Values:
00917  * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
00918  *     2.0 part B.
00919  * - 1 - Automatic recovering from Bus Off state disabled.
00920  */
00921 /*@{*/
00922 #define BP_CAN_CTRL1_BOFFREC (6U)          /*!< Bit position for CAN_CTRL1_BOFFREC. */
00923 #define BM_CAN_CTRL1_BOFFREC (0x00000040U) /*!< Bit mask for CAN_CTRL1_BOFFREC. */
00924 #define BS_CAN_CTRL1_BOFFREC (1U)          /*!< Bit field size in bits for CAN_CTRL1_BOFFREC. */
00925 
00926 /*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
00927 #define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
00928 
00929 /*! @brief Format value for bitfield CAN_CTRL1_BOFFREC. */
00930 #define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC)
00931 
00932 /*! @brief Set the BOFFREC field to a new value. */
00933 #define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
00934 /*@}*/
00935 
00936 /*!
00937  * @name Register CAN_CTRL1, field SMP[7] (RW)
00938  *
00939  * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
00940  * be written only in Freeze mode because it is blocked by hardware in other
00941  * modes.
00942  *
00943  * Values:
00944  * - 0 - Just one sample is used to determine the bit value.
00945  * - 1 - Three samples are used to determine the value of the received bit: the
00946  *     regular one (sample point) and 2 preceding samples; a majority rule is
00947  *     used.
00948  */
00949 /*@{*/
00950 #define BP_CAN_CTRL1_SMP     (7U)          /*!< Bit position for CAN_CTRL1_SMP. */
00951 #define BM_CAN_CTRL1_SMP     (0x00000080U) /*!< Bit mask for CAN_CTRL1_SMP. */
00952 #define BS_CAN_CTRL1_SMP     (1U)          /*!< Bit field size in bits for CAN_CTRL1_SMP. */
00953 
00954 /*! @brief Read current value of the CAN_CTRL1_SMP field. */
00955 #define BR_CAN_CTRL1_SMP(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
00956 
00957 /*! @brief Format value for bitfield CAN_CTRL1_SMP. */
00958 #define BF_CAN_CTRL1_SMP(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP)
00959 
00960 /*! @brief Set the SMP field to a new value. */
00961 #define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
00962 /*@}*/
00963 
00964 /*!
00965  * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
00966  *
00967  * This bit provides a mask for the Rx Warning Interrupt associated with the
00968  * RWRNINT flag in the Error and Status Register. This bit is read as zero when
00969  * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
00970  * asserted.
00971  *
00972  * Values:
00973  * - 0 - Rx Warning Interrupt disabled.
00974  * - 1 - Rx Warning Interrupt enabled.
00975  */
00976 /*@{*/
00977 #define BP_CAN_CTRL1_RWRNMSK (10U)         /*!< Bit position for CAN_CTRL1_RWRNMSK. */
00978 #define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /*!< Bit mask for CAN_CTRL1_RWRNMSK. */
00979 #define BS_CAN_CTRL1_RWRNMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_RWRNMSK. */
00980 
00981 /*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
00982 #define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
00983 
00984 /*! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. */
00985 #define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK)
00986 
00987 /*! @brief Set the RWRNMSK field to a new value. */
00988 #define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
00989 /*@}*/
00990 
00991 /*!
00992  * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
00993  *
00994  * This bit provides a mask for the Tx Warning Interrupt associated with the
00995  * TWRNINT flag in the Error and Status Register. This bit is read as zero when
00996  * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
00997  * asserted.
00998  *
00999  * Values:
01000  * - 0 - Tx Warning Interrupt disabled.
01001  * - 1 - Tx Warning Interrupt enabled.
01002  */
01003 /*@{*/
01004 #define BP_CAN_CTRL1_TWRNMSK (11U)         /*!< Bit position for CAN_CTRL1_TWRNMSK. */
01005 #define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /*!< Bit mask for CAN_CTRL1_TWRNMSK. */
01006 #define BS_CAN_CTRL1_TWRNMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_TWRNMSK. */
01007 
01008 /*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
01009 #define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
01010 
01011 /*! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. */
01012 #define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK)
01013 
01014 /*! @brief Set the TWRNMSK field to a new value. */
01015 #define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
01016 /*@}*/
01017 
01018 /*!
01019  * @name Register CAN_CTRL1, field LPB[12] (RW)
01020  *
01021  * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
01022  * FlexCAN performs an internal loop back that can be used for self test operation.
01023  * The bit stream output of the transmitter is fed back internally to the receiver
01024  * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
01025  * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
01026  * and treats its own transmitted message as a message received from a remote
01027  * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
01028  * frame acknowledge field, generating an internal acknowledge bit to ensure proper
01029  * reception of its own message. Both transmit and receive interrupts are
01030  * generated. This bit can be written only in Freeze mode because it is blocked by
01031  * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
01032  * this will impede the self reception of a transmitted message.
01033  *
01034  * Values:
01035  * - 0 - Loop Back disabled.
01036  * - 1 - Loop Back enabled.
01037  */
01038 /*@{*/
01039 #define BP_CAN_CTRL1_LPB     (12U)         /*!< Bit position for CAN_CTRL1_LPB. */
01040 #define BM_CAN_CTRL1_LPB     (0x00001000U) /*!< Bit mask for CAN_CTRL1_LPB. */
01041 #define BS_CAN_CTRL1_LPB     (1U)          /*!< Bit field size in bits for CAN_CTRL1_LPB. */
01042 
01043 /*! @brief Read current value of the CAN_CTRL1_LPB field. */
01044 #define BR_CAN_CTRL1_LPB(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
01045 
01046 /*! @brief Format value for bitfield CAN_CTRL1_LPB. */
01047 #define BF_CAN_CTRL1_LPB(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB)
01048 
01049 /*! @brief Set the LPB field to a new value. */
01050 #define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
01051 /*@}*/
01052 
01053 /*!
01054  * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
01055  *
01056  * This bit selects the clock source to the CAN Protocol Engine (PE) to be
01057  * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
01058  * The selected clock is the one fed to the prescaler to generate the Serial Clock
01059  * (Sclock). In order to guarantee reliable operation, this bit can be written
01060  * only in Disable mode because it is blocked by hardware in other modes. See
01061  * Section "Protocol Timing".
01062  *
01063  * Values:
01064  * - 0 - The CAN engine clock source is the oscillator clock. Under this
01065  *     condition, the oscillator clock frequency must be lower than the bus clock.
01066  * - 1 - The CAN engine clock source is the peripheral clock.
01067  */
01068 /*@{*/
01069 #define BP_CAN_CTRL1_CLKSRC  (13U)         /*!< Bit position for CAN_CTRL1_CLKSRC. */
01070 #define BM_CAN_CTRL1_CLKSRC  (0x00002000U) /*!< Bit mask for CAN_CTRL1_CLKSRC. */
01071 #define BS_CAN_CTRL1_CLKSRC  (1U)          /*!< Bit field size in bits for CAN_CTRL1_CLKSRC. */
01072 
01073 /*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
01074 #define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
01075 
01076 /*! @brief Format value for bitfield CAN_CTRL1_CLKSRC. */
01077 #define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC)
01078 
01079 /*! @brief Set the CLKSRC field to a new value. */
01080 #define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
01081 /*@}*/
01082 
01083 /*!
01084  * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
01085  *
01086  * This bit provides a mask for the Error Interrupt.
01087  *
01088  * Values:
01089  * - 0 - Error interrupt disabled.
01090  * - 1 - Error interrupt enabled.
01091  */
01092 /*@{*/
01093 #define BP_CAN_CTRL1_ERRMSK  (14U)         /*!< Bit position for CAN_CTRL1_ERRMSK. */
01094 #define BM_CAN_CTRL1_ERRMSK  (0x00004000U) /*!< Bit mask for CAN_CTRL1_ERRMSK. */
01095 #define BS_CAN_CTRL1_ERRMSK  (1U)          /*!< Bit field size in bits for CAN_CTRL1_ERRMSK. */
01096 
01097 /*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
01098 #define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
01099 
01100 /*! @brief Format value for bitfield CAN_CTRL1_ERRMSK. */
01101 #define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK)
01102 
01103 /*! @brief Set the ERRMSK field to a new value. */
01104 #define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
01105 /*@}*/
01106 
01107 /*!
01108  * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
01109  *
01110  * This bit provides a mask for the Bus Off Interrupt.
01111  *
01112  * Values:
01113  * - 0 - Bus Off interrupt disabled.
01114  * - 1 - Bus Off interrupt enabled.
01115  */
01116 /*@{*/
01117 #define BP_CAN_CTRL1_BOFFMSK (15U)         /*!< Bit position for CAN_CTRL1_BOFFMSK. */
01118 #define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /*!< Bit mask for CAN_CTRL1_BOFFMSK. */
01119 #define BS_CAN_CTRL1_BOFFMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_BOFFMSK. */
01120 
01121 /*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
01122 #define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
01123 
01124 /*! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. */
01125 #define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK)
01126 
01127 /*! @brief Set the BOFFMSK field to a new value. */
01128 #define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
01129 /*@}*/
01130 
01131 /*!
01132  * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
01133  *
01134  * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
01135  * time. The valid programmable values are 1-7. This field can be written only in
01136  * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
01137  * Segment 2 = (PSEG2 + 1) * Time-Quanta.
01138  */
01139 /*@{*/
01140 #define BP_CAN_CTRL1_PSEG2   (16U)         /*!< Bit position for CAN_CTRL1_PSEG2. */
01141 #define BM_CAN_CTRL1_PSEG2   (0x00070000U) /*!< Bit mask for CAN_CTRL1_PSEG2. */
01142 #define BS_CAN_CTRL1_PSEG2   (3U)          /*!< Bit field size in bits for CAN_CTRL1_PSEG2. */
01143 
01144 /*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
01145 #define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
01146 
01147 /*! @brief Format value for bitfield CAN_CTRL1_PSEG2. */
01148 #define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2)
01149 
01150 /*! @brief Set the PSEG2 field to a new value. */
01151 #define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
01152 /*@}*/
01153 
01154 /*!
01155  * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
01156  *
01157  * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
01158  * time. The valid programmable values are 0-7. This field can be written only in
01159  * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
01160  * Segment 1 = (PSEG1 + 1) * Time-Quanta.
01161  */
01162 /*@{*/
01163 #define BP_CAN_CTRL1_PSEG1   (19U)         /*!< Bit position for CAN_CTRL1_PSEG1. */
01164 #define BM_CAN_CTRL1_PSEG1   (0x00380000U) /*!< Bit mask for CAN_CTRL1_PSEG1. */
01165 #define BS_CAN_CTRL1_PSEG1   (3U)          /*!< Bit field size in bits for CAN_CTRL1_PSEG1. */
01166 
01167 /*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
01168 #define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
01169 
01170 /*! @brief Format value for bitfield CAN_CTRL1_PSEG1. */
01171 #define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1)
01172 
01173 /*! @brief Set the PSEG1 field to a new value. */
01174 #define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
01175 /*@}*/
01176 
01177 /*!
01178  * @name Register CAN_CTRL1, field RJW[23:22] (RW)
01179  *
01180  * This 2-bit field defines the maximum number of time quanta that a bit time
01181  * can be changed by one re-synchronization. One time quantum is equal to the
01182  * Sclock period. The valid programmable values are 0-3. This field can be written
01183  * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
01184  * Width = RJW + 1.
01185  */
01186 /*@{*/
01187 #define BP_CAN_CTRL1_RJW     (22U)         /*!< Bit position for CAN_CTRL1_RJW. */
01188 #define BM_CAN_CTRL1_RJW     (0x00C00000U) /*!< Bit mask for CAN_CTRL1_RJW. */
01189 #define BS_CAN_CTRL1_RJW     (2U)          /*!< Bit field size in bits for CAN_CTRL1_RJW. */
01190 
01191 /*! @brief Read current value of the CAN_CTRL1_RJW field. */
01192 #define BR_CAN_CTRL1_RJW(x)  (HW_CAN_CTRL1(x).B.RJW)
01193 
01194 /*! @brief Format value for bitfield CAN_CTRL1_RJW. */
01195 #define BF_CAN_CTRL1_RJW(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW)
01196 
01197 /*! @brief Set the RJW field to a new value. */
01198 #define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
01199 /*@}*/
01200 
01201 /*!
01202  * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
01203  *
01204  * This 8-bit field defines the ratio between the PE clock frequency and the
01205  * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
01206  * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
01207  * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
01208  * Sclock frequency equal to the PE clock frequency divided by 256. See Section
01209  * "Protocol Timing". This field can be written only in Freeze mode because it is
01210  * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
01211  * (PRESDIV + 1)
01212  */
01213 /*@{*/
01214 #define BP_CAN_CTRL1_PRESDIV (24U)         /*!< Bit position for CAN_CTRL1_PRESDIV. */
01215 #define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /*!< Bit mask for CAN_CTRL1_PRESDIV. */
01216 #define BS_CAN_CTRL1_PRESDIV (8U)          /*!< Bit field size in bits for CAN_CTRL1_PRESDIV. */
01217 
01218 /*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
01219 #define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
01220 
01221 /*! @brief Format value for bitfield CAN_CTRL1_PRESDIV. */
01222 #define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV)
01223 
01224 /*! @brief Set the PRESDIV field to a new value. */
01225 #define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
01226 /*@}*/
01227 
01228 /*******************************************************************************
01229  * HW_CAN_TIMER - Free Running Timer
01230  ******************************************************************************/
01231 
01232 /*!
01233  * @brief HW_CAN_TIMER - Free Running Timer (RW)
01234  *
01235  * Reset value: 0x00000000U
01236  *
01237  * This register represents a 16-bit free running counter that can be read and
01238  * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
01239  * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
01240  * defines the baud rate on the CAN bus. During a message transmission/reception,
01241  * it increments by one for each bit that is received or transmitted. When there
01242  * is no message on the bus, it counts using the previously programmed baud
01243  * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
01244  * timer value is captured when the second bit of the identifier field of any frame
01245  * is on the CAN bus. This captured value is written into the Time Stamp entry
01246  * in a message buffer after a successful reception or transmission of a message.
01247  * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
01248  * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
01249  * can write to this register anytime. However, if the write occurs at the same
01250  * time that the Timer is being reset by a reception in the first Mailbox, then
01251  * the write value is discarded. Reading this register affects the Mailbox
01252  * Unlocking procedure; see Section "Mailbox Lock Mechanism".
01253  */
01254 typedef union _hw_can_timer
01255 {
01256     uint32_t U;
01257     struct _hw_can_timer_bitfields
01258     {
01259         uint32_t TIMER : 16;           /*!< [15:0] Timer Value */
01260         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01261     } B;
01262 } hw_can_timer_t;
01263 
01264 /*!
01265  * @name Constants and macros for entire CAN_TIMER register
01266  */
01267 /*@{*/
01268 #define HW_CAN_TIMER_ADDR(x)     ((x) + 0x8U)
01269 
01270 #define HW_CAN_TIMER(x)          (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
01271 #define HW_CAN_TIMER_RD(x)       (HW_CAN_TIMER(x).U)
01272 #define HW_CAN_TIMER_WR(x, v)    (HW_CAN_TIMER(x).U = (v))
01273 #define HW_CAN_TIMER_SET(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) |  (v)))
01274 #define HW_CAN_TIMER_CLR(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
01275 #define HW_CAN_TIMER_TOG(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^  (v)))
01276 /*@}*/
01277 
01278 /*
01279  * Constants & macros for individual CAN_TIMER bitfields
01280  */
01281 
01282 /*!
01283  * @name Register CAN_TIMER, field TIMER[15:0] (RW)
01284  *
01285  * Contains the free-running counter value.
01286  */
01287 /*@{*/
01288 #define BP_CAN_TIMER_TIMER   (0U)          /*!< Bit position for CAN_TIMER_TIMER. */
01289 #define BM_CAN_TIMER_TIMER   (0x0000FFFFU) /*!< Bit mask for CAN_TIMER_TIMER. */
01290 #define BS_CAN_TIMER_TIMER   (16U)         /*!< Bit field size in bits for CAN_TIMER_TIMER. */
01291 
01292 /*! @brief Read current value of the CAN_TIMER_TIMER field. */
01293 #define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
01294 
01295 /*! @brief Format value for bitfield CAN_TIMER_TIMER. */
01296 #define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER)
01297 
01298 /*! @brief Set the TIMER field to a new value. */
01299 #define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
01300 /*@}*/
01301 
01302 /*******************************************************************************
01303  * HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
01304  ******************************************************************************/
01305 
01306 /*!
01307  * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
01308  *
01309  * Reset value: 0xFFFFFFFFU
01310  *
01311  * This register is located in RAM. RXMGMASK is provided for legacy application
01312  * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
01313  * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
01314  * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
01315  * mask registers. This register can only be written in Freeze mode as it is
01316  * blocked by hardware in other modes.
01317  */
01318 typedef union _hw_can_rxmgmask
01319 {
01320     uint32_t U;
01321     struct _hw_can_rxmgmask_bitfields
01322     {
01323         uint32_t MG : 32;              /*!< [31:0] Rx Mailboxes Global Mask Bits */
01324     } B;
01325 } hw_can_rxmgmask_t;
01326 
01327 /*!
01328  * @name Constants and macros for entire CAN_RXMGMASK register
01329  */
01330 /*@{*/
01331 #define HW_CAN_RXMGMASK_ADDR(x)  ((x) + 0x10U)
01332 
01333 #define HW_CAN_RXMGMASK(x)       (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
01334 #define HW_CAN_RXMGMASK_RD(x)    (HW_CAN_RXMGMASK(x).U)
01335 #define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
01336 #define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) |  (v)))
01337 #define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
01338 #define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^  (v)))
01339 /*@}*/
01340 
01341 /*
01342  * Constants & macros for individual CAN_RXMGMASK bitfields
01343  */
01344 
01345 /*!
01346  * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
01347  *
01348  * These bits mask the Mailbox filter bits. Note that the alignment with the ID
01349  * word of the Mailbox is not perfect as the two most significant MG bits affect
01350  * the fields RTR and IDE, which are located in the Control and Status word of
01351  * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
01352  * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
01353  * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
01354  * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
01355  * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
01356  * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
01357  * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
01358  * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
01359  * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
01360  *
01361  * Values:
01362  * - 0 - The corresponding bit in the filter is "don't care."
01363  * - 1 - The corresponding bit in the filter is checked.
01364  */
01365 /*@{*/
01366 #define BP_CAN_RXMGMASK_MG   (0U)          /*!< Bit position for CAN_RXMGMASK_MG. */
01367 #define BM_CAN_RXMGMASK_MG   (0xFFFFFFFFU) /*!< Bit mask for CAN_RXMGMASK_MG. */
01368 #define BS_CAN_RXMGMASK_MG   (32U)         /*!< Bit field size in bits for CAN_RXMGMASK_MG. */
01369 
01370 /*! @brief Read current value of the CAN_RXMGMASK_MG field. */
01371 #define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
01372 
01373 /*! @brief Format value for bitfield CAN_RXMGMASK_MG. */
01374 #define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG)
01375 
01376 /*! @brief Set the MG field to a new value. */
01377 #define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
01378 /*@}*/
01379 
01380 /*******************************************************************************
01381  * HW_CAN_RX14MASK - Rx 14 Mask register
01382  ******************************************************************************/
01383 
01384 /*!
01385  * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
01386  *
01387  * Reset value: 0xFFFFFFFFU
01388  *
01389  * This register is located in RAM. RX14MASK is provided for legacy application
01390  * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
01391  * is used to mask the filter fields of Message Buffer 14. This register can only
01392  * be programmed while the module is in Freeze mode as it is blocked by hardware
01393  * in other modes.
01394  */
01395 typedef union _hw_can_rx14mask
01396 {
01397     uint32_t U;
01398     struct _hw_can_rx14mask_bitfields
01399     {
01400         uint32_t RX14M : 32;           /*!< [31:0] Rx Buffer 14 Mask Bits */
01401     } B;
01402 } hw_can_rx14mask_t;
01403 
01404 /*!
01405  * @name Constants and macros for entire CAN_RX14MASK register
01406  */
01407 /*@{*/
01408 #define HW_CAN_RX14MASK_ADDR(x)  ((x) + 0x14U)
01409 
01410 #define HW_CAN_RX14MASK(x)       (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
01411 #define HW_CAN_RX14MASK_RD(x)    (HW_CAN_RX14MASK(x).U)
01412 #define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
01413 #define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) |  (v)))
01414 #define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
01415 #define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^  (v)))
01416 /*@}*/
01417 
01418 /*
01419  * Constants & macros for individual CAN_RX14MASK bitfields
01420  */
01421 
01422 /*!
01423  * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
01424  *
01425  * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
01426  * that RXMGMASK masks other Mailboxes' filters. See the description of the
01427  * CAN_RXMGMASK register.
01428  *
01429  * Values:
01430  * - 0 - The corresponding bit in the filter is "don't care."
01431  * - 1 - The corresponding bit in the filter is checked.
01432  */
01433 /*@{*/
01434 #define BP_CAN_RX14MASK_RX14M (0U)         /*!< Bit position for CAN_RX14MASK_RX14M. */
01435 #define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX14MASK_RX14M. */
01436 #define BS_CAN_RX14MASK_RX14M (32U)        /*!< Bit field size in bits for CAN_RX14MASK_RX14M. */
01437 
01438 /*! @brief Read current value of the CAN_RX14MASK_RX14M field. */
01439 #define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
01440 
01441 /*! @brief Format value for bitfield CAN_RX14MASK_RX14M. */
01442 #define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M)
01443 
01444 /*! @brief Set the RX14M field to a new value. */
01445 #define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
01446 /*@}*/
01447 
01448 /*******************************************************************************
01449  * HW_CAN_RX15MASK - Rx 15 Mask register
01450  ******************************************************************************/
01451 
01452 /*!
01453  * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
01454  *
01455  * Reset value: 0xFFFFFFFFU
01456  *
01457  * This register is located in RAM. RX15MASK is provided for legacy application
01458  * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
01459  * is used to mask the filter fields of Message Buffer 15. This register can be
01460  * programmed only while the module is in Freeze mode because it is blocked by
01461  * hardware in other modes.
01462  */
01463 typedef union _hw_can_rx15mask
01464 {
01465     uint32_t U;
01466     struct _hw_can_rx15mask_bitfields
01467     {
01468         uint32_t RX15M : 32;           /*!< [31:0] Rx Buffer 15 Mask Bits */
01469     } B;
01470 } hw_can_rx15mask_t;
01471 
01472 /*!
01473  * @name Constants and macros for entire CAN_RX15MASK register
01474  */
01475 /*@{*/
01476 #define HW_CAN_RX15MASK_ADDR(x)  ((x) + 0x18U)
01477 
01478 #define HW_CAN_RX15MASK(x)       (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
01479 #define HW_CAN_RX15MASK_RD(x)    (HW_CAN_RX15MASK(x).U)
01480 #define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
01481 #define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) |  (v)))
01482 #define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
01483 #define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^  (v)))
01484 /*@}*/
01485 
01486 /*
01487  * Constants & macros for individual CAN_RX15MASK bitfields
01488  */
01489 
01490 /*!
01491  * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
01492  *
01493  * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
01494  * that RXMGMASK masks other Mailboxes' filters. See the description of the
01495  * CAN_RXMGMASK register.
01496  *
01497  * Values:
01498  * - 0 - The corresponding bit in the filter is "don't care."
01499  * - 1 - The corresponding bit in the filter is checked.
01500  */
01501 /*@{*/
01502 #define BP_CAN_RX15MASK_RX15M (0U)         /*!< Bit position for CAN_RX15MASK_RX15M. */
01503 #define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX15MASK_RX15M. */
01504 #define BS_CAN_RX15MASK_RX15M (32U)        /*!< Bit field size in bits for CAN_RX15MASK_RX15M. */
01505 
01506 /*! @brief Read current value of the CAN_RX15MASK_RX15M field. */
01507 #define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
01508 
01509 /*! @brief Format value for bitfield CAN_RX15MASK_RX15M. */
01510 #define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M)
01511 
01512 /*! @brief Set the RX15M field to a new value. */
01513 #define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
01514 /*@}*/
01515 
01516 /*******************************************************************************
01517  * HW_CAN_ECR - Error Counter
01518  ******************************************************************************/
01519 
01520 /*!
01521  * @brief HW_CAN_ECR - Error Counter (RW)
01522  *
01523  * Reset value: 0x00000000U
01524  *
01525  * This register has two 8-bit fields reflecting the value of two FlexCAN error
01526  * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
01527  * (RXERRCNT field). The rules for increasing and decreasing these counters are
01528  * described in the CAN protocol and are completely implemented in the FlexCAN
01529  * module. Both counters are read-only except in Freeze mode, where they can be
01530  * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
01531  * for example, transmit Error Active or Error Passive flag, delay its
01532  * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
01533  * Off state. The following are the basic rules for FlexCAN bus state transitions:
01534  * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
01535  * 128, the FLTCONF field in the Error and Status Register is updated to reflect
01536  * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
01537  * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
01538  * other already satisfies this condition, the FLTCONF field in the Error and
01539  * Status Register is updated to reflect 'Error Active' state. If the value of
01540  * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
01541  * Register is updated to reflect 'Bus Off' state, and an interrupt may be
01542  * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
01543  * state, then TXERRCNT is cascaded together with another internal counter to count
01544  * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
01545  * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
01546  * 11 such bits and then wraps around while incrementing the TXERRCNT. When
01547  * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
01548  * Register is updated to be 'Error Active' and both error counters are reset to zero.
01549  * At any instance of dominant bit following a stream of less than 11
01550  * consecutive recessive bits, the internal counter resets itself to zero without affecting
01551  * the TXERRCNT value. If during system start-up, only one node is operating,
01552  * then its TXERRCNT increases in each message it is trying to transmit, as a
01553  * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
01554  * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
01555  * increment anymore by acknowledge errors. Therefore the device never goes to
01556  * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
01557  * is not incremented further, even if more errors are detected while being a
01558  * receiver. At the next successful message reception, the counter is set to a value
01559  * between 119 and 127 to resume to 'Error Active' state.
01560  */
01561 typedef union _hw_can_ecr
01562 {
01563     uint32_t U;
01564     struct _hw_can_ecr_bitfields
01565     {
01566         uint32_t TXERRCNT : 8;         /*!< [7:0] Transmit Error Counter */
01567         uint32_t RXERRCNT : 8;         /*!< [15:8] Receive Error Counter */
01568         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01569     } B;
01570 } hw_can_ecr_t;
01571 
01572 /*!
01573  * @name Constants and macros for entire CAN_ECR register
01574  */
01575 /*@{*/
01576 #define HW_CAN_ECR_ADDR(x)       ((x) + 0x1CU)
01577 
01578 #define HW_CAN_ECR(x)            (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
01579 #define HW_CAN_ECR_RD(x)         (HW_CAN_ECR(x).U)
01580 #define HW_CAN_ECR_WR(x, v)      (HW_CAN_ECR(x).U = (v))
01581 #define HW_CAN_ECR_SET(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) |  (v)))
01582 #define HW_CAN_ECR_CLR(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
01583 #define HW_CAN_ECR_TOG(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^  (v)))
01584 /*@}*/
01585 
01586 /*
01587  * Constants & macros for individual CAN_ECR bitfields
01588  */
01589 
01590 /*!
01591  * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
01592  */
01593 /*@{*/
01594 #define BP_CAN_ECR_TXERRCNT  (0U)          /*!< Bit position for CAN_ECR_TXERRCNT. */
01595 #define BM_CAN_ECR_TXERRCNT  (0x000000FFU) /*!< Bit mask for CAN_ECR_TXERRCNT. */
01596 #define BS_CAN_ECR_TXERRCNT  (8U)          /*!< Bit field size in bits for CAN_ECR_TXERRCNT. */
01597 
01598 /*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
01599 #define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
01600 
01601 /*! @brief Format value for bitfield CAN_ECR_TXERRCNT. */
01602 #define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT)
01603 
01604 /*! @brief Set the TXERRCNT field to a new value. */
01605 #define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
01606 /*@}*/
01607 
01608 /*!
01609  * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
01610  */
01611 /*@{*/
01612 #define BP_CAN_ECR_RXERRCNT  (8U)          /*!< Bit position for CAN_ECR_RXERRCNT. */
01613 #define BM_CAN_ECR_RXERRCNT  (0x0000FF00U) /*!< Bit mask for CAN_ECR_RXERRCNT. */
01614 #define BS_CAN_ECR_RXERRCNT  (8U)          /*!< Bit field size in bits for CAN_ECR_RXERRCNT. */
01615 
01616 /*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
01617 #define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
01618 
01619 /*! @brief Format value for bitfield CAN_ECR_RXERRCNT. */
01620 #define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT)
01621 
01622 /*! @brief Set the RXERRCNT field to a new value. */
01623 #define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
01624 /*@}*/
01625 
01626 /*******************************************************************************
01627  * HW_CAN_ESR1 - Error and Status 1 register
01628  ******************************************************************************/
01629 
01630 /*!
01631  * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
01632  *
01633  * Reset value: 0x00000000U
01634  *
01635  * This register reflects various error conditions, some general status of the
01636  * device and it is the source of interrupts to the CPU. The CPU read action
01637  * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
01638  * that occurred since the last time the CPU read this register. Bits 9-3 are
01639  * status bits. The following table shows the FlexCAN state variables and their
01640  * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
01641  * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
01642  * Transmitting 1 0 0 1 Receiving
01643  */
01644 typedef union _hw_can_esr1
01645 {
01646     uint32_t U;
01647     struct _hw_can_esr1_bitfields
01648     {
01649         uint32_t WAKINT : 1;           /*!< [0] Wake-Up Interrupt */
01650         uint32_t ERRINT : 1;           /*!< [1] Error Interrupt */
01651         uint32_t BOFFINT : 1;          /*!< [2] Bus Off Interrupt */
01652         uint32_t RX : 1;               /*!< [3] FlexCAN In Reception */
01653         uint32_t FLTCONF : 2;          /*!< [5:4] Fault Confinement State */
01654         uint32_t TX : 1;               /*!< [6] FlexCAN In Transmission */
01655         uint32_t IDLE : 1;             /*!< [7]  */
01656         uint32_t RXWRN : 1;            /*!< [8] Rx Error Warning */
01657         uint32_t TXWRN : 1;            /*!< [9] TX Error Warning */
01658         uint32_t STFERR : 1;           /*!< [10] Stuffing Error */
01659         uint32_t FRMERR : 1;           /*!< [11] Form Error */
01660         uint32_t CRCERR : 1;           /*!< [12] Cyclic Redundancy Check Error */
01661         uint32_t ACKERR : 1;           /*!< [13] Acknowledge Error */
01662         uint32_t BIT0ERR : 1;          /*!< [14] Bit0 Error */
01663         uint32_t BIT1ERR : 1;          /*!< [15] Bit1 Error */
01664         uint32_t RWRNINT : 1;          /*!< [16] Rx Warning Interrupt Flag */
01665         uint32_t TWRNINT : 1;          /*!< [17] Tx Warning Interrupt Flag */
01666         uint32_t SYNCH : 1;            /*!< [18] CAN Synchronization Status */
01667         uint32_t RESERVED0 : 13;       /*!< [31:19]  */
01668     } B;
01669 } hw_can_esr1_t;
01670 
01671 /*!
01672  * @name Constants and macros for entire CAN_ESR1 register
01673  */
01674 /*@{*/
01675 #define HW_CAN_ESR1_ADDR(x)      ((x) + 0x20U)
01676 
01677 #define HW_CAN_ESR1(x)           (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
01678 #define HW_CAN_ESR1_RD(x)        (HW_CAN_ESR1(x).U)
01679 #define HW_CAN_ESR1_WR(x, v)     (HW_CAN_ESR1(x).U = (v))
01680 #define HW_CAN_ESR1_SET(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) |  (v)))
01681 #define HW_CAN_ESR1_CLR(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
01682 #define HW_CAN_ESR1_TOG(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^  (v)))
01683 /*@}*/
01684 
01685 /*
01686  * Constants & macros for individual CAN_ESR1 bitfields
01687  */
01688 
01689 /*!
01690  * @name Register CAN_ESR1, field WAKINT[0] (W1C)
01691  *
01692  * This field applies when FlexCAN is in low-power mode under Self Wake Up
01693  * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
01694  * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
01695  * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
01696  * is masked. The CPU must clear this flag before disabling the bit. Otherwise
01697  * it will be set when the SLFWAK is set again. Writing 0 has no effect.
01698  *
01699  * Values:
01700  * - 0 - No such occurrence.
01701  * - 1 - Indicates a recessive to dominant transition was received on the CAN
01702  *     bus.
01703  */
01704 /*@{*/
01705 #define BP_CAN_ESR1_WAKINT   (0U)          /*!< Bit position for CAN_ESR1_WAKINT. */
01706 #define BM_CAN_ESR1_WAKINT   (0x00000001U) /*!< Bit mask for CAN_ESR1_WAKINT. */
01707 #define BS_CAN_ESR1_WAKINT   (1U)          /*!< Bit field size in bits for CAN_ESR1_WAKINT. */
01708 
01709 /*! @brief Read current value of the CAN_ESR1_WAKINT field. */
01710 #define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
01711 
01712 /*! @brief Format value for bitfield CAN_ESR1_WAKINT. */
01713 #define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT)
01714 
01715 /*! @brief Set the WAKINT field to a new value. */
01716 #define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
01717 /*@}*/
01718 
01719 /*!
01720  * @name Register CAN_ESR1, field ERRINT[1] (W1C)
01721  *
01722  * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
01723  * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
01724  * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
01725  *
01726  * Values:
01727  * - 0 - No such occurrence.
01728  * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
01729  */
01730 /*@{*/
01731 #define BP_CAN_ESR1_ERRINT   (1U)          /*!< Bit position for CAN_ESR1_ERRINT. */
01732 #define BM_CAN_ESR1_ERRINT   (0x00000002U) /*!< Bit mask for CAN_ESR1_ERRINT. */
01733 #define BS_CAN_ESR1_ERRINT   (1U)          /*!< Bit field size in bits for CAN_ESR1_ERRINT. */
01734 
01735 /*! @brief Read current value of the CAN_ESR1_ERRINT field. */
01736 #define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
01737 
01738 /*! @brief Format value for bitfield CAN_ESR1_ERRINT. */
01739 #define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT)
01740 
01741 /*! @brief Set the ERRINT field to a new value. */
01742 #define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
01743 /*@}*/
01744 
01745 /*!
01746  * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
01747  *
01748  * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
01749  * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
01750  * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
01751  *
01752  * Values:
01753  * - 0 - No such occurrence.
01754  * - 1 - FlexCAN module entered Bus Off state.
01755  */
01756 /*@{*/
01757 #define BP_CAN_ESR1_BOFFINT  (2U)          /*!< Bit position for CAN_ESR1_BOFFINT. */
01758 #define BM_CAN_ESR1_BOFFINT  (0x00000004U) /*!< Bit mask for CAN_ESR1_BOFFINT. */
01759 #define BS_CAN_ESR1_BOFFINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_BOFFINT. */
01760 
01761 /*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
01762 #define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
01763 
01764 /*! @brief Format value for bitfield CAN_ESR1_BOFFINT. */
01765 #define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT)
01766 
01767 /*! @brief Set the BOFFINT field to a new value. */
01768 #define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
01769 /*@}*/
01770 
01771 /*!
01772  * @name Register CAN_ESR1, field RX[3] (RO)
01773  *
01774  * This bit indicates if FlexCAN is receiving a message. See the table in the
01775  * overall CAN_ESR1 register description.
01776  *
01777  * Values:
01778  * - 0 - FlexCAN is not receiving a message.
01779  * - 1 - FlexCAN is receiving a message.
01780  */
01781 /*@{*/
01782 #define BP_CAN_ESR1_RX       (3U)          /*!< Bit position for CAN_ESR1_RX. */
01783 #define BM_CAN_ESR1_RX       (0x00000008U) /*!< Bit mask for CAN_ESR1_RX. */
01784 #define BS_CAN_ESR1_RX       (1U)          /*!< Bit field size in bits for CAN_ESR1_RX. */
01785 
01786 /*! @brief Read current value of the CAN_ESR1_RX field. */
01787 #define BR_CAN_ESR1_RX(x)    (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
01788 /*@}*/
01789 
01790 /*!
01791  * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
01792  *
01793  * This 2-bit field indicates the Confinement State of the FlexCAN module. If
01794  * the LOM bit in the Control Register is asserted, after some delay that depends
01795  * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
01796  * same delay affects the way how FLTCONF reflects an update to ECR register by
01797  * the CPU. It may be necessary up to one CAN bit time to get them coherent
01798  * again. Because the Control Register is not affected by soft reset, the FLTCONF
01799  * field will not be affected by soft reset if the LOM bit is asserted.
01800  *
01801  * Values:
01802  * - 00 - Error Active
01803  * - 01 - Error Passive
01804  * - 1x - Bus Off
01805  */
01806 /*@{*/
01807 #define BP_CAN_ESR1_FLTCONF  (4U)          /*!< Bit position for CAN_ESR1_FLTCONF. */
01808 #define BM_CAN_ESR1_FLTCONF  (0x00000030U) /*!< Bit mask for CAN_ESR1_FLTCONF. */
01809 #define BS_CAN_ESR1_FLTCONF  (2U)          /*!< Bit field size in bits for CAN_ESR1_FLTCONF. */
01810 
01811 /*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
01812 #define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
01813 /*@}*/
01814 
01815 /*!
01816  * @name Register CAN_ESR1, field TX[6] (RO)
01817  *
01818  * This bit indicates if FlexCAN is transmitting a message. See the table in the
01819  * overall CAN_ESR1 register description.
01820  *
01821  * Values:
01822  * - 0 - FlexCAN is not transmitting a message.
01823  * - 1 - FlexCAN is transmitting a message.
01824  */
01825 /*@{*/
01826 #define BP_CAN_ESR1_TX       (6U)          /*!< Bit position for CAN_ESR1_TX. */
01827 #define BM_CAN_ESR1_TX       (0x00000040U) /*!< Bit mask for CAN_ESR1_TX. */
01828 #define BS_CAN_ESR1_TX       (1U)          /*!< Bit field size in bits for CAN_ESR1_TX. */
01829 
01830 /*! @brief Read current value of the CAN_ESR1_TX field. */
01831 #define BR_CAN_ESR1_TX(x)    (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
01832 /*@}*/
01833 
01834 /*!
01835  * @name Register CAN_ESR1, field IDLE[7] (RO)
01836  *
01837  * This bit indicates when CAN bus is in IDLE state. See the table in the
01838  * overall CAN_ESR1 register description.
01839  *
01840  * Values:
01841  * - 0 - No such occurrence.
01842  * - 1 - CAN bus is now IDLE.
01843  */
01844 /*@{*/
01845 #define BP_CAN_ESR1_IDLE     (7U)          /*!< Bit position for CAN_ESR1_IDLE. */
01846 #define BM_CAN_ESR1_IDLE     (0x00000080U) /*!< Bit mask for CAN_ESR1_IDLE. */
01847 #define BS_CAN_ESR1_IDLE     (1U)          /*!< Bit field size in bits for CAN_ESR1_IDLE. */
01848 
01849 /*! @brief Read current value of the CAN_ESR1_IDLE field. */
01850 #define BR_CAN_ESR1_IDLE(x)  (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
01851 /*@}*/
01852 
01853 /*!
01854  * @name Register CAN_ESR1, field RXWRN[8] (RO)
01855  *
01856  * This bit indicates when repetitive errors are occurring during message
01857  * reception. This bit is not updated during Freeze mode.
01858  *
01859  * Values:
01860  * - 0 - No such occurrence.
01861  * - 1 - RXERRCNT is greater than or equal to 96.
01862  */
01863 /*@{*/
01864 #define BP_CAN_ESR1_RXWRN    (8U)          /*!< Bit position for CAN_ESR1_RXWRN. */
01865 #define BM_CAN_ESR1_RXWRN    (0x00000100U) /*!< Bit mask for CAN_ESR1_RXWRN. */
01866 #define BS_CAN_ESR1_RXWRN    (1U)          /*!< Bit field size in bits for CAN_ESR1_RXWRN. */
01867 
01868 /*! @brief Read current value of the CAN_ESR1_RXWRN field. */
01869 #define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
01870 /*@}*/
01871 
01872 /*!
01873  * @name Register CAN_ESR1, field TXWRN[9] (RO)
01874  *
01875  * This bit indicates when repetitive errors are occurring during message
01876  * transmission. This bit is not updated during Freeze mode.
01877  *
01878  * Values:
01879  * - 0 - No such occurrence.
01880  * - 1 - TXERRCNT is greater than or equal to 96.
01881  */
01882 /*@{*/
01883 #define BP_CAN_ESR1_TXWRN    (9U)          /*!< Bit position for CAN_ESR1_TXWRN. */
01884 #define BM_CAN_ESR1_TXWRN    (0x00000200U) /*!< Bit mask for CAN_ESR1_TXWRN. */
01885 #define BS_CAN_ESR1_TXWRN    (1U)          /*!< Bit field size in bits for CAN_ESR1_TXWRN. */
01886 
01887 /*! @brief Read current value of the CAN_ESR1_TXWRN field. */
01888 #define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
01889 /*@}*/
01890 
01891 /*!
01892  * @name Register CAN_ESR1, field STFERR[10] (RO)
01893  *
01894  * This bit indicates that a Stuffing Error has been etected.
01895  *
01896  * Values:
01897  * - 0 - No such occurrence.
01898  * - 1 - A Stuffing Error occurred since last read of this register.
01899  */
01900 /*@{*/
01901 #define BP_CAN_ESR1_STFERR   (10U)         /*!< Bit position for CAN_ESR1_STFERR. */
01902 #define BM_CAN_ESR1_STFERR   (0x00000400U) /*!< Bit mask for CAN_ESR1_STFERR. */
01903 #define BS_CAN_ESR1_STFERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_STFERR. */
01904 
01905 /*! @brief Read current value of the CAN_ESR1_STFERR field. */
01906 #define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
01907 /*@}*/
01908 
01909 /*!
01910  * @name Register CAN_ESR1, field FRMERR[11] (RO)
01911  *
01912  * This bit indicates that a Form Error has been detected by the receiver node,
01913  * that is, a fixed-form bit field contains at least one illegal bit.
01914  *
01915  * Values:
01916  * - 0 - No such occurrence.
01917  * - 1 - A Form Error occurred since last read of this register.
01918  */
01919 /*@{*/
01920 #define BP_CAN_ESR1_FRMERR   (11U)         /*!< Bit position for CAN_ESR1_FRMERR. */
01921 #define BM_CAN_ESR1_FRMERR   (0x00000800U) /*!< Bit mask for CAN_ESR1_FRMERR. */
01922 #define BS_CAN_ESR1_FRMERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_FRMERR. */
01923 
01924 /*! @brief Read current value of the CAN_ESR1_FRMERR field. */
01925 #define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
01926 /*@}*/
01927 
01928 /*!
01929  * @name Register CAN_ESR1, field CRCERR[12] (RO)
01930  *
01931  * This bit indicates that a CRC Error has been detected by the receiver node,
01932  * that is, the calculated CRC is different from the received.
01933  *
01934  * Values:
01935  * - 0 - No such occurrence.
01936  * - 1 - A CRC error occurred since last read of this register.
01937  */
01938 /*@{*/
01939 #define BP_CAN_ESR1_CRCERR   (12U)         /*!< Bit position for CAN_ESR1_CRCERR. */
01940 #define BM_CAN_ESR1_CRCERR   (0x00001000U) /*!< Bit mask for CAN_ESR1_CRCERR. */
01941 #define BS_CAN_ESR1_CRCERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_CRCERR. */
01942 
01943 /*! @brief Read current value of the CAN_ESR1_CRCERR field. */
01944 #define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
01945 /*@}*/
01946 
01947 /*!
01948  * @name Register CAN_ESR1, field ACKERR[13] (RO)
01949  *
01950  * This bit indicates that an Acknowledge Error has been detected by the
01951  * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
01952  *
01953  * Values:
01954  * - 0 - No such occurrence.
01955  * - 1 - An ACK error occurred since last read of this register.
01956  */
01957 /*@{*/
01958 #define BP_CAN_ESR1_ACKERR   (13U)         /*!< Bit position for CAN_ESR1_ACKERR. */
01959 #define BM_CAN_ESR1_ACKERR   (0x00002000U) /*!< Bit mask for CAN_ESR1_ACKERR. */
01960 #define BS_CAN_ESR1_ACKERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_ACKERR. */
01961 
01962 /*! @brief Read current value of the CAN_ESR1_ACKERR field. */
01963 #define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
01964 /*@}*/
01965 
01966 /*!
01967  * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
01968  *
01969  * This bit indicates when an inconsistency occurs between the transmitted and
01970  * the received bit in a message.
01971  *
01972  * Values:
01973  * - 0 - No such occurrence.
01974  * - 1 - At least one bit sent as dominant is received as recessive.
01975  */
01976 /*@{*/
01977 #define BP_CAN_ESR1_BIT0ERR  (14U)         /*!< Bit position for CAN_ESR1_BIT0ERR. */
01978 #define BM_CAN_ESR1_BIT0ERR  (0x00004000U) /*!< Bit mask for CAN_ESR1_BIT0ERR. */
01979 #define BS_CAN_ESR1_BIT0ERR  (1U)          /*!< Bit field size in bits for CAN_ESR1_BIT0ERR. */
01980 
01981 /*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
01982 #define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
01983 /*@}*/
01984 
01985 /*!
01986  * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
01987  *
01988  * This bit indicates when an inconsistency occurs between the transmitted and
01989  * the received bit in a message. This bit is not set by a transmitter in case of
01990  * arbitration field or ACK slot, or in case of a node sending a passive error
01991  * flag that detects dominant bits.
01992  *
01993  * Values:
01994  * - 0 - No such occurrence.
01995  * - 1 - At least one bit sent as recessive is received as dominant.
01996  */
01997 /*@{*/
01998 #define BP_CAN_ESR1_BIT1ERR  (15U)         /*!< Bit position for CAN_ESR1_BIT1ERR. */
01999 #define BM_CAN_ESR1_BIT1ERR  (0x00008000U) /*!< Bit mask for CAN_ESR1_BIT1ERR. */
02000 #define BS_CAN_ESR1_BIT1ERR  (1U)          /*!< Bit field size in bits for CAN_ESR1_BIT1ERR. */
02001 
02002 /*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
02003 #define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
02004 /*@}*/
02005 
02006 /*!
02007  * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
02008  *
02009  * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
02010  * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
02011  * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
02012  * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
02013  * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
02014  * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
02015  * effect. This bit is not updated during Freeze mode.
02016  *
02017  * Values:
02018  * - 0 - No such occurrence.
02019  * - 1 - The Rx error counter transitioned from less than 96 to greater than or
02020  *     equal to 96.
02021  */
02022 /*@{*/
02023 #define BP_CAN_ESR1_RWRNINT  (16U)         /*!< Bit position for CAN_ESR1_RWRNINT. */
02024 #define BM_CAN_ESR1_RWRNINT  (0x00010000U) /*!< Bit mask for CAN_ESR1_RWRNINT. */
02025 #define BS_CAN_ESR1_RWRNINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_RWRNINT. */
02026 
02027 /*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
02028 #define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
02029 
02030 /*! @brief Format value for bitfield CAN_ESR1_RWRNINT. */
02031 #define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT)
02032 
02033 /*! @brief Set the RWRNINT field to a new value. */
02034 #define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
02035 /*@}*/
02036 
02037 /*!
02038  * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
02039  *
02040  * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
02041  * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
02042  * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
02043  * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
02044  * is negated, this flag is masked. CPU must clear this flag before disabling
02045  * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
02046  * effect. This flag is not generated during Bus Off state. This bit is not
02047  * updated during Freeze mode.
02048  *
02049  * Values:
02050  * - 0 - No such occurrence.
02051  * - 1 - The Tx error counter transitioned from less than 96 to greater than or
02052  *     equal to 96.
02053  */
02054 /*@{*/
02055 #define BP_CAN_ESR1_TWRNINT  (17U)         /*!< Bit position for CAN_ESR1_TWRNINT. */
02056 #define BM_CAN_ESR1_TWRNINT  (0x00020000U) /*!< Bit mask for CAN_ESR1_TWRNINT. */
02057 #define BS_CAN_ESR1_TWRNINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_TWRNINT. */
02058 
02059 /*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
02060 #define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
02061 
02062 /*! @brief Format value for bitfield CAN_ESR1_TWRNINT. */
02063 #define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT)
02064 
02065 /*! @brief Set the TWRNINT field to a new value. */
02066 #define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
02067 /*@}*/
02068 
02069 /*!
02070  * @name Register CAN_ESR1, field SYNCH[18] (RO)
02071  *
02072  * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
02073  * bus and able to participate in the communication process. It is set and
02074  * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
02075  *
02076  * Values:
02077  * - 0 - FlexCAN is not synchronized to the CAN bus.
02078  * - 1 - FlexCAN is synchronized to the CAN bus.
02079  */
02080 /*@{*/
02081 #define BP_CAN_ESR1_SYNCH    (18U)         /*!< Bit position for CAN_ESR1_SYNCH. */
02082 #define BM_CAN_ESR1_SYNCH    (0x00040000U) /*!< Bit mask for CAN_ESR1_SYNCH. */
02083 #define BS_CAN_ESR1_SYNCH    (1U)          /*!< Bit field size in bits for CAN_ESR1_SYNCH. */
02084 
02085 /*! @brief Read current value of the CAN_ESR1_SYNCH field. */
02086 #define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
02087 /*@}*/
02088 
02089 /*******************************************************************************
02090  * HW_CAN_IMASK1 - Interrupt Masks 1 register
02091  ******************************************************************************/
02092 
02093 /*!
02094  * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
02095  *
02096  * Reset value: 0x00000000U
02097  *
02098  * This register allows any number of a range of the 32 Message Buffer
02099  * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
02100  * bit per buffer, enabling the CPU to determine which buffer generates an
02101  * interrupt after a successful transmission or reception, that is, when the
02102  * corresponding IFLAG1 bit is set.
02103  */
02104 typedef union _hw_can_imask1
02105 {
02106     uint32_t U;
02107     struct _hw_can_imask1_bitfields
02108     {
02109         uint32_t BUFLM : 32;           /*!< [31:0] Buffer MB i Mask */
02110     } B;
02111 } hw_can_imask1_t;
02112 
02113 /*!
02114  * @name Constants and macros for entire CAN_IMASK1 register
02115  */
02116 /*@{*/
02117 #define HW_CAN_IMASK1_ADDR(x)    ((x) + 0x28U)
02118 
02119 #define HW_CAN_IMASK1(x)         (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
02120 #define HW_CAN_IMASK1_RD(x)      (HW_CAN_IMASK1(x).U)
02121 #define HW_CAN_IMASK1_WR(x, v)   (HW_CAN_IMASK1(x).U = (v))
02122 #define HW_CAN_IMASK1_SET(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) |  (v)))
02123 #define HW_CAN_IMASK1_CLR(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
02124 #define HW_CAN_IMASK1_TOG(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^  (v)))
02125 /*@}*/
02126 
02127 /*
02128  * Constants & macros for individual CAN_IMASK1 bitfields
02129  */
02130 
02131 /*!
02132  * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
02133  *
02134  * Each bit enables or disables the corresponding FlexCAN Message Buffer
02135  * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
02136  * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
02137  *
02138  * Values:
02139  * - 0 - The corresponding buffer Interrupt is disabled.
02140  * - 1 - The corresponding buffer Interrupt is enabled.
02141  */
02142 /*@{*/
02143 #define BP_CAN_IMASK1_BUFLM  (0U)          /*!< Bit position for CAN_IMASK1_BUFLM. */
02144 #define BM_CAN_IMASK1_BUFLM  (0xFFFFFFFFU) /*!< Bit mask for CAN_IMASK1_BUFLM. */
02145 #define BS_CAN_IMASK1_BUFLM  (32U)         /*!< Bit field size in bits for CAN_IMASK1_BUFLM. */
02146 
02147 /*! @brief Read current value of the CAN_IMASK1_BUFLM field. */
02148 #define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
02149 
02150 /*! @brief Format value for bitfield CAN_IMASK1_BUFLM. */
02151 #define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM)
02152 
02153 /*! @brief Set the BUFLM field to a new value. */
02154 #define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
02155 /*@}*/
02156 
02157 /*******************************************************************************
02158  * HW_CAN_IFLAG1 - Interrupt Flags 1 register
02159  ******************************************************************************/
02160 
02161 /*!
02162  * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
02163  *
02164  * Reset value: 0x00000000U
02165  *
02166  * This register defines the flags for the 32 Message Buffer interrupts for MB31
02167  * to MB0. It contains one interrupt flag bit per buffer. Each successful
02168  * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
02169  * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
02170  * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
02171  * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
02172  * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
02173  * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
02174  * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
02175  * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
02176  * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
02177  * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
02178  * the FIFO flags must be cleared. The same care must be taken when an RFFN
02179  * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
02180  * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
02181  * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
02182  * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
02183  * they will remain set and be inconsistent with the number of MBs available.
02184  */
02185 typedef union _hw_can_iflag1
02186 {
02187     uint32_t U;
02188     struct _hw_can_iflag1_bitfields
02189     {
02190         uint32_t BUF0I : 1;            /*!< [0] Buffer MB0 Interrupt Or "reserved" */
02191         uint32_t BUF4TO1I : 4;         /*!< [4:1] Buffer MB i Interrupt Or "reserved"
02192                                         * */
02193         uint32_t BUF5I : 1;            /*!< [5] Buffer MB5 Interrupt Or "Frames
02194                                         * available in Rx FIFO" */
02195         uint32_t BUF6I : 1;            /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO
02196                                         * Warning" */
02197         uint32_t BUF7I : 1;            /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO
02198                                         * Overflow" */
02199         uint32_t BUF31TO8I : 24;       /*!< [31:8] Buffer MBi Interrupt */
02200     } B;
02201 } hw_can_iflag1_t;
02202 
02203 /*!
02204  * @name Constants and macros for entire CAN_IFLAG1 register
02205  */
02206 /*@{*/
02207 #define HW_CAN_IFLAG1_ADDR(x)    ((x) + 0x30U)
02208 
02209 #define HW_CAN_IFLAG1(x)         (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
02210 #define HW_CAN_IFLAG1_RD(x)      (HW_CAN_IFLAG1(x).U)
02211 #define HW_CAN_IFLAG1_WR(x, v)   (HW_CAN_IFLAG1(x).U = (v))
02212 #define HW_CAN_IFLAG1_SET(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) |  (v)))
02213 #define HW_CAN_IFLAG1_CLR(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
02214 #define HW_CAN_IFLAG1_TOG(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^  (v)))
02215 /*@}*/
02216 
02217 /*
02218  * Constants & macros for individual CAN_IFLAG1 bitfields
02219  */
02220 
02221 /*!
02222  * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
02223  *
02224  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02225  * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
02226  * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
02227  * set.
02228  *
02229  * Values:
02230  * - 0 - The corresponding buffer has no occurrence of successfully completed
02231  *     transmission or reception when MCR[RFEN]=0.
02232  * - 1 - The corresponding buffer has successfully completed transmission or
02233  *     reception when MCR[RFEN]=0.
02234  */
02235 /*@{*/
02236 #define BP_CAN_IFLAG1_BUF0I  (0U)          /*!< Bit position for CAN_IFLAG1_BUF0I. */
02237 #define BM_CAN_IFLAG1_BUF0I  (0x00000001U) /*!< Bit mask for CAN_IFLAG1_BUF0I. */
02238 #define BS_CAN_IFLAG1_BUF0I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF0I. */
02239 
02240 /*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
02241 #define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
02242 
02243 /*! @brief Format value for bitfield CAN_IFLAG1_BUF0I. */
02244 #define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I)
02245 
02246 /*! @brief Set the BUF0I field to a new value. */
02247 #define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
02248 /*@}*/
02249 
02250 /*!
02251  * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
02252  *
02253  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
02254  * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
02255  * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
02256  * when MCR[RFEN] is set.
02257  *
02258  * Values:
02259  * - 0 - The corresponding buffer has no occurrence of successfully completed
02260  *     transmission or reception when MCR[RFEN]=0.
02261  * - 1 - The corresponding buffer has successfully completed transmission or
02262  *     reception when MCR[RFEN]=0.
02263  */
02264 /*@{*/
02265 #define BP_CAN_IFLAG1_BUF4TO1I (1U)        /*!< Bit position for CAN_IFLAG1_BUF4TO1I. */
02266 #define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /*!< Bit mask for CAN_IFLAG1_BUF4TO1I. */
02267 #define BS_CAN_IFLAG1_BUF4TO1I (4U)        /*!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. */
02268 
02269 /*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
02270 #define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
02271 
02272 /*! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. */
02273 #define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I)
02274 
02275 /*! @brief Set the BUF4TO1I field to a new value. */
02276 #define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
02277 /*@}*/
02278 
02279 /*!
02280  * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
02281  *
02282  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02283  * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
02284  * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
02285  * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
02286  * least one frame is available to be read from the Rx FIFO.
02287  *
02288  * Values:
02289  * - 0 - No occurrence of MB5 completing transmission/reception when
02290  *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
02291  * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
02292  *     available in the Rx FIFO when MCR[RFEN]=1
02293  */
02294 /*@{*/
02295 #define BP_CAN_IFLAG1_BUF5I  (5U)          /*!< Bit position for CAN_IFLAG1_BUF5I. */
02296 #define BM_CAN_IFLAG1_BUF5I  (0x00000020U) /*!< Bit mask for CAN_IFLAG1_BUF5I. */
02297 #define BS_CAN_IFLAG1_BUF5I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF5I. */
02298 
02299 /*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
02300 #define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
02301 
02302 /*! @brief Format value for bitfield CAN_IFLAG1_BUF5I. */
02303 #define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I)
02304 
02305 /*! @brief Set the BUF5I field to a new value. */
02306 #define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
02307 /*@}*/
02308 
02309 /*!
02310  * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
02311  *
02312  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02313  * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
02314  * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
02315  * when MCR[RFEN] is set. In this case, the flag indicates when the number of
02316  * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
02317  * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
02318  * cleared while the number of unread messages is greater than 4, it does not
02319  * assert again until the number of unread messages within the Rx FIFO is decreased
02320  * to be equal to or less than 4.
02321  *
02322  * Values:
02323  * - 0 - No occurrence of MB6 completing transmission/reception when
02324  *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
02325  * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
02326  *     almost full when MCR[RFEN]=1
02327  */
02328 /*@{*/
02329 #define BP_CAN_IFLAG1_BUF6I  (6U)          /*!< Bit position for CAN_IFLAG1_BUF6I. */
02330 #define BM_CAN_IFLAG1_BUF6I  (0x00000040U) /*!< Bit mask for CAN_IFLAG1_BUF6I. */
02331 #define BS_CAN_IFLAG1_BUF6I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF6I. */
02332 
02333 /*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
02334 #define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
02335 
02336 /*! @brief Format value for bitfield CAN_IFLAG1_BUF6I. */
02337 #define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I)
02338 
02339 /*! @brief Set the BUF6I field to a new value. */
02340 #define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
02341 /*@}*/
02342 
02343 /*!
02344  * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
02345  *
02346  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02347  * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
02348  * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
02349  * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
02350  * because the Rx FIFO is full. Note that the flag will not be asserted when the
02351  * Rx FIFO is full and the message was captured by a Mailbox.
02352  *
02353  * Values:
02354  * - 0 - No occurrence of MB7 completing transmission/reception when
02355  *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
02356  * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
02357  *     overflow when MCR[RFEN]=1
02358  */
02359 /*@{*/
02360 #define BP_CAN_IFLAG1_BUF7I  (7U)          /*!< Bit position for CAN_IFLAG1_BUF7I. */
02361 #define BM_CAN_IFLAG1_BUF7I  (0x00000080U) /*!< Bit mask for CAN_IFLAG1_BUF7I. */
02362 #define BS_CAN_IFLAG1_BUF7I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF7I. */
02363 
02364 /*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
02365 #define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
02366 
02367 /*! @brief Format value for bitfield CAN_IFLAG1_BUF7I. */
02368 #define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I)
02369 
02370 /*! @brief Set the BUF7I field to a new value. */
02371 #define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
02372 /*@}*/
02373 
02374 /*!
02375  * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
02376  *
02377  * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
02378  * MB8.
02379  *
02380  * Values:
02381  * - 0 - The corresponding buffer has no occurrence of successfully completed
02382  *     transmission or reception.
02383  * - 1 - The corresponding buffer has successfully completed transmission or
02384  *     reception.
02385  */
02386 /*@{*/
02387 #define BP_CAN_IFLAG1_BUF31TO8I (8U)       /*!< Bit position for CAN_IFLAG1_BUF31TO8I. */
02388 #define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /*!< Bit mask for CAN_IFLAG1_BUF31TO8I. */
02389 #define BS_CAN_IFLAG1_BUF31TO8I (24U)      /*!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. */
02390 
02391 /*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
02392 #define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
02393 
02394 /*! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. */
02395 #define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I)
02396 
02397 /*! @brief Set the BUF31TO8I field to a new value. */
02398 #define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
02399 /*@}*/
02400 
02401 /*******************************************************************************
02402  * HW_CAN_CTRL2 - Control 2 register
02403  ******************************************************************************/
02404 
02405 /*!
02406  * @brief HW_CAN_CTRL2 - Control 2 register (RW)
02407  *
02408  * Reset value: 0x00B00000U
02409  *
02410  * This register contains control bits for CAN errors, FIFO features, and mode
02411  * selection.
02412  */
02413 typedef union _hw_can_ctrl2
02414 {
02415     uint32_t U;
02416     struct _hw_can_ctrl2_bitfields
02417     {
02418         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
02419         uint32_t EACEN : 1;            /*!< [16] Entire Frame Arbitration Field
02420                                         * Comparison Enable For Rx Mailboxes */
02421         uint32_t RRS : 1;              /*!< [17] Remote Request Storing */
02422         uint32_t MRP : 1;              /*!< [18] Mailboxes Reception Priority */
02423         uint32_t TASD : 5;             /*!< [23:19] Tx Arbitration Start Delay */
02424         uint32_t RFFN : 4;             /*!< [27:24] Number Of Rx FIFO Filters */
02425         uint32_t WRMFRZ : 1;           /*!< [28] Write-Access To Memory In Freeze Mode
02426                                         * */
02427         uint32_t RESERVED1 : 3;        /*!< [31:29]  */
02428     } B;
02429 } hw_can_ctrl2_t;
02430 
02431 /*!
02432  * @name Constants and macros for entire CAN_CTRL2 register
02433  */
02434 /*@{*/
02435 #define HW_CAN_CTRL2_ADDR(x)     ((x) + 0x34U)
02436 
02437 #define HW_CAN_CTRL2(x)          (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
02438 #define HW_CAN_CTRL2_RD(x)       (HW_CAN_CTRL2(x).U)
02439 #define HW_CAN_CTRL2_WR(x, v)    (HW_CAN_CTRL2(x).U = (v))
02440 #define HW_CAN_CTRL2_SET(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) |  (v)))
02441 #define HW_CAN_CTRL2_CLR(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
02442 #define HW_CAN_CTRL2_TOG(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^  (v)))
02443 /*@}*/
02444 
02445 /*
02446  * Constants & macros for individual CAN_CTRL2 bitfields
02447  */
02448 
02449 /*!
02450  * @name Register CAN_CTRL2, field EACEN[16] (RW)
02451  *
02452  * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
02453  * filters with their corresponding bits in the incoming frame by the matching
02454  * process. This bit does not affect matching for Rx FIFO. This bit can be written
02455  * only in Freeze mode because it is blocked by hardware in other modes.
02456  *
02457  * Values:
02458  * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
02459  *     compared despite mask bits.
02460  * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
02461  *     their corresponding bits within the incoming frame. Mask bits do apply.
02462  */
02463 /*@{*/
02464 #define BP_CAN_CTRL2_EACEN   (16U)         /*!< Bit position for CAN_CTRL2_EACEN. */
02465 #define BM_CAN_CTRL2_EACEN   (0x00010000U) /*!< Bit mask for CAN_CTRL2_EACEN. */
02466 #define BS_CAN_CTRL2_EACEN   (1U)          /*!< Bit field size in bits for CAN_CTRL2_EACEN. */
02467 
02468 /*! @brief Read current value of the CAN_CTRL2_EACEN field. */
02469 #define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
02470 
02471 /*! @brief Format value for bitfield CAN_CTRL2_EACEN. */
02472 #define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN)
02473 
02474 /*! @brief Set the EACEN field to a new value. */
02475 #define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
02476 /*@}*/
02477 
02478 /*!
02479  * @name Register CAN_CTRL2, field RRS[17] (RW)
02480  *
02481  * If this bit is asserted Remote Request Frame is submitted to a matching
02482  * process and stored in the corresponding Message Buffer in the same fashion of a
02483  * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
02484  * negated the Remote Request Frame is submitted to a matching process and an
02485  * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
02486  * is found with the same ID. This bit can be written only in Freeze mode
02487  * because it is blocked by hardware in other modes.
02488  *
02489  * Values:
02490  * - 0 - Remote Response Frame is generated.
02491  * - 1 - Remote Request Frame is stored.
02492  */
02493 /*@{*/
02494 #define BP_CAN_CTRL2_RRS     (17U)         /*!< Bit position for CAN_CTRL2_RRS. */
02495 #define BM_CAN_CTRL2_RRS     (0x00020000U) /*!< Bit mask for CAN_CTRL2_RRS. */
02496 #define BS_CAN_CTRL2_RRS     (1U)          /*!< Bit field size in bits for CAN_CTRL2_RRS. */
02497 
02498 /*! @brief Read current value of the CAN_CTRL2_RRS field. */
02499 #define BR_CAN_CTRL2_RRS(x)  (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
02500 
02501 /*! @brief Format value for bitfield CAN_CTRL2_RRS. */
02502 #define BF_CAN_CTRL2_RRS(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS)
02503 
02504 /*! @brief Set the RRS field to a new value. */
02505 #define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
02506 /*@}*/
02507 
02508 /*!
02509  * @name Register CAN_CTRL2, field MRP[18] (RW)
02510  *
02511  * If this bit is set the matching process starts from the Mailboxes and if no
02512  * match occurs the matching continues on the Rx FIFO. This bit can be written
02513  * only in Freeze mode because it is blocked by hardware in other modes.
02514  *
02515  * Values:
02516  * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
02517  * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
02518  */
02519 /*@{*/
02520 #define BP_CAN_CTRL2_MRP     (18U)         /*!< Bit position for CAN_CTRL2_MRP. */
02521 #define BM_CAN_CTRL2_MRP     (0x00040000U) /*!< Bit mask for CAN_CTRL2_MRP. */
02522 #define BS_CAN_CTRL2_MRP     (1U)          /*!< Bit field size in bits for CAN_CTRL2_MRP. */
02523 
02524 /*! @brief Read current value of the CAN_CTRL2_MRP field. */
02525 #define BR_CAN_CTRL2_MRP(x)  (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
02526 
02527 /*! @brief Format value for bitfield CAN_CTRL2_MRP. */
02528 #define BF_CAN_CTRL2_MRP(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP)
02529 
02530 /*! @brief Set the MRP field to a new value. */
02531 #define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
02532 /*@}*/
02533 
02534 /*!
02535  * @name Register CAN_CTRL2, field TASD[23:19] (RW)
02536  *
02537  * This 5-bit field indicates how many CAN bits the Tx arbitration process start
02538  * point can be delayed from the first bit of CRC field on CAN bus. This field
02539  * can be written only in Freeze mode because it is blocked by hardware in other
02540  * modes. This field is useful to optimize the transmit performance based on
02541  * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
02542  * The duration of an arbitration process, in terms of CAN bits, is directly
02543  * proportional to the number of available MBs and CAN baud rate and inversely
02544  * proportional to the peripheral clock frequency. The optimal arbitration timing is
02545  * that in which the last MB is scanned right before the first bit of the
02546  * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
02547  * clock ratio is high and the CAN baud rate is low then the arbitration can be
02548  * delayed and vice-versa. If TASD is 0 then the arbitration start is not
02549  * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
02550  * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
02551  * the CPU can configure a Tx MB later and less time is reserved for
02552  * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
02553  * to find winner MBs in time to compete with other nodes for the CAN bus. If the
02554  * arbitration ends too much time before the first bit of Intermission field then
02555  * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
02556  * not the best to be transmitted. The optimal configuration for TASD can be
02557  * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
02558  * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
02559  * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
02560  * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
02561  * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
02562  * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
02563  * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
02564  * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
02565  * Timing" for more details.
02566  */
02567 /*@{*/
02568 #define BP_CAN_CTRL2_TASD    (19U)         /*!< Bit position for CAN_CTRL2_TASD. */
02569 #define BM_CAN_CTRL2_TASD    (0x00F80000U) /*!< Bit mask for CAN_CTRL2_TASD. */
02570 #define BS_CAN_CTRL2_TASD    (5U)          /*!< Bit field size in bits for CAN_CTRL2_TASD. */
02571 
02572 /*! @brief Read current value of the CAN_CTRL2_TASD field. */
02573 #define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
02574 
02575 /*! @brief Format value for bitfield CAN_CTRL2_TASD. */
02576 #define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD)
02577 
02578 /*! @brief Set the TASD field to a new value. */
02579 #define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
02580 /*@}*/
02581 
02582 /*!
02583  * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
02584  *
02585  * This 4-bit field defines the number of Rx FIFO filters, as shown in the
02586  * following table. The maximum selectable number of filters is determined by the MCU.
02587  * This field can only be written in Freeze mode as it is blocked by hardware in
02588  * other modes. This field must not be programmed with values that make the
02589  * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
02590  * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
02591  * a memory space equivalent to two Message Buffers which means that the more
02592  * filters are implemented the less Mailboxes will be available. Considering that
02593  * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
02594  * be programmed with a value correponding to a number of filters not greater
02595  * than the number of available memory words which can be calculated as follows:
02596  * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
02597  * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
02598  * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
02599  * SETUP_MB value (memory space available) the exceeding ones will not be functional.
02600  * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
02601  * Filter Table Remaining Available MailboxesThe number of the last remaining
02602  * available mailboxes is defined by the least value between the parameter
02603  * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
02604  * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
02605  * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
02606  * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
02607  * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
02608  * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
02609  * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
02610  * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
02611  * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
02612  * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
02613  * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
02614  * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
02615  * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
02616  * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
02617  * 0-37 MB 38-63 Elements 0-31 Elements 32-127
02618  */
02619 /*@{*/
02620 #define BP_CAN_CTRL2_RFFN    (24U)         /*!< Bit position for CAN_CTRL2_RFFN. */
02621 #define BM_CAN_CTRL2_RFFN    (0x0F000000U) /*!< Bit mask for CAN_CTRL2_RFFN. */
02622 #define BS_CAN_CTRL2_RFFN    (4U)          /*!< Bit field size in bits for CAN_CTRL2_RFFN. */
02623 
02624 /*! @brief Read current value of the CAN_CTRL2_RFFN field. */
02625 #define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
02626 
02627 /*! @brief Format value for bitfield CAN_CTRL2_RFFN. */
02628 #define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN)
02629 
02630 /*! @brief Set the RFFN field to a new value. */
02631 #define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
02632 /*@}*/
02633 
02634 /*!
02635  * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
02636  *
02637  * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
02638  * can only be written in Freeze mode and has no effect out of Freeze mode.
02639  *
02640  * Values:
02641  * - 0 - Maintain the write access restrictions.
02642  * - 1 - Enable unrestricted write access to FlexCAN memory.
02643  */
02644 /*@{*/
02645 #define BP_CAN_CTRL2_WRMFRZ  (28U)         /*!< Bit position for CAN_CTRL2_WRMFRZ. */
02646 #define BM_CAN_CTRL2_WRMFRZ  (0x10000000U) /*!< Bit mask for CAN_CTRL2_WRMFRZ. */
02647 #define BS_CAN_CTRL2_WRMFRZ  (1U)          /*!< Bit field size in bits for CAN_CTRL2_WRMFRZ. */
02648 
02649 /*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
02650 #define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
02651 
02652 /*! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. */
02653 #define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ)
02654 
02655 /*! @brief Set the WRMFRZ field to a new value. */
02656 #define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
02657 /*@}*/
02658 
02659 /*******************************************************************************
02660  * HW_CAN_ESR2 - Error and Status 2 register
02661  ******************************************************************************/
02662 
02663 /*!
02664  * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
02665  *
02666  * Reset value: 0x00000000U
02667  *
02668  * This register reflects various interrupt flags and some general status.
02669  */
02670 typedef union _hw_can_esr2
02671 {
02672     uint32_t U;
02673     struct _hw_can_esr2_bitfields
02674     {
02675         uint32_t RESERVED0 : 13;       /*!< [12:0]  */
02676         uint32_t IMB : 1;              /*!< [13] Inactive Mailbox */
02677         uint32_t VPS : 1;              /*!< [14] Valid Priority Status */
02678         uint32_t RESERVED1 : 1;        /*!< [15]  */
02679         uint32_t LPTM : 7;             /*!< [22:16] Lowest Priority Tx Mailbox */
02680         uint32_t RESERVED2 : 9;        /*!< [31:23]  */
02681     } B;
02682 } hw_can_esr2_t;
02683 
02684 /*!
02685  * @name Constants and macros for entire CAN_ESR2 register
02686  */
02687 /*@{*/
02688 #define HW_CAN_ESR2_ADDR(x)      ((x) + 0x38U)
02689 
02690 #define HW_CAN_ESR2(x)           (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
02691 #define HW_CAN_ESR2_RD(x)        (HW_CAN_ESR2(x).U)
02692 /*@}*/
02693 
02694 /*
02695  * Constants & macros for individual CAN_ESR2 bitfields
02696  */
02697 
02698 /*!
02699  * @name Register CAN_ESR2, field IMB[13] (RO)
02700  *
02701  * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
02702  * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
02703  * following cases: During arbitration, if an LPTM is found and it is inactive. If
02704  * IMB is not asserted and a frame is transmitted successfully. This bit is
02705  * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
02706  * mechanism have the following behavior: if an MB is successfully transmitted and
02707  * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
02708  * the index related to the MB just transmitted is loaded into ESR2[LPTM].
02709  *
02710  * Values:
02711  * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
02712  * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
02713  *     content is the number of the first one.
02714  */
02715 /*@{*/
02716 #define BP_CAN_ESR2_IMB      (13U)         /*!< Bit position for CAN_ESR2_IMB. */
02717 #define BM_CAN_ESR2_IMB      (0x00002000U) /*!< Bit mask for CAN_ESR2_IMB. */
02718 #define BS_CAN_ESR2_IMB      (1U)          /*!< Bit field size in bits for CAN_ESR2_IMB. */
02719 
02720 /*! @brief Read current value of the CAN_ESR2_IMB field. */
02721 #define BR_CAN_ESR2_IMB(x)   (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
02722 /*@}*/
02723 
02724 /*!
02725  * @name Register CAN_ESR2, field VPS[14] (RO)
02726  *
02727  * This bit indicates whether IMB and LPTM contents are currently valid or not.
02728  * VPS is asserted upon every complete Tx arbitration process unless the CPU
02729  * writes to Control and Status word of a Mailbox that has already been scanned, that
02730  * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
02731  * If there is no inactive Mailbox and only one Tx Mailbox that is being
02732  * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
02733  * arbitration process or upon a write to Control and Status word of any Mailbox.
02734  * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
02735  * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
02736  * in C/S of a MB that is being transmitted (pending abort), or any write attempt
02737  * into a Tx MB with IFLAG set is blocked.
02738  *
02739  * Values:
02740  * - 0 - Contents of IMB and LPTM are invalid.
02741  * - 1 - Contents of IMB and LPTM are valid.
02742  */
02743 /*@{*/
02744 #define BP_CAN_ESR2_VPS      (14U)         /*!< Bit position for CAN_ESR2_VPS. */
02745 #define BM_CAN_ESR2_VPS      (0x00004000U) /*!< Bit mask for CAN_ESR2_VPS. */
02746 #define BS_CAN_ESR2_VPS      (1U)          /*!< Bit field size in bits for CAN_ESR2_VPS. */
02747 
02748 /*! @brief Read current value of the CAN_ESR2_VPS field. */
02749 #define BR_CAN_ESR2_VPS(x)   (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
02750 /*@}*/
02751 
02752 /*!
02753  * @name Register CAN_ESR2, field LPTM[22:16] (RO)
02754  *
02755  * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
02756  * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
02757  * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
02758  * negated then the Mailbox indicated is the one that has the greatest arbitration
02759  * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
02760  * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
02761  * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
02762  * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
02763  * updated with its Mailbox number.
02764  */
02765 /*@{*/
02766 #define BP_CAN_ESR2_LPTM     (16U)         /*!< Bit position for CAN_ESR2_LPTM. */
02767 #define BM_CAN_ESR2_LPTM     (0x007F0000U) /*!< Bit mask for CAN_ESR2_LPTM. */
02768 #define BS_CAN_ESR2_LPTM     (7U)          /*!< Bit field size in bits for CAN_ESR2_LPTM. */
02769 
02770 /*! @brief Read current value of the CAN_ESR2_LPTM field. */
02771 #define BR_CAN_ESR2_LPTM(x)  (HW_CAN_ESR2(x).B.LPTM)
02772 /*@}*/
02773 
02774 /*******************************************************************************
02775  * HW_CAN_CRCR - CRC Register
02776  ******************************************************************************/
02777 
02778 /*!
02779  * @brief HW_CAN_CRCR - CRC Register (RO)
02780  *
02781  * Reset value: 0x00000000U
02782  *
02783  * This register provides information about the CRC of transmitted messages.
02784  */
02785 typedef union _hw_can_crcr
02786 {
02787     uint32_t U;
02788     struct _hw_can_crcr_bitfields
02789     {
02790         uint32_t TXCRC : 15;           /*!< [14:0] CRC Transmitted */
02791         uint32_t RESERVED0 : 1;        /*!< [15]  */
02792         uint32_t MBCRC : 7;            /*!< [22:16] CRC Mailbox */
02793         uint32_t RESERVED1 : 9;        /*!< [31:23]  */
02794     } B;
02795 } hw_can_crcr_t;
02796 
02797 /*!
02798  * @name Constants and macros for entire CAN_CRCR register
02799  */
02800 /*@{*/
02801 #define HW_CAN_CRCR_ADDR(x)      ((x) + 0x44U)
02802 
02803 #define HW_CAN_CRCR(x)           (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
02804 #define HW_CAN_CRCR_RD(x)        (HW_CAN_CRCR(x).U)
02805 /*@}*/
02806 
02807 /*
02808  * Constants & macros for individual CAN_CRCR bitfields
02809  */
02810 
02811 /*!
02812  * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
02813  *
02814  * This field indicates the CRC value of the last message transmitted. This
02815  * field is updated at the same time the Tx Interrupt Flag is asserted.
02816  */
02817 /*@{*/
02818 #define BP_CAN_CRCR_TXCRC    (0U)          /*!< Bit position for CAN_CRCR_TXCRC. */
02819 #define BM_CAN_CRCR_TXCRC    (0x00007FFFU) /*!< Bit mask for CAN_CRCR_TXCRC. */
02820 #define BS_CAN_CRCR_TXCRC    (15U)         /*!< Bit field size in bits for CAN_CRCR_TXCRC. */
02821 
02822 /*! @brief Read current value of the CAN_CRCR_TXCRC field. */
02823 #define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
02824 /*@}*/
02825 
02826 /*!
02827  * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
02828  *
02829  * This field indicates the number of the Mailbox corresponding to the value in
02830  * TXCRC field.
02831  */
02832 /*@{*/
02833 #define BP_CAN_CRCR_MBCRC    (16U)         /*!< Bit position for CAN_CRCR_MBCRC. */
02834 #define BM_CAN_CRCR_MBCRC    (0x007F0000U) /*!< Bit mask for CAN_CRCR_MBCRC. */
02835 #define BS_CAN_CRCR_MBCRC    (7U)          /*!< Bit field size in bits for CAN_CRCR_MBCRC. */
02836 
02837 /*! @brief Read current value of the CAN_CRCR_MBCRC field. */
02838 #define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
02839 /*@}*/
02840 
02841 /*******************************************************************************
02842  * HW_CAN_RXFGMASK - Rx FIFO Global Mask register
02843  ******************************************************************************/
02844 
02845 /*!
02846  * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
02847  *
02848  * Reset value: 0xFFFFFFFFU
02849  *
02850  * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
02851  * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
02852  * according to CTRL2[RFFN] field setting. This register can only be written in
02853  * Freeze mode as it is blocked by hardware in other modes.
02854  */
02855 typedef union _hw_can_rxfgmask
02856 {
02857     uint32_t U;
02858     struct _hw_can_rxfgmask_bitfields
02859     {
02860         uint32_t FGM : 32;             /*!< [31:0] Rx FIFO Global Mask Bits */
02861     } B;
02862 } hw_can_rxfgmask_t;
02863 
02864 /*!
02865  * @name Constants and macros for entire CAN_RXFGMASK register
02866  */
02867 /*@{*/
02868 #define HW_CAN_RXFGMASK_ADDR(x)  ((x) + 0x48U)
02869 
02870 #define HW_CAN_RXFGMASK(x)       (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
02871 #define HW_CAN_RXFGMASK_RD(x)    (HW_CAN_RXFGMASK(x).U)
02872 #define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
02873 #define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) |  (v)))
02874 #define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
02875 #define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^  (v)))
02876 /*@}*/
02877 
02878 /*
02879  * Constants & macros for individual CAN_RXFGMASK bitfields
02880  */
02881 
02882 /*!
02883  * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
02884  *
02885  * These bits mask the ID Filter Table elements bits in a perfect alignment. The
02886  * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
02887  * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
02888  * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
02889  * the fourteen most significant bits of the Identifier of the incoming frame are
02890  * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
02891  * the format C only the eight most significant bits of the Identifier of the
02892  * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
02893  * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
02894  * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
02895  *
02896  * Values:
02897  * - 0 - The corresponding bit in the filter is "don't care."
02898  * - 1 - The corresponding bit in the filter is checked.
02899  */
02900 /*@{*/
02901 #define BP_CAN_RXFGMASK_FGM  (0U)          /*!< Bit position for CAN_RXFGMASK_FGM. */
02902 #define BM_CAN_RXFGMASK_FGM  (0xFFFFFFFFU) /*!< Bit mask for CAN_RXFGMASK_FGM. */
02903 #define BS_CAN_RXFGMASK_FGM  (32U)         /*!< Bit field size in bits for CAN_RXFGMASK_FGM. */
02904 
02905 /*! @brief Read current value of the CAN_RXFGMASK_FGM field. */
02906 #define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
02907 
02908 /*! @brief Format value for bitfield CAN_RXFGMASK_FGM. */
02909 #define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM)
02910 
02911 /*! @brief Set the FGM field to a new value. */
02912 #define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
02913 /*@}*/
02914 
02915 /*******************************************************************************
02916  * HW_CAN_RXFIR - Rx FIFO Information Register
02917  ******************************************************************************/
02918 
02919 /*!
02920  * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
02921  *
02922  * Reset value: 0x00000000U
02923  *
02924  * RXFIR provides information on Rx FIFO. This register is the port through
02925  * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
02926  * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
02927  * well as its output is updated whenever the output of the Rx FIFO is updated
02928  * with the next message. See Section "Rx FIFO" for instructions on reading this
02929  * register.
02930  */
02931 typedef union _hw_can_rxfir
02932 {
02933     uint32_t U;
02934     struct _hw_can_rxfir_bitfields
02935     {
02936         uint32_t IDHIT : 9;            /*!< [8:0] Identifier Acceptance Filter Hit
02937                                         * Indicator */
02938         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
02939     } B;
02940 } hw_can_rxfir_t;
02941 
02942 /*!
02943  * @name Constants and macros for entire CAN_RXFIR register
02944  */
02945 /*@{*/
02946 #define HW_CAN_RXFIR_ADDR(x)     ((x) + 0x4CU)
02947 
02948 #define HW_CAN_RXFIR(x)          (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
02949 #define HW_CAN_RXFIR_RD(x)       (HW_CAN_RXFIR(x).U)
02950 /*@}*/
02951 
02952 /*
02953  * Constants & macros for individual CAN_RXFIR bitfields
02954  */
02955 
02956 /*!
02957  * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
02958  *
02959  * This field indicates which Identifier Acceptance Filter was hit by the
02960  * received message that is in the output of the Rx FIFO. If multiple filters match the
02961  * incoming message ID then the first matching IDAF found (lowest number) by the
02962  * matching process is indicated. This field is valid only while the
02963  * IFLAG[BUF5I] is asserted.
02964  */
02965 /*@{*/
02966 #define BP_CAN_RXFIR_IDHIT   (0U)          /*!< Bit position for CAN_RXFIR_IDHIT. */
02967 #define BM_CAN_RXFIR_IDHIT   (0x000001FFU) /*!< Bit mask for CAN_RXFIR_IDHIT. */
02968 #define BS_CAN_RXFIR_IDHIT   (9U)          /*!< Bit field size in bits for CAN_RXFIR_IDHIT. */
02969 
02970 /*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
02971 #define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
02972 /*@}*/
02973 
02974 /*******************************************************************************
02975  * HW_CAN_CSn - Message Buffer 0 CS Register
02976  ******************************************************************************/
02977 
02978 /*!
02979  * @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW)
02980  *
02981  * Reset value: 0x00000000U
02982  */
02983 typedef union _hw_can_csn
02984 {
02985     uint32_t U;
02986     struct _hw_can_csn_bitfields
02987     {
02988         uint32_t TIME_STAMP : 16;      /*!< [15:0] Free-Running Counter Time
02989                                         * stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx
02990                                         * and Rx frames at the time when the beginning of the Identifier field
02991                                         * appears on the CAN bus. */
02992         uint32_t DLC : 4;              /*!< [19:16] Length of the data to be
02993                                         * stored/transmitted. */
02994         uint32_t RTR : 1;              /*!< [20] Remote Transmission Request. One/zero for
02995                                         * remote/data frame. */
02996         uint32_t IDE : 1;              /*!< [21] ID Extended. One/zero for
02997                                         * extended/standard format frame. */
02998         uint32_t SRR : 1;              /*!< [22] Substitute Remote Request. Contains a
02999                                         * fixed recessive bit. */
03000         uint32_t RESERVED0 : 1;        /*!< [23] Reserved */
03001         uint32_t CODE : 4;             /*!< [27:24] Reserved */
03002         uint32_t RESERVED1 : 4;        /*!< [31:28] Reserved */
03003     } B;
03004 } hw_can_csn_t;
03005 
03006 /*!
03007  * @name Constants and macros for entire CAN_CSn register
03008  */
03009 /*@{*/
03010 #define HW_CAN_CSn_COUNT (16U)
03011 
03012 #define HW_CAN_CSn_ADDR(x, n)    ((x) + 0x80U + (0x10U * (n)))
03013 
03014 #define HW_CAN_CSn(x, n)         (*(__IO hw_can_csn_t *) HW_CAN_CSn_ADDR(x, n))
03015 #define HW_CAN_CSn_RD(x, n)      (HW_CAN_CSn(x, n).U)
03016 #define HW_CAN_CSn_WR(x, n, v)   (HW_CAN_CSn(x, n).U = (v))
03017 #define HW_CAN_CSn_SET(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) |  (v)))
03018 #define HW_CAN_CSn_CLR(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v)))
03019 #define HW_CAN_CSn_TOG(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^  (v)))
03020 /*@}*/
03021 
03022 /*
03023  * Constants & macros for individual CAN_CSn bitfields
03024  */
03025 
03026 /*!
03027  * @name Register CAN_CSn, field TIME_STAMP[15:0] (RW)
03028  */
03029 /*@{*/
03030 #define BP_CAN_CSn_TIME_STAMP (0U)         /*!< Bit position for CAN_CSn_TIME_STAMP. */
03031 #define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /*!< Bit mask for CAN_CSn_TIME_STAMP. */
03032 #define BS_CAN_CSn_TIME_STAMP (16U)        /*!< Bit field size in bits for CAN_CSn_TIME_STAMP. */
03033 
03034 /*! @brief Read current value of the CAN_CSn_TIME_STAMP field. */
03035 #define BR_CAN_CSn_TIME_STAMP(x, n) (HW_CAN_CSn(x, n).B.TIME_STAMP)
03036 
03037 /*! @brief Format value for bitfield CAN_CSn_TIME_STAMP. */
03038 #define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP)
03039 
03040 /*! @brief Set the TIME_STAMP field to a new value. */
03041 #define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) | BF_CAN_CSn_TIME_STAMP(v)))
03042 /*@}*/
03043 
03044 /*!
03045  * @name Register CAN_CSn, field DLC[19:16] (RW)
03046  */
03047 /*@{*/
03048 #define BP_CAN_CSn_DLC       (16U)         /*!< Bit position for CAN_CSn_DLC. */
03049 #define BM_CAN_CSn_DLC       (0x000F0000U) /*!< Bit mask for CAN_CSn_DLC. */
03050 #define BS_CAN_CSn_DLC       (4U)          /*!< Bit field size in bits for CAN_CSn_DLC. */
03051 
03052 /*! @brief Read current value of the CAN_CSn_DLC field. */
03053 #define BR_CAN_CSn_DLC(x, n) (HW_CAN_CSn(x, n).B.DLC)
03054 
03055 /*! @brief Format value for bitfield CAN_CSn_DLC. */
03056 #define BF_CAN_CSn_DLC(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC)
03057 
03058 /*! @brief Set the DLC field to a new value. */
03059 #define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) | BF_CAN_CSn_DLC(v)))
03060 /*@}*/
03061 
03062 /*!
03063  * @name Register CAN_CSn, field RTR[20] (RW)
03064  */
03065 /*@{*/
03066 #define BP_CAN_CSn_RTR       (20U)         /*!< Bit position for CAN_CSn_RTR. */
03067 #define BM_CAN_CSn_RTR       (0x00100000U) /*!< Bit mask for CAN_CSn_RTR. */
03068 #define BS_CAN_CSn_RTR       (1U)          /*!< Bit field size in bits for CAN_CSn_RTR. */
03069 
03070 /*! @brief Read current value of the CAN_CSn_RTR field. */
03071 #define BR_CAN_CSn_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR))
03072 
03073 /*! @brief Format value for bitfield CAN_CSn_RTR. */
03074 #define BF_CAN_CSn_RTR(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR)
03075 
03076 /*! @brief Set the RTR field to a new value. */
03077 #define BW_CAN_CSn_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR) = (v))
03078 /*@}*/
03079 
03080 /*!
03081  * @name Register CAN_CSn, field IDE[21] (RW)
03082  */
03083 /*@{*/
03084 #define BP_CAN_CSn_IDE       (21U)         /*!< Bit position for CAN_CSn_IDE. */
03085 #define BM_CAN_CSn_IDE       (0x00200000U) /*!< Bit mask for CAN_CSn_IDE. */
03086 #define BS_CAN_CSn_IDE       (1U)          /*!< Bit field size in bits for CAN_CSn_IDE. */
03087 
03088 /*! @brief Read current value of the CAN_CSn_IDE field. */
03089 #define BR_CAN_CSn_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE))
03090 
03091 /*! @brief Format value for bitfield CAN_CSn_IDE. */
03092 #define BF_CAN_CSn_IDE(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE)
03093 
03094 /*! @brief Set the IDE field to a new value. */
03095 #define BW_CAN_CSn_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE) = (v))
03096 /*@}*/
03097 
03098 /*!
03099  * @name Register CAN_CSn, field SRR[22] (RW)
03100  */
03101 /*@{*/
03102 #define BP_CAN_CSn_SRR       (22U)         /*!< Bit position for CAN_CSn_SRR. */
03103 #define BM_CAN_CSn_SRR       (0x00400000U) /*!< Bit mask for CAN_CSn_SRR. */
03104 #define BS_CAN_CSn_SRR       (1U)          /*!< Bit field size in bits for CAN_CSn_SRR. */
03105 
03106 /*! @brief Read current value of the CAN_CSn_SRR field. */
03107 #define BR_CAN_CSn_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR))
03108 
03109 /*! @brief Format value for bitfield CAN_CSn_SRR. */
03110 #define BF_CAN_CSn_SRR(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR)
03111 
03112 /*! @brief Set the SRR field to a new value. */
03113 #define BW_CAN_CSn_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR) = (v))
03114 /*@}*/
03115 
03116 /*!
03117  * @name Register CAN_CSn, field CODE[27:24] (RW)
03118  */
03119 /*@{*/
03120 #define BP_CAN_CSn_CODE      (24U)         /*!< Bit position for CAN_CSn_CODE. */
03121 #define BM_CAN_CSn_CODE      (0x0F000000U) /*!< Bit mask for CAN_CSn_CODE. */
03122 #define BS_CAN_CSn_CODE      (4U)          /*!< Bit field size in bits for CAN_CSn_CODE. */
03123 
03124 /*! @brief Read current value of the CAN_CSn_CODE field. */
03125 #define BR_CAN_CSn_CODE(x, n) (HW_CAN_CSn(x, n).B.CODE)
03126 
03127 /*! @brief Format value for bitfield CAN_CSn_CODE. */
03128 #define BF_CAN_CSn_CODE(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE)
03129 
03130 /*! @brief Set the CODE field to a new value. */
03131 #define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) | BF_CAN_CSn_CODE(v)))
03132 /*@}*/
03133 /*******************************************************************************
03134  * HW_CAN_IDn - Message Buffer 0 ID Register
03135  ******************************************************************************/
03136 
03137 /*!
03138  * @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW)
03139  *
03140  * Reset value: 0x00000000U
03141  */
03142 typedef union _hw_can_idn
03143 {
03144     uint32_t U;
03145     struct _hw_can_idn_bitfields
03146     {
03147         uint32_t EXT : 18;             /*!< [17:0] Contains extended (LOW word)
03148                                         * identifier of message buffer. */
03149         uint32_t STD : 11;             /*!< [28:18] Contains standard/extended (HIGH
03150                                         * word) identifier of message buffer. */
03151         uint32_t PRIO : 3;             /*!< [31:29] Local priority. This 3-bit fieldis
03152                                         * only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
03153                                         * buffers. These bits are not transmitted. They are appended to the regular
03154                                         * ID to define the transmission priority. */
03155     } B;
03156 } hw_can_idn_t;
03157 
03158 /*!
03159  * @name Constants and macros for entire CAN_IDn register
03160  */
03161 /*@{*/
03162 #define HW_CAN_IDn_COUNT (16U)
03163 
03164 #define HW_CAN_IDn_ADDR(x, n)    ((x) + 0x84U + (0x10U * (n)))
03165 
03166 #define HW_CAN_IDn(x, n)         (*(__IO hw_can_idn_t *) HW_CAN_IDn_ADDR(x, n))
03167 #define HW_CAN_IDn_RD(x, n)      (HW_CAN_IDn(x, n).U)
03168 #define HW_CAN_IDn_WR(x, n, v)   (HW_CAN_IDn(x, n).U = (v))
03169 #define HW_CAN_IDn_SET(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) |  (v)))
03170 #define HW_CAN_IDn_CLR(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v)))
03171 #define HW_CAN_IDn_TOG(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^  (v)))
03172 /*@}*/
03173 
03174 /*
03175  * Constants & macros for individual CAN_IDn bitfields
03176  */
03177 
03178 /*!
03179  * @name Register CAN_IDn, field EXT[17:0] (RW)
03180  */
03181 /*@{*/
03182 #define BP_CAN_IDn_EXT       (0U)          /*!< Bit position for CAN_IDn_EXT. */
03183 #define BM_CAN_IDn_EXT       (0x0003FFFFU) /*!< Bit mask for CAN_IDn_EXT. */
03184 #define BS_CAN_IDn_EXT       (18U)         /*!< Bit field size in bits for CAN_IDn_EXT. */
03185 
03186 /*! @brief Read current value of the CAN_IDn_EXT field. */
03187 #define BR_CAN_IDn_EXT(x, n) (HW_CAN_IDn(x, n).B.EXT)
03188 
03189 /*! @brief Format value for bitfield CAN_IDn_EXT. */
03190 #define BF_CAN_IDn_EXT(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT)
03191 
03192 /*! @brief Set the EXT field to a new value. */
03193 #define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) | BF_CAN_IDn_EXT(v)))
03194 /*@}*/
03195 
03196 /*!
03197  * @name Register CAN_IDn, field STD[28:18] (RW)
03198  */
03199 /*@{*/
03200 #define BP_CAN_IDn_STD       (18U)         /*!< Bit position for CAN_IDn_STD. */
03201 #define BM_CAN_IDn_STD       (0x1FFC0000U) /*!< Bit mask for CAN_IDn_STD. */
03202 #define BS_CAN_IDn_STD       (11U)         /*!< Bit field size in bits for CAN_IDn_STD. */
03203 
03204 /*! @brief Read current value of the CAN_IDn_STD field. */
03205 #define BR_CAN_IDn_STD(x, n) (HW_CAN_IDn(x, n).B.STD)
03206 
03207 /*! @brief Format value for bitfield CAN_IDn_STD. */
03208 #define BF_CAN_IDn_STD(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD)
03209 
03210 /*! @brief Set the STD field to a new value. */
03211 #define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) | BF_CAN_IDn_STD(v)))
03212 /*@}*/
03213 
03214 /*!
03215  * @name Register CAN_IDn, field PRIO[31:29] (RW)
03216  */
03217 /*@{*/
03218 #define BP_CAN_IDn_PRIO      (29U)         /*!< Bit position for CAN_IDn_PRIO. */
03219 #define BM_CAN_IDn_PRIO      (0xE0000000U) /*!< Bit mask for CAN_IDn_PRIO. */
03220 #define BS_CAN_IDn_PRIO      (3U)          /*!< Bit field size in bits for CAN_IDn_PRIO. */
03221 
03222 /*! @brief Read current value of the CAN_IDn_PRIO field. */
03223 #define BR_CAN_IDn_PRIO(x, n) (HW_CAN_IDn(x, n).B.PRIO)
03224 
03225 /*! @brief Format value for bitfield CAN_IDn_PRIO. */
03226 #define BF_CAN_IDn_PRIO(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO)
03227 
03228 /*! @brief Set the PRIO field to a new value. */
03229 #define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) | BF_CAN_IDn_PRIO(v)))
03230 /*@}*/
03231 /*******************************************************************************
03232  * HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
03233  ******************************************************************************/
03234 
03235 /*!
03236  * @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW)
03237  *
03238  * Reset value: 0x00000000U
03239  */
03240 typedef union _hw_can_word0n
03241 {
03242     uint32_t U;
03243     struct _hw_can_word0n_bitfields
03244     {
03245         uint32_t DATA_BYTE_3 : 8;      /*!< [7:0] Data byte 3 of Rx/Tx frame. */
03246         uint32_t DATA_BYTE_2 : 8;      /*!< [15:8] Data byte 2 of Rx/Tx frame. */
03247         uint32_t DATA_BYTE_1 : 8;      /*!< [23:16] Data byte 1 of Rx/Tx frame. */
03248         uint32_t DATA_BYTE_0 : 8;      /*!< [31:24] Data byte 0 of Rx/Tx frame. */
03249     } B;
03250 } hw_can_word0n_t;
03251 
03252 /*!
03253  * @name Constants and macros for entire CAN_WORD0n register
03254  */
03255 /*@{*/
03256 #define HW_CAN_WORD0n_COUNT (16U)
03257 
03258 #define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n)))
03259 
03260 #define HW_CAN_WORD0n(x, n)      (*(__IO hw_can_word0n_t *) HW_CAN_WORD0n_ADDR(x, n))
03261 #define HW_CAN_WORD0n_RD(x, n)   (HW_CAN_WORD0n(x, n).U)
03262 #define HW_CAN_WORD0n_WR(x, n, v) (HW_CAN_WORD0n(x, n).U = (v))
03263 #define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) |  (v)))
03264 #define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v)))
03265 #define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^  (v)))
03266 /*@}*/
03267 
03268 /*
03269  * Constants & macros for individual CAN_WORD0n bitfields
03270  */
03271 
03272 /*!
03273  * @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW)
03274  */
03275 /*@{*/
03276 #define BP_CAN_WORD0n_DATA_BYTE_3 (0U)     /*!< Bit position for CAN_WORD0n_DATA_BYTE_3. */
03277 #define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_3. */
03278 #define BS_CAN_WORD0n_DATA_BYTE_3 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. */
03279 
03280 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. */
03281 #define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_3)
03282 
03283 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. */
03284 #define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3)
03285 
03286 /*! @brief Set the DATA_BYTE_3 field to a new value. */
03287 #define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) | BF_CAN_WORD0n_DATA_BYTE_3(v)))
03288 /*@}*/
03289 
03290 /*!
03291  * @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW)
03292  */
03293 /*@{*/
03294 #define BP_CAN_WORD0n_DATA_BYTE_2 (8U)     /*!< Bit position for CAN_WORD0n_DATA_BYTE_2. */
03295 #define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_2. */
03296 #define BS_CAN_WORD0n_DATA_BYTE_2 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. */
03297 
03298 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. */
03299 #define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_2)
03300 
03301 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. */
03302 #define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2)
03303 
03304 /*! @brief Set the DATA_BYTE_2 field to a new value. */
03305 #define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) | BF_CAN_WORD0n_DATA_BYTE_2(v)))
03306 /*@}*/
03307 
03308 /*!
03309  * @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW)
03310  */
03311 /*@{*/
03312 #define BP_CAN_WORD0n_DATA_BYTE_1 (16U)    /*!< Bit position for CAN_WORD0n_DATA_BYTE_1. */
03313 #define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_1. */
03314 #define BS_CAN_WORD0n_DATA_BYTE_1 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. */
03315 
03316 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. */
03317 #define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_1)
03318 
03319 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. */
03320 #define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1)
03321 
03322 /*! @brief Set the DATA_BYTE_1 field to a new value. */
03323 #define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) | BF_CAN_WORD0n_DATA_BYTE_1(v)))
03324 /*@}*/
03325 
03326 /*!
03327  * @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW)
03328  */
03329 /*@{*/
03330 #define BP_CAN_WORD0n_DATA_BYTE_0 (24U)    /*!< Bit position for CAN_WORD0n_DATA_BYTE_0. */
03331 #define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_0. */
03332 #define BS_CAN_WORD0n_DATA_BYTE_0 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. */
03333 
03334 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. */
03335 #define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_0)
03336 
03337 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. */
03338 #define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0)
03339 
03340 /*! @brief Set the DATA_BYTE_0 field to a new value. */
03341 #define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) | BF_CAN_WORD0n_DATA_BYTE_0(v)))
03342 /*@}*/
03343 /*******************************************************************************
03344  * HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
03345  ******************************************************************************/
03346 
03347 /*!
03348  * @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW)
03349  *
03350  * Reset value: 0x00000000U
03351  */
03352 typedef union _hw_can_word1n
03353 {
03354     uint32_t U;
03355     struct _hw_can_word1n_bitfields
03356     {
03357         uint32_t DATA_BYTE_7 : 8;      /*!< [7:0] Data byte 7 of Rx/Tx frame. */
03358         uint32_t DATA_BYTE_6 : 8;      /*!< [15:8] Data byte 6 of Rx/Tx frame. */
03359         uint32_t DATA_BYTE_5 : 8;      /*!< [23:16] Data byte 5 of Rx/Tx frame. */
03360         uint32_t DATA_BYTE_4 : 8;      /*!< [31:24] Data byte 4 of Rx/Tx frame. */
03361     } B;
03362 } hw_can_word1n_t;
03363 
03364 /*!
03365  * @name Constants and macros for entire CAN_WORD1n register
03366  */
03367 /*@{*/
03368 #define HW_CAN_WORD1n_COUNT (16U)
03369 
03370 #define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n)))
03371 
03372 #define HW_CAN_WORD1n(x, n)      (*(__IO hw_can_word1n_t *) HW_CAN_WORD1n_ADDR(x, n))
03373 #define HW_CAN_WORD1n_RD(x, n)   (HW_CAN_WORD1n(x, n).U)
03374 #define HW_CAN_WORD1n_WR(x, n, v) (HW_CAN_WORD1n(x, n).U = (v))
03375 #define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) |  (v)))
03376 #define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v)))
03377 #define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^  (v)))
03378 /*@}*/
03379 
03380 /*
03381  * Constants & macros for individual CAN_WORD1n bitfields
03382  */
03383 
03384 /*!
03385  * @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW)
03386  */
03387 /*@{*/
03388 #define BP_CAN_WORD1n_DATA_BYTE_7 (0U)     /*!< Bit position for CAN_WORD1n_DATA_BYTE_7. */
03389 #define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_7. */
03390 #define BS_CAN_WORD1n_DATA_BYTE_7 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. */
03391 
03392 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. */
03393 #define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_7)
03394 
03395 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. */
03396 #define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7)
03397 
03398 /*! @brief Set the DATA_BYTE_7 field to a new value. */
03399 #define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) | BF_CAN_WORD1n_DATA_BYTE_7(v)))
03400 /*@}*/
03401 
03402 /*!
03403  * @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW)
03404  */
03405 /*@{*/
03406 #define BP_CAN_WORD1n_DATA_BYTE_6 (8U)     /*!< Bit position for CAN_WORD1n_DATA_BYTE_6. */
03407 #define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_6. */
03408 #define BS_CAN_WORD1n_DATA_BYTE_6 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. */
03409 
03410 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. */
03411 #define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_6)
03412 
03413 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. */
03414 #define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6)
03415 
03416 /*! @brief Set the DATA_BYTE_6 field to a new value. */
03417 #define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) | BF_CAN_WORD1n_DATA_BYTE_6(v)))
03418 /*@}*/
03419 
03420 /*!
03421  * @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW)
03422  */
03423 /*@{*/
03424 #define BP_CAN_WORD1n_DATA_BYTE_5 (16U)    /*!< Bit position for CAN_WORD1n_DATA_BYTE_5. */
03425 #define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_5. */
03426 #define BS_CAN_WORD1n_DATA_BYTE_5 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. */
03427 
03428 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. */
03429 #define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_5)
03430 
03431 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. */
03432 #define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5)
03433 
03434 /*! @brief Set the DATA_BYTE_5 field to a new value. */
03435 #define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) | BF_CAN_WORD1n_DATA_BYTE_5(v)))
03436 /*@}*/
03437 
03438 /*!
03439  * @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW)
03440  */
03441 /*@{*/
03442 #define BP_CAN_WORD1n_DATA_BYTE_4 (24U)    /*!< Bit position for CAN_WORD1n_DATA_BYTE_4. */
03443 #define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_4. */
03444 #define BS_CAN_WORD1n_DATA_BYTE_4 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. */
03445 
03446 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. */
03447 #define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_4)
03448 
03449 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. */
03450 #define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4)
03451 
03452 /*! @brief Set the DATA_BYTE_4 field to a new value. */
03453 #define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) | BF_CAN_WORD1n_DATA_BYTE_4(v)))
03454 /*@}*/
03455 
03456 /*******************************************************************************
03457  * HW_CAN_RXIMRn - Rx Individual Mask Registers
03458  ******************************************************************************/
03459 
03460 /*!
03461  * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
03462  *
03463  * Reset value: 0x00000000U
03464  *
03465  * These registers are located in RAM. RXIMR are used as acceptance masks for ID
03466  * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
03467  * register is provided for each available Mailbox, providing ID masking
03468  * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
03469  * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
03470  * Table elements on a one-to-one correspondence depending on the setting of
03471  * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
03472  * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
03473  * are not affected by reset and must be explicitly initialized prior to any
03474  * reception.
03475  */
03476 typedef union _hw_can_rximrn
03477 {
03478     uint32_t U;
03479     struct _hw_can_rximrn_bitfields
03480     {
03481         uint32_t MI : 32;              /*!< [31:0] Individual Mask Bits */
03482     } B;
03483 } hw_can_rximrn_t;
03484 
03485 /*!
03486  * @name Constants and macros for entire CAN_RXIMRn register
03487  */
03488 /*@{*/
03489 #define HW_CAN_RXIMRn_COUNT (16U)
03490 
03491 #define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n)))
03492 
03493 #define HW_CAN_RXIMRn(x, n)      (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
03494 #define HW_CAN_RXIMRn_RD(x, n)   (HW_CAN_RXIMRn(x, n).U)
03495 #define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
03496 #define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) |  (v)))
03497 #define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
03498 #define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^  (v)))
03499 /*@}*/
03500 
03501 /*
03502  * Constants & macros for individual CAN_RXIMRn bitfields
03503  */
03504 
03505 /*!
03506  * @name Register CAN_RXIMRn, field MI[31:0] (RW)
03507  *
03508  * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
03509  * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
03510  * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
03511  * see the RXFGMASK register description.
03512  *
03513  * Values:
03514  * - 0 - The corresponding bit in the filter is "don't care."
03515  * - 1 - The corresponding bit in the filter is checked.
03516  */
03517 /*@{*/
03518 #define BP_CAN_RXIMRn_MI     (0U)          /*!< Bit position for CAN_RXIMRn_MI. */
03519 #define BM_CAN_RXIMRn_MI     (0xFFFFFFFFU) /*!< Bit mask for CAN_RXIMRn_MI. */
03520 #define BS_CAN_RXIMRn_MI     (32U)         /*!< Bit field size in bits for CAN_RXIMRn_MI. */
03521 
03522 /*! @brief Read current value of the CAN_RXIMRn_MI field. */
03523 #define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
03524 
03525 /*! @brief Format value for bitfield CAN_RXIMRn_MI. */
03526 #define BF_CAN_RXIMRn_MI(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI)
03527 
03528 /*! @brief Set the MI field to a new value. */
03529 #define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
03530 /*@}*/
03531 
03532 /*******************************************************************************
03533  * hw_can_t - module struct
03534  ******************************************************************************/
03535 /*!
03536  * @brief All CAN module registers.
03537  */
03538 #pragma pack(1)
03539 typedef struct _hw_can
03540 {
03541     __IO hw_can_mcr_t MCR ;                 /*!< [0x0] Module Configuration Register */
03542     __IO hw_can_ctrl1_t CTRL1 ;             /*!< [0x4] Control 1 register */
03543     __IO hw_can_timer_t TIMER ;             /*!< [0x8] Free Running Timer */
03544     uint8_t _reserved0[4];
03545     __IO hw_can_rxmgmask_t RXMGMASK ;       /*!< [0x10] Rx Mailboxes Global Mask Register */
03546     __IO hw_can_rx14mask_t RX14MASK ;       /*!< [0x14] Rx 14 Mask register */
03547     __IO hw_can_rx15mask_t RX15MASK ;       /*!< [0x18] Rx 15 Mask register */
03548     __IO hw_can_ecr_t ECR ;                 /*!< [0x1C] Error Counter */
03549     __IO hw_can_esr1_t ESR1 ;               /*!< [0x20] Error and Status 1 register */
03550     uint8_t _reserved1[4];
03551     __IO hw_can_imask1_t IMASK1 ;           /*!< [0x28] Interrupt Masks 1 register */
03552     uint8_t _reserved2[4];
03553     __IO hw_can_iflag1_t IFLAG1 ;           /*!< [0x30] Interrupt Flags 1 register */
03554     __IO hw_can_ctrl2_t CTRL2 ;             /*!< [0x34] Control 2 register */
03555     __I hw_can_esr2_t ESR2 ;                /*!< [0x38] Error and Status 2 register */
03556     uint8_t _reserved3[8];
03557     __I hw_can_crcr_t CRCR ;                /*!< [0x44] CRC Register */
03558     __IO hw_can_rxfgmask_t RXFGMASK ;       /*!< [0x48] Rx FIFO Global Mask register */
03559     __I hw_can_rxfir_t RXFIR ;              /*!< [0x4C] Rx FIFO Information Register */
03560     uint8_t _reserved4[48];
03561     struct {
03562         __IO hw_can_csn_t CSn ;             /*!< [0x80] Message Buffer 0 CS Register */
03563         __IO hw_can_idn_t IDn ;             /*!< [0x84] Message Buffer 0 ID Register */
03564         __IO hw_can_word0n_t WORD0n ;       /*!< [0x88] Message Buffer 0 WORD0 Register */
03565         __IO hw_can_word1n_t WORD1n ;       /*!< [0x8C] Message Buffer 0 WORD1 Register */
03566     } MB[16];
03567     uint8_t _reserved5[1792];
03568     __IO hw_can_rximrn_t RXIMRn [16];       /*!< [0x880] Rx Individual Mask Registers */
03569 } hw_can_t;
03570 #pragma pack()
03571 
03572 /*! @brief Macro to access all CAN registers. */
03573 /*! @param x CAN module instance base address. */
03574 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
03575  *     use the '&' operator, like <code>&HW_CAN(CAN0_BASE)</code>. */
03576 #define HW_CAN(x)      (*(hw_can_t *)(x))
03577 
03578 #endif /* __HW_CAN_REGISTERS_H__ */
03579 /* EOF */