MK64F12_axbs.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_AXBS_REGISTERS_H__
00081 #define __HW_AXBS_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 AXBS
00088  *
00089  * Crossbar switch
00090  *
00091  * Registers defined in this header file:
00092  * - HW_AXBS_PRSn - Priority Registers Slave
00093  * - HW_AXBS_CRSn - Control Register
00094  * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
00095  * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
00096  * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
00097  * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
00098  * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
00099  * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
00100  *
00101  * - hw_axbs_t - Struct containing all module registers.
00102  */
00103 
00104 #define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
00105 
00106 /*******************************************************************************
00107  * HW_AXBS_PRSn - Priority Registers Slave
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
00112  *
00113  * Reset value: 0x00543210U
00114  *
00115  * The priority registers (PRSn) set the priority of each master port on a per
00116  * slave port basis and reside in each slave port. The priority register can be
00117  * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
00118  * register can only be read; attempts to write to it have no effect on PRSn and
00119  * result in a bus-error response to the master initiating the write. Two available
00120  * masters must not be programmed with the same priority level. Attempts to
00121  * program two or more masters with the same priority level result in a bus-error
00122  * response and the PRSn is not updated. Valid values for the Mn priority fields
00123  * depend on which masters are available on the chip. This information can be found in
00124  * the chip-specific information for the crossbar. If the chip contains less
00125  * than five masters, values 0 to 3 are valid. Writing other values will result in
00126  * an error. If the chip contains five or more masters, valid values are 0 to n-1,
00127  * where n is the number of masters attached to the AXBS module. Other values
00128  * will result in an error.
00129  */
00130 typedef union _hw_axbs_prsn
00131 {
00132     uint32_t U;
00133     struct _hw_axbs_prsn_bitfields
00134     {
00135         uint32_t M0 : 3;               /*!< [2:0] Master 0 Priority. Sets the arbitration
00136                                         * priority for this port on the associated slave port. */
00137         uint32_t RESERVED0 : 1;        /*!< [3]  */
00138         uint32_t M1 : 3;               /*!< [6:4] Master 1 Priority. Sets the arbitration
00139                                         * priority for this port on the associated slave port. */
00140         uint32_t RESERVED1 : 1;        /*!< [7]  */
00141         uint32_t M2 : 3;               /*!< [10:8] Master 2 Priority. Sets the arbitration
00142                                         * priority for this port on the associated slave port. */
00143         uint32_t RESERVED2 : 1;        /*!< [11]  */
00144         uint32_t M3 : 3;               /*!< [14:12] Master 3 Priority. Sets the arbitration
00145                                         * priority for this port on the associated slave port. */
00146         uint32_t RESERVED3 : 1;        /*!< [15]  */
00147         uint32_t M4 : 3;               /*!< [18:16] Master 4 Priority. Sets the arbitration
00148                                         * priority for this port on the associated slave port. */
00149         uint32_t RESERVED4 : 1;        /*!< [19]  */
00150         uint32_t M5 : 3;               /*!< [22:20] Master 5 Priority. Sets the arbitration
00151                                         * priority for this port on the associated slave port. */
00152         uint32_t RESERVED5 : 9;        /*!< [31:23]  */
00153     } B;
00154 } hw_axbs_prsn_t;
00155 
00156 /*!
00157  * @name Constants and macros for entire AXBS_PRSn register
00158  */
00159 /*@{*/
00160 #define HW_AXBS_PRSn_COUNT (5U)
00161 
00162 #define HW_AXBS_PRSn_ADDR(x, n)  ((x) + 0x0U + (0x100U * (n)))
00163 
00164 #define HW_AXBS_PRSn(x, n)       (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n))
00165 #define HW_AXBS_PRSn_RD(x, n)    (HW_AXBS_PRSn(x, n).U)
00166 #define HW_AXBS_PRSn_WR(x, n, v) (HW_AXBS_PRSn(x, n).U = (v))
00167 #define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) |  (v)))
00168 #define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v)))
00169 #define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^  (v)))
00170 /*@}*/
00171 
00172 /*
00173  * Constants & macros for individual AXBS_PRSn bitfields
00174  */
00175 
00176 /*!
00177  * @name Register AXBS_PRSn, field M0[2:0] (RW)
00178  *
00179  * Values:
00180  * - 000 - This master has level 1, or highest, priority when accessing the
00181  *     slave port.
00182  * - 001 - This master has level 2 priority when accessing the slave port.
00183  * - 010 - This master has level 3 priority when accessing the slave port.
00184  * - 011 - This master has level 4 priority when accessing the slave port.
00185  * - 100 - This master has level 5 priority when accessing the slave port.
00186  * - 101 - This master has level 6 priority when accessing the slave port.
00187  * - 110 - This master has level 7 priority when accessing the slave port.
00188  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00189  *     port.
00190  */
00191 /*@{*/
00192 #define BP_AXBS_PRSn_M0      (0U)          /*!< Bit position for AXBS_PRSn_M0. */
00193 #define BM_AXBS_PRSn_M0      (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */
00194 #define BS_AXBS_PRSn_M0      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M0. */
00195 
00196 /*! @brief Read current value of the AXBS_PRSn_M0 field. */
00197 #define BR_AXBS_PRSn_M0(x, n) (HW_AXBS_PRSn(x, n).B.M0)
00198 
00199 /*! @brief Format value for bitfield AXBS_PRSn_M0. */
00200 #define BF_AXBS_PRSn_M0(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0)
00201 
00202 /*! @brief Set the M0 field to a new value. */
00203 #define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
00204 /*@}*/
00205 
00206 /*!
00207  * @name Register AXBS_PRSn, field M1[6:4] (RW)
00208  *
00209  * Values:
00210  * - 000 - This master has level 1, or highest, priority when accessing the
00211  *     slave port.
00212  * - 001 - This master has level 2 priority when accessing the slave port.
00213  * - 010 - This master has level 3 priority when accessing the slave port.
00214  * - 011 - This master has level 4 priority when accessing the slave port.
00215  * - 100 - This master has level 5 priority when accessing the slave port.
00216  * - 101 - This master has level 6 priority when accessing the slave port.
00217  * - 110 - This master has level 7 priority when accessing the slave port.
00218  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00219  *     port.
00220  */
00221 /*@{*/
00222 #define BP_AXBS_PRSn_M1      (4U)          /*!< Bit position for AXBS_PRSn_M1. */
00223 #define BM_AXBS_PRSn_M1      (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */
00224 #define BS_AXBS_PRSn_M1      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M1. */
00225 
00226 /*! @brief Read current value of the AXBS_PRSn_M1 field. */
00227 #define BR_AXBS_PRSn_M1(x, n) (HW_AXBS_PRSn(x, n).B.M1)
00228 
00229 /*! @brief Format value for bitfield AXBS_PRSn_M1. */
00230 #define BF_AXBS_PRSn_M1(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1)
00231 
00232 /*! @brief Set the M1 field to a new value. */
00233 #define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
00234 /*@}*/
00235 
00236 /*!
00237  * @name Register AXBS_PRSn, field M2[10:8] (RW)
00238  *
00239  * Values:
00240  * - 000 - This master has level 1, or highest, priority when accessing the
00241  *     slave port.
00242  * - 001 - This master has level 2 priority when accessing the slave port.
00243  * - 010 - This master has level 3 priority when accessing the slave port.
00244  * - 011 - This master has level 4 priority when accessing the slave port.
00245  * - 100 - This master has level 5 priority when accessing the slave port.
00246  * - 101 - This master has level 6 priority when accessing the slave port.
00247  * - 110 - This master has level 7 priority when accessing the slave port.
00248  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00249  *     port.
00250  */
00251 /*@{*/
00252 #define BP_AXBS_PRSn_M2      (8U)          /*!< Bit position for AXBS_PRSn_M2. */
00253 #define BM_AXBS_PRSn_M2      (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */
00254 #define BS_AXBS_PRSn_M2      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M2. */
00255 
00256 /*! @brief Read current value of the AXBS_PRSn_M2 field. */
00257 #define BR_AXBS_PRSn_M2(x, n) (HW_AXBS_PRSn(x, n).B.M2)
00258 
00259 /*! @brief Format value for bitfield AXBS_PRSn_M2. */
00260 #define BF_AXBS_PRSn_M2(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2)
00261 
00262 /*! @brief Set the M2 field to a new value. */
00263 #define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
00264 /*@}*/
00265 
00266 /*!
00267  * @name Register AXBS_PRSn, field M3[14:12] (RW)
00268  *
00269  * Values:
00270  * - 000 - This master has level 1, or highest, priority when accessing the
00271  *     slave port.
00272  * - 001 - This master has level 2 priority when accessing the slave port.
00273  * - 010 - This master has level 3 priority when accessing the slave port.
00274  * - 011 - This master has level 4 priority when accessing the slave port.
00275  * - 100 - This master has level 5 priority when accessing the slave port.
00276  * - 101 - This master has level 6 priority when accessing the slave port.
00277  * - 110 - This master has level 7 priority when accessing the slave port.
00278  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00279  *     port.
00280  */
00281 /*@{*/
00282 #define BP_AXBS_PRSn_M3      (12U)         /*!< Bit position for AXBS_PRSn_M3. */
00283 #define BM_AXBS_PRSn_M3      (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */
00284 #define BS_AXBS_PRSn_M3      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M3. */
00285 
00286 /*! @brief Read current value of the AXBS_PRSn_M3 field. */
00287 #define BR_AXBS_PRSn_M3(x, n) (HW_AXBS_PRSn(x, n).B.M3)
00288 
00289 /*! @brief Format value for bitfield AXBS_PRSn_M3. */
00290 #define BF_AXBS_PRSn_M3(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3)
00291 
00292 /*! @brief Set the M3 field to a new value. */
00293 #define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
00294 /*@}*/
00295 
00296 /*!
00297  * @name Register AXBS_PRSn, field M4[18:16] (RW)
00298  *
00299  * Values:
00300  * - 000 - This master has level 1, or highest, priority when accessing the
00301  *     slave port.
00302  * - 001 - This master has level 2 priority when accessing the slave port.
00303  * - 010 - This master has level 3 priority when accessing the slave port.
00304  * - 011 - This master has level 4 priority when accessing the slave port.
00305  * - 100 - This master has level 5 priority when accessing the slave port.
00306  * - 101 - This master has level 6 priority when accessing the slave port.
00307  * - 110 - This master has level 7 priority when accessing the slave port.
00308  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00309  *     port.
00310  */
00311 /*@{*/
00312 #define BP_AXBS_PRSn_M4      (16U)         /*!< Bit position for AXBS_PRSn_M4. */
00313 #define BM_AXBS_PRSn_M4      (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */
00314 #define BS_AXBS_PRSn_M4      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M4. */
00315 
00316 /*! @brief Read current value of the AXBS_PRSn_M4 field. */
00317 #define BR_AXBS_PRSn_M4(x, n) (HW_AXBS_PRSn(x, n).B.M4)
00318 
00319 /*! @brief Format value for bitfield AXBS_PRSn_M4. */
00320 #define BF_AXBS_PRSn_M4(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4)
00321 
00322 /*! @brief Set the M4 field to a new value. */
00323 #define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
00324 /*@}*/
00325 
00326 /*!
00327  * @name Register AXBS_PRSn, field M5[22:20] (RW)
00328  *
00329  * Values:
00330  * - 000 - This master has level 1, or highest, priority when accessing the
00331  *     slave port.
00332  * - 001 - This master has level 2 priority when accessing the slave port.
00333  * - 010 - This master has level 3 priority when accessing the slave port.
00334  * - 011 - This master has level 4 priority when accessing the slave port.
00335  * - 100 - This master has level 5 priority when accessing the slave port.
00336  * - 101 - This master has level 6 priority when accessing the slave port.
00337  * - 110 - This master has level 7 priority when accessing the slave port.
00338  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00339  *     port.
00340  */
00341 /*@{*/
00342 #define BP_AXBS_PRSn_M5      (20U)         /*!< Bit position for AXBS_PRSn_M5. */
00343 #define BM_AXBS_PRSn_M5      (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */
00344 #define BS_AXBS_PRSn_M5      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M5. */
00345 
00346 /*! @brief Read current value of the AXBS_PRSn_M5 field. */
00347 #define BR_AXBS_PRSn_M5(x, n) (HW_AXBS_PRSn(x, n).B.M5)
00348 
00349 /*! @brief Format value for bitfield AXBS_PRSn_M5. */
00350 #define BF_AXBS_PRSn_M5(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5)
00351 
00352 /*! @brief Set the M5 field to a new value. */
00353 #define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
00354 /*@}*/
00355 /*******************************************************************************
00356  * HW_AXBS_CRSn - Control Register
00357  ******************************************************************************/
00358 
00359 /*!
00360  * @brief HW_AXBS_CRSn - Control Register (RW)
00361  *
00362  * Reset value: 0x00000000U
00363  *
00364  * These registers control several features of each slave port and must be
00365  * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
00366  * attempts to write to it have no effect and result in an error response.
00367  */
00368 typedef union _hw_axbs_crsn
00369 {
00370     uint32_t U;
00371     struct _hw_axbs_crsn_bitfields
00372     {
00373         uint32_t PARK : 3;             /*!< [2:0] Park */
00374         uint32_t RESERVED0 : 1;        /*!< [3]  */
00375         uint32_t PCTL : 2;             /*!< [5:4] Parking Control */
00376         uint32_t RESERVED1 : 2;        /*!< [7:6]  */
00377         uint32_t ARB : 2;              /*!< [9:8] Arbitration Mode */
00378         uint32_t RESERVED2 : 20;       /*!< [29:10]  */
00379         uint32_t HLP : 1;              /*!< [30] Halt Low Priority */
00380         uint32_t RO : 1;               /*!< [31] Read Only */
00381     } B;
00382 } hw_axbs_crsn_t;
00383 
00384 /*!
00385  * @name Constants and macros for entire AXBS_CRSn register
00386  */
00387 /*@{*/
00388 #define HW_AXBS_CRSn_COUNT (5U)
00389 
00390 #define HW_AXBS_CRSn_ADDR(x, n)  ((x) + 0x10U + (0x100U * (n)))
00391 
00392 #define HW_AXBS_CRSn(x, n)       (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n))
00393 #define HW_AXBS_CRSn_RD(x, n)    (HW_AXBS_CRSn(x, n).U)
00394 #define HW_AXBS_CRSn_WR(x, n, v) (HW_AXBS_CRSn(x, n).U = (v))
00395 #define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) |  (v)))
00396 #define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v)))
00397 #define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^  (v)))
00398 /*@}*/
00399 
00400 /*
00401  * Constants & macros for individual AXBS_CRSn bitfields
00402  */
00403 
00404 /*!
00405  * @name Register AXBS_CRSn, field PARK[2:0] (RW)
00406  *
00407  * Determines which master port the current slave port parks on when no masters
00408  * are actively making requests and the PCTL bits are cleared. Select only master
00409  * ports that are present on the chip. Otherwise, undefined behavior might occur.
00410  *
00411  * Values:
00412  * - 000 - Park on master port M0
00413  * - 001 - Park on master port M1
00414  * - 010 - Park on master port M2
00415  * - 011 - Park on master port M3
00416  * - 100 - Park on master port M4
00417  * - 101 - Park on master port M5
00418  * - 110 - Park on master port M6
00419  * - 111 - Park on master port M7
00420  */
00421 /*@{*/
00422 #define BP_AXBS_CRSn_PARK    (0U)          /*!< Bit position for AXBS_CRSn_PARK. */
00423 #define BM_AXBS_CRSn_PARK    (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */
00424 #define BS_AXBS_CRSn_PARK    (3U)          /*!< Bit field size in bits for AXBS_CRSn_PARK. */
00425 
00426 /*! @brief Read current value of the AXBS_CRSn_PARK field. */
00427 #define BR_AXBS_CRSn_PARK(x, n) (HW_AXBS_CRSn(x, n).B.PARK)
00428 
00429 /*! @brief Format value for bitfield AXBS_CRSn_PARK. */
00430 #define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK)
00431 
00432 /*! @brief Set the PARK field to a new value. */
00433 #define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
00434 /*@}*/
00435 
00436 /*!
00437  * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
00438  *
00439  * Determines the slave port's parking control. The low-power park feature
00440  * results in an overall power savings if the slave port is not saturated. However,
00441  * this forces an extra latency clock when any master tries to access the slave
00442  * port while not in use because it is not parked on any master.
00443  *
00444  * Values:
00445  * - 00 - When no master makes a request, the arbiter parks the slave port on
00446  *     the master port defined by the PARK field
00447  * - 01 - When no master makes a request, the arbiter parks the slave port on
00448  *     the last master to be in control of the slave port
00449  * - 10 - When no master makes a request, the slave port is not parked on a
00450  *     master and the arbiter drives all outputs to a constant safe state
00451  * - 11 - Reserved
00452  */
00453 /*@{*/
00454 #define BP_AXBS_CRSn_PCTL    (4U)          /*!< Bit position for AXBS_CRSn_PCTL. */
00455 #define BM_AXBS_CRSn_PCTL    (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */
00456 #define BS_AXBS_CRSn_PCTL    (2U)          /*!< Bit field size in bits for AXBS_CRSn_PCTL. */
00457 
00458 /*! @brief Read current value of the AXBS_CRSn_PCTL field. */
00459 #define BR_AXBS_CRSn_PCTL(x, n) (HW_AXBS_CRSn(x, n).B.PCTL)
00460 
00461 /*! @brief Format value for bitfield AXBS_CRSn_PCTL. */
00462 #define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL)
00463 
00464 /*! @brief Set the PCTL field to a new value. */
00465 #define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
00466 /*@}*/
00467 
00468 /*!
00469  * @name Register AXBS_CRSn, field ARB[9:8] (RW)
00470  *
00471  * Selects the arbitration policy for the slave port.
00472  *
00473  * Values:
00474  * - 00 - Fixed priority
00475  * - 01 - Round-robin, or rotating, priority
00476  * - 10 - Reserved
00477  * - 11 - Reserved
00478  */
00479 /*@{*/
00480 #define BP_AXBS_CRSn_ARB     (8U)          /*!< Bit position for AXBS_CRSn_ARB. */
00481 #define BM_AXBS_CRSn_ARB     (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */
00482 #define BS_AXBS_CRSn_ARB     (2U)          /*!< Bit field size in bits for AXBS_CRSn_ARB. */
00483 
00484 /*! @brief Read current value of the AXBS_CRSn_ARB field. */
00485 #define BR_AXBS_CRSn_ARB(x, n) (HW_AXBS_CRSn(x, n).B.ARB)
00486 
00487 /*! @brief Format value for bitfield AXBS_CRSn_ARB. */
00488 #define BF_AXBS_CRSn_ARB(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB)
00489 
00490 /*! @brief Set the ARB field to a new value. */
00491 #define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
00492 /*@}*/
00493 
00494 /*!
00495  * @name Register AXBS_CRSn, field HLP[30] (RW)
00496  *
00497  * Sets the initial arbitration priority for low power mode requests . Setting
00498  * this bit will not affect the request for low power mode from attaining highest
00499  * priority once it has control of the slave ports.
00500  *
00501  * Values:
00502  * - 0 - The low power mode request has the highest priority for arbitration on
00503  *     this slave port
00504  * - 1 - The low power mode request has the lowest initial priority for
00505  *     arbitration on this slave port
00506  */
00507 /*@{*/
00508 #define BP_AXBS_CRSn_HLP     (30U)         /*!< Bit position for AXBS_CRSn_HLP. */
00509 #define BM_AXBS_CRSn_HLP     (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */
00510 #define BS_AXBS_CRSn_HLP     (1U)          /*!< Bit field size in bits for AXBS_CRSn_HLP. */
00511 
00512 /*! @brief Read current value of the AXBS_CRSn_HLP field. */
00513 #define BR_AXBS_CRSn_HLP(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP))
00514 
00515 /*! @brief Format value for bitfield AXBS_CRSn_HLP. */
00516 #define BF_AXBS_CRSn_HLP(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP)
00517 
00518 /*! @brief Set the HLP field to a new value. */
00519 #define BW_AXBS_CRSn_HLP(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP) = (v))
00520 /*@}*/
00521 
00522 /*!
00523  * @name Register AXBS_CRSn, field RO[31] (RW)
00524  *
00525  * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
00526  * only a hardware reset clears it.
00527  *
00528  * Values:
00529  * - 0 - The slave port's registers are writeable
00530  * - 1 - The slave port's registers are read-only and cannot be written.
00531  *     Attempted writes have no effect on the registers and result in a bus error
00532  *     response.
00533  */
00534 /*@{*/
00535 #define BP_AXBS_CRSn_RO      (31U)         /*!< Bit position for AXBS_CRSn_RO. */
00536 #define BM_AXBS_CRSn_RO      (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */
00537 #define BS_AXBS_CRSn_RO      (1U)          /*!< Bit field size in bits for AXBS_CRSn_RO. */
00538 
00539 /*! @brief Read current value of the AXBS_CRSn_RO field. */
00540 #define BR_AXBS_CRSn_RO(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO))
00541 
00542 /*! @brief Format value for bitfield AXBS_CRSn_RO. */
00543 #define BF_AXBS_CRSn_RO(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO)
00544 
00545 /*! @brief Set the RO field to a new value. */
00546 #define BW_AXBS_CRSn_RO(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO) = (v))
00547 /*@}*/
00548 
00549 /*******************************************************************************
00550  * HW_AXBS_MGPCR0 - Master General Purpose Control Register
00551  ******************************************************************************/
00552 
00553 /*!
00554  * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
00555  *
00556  * Reset value: 0x00000000U
00557  *
00558  * The MGPCR controls only whether the master's undefined length burst accesses
00559  * are allowed to complete uninterrupted or whether they can be broken by
00560  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00561  * mode with 32-bit accesses.
00562  */
00563 typedef union _hw_axbs_mgpcr0
00564 {
00565     uint32_t U;
00566     struct _hw_axbs_mgpcr0_bitfields
00567     {
00568         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00569         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00570     } B;
00571 } hw_axbs_mgpcr0_t;
00572 
00573 /*!
00574  * @name Constants and macros for entire AXBS_MGPCR0 register
00575  */
00576 /*@{*/
00577 #define HW_AXBS_MGPCR0_ADDR(x)   ((x) + 0x800U)
00578 
00579 #define HW_AXBS_MGPCR0(x)        (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x))
00580 #define HW_AXBS_MGPCR0_RD(x)     (HW_AXBS_MGPCR0(x).U)
00581 #define HW_AXBS_MGPCR0_WR(x, v)  (HW_AXBS_MGPCR0(x).U = (v))
00582 #define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) |  (v)))
00583 #define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v)))
00584 #define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^  (v)))
00585 /*@}*/
00586 
00587 /*
00588  * Constants & macros for individual AXBS_MGPCR0 bitfields
00589  */
00590 
00591 /*!
00592  * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
00593  *
00594  * Determines whether, and when, the crossbar switch arbitrates away the slave
00595  * port the master owns when the master is performing undefined length burst
00596  * accesses.
00597  *
00598  * Values:
00599  * - 000 - No arbitration is allowed during an undefined length burst
00600  * - 001 - Arbitration is allowed at any time during an undefined length burst
00601  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00602  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00603  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00604  * - 101 - Reserved
00605  * - 110 - Reserved
00606  * - 111 - Reserved
00607  */
00608 /*@{*/
00609 #define BP_AXBS_MGPCR0_AULB  (0U)          /*!< Bit position for AXBS_MGPCR0_AULB. */
00610 #define BM_AXBS_MGPCR0_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */
00611 #define BS_AXBS_MGPCR0_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */
00612 
00613 /*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
00614 #define BR_AXBS_MGPCR0_AULB(x) (HW_AXBS_MGPCR0(x).B.AULB)
00615 
00616 /*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */
00617 #define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB)
00618 
00619 /*! @brief Set the AULB field to a new value. */
00620 #define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
00621 /*@}*/
00622 
00623 /*******************************************************************************
00624  * HW_AXBS_MGPCR1 - Master General Purpose Control Register
00625  ******************************************************************************/
00626 
00627 /*!
00628  * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
00629  *
00630  * Reset value: 0x00000000U
00631  *
00632  * The MGPCR controls only whether the master's undefined length burst accesses
00633  * are allowed to complete uninterrupted or whether they can be broken by
00634  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00635  * mode with 32-bit accesses.
00636  */
00637 typedef union _hw_axbs_mgpcr1
00638 {
00639     uint32_t U;
00640     struct _hw_axbs_mgpcr1_bitfields
00641     {
00642         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00643         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00644     } B;
00645 } hw_axbs_mgpcr1_t;
00646 
00647 /*!
00648  * @name Constants and macros for entire AXBS_MGPCR1 register
00649  */
00650 /*@{*/
00651 #define HW_AXBS_MGPCR1_ADDR(x)   ((x) + 0x900U)
00652 
00653 #define HW_AXBS_MGPCR1(x)        (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x))
00654 #define HW_AXBS_MGPCR1_RD(x)     (HW_AXBS_MGPCR1(x).U)
00655 #define HW_AXBS_MGPCR1_WR(x, v)  (HW_AXBS_MGPCR1(x).U = (v))
00656 #define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) |  (v)))
00657 #define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v)))
00658 #define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^  (v)))
00659 /*@}*/
00660 
00661 /*
00662  * Constants & macros for individual AXBS_MGPCR1 bitfields
00663  */
00664 
00665 /*!
00666  * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
00667  *
00668  * Determines whether, and when, the crossbar switch arbitrates away the slave
00669  * port the master owns when the master is performing undefined length burst
00670  * accesses.
00671  *
00672  * Values:
00673  * - 000 - No arbitration is allowed during an undefined length burst
00674  * - 001 - Arbitration is allowed at any time during an undefined length burst
00675  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00676  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00677  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00678  * - 101 - Reserved
00679  * - 110 - Reserved
00680  * - 111 - Reserved
00681  */
00682 /*@{*/
00683 #define BP_AXBS_MGPCR1_AULB  (0U)          /*!< Bit position for AXBS_MGPCR1_AULB. */
00684 #define BM_AXBS_MGPCR1_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */
00685 #define BS_AXBS_MGPCR1_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */
00686 
00687 /*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
00688 #define BR_AXBS_MGPCR1_AULB(x) (HW_AXBS_MGPCR1(x).B.AULB)
00689 
00690 /*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */
00691 #define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB)
00692 
00693 /*! @brief Set the AULB field to a new value. */
00694 #define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
00695 /*@}*/
00696 
00697 /*******************************************************************************
00698  * HW_AXBS_MGPCR2 - Master General Purpose Control Register
00699  ******************************************************************************/
00700 
00701 /*!
00702  * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
00703  *
00704  * Reset value: 0x00000000U
00705  *
00706  * The MGPCR controls only whether the master's undefined length burst accesses
00707  * are allowed to complete uninterrupted or whether they can be broken by
00708  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00709  * mode with 32-bit accesses.
00710  */
00711 typedef union _hw_axbs_mgpcr2
00712 {
00713     uint32_t U;
00714     struct _hw_axbs_mgpcr2_bitfields
00715     {
00716         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00717         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00718     } B;
00719 } hw_axbs_mgpcr2_t;
00720 
00721 /*!
00722  * @name Constants and macros for entire AXBS_MGPCR2 register
00723  */
00724 /*@{*/
00725 #define HW_AXBS_MGPCR2_ADDR(x)   ((x) + 0xA00U)
00726 
00727 #define HW_AXBS_MGPCR2(x)        (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x))
00728 #define HW_AXBS_MGPCR2_RD(x)     (HW_AXBS_MGPCR2(x).U)
00729 #define HW_AXBS_MGPCR2_WR(x, v)  (HW_AXBS_MGPCR2(x).U = (v))
00730 #define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) |  (v)))
00731 #define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v)))
00732 #define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^  (v)))
00733 /*@}*/
00734 
00735 /*
00736  * Constants & macros for individual AXBS_MGPCR2 bitfields
00737  */
00738 
00739 /*!
00740  * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
00741  *
00742  * Determines whether, and when, the crossbar switch arbitrates away the slave
00743  * port the master owns when the master is performing undefined length burst
00744  * accesses.
00745  *
00746  * Values:
00747  * - 000 - No arbitration is allowed during an undefined length burst
00748  * - 001 - Arbitration is allowed at any time during an undefined length burst
00749  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00750  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00751  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00752  * - 101 - Reserved
00753  * - 110 - Reserved
00754  * - 111 - Reserved
00755  */
00756 /*@{*/
00757 #define BP_AXBS_MGPCR2_AULB  (0U)          /*!< Bit position for AXBS_MGPCR2_AULB. */
00758 #define BM_AXBS_MGPCR2_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */
00759 #define BS_AXBS_MGPCR2_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */
00760 
00761 /*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
00762 #define BR_AXBS_MGPCR2_AULB(x) (HW_AXBS_MGPCR2(x).B.AULB)
00763 
00764 /*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */
00765 #define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB)
00766 
00767 /*! @brief Set the AULB field to a new value. */
00768 #define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
00769 /*@}*/
00770 
00771 /*******************************************************************************
00772  * HW_AXBS_MGPCR3 - Master General Purpose Control Register
00773  ******************************************************************************/
00774 
00775 /*!
00776  * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
00777  *
00778  * Reset value: 0x00000000U
00779  *
00780  * The MGPCR controls only whether the master's undefined length burst accesses
00781  * are allowed to complete uninterrupted or whether they can be broken by
00782  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00783  * mode with 32-bit accesses.
00784  */
00785 typedef union _hw_axbs_mgpcr3
00786 {
00787     uint32_t U;
00788     struct _hw_axbs_mgpcr3_bitfields
00789     {
00790         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00791         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00792     } B;
00793 } hw_axbs_mgpcr3_t;
00794 
00795 /*!
00796  * @name Constants and macros for entire AXBS_MGPCR3 register
00797  */
00798 /*@{*/
00799 #define HW_AXBS_MGPCR3_ADDR(x)   ((x) + 0xB00U)
00800 
00801 #define HW_AXBS_MGPCR3(x)        (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x))
00802 #define HW_AXBS_MGPCR3_RD(x)     (HW_AXBS_MGPCR3(x).U)
00803 #define HW_AXBS_MGPCR3_WR(x, v)  (HW_AXBS_MGPCR3(x).U = (v))
00804 #define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) |  (v)))
00805 #define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v)))
00806 #define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^  (v)))
00807 /*@}*/
00808 
00809 /*
00810  * Constants & macros for individual AXBS_MGPCR3 bitfields
00811  */
00812 
00813 /*!
00814  * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
00815  *
00816  * Determines whether, and when, the crossbar switch arbitrates away the slave
00817  * port the master owns when the master is performing undefined length burst
00818  * accesses.
00819  *
00820  * Values:
00821  * - 000 - No arbitration is allowed during an undefined length burst
00822  * - 001 - Arbitration is allowed at any time during an undefined length burst
00823  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00824  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00825  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00826  * - 101 - Reserved
00827  * - 110 - Reserved
00828  * - 111 - Reserved
00829  */
00830 /*@{*/
00831 #define BP_AXBS_MGPCR3_AULB  (0U)          /*!< Bit position for AXBS_MGPCR3_AULB. */
00832 #define BM_AXBS_MGPCR3_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */
00833 #define BS_AXBS_MGPCR3_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */
00834 
00835 /*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
00836 #define BR_AXBS_MGPCR3_AULB(x) (HW_AXBS_MGPCR3(x).B.AULB)
00837 
00838 /*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */
00839 #define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB)
00840 
00841 /*! @brief Set the AULB field to a new value. */
00842 #define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
00843 /*@}*/
00844 
00845 /*******************************************************************************
00846  * HW_AXBS_MGPCR4 - Master General Purpose Control Register
00847  ******************************************************************************/
00848 
00849 /*!
00850  * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
00851  *
00852  * Reset value: 0x00000000U
00853  *
00854  * The MGPCR controls only whether the master's undefined length burst accesses
00855  * are allowed to complete uninterrupted or whether they can be broken by
00856  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00857  * mode with 32-bit accesses.
00858  */
00859 typedef union _hw_axbs_mgpcr4
00860 {
00861     uint32_t U;
00862     struct _hw_axbs_mgpcr4_bitfields
00863     {
00864         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00865         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00866     } B;
00867 } hw_axbs_mgpcr4_t;
00868 
00869 /*!
00870  * @name Constants and macros for entire AXBS_MGPCR4 register
00871  */
00872 /*@{*/
00873 #define HW_AXBS_MGPCR4_ADDR(x)   ((x) + 0xC00U)
00874 
00875 #define HW_AXBS_MGPCR4(x)        (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x))
00876 #define HW_AXBS_MGPCR4_RD(x)     (HW_AXBS_MGPCR4(x).U)
00877 #define HW_AXBS_MGPCR4_WR(x, v)  (HW_AXBS_MGPCR4(x).U = (v))
00878 #define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) |  (v)))
00879 #define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v)))
00880 #define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^  (v)))
00881 /*@}*/
00882 
00883 /*
00884  * Constants & macros for individual AXBS_MGPCR4 bitfields
00885  */
00886 
00887 /*!
00888  * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
00889  *
00890  * Determines whether, and when, the crossbar switch arbitrates away the slave
00891  * port the master owns when the master is performing undefined length burst
00892  * accesses.
00893  *
00894  * Values:
00895  * - 000 - No arbitration is allowed during an undefined length burst
00896  * - 001 - Arbitration is allowed at any time during an undefined length burst
00897  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00898  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00899  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00900  * - 101 - Reserved
00901  * - 110 - Reserved
00902  * - 111 - Reserved
00903  */
00904 /*@{*/
00905 #define BP_AXBS_MGPCR4_AULB  (0U)          /*!< Bit position for AXBS_MGPCR4_AULB. */
00906 #define BM_AXBS_MGPCR4_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */
00907 #define BS_AXBS_MGPCR4_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */
00908 
00909 /*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
00910 #define BR_AXBS_MGPCR4_AULB(x) (HW_AXBS_MGPCR4(x).B.AULB)
00911 
00912 /*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */
00913 #define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB)
00914 
00915 /*! @brief Set the AULB field to a new value. */
00916 #define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
00917 /*@}*/
00918 
00919 /*******************************************************************************
00920  * HW_AXBS_MGPCR5 - Master General Purpose Control Register
00921  ******************************************************************************/
00922 
00923 /*!
00924  * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
00925  *
00926  * Reset value: 0x00000000U
00927  *
00928  * The MGPCR controls only whether the master's undefined length burst accesses
00929  * are allowed to complete uninterrupted or whether they can be broken by
00930  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00931  * mode with 32-bit accesses.
00932  */
00933 typedef union _hw_axbs_mgpcr5
00934 {
00935     uint32_t U;
00936     struct _hw_axbs_mgpcr5_bitfields
00937     {
00938         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00939         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00940     } B;
00941 } hw_axbs_mgpcr5_t;
00942 
00943 /*!
00944  * @name Constants and macros for entire AXBS_MGPCR5 register
00945  */
00946 /*@{*/
00947 #define HW_AXBS_MGPCR5_ADDR(x)   ((x) + 0xD00U)
00948 
00949 #define HW_AXBS_MGPCR5(x)        (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x))
00950 #define HW_AXBS_MGPCR5_RD(x)     (HW_AXBS_MGPCR5(x).U)
00951 #define HW_AXBS_MGPCR5_WR(x, v)  (HW_AXBS_MGPCR5(x).U = (v))
00952 #define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) |  (v)))
00953 #define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v)))
00954 #define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^  (v)))
00955 /*@}*/
00956 
00957 /*
00958  * Constants & macros for individual AXBS_MGPCR5 bitfields
00959  */
00960 
00961 /*!
00962  * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
00963  *
00964  * Determines whether, and when, the crossbar switch arbitrates away the slave
00965  * port the master owns when the master is performing undefined length burst
00966  * accesses.
00967  *
00968  * Values:
00969  * - 000 - No arbitration is allowed during an undefined length burst
00970  * - 001 - Arbitration is allowed at any time during an undefined length burst
00971  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00972  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00973  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00974  * - 101 - Reserved
00975  * - 110 - Reserved
00976  * - 111 - Reserved
00977  */
00978 /*@{*/
00979 #define BP_AXBS_MGPCR5_AULB  (0U)          /*!< Bit position for AXBS_MGPCR5_AULB. */
00980 #define BM_AXBS_MGPCR5_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */
00981 #define BS_AXBS_MGPCR5_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */
00982 
00983 /*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
00984 #define BR_AXBS_MGPCR5_AULB(x) (HW_AXBS_MGPCR5(x).B.AULB)
00985 
00986 /*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */
00987 #define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB)
00988 
00989 /*! @brief Set the AULB field to a new value. */
00990 #define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
00991 /*@}*/
00992 
00993 /*******************************************************************************
00994  * hw_axbs_t - module struct
00995  ******************************************************************************/
00996 /*!
00997  * @brief All AXBS module registers.
00998  */
00999 #pragma pack(1)
01000 typedef struct _hw_axbs
01001 {
01002     struct {
01003         __IO hw_axbs_prsn_t PRSn ;          /*!< [0x0] Priority Registers Slave */
01004         uint8_t _reserved0[12];
01005         __IO hw_axbs_crsn_t CRSn ;          /*!< [0x10] Control Register */
01006         uint8_t _reserved1[236];
01007     } SLAVE[5];
01008     uint8_t _reserved0[768];
01009     __IO hw_axbs_mgpcr0_t MGPCR0 ;          /*!< [0x800] Master General Purpose Control Register */
01010     uint8_t _reserved1[252];
01011     __IO hw_axbs_mgpcr1_t MGPCR1 ;          /*!< [0x900] Master General Purpose Control Register */
01012     uint8_t _reserved2[252];
01013     __IO hw_axbs_mgpcr2_t MGPCR2 ;          /*!< [0xA00] Master General Purpose Control Register */
01014     uint8_t _reserved3[252];
01015     __IO hw_axbs_mgpcr3_t MGPCR3 ;          /*!< [0xB00] Master General Purpose Control Register */
01016     uint8_t _reserved4[252];
01017     __IO hw_axbs_mgpcr4_t MGPCR4 ;          /*!< [0xC00] Master General Purpose Control Register */
01018     uint8_t _reserved5[252];
01019     __IO hw_axbs_mgpcr5_t MGPCR5 ;          /*!< [0xD00] Master General Purpose Control Register */
01020 } hw_axbs_t;
01021 #pragma pack()
01022 
01023 /*! @brief Macro to access all AXBS registers. */
01024 /*! @param x AXBS module instance base address. */
01025 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01026  *     use the '&' operator, like <code>&HW_AXBS(AXBS_BASE)</code>. */
01027 #define HW_AXBS(x)     (*(hw_axbs_t *)(x))
01028 
01029 #endif /* __HW_AXBS_REGISTERS_H__ */
01030 /* EOF */