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MK64F12_aips.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** Redistribution and use in source and binary forms, with or without modification, 00019 ** are permitted provided that the following conditions are met: 00020 ** 00021 ** o Redistributions of source code must retain the above copyright notice, this list 00022 ** of conditions and the following disclaimer. 00023 ** 00024 ** o Redistributions in binary form must reproduce the above copyright notice, this 00025 ** list of conditions and the following disclaimer in the documentation and/or 00026 ** other materials provided with the distribution. 00027 ** 00028 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00029 ** contributors may be used to endorse or promote products derived from this 00030 ** software without specific prior written permission. 00031 ** 00032 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00033 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00034 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00035 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00036 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00037 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00038 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00039 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00040 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00041 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00042 ** 00043 ** http: www.freescale.com 00044 ** mail: support@freescale.com 00045 ** 00046 ** Revisions: 00047 ** - rev. 1.0 (2013-08-12) 00048 ** Initial version. 00049 ** - rev. 2.0 (2013-10-29) 00050 ** Register accessor macros added to the memory map. 00051 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00052 ** Startup file for gcc has been updated according to CMSIS 3.2. 00053 ** System initialization updated. 00054 ** MCG - registers updated. 00055 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00056 ** - rev. 2.1 (2013-10-30) 00057 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00058 ** - rev. 2.2 (2013-12-09) 00059 ** DMA - EARS register removed. 00060 ** AIPS0, AIPS1 - MPRA register updated. 00061 ** - rev. 2.3 (2014-01-24) 00062 ** Update according to reference manual rev. 2 00063 ** ENET, MCG, MCM, SIM, USB - registers updated 00064 ** - rev. 2.4 (2014-02-10) 00065 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00066 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00067 ** - rev. 2.5 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00071 ** 00072 ** ################################################################### 00073 */ 00074 00075 /* 00076 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00077 * 00078 * This file was generated automatically and any changes may be lost. 00079 */ 00080 #ifndef __HW_AIPS_REGISTERS_H__ 00081 #define __HW_AIPS_REGISTERS_H__ 00082 00083 #include "MK64F12.h" 00084 #include "fsl_bitaccess.h" 00085 00086 /* 00087 * MK64F12 AIPS 00088 * 00089 * AIPS-Lite Bridge 00090 * 00091 * Registers defined in this header file: 00092 * - HW_AIPS_MPRA - Master Privilege Register A 00093 * - HW_AIPS_PACRA - Peripheral Access Control Register 00094 * - HW_AIPS_PACRB - Peripheral Access Control Register 00095 * - HW_AIPS_PACRC - Peripheral Access Control Register 00096 * - HW_AIPS_PACRD - Peripheral Access Control Register 00097 * - HW_AIPS_PACRE - Peripheral Access Control Register 00098 * - HW_AIPS_PACRF - Peripheral Access Control Register 00099 * - HW_AIPS_PACRG - Peripheral Access Control Register 00100 * - HW_AIPS_PACRH - Peripheral Access Control Register 00101 * - HW_AIPS_PACRI - Peripheral Access Control Register 00102 * - HW_AIPS_PACRJ - Peripheral Access Control Register 00103 * - HW_AIPS_PACRK - Peripheral Access Control Register 00104 * - HW_AIPS_PACRL - Peripheral Access Control Register 00105 * - HW_AIPS_PACRM - Peripheral Access Control Register 00106 * - HW_AIPS_PACRN - Peripheral Access Control Register 00107 * - HW_AIPS_PACRO - Peripheral Access Control Register 00108 * - HW_AIPS_PACRP - Peripheral Access Control Register 00109 * - HW_AIPS_PACRU - Peripheral Access Control Register 00110 * 00111 * - hw_aips_t - Struct containing all module registers. 00112 */ 00113 00114 #define HW_AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */ 00115 #define HW_AIPS0 (0U) /*!< Instance number for AIPS0. */ 00116 #define HW_AIPS1 (1U) /*!< Instance number for AIPS1. */ 00117 00118 /******************************************************************************* 00119 * HW_AIPS_MPRA - Master Privilege Register A 00120 ******************************************************************************/ 00121 00122 /*! 00123 * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) 00124 * 00125 * Reset value: 0x77700000U 00126 * 00127 * The MPRA specifies identical 4-bit fields defining the access-privilege level 00128 * associated with a bus master to various peripherals on the chip. The register 00129 * provides one field per bus master. At reset, the default value loaded into 00130 * the MPRA fields is chip-specific. See the chip configuration details for the 00131 * value of a particular device. A register field that maps to an unimplemented 00132 * master or peripheral behaves as read-only-zero. Each master is assigned a logical 00133 * ID from 0 to 15. See the master logical ID assignment table in the 00134 * chip-specific AIPS information. 00135 */ 00136 typedef union _hw_aips_mpra 00137 { 00138 uint32_t U; 00139 struct _hw_aips_mpra_bitfields 00140 { 00141 uint32_t RESERVED0 : 8; /*!< [7:0] */ 00142 uint32_t MPL5 : 1; /*!< [8] Master 5 Privilege Level */ 00143 uint32_t MTW5 : 1; /*!< [9] Master 5 Trusted For Writes */ 00144 uint32_t MTR5 : 1; /*!< [10] Master 5 Trusted For Read */ 00145 uint32_t RESERVED1 : 1; /*!< [11] */ 00146 uint32_t MPL4 : 1; /*!< [12] Master 4 Privilege Level */ 00147 uint32_t MTW4 : 1; /*!< [13] Master 4 Trusted For Writes */ 00148 uint32_t MTR4 : 1; /*!< [14] Master 4 Trusted For Read */ 00149 uint32_t RESERVED2 : 1; /*!< [15] */ 00150 uint32_t MPL3 : 1; /*!< [16] Master 3 Privilege Level */ 00151 uint32_t MTW3 : 1; /*!< [17] Master 3 Trusted For Writes */ 00152 uint32_t MTR3 : 1; /*!< [18] Master 3 Trusted For Read */ 00153 uint32_t RESERVED3 : 1; /*!< [19] */ 00154 uint32_t MPL2 : 1; /*!< [20] Master 2 Privilege Level */ 00155 uint32_t MTW2 : 1; /*!< [21] Master 2 Trusted For Writes */ 00156 uint32_t MTR2 : 1; /*!< [22] Master 2 Trusted For Read */ 00157 uint32_t RESERVED4 : 1; /*!< [23] */ 00158 uint32_t MPL1 : 1; /*!< [24] Master 1 Privilege Level */ 00159 uint32_t MTW1 : 1; /*!< [25] Master 1 Trusted for Writes */ 00160 uint32_t MTR1 : 1; /*!< [26] Master 1 Trusted for Read */ 00161 uint32_t RESERVED5 : 1; /*!< [27] */ 00162 uint32_t MPL0 : 1; /*!< [28] Master 0 Privilege Level */ 00163 uint32_t MTW0 : 1; /*!< [29] Master 0 Trusted For Writes */ 00164 uint32_t MTR0 : 1; /*!< [30] Master 0 Trusted For Read */ 00165 uint32_t RESERVED6 : 1; /*!< [31] */ 00166 } B; 00167 } hw_aips_mpra_t; 00168 00169 /*! 00170 * @name Constants and macros for entire AIPS_MPRA register 00171 */ 00172 /*@{*/ 00173 #define HW_AIPS_MPRA_ADDR(x) ((x) + 0x0U) 00174 00175 #define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) 00176 #define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U) 00177 #define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v)) 00178 #define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) 00179 #define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) 00180 #define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) 00181 /*@}*/ 00182 00183 /* 00184 * Constants & macros for individual AIPS_MPRA bitfields 00185 */ 00186 00187 /*! 00188 * @name Register AIPS_MPRA, field MPL5[8] (RW) 00189 * 00190 * Specifies how the privilege level of the master is determined. 00191 * 00192 * Values: 00193 * - 0 - Accesses from this master are forced to user-mode. 00194 * - 1 - Accesses from this master are not forced to user-mode. 00195 */ 00196 /*@{*/ 00197 #define BP_AIPS_MPRA_MPL5 (8U) /*!< Bit position for AIPS_MPRA_MPL5. */ 00198 #define BM_AIPS_MPRA_MPL5 (0x00000100U) /*!< Bit mask for AIPS_MPRA_MPL5. */ 00199 #define BS_AIPS_MPRA_MPL5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL5. */ 00200 00201 /*! @brief Read current value of the AIPS_MPRA_MPL5 field. */ 00202 #define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5)) 00203 00204 /*! @brief Format value for bitfield AIPS_MPRA_MPL5. */ 00205 #define BF_AIPS_MPRA_MPL5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL5) & BM_AIPS_MPRA_MPL5) 00206 00207 /*! @brief Set the MPL5 field to a new value. */ 00208 #define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v)) 00209 /*@}*/ 00210 00211 /*! 00212 * @name Register AIPS_MPRA, field MTW5[9] (RW) 00213 * 00214 * Determines whether the master is trusted for write accesses. 00215 * 00216 * Values: 00217 * - 0 - This master is not trusted for write accesses. 00218 * - 1 - This master is trusted for write accesses. 00219 */ 00220 /*@{*/ 00221 #define BP_AIPS_MPRA_MTW5 (9U) /*!< Bit position for AIPS_MPRA_MTW5. */ 00222 #define BM_AIPS_MPRA_MTW5 (0x00000200U) /*!< Bit mask for AIPS_MPRA_MTW5. */ 00223 #define BS_AIPS_MPRA_MTW5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW5. */ 00224 00225 /*! @brief Read current value of the AIPS_MPRA_MTW5 field. */ 00226 #define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5)) 00227 00228 /*! @brief Format value for bitfield AIPS_MPRA_MTW5. */ 00229 #define BF_AIPS_MPRA_MTW5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW5) & BM_AIPS_MPRA_MTW5) 00230 00231 /*! @brief Set the MTW5 field to a new value. */ 00232 #define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v)) 00233 /*@}*/ 00234 00235 /*! 00236 * @name Register AIPS_MPRA, field MTR5[10] (RW) 00237 * 00238 * Determines whether the master is trusted for read accesses. 00239 * 00240 * Values: 00241 * - 0 - This master is not trusted for read accesses. 00242 * - 1 - This master is trusted for read accesses. 00243 */ 00244 /*@{*/ 00245 #define BP_AIPS_MPRA_MTR5 (10U) /*!< Bit position for AIPS_MPRA_MTR5. */ 00246 #define BM_AIPS_MPRA_MTR5 (0x00000400U) /*!< Bit mask for AIPS_MPRA_MTR5. */ 00247 #define BS_AIPS_MPRA_MTR5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR5. */ 00248 00249 /*! @brief Read current value of the AIPS_MPRA_MTR5 field. */ 00250 #define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5)) 00251 00252 /*! @brief Format value for bitfield AIPS_MPRA_MTR5. */ 00253 #define BF_AIPS_MPRA_MTR5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR5) & BM_AIPS_MPRA_MTR5) 00254 00255 /*! @brief Set the MTR5 field to a new value. */ 00256 #define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v)) 00257 /*@}*/ 00258 00259 /*! 00260 * @name Register AIPS_MPRA, field MPL4[12] (RW) 00261 * 00262 * Specifies how the privilege level of the master is determined. 00263 * 00264 * Values: 00265 * - 0 - Accesses from this master are forced to user-mode. 00266 * - 1 - Accesses from this master are not forced to user-mode. 00267 */ 00268 /*@{*/ 00269 #define BP_AIPS_MPRA_MPL4 (12U) /*!< Bit position for AIPS_MPRA_MPL4. */ 00270 #define BM_AIPS_MPRA_MPL4 (0x00001000U) /*!< Bit mask for AIPS_MPRA_MPL4. */ 00271 #define BS_AIPS_MPRA_MPL4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL4. */ 00272 00273 /*! @brief Read current value of the AIPS_MPRA_MPL4 field. */ 00274 #define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4)) 00275 00276 /*! @brief Format value for bitfield AIPS_MPRA_MPL4. */ 00277 #define BF_AIPS_MPRA_MPL4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL4) & BM_AIPS_MPRA_MPL4) 00278 00279 /*! @brief Set the MPL4 field to a new value. */ 00280 #define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v)) 00281 /*@}*/ 00282 00283 /*! 00284 * @name Register AIPS_MPRA, field MTW4[13] (RW) 00285 * 00286 * Determines whether the master is trusted for write accesses. 00287 * 00288 * Values: 00289 * - 0 - This master is not trusted for write accesses. 00290 * - 1 - This master is trusted for write accesses. 00291 */ 00292 /*@{*/ 00293 #define BP_AIPS_MPRA_MTW4 (13U) /*!< Bit position for AIPS_MPRA_MTW4. */ 00294 #define BM_AIPS_MPRA_MTW4 (0x00002000U) /*!< Bit mask for AIPS_MPRA_MTW4. */ 00295 #define BS_AIPS_MPRA_MTW4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW4. */ 00296 00297 /*! @brief Read current value of the AIPS_MPRA_MTW4 field. */ 00298 #define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4)) 00299 00300 /*! @brief Format value for bitfield AIPS_MPRA_MTW4. */ 00301 #define BF_AIPS_MPRA_MTW4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW4) & BM_AIPS_MPRA_MTW4) 00302 00303 /*! @brief Set the MTW4 field to a new value. */ 00304 #define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v)) 00305 /*@}*/ 00306 00307 /*! 00308 * @name Register AIPS_MPRA, field MTR4[14] (RW) 00309 * 00310 * Determines whether the master is trusted for read accesses. 00311 * 00312 * Values: 00313 * - 0 - This master is not trusted for read accesses. 00314 * - 1 - This master is trusted for read accesses. 00315 */ 00316 /*@{*/ 00317 #define BP_AIPS_MPRA_MTR4 (14U) /*!< Bit position for AIPS_MPRA_MTR4. */ 00318 #define BM_AIPS_MPRA_MTR4 (0x00004000U) /*!< Bit mask for AIPS_MPRA_MTR4. */ 00319 #define BS_AIPS_MPRA_MTR4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR4. */ 00320 00321 /*! @brief Read current value of the AIPS_MPRA_MTR4 field. */ 00322 #define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4)) 00323 00324 /*! @brief Format value for bitfield AIPS_MPRA_MTR4. */ 00325 #define BF_AIPS_MPRA_MTR4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR4) & BM_AIPS_MPRA_MTR4) 00326 00327 /*! @brief Set the MTR4 field to a new value. */ 00328 #define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v)) 00329 /*@}*/ 00330 00331 /*! 00332 * @name Register AIPS_MPRA, field MPL3[16] (RW) 00333 * 00334 * Specifies how the privilege level of the master is determined. 00335 * 00336 * Values: 00337 * - 0 - Accesses from this master are forced to user-mode. 00338 * - 1 - Accesses from this master are not forced to user-mode. 00339 */ 00340 /*@{*/ 00341 #define BP_AIPS_MPRA_MPL3 (16U) /*!< Bit position for AIPS_MPRA_MPL3. */ 00342 #define BM_AIPS_MPRA_MPL3 (0x00010000U) /*!< Bit mask for AIPS_MPRA_MPL3. */ 00343 #define BS_AIPS_MPRA_MPL3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL3. */ 00344 00345 /*! @brief Read current value of the AIPS_MPRA_MPL3 field. */ 00346 #define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3)) 00347 00348 /*! @brief Format value for bitfield AIPS_MPRA_MPL3. */ 00349 #define BF_AIPS_MPRA_MPL3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL3) & BM_AIPS_MPRA_MPL3) 00350 00351 /*! @brief Set the MPL3 field to a new value. */ 00352 #define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v)) 00353 /*@}*/ 00354 00355 /*! 00356 * @name Register AIPS_MPRA, field MTW3[17] (RW) 00357 * 00358 * Determines whether the master is trusted for write accesses. 00359 * 00360 * Values: 00361 * - 0 - This master is not trusted for write accesses. 00362 * - 1 - This master is trusted for write accesses. 00363 */ 00364 /*@{*/ 00365 #define BP_AIPS_MPRA_MTW3 (17U) /*!< Bit position for AIPS_MPRA_MTW3. */ 00366 #define BM_AIPS_MPRA_MTW3 (0x00020000U) /*!< Bit mask for AIPS_MPRA_MTW3. */ 00367 #define BS_AIPS_MPRA_MTW3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW3. */ 00368 00369 /*! @brief Read current value of the AIPS_MPRA_MTW3 field. */ 00370 #define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3)) 00371 00372 /*! @brief Format value for bitfield AIPS_MPRA_MTW3. */ 00373 #define BF_AIPS_MPRA_MTW3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW3) & BM_AIPS_MPRA_MTW3) 00374 00375 /*! @brief Set the MTW3 field to a new value. */ 00376 #define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v)) 00377 /*@}*/ 00378 00379 /*! 00380 * @name Register AIPS_MPRA, field MTR3[18] (RW) 00381 * 00382 * Determines whether the master is trusted for read accesses. 00383 * 00384 * Values: 00385 * - 0 - This master is not trusted for read accesses. 00386 * - 1 - This master is trusted for read accesses. 00387 */ 00388 /*@{*/ 00389 #define BP_AIPS_MPRA_MTR3 (18U) /*!< Bit position for AIPS_MPRA_MTR3. */ 00390 #define BM_AIPS_MPRA_MTR3 (0x00040000U) /*!< Bit mask for AIPS_MPRA_MTR3. */ 00391 #define BS_AIPS_MPRA_MTR3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR3. */ 00392 00393 /*! @brief Read current value of the AIPS_MPRA_MTR3 field. */ 00394 #define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3)) 00395 00396 /*! @brief Format value for bitfield AIPS_MPRA_MTR3. */ 00397 #define BF_AIPS_MPRA_MTR3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR3) & BM_AIPS_MPRA_MTR3) 00398 00399 /*! @brief Set the MTR3 field to a new value. */ 00400 #define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v)) 00401 /*@}*/ 00402 00403 /*! 00404 * @name Register AIPS_MPRA, field MPL2[20] (RW) 00405 * 00406 * Specifies how the privilege level of the master is determined. 00407 * 00408 * Values: 00409 * - 0 - Accesses from this master are forced to user-mode. 00410 * - 1 - Accesses from this master are not forced to user-mode. 00411 */ 00412 /*@{*/ 00413 #define BP_AIPS_MPRA_MPL2 (20U) /*!< Bit position for AIPS_MPRA_MPL2. */ 00414 #define BM_AIPS_MPRA_MPL2 (0x00100000U) /*!< Bit mask for AIPS_MPRA_MPL2. */ 00415 #define BS_AIPS_MPRA_MPL2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL2. */ 00416 00417 /*! @brief Read current value of the AIPS_MPRA_MPL2 field. */ 00418 #define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2)) 00419 00420 /*! @brief Format value for bitfield AIPS_MPRA_MPL2. */ 00421 #define BF_AIPS_MPRA_MPL2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL2) & BM_AIPS_MPRA_MPL2) 00422 00423 /*! @brief Set the MPL2 field to a new value. */ 00424 #define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v)) 00425 /*@}*/ 00426 00427 /*! 00428 * @name Register AIPS_MPRA, field MTW2[21] (RW) 00429 * 00430 * Determines whether the master is trusted for write accesses. 00431 * 00432 * Values: 00433 * - 0 - This master is not trusted for write accesses. 00434 * - 1 - This master is trusted for write accesses. 00435 */ 00436 /*@{*/ 00437 #define BP_AIPS_MPRA_MTW2 (21U) /*!< Bit position for AIPS_MPRA_MTW2. */ 00438 #define BM_AIPS_MPRA_MTW2 (0x00200000U) /*!< Bit mask for AIPS_MPRA_MTW2. */ 00439 #define BS_AIPS_MPRA_MTW2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW2. */ 00440 00441 /*! @brief Read current value of the AIPS_MPRA_MTW2 field. */ 00442 #define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2)) 00443 00444 /*! @brief Format value for bitfield AIPS_MPRA_MTW2. */ 00445 #define BF_AIPS_MPRA_MTW2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW2) & BM_AIPS_MPRA_MTW2) 00446 00447 /*! @brief Set the MTW2 field to a new value. */ 00448 #define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v)) 00449 /*@}*/ 00450 00451 /*! 00452 * @name Register AIPS_MPRA, field MTR2[22] (RW) 00453 * 00454 * Determines whether the master is trusted for read accesses. 00455 * 00456 * Values: 00457 * - 0 - This master is not trusted for read accesses. 00458 * - 1 - This master is trusted for read accesses. 00459 */ 00460 /*@{*/ 00461 #define BP_AIPS_MPRA_MTR2 (22U) /*!< Bit position for AIPS_MPRA_MTR2. */ 00462 #define BM_AIPS_MPRA_MTR2 (0x00400000U) /*!< Bit mask for AIPS_MPRA_MTR2. */ 00463 #define BS_AIPS_MPRA_MTR2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR2. */ 00464 00465 /*! @brief Read current value of the AIPS_MPRA_MTR2 field. */ 00466 #define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2)) 00467 00468 /*! @brief Format value for bitfield AIPS_MPRA_MTR2. */ 00469 #define BF_AIPS_MPRA_MTR2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR2) & BM_AIPS_MPRA_MTR2) 00470 00471 /*! @brief Set the MTR2 field to a new value. */ 00472 #define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v)) 00473 /*@}*/ 00474 00475 /*! 00476 * @name Register AIPS_MPRA, field MPL1[24] (RW) 00477 * 00478 * Specifies how the privilege level of the master is determined. 00479 * 00480 * Values: 00481 * - 0 - Accesses from this master are forced to user-mode. 00482 * - 1 - Accesses from this master are not forced to user-mode. 00483 */ 00484 /*@{*/ 00485 #define BP_AIPS_MPRA_MPL1 (24U) /*!< Bit position for AIPS_MPRA_MPL1. */ 00486 #define BM_AIPS_MPRA_MPL1 (0x01000000U) /*!< Bit mask for AIPS_MPRA_MPL1. */ 00487 #define BS_AIPS_MPRA_MPL1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL1. */ 00488 00489 /*! @brief Read current value of the AIPS_MPRA_MPL1 field. */ 00490 #define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1)) 00491 00492 /*! @brief Format value for bitfield AIPS_MPRA_MPL1. */ 00493 #define BF_AIPS_MPRA_MPL1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL1) & BM_AIPS_MPRA_MPL1) 00494 00495 /*! @brief Set the MPL1 field to a new value. */ 00496 #define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v)) 00497 /*@}*/ 00498 00499 /*! 00500 * @name Register AIPS_MPRA, field MTW1[25] (RW) 00501 * 00502 * Determines whether the master is trusted for write accesses. 00503 * 00504 * Values: 00505 * - 0 - This master is not trusted for write accesses. 00506 * - 1 - This master is trusted for write accesses. 00507 */ 00508 /*@{*/ 00509 #define BP_AIPS_MPRA_MTW1 (25U) /*!< Bit position for AIPS_MPRA_MTW1. */ 00510 #define BM_AIPS_MPRA_MTW1 (0x02000000U) /*!< Bit mask for AIPS_MPRA_MTW1. */ 00511 #define BS_AIPS_MPRA_MTW1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW1. */ 00512 00513 /*! @brief Read current value of the AIPS_MPRA_MTW1 field. */ 00514 #define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1)) 00515 00516 /*! @brief Format value for bitfield AIPS_MPRA_MTW1. */ 00517 #define BF_AIPS_MPRA_MTW1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW1) & BM_AIPS_MPRA_MTW1) 00518 00519 /*! @brief Set the MTW1 field to a new value. */ 00520 #define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v)) 00521 /*@}*/ 00522 00523 /*! 00524 * @name Register AIPS_MPRA, field MTR1[26] (RW) 00525 * 00526 * Determines whether the master is trusted for read accesses. 00527 * 00528 * Values: 00529 * - 0 - This master is not trusted for read accesses. 00530 * - 1 - This master is trusted for read accesses. 00531 */ 00532 /*@{*/ 00533 #define BP_AIPS_MPRA_MTR1 (26U) /*!< Bit position for AIPS_MPRA_MTR1. */ 00534 #define BM_AIPS_MPRA_MTR1 (0x04000000U) /*!< Bit mask for AIPS_MPRA_MTR1. */ 00535 #define BS_AIPS_MPRA_MTR1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR1. */ 00536 00537 /*! @brief Read current value of the AIPS_MPRA_MTR1 field. */ 00538 #define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1)) 00539 00540 /*! @brief Format value for bitfield AIPS_MPRA_MTR1. */ 00541 #define BF_AIPS_MPRA_MTR1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR1) & BM_AIPS_MPRA_MTR1) 00542 00543 /*! @brief Set the MTR1 field to a new value. */ 00544 #define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v)) 00545 /*@}*/ 00546 00547 /*! 00548 * @name Register AIPS_MPRA, field MPL0[28] (RW) 00549 * 00550 * Specifies how the privilege level of the master is determined. 00551 * 00552 * Values: 00553 * - 0 - Accesses from this master are forced to user-mode. 00554 * - 1 - Accesses from this master are not forced to user-mode. 00555 */ 00556 /*@{*/ 00557 #define BP_AIPS_MPRA_MPL0 (28U) /*!< Bit position for AIPS_MPRA_MPL0. */ 00558 #define BM_AIPS_MPRA_MPL0 (0x10000000U) /*!< Bit mask for AIPS_MPRA_MPL0. */ 00559 #define BS_AIPS_MPRA_MPL0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL0. */ 00560 00561 /*! @brief Read current value of the AIPS_MPRA_MPL0 field. */ 00562 #define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0)) 00563 00564 /*! @brief Format value for bitfield AIPS_MPRA_MPL0. */ 00565 #define BF_AIPS_MPRA_MPL0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL0) & BM_AIPS_MPRA_MPL0) 00566 00567 /*! @brief Set the MPL0 field to a new value. */ 00568 #define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v)) 00569 /*@}*/ 00570 00571 /*! 00572 * @name Register AIPS_MPRA, field MTW0[29] (RW) 00573 * 00574 * Determines whether the master is trusted for write accesses. 00575 * 00576 * Values: 00577 * - 0 - This master is not trusted for write accesses. 00578 * - 1 - This master is trusted for write accesses. 00579 */ 00580 /*@{*/ 00581 #define BP_AIPS_MPRA_MTW0 (29U) /*!< Bit position for AIPS_MPRA_MTW0. */ 00582 #define BM_AIPS_MPRA_MTW0 (0x20000000U) /*!< Bit mask for AIPS_MPRA_MTW0. */ 00583 #define BS_AIPS_MPRA_MTW0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW0. */ 00584 00585 /*! @brief Read current value of the AIPS_MPRA_MTW0 field. */ 00586 #define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0)) 00587 00588 /*! @brief Format value for bitfield AIPS_MPRA_MTW0. */ 00589 #define BF_AIPS_MPRA_MTW0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW0) & BM_AIPS_MPRA_MTW0) 00590 00591 /*! @brief Set the MTW0 field to a new value. */ 00592 #define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v)) 00593 /*@}*/ 00594 00595 /*! 00596 * @name Register AIPS_MPRA, field MTR0[30] (RW) 00597 * 00598 * Determines whether the master is trusted for read accesses. 00599 * 00600 * Values: 00601 * - 0 - This master is not trusted for read accesses. 00602 * - 1 - This master is trusted for read accesses. 00603 */ 00604 /*@{*/ 00605 #define BP_AIPS_MPRA_MTR0 (30U) /*!< Bit position for AIPS_MPRA_MTR0. */ 00606 #define BM_AIPS_MPRA_MTR0 (0x40000000U) /*!< Bit mask for AIPS_MPRA_MTR0. */ 00607 #define BS_AIPS_MPRA_MTR0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR0. */ 00608 00609 /*! @brief Read current value of the AIPS_MPRA_MTR0 field. */ 00610 #define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0)) 00611 00612 /*! @brief Format value for bitfield AIPS_MPRA_MTR0. */ 00613 #define BF_AIPS_MPRA_MTR0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR0) & BM_AIPS_MPRA_MTR0) 00614 00615 /*! @brief Set the MTR0 field to a new value. */ 00616 #define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v)) 00617 /*@}*/ 00618 00619 /******************************************************************************* 00620 * HW_AIPS_PACRA - Peripheral Access Control Register 00621 ******************************************************************************/ 00622 00623 /*! 00624 * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) 00625 * 00626 * Reset value: 0x50004000U 00627 * 00628 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 00629 * defines the access levels for a particular peripheral. The mapping between a 00630 * peripheral and its PACR field is shown in the table below. The peripheral assignment 00631 * to each PACR is defined by the memory map slot that the peripheral is 00632 * assigned to. See this chip's memory map for the assignment of a particular 00633 * peripheral. The following table shows the location of each peripheral slot's PACR field 00634 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 00635 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 00636 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 00637 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 00638 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 00639 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 00640 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 00641 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 00642 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 00643 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 00644 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 00645 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 00646 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 00647 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 00648 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 00649 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 00650 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 00651 * A-D, which control peripheral slots 0-31, are shown below. The following 00652 * section, PACRPeripheral Access Control Register , shows the register field 00653 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 00654 * sections because they occupy two non-contiguous address spaces. 00655 */ 00656 typedef union _hw_aips_pacra 00657 { 00658 uint32_t U; 00659 struct _hw_aips_pacra_bitfields 00660 { 00661 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 00662 uint32_t WP7 : 1; /*!< [1] Write Protect */ 00663 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 00664 uint32_t RESERVED0 : 1; /*!< [3] */ 00665 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 00666 uint32_t WP6 : 1; /*!< [5] Write Protect */ 00667 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 00668 uint32_t RESERVED1 : 1; /*!< [7] */ 00669 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 00670 uint32_t WP5 : 1; /*!< [9] Write Protect */ 00671 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 00672 uint32_t RESERVED2 : 1; /*!< [11] */ 00673 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 00674 uint32_t WP4 : 1; /*!< [13] Write Protect */ 00675 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 00676 uint32_t RESERVED3 : 1; /*!< [15] */ 00677 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 00678 uint32_t WP3 : 1; /*!< [17] Write Protect */ 00679 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 00680 uint32_t RESERVED4 : 1; /*!< [19] */ 00681 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 00682 uint32_t WP2 : 1; /*!< [21] Write Protect */ 00683 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 00684 uint32_t RESERVED5 : 1; /*!< [23] */ 00685 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 00686 uint32_t WP1 : 1; /*!< [25] Write Protect */ 00687 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 00688 uint32_t RESERVED6 : 1; /*!< [27] */ 00689 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 00690 uint32_t WP0 : 1; /*!< [29] Write Protect */ 00691 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 00692 uint32_t RESERVED7 : 1; /*!< [31] */ 00693 } B; 00694 } hw_aips_pacra_t; 00695 00696 /*! 00697 * @name Constants and macros for entire AIPS_PACRA register 00698 */ 00699 /*@{*/ 00700 #define HW_AIPS_PACRA_ADDR(x) ((x) + 0x20U) 00701 00702 #define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) 00703 #define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U) 00704 #define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v)) 00705 #define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) 00706 #define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) 00707 #define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) 00708 /*@}*/ 00709 00710 /* 00711 * Constants & macros for individual AIPS_PACRA bitfields 00712 */ 00713 00714 /*! 00715 * @name Register AIPS_PACRA, field TP7[0] (RW) 00716 * 00717 * Determines whether the peripheral allows accesses from an untrusted master. 00718 * When this field is set and an access is attempted by an untrusted master, the 00719 * access terminates with an error response and no peripheral access initiates. 00720 * 00721 * Values: 00722 * - 0 - Accesses from an untrusted master are allowed. 00723 * - 1 - Accesses from an untrusted master are not allowed. 00724 */ 00725 /*@{*/ 00726 #define BP_AIPS_PACRA_TP7 (0U) /*!< Bit position for AIPS_PACRA_TP7. */ 00727 #define BM_AIPS_PACRA_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRA_TP7. */ 00728 #define BS_AIPS_PACRA_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP7. */ 00729 00730 /*! @brief Read current value of the AIPS_PACRA_TP7 field. */ 00731 #define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7)) 00732 00733 /*! @brief Format value for bitfield AIPS_PACRA_TP7. */ 00734 #define BF_AIPS_PACRA_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP7) & BM_AIPS_PACRA_TP7) 00735 00736 /*! @brief Set the TP7 field to a new value. */ 00737 #define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v)) 00738 /*@}*/ 00739 00740 /*! 00741 * @name Register AIPS_PACRA, field WP7[1] (RW) 00742 * 00743 * Determines whether the peripheral allows write accesses. When this field is 00744 * set and a write access is attempted, access terminates with an error response 00745 * and no peripheral access initiates. 00746 * 00747 * Values: 00748 * - 0 - This peripheral allows write accesses. 00749 * - 1 - This peripheral is write protected. 00750 */ 00751 /*@{*/ 00752 #define BP_AIPS_PACRA_WP7 (1U) /*!< Bit position for AIPS_PACRA_WP7. */ 00753 #define BM_AIPS_PACRA_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRA_WP7. */ 00754 #define BS_AIPS_PACRA_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP7. */ 00755 00756 /*! @brief Read current value of the AIPS_PACRA_WP7 field. */ 00757 #define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7)) 00758 00759 /*! @brief Format value for bitfield AIPS_PACRA_WP7. */ 00760 #define BF_AIPS_PACRA_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP7) & BM_AIPS_PACRA_WP7) 00761 00762 /*! @brief Set the WP7 field to a new value. */ 00763 #define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v)) 00764 /*@}*/ 00765 00766 /*! 00767 * @name Register AIPS_PACRA, field SP7[2] (RW) 00768 * 00769 * Determines whether the peripheral requires supervisor privilege level for 00770 * accesses. When this field is set, the master privilege level must indicate the 00771 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00772 * must be set. If not, access terminates with an error response and no peripheral 00773 * access initiates. 00774 * 00775 * Values: 00776 * - 0 - This peripheral does not require supervisor privilege level for 00777 * accesses. 00778 * - 1 - This peripheral requires supervisor privilege level for accesses. 00779 */ 00780 /*@{*/ 00781 #define BP_AIPS_PACRA_SP7 (2U) /*!< Bit position for AIPS_PACRA_SP7. */ 00782 #define BM_AIPS_PACRA_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRA_SP7. */ 00783 #define BS_AIPS_PACRA_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP7. */ 00784 00785 /*! @brief Read current value of the AIPS_PACRA_SP7 field. */ 00786 #define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7)) 00787 00788 /*! @brief Format value for bitfield AIPS_PACRA_SP7. */ 00789 #define BF_AIPS_PACRA_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP7) & BM_AIPS_PACRA_SP7) 00790 00791 /*! @brief Set the SP7 field to a new value. */ 00792 #define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v)) 00793 /*@}*/ 00794 00795 /*! 00796 * @name Register AIPS_PACRA, field TP6[4] (RW) 00797 * 00798 * Determines whether the peripheral allows accesses from an untrusted master. 00799 * When this field is set and an access is attempted by an untrusted master, the 00800 * access terminates with an error response and no peripheral access initiates. 00801 * 00802 * Values: 00803 * - 0 - Accesses from an untrusted master are allowed. 00804 * - 1 - Accesses from an untrusted master are not allowed. 00805 */ 00806 /*@{*/ 00807 #define BP_AIPS_PACRA_TP6 (4U) /*!< Bit position for AIPS_PACRA_TP6. */ 00808 #define BM_AIPS_PACRA_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRA_TP6. */ 00809 #define BS_AIPS_PACRA_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP6. */ 00810 00811 /*! @brief Read current value of the AIPS_PACRA_TP6 field. */ 00812 #define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6)) 00813 00814 /*! @brief Format value for bitfield AIPS_PACRA_TP6. */ 00815 #define BF_AIPS_PACRA_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP6) & BM_AIPS_PACRA_TP6) 00816 00817 /*! @brief Set the TP6 field to a new value. */ 00818 #define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v)) 00819 /*@}*/ 00820 00821 /*! 00822 * @name Register AIPS_PACRA, field WP6[5] (RW) 00823 * 00824 * Determines whether the peripheral allows write accesses. When this field is 00825 * set and a write access is attempted, access terminates with an error response 00826 * and no peripheral access initiates. 00827 * 00828 * Values: 00829 * - 0 - This peripheral allows write accesses. 00830 * - 1 - This peripheral is write protected. 00831 */ 00832 /*@{*/ 00833 #define BP_AIPS_PACRA_WP6 (5U) /*!< Bit position for AIPS_PACRA_WP6. */ 00834 #define BM_AIPS_PACRA_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRA_WP6. */ 00835 #define BS_AIPS_PACRA_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP6. */ 00836 00837 /*! @brief Read current value of the AIPS_PACRA_WP6 field. */ 00838 #define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6)) 00839 00840 /*! @brief Format value for bitfield AIPS_PACRA_WP6. */ 00841 #define BF_AIPS_PACRA_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP6) & BM_AIPS_PACRA_WP6) 00842 00843 /*! @brief Set the WP6 field to a new value. */ 00844 #define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v)) 00845 /*@}*/ 00846 00847 /*! 00848 * @name Register AIPS_PACRA, field SP6[6] (RW) 00849 * 00850 * Determines whether the peripheral requires supervisor privilege level for 00851 * accesses. When this field is set, the master privilege level must indicate the 00852 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00853 * must be set. If not, access terminates with an error response and no peripheral 00854 * access initiates. 00855 * 00856 * Values: 00857 * - 0 - This peripheral does not require supervisor privilege level for 00858 * accesses. 00859 * - 1 - This peripheral requires supervisor privilege level for accesses. 00860 */ 00861 /*@{*/ 00862 #define BP_AIPS_PACRA_SP6 (6U) /*!< Bit position for AIPS_PACRA_SP6. */ 00863 #define BM_AIPS_PACRA_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRA_SP6. */ 00864 #define BS_AIPS_PACRA_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP6. */ 00865 00866 /*! @brief Read current value of the AIPS_PACRA_SP6 field. */ 00867 #define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6)) 00868 00869 /*! @brief Format value for bitfield AIPS_PACRA_SP6. */ 00870 #define BF_AIPS_PACRA_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP6) & BM_AIPS_PACRA_SP6) 00871 00872 /*! @brief Set the SP6 field to a new value. */ 00873 #define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v)) 00874 /*@}*/ 00875 00876 /*! 00877 * @name Register AIPS_PACRA, field TP5[8] (RW) 00878 * 00879 * Determines whether the peripheral allows accesses from an untrusted master. 00880 * When this field is set and an access is attempted by an untrusted master, the 00881 * access terminates with an error response and no peripheral access initiates. 00882 * 00883 * Values: 00884 * - 0 - Accesses from an untrusted master are allowed. 00885 * - 1 - Accesses from an untrusted master are not allowed. 00886 */ 00887 /*@{*/ 00888 #define BP_AIPS_PACRA_TP5 (8U) /*!< Bit position for AIPS_PACRA_TP5. */ 00889 #define BM_AIPS_PACRA_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRA_TP5. */ 00890 #define BS_AIPS_PACRA_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP5. */ 00891 00892 /*! @brief Read current value of the AIPS_PACRA_TP5 field. */ 00893 #define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5)) 00894 00895 /*! @brief Format value for bitfield AIPS_PACRA_TP5. */ 00896 #define BF_AIPS_PACRA_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP5) & BM_AIPS_PACRA_TP5) 00897 00898 /*! @brief Set the TP5 field to a new value. */ 00899 #define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v)) 00900 /*@}*/ 00901 00902 /*! 00903 * @name Register AIPS_PACRA, field WP5[9] (RW) 00904 * 00905 * Determines whether the peripheral allows write accesses. When this field is 00906 * set and a write access is attempted, access terminates with an error response 00907 * and no peripheral access initiates. 00908 * 00909 * Values: 00910 * - 0 - This peripheral allows write accesses. 00911 * - 1 - This peripheral is write protected. 00912 */ 00913 /*@{*/ 00914 #define BP_AIPS_PACRA_WP5 (9U) /*!< Bit position for AIPS_PACRA_WP5. */ 00915 #define BM_AIPS_PACRA_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRA_WP5. */ 00916 #define BS_AIPS_PACRA_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP5. */ 00917 00918 /*! @brief Read current value of the AIPS_PACRA_WP5 field. */ 00919 #define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5)) 00920 00921 /*! @brief Format value for bitfield AIPS_PACRA_WP5. */ 00922 #define BF_AIPS_PACRA_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP5) & BM_AIPS_PACRA_WP5) 00923 00924 /*! @brief Set the WP5 field to a new value. */ 00925 #define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v)) 00926 /*@}*/ 00927 00928 /*! 00929 * @name Register AIPS_PACRA, field SP5[10] (RW) 00930 * 00931 * Determines whether the peripheral requires supervisor privilege level for 00932 * accesses. When this field is set, the master privilege level must indicate the 00933 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00934 * must be set. If not, access terminates with an error response and no peripheral 00935 * access initiates. 00936 * 00937 * Values: 00938 * - 0 - This peripheral does not require supervisor privilege level for 00939 * accesses. 00940 * - 1 - This peripheral requires supervisor privilege level for accesses. 00941 */ 00942 /*@{*/ 00943 #define BP_AIPS_PACRA_SP5 (10U) /*!< Bit position for AIPS_PACRA_SP5. */ 00944 #define BM_AIPS_PACRA_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRA_SP5. */ 00945 #define BS_AIPS_PACRA_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP5. */ 00946 00947 /*! @brief Read current value of the AIPS_PACRA_SP5 field. */ 00948 #define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5)) 00949 00950 /*! @brief Format value for bitfield AIPS_PACRA_SP5. */ 00951 #define BF_AIPS_PACRA_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP5) & BM_AIPS_PACRA_SP5) 00952 00953 /*! @brief Set the SP5 field to a new value. */ 00954 #define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v)) 00955 /*@}*/ 00956 00957 /*! 00958 * @name Register AIPS_PACRA, field TP4[12] (RW) 00959 * 00960 * Determines whether the peripheral allows accesses from an untrusted master. 00961 * When this field is set and an access is attempted by an untrusted master, the 00962 * access terminates with an error response and no peripheral access initiates. 00963 * 00964 * Values: 00965 * - 0 - Accesses from an untrusted master are allowed. 00966 * - 1 - Accesses from an untrusted master are not allowed. 00967 */ 00968 /*@{*/ 00969 #define BP_AIPS_PACRA_TP4 (12U) /*!< Bit position for AIPS_PACRA_TP4. */ 00970 #define BM_AIPS_PACRA_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRA_TP4. */ 00971 #define BS_AIPS_PACRA_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP4. */ 00972 00973 /*! @brief Read current value of the AIPS_PACRA_TP4 field. */ 00974 #define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4)) 00975 00976 /*! @brief Format value for bitfield AIPS_PACRA_TP4. */ 00977 #define BF_AIPS_PACRA_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP4) & BM_AIPS_PACRA_TP4) 00978 00979 /*! @brief Set the TP4 field to a new value. */ 00980 #define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v)) 00981 /*@}*/ 00982 00983 /*! 00984 * @name Register AIPS_PACRA, field WP4[13] (RW) 00985 * 00986 * Determines whether the peripheral allows write accesss. When this bit is set 00987 * and a write access is attempted, access terminates with an error response and 00988 * no peripheral access initiates. 00989 * 00990 * Values: 00991 * - 0 - This peripheral allows write accesses. 00992 * - 1 - This peripheral is write protected. 00993 */ 00994 /*@{*/ 00995 #define BP_AIPS_PACRA_WP4 (13U) /*!< Bit position for AIPS_PACRA_WP4. */ 00996 #define BM_AIPS_PACRA_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRA_WP4. */ 00997 #define BS_AIPS_PACRA_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP4. */ 00998 00999 /*! @brief Read current value of the AIPS_PACRA_WP4 field. */ 01000 #define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4)) 01001 01002 /*! @brief Format value for bitfield AIPS_PACRA_WP4. */ 01003 #define BF_AIPS_PACRA_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP4) & BM_AIPS_PACRA_WP4) 01004 01005 /*! @brief Set the WP4 field to a new value. */ 01006 #define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v)) 01007 /*@}*/ 01008 01009 /*! 01010 * @name Register AIPS_PACRA, field SP4[14] (RW) 01011 * 01012 * Determines whether the peripheral requires supervisor privilege level for 01013 * accesses. When this field is set, the master privilege level must indicate the 01014 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01015 * must be set. If not, access terminates with an error response and no peripheral 01016 * access initiates. 01017 * 01018 * Values: 01019 * - 0 - This peripheral does not require supervisor privilege level for 01020 * accesses. 01021 * - 1 - This peripheral requires supervisor privilege level for accesses. 01022 */ 01023 /*@{*/ 01024 #define BP_AIPS_PACRA_SP4 (14U) /*!< Bit position for AIPS_PACRA_SP4. */ 01025 #define BM_AIPS_PACRA_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRA_SP4. */ 01026 #define BS_AIPS_PACRA_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP4. */ 01027 01028 /*! @brief Read current value of the AIPS_PACRA_SP4 field. */ 01029 #define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4)) 01030 01031 /*! @brief Format value for bitfield AIPS_PACRA_SP4. */ 01032 #define BF_AIPS_PACRA_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP4) & BM_AIPS_PACRA_SP4) 01033 01034 /*! @brief Set the SP4 field to a new value. */ 01035 #define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v)) 01036 /*@}*/ 01037 01038 /*! 01039 * @name Register AIPS_PACRA, field TP3[16] (RW) 01040 * 01041 * Determines whether the peripheral allows accesses from an untrusted master. 01042 * When this bit is set and an access is attempted by an untrusted master, the 01043 * access terminates with an error response and no peripheral access initiates. 01044 * 01045 * Values: 01046 * - 0 - Accesses from an untrusted master are allowed. 01047 * - 1 - Accesses from an untrusted master are not allowed. 01048 */ 01049 /*@{*/ 01050 #define BP_AIPS_PACRA_TP3 (16U) /*!< Bit position for AIPS_PACRA_TP3. */ 01051 #define BM_AIPS_PACRA_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRA_TP3. */ 01052 #define BS_AIPS_PACRA_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP3. */ 01053 01054 /*! @brief Read current value of the AIPS_PACRA_TP3 field. */ 01055 #define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3)) 01056 01057 /*! @brief Format value for bitfield AIPS_PACRA_TP3. */ 01058 #define BF_AIPS_PACRA_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP3) & BM_AIPS_PACRA_TP3) 01059 01060 /*! @brief Set the TP3 field to a new value. */ 01061 #define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v)) 01062 /*@}*/ 01063 01064 /*! 01065 * @name Register AIPS_PACRA, field WP3[17] (RW) 01066 * 01067 * Determines whether the peripheral allows write accesses. When this field is 01068 * set and a write access is attempted, access terminates with an error response 01069 * and no peripheral access initiates. 01070 * 01071 * Values: 01072 * - 0 - This peripheral allows write accesses. 01073 * - 1 - This peripheral is write protected. 01074 */ 01075 /*@{*/ 01076 #define BP_AIPS_PACRA_WP3 (17U) /*!< Bit position for AIPS_PACRA_WP3. */ 01077 #define BM_AIPS_PACRA_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRA_WP3. */ 01078 #define BS_AIPS_PACRA_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP3. */ 01079 01080 /*! @brief Read current value of the AIPS_PACRA_WP3 field. */ 01081 #define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3)) 01082 01083 /*! @brief Format value for bitfield AIPS_PACRA_WP3. */ 01084 #define BF_AIPS_PACRA_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP3) & BM_AIPS_PACRA_WP3) 01085 01086 /*! @brief Set the WP3 field to a new value. */ 01087 #define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v)) 01088 /*@}*/ 01089 01090 /*! 01091 * @name Register AIPS_PACRA, field SP3[18] (RW) 01092 * 01093 * Determines whether the peripheral requires supervisor privilege level for 01094 * access. When this bit is set, the master privilege level must indicate the 01095 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 01096 * set. If not, access terminates with an error response and no peripheral access 01097 * initiates. 01098 * 01099 * Values: 01100 * - 0 - This peripheral does not require supervisor privilege level for 01101 * accesses. 01102 * - 1 - This peripheral requires supervisor privilege level for accesses. 01103 */ 01104 /*@{*/ 01105 #define BP_AIPS_PACRA_SP3 (18U) /*!< Bit position for AIPS_PACRA_SP3. */ 01106 #define BM_AIPS_PACRA_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRA_SP3. */ 01107 #define BS_AIPS_PACRA_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP3. */ 01108 01109 /*! @brief Read current value of the AIPS_PACRA_SP3 field. */ 01110 #define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3)) 01111 01112 /*! @brief Format value for bitfield AIPS_PACRA_SP3. */ 01113 #define BF_AIPS_PACRA_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP3) & BM_AIPS_PACRA_SP3) 01114 01115 /*! @brief Set the SP3 field to a new value. */ 01116 #define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v)) 01117 /*@}*/ 01118 01119 /*! 01120 * @name Register AIPS_PACRA, field TP2[20] (RW) 01121 * 01122 * Determines whether the peripheral allows accesses from an untrusted master. 01123 * When this field is set and an access is attempted by an untrusted master, the 01124 * access terminates with an error response and no peripheral access initiates. 01125 * 01126 * Values: 01127 * - 0 - Accesses from an untrusted master are allowed. 01128 * - 1 - Accesses from an untrusted master are not allowed. 01129 */ 01130 /*@{*/ 01131 #define BP_AIPS_PACRA_TP2 (20U) /*!< Bit position for AIPS_PACRA_TP2. */ 01132 #define BM_AIPS_PACRA_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRA_TP2. */ 01133 #define BS_AIPS_PACRA_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP2. */ 01134 01135 /*! @brief Read current value of the AIPS_PACRA_TP2 field. */ 01136 #define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2)) 01137 01138 /*! @brief Format value for bitfield AIPS_PACRA_TP2. */ 01139 #define BF_AIPS_PACRA_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP2) & BM_AIPS_PACRA_TP2) 01140 01141 /*! @brief Set the TP2 field to a new value. */ 01142 #define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v)) 01143 /*@}*/ 01144 01145 /*! 01146 * @name Register AIPS_PACRA, field WP2[21] (RW) 01147 * 01148 * Determines whether the peripheral allows write accesss. When this bit is set 01149 * and a write access is attempted, access terminates with an error response and 01150 * no peripheral access initiates. 01151 * 01152 * Values: 01153 * - 0 - This peripheral allows write accesses. 01154 * - 1 - This peripheral is write protected. 01155 */ 01156 /*@{*/ 01157 #define BP_AIPS_PACRA_WP2 (21U) /*!< Bit position for AIPS_PACRA_WP2. */ 01158 #define BM_AIPS_PACRA_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRA_WP2. */ 01159 #define BS_AIPS_PACRA_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP2. */ 01160 01161 /*! @brief Read current value of the AIPS_PACRA_WP2 field. */ 01162 #define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2)) 01163 01164 /*! @brief Format value for bitfield AIPS_PACRA_WP2. */ 01165 #define BF_AIPS_PACRA_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP2) & BM_AIPS_PACRA_WP2) 01166 01167 /*! @brief Set the WP2 field to a new value. */ 01168 #define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v)) 01169 /*@}*/ 01170 01171 /*! 01172 * @name Register AIPS_PACRA, field SP2[22] (RW) 01173 * 01174 * Determines whether the peripheral requires supervisor privilege level for 01175 * accesses. When this field is set, the master privilege level must indicate the 01176 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01177 * must be set. If not, access terminates with an error response and no peripheral 01178 * access initiates. 01179 * 01180 * Values: 01181 * - 0 - This peripheral does not require supervisor privilege level for 01182 * accesses. 01183 * - 1 - This peripheral requires supervisor privilege level for accesses. 01184 */ 01185 /*@{*/ 01186 #define BP_AIPS_PACRA_SP2 (22U) /*!< Bit position for AIPS_PACRA_SP2. */ 01187 #define BM_AIPS_PACRA_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRA_SP2. */ 01188 #define BS_AIPS_PACRA_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP2. */ 01189 01190 /*! @brief Read current value of the AIPS_PACRA_SP2 field. */ 01191 #define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2)) 01192 01193 /*! @brief Format value for bitfield AIPS_PACRA_SP2. */ 01194 #define BF_AIPS_PACRA_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP2) & BM_AIPS_PACRA_SP2) 01195 01196 /*! @brief Set the SP2 field to a new value. */ 01197 #define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v)) 01198 /*@}*/ 01199 01200 /*! 01201 * @name Register AIPS_PACRA, field TP1[24] (RW) 01202 * 01203 * Determines whether the peripheral allows accesses from an untrusted master. 01204 * When this bit is set and an access is attempted by an untrusted master, the 01205 * access terminates with an error response and no peripheral access initiates. 01206 * 01207 * Values: 01208 * - 0 - Accesses from an untrusted master are allowed. 01209 * - 1 - Accesses from an untrusted master are not allowed. 01210 */ 01211 /*@{*/ 01212 #define BP_AIPS_PACRA_TP1 (24U) /*!< Bit position for AIPS_PACRA_TP1. */ 01213 #define BM_AIPS_PACRA_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRA_TP1. */ 01214 #define BS_AIPS_PACRA_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP1. */ 01215 01216 /*! @brief Read current value of the AIPS_PACRA_TP1 field. */ 01217 #define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1)) 01218 01219 /*! @brief Format value for bitfield AIPS_PACRA_TP1. */ 01220 #define BF_AIPS_PACRA_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP1) & BM_AIPS_PACRA_TP1) 01221 01222 /*! @brief Set the TP1 field to a new value. */ 01223 #define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v)) 01224 /*@}*/ 01225 01226 /*! 01227 * @name Register AIPS_PACRA, field WP1[25] (RW) 01228 * 01229 * Determines whether the peripheral allows write accesses. When this field is 01230 * set and a write access is attempted, access terminates with an error response 01231 * and no peripheral access initiates. 01232 * 01233 * Values: 01234 * - 0 - This peripheral allows write accesses. 01235 * - 1 - This peripheral is write protected. 01236 */ 01237 /*@{*/ 01238 #define BP_AIPS_PACRA_WP1 (25U) /*!< Bit position for AIPS_PACRA_WP1. */ 01239 #define BM_AIPS_PACRA_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRA_WP1. */ 01240 #define BS_AIPS_PACRA_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP1. */ 01241 01242 /*! @brief Read current value of the AIPS_PACRA_WP1 field. */ 01243 #define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1)) 01244 01245 /*! @brief Format value for bitfield AIPS_PACRA_WP1. */ 01246 #define BF_AIPS_PACRA_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP1) & BM_AIPS_PACRA_WP1) 01247 01248 /*! @brief Set the WP1 field to a new value. */ 01249 #define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v)) 01250 /*@}*/ 01251 01252 /*! 01253 * @name Register AIPS_PACRA, field SP1[26] (RW) 01254 * 01255 * Determines whether the peripheral requires supervisor privilege level for 01256 * accesses. When this field is set, the master privilege level must indicate the 01257 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01258 * must be set. If not, access terminates with an error response and no peripheral 01259 * access initiates. 01260 * 01261 * Values: 01262 * - 0 - This peripheral does not require supervisor privilege level for 01263 * accesses. 01264 * - 1 - This peripheral requires supervisor privilege level for accesses. 01265 */ 01266 /*@{*/ 01267 #define BP_AIPS_PACRA_SP1 (26U) /*!< Bit position for AIPS_PACRA_SP1. */ 01268 #define BM_AIPS_PACRA_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRA_SP1. */ 01269 #define BS_AIPS_PACRA_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP1. */ 01270 01271 /*! @brief Read current value of the AIPS_PACRA_SP1 field. */ 01272 #define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1)) 01273 01274 /*! @brief Format value for bitfield AIPS_PACRA_SP1. */ 01275 #define BF_AIPS_PACRA_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP1) & BM_AIPS_PACRA_SP1) 01276 01277 /*! @brief Set the SP1 field to a new value. */ 01278 #define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v)) 01279 /*@}*/ 01280 01281 /*! 01282 * @name Register AIPS_PACRA, field TP0[28] (RW) 01283 * 01284 * Determines whether the peripheral allows accesses from an untrusted master. 01285 * When this field is set and an access is attempted by an untrusted master, the 01286 * access terminates with an error response and no peripheral access initiates. 01287 * 01288 * Values: 01289 * - 0 - Accesses from an untrusted master are allowed. 01290 * - 1 - Accesses from an untrusted master are not allowed. 01291 */ 01292 /*@{*/ 01293 #define BP_AIPS_PACRA_TP0 (28U) /*!< Bit position for AIPS_PACRA_TP0. */ 01294 #define BM_AIPS_PACRA_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRA_TP0. */ 01295 #define BS_AIPS_PACRA_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP0. */ 01296 01297 /*! @brief Read current value of the AIPS_PACRA_TP0 field. */ 01298 #define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0)) 01299 01300 /*! @brief Format value for bitfield AIPS_PACRA_TP0. */ 01301 #define BF_AIPS_PACRA_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP0) & BM_AIPS_PACRA_TP0) 01302 01303 /*! @brief Set the TP0 field to a new value. */ 01304 #define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v)) 01305 /*@}*/ 01306 01307 /*! 01308 * @name Register AIPS_PACRA, field WP0[29] (RW) 01309 * 01310 * Determines whether the peripheral allows write accesss. When this bit is set 01311 * and a write access is attempted, access terminates with an error response and 01312 * no peripheral access initiates. 01313 * 01314 * Values: 01315 * - 0 - This peripheral allows write accesses. 01316 * - 1 - This peripheral is write protected. 01317 */ 01318 /*@{*/ 01319 #define BP_AIPS_PACRA_WP0 (29U) /*!< Bit position for AIPS_PACRA_WP0. */ 01320 #define BM_AIPS_PACRA_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRA_WP0. */ 01321 #define BS_AIPS_PACRA_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP0. */ 01322 01323 /*! @brief Read current value of the AIPS_PACRA_WP0 field. */ 01324 #define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0)) 01325 01326 /*! @brief Format value for bitfield AIPS_PACRA_WP0. */ 01327 #define BF_AIPS_PACRA_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP0) & BM_AIPS_PACRA_WP0) 01328 01329 /*! @brief Set the WP0 field to a new value. */ 01330 #define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v)) 01331 /*@}*/ 01332 01333 /*! 01334 * @name Register AIPS_PACRA, field SP0[30] (RW) 01335 * 01336 * Determines whether the peripheral requires supervisor privilege level for 01337 * accesses. When this field is set, the master privilege level must indicate the 01338 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01339 * must be set. If not, access terminates with an error response and no peripheral 01340 * access initiates. 01341 * 01342 * Values: 01343 * - 0 - This peripheral does not require supervisor privilege level for 01344 * accesses. 01345 * - 1 - This peripheral requires supervisor privilege level for accesses. 01346 */ 01347 /*@{*/ 01348 #define BP_AIPS_PACRA_SP0 (30U) /*!< Bit position for AIPS_PACRA_SP0. */ 01349 #define BM_AIPS_PACRA_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRA_SP0. */ 01350 #define BS_AIPS_PACRA_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP0. */ 01351 01352 /*! @brief Read current value of the AIPS_PACRA_SP0 field. */ 01353 #define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0)) 01354 01355 /*! @brief Format value for bitfield AIPS_PACRA_SP0. */ 01356 #define BF_AIPS_PACRA_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP0) & BM_AIPS_PACRA_SP0) 01357 01358 /*! @brief Set the SP0 field to a new value. */ 01359 #define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v)) 01360 /*@}*/ 01361 01362 /******************************************************************************* 01363 * HW_AIPS_PACRB - Peripheral Access Control Register 01364 ******************************************************************************/ 01365 01366 /*! 01367 * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) 01368 * 01369 * Reset value: 0x44004400U 01370 * 01371 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 01372 * defines the access levels for a particular peripheral. The mapping between a 01373 * peripheral and its PACR field is shown in the table below. The peripheral assignment 01374 * to each PACR is defined by the memory map slot that the peripheral is 01375 * assigned to. See this chip's memory map for the assignment of a particular 01376 * peripheral. The following table shows the location of each peripheral slot's PACR field 01377 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 01378 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 01379 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 01380 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 01381 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 01382 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 01383 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 01384 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 01385 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 01386 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 01387 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 01388 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 01389 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 01390 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 01391 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 01392 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 01393 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 01394 * A-D, which control peripheral slots 0-31, are shown below. The following 01395 * section, PACRPeripheral Access Control Register , shows the register field 01396 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 01397 * sections because they occupy two non-contiguous address spaces. 01398 */ 01399 typedef union _hw_aips_pacrb 01400 { 01401 uint32_t U; 01402 struct _hw_aips_pacrb_bitfields 01403 { 01404 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 01405 uint32_t WP7 : 1; /*!< [1] Write Protect */ 01406 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 01407 uint32_t RESERVED0 : 1; /*!< [3] */ 01408 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 01409 uint32_t WP6 : 1; /*!< [5] Write Protect */ 01410 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 01411 uint32_t RESERVED1 : 1; /*!< [7] */ 01412 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 01413 uint32_t WP5 : 1; /*!< [9] Write Protect */ 01414 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 01415 uint32_t RESERVED2 : 1; /*!< [11] */ 01416 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 01417 uint32_t WP4 : 1; /*!< [13] Write Protect */ 01418 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 01419 uint32_t RESERVED3 : 1; /*!< [15] */ 01420 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 01421 uint32_t WP3 : 1; /*!< [17] Write Protect */ 01422 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 01423 uint32_t RESERVED4 : 1; /*!< [19] */ 01424 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 01425 uint32_t WP2 : 1; /*!< [21] Write Protect */ 01426 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 01427 uint32_t RESERVED5 : 1; /*!< [23] */ 01428 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 01429 uint32_t WP1 : 1; /*!< [25] Write Protect */ 01430 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 01431 uint32_t RESERVED6 : 1; /*!< [27] */ 01432 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 01433 uint32_t WP0 : 1; /*!< [29] Write Protect */ 01434 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 01435 uint32_t RESERVED7 : 1; /*!< [31] */ 01436 } B; 01437 } hw_aips_pacrb_t; 01438 01439 /*! 01440 * @name Constants and macros for entire AIPS_PACRB register 01441 */ 01442 /*@{*/ 01443 #define HW_AIPS_PACRB_ADDR(x) ((x) + 0x24U) 01444 01445 #define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) 01446 #define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U) 01447 #define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v)) 01448 #define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) 01449 #define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) 01450 #define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) 01451 /*@}*/ 01452 01453 /* 01454 * Constants & macros for individual AIPS_PACRB bitfields 01455 */ 01456 01457 /*! 01458 * @name Register AIPS_PACRB, field TP7[0] (RW) 01459 * 01460 * Determines whether the peripheral allows accesses from an untrusted master. 01461 * When this field is set and an access is attempted by an untrusted master, the 01462 * access terminates with an error response and no peripheral access initiates. 01463 * 01464 * Values: 01465 * - 0 - Accesses from an untrusted master are allowed. 01466 * - 1 - Accesses from an untrusted master are not allowed. 01467 */ 01468 /*@{*/ 01469 #define BP_AIPS_PACRB_TP7 (0U) /*!< Bit position for AIPS_PACRB_TP7. */ 01470 #define BM_AIPS_PACRB_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRB_TP7. */ 01471 #define BS_AIPS_PACRB_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP7. */ 01472 01473 /*! @brief Read current value of the AIPS_PACRB_TP7 field. */ 01474 #define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7)) 01475 01476 /*! @brief Format value for bitfield AIPS_PACRB_TP7. */ 01477 #define BF_AIPS_PACRB_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP7) & BM_AIPS_PACRB_TP7) 01478 01479 /*! @brief Set the TP7 field to a new value. */ 01480 #define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v)) 01481 /*@}*/ 01482 01483 /*! 01484 * @name Register AIPS_PACRB, field WP7[1] (RW) 01485 * 01486 * Determines whether the peripheral allows write accesses. When this field is 01487 * set and a write access is attempted, access terminates with an error response 01488 * and no peripheral access initiates. 01489 * 01490 * Values: 01491 * - 0 - This peripheral allows write accesses. 01492 * - 1 - This peripheral is write protected. 01493 */ 01494 /*@{*/ 01495 #define BP_AIPS_PACRB_WP7 (1U) /*!< Bit position for AIPS_PACRB_WP7. */ 01496 #define BM_AIPS_PACRB_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRB_WP7. */ 01497 #define BS_AIPS_PACRB_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP7. */ 01498 01499 /*! @brief Read current value of the AIPS_PACRB_WP7 field. */ 01500 #define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7)) 01501 01502 /*! @brief Format value for bitfield AIPS_PACRB_WP7. */ 01503 #define BF_AIPS_PACRB_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP7) & BM_AIPS_PACRB_WP7) 01504 01505 /*! @brief Set the WP7 field to a new value. */ 01506 #define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v)) 01507 /*@}*/ 01508 01509 /*! 01510 * @name Register AIPS_PACRB, field SP7[2] (RW) 01511 * 01512 * Determines whether the peripheral requires supervisor privilege level for 01513 * accesses. When this field is set, the master privilege level must indicate the 01514 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01515 * must be set. If not, access terminates with an error response and no peripheral 01516 * access initiates. 01517 * 01518 * Values: 01519 * - 0 - This peripheral does not require supervisor privilege level for 01520 * accesses. 01521 * - 1 - This peripheral requires supervisor privilege level for accesses. 01522 */ 01523 /*@{*/ 01524 #define BP_AIPS_PACRB_SP7 (2U) /*!< Bit position for AIPS_PACRB_SP7. */ 01525 #define BM_AIPS_PACRB_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRB_SP7. */ 01526 #define BS_AIPS_PACRB_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP7. */ 01527 01528 /*! @brief Read current value of the AIPS_PACRB_SP7 field. */ 01529 #define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7)) 01530 01531 /*! @brief Format value for bitfield AIPS_PACRB_SP7. */ 01532 #define BF_AIPS_PACRB_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP7) & BM_AIPS_PACRB_SP7) 01533 01534 /*! @brief Set the SP7 field to a new value. */ 01535 #define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v)) 01536 /*@}*/ 01537 01538 /*! 01539 * @name Register AIPS_PACRB, field TP6[4] (RW) 01540 * 01541 * Determines whether the peripheral allows accesses from an untrusted master. 01542 * When this field is set and an access is attempted by an untrusted master, the 01543 * access terminates with an error response and no peripheral access initiates. 01544 * 01545 * Values: 01546 * - 0 - Accesses from an untrusted master are allowed. 01547 * - 1 - Accesses from an untrusted master are not allowed. 01548 */ 01549 /*@{*/ 01550 #define BP_AIPS_PACRB_TP6 (4U) /*!< Bit position for AIPS_PACRB_TP6. */ 01551 #define BM_AIPS_PACRB_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRB_TP6. */ 01552 #define BS_AIPS_PACRB_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP6. */ 01553 01554 /*! @brief Read current value of the AIPS_PACRB_TP6 field. */ 01555 #define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6)) 01556 01557 /*! @brief Format value for bitfield AIPS_PACRB_TP6. */ 01558 #define BF_AIPS_PACRB_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP6) & BM_AIPS_PACRB_TP6) 01559 01560 /*! @brief Set the TP6 field to a new value. */ 01561 #define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v)) 01562 /*@}*/ 01563 01564 /*! 01565 * @name Register AIPS_PACRB, field WP6[5] (RW) 01566 * 01567 * Determines whether the peripheral allows write accesses. When this field is 01568 * set and a write access is attempted, access terminates with an error response 01569 * and no peripheral access initiates. 01570 * 01571 * Values: 01572 * - 0 - This peripheral allows write accesses. 01573 * - 1 - This peripheral is write protected. 01574 */ 01575 /*@{*/ 01576 #define BP_AIPS_PACRB_WP6 (5U) /*!< Bit position for AIPS_PACRB_WP6. */ 01577 #define BM_AIPS_PACRB_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRB_WP6. */ 01578 #define BS_AIPS_PACRB_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP6. */ 01579 01580 /*! @brief Read current value of the AIPS_PACRB_WP6 field. */ 01581 #define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6)) 01582 01583 /*! @brief Format value for bitfield AIPS_PACRB_WP6. */ 01584 #define BF_AIPS_PACRB_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP6) & BM_AIPS_PACRB_WP6) 01585 01586 /*! @brief Set the WP6 field to a new value. */ 01587 #define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v)) 01588 /*@}*/ 01589 01590 /*! 01591 * @name Register AIPS_PACRB, field SP6[6] (RW) 01592 * 01593 * Determines whether the peripheral requires supervisor privilege level for 01594 * accesses. When this field is set, the master privilege level must indicate the 01595 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01596 * must be set. If not, access terminates with an error response and no peripheral 01597 * access initiates. 01598 * 01599 * Values: 01600 * - 0 - This peripheral does not require supervisor privilege level for 01601 * accesses. 01602 * - 1 - This peripheral requires supervisor privilege level for accesses. 01603 */ 01604 /*@{*/ 01605 #define BP_AIPS_PACRB_SP6 (6U) /*!< Bit position for AIPS_PACRB_SP6. */ 01606 #define BM_AIPS_PACRB_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRB_SP6. */ 01607 #define BS_AIPS_PACRB_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP6. */ 01608 01609 /*! @brief Read current value of the AIPS_PACRB_SP6 field. */ 01610 #define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6)) 01611 01612 /*! @brief Format value for bitfield AIPS_PACRB_SP6. */ 01613 #define BF_AIPS_PACRB_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP6) & BM_AIPS_PACRB_SP6) 01614 01615 /*! @brief Set the SP6 field to a new value. */ 01616 #define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v)) 01617 /*@}*/ 01618 01619 /*! 01620 * @name Register AIPS_PACRB, field TP5[8] (RW) 01621 * 01622 * Determines whether the peripheral allows accesses from an untrusted master. 01623 * When this field is set and an access is attempted by an untrusted master, the 01624 * access terminates with an error response and no peripheral access initiates. 01625 * 01626 * Values: 01627 * - 0 - Accesses from an untrusted master are allowed. 01628 * - 1 - Accesses from an untrusted master are not allowed. 01629 */ 01630 /*@{*/ 01631 #define BP_AIPS_PACRB_TP5 (8U) /*!< Bit position for AIPS_PACRB_TP5. */ 01632 #define BM_AIPS_PACRB_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRB_TP5. */ 01633 #define BS_AIPS_PACRB_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP5. */ 01634 01635 /*! @brief Read current value of the AIPS_PACRB_TP5 field. */ 01636 #define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5)) 01637 01638 /*! @brief Format value for bitfield AIPS_PACRB_TP5. */ 01639 #define BF_AIPS_PACRB_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP5) & BM_AIPS_PACRB_TP5) 01640 01641 /*! @brief Set the TP5 field to a new value. */ 01642 #define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v)) 01643 /*@}*/ 01644 01645 /*! 01646 * @name Register AIPS_PACRB, field WP5[9] (RW) 01647 * 01648 * Determines whether the peripheral allows write accesses. When this field is 01649 * set and a write access is attempted, access terminates with an error response 01650 * and no peripheral access initiates. 01651 * 01652 * Values: 01653 * - 0 - This peripheral allows write accesses. 01654 * - 1 - This peripheral is write protected. 01655 */ 01656 /*@{*/ 01657 #define BP_AIPS_PACRB_WP5 (9U) /*!< Bit position for AIPS_PACRB_WP5. */ 01658 #define BM_AIPS_PACRB_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRB_WP5. */ 01659 #define BS_AIPS_PACRB_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP5. */ 01660 01661 /*! @brief Read current value of the AIPS_PACRB_WP5 field. */ 01662 #define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5)) 01663 01664 /*! @brief Format value for bitfield AIPS_PACRB_WP5. */ 01665 #define BF_AIPS_PACRB_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP5) & BM_AIPS_PACRB_WP5) 01666 01667 /*! @brief Set the WP5 field to a new value. */ 01668 #define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v)) 01669 /*@}*/ 01670 01671 /*! 01672 * @name Register AIPS_PACRB, field SP5[10] (RW) 01673 * 01674 * Determines whether the peripheral requires supervisor privilege level for 01675 * accesses. When this field is set, the master privilege level must indicate the 01676 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01677 * must be set. If not, access terminates with an error response and no peripheral 01678 * access initiates. 01679 * 01680 * Values: 01681 * - 0 - This peripheral does not require supervisor privilege level for 01682 * accesses. 01683 * - 1 - This peripheral requires supervisor privilege level for accesses. 01684 */ 01685 /*@{*/ 01686 #define BP_AIPS_PACRB_SP5 (10U) /*!< Bit position for AIPS_PACRB_SP5. */ 01687 #define BM_AIPS_PACRB_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRB_SP5. */ 01688 #define BS_AIPS_PACRB_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP5. */ 01689 01690 /*! @brief Read current value of the AIPS_PACRB_SP5 field. */ 01691 #define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5)) 01692 01693 /*! @brief Format value for bitfield AIPS_PACRB_SP5. */ 01694 #define BF_AIPS_PACRB_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP5) & BM_AIPS_PACRB_SP5) 01695 01696 /*! @brief Set the SP5 field to a new value. */ 01697 #define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v)) 01698 /*@}*/ 01699 01700 /*! 01701 * @name Register AIPS_PACRB, field TP4[12] (RW) 01702 * 01703 * Determines whether the peripheral allows accesses from an untrusted master. 01704 * When this field is set and an access is attempted by an untrusted master, the 01705 * access terminates with an error response and no peripheral access initiates. 01706 * 01707 * Values: 01708 * - 0 - Accesses from an untrusted master are allowed. 01709 * - 1 - Accesses from an untrusted master are not allowed. 01710 */ 01711 /*@{*/ 01712 #define BP_AIPS_PACRB_TP4 (12U) /*!< Bit position for AIPS_PACRB_TP4. */ 01713 #define BM_AIPS_PACRB_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRB_TP4. */ 01714 #define BS_AIPS_PACRB_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP4. */ 01715 01716 /*! @brief Read current value of the AIPS_PACRB_TP4 field. */ 01717 #define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4)) 01718 01719 /*! @brief Format value for bitfield AIPS_PACRB_TP4. */ 01720 #define BF_AIPS_PACRB_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP4) & BM_AIPS_PACRB_TP4) 01721 01722 /*! @brief Set the TP4 field to a new value. */ 01723 #define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v)) 01724 /*@}*/ 01725 01726 /*! 01727 * @name Register AIPS_PACRB, field WP4[13] (RW) 01728 * 01729 * Determines whether the peripheral allows write accesss. When this bit is set 01730 * and a write access is attempted, access terminates with an error response and 01731 * no peripheral access initiates. 01732 * 01733 * Values: 01734 * - 0 - This peripheral allows write accesses. 01735 * - 1 - This peripheral is write protected. 01736 */ 01737 /*@{*/ 01738 #define BP_AIPS_PACRB_WP4 (13U) /*!< Bit position for AIPS_PACRB_WP4. */ 01739 #define BM_AIPS_PACRB_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRB_WP4. */ 01740 #define BS_AIPS_PACRB_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP4. */ 01741 01742 /*! @brief Read current value of the AIPS_PACRB_WP4 field. */ 01743 #define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4)) 01744 01745 /*! @brief Format value for bitfield AIPS_PACRB_WP4. */ 01746 #define BF_AIPS_PACRB_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP4) & BM_AIPS_PACRB_WP4) 01747 01748 /*! @brief Set the WP4 field to a new value. */ 01749 #define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v)) 01750 /*@}*/ 01751 01752 /*! 01753 * @name Register AIPS_PACRB, field SP4[14] (RW) 01754 * 01755 * Determines whether the peripheral requires supervisor privilege level for 01756 * accesses. When this field is set, the master privilege level must indicate the 01757 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01758 * must be set. If not, access terminates with an error response and no peripheral 01759 * access initiates. 01760 * 01761 * Values: 01762 * - 0 - This peripheral does not require supervisor privilege level for 01763 * accesses. 01764 * - 1 - This peripheral requires supervisor privilege level for accesses. 01765 */ 01766 /*@{*/ 01767 #define BP_AIPS_PACRB_SP4 (14U) /*!< Bit position for AIPS_PACRB_SP4. */ 01768 #define BM_AIPS_PACRB_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRB_SP4. */ 01769 #define BS_AIPS_PACRB_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP4. */ 01770 01771 /*! @brief Read current value of the AIPS_PACRB_SP4 field. */ 01772 #define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4)) 01773 01774 /*! @brief Format value for bitfield AIPS_PACRB_SP4. */ 01775 #define BF_AIPS_PACRB_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP4) & BM_AIPS_PACRB_SP4) 01776 01777 /*! @brief Set the SP4 field to a new value. */ 01778 #define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v)) 01779 /*@}*/ 01780 01781 /*! 01782 * @name Register AIPS_PACRB, field TP3[16] (RW) 01783 * 01784 * Determines whether the peripheral allows accesses from an untrusted master. 01785 * When this bit is set and an access is attempted by an untrusted master, the 01786 * access terminates with an error response and no peripheral access initiates. 01787 * 01788 * Values: 01789 * - 0 - Accesses from an untrusted master are allowed. 01790 * - 1 - Accesses from an untrusted master are not allowed. 01791 */ 01792 /*@{*/ 01793 #define BP_AIPS_PACRB_TP3 (16U) /*!< Bit position for AIPS_PACRB_TP3. */ 01794 #define BM_AIPS_PACRB_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRB_TP3. */ 01795 #define BS_AIPS_PACRB_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP3. */ 01796 01797 /*! @brief Read current value of the AIPS_PACRB_TP3 field. */ 01798 #define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3)) 01799 01800 /*! @brief Format value for bitfield AIPS_PACRB_TP3. */ 01801 #define BF_AIPS_PACRB_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP3) & BM_AIPS_PACRB_TP3) 01802 01803 /*! @brief Set the TP3 field to a new value. */ 01804 #define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v)) 01805 /*@}*/ 01806 01807 /*! 01808 * @name Register AIPS_PACRB, field WP3[17] (RW) 01809 * 01810 * Determines whether the peripheral allows write accesses. When this field is 01811 * set and a write access is attempted, access terminates with an error response 01812 * and no peripheral access initiates. 01813 * 01814 * Values: 01815 * - 0 - This peripheral allows write accesses. 01816 * - 1 - This peripheral is write protected. 01817 */ 01818 /*@{*/ 01819 #define BP_AIPS_PACRB_WP3 (17U) /*!< Bit position for AIPS_PACRB_WP3. */ 01820 #define BM_AIPS_PACRB_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRB_WP3. */ 01821 #define BS_AIPS_PACRB_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP3. */ 01822 01823 /*! @brief Read current value of the AIPS_PACRB_WP3 field. */ 01824 #define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3)) 01825 01826 /*! @brief Format value for bitfield AIPS_PACRB_WP3. */ 01827 #define BF_AIPS_PACRB_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP3) & BM_AIPS_PACRB_WP3) 01828 01829 /*! @brief Set the WP3 field to a new value. */ 01830 #define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v)) 01831 /*@}*/ 01832 01833 /*! 01834 * @name Register AIPS_PACRB, field SP3[18] (RW) 01835 * 01836 * Determines whether the peripheral requires supervisor privilege level for 01837 * access. When this bit is set, the master privilege level must indicate the 01838 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 01839 * set. If not, access terminates with an error response and no peripheral access 01840 * initiates. 01841 * 01842 * Values: 01843 * - 0 - This peripheral does not require supervisor privilege level for 01844 * accesses. 01845 * - 1 - This peripheral requires supervisor privilege level for accesses. 01846 */ 01847 /*@{*/ 01848 #define BP_AIPS_PACRB_SP3 (18U) /*!< Bit position for AIPS_PACRB_SP3. */ 01849 #define BM_AIPS_PACRB_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRB_SP3. */ 01850 #define BS_AIPS_PACRB_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP3. */ 01851 01852 /*! @brief Read current value of the AIPS_PACRB_SP3 field. */ 01853 #define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3)) 01854 01855 /*! @brief Format value for bitfield AIPS_PACRB_SP3. */ 01856 #define BF_AIPS_PACRB_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP3) & BM_AIPS_PACRB_SP3) 01857 01858 /*! @brief Set the SP3 field to a new value. */ 01859 #define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v)) 01860 /*@}*/ 01861 01862 /*! 01863 * @name Register AIPS_PACRB, field TP2[20] (RW) 01864 * 01865 * Determines whether the peripheral allows accesses from an untrusted master. 01866 * When this field is set and an access is attempted by an untrusted master, the 01867 * access terminates with an error response and no peripheral access initiates. 01868 * 01869 * Values: 01870 * - 0 - Accesses from an untrusted master are allowed. 01871 * - 1 - Accesses from an untrusted master are not allowed. 01872 */ 01873 /*@{*/ 01874 #define BP_AIPS_PACRB_TP2 (20U) /*!< Bit position for AIPS_PACRB_TP2. */ 01875 #define BM_AIPS_PACRB_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRB_TP2. */ 01876 #define BS_AIPS_PACRB_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP2. */ 01877 01878 /*! @brief Read current value of the AIPS_PACRB_TP2 field. */ 01879 #define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2)) 01880 01881 /*! @brief Format value for bitfield AIPS_PACRB_TP2. */ 01882 #define BF_AIPS_PACRB_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP2) & BM_AIPS_PACRB_TP2) 01883 01884 /*! @brief Set the TP2 field to a new value. */ 01885 #define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v)) 01886 /*@}*/ 01887 01888 /*! 01889 * @name Register AIPS_PACRB, field WP2[21] (RW) 01890 * 01891 * Determines whether the peripheral allows write accesss. When this bit is set 01892 * and a write access is attempted, access terminates with an error response and 01893 * no peripheral access initiates. 01894 * 01895 * Values: 01896 * - 0 - This peripheral allows write accesses. 01897 * - 1 - This peripheral is write protected. 01898 */ 01899 /*@{*/ 01900 #define BP_AIPS_PACRB_WP2 (21U) /*!< Bit position for AIPS_PACRB_WP2. */ 01901 #define BM_AIPS_PACRB_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRB_WP2. */ 01902 #define BS_AIPS_PACRB_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP2. */ 01903 01904 /*! @brief Read current value of the AIPS_PACRB_WP2 field. */ 01905 #define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2)) 01906 01907 /*! @brief Format value for bitfield AIPS_PACRB_WP2. */ 01908 #define BF_AIPS_PACRB_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP2) & BM_AIPS_PACRB_WP2) 01909 01910 /*! @brief Set the WP2 field to a new value. */ 01911 #define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v)) 01912 /*@}*/ 01913 01914 /*! 01915 * @name Register AIPS_PACRB, field SP2[22] (RW) 01916 * 01917 * Determines whether the peripheral requires supervisor privilege level for 01918 * accesses. When this field is set, the master privilege level must indicate the 01919 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01920 * must be set. If not, access terminates with an error response and no peripheral 01921 * access initiates. 01922 * 01923 * Values: 01924 * - 0 - This peripheral does not require supervisor privilege level for 01925 * accesses. 01926 * - 1 - This peripheral requires supervisor privilege level for accesses. 01927 */ 01928 /*@{*/ 01929 #define BP_AIPS_PACRB_SP2 (22U) /*!< Bit position for AIPS_PACRB_SP2. */ 01930 #define BM_AIPS_PACRB_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRB_SP2. */ 01931 #define BS_AIPS_PACRB_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP2. */ 01932 01933 /*! @brief Read current value of the AIPS_PACRB_SP2 field. */ 01934 #define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2)) 01935 01936 /*! @brief Format value for bitfield AIPS_PACRB_SP2. */ 01937 #define BF_AIPS_PACRB_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP2) & BM_AIPS_PACRB_SP2) 01938 01939 /*! @brief Set the SP2 field to a new value. */ 01940 #define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v)) 01941 /*@}*/ 01942 01943 /*! 01944 * @name Register AIPS_PACRB, field TP1[24] (RW) 01945 * 01946 * Determines whether the peripheral allows accesses from an untrusted master. 01947 * When this bit is set and an access is attempted by an untrusted master, the 01948 * access terminates with an error response and no peripheral access initiates. 01949 * 01950 * Values: 01951 * - 0 - Accesses from an untrusted master are allowed. 01952 * - 1 - Accesses from an untrusted master are not allowed. 01953 */ 01954 /*@{*/ 01955 #define BP_AIPS_PACRB_TP1 (24U) /*!< Bit position for AIPS_PACRB_TP1. */ 01956 #define BM_AIPS_PACRB_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRB_TP1. */ 01957 #define BS_AIPS_PACRB_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP1. */ 01958 01959 /*! @brief Read current value of the AIPS_PACRB_TP1 field. */ 01960 #define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1)) 01961 01962 /*! @brief Format value for bitfield AIPS_PACRB_TP1. */ 01963 #define BF_AIPS_PACRB_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP1) & BM_AIPS_PACRB_TP1) 01964 01965 /*! @brief Set the TP1 field to a new value. */ 01966 #define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v)) 01967 /*@}*/ 01968 01969 /*! 01970 * @name Register AIPS_PACRB, field WP1[25] (RW) 01971 * 01972 * Determines whether the peripheral allows write accesses. When this field is 01973 * set and a write access is attempted, access terminates with an error response 01974 * and no peripheral access initiates. 01975 * 01976 * Values: 01977 * - 0 - This peripheral allows write accesses. 01978 * - 1 - This peripheral is write protected. 01979 */ 01980 /*@{*/ 01981 #define BP_AIPS_PACRB_WP1 (25U) /*!< Bit position for AIPS_PACRB_WP1. */ 01982 #define BM_AIPS_PACRB_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRB_WP1. */ 01983 #define BS_AIPS_PACRB_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP1. */ 01984 01985 /*! @brief Read current value of the AIPS_PACRB_WP1 field. */ 01986 #define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1)) 01987 01988 /*! @brief Format value for bitfield AIPS_PACRB_WP1. */ 01989 #define BF_AIPS_PACRB_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP1) & BM_AIPS_PACRB_WP1) 01990 01991 /*! @brief Set the WP1 field to a new value. */ 01992 #define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v)) 01993 /*@}*/ 01994 01995 /*! 01996 * @name Register AIPS_PACRB, field SP1[26] (RW) 01997 * 01998 * Determines whether the peripheral requires supervisor privilege level for 01999 * accesses. When this field is set, the master privilege level must indicate the 02000 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02001 * must be set. If not, access terminates with an error response and no peripheral 02002 * access initiates. 02003 * 02004 * Values: 02005 * - 0 - This peripheral does not require supervisor privilege level for 02006 * accesses. 02007 * - 1 - This peripheral requires supervisor privilege level for accesses. 02008 */ 02009 /*@{*/ 02010 #define BP_AIPS_PACRB_SP1 (26U) /*!< Bit position for AIPS_PACRB_SP1. */ 02011 #define BM_AIPS_PACRB_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRB_SP1. */ 02012 #define BS_AIPS_PACRB_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP1. */ 02013 02014 /*! @brief Read current value of the AIPS_PACRB_SP1 field. */ 02015 #define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1)) 02016 02017 /*! @brief Format value for bitfield AIPS_PACRB_SP1. */ 02018 #define BF_AIPS_PACRB_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP1) & BM_AIPS_PACRB_SP1) 02019 02020 /*! @brief Set the SP1 field to a new value. */ 02021 #define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v)) 02022 /*@}*/ 02023 02024 /*! 02025 * @name Register AIPS_PACRB, field TP0[28] (RW) 02026 * 02027 * Determines whether the peripheral allows accesses from an untrusted master. 02028 * When this field is set and an access is attempted by an untrusted master, the 02029 * access terminates with an error response and no peripheral access initiates. 02030 * 02031 * Values: 02032 * - 0 - Accesses from an untrusted master are allowed. 02033 * - 1 - Accesses from an untrusted master are not allowed. 02034 */ 02035 /*@{*/ 02036 #define BP_AIPS_PACRB_TP0 (28U) /*!< Bit position for AIPS_PACRB_TP0. */ 02037 #define BM_AIPS_PACRB_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRB_TP0. */ 02038 #define BS_AIPS_PACRB_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP0. */ 02039 02040 /*! @brief Read current value of the AIPS_PACRB_TP0 field. */ 02041 #define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0)) 02042 02043 /*! @brief Format value for bitfield AIPS_PACRB_TP0. */ 02044 #define BF_AIPS_PACRB_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP0) & BM_AIPS_PACRB_TP0) 02045 02046 /*! @brief Set the TP0 field to a new value. */ 02047 #define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v)) 02048 /*@}*/ 02049 02050 /*! 02051 * @name Register AIPS_PACRB, field WP0[29] (RW) 02052 * 02053 * Determines whether the peripheral allows write accesss. When this bit is set 02054 * and a write access is attempted, access terminates with an error response and 02055 * no peripheral access initiates. 02056 * 02057 * Values: 02058 * - 0 - This peripheral allows write accesses. 02059 * - 1 - This peripheral is write protected. 02060 */ 02061 /*@{*/ 02062 #define BP_AIPS_PACRB_WP0 (29U) /*!< Bit position for AIPS_PACRB_WP0. */ 02063 #define BM_AIPS_PACRB_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRB_WP0. */ 02064 #define BS_AIPS_PACRB_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP0. */ 02065 02066 /*! @brief Read current value of the AIPS_PACRB_WP0 field. */ 02067 #define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0)) 02068 02069 /*! @brief Format value for bitfield AIPS_PACRB_WP0. */ 02070 #define BF_AIPS_PACRB_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP0) & BM_AIPS_PACRB_WP0) 02071 02072 /*! @brief Set the WP0 field to a new value. */ 02073 #define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v)) 02074 /*@}*/ 02075 02076 /*! 02077 * @name Register AIPS_PACRB, field SP0[30] (RW) 02078 * 02079 * Determines whether the peripheral requires supervisor privilege level for 02080 * accesses. When this field is set, the master privilege level must indicate the 02081 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02082 * must be set. If not, access terminates with an error response and no peripheral 02083 * access initiates. 02084 * 02085 * Values: 02086 * - 0 - This peripheral does not require supervisor privilege level for 02087 * accesses. 02088 * - 1 - This peripheral requires supervisor privilege level for accesses. 02089 */ 02090 /*@{*/ 02091 #define BP_AIPS_PACRB_SP0 (30U) /*!< Bit position for AIPS_PACRB_SP0. */ 02092 #define BM_AIPS_PACRB_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRB_SP0. */ 02093 #define BS_AIPS_PACRB_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP0. */ 02094 02095 /*! @brief Read current value of the AIPS_PACRB_SP0 field. */ 02096 #define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0)) 02097 02098 /*! @brief Format value for bitfield AIPS_PACRB_SP0. */ 02099 #define BF_AIPS_PACRB_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP0) & BM_AIPS_PACRB_SP0) 02100 02101 /*! @brief Set the SP0 field to a new value. */ 02102 #define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v)) 02103 /*@}*/ 02104 02105 /******************************************************************************* 02106 * HW_AIPS_PACRC - Peripheral Access Control Register 02107 ******************************************************************************/ 02108 02109 /*! 02110 * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) 02111 * 02112 * Reset value: 0x00000000U 02113 * 02114 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 02115 * defines the access levels for a particular peripheral. The mapping between a 02116 * peripheral and its PACR field is shown in the table below. The peripheral assignment 02117 * to each PACR is defined by the memory map slot that the peripheral is 02118 * assigned to. See this chip's memory map for the assignment of a particular 02119 * peripheral. The following table shows the location of each peripheral slot's PACR field 02120 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 02121 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 02122 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 02123 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 02124 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 02125 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 02126 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 02127 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 02128 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 02129 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 02130 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 02131 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 02132 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 02133 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 02134 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 02135 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 02136 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 02137 * A-D, which control peripheral slots 0-31, are shown below. The following 02138 * section, PACRPeripheral Access Control Register , shows the register field 02139 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 02140 * sections because they occupy two non-contiguous address spaces. 02141 */ 02142 typedef union _hw_aips_pacrc 02143 { 02144 uint32_t U; 02145 struct _hw_aips_pacrc_bitfields 02146 { 02147 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 02148 uint32_t WP7 : 1; /*!< [1] Write Protect */ 02149 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 02150 uint32_t RESERVED0 : 1; /*!< [3] */ 02151 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 02152 uint32_t WP6 : 1; /*!< [5] Write Protect */ 02153 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 02154 uint32_t RESERVED1 : 1; /*!< [7] */ 02155 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 02156 uint32_t WP5 : 1; /*!< [9] Write Protect */ 02157 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 02158 uint32_t RESERVED2 : 1; /*!< [11] */ 02159 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 02160 uint32_t WP4 : 1; /*!< [13] Write Protect */ 02161 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 02162 uint32_t RESERVED3 : 1; /*!< [15] */ 02163 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 02164 uint32_t WP3 : 1; /*!< [17] Write Protect */ 02165 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 02166 uint32_t RESERVED4 : 1; /*!< [19] */ 02167 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 02168 uint32_t WP2 : 1; /*!< [21] Write Protect */ 02169 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 02170 uint32_t RESERVED5 : 1; /*!< [23] */ 02171 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 02172 uint32_t WP1 : 1; /*!< [25] Write Protect */ 02173 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 02174 uint32_t RESERVED6 : 1; /*!< [27] */ 02175 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 02176 uint32_t WP0 : 1; /*!< [29] Write Protect */ 02177 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 02178 uint32_t RESERVED7 : 1; /*!< [31] */ 02179 } B; 02180 } hw_aips_pacrc_t; 02181 02182 /*! 02183 * @name Constants and macros for entire AIPS_PACRC register 02184 */ 02185 /*@{*/ 02186 #define HW_AIPS_PACRC_ADDR(x) ((x) + 0x28U) 02187 02188 #define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) 02189 #define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U) 02190 #define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v)) 02191 #define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) 02192 #define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) 02193 #define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) 02194 /*@}*/ 02195 02196 /* 02197 * Constants & macros for individual AIPS_PACRC bitfields 02198 */ 02199 02200 /*! 02201 * @name Register AIPS_PACRC, field TP7[0] (RW) 02202 * 02203 * Determines whether the peripheral allows accesses from an untrusted master. 02204 * When this field is set and an access is attempted by an untrusted master, the 02205 * access terminates with an error response and no peripheral access initiates. 02206 * 02207 * Values: 02208 * - 0 - Accesses from an untrusted master are allowed. 02209 * - 1 - Accesses from an untrusted master are not allowed. 02210 */ 02211 /*@{*/ 02212 #define BP_AIPS_PACRC_TP7 (0U) /*!< Bit position for AIPS_PACRC_TP7. */ 02213 #define BM_AIPS_PACRC_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRC_TP7. */ 02214 #define BS_AIPS_PACRC_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP7. */ 02215 02216 /*! @brief Read current value of the AIPS_PACRC_TP7 field. */ 02217 #define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7)) 02218 02219 /*! @brief Format value for bitfield AIPS_PACRC_TP7. */ 02220 #define BF_AIPS_PACRC_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP7) & BM_AIPS_PACRC_TP7) 02221 02222 /*! @brief Set the TP7 field to a new value. */ 02223 #define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v)) 02224 /*@}*/ 02225 02226 /*! 02227 * @name Register AIPS_PACRC, field WP7[1] (RW) 02228 * 02229 * Determines whether the peripheral allows write accesses. When this field is 02230 * set and a write access is attempted, access terminates with an error response 02231 * and no peripheral access initiates. 02232 * 02233 * Values: 02234 * - 0 - This peripheral allows write accesses. 02235 * - 1 - This peripheral is write protected. 02236 */ 02237 /*@{*/ 02238 #define BP_AIPS_PACRC_WP7 (1U) /*!< Bit position for AIPS_PACRC_WP7. */ 02239 #define BM_AIPS_PACRC_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRC_WP7. */ 02240 #define BS_AIPS_PACRC_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP7. */ 02241 02242 /*! @brief Read current value of the AIPS_PACRC_WP7 field. */ 02243 #define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7)) 02244 02245 /*! @brief Format value for bitfield AIPS_PACRC_WP7. */ 02246 #define BF_AIPS_PACRC_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP7) & BM_AIPS_PACRC_WP7) 02247 02248 /*! @brief Set the WP7 field to a new value. */ 02249 #define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v)) 02250 /*@}*/ 02251 02252 /*! 02253 * @name Register AIPS_PACRC, field SP7[2] (RW) 02254 * 02255 * Determines whether the peripheral requires supervisor privilege level for 02256 * accesses. When this field is set, the master privilege level must indicate the 02257 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02258 * must be set. If not, access terminates with an error response and no peripheral 02259 * access initiates. 02260 * 02261 * Values: 02262 * - 0 - This peripheral does not require supervisor privilege level for 02263 * accesses. 02264 * - 1 - This peripheral requires supervisor privilege level for accesses. 02265 */ 02266 /*@{*/ 02267 #define BP_AIPS_PACRC_SP7 (2U) /*!< Bit position for AIPS_PACRC_SP7. */ 02268 #define BM_AIPS_PACRC_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRC_SP7. */ 02269 #define BS_AIPS_PACRC_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP7. */ 02270 02271 /*! @brief Read current value of the AIPS_PACRC_SP7 field. */ 02272 #define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7)) 02273 02274 /*! @brief Format value for bitfield AIPS_PACRC_SP7. */ 02275 #define BF_AIPS_PACRC_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP7) & BM_AIPS_PACRC_SP7) 02276 02277 /*! @brief Set the SP7 field to a new value. */ 02278 #define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v)) 02279 /*@}*/ 02280 02281 /*! 02282 * @name Register AIPS_PACRC, field TP6[4] (RW) 02283 * 02284 * Determines whether the peripheral allows accesses from an untrusted master. 02285 * When this field is set and an access is attempted by an untrusted master, the 02286 * access terminates with an error response and no peripheral access initiates. 02287 * 02288 * Values: 02289 * - 0 - Accesses from an untrusted master are allowed. 02290 * - 1 - Accesses from an untrusted master are not allowed. 02291 */ 02292 /*@{*/ 02293 #define BP_AIPS_PACRC_TP6 (4U) /*!< Bit position for AIPS_PACRC_TP6. */ 02294 #define BM_AIPS_PACRC_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRC_TP6. */ 02295 #define BS_AIPS_PACRC_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP6. */ 02296 02297 /*! @brief Read current value of the AIPS_PACRC_TP6 field. */ 02298 #define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6)) 02299 02300 /*! @brief Format value for bitfield AIPS_PACRC_TP6. */ 02301 #define BF_AIPS_PACRC_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP6) & BM_AIPS_PACRC_TP6) 02302 02303 /*! @brief Set the TP6 field to a new value. */ 02304 #define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v)) 02305 /*@}*/ 02306 02307 /*! 02308 * @name Register AIPS_PACRC, field WP6[5] (RW) 02309 * 02310 * Determines whether the peripheral allows write accesses. When this field is 02311 * set and a write access is attempted, access terminates with an error response 02312 * and no peripheral access initiates. 02313 * 02314 * Values: 02315 * - 0 - This peripheral allows write accesses. 02316 * - 1 - This peripheral is write protected. 02317 */ 02318 /*@{*/ 02319 #define BP_AIPS_PACRC_WP6 (5U) /*!< Bit position for AIPS_PACRC_WP6. */ 02320 #define BM_AIPS_PACRC_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRC_WP6. */ 02321 #define BS_AIPS_PACRC_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP6. */ 02322 02323 /*! @brief Read current value of the AIPS_PACRC_WP6 field. */ 02324 #define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6)) 02325 02326 /*! @brief Format value for bitfield AIPS_PACRC_WP6. */ 02327 #define BF_AIPS_PACRC_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP6) & BM_AIPS_PACRC_WP6) 02328 02329 /*! @brief Set the WP6 field to a new value. */ 02330 #define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v)) 02331 /*@}*/ 02332 02333 /*! 02334 * @name Register AIPS_PACRC, field SP6[6] (RW) 02335 * 02336 * Determines whether the peripheral requires supervisor privilege level for 02337 * accesses. When this field is set, the master privilege level must indicate the 02338 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02339 * must be set. If not, access terminates with an error response and no peripheral 02340 * access initiates. 02341 * 02342 * Values: 02343 * - 0 - This peripheral does not require supervisor privilege level for 02344 * accesses. 02345 * - 1 - This peripheral requires supervisor privilege level for accesses. 02346 */ 02347 /*@{*/ 02348 #define BP_AIPS_PACRC_SP6 (6U) /*!< Bit position for AIPS_PACRC_SP6. */ 02349 #define BM_AIPS_PACRC_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRC_SP6. */ 02350 #define BS_AIPS_PACRC_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP6. */ 02351 02352 /*! @brief Read current value of the AIPS_PACRC_SP6 field. */ 02353 #define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6)) 02354 02355 /*! @brief Format value for bitfield AIPS_PACRC_SP6. */ 02356 #define BF_AIPS_PACRC_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP6) & BM_AIPS_PACRC_SP6) 02357 02358 /*! @brief Set the SP6 field to a new value. */ 02359 #define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v)) 02360 /*@}*/ 02361 02362 /*! 02363 * @name Register AIPS_PACRC, field TP5[8] (RW) 02364 * 02365 * Determines whether the peripheral allows accesses from an untrusted master. 02366 * When this field is set and an access is attempted by an untrusted master, the 02367 * access terminates with an error response and no peripheral access initiates. 02368 * 02369 * Values: 02370 * - 0 - Accesses from an untrusted master are allowed. 02371 * - 1 - Accesses from an untrusted master are not allowed. 02372 */ 02373 /*@{*/ 02374 #define BP_AIPS_PACRC_TP5 (8U) /*!< Bit position for AIPS_PACRC_TP5. */ 02375 #define BM_AIPS_PACRC_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRC_TP5. */ 02376 #define BS_AIPS_PACRC_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP5. */ 02377 02378 /*! @brief Read current value of the AIPS_PACRC_TP5 field. */ 02379 #define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5)) 02380 02381 /*! @brief Format value for bitfield AIPS_PACRC_TP5. */ 02382 #define BF_AIPS_PACRC_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP5) & BM_AIPS_PACRC_TP5) 02383 02384 /*! @brief Set the TP5 field to a new value. */ 02385 #define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v)) 02386 /*@}*/ 02387 02388 /*! 02389 * @name Register AIPS_PACRC, field WP5[9] (RW) 02390 * 02391 * Determines whether the peripheral allows write accesses. When this field is 02392 * set and a write access is attempted, access terminates with an error response 02393 * and no peripheral access initiates. 02394 * 02395 * Values: 02396 * - 0 - This peripheral allows write accesses. 02397 * - 1 - This peripheral is write protected. 02398 */ 02399 /*@{*/ 02400 #define BP_AIPS_PACRC_WP5 (9U) /*!< Bit position for AIPS_PACRC_WP5. */ 02401 #define BM_AIPS_PACRC_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRC_WP5. */ 02402 #define BS_AIPS_PACRC_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP5. */ 02403 02404 /*! @brief Read current value of the AIPS_PACRC_WP5 field. */ 02405 #define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5)) 02406 02407 /*! @brief Format value for bitfield AIPS_PACRC_WP5. */ 02408 #define BF_AIPS_PACRC_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP5) & BM_AIPS_PACRC_WP5) 02409 02410 /*! @brief Set the WP5 field to a new value. */ 02411 #define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v)) 02412 /*@}*/ 02413 02414 /*! 02415 * @name Register AIPS_PACRC, field SP5[10] (RW) 02416 * 02417 * Determines whether the peripheral requires supervisor privilege level for 02418 * accesses. When this field is set, the master privilege level must indicate the 02419 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02420 * must be set. If not, access terminates with an error response and no peripheral 02421 * access initiates. 02422 * 02423 * Values: 02424 * - 0 - This peripheral does not require supervisor privilege level for 02425 * accesses. 02426 * - 1 - This peripheral requires supervisor privilege level for accesses. 02427 */ 02428 /*@{*/ 02429 #define BP_AIPS_PACRC_SP5 (10U) /*!< Bit position for AIPS_PACRC_SP5. */ 02430 #define BM_AIPS_PACRC_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRC_SP5. */ 02431 #define BS_AIPS_PACRC_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP5. */ 02432 02433 /*! @brief Read current value of the AIPS_PACRC_SP5 field. */ 02434 #define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5)) 02435 02436 /*! @brief Format value for bitfield AIPS_PACRC_SP5. */ 02437 #define BF_AIPS_PACRC_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP5) & BM_AIPS_PACRC_SP5) 02438 02439 /*! @brief Set the SP5 field to a new value. */ 02440 #define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v)) 02441 /*@}*/ 02442 02443 /*! 02444 * @name Register AIPS_PACRC, field TP4[12] (RW) 02445 * 02446 * Determines whether the peripheral allows accesses from an untrusted master. 02447 * When this field is set and an access is attempted by an untrusted master, the 02448 * access terminates with an error response and no peripheral access initiates. 02449 * 02450 * Values: 02451 * - 0 - Accesses from an untrusted master are allowed. 02452 * - 1 - Accesses from an untrusted master are not allowed. 02453 */ 02454 /*@{*/ 02455 #define BP_AIPS_PACRC_TP4 (12U) /*!< Bit position for AIPS_PACRC_TP4. */ 02456 #define BM_AIPS_PACRC_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRC_TP4. */ 02457 #define BS_AIPS_PACRC_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP4. */ 02458 02459 /*! @brief Read current value of the AIPS_PACRC_TP4 field. */ 02460 #define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4)) 02461 02462 /*! @brief Format value for bitfield AIPS_PACRC_TP4. */ 02463 #define BF_AIPS_PACRC_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP4) & BM_AIPS_PACRC_TP4) 02464 02465 /*! @brief Set the TP4 field to a new value. */ 02466 #define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v)) 02467 /*@}*/ 02468 02469 /*! 02470 * @name Register AIPS_PACRC, field WP4[13] (RW) 02471 * 02472 * Determines whether the peripheral allows write accesss. When this bit is set 02473 * and a write access is attempted, access terminates with an error response and 02474 * no peripheral access initiates. 02475 * 02476 * Values: 02477 * - 0 - This peripheral allows write accesses. 02478 * - 1 - This peripheral is write protected. 02479 */ 02480 /*@{*/ 02481 #define BP_AIPS_PACRC_WP4 (13U) /*!< Bit position for AIPS_PACRC_WP4. */ 02482 #define BM_AIPS_PACRC_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRC_WP4. */ 02483 #define BS_AIPS_PACRC_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP4. */ 02484 02485 /*! @brief Read current value of the AIPS_PACRC_WP4 field. */ 02486 #define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4)) 02487 02488 /*! @brief Format value for bitfield AIPS_PACRC_WP4. */ 02489 #define BF_AIPS_PACRC_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP4) & BM_AIPS_PACRC_WP4) 02490 02491 /*! @brief Set the WP4 field to a new value. */ 02492 #define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v)) 02493 /*@}*/ 02494 02495 /*! 02496 * @name Register AIPS_PACRC, field SP4[14] (RW) 02497 * 02498 * Determines whether the peripheral requires supervisor privilege level for 02499 * accesses. When this field is set, the master privilege level must indicate the 02500 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02501 * must be set. If not, access terminates with an error response and no peripheral 02502 * access initiates. 02503 * 02504 * Values: 02505 * - 0 - This peripheral does not require supervisor privilege level for 02506 * accesses. 02507 * - 1 - This peripheral requires supervisor privilege level for accesses. 02508 */ 02509 /*@{*/ 02510 #define BP_AIPS_PACRC_SP4 (14U) /*!< Bit position for AIPS_PACRC_SP4. */ 02511 #define BM_AIPS_PACRC_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRC_SP4. */ 02512 #define BS_AIPS_PACRC_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP4. */ 02513 02514 /*! @brief Read current value of the AIPS_PACRC_SP4 field. */ 02515 #define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4)) 02516 02517 /*! @brief Format value for bitfield AIPS_PACRC_SP4. */ 02518 #define BF_AIPS_PACRC_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP4) & BM_AIPS_PACRC_SP4) 02519 02520 /*! @brief Set the SP4 field to a new value. */ 02521 #define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v)) 02522 /*@}*/ 02523 02524 /*! 02525 * @name Register AIPS_PACRC, field TP3[16] (RW) 02526 * 02527 * Determines whether the peripheral allows accesses from an untrusted master. 02528 * When this bit is set and an access is attempted by an untrusted master, the 02529 * access terminates with an error response and no peripheral access initiates. 02530 * 02531 * Values: 02532 * - 0 - Accesses from an untrusted master are allowed. 02533 * - 1 - Accesses from an untrusted master are not allowed. 02534 */ 02535 /*@{*/ 02536 #define BP_AIPS_PACRC_TP3 (16U) /*!< Bit position for AIPS_PACRC_TP3. */ 02537 #define BM_AIPS_PACRC_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRC_TP3. */ 02538 #define BS_AIPS_PACRC_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP3. */ 02539 02540 /*! @brief Read current value of the AIPS_PACRC_TP3 field. */ 02541 #define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3)) 02542 02543 /*! @brief Format value for bitfield AIPS_PACRC_TP3. */ 02544 #define BF_AIPS_PACRC_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP3) & BM_AIPS_PACRC_TP3) 02545 02546 /*! @brief Set the TP3 field to a new value. */ 02547 #define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v)) 02548 /*@}*/ 02549 02550 /*! 02551 * @name Register AIPS_PACRC, field WP3[17] (RW) 02552 * 02553 * Determines whether the peripheral allows write accesses. When this field is 02554 * set and a write access is attempted, access terminates with an error response 02555 * and no peripheral access initiates. 02556 * 02557 * Values: 02558 * - 0 - This peripheral allows write accesses. 02559 * - 1 - This peripheral is write protected. 02560 */ 02561 /*@{*/ 02562 #define BP_AIPS_PACRC_WP3 (17U) /*!< Bit position for AIPS_PACRC_WP3. */ 02563 #define BM_AIPS_PACRC_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRC_WP3. */ 02564 #define BS_AIPS_PACRC_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP3. */ 02565 02566 /*! @brief Read current value of the AIPS_PACRC_WP3 field. */ 02567 #define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3)) 02568 02569 /*! @brief Format value for bitfield AIPS_PACRC_WP3. */ 02570 #define BF_AIPS_PACRC_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP3) & BM_AIPS_PACRC_WP3) 02571 02572 /*! @brief Set the WP3 field to a new value. */ 02573 #define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v)) 02574 /*@}*/ 02575 02576 /*! 02577 * @name Register AIPS_PACRC, field SP3[18] (RW) 02578 * 02579 * Determines whether the peripheral requires supervisor privilege level for 02580 * access. When this bit is set, the master privilege level must indicate the 02581 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 02582 * set. If not, access terminates with an error response and no peripheral access 02583 * initiates. 02584 * 02585 * Values: 02586 * - 0 - This peripheral does not require supervisor privilege level for 02587 * accesses. 02588 * - 1 - This peripheral requires supervisor privilege level for accesses. 02589 */ 02590 /*@{*/ 02591 #define BP_AIPS_PACRC_SP3 (18U) /*!< Bit position for AIPS_PACRC_SP3. */ 02592 #define BM_AIPS_PACRC_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRC_SP3. */ 02593 #define BS_AIPS_PACRC_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP3. */ 02594 02595 /*! @brief Read current value of the AIPS_PACRC_SP3 field. */ 02596 #define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3)) 02597 02598 /*! @brief Format value for bitfield AIPS_PACRC_SP3. */ 02599 #define BF_AIPS_PACRC_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP3) & BM_AIPS_PACRC_SP3) 02600 02601 /*! @brief Set the SP3 field to a new value. */ 02602 #define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v)) 02603 /*@}*/ 02604 02605 /*! 02606 * @name Register AIPS_PACRC, field TP2[20] (RW) 02607 * 02608 * Determines whether the peripheral allows accesses from an untrusted master. 02609 * When this field is set and an access is attempted by an untrusted master, the 02610 * access terminates with an error response and no peripheral access initiates. 02611 * 02612 * Values: 02613 * - 0 - Accesses from an untrusted master are allowed. 02614 * - 1 - Accesses from an untrusted master are not allowed. 02615 */ 02616 /*@{*/ 02617 #define BP_AIPS_PACRC_TP2 (20U) /*!< Bit position for AIPS_PACRC_TP2. */ 02618 #define BM_AIPS_PACRC_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRC_TP2. */ 02619 #define BS_AIPS_PACRC_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP2. */ 02620 02621 /*! @brief Read current value of the AIPS_PACRC_TP2 field. */ 02622 #define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2)) 02623 02624 /*! @brief Format value for bitfield AIPS_PACRC_TP2. */ 02625 #define BF_AIPS_PACRC_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP2) & BM_AIPS_PACRC_TP2) 02626 02627 /*! @brief Set the TP2 field to a new value. */ 02628 #define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v)) 02629 /*@}*/ 02630 02631 /*! 02632 * @name Register AIPS_PACRC, field WP2[21] (RW) 02633 * 02634 * Determines whether the peripheral allows write accesss. When this bit is set 02635 * and a write access is attempted, access terminates with an error response and 02636 * no peripheral access initiates. 02637 * 02638 * Values: 02639 * - 0 - This peripheral allows write accesses. 02640 * - 1 - This peripheral is write protected. 02641 */ 02642 /*@{*/ 02643 #define BP_AIPS_PACRC_WP2 (21U) /*!< Bit position for AIPS_PACRC_WP2. */ 02644 #define BM_AIPS_PACRC_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRC_WP2. */ 02645 #define BS_AIPS_PACRC_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP2. */ 02646 02647 /*! @brief Read current value of the AIPS_PACRC_WP2 field. */ 02648 #define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2)) 02649 02650 /*! @brief Format value for bitfield AIPS_PACRC_WP2. */ 02651 #define BF_AIPS_PACRC_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP2) & BM_AIPS_PACRC_WP2) 02652 02653 /*! @brief Set the WP2 field to a new value. */ 02654 #define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v)) 02655 /*@}*/ 02656 02657 /*! 02658 * @name Register AIPS_PACRC, field SP2[22] (RW) 02659 * 02660 * Determines whether the peripheral requires supervisor privilege level for 02661 * accesses. When this field is set, the master privilege level must indicate the 02662 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02663 * must be set. If not, access terminates with an error response and no peripheral 02664 * access initiates. 02665 * 02666 * Values: 02667 * - 0 - This peripheral does not require supervisor privilege level for 02668 * accesses. 02669 * - 1 - This peripheral requires supervisor privilege level for accesses. 02670 */ 02671 /*@{*/ 02672 #define BP_AIPS_PACRC_SP2 (22U) /*!< Bit position for AIPS_PACRC_SP2. */ 02673 #define BM_AIPS_PACRC_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRC_SP2. */ 02674 #define BS_AIPS_PACRC_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP2. */ 02675 02676 /*! @brief Read current value of the AIPS_PACRC_SP2 field. */ 02677 #define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2)) 02678 02679 /*! @brief Format value for bitfield AIPS_PACRC_SP2. */ 02680 #define BF_AIPS_PACRC_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP2) & BM_AIPS_PACRC_SP2) 02681 02682 /*! @brief Set the SP2 field to a new value. */ 02683 #define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v)) 02684 /*@}*/ 02685 02686 /*! 02687 * @name Register AIPS_PACRC, field TP1[24] (RW) 02688 * 02689 * Determines whether the peripheral allows accesses from an untrusted master. 02690 * When this bit is set and an access is attempted by an untrusted master, the 02691 * access terminates with an error response and no peripheral access initiates. 02692 * 02693 * Values: 02694 * - 0 - Accesses from an untrusted master are allowed. 02695 * - 1 - Accesses from an untrusted master are not allowed. 02696 */ 02697 /*@{*/ 02698 #define BP_AIPS_PACRC_TP1 (24U) /*!< Bit position for AIPS_PACRC_TP1. */ 02699 #define BM_AIPS_PACRC_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRC_TP1. */ 02700 #define BS_AIPS_PACRC_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP1. */ 02701 02702 /*! @brief Read current value of the AIPS_PACRC_TP1 field. */ 02703 #define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1)) 02704 02705 /*! @brief Format value for bitfield AIPS_PACRC_TP1. */ 02706 #define BF_AIPS_PACRC_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP1) & BM_AIPS_PACRC_TP1) 02707 02708 /*! @brief Set the TP1 field to a new value. */ 02709 #define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v)) 02710 /*@}*/ 02711 02712 /*! 02713 * @name Register AIPS_PACRC, field WP1[25] (RW) 02714 * 02715 * Determines whether the peripheral allows write accesses. When this field is 02716 * set and a write access is attempted, access terminates with an error response 02717 * and no peripheral access initiates. 02718 * 02719 * Values: 02720 * - 0 - This peripheral allows write accesses. 02721 * - 1 - This peripheral is write protected. 02722 */ 02723 /*@{*/ 02724 #define BP_AIPS_PACRC_WP1 (25U) /*!< Bit position for AIPS_PACRC_WP1. */ 02725 #define BM_AIPS_PACRC_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRC_WP1. */ 02726 #define BS_AIPS_PACRC_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP1. */ 02727 02728 /*! @brief Read current value of the AIPS_PACRC_WP1 field. */ 02729 #define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1)) 02730 02731 /*! @brief Format value for bitfield AIPS_PACRC_WP1. */ 02732 #define BF_AIPS_PACRC_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP1) & BM_AIPS_PACRC_WP1) 02733 02734 /*! @brief Set the WP1 field to a new value. */ 02735 #define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v)) 02736 /*@}*/ 02737 02738 /*! 02739 * @name Register AIPS_PACRC, field SP1[26] (RW) 02740 * 02741 * Determines whether the peripheral requires supervisor privilege level for 02742 * accesses. When this field is set, the master privilege level must indicate the 02743 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02744 * must be set. If not, access terminates with an error response and no peripheral 02745 * access initiates. 02746 * 02747 * Values: 02748 * - 0 - This peripheral does not require supervisor privilege level for 02749 * accesses. 02750 * - 1 - This peripheral requires supervisor privilege level for accesses. 02751 */ 02752 /*@{*/ 02753 #define BP_AIPS_PACRC_SP1 (26U) /*!< Bit position for AIPS_PACRC_SP1. */ 02754 #define BM_AIPS_PACRC_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRC_SP1. */ 02755 #define BS_AIPS_PACRC_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP1. */ 02756 02757 /*! @brief Read current value of the AIPS_PACRC_SP1 field. */ 02758 #define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1)) 02759 02760 /*! @brief Format value for bitfield AIPS_PACRC_SP1. */ 02761 #define BF_AIPS_PACRC_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP1) & BM_AIPS_PACRC_SP1) 02762 02763 /*! @brief Set the SP1 field to a new value. */ 02764 #define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v)) 02765 /*@}*/ 02766 02767 /*! 02768 * @name Register AIPS_PACRC, field TP0[28] (RW) 02769 * 02770 * Determines whether the peripheral allows accesses from an untrusted master. 02771 * When this field is set and an access is attempted by an untrusted master, the 02772 * access terminates with an error response and no peripheral access initiates. 02773 * 02774 * Values: 02775 * - 0 - Accesses from an untrusted master are allowed. 02776 * - 1 - Accesses from an untrusted master are not allowed. 02777 */ 02778 /*@{*/ 02779 #define BP_AIPS_PACRC_TP0 (28U) /*!< Bit position for AIPS_PACRC_TP0. */ 02780 #define BM_AIPS_PACRC_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRC_TP0. */ 02781 #define BS_AIPS_PACRC_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP0. */ 02782 02783 /*! @brief Read current value of the AIPS_PACRC_TP0 field. */ 02784 #define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0)) 02785 02786 /*! @brief Format value for bitfield AIPS_PACRC_TP0. */ 02787 #define BF_AIPS_PACRC_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP0) & BM_AIPS_PACRC_TP0) 02788 02789 /*! @brief Set the TP0 field to a new value. */ 02790 #define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v)) 02791 /*@}*/ 02792 02793 /*! 02794 * @name Register AIPS_PACRC, field WP0[29] (RW) 02795 * 02796 * Determines whether the peripheral allows write accesss. When this bit is set 02797 * and a write access is attempted, access terminates with an error response and 02798 * no peripheral access initiates. 02799 * 02800 * Values: 02801 * - 0 - This peripheral allows write accesses. 02802 * - 1 - This peripheral is write protected. 02803 */ 02804 /*@{*/ 02805 #define BP_AIPS_PACRC_WP0 (29U) /*!< Bit position for AIPS_PACRC_WP0. */ 02806 #define BM_AIPS_PACRC_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRC_WP0. */ 02807 #define BS_AIPS_PACRC_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP0. */ 02808 02809 /*! @brief Read current value of the AIPS_PACRC_WP0 field. */ 02810 #define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0)) 02811 02812 /*! @brief Format value for bitfield AIPS_PACRC_WP0. */ 02813 #define BF_AIPS_PACRC_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP0) & BM_AIPS_PACRC_WP0) 02814 02815 /*! @brief Set the WP0 field to a new value. */ 02816 #define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v)) 02817 /*@}*/ 02818 02819 /*! 02820 * @name Register AIPS_PACRC, field SP0[30] (RW) 02821 * 02822 * Determines whether the peripheral requires supervisor privilege level for 02823 * accesses. When this field is set, the master privilege level must indicate the 02824 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02825 * must be set. If not, access terminates with an error response and no peripheral 02826 * access initiates. 02827 * 02828 * Values: 02829 * - 0 - This peripheral does not require supervisor privilege level for 02830 * accesses. 02831 * - 1 - This peripheral requires supervisor privilege level for accesses. 02832 */ 02833 /*@{*/ 02834 #define BP_AIPS_PACRC_SP0 (30U) /*!< Bit position for AIPS_PACRC_SP0. */ 02835 #define BM_AIPS_PACRC_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRC_SP0. */ 02836 #define BS_AIPS_PACRC_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP0. */ 02837 02838 /*! @brief Read current value of the AIPS_PACRC_SP0 field. */ 02839 #define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0)) 02840 02841 /*! @brief Format value for bitfield AIPS_PACRC_SP0. */ 02842 #define BF_AIPS_PACRC_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP0) & BM_AIPS_PACRC_SP0) 02843 02844 /*! @brief Set the SP0 field to a new value. */ 02845 #define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v)) 02846 /*@}*/ 02847 02848 /******************************************************************************* 02849 * HW_AIPS_PACRD - Peripheral Access Control Register 02850 ******************************************************************************/ 02851 02852 /*! 02853 * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) 02854 * 02855 * Reset value: 0x00000004U 02856 * 02857 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 02858 * defines the access levels for a particular peripheral. The mapping between a 02859 * peripheral and its PACR field is shown in the table below. The peripheral assignment 02860 * to each PACR is defined by the memory map slot that the peripheral is 02861 * assigned to. See this chip's memory map for the assignment of a particular 02862 * peripheral. The following table shows the location of each peripheral slot's PACR field 02863 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 02864 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 02865 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 02866 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 02867 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 02868 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 02869 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 02870 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 02871 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 02872 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 02873 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 02874 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 02875 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 02876 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 02877 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 02878 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 02879 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 02880 * A-D, which control peripheral slots 0-31, are shown below. The following 02881 * section, PACRPeripheral Access Control Register , shows the register field 02882 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 02883 * sections because they occupy two non-contiguous address spaces. 02884 */ 02885 typedef union _hw_aips_pacrd 02886 { 02887 uint32_t U; 02888 struct _hw_aips_pacrd_bitfields 02889 { 02890 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 02891 uint32_t WP7 : 1; /*!< [1] Write Protect */ 02892 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 02893 uint32_t RESERVED0 : 1; /*!< [3] */ 02894 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 02895 uint32_t WP6 : 1; /*!< [5] Write Protect */ 02896 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 02897 uint32_t RESERVED1 : 1; /*!< [7] */ 02898 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 02899 uint32_t WP5 : 1; /*!< [9] Write Protect */ 02900 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 02901 uint32_t RESERVED2 : 1; /*!< [11] */ 02902 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 02903 uint32_t WP4 : 1; /*!< [13] Write Protect */ 02904 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 02905 uint32_t RESERVED3 : 1; /*!< [15] */ 02906 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 02907 uint32_t WP3 : 1; /*!< [17] Write Protect */ 02908 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 02909 uint32_t RESERVED4 : 1; /*!< [19] */ 02910 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 02911 uint32_t WP2 : 1; /*!< [21] Write Protect */ 02912 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 02913 uint32_t RESERVED5 : 1; /*!< [23] */ 02914 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 02915 uint32_t WP1 : 1; /*!< [25] Write Protect */ 02916 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 02917 uint32_t RESERVED6 : 1; /*!< [27] */ 02918 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 02919 uint32_t WP0 : 1; /*!< [29] Write Protect */ 02920 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 02921 uint32_t RESERVED7 : 1; /*!< [31] */ 02922 } B; 02923 } hw_aips_pacrd_t; 02924 02925 /*! 02926 * @name Constants and macros for entire AIPS_PACRD register 02927 */ 02928 /*@{*/ 02929 #define HW_AIPS_PACRD_ADDR(x) ((x) + 0x2CU) 02930 02931 #define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) 02932 #define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U) 02933 #define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v)) 02934 #define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) 02935 #define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) 02936 #define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) 02937 /*@}*/ 02938 02939 /* 02940 * Constants & macros for individual AIPS_PACRD bitfields 02941 */ 02942 02943 /*! 02944 * @name Register AIPS_PACRD, field TP7[0] (RW) 02945 * 02946 * Determines whether the peripheral allows accesses from an untrusted master. 02947 * When this field is set and an access is attempted by an untrusted master, the 02948 * access terminates with an error response and no peripheral access initiates. 02949 * 02950 * Values: 02951 * - 0 - Accesses from an untrusted master are allowed. 02952 * - 1 - Accesses from an untrusted master are not allowed. 02953 */ 02954 /*@{*/ 02955 #define BP_AIPS_PACRD_TP7 (0U) /*!< Bit position for AIPS_PACRD_TP7. */ 02956 #define BM_AIPS_PACRD_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRD_TP7. */ 02957 #define BS_AIPS_PACRD_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP7. */ 02958 02959 /*! @brief Read current value of the AIPS_PACRD_TP7 field. */ 02960 #define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7)) 02961 02962 /*! @brief Format value for bitfield AIPS_PACRD_TP7. */ 02963 #define BF_AIPS_PACRD_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP7) & BM_AIPS_PACRD_TP7) 02964 02965 /*! @brief Set the TP7 field to a new value. */ 02966 #define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v)) 02967 /*@}*/ 02968 02969 /*! 02970 * @name Register AIPS_PACRD, field WP7[1] (RW) 02971 * 02972 * Determines whether the peripheral allows write accesses. When this field is 02973 * set and a write access is attempted, access terminates with an error response 02974 * and no peripheral access initiates. 02975 * 02976 * Values: 02977 * - 0 - This peripheral allows write accesses. 02978 * - 1 - This peripheral is write protected. 02979 */ 02980 /*@{*/ 02981 #define BP_AIPS_PACRD_WP7 (1U) /*!< Bit position for AIPS_PACRD_WP7. */ 02982 #define BM_AIPS_PACRD_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRD_WP7. */ 02983 #define BS_AIPS_PACRD_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP7. */ 02984 02985 /*! @brief Read current value of the AIPS_PACRD_WP7 field. */ 02986 #define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7)) 02987 02988 /*! @brief Format value for bitfield AIPS_PACRD_WP7. */ 02989 #define BF_AIPS_PACRD_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP7) & BM_AIPS_PACRD_WP7) 02990 02991 /*! @brief Set the WP7 field to a new value. */ 02992 #define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v)) 02993 /*@}*/ 02994 02995 /*! 02996 * @name Register AIPS_PACRD, field SP7[2] (RW) 02997 * 02998 * Determines whether the peripheral requires supervisor privilege level for 02999 * accesses. When this field is set, the master privilege level must indicate the 03000 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03001 * must be set. If not, access terminates with an error response and no peripheral 03002 * access initiates. 03003 * 03004 * Values: 03005 * - 0 - This peripheral does not require supervisor privilege level for 03006 * accesses. 03007 * - 1 - This peripheral requires supervisor privilege level for accesses. 03008 */ 03009 /*@{*/ 03010 #define BP_AIPS_PACRD_SP7 (2U) /*!< Bit position for AIPS_PACRD_SP7. */ 03011 #define BM_AIPS_PACRD_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRD_SP7. */ 03012 #define BS_AIPS_PACRD_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP7. */ 03013 03014 /*! @brief Read current value of the AIPS_PACRD_SP7 field. */ 03015 #define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7)) 03016 03017 /*! @brief Format value for bitfield AIPS_PACRD_SP7. */ 03018 #define BF_AIPS_PACRD_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP7) & BM_AIPS_PACRD_SP7) 03019 03020 /*! @brief Set the SP7 field to a new value. */ 03021 #define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v)) 03022 /*@}*/ 03023 03024 /*! 03025 * @name Register AIPS_PACRD, field TP6[4] (RW) 03026 * 03027 * Determines whether the peripheral allows accesses from an untrusted master. 03028 * When this field is set and an access is attempted by an untrusted master, the 03029 * access terminates with an error response and no peripheral access initiates. 03030 * 03031 * Values: 03032 * - 0 - Accesses from an untrusted master are allowed. 03033 * - 1 - Accesses from an untrusted master are not allowed. 03034 */ 03035 /*@{*/ 03036 #define BP_AIPS_PACRD_TP6 (4U) /*!< Bit position for AIPS_PACRD_TP6. */ 03037 #define BM_AIPS_PACRD_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRD_TP6. */ 03038 #define BS_AIPS_PACRD_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP6. */ 03039 03040 /*! @brief Read current value of the AIPS_PACRD_TP6 field. */ 03041 #define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6)) 03042 03043 /*! @brief Format value for bitfield AIPS_PACRD_TP6. */ 03044 #define BF_AIPS_PACRD_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP6) & BM_AIPS_PACRD_TP6) 03045 03046 /*! @brief Set the TP6 field to a new value. */ 03047 #define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v)) 03048 /*@}*/ 03049 03050 /*! 03051 * @name Register AIPS_PACRD, field WP6[5] (RW) 03052 * 03053 * Determines whether the peripheral allows write accesses. When this field is 03054 * set and a write access is attempted, access terminates with an error response 03055 * and no peripheral access initiates. 03056 * 03057 * Values: 03058 * - 0 - This peripheral allows write accesses. 03059 * - 1 - This peripheral is write protected. 03060 */ 03061 /*@{*/ 03062 #define BP_AIPS_PACRD_WP6 (5U) /*!< Bit position for AIPS_PACRD_WP6. */ 03063 #define BM_AIPS_PACRD_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRD_WP6. */ 03064 #define BS_AIPS_PACRD_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP6. */ 03065 03066 /*! @brief Read current value of the AIPS_PACRD_WP6 field. */ 03067 #define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6)) 03068 03069 /*! @brief Format value for bitfield AIPS_PACRD_WP6. */ 03070 #define BF_AIPS_PACRD_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP6) & BM_AIPS_PACRD_WP6) 03071 03072 /*! @brief Set the WP6 field to a new value. */ 03073 #define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v)) 03074 /*@}*/ 03075 03076 /*! 03077 * @name Register AIPS_PACRD, field SP6[6] (RW) 03078 * 03079 * Determines whether the peripheral requires supervisor privilege level for 03080 * accesses. When this field is set, the master privilege level must indicate the 03081 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03082 * must be set. If not, access terminates with an error response and no peripheral 03083 * access initiates. 03084 * 03085 * Values: 03086 * - 0 - This peripheral does not require supervisor privilege level for 03087 * accesses. 03088 * - 1 - This peripheral requires supervisor privilege level for accesses. 03089 */ 03090 /*@{*/ 03091 #define BP_AIPS_PACRD_SP6 (6U) /*!< Bit position for AIPS_PACRD_SP6. */ 03092 #define BM_AIPS_PACRD_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRD_SP6. */ 03093 #define BS_AIPS_PACRD_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP6. */ 03094 03095 /*! @brief Read current value of the AIPS_PACRD_SP6 field. */ 03096 #define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6)) 03097 03098 /*! @brief Format value for bitfield AIPS_PACRD_SP6. */ 03099 #define BF_AIPS_PACRD_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP6) & BM_AIPS_PACRD_SP6) 03100 03101 /*! @brief Set the SP6 field to a new value. */ 03102 #define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v)) 03103 /*@}*/ 03104 03105 /*! 03106 * @name Register AIPS_PACRD, field TP5[8] (RW) 03107 * 03108 * Determines whether the peripheral allows accesses from an untrusted master. 03109 * When this field is set and an access is attempted by an untrusted master, the 03110 * access terminates with an error response and no peripheral access initiates. 03111 * 03112 * Values: 03113 * - 0 - Accesses from an untrusted master are allowed. 03114 * - 1 - Accesses from an untrusted master are not allowed. 03115 */ 03116 /*@{*/ 03117 #define BP_AIPS_PACRD_TP5 (8U) /*!< Bit position for AIPS_PACRD_TP5. */ 03118 #define BM_AIPS_PACRD_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRD_TP5. */ 03119 #define BS_AIPS_PACRD_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP5. */ 03120 03121 /*! @brief Read current value of the AIPS_PACRD_TP5 field. */ 03122 #define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5)) 03123 03124 /*! @brief Format value for bitfield AIPS_PACRD_TP5. */ 03125 #define BF_AIPS_PACRD_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP5) & BM_AIPS_PACRD_TP5) 03126 03127 /*! @brief Set the TP5 field to a new value. */ 03128 #define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v)) 03129 /*@}*/ 03130 03131 /*! 03132 * @name Register AIPS_PACRD, field WP5[9] (RW) 03133 * 03134 * Determines whether the peripheral allows write accesses. When this field is 03135 * set and a write access is attempted, access terminates with an error response 03136 * and no peripheral access initiates. 03137 * 03138 * Values: 03139 * - 0 - This peripheral allows write accesses. 03140 * - 1 - This peripheral is write protected. 03141 */ 03142 /*@{*/ 03143 #define BP_AIPS_PACRD_WP5 (9U) /*!< Bit position for AIPS_PACRD_WP5. */ 03144 #define BM_AIPS_PACRD_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRD_WP5. */ 03145 #define BS_AIPS_PACRD_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP5. */ 03146 03147 /*! @brief Read current value of the AIPS_PACRD_WP5 field. */ 03148 #define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5)) 03149 03150 /*! @brief Format value for bitfield AIPS_PACRD_WP5. */ 03151 #define BF_AIPS_PACRD_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP5) & BM_AIPS_PACRD_WP5) 03152 03153 /*! @brief Set the WP5 field to a new value. */ 03154 #define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v)) 03155 /*@}*/ 03156 03157 /*! 03158 * @name Register AIPS_PACRD, field SP5[10] (RW) 03159 * 03160 * Determines whether the peripheral requires supervisor privilege level for 03161 * accesses. When this field is set, the master privilege level must indicate the 03162 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03163 * must be set. If not, access terminates with an error response and no peripheral 03164 * access initiates. 03165 * 03166 * Values: 03167 * - 0 - This peripheral does not require supervisor privilege level for 03168 * accesses. 03169 * - 1 - This peripheral requires supervisor privilege level for accesses. 03170 */ 03171 /*@{*/ 03172 #define BP_AIPS_PACRD_SP5 (10U) /*!< Bit position for AIPS_PACRD_SP5. */ 03173 #define BM_AIPS_PACRD_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRD_SP5. */ 03174 #define BS_AIPS_PACRD_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP5. */ 03175 03176 /*! @brief Read current value of the AIPS_PACRD_SP5 field. */ 03177 #define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5)) 03178 03179 /*! @brief Format value for bitfield AIPS_PACRD_SP5. */ 03180 #define BF_AIPS_PACRD_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP5) & BM_AIPS_PACRD_SP5) 03181 03182 /*! @brief Set the SP5 field to a new value. */ 03183 #define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v)) 03184 /*@}*/ 03185 03186 /*! 03187 * @name Register AIPS_PACRD, field TP4[12] (RW) 03188 * 03189 * Determines whether the peripheral allows accesses from an untrusted master. 03190 * When this field is set and an access is attempted by an untrusted master, the 03191 * access terminates with an error response and no peripheral access initiates. 03192 * 03193 * Values: 03194 * - 0 - Accesses from an untrusted master are allowed. 03195 * - 1 - Accesses from an untrusted master are not allowed. 03196 */ 03197 /*@{*/ 03198 #define BP_AIPS_PACRD_TP4 (12U) /*!< Bit position for AIPS_PACRD_TP4. */ 03199 #define BM_AIPS_PACRD_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRD_TP4. */ 03200 #define BS_AIPS_PACRD_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP4. */ 03201 03202 /*! @brief Read current value of the AIPS_PACRD_TP4 field. */ 03203 #define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4)) 03204 03205 /*! @brief Format value for bitfield AIPS_PACRD_TP4. */ 03206 #define BF_AIPS_PACRD_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP4) & BM_AIPS_PACRD_TP4) 03207 03208 /*! @brief Set the TP4 field to a new value. */ 03209 #define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v)) 03210 /*@}*/ 03211 03212 /*! 03213 * @name Register AIPS_PACRD, field WP4[13] (RW) 03214 * 03215 * Determines whether the peripheral allows write accesss. When this bit is set 03216 * and a write access is attempted, access terminates with an error response and 03217 * no peripheral access initiates. 03218 * 03219 * Values: 03220 * - 0 - This peripheral allows write accesses. 03221 * - 1 - This peripheral is write protected. 03222 */ 03223 /*@{*/ 03224 #define BP_AIPS_PACRD_WP4 (13U) /*!< Bit position for AIPS_PACRD_WP4. */ 03225 #define BM_AIPS_PACRD_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRD_WP4. */ 03226 #define BS_AIPS_PACRD_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP4. */ 03227 03228 /*! @brief Read current value of the AIPS_PACRD_WP4 field. */ 03229 #define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4)) 03230 03231 /*! @brief Format value for bitfield AIPS_PACRD_WP4. */ 03232 #define BF_AIPS_PACRD_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP4) & BM_AIPS_PACRD_WP4) 03233 03234 /*! @brief Set the WP4 field to a new value. */ 03235 #define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v)) 03236 /*@}*/ 03237 03238 /*! 03239 * @name Register AIPS_PACRD, field SP4[14] (RW) 03240 * 03241 * Determines whether the peripheral requires supervisor privilege level for 03242 * accesses. When this field is set, the master privilege level must indicate the 03243 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03244 * must be set. If not, access terminates with an error response and no peripheral 03245 * access initiates. 03246 * 03247 * Values: 03248 * - 0 - This peripheral does not require supervisor privilege level for 03249 * accesses. 03250 * - 1 - This peripheral requires supervisor privilege level for accesses. 03251 */ 03252 /*@{*/ 03253 #define BP_AIPS_PACRD_SP4 (14U) /*!< Bit position for AIPS_PACRD_SP4. */ 03254 #define BM_AIPS_PACRD_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRD_SP4. */ 03255 #define BS_AIPS_PACRD_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP4. */ 03256 03257 /*! @brief Read current value of the AIPS_PACRD_SP4 field. */ 03258 #define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4)) 03259 03260 /*! @brief Format value for bitfield AIPS_PACRD_SP4. */ 03261 #define BF_AIPS_PACRD_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP4) & BM_AIPS_PACRD_SP4) 03262 03263 /*! @brief Set the SP4 field to a new value. */ 03264 #define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v)) 03265 /*@}*/ 03266 03267 /*! 03268 * @name Register AIPS_PACRD, field TP3[16] (RW) 03269 * 03270 * Determines whether the peripheral allows accesses from an untrusted master. 03271 * When this bit is set and an access is attempted by an untrusted master, the 03272 * access terminates with an error response and no peripheral access initiates. 03273 * 03274 * Values: 03275 * - 0 - Accesses from an untrusted master are allowed. 03276 * - 1 - Accesses from an untrusted master are not allowed. 03277 */ 03278 /*@{*/ 03279 #define BP_AIPS_PACRD_TP3 (16U) /*!< Bit position for AIPS_PACRD_TP3. */ 03280 #define BM_AIPS_PACRD_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRD_TP3. */ 03281 #define BS_AIPS_PACRD_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP3. */ 03282 03283 /*! @brief Read current value of the AIPS_PACRD_TP3 field. */ 03284 #define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3)) 03285 03286 /*! @brief Format value for bitfield AIPS_PACRD_TP3. */ 03287 #define BF_AIPS_PACRD_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP3) & BM_AIPS_PACRD_TP3) 03288 03289 /*! @brief Set the TP3 field to a new value. */ 03290 #define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v)) 03291 /*@}*/ 03292 03293 /*! 03294 * @name Register AIPS_PACRD, field WP3[17] (RW) 03295 * 03296 * Determines whether the peripheral allows write accesses. When this field is 03297 * set and a write access is attempted, access terminates with an error response 03298 * and no peripheral access initiates. 03299 * 03300 * Values: 03301 * - 0 - This peripheral allows write accesses. 03302 * - 1 - This peripheral is write protected. 03303 */ 03304 /*@{*/ 03305 #define BP_AIPS_PACRD_WP3 (17U) /*!< Bit position for AIPS_PACRD_WP3. */ 03306 #define BM_AIPS_PACRD_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRD_WP3. */ 03307 #define BS_AIPS_PACRD_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP3. */ 03308 03309 /*! @brief Read current value of the AIPS_PACRD_WP3 field. */ 03310 #define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3)) 03311 03312 /*! @brief Format value for bitfield AIPS_PACRD_WP3. */ 03313 #define BF_AIPS_PACRD_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP3) & BM_AIPS_PACRD_WP3) 03314 03315 /*! @brief Set the WP3 field to a new value. */ 03316 #define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v)) 03317 /*@}*/ 03318 03319 /*! 03320 * @name Register AIPS_PACRD, field SP3[18] (RW) 03321 * 03322 * Determines whether the peripheral requires supervisor privilege level for 03323 * access. When this bit is set, the master privilege level must indicate the 03324 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 03325 * set. If not, access terminates with an error response and no peripheral access 03326 * initiates. 03327 * 03328 * Values: 03329 * - 0 - This peripheral does not require supervisor privilege level for 03330 * accesses. 03331 * - 1 - This peripheral requires supervisor privilege level for accesses. 03332 */ 03333 /*@{*/ 03334 #define BP_AIPS_PACRD_SP3 (18U) /*!< Bit position for AIPS_PACRD_SP3. */ 03335 #define BM_AIPS_PACRD_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRD_SP3. */ 03336 #define BS_AIPS_PACRD_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP3. */ 03337 03338 /*! @brief Read current value of the AIPS_PACRD_SP3 field. */ 03339 #define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3)) 03340 03341 /*! @brief Format value for bitfield AIPS_PACRD_SP3. */ 03342 #define BF_AIPS_PACRD_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP3) & BM_AIPS_PACRD_SP3) 03343 03344 /*! @brief Set the SP3 field to a new value. */ 03345 #define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v)) 03346 /*@}*/ 03347 03348 /*! 03349 * @name Register AIPS_PACRD, field TP2[20] (RW) 03350 * 03351 * Determines whether the peripheral allows accesses from an untrusted master. 03352 * When this field is set and an access is attempted by an untrusted master, the 03353 * access terminates with an error response and no peripheral access initiates. 03354 * 03355 * Values: 03356 * - 0 - Accesses from an untrusted master are allowed. 03357 * - 1 - Accesses from an untrusted master are not allowed. 03358 */ 03359 /*@{*/ 03360 #define BP_AIPS_PACRD_TP2 (20U) /*!< Bit position for AIPS_PACRD_TP2. */ 03361 #define BM_AIPS_PACRD_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRD_TP2. */ 03362 #define BS_AIPS_PACRD_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP2. */ 03363 03364 /*! @brief Read current value of the AIPS_PACRD_TP2 field. */ 03365 #define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2)) 03366 03367 /*! @brief Format value for bitfield AIPS_PACRD_TP2. */ 03368 #define BF_AIPS_PACRD_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP2) & BM_AIPS_PACRD_TP2) 03369 03370 /*! @brief Set the TP2 field to a new value. */ 03371 #define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v)) 03372 /*@}*/ 03373 03374 /*! 03375 * @name Register AIPS_PACRD, field WP2[21] (RW) 03376 * 03377 * Determines whether the peripheral allows write accesss. When this bit is set 03378 * and a write access is attempted, access terminates with an error response and 03379 * no peripheral access initiates. 03380 * 03381 * Values: 03382 * - 0 - This peripheral allows write accesses. 03383 * - 1 - This peripheral is write protected. 03384 */ 03385 /*@{*/ 03386 #define BP_AIPS_PACRD_WP2 (21U) /*!< Bit position for AIPS_PACRD_WP2. */ 03387 #define BM_AIPS_PACRD_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRD_WP2. */ 03388 #define BS_AIPS_PACRD_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP2. */ 03389 03390 /*! @brief Read current value of the AIPS_PACRD_WP2 field. */ 03391 #define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2)) 03392 03393 /*! @brief Format value for bitfield AIPS_PACRD_WP2. */ 03394 #define BF_AIPS_PACRD_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP2) & BM_AIPS_PACRD_WP2) 03395 03396 /*! @brief Set the WP2 field to a new value. */ 03397 #define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v)) 03398 /*@}*/ 03399 03400 /*! 03401 * @name Register AIPS_PACRD, field SP2[22] (RW) 03402 * 03403 * Determines whether the peripheral requires supervisor privilege level for 03404 * accesses. When this field is set, the master privilege level must indicate the 03405 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03406 * must be set. If not, access terminates with an error response and no peripheral 03407 * access initiates. 03408 * 03409 * Values: 03410 * - 0 - This peripheral does not require supervisor privilege level for 03411 * accesses. 03412 * - 1 - This peripheral requires supervisor privilege level for accesses. 03413 */ 03414 /*@{*/ 03415 #define BP_AIPS_PACRD_SP2 (22U) /*!< Bit position for AIPS_PACRD_SP2. */ 03416 #define BM_AIPS_PACRD_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRD_SP2. */ 03417 #define BS_AIPS_PACRD_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP2. */ 03418 03419 /*! @brief Read current value of the AIPS_PACRD_SP2 field. */ 03420 #define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2)) 03421 03422 /*! @brief Format value for bitfield AIPS_PACRD_SP2. */ 03423 #define BF_AIPS_PACRD_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP2) & BM_AIPS_PACRD_SP2) 03424 03425 /*! @brief Set the SP2 field to a new value. */ 03426 #define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v)) 03427 /*@}*/ 03428 03429 /*! 03430 * @name Register AIPS_PACRD, field TP1[24] (RW) 03431 * 03432 * Determines whether the peripheral allows accesses from an untrusted master. 03433 * When this bit is set and an access is attempted by an untrusted master, the 03434 * access terminates with an error response and no peripheral access initiates. 03435 * 03436 * Values: 03437 * - 0 - Accesses from an untrusted master are allowed. 03438 * - 1 - Accesses from an untrusted master are not allowed. 03439 */ 03440 /*@{*/ 03441 #define BP_AIPS_PACRD_TP1 (24U) /*!< Bit position for AIPS_PACRD_TP1. */ 03442 #define BM_AIPS_PACRD_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRD_TP1. */ 03443 #define BS_AIPS_PACRD_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP1. */ 03444 03445 /*! @brief Read current value of the AIPS_PACRD_TP1 field. */ 03446 #define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1)) 03447 03448 /*! @brief Format value for bitfield AIPS_PACRD_TP1. */ 03449 #define BF_AIPS_PACRD_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP1) & BM_AIPS_PACRD_TP1) 03450 03451 /*! @brief Set the TP1 field to a new value. */ 03452 #define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v)) 03453 /*@}*/ 03454 03455 /*! 03456 * @name Register AIPS_PACRD, field WP1[25] (RW) 03457 * 03458 * Determines whether the peripheral allows write accesses. When this field is 03459 * set and a write access is attempted, access terminates with an error response 03460 * and no peripheral access initiates. 03461 * 03462 * Values: 03463 * - 0 - This peripheral allows write accesses. 03464 * - 1 - This peripheral is write protected. 03465 */ 03466 /*@{*/ 03467 #define BP_AIPS_PACRD_WP1 (25U) /*!< Bit position for AIPS_PACRD_WP1. */ 03468 #define BM_AIPS_PACRD_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRD_WP1. */ 03469 #define BS_AIPS_PACRD_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP1. */ 03470 03471 /*! @brief Read current value of the AIPS_PACRD_WP1 field. */ 03472 #define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1)) 03473 03474 /*! @brief Format value for bitfield AIPS_PACRD_WP1. */ 03475 #define BF_AIPS_PACRD_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP1) & BM_AIPS_PACRD_WP1) 03476 03477 /*! @brief Set the WP1 field to a new value. */ 03478 #define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v)) 03479 /*@}*/ 03480 03481 /*! 03482 * @name Register AIPS_PACRD, field SP1[26] (RW) 03483 * 03484 * Determines whether the peripheral requires supervisor privilege level for 03485 * accesses. When this field is set, the master privilege level must indicate the 03486 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03487 * must be set. If not, access terminates with an error response and no peripheral 03488 * access initiates. 03489 * 03490 * Values: 03491 * - 0 - This peripheral does not require supervisor privilege level for 03492 * accesses. 03493 * - 1 - This peripheral requires supervisor privilege level for accesses. 03494 */ 03495 /*@{*/ 03496 #define BP_AIPS_PACRD_SP1 (26U) /*!< Bit position for AIPS_PACRD_SP1. */ 03497 #define BM_AIPS_PACRD_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRD_SP1. */ 03498 #define BS_AIPS_PACRD_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP1. */ 03499 03500 /*! @brief Read current value of the AIPS_PACRD_SP1 field. */ 03501 #define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1)) 03502 03503 /*! @brief Format value for bitfield AIPS_PACRD_SP1. */ 03504 #define BF_AIPS_PACRD_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP1) & BM_AIPS_PACRD_SP1) 03505 03506 /*! @brief Set the SP1 field to a new value. */ 03507 #define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v)) 03508 /*@}*/ 03509 03510 /*! 03511 * @name Register AIPS_PACRD, field TP0[28] (RW) 03512 * 03513 * Determines whether the peripheral allows accesses from an untrusted master. 03514 * When this field is set and an access is attempted by an untrusted master, the 03515 * access terminates with an error response and no peripheral access initiates. 03516 * 03517 * Values: 03518 * - 0 - Accesses from an untrusted master are allowed. 03519 * - 1 - Accesses from an untrusted master are not allowed. 03520 */ 03521 /*@{*/ 03522 #define BP_AIPS_PACRD_TP0 (28U) /*!< Bit position for AIPS_PACRD_TP0. */ 03523 #define BM_AIPS_PACRD_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRD_TP0. */ 03524 #define BS_AIPS_PACRD_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP0. */ 03525 03526 /*! @brief Read current value of the AIPS_PACRD_TP0 field. */ 03527 #define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0)) 03528 03529 /*! @brief Format value for bitfield AIPS_PACRD_TP0. */ 03530 #define BF_AIPS_PACRD_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP0) & BM_AIPS_PACRD_TP0) 03531 03532 /*! @brief Set the TP0 field to a new value. */ 03533 #define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v)) 03534 /*@}*/ 03535 03536 /*! 03537 * @name Register AIPS_PACRD, field WP0[29] (RW) 03538 * 03539 * Determines whether the peripheral allows write accesss. When this bit is set 03540 * and a write access is attempted, access terminates with an error response and 03541 * no peripheral access initiates. 03542 * 03543 * Values: 03544 * - 0 - This peripheral allows write accesses. 03545 * - 1 - This peripheral is write protected. 03546 */ 03547 /*@{*/ 03548 #define BP_AIPS_PACRD_WP0 (29U) /*!< Bit position for AIPS_PACRD_WP0. */ 03549 #define BM_AIPS_PACRD_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRD_WP0. */ 03550 #define BS_AIPS_PACRD_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP0. */ 03551 03552 /*! @brief Read current value of the AIPS_PACRD_WP0 field. */ 03553 #define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0)) 03554 03555 /*! @brief Format value for bitfield AIPS_PACRD_WP0. */ 03556 #define BF_AIPS_PACRD_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP0) & BM_AIPS_PACRD_WP0) 03557 03558 /*! @brief Set the WP0 field to a new value. */ 03559 #define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v)) 03560 /*@}*/ 03561 03562 /*! 03563 * @name Register AIPS_PACRD, field SP0[30] (RW) 03564 * 03565 * Determines whether the peripheral requires supervisor privilege level for 03566 * accesses. When this field is set, the master privilege level must indicate the 03567 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03568 * must be set. If not, access terminates with an error response and no peripheral 03569 * access initiates. 03570 * 03571 * Values: 03572 * - 0 - This peripheral does not require supervisor privilege level for 03573 * accesses. 03574 * - 1 - This peripheral requires supervisor privilege level for accesses. 03575 */ 03576 /*@{*/ 03577 #define BP_AIPS_PACRD_SP0 (30U) /*!< Bit position for AIPS_PACRD_SP0. */ 03578 #define BM_AIPS_PACRD_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRD_SP0. */ 03579 #define BS_AIPS_PACRD_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP0. */ 03580 03581 /*! @brief Read current value of the AIPS_PACRD_SP0 field. */ 03582 #define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0)) 03583 03584 /*! @brief Format value for bitfield AIPS_PACRD_SP0. */ 03585 #define BF_AIPS_PACRD_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP0) & BM_AIPS_PACRD_SP0) 03586 03587 /*! @brief Set the SP0 field to a new value. */ 03588 #define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v)) 03589 /*@}*/ 03590 03591 /******************************************************************************* 03592 * HW_AIPS_PACRE - Peripheral Access Control Register 03593 ******************************************************************************/ 03594 03595 /*! 03596 * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) 03597 * 03598 * Reset value: 0x44444444U 03599 * 03600 * This section describes PACR registers E-P, which control peripheral slots 03601 * 32-127. See PACRPeripheral Access Control Register for the description of these 03602 * registers. 03603 */ 03604 typedef union _hw_aips_pacre 03605 { 03606 uint32_t U; 03607 struct _hw_aips_pacre_bitfields 03608 { 03609 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 03610 uint32_t WP7 : 1; /*!< [1] Write Protect */ 03611 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 03612 uint32_t RESERVED0 : 1; /*!< [3] */ 03613 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 03614 uint32_t WP6 : 1; /*!< [5] Write Protect */ 03615 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 03616 uint32_t RESERVED1 : 1; /*!< [7] */ 03617 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 03618 uint32_t WP5 : 1; /*!< [9] Write Protect */ 03619 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 03620 uint32_t RESERVED2 : 1; /*!< [11] */ 03621 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 03622 uint32_t WP4 : 1; /*!< [13] Write Protect */ 03623 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 03624 uint32_t RESERVED3 : 1; /*!< [15] */ 03625 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 03626 uint32_t WP3 : 1; /*!< [17] Write Protect */ 03627 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 03628 uint32_t RESERVED4 : 1; /*!< [19] */ 03629 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 03630 uint32_t WP2 : 1; /*!< [21] Write Protect */ 03631 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 03632 uint32_t RESERVED5 : 1; /*!< [23] */ 03633 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 03634 uint32_t WP1 : 1; /*!< [25] Write Protect */ 03635 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 03636 uint32_t RESERVED6 : 1; /*!< [27] */ 03637 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 03638 uint32_t WP0 : 1; /*!< [29] Write Protect */ 03639 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 03640 uint32_t RESERVED7 : 1; /*!< [31] */ 03641 } B; 03642 } hw_aips_pacre_t; 03643 03644 /*! 03645 * @name Constants and macros for entire AIPS_PACRE register 03646 */ 03647 /*@{*/ 03648 #define HW_AIPS_PACRE_ADDR(x) ((x) + 0x40U) 03649 03650 #define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) 03651 #define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U) 03652 #define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v)) 03653 #define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) 03654 #define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) 03655 #define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) 03656 /*@}*/ 03657 03658 /* 03659 * Constants & macros for individual AIPS_PACRE bitfields 03660 */ 03661 03662 /*! 03663 * @name Register AIPS_PACRE, field TP7[0] (RW) 03664 * 03665 * Determines whether the peripheral allows accesses from an untrusted master. 03666 * When this field is set and an access is attempted by an untrusted master, the 03667 * access terminates with an error response and no peripheral access initiates. 03668 * 03669 * Values: 03670 * - 0 - Accesses from an untrusted master are allowed. 03671 * - 1 - Accesses from an untrusted master are not allowed. 03672 */ 03673 /*@{*/ 03674 #define BP_AIPS_PACRE_TP7 (0U) /*!< Bit position for AIPS_PACRE_TP7. */ 03675 #define BM_AIPS_PACRE_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRE_TP7. */ 03676 #define BS_AIPS_PACRE_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP7. */ 03677 03678 /*! @brief Read current value of the AIPS_PACRE_TP7 field. */ 03679 #define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7)) 03680 03681 /*! @brief Format value for bitfield AIPS_PACRE_TP7. */ 03682 #define BF_AIPS_PACRE_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP7) & BM_AIPS_PACRE_TP7) 03683 03684 /*! @brief Set the TP7 field to a new value. */ 03685 #define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v)) 03686 /*@}*/ 03687 03688 /*! 03689 * @name Register AIPS_PACRE, field WP7[1] (RW) 03690 * 03691 * Determines whether the peripheral allows write accesses. When this field is 03692 * set and a write access is attempted, access terminates with an error response 03693 * and no peripheral access initiates. 03694 * 03695 * Values: 03696 * - 0 - This peripheral allows write accesses. 03697 * - 1 - This peripheral is write protected. 03698 */ 03699 /*@{*/ 03700 #define BP_AIPS_PACRE_WP7 (1U) /*!< Bit position for AIPS_PACRE_WP7. */ 03701 #define BM_AIPS_PACRE_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRE_WP7. */ 03702 #define BS_AIPS_PACRE_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP7. */ 03703 03704 /*! @brief Read current value of the AIPS_PACRE_WP7 field. */ 03705 #define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7)) 03706 03707 /*! @brief Format value for bitfield AIPS_PACRE_WP7. */ 03708 #define BF_AIPS_PACRE_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP7) & BM_AIPS_PACRE_WP7) 03709 03710 /*! @brief Set the WP7 field to a new value. */ 03711 #define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v)) 03712 /*@}*/ 03713 03714 /*! 03715 * @name Register AIPS_PACRE, field SP7[2] (RW) 03716 * 03717 * Determines whether the peripheral requires supervisor privilege level for 03718 * accesses. When this field is set, the master privilege level must indicate the 03719 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03720 * must be set. If not, access terminates with an error response and no peripheral 03721 * access initiates. 03722 * 03723 * Values: 03724 * - 0 - This peripheral does not require supervisor privilege level for 03725 * accesses. 03726 * - 1 - This peripheral requires supervisor privilege level for accesses. 03727 */ 03728 /*@{*/ 03729 #define BP_AIPS_PACRE_SP7 (2U) /*!< Bit position for AIPS_PACRE_SP7. */ 03730 #define BM_AIPS_PACRE_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRE_SP7. */ 03731 #define BS_AIPS_PACRE_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP7. */ 03732 03733 /*! @brief Read current value of the AIPS_PACRE_SP7 field. */ 03734 #define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7)) 03735 03736 /*! @brief Format value for bitfield AIPS_PACRE_SP7. */ 03737 #define BF_AIPS_PACRE_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP7) & BM_AIPS_PACRE_SP7) 03738 03739 /*! @brief Set the SP7 field to a new value. */ 03740 #define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v)) 03741 /*@}*/ 03742 03743 /*! 03744 * @name Register AIPS_PACRE, field TP6[4] (RW) 03745 * 03746 * Determines whether the peripheral allows accesses from an untrusted master. 03747 * When this field is set and an access is attempted by an untrusted master, the 03748 * access terminates with an error response and no peripheral access initiates. 03749 * 03750 * Values: 03751 * - 0 - Accesses from an untrusted master are allowed. 03752 * - 1 - Accesses from an untrusted master are not allowed. 03753 */ 03754 /*@{*/ 03755 #define BP_AIPS_PACRE_TP6 (4U) /*!< Bit position for AIPS_PACRE_TP6. */ 03756 #define BM_AIPS_PACRE_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRE_TP6. */ 03757 #define BS_AIPS_PACRE_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP6. */ 03758 03759 /*! @brief Read current value of the AIPS_PACRE_TP6 field. */ 03760 #define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6)) 03761 03762 /*! @brief Format value for bitfield AIPS_PACRE_TP6. */ 03763 #define BF_AIPS_PACRE_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP6) & BM_AIPS_PACRE_TP6) 03764 03765 /*! @brief Set the TP6 field to a new value. */ 03766 #define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v)) 03767 /*@}*/ 03768 03769 /*! 03770 * @name Register AIPS_PACRE, field WP6[5] (RW) 03771 * 03772 * Determines whether the peripheral allows write accesses. When this field is 03773 * set and a write access is attempted, access terminates with an error response 03774 * and no peripheral access initiates. 03775 * 03776 * Values: 03777 * - 0 - This peripheral allows write accesses. 03778 * - 1 - This peripheral is write protected. 03779 */ 03780 /*@{*/ 03781 #define BP_AIPS_PACRE_WP6 (5U) /*!< Bit position for AIPS_PACRE_WP6. */ 03782 #define BM_AIPS_PACRE_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRE_WP6. */ 03783 #define BS_AIPS_PACRE_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP6. */ 03784 03785 /*! @brief Read current value of the AIPS_PACRE_WP6 field. */ 03786 #define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6)) 03787 03788 /*! @brief Format value for bitfield AIPS_PACRE_WP6. */ 03789 #define BF_AIPS_PACRE_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP6) & BM_AIPS_PACRE_WP6) 03790 03791 /*! @brief Set the WP6 field to a new value. */ 03792 #define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v)) 03793 /*@}*/ 03794 03795 /*! 03796 * @name Register AIPS_PACRE, field SP6[6] (RW) 03797 * 03798 * Determines whether the peripheral requires supervisor privilege level for 03799 * accesses. When this field is set, the master privilege level must indicate the 03800 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03801 * must be set. If not, access terminates with an error response and no peripheral 03802 * access initiates. 03803 * 03804 * Values: 03805 * - 0 - This peripheral does not require supervisor privilege level for 03806 * accesses. 03807 * - 1 - This peripheral requires supervisor privilege level for accesses. 03808 */ 03809 /*@{*/ 03810 #define BP_AIPS_PACRE_SP6 (6U) /*!< Bit position for AIPS_PACRE_SP6. */ 03811 #define BM_AIPS_PACRE_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRE_SP6. */ 03812 #define BS_AIPS_PACRE_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP6. */ 03813 03814 /*! @brief Read current value of the AIPS_PACRE_SP6 field. */ 03815 #define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6)) 03816 03817 /*! @brief Format value for bitfield AIPS_PACRE_SP6. */ 03818 #define BF_AIPS_PACRE_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP6) & BM_AIPS_PACRE_SP6) 03819 03820 /*! @brief Set the SP6 field to a new value. */ 03821 #define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v)) 03822 /*@}*/ 03823 03824 /*! 03825 * @name Register AIPS_PACRE, field TP5[8] (RW) 03826 * 03827 * Determines whether the peripheral allows accesses from an untrusted master. 03828 * When this field is set and an access is attempted by an untrusted master, the 03829 * access terminates with an error response and no peripheral access initiates. 03830 * 03831 * Values: 03832 * - 0 - Accesses from an untrusted master are allowed. 03833 * - 1 - Accesses from an untrusted master are not allowed. 03834 */ 03835 /*@{*/ 03836 #define BP_AIPS_PACRE_TP5 (8U) /*!< Bit position for AIPS_PACRE_TP5. */ 03837 #define BM_AIPS_PACRE_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRE_TP5. */ 03838 #define BS_AIPS_PACRE_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP5. */ 03839 03840 /*! @brief Read current value of the AIPS_PACRE_TP5 field. */ 03841 #define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5)) 03842 03843 /*! @brief Format value for bitfield AIPS_PACRE_TP5. */ 03844 #define BF_AIPS_PACRE_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP5) & BM_AIPS_PACRE_TP5) 03845 03846 /*! @brief Set the TP5 field to a new value. */ 03847 #define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v)) 03848 /*@}*/ 03849 03850 /*! 03851 * @name Register AIPS_PACRE, field WP5[9] (RW) 03852 * 03853 * Determines whether the peripheral allows write accesses. When this field is 03854 * set and a write access is attempted, access terminates with an error response 03855 * and no peripheral access initiates. 03856 * 03857 * Values: 03858 * - 0 - This peripheral allows write accesses. 03859 * - 1 - This peripheral is write protected. 03860 */ 03861 /*@{*/ 03862 #define BP_AIPS_PACRE_WP5 (9U) /*!< Bit position for AIPS_PACRE_WP5. */ 03863 #define BM_AIPS_PACRE_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRE_WP5. */ 03864 #define BS_AIPS_PACRE_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP5. */ 03865 03866 /*! @brief Read current value of the AIPS_PACRE_WP5 field. */ 03867 #define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5)) 03868 03869 /*! @brief Format value for bitfield AIPS_PACRE_WP5. */ 03870 #define BF_AIPS_PACRE_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP5) & BM_AIPS_PACRE_WP5) 03871 03872 /*! @brief Set the WP5 field to a new value. */ 03873 #define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v)) 03874 /*@}*/ 03875 03876 /*! 03877 * @name Register AIPS_PACRE, field SP5[10] (RW) 03878 * 03879 * Determines whether the peripheral requires supervisor privilege level for 03880 * accesses. When this field is set, the master privilege level must indicate the 03881 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03882 * must be set. If not, access terminates with an error response and no peripheral 03883 * access initiates. 03884 * 03885 * Values: 03886 * - 0 - This peripheral does not require supervisor privilege level for 03887 * accesses. 03888 * - 1 - This peripheral requires supervisor privilege level for accesses. 03889 */ 03890 /*@{*/ 03891 #define BP_AIPS_PACRE_SP5 (10U) /*!< Bit position for AIPS_PACRE_SP5. */ 03892 #define BM_AIPS_PACRE_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRE_SP5. */ 03893 #define BS_AIPS_PACRE_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP5. */ 03894 03895 /*! @brief Read current value of the AIPS_PACRE_SP5 field. */ 03896 #define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5)) 03897 03898 /*! @brief Format value for bitfield AIPS_PACRE_SP5. */ 03899 #define BF_AIPS_PACRE_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP5) & BM_AIPS_PACRE_SP5) 03900 03901 /*! @brief Set the SP5 field to a new value. */ 03902 #define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v)) 03903 /*@}*/ 03904 03905 /*! 03906 * @name Register AIPS_PACRE, field TP4[12] (RW) 03907 * 03908 * Determines whether the peripheral allows accesses from an untrusted master. 03909 * When this bit is set and an access is attempted by an untrusted master, the 03910 * access terminates with an error response and no peripheral access initiates. 03911 * 03912 * Values: 03913 * - 0 - Accesses from an untrusted master are allowed. 03914 * - 1 - Accesses from an untrusted master are not allowed. 03915 */ 03916 /*@{*/ 03917 #define BP_AIPS_PACRE_TP4 (12U) /*!< Bit position for AIPS_PACRE_TP4. */ 03918 #define BM_AIPS_PACRE_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRE_TP4. */ 03919 #define BS_AIPS_PACRE_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP4. */ 03920 03921 /*! @brief Read current value of the AIPS_PACRE_TP4 field. */ 03922 #define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4)) 03923 03924 /*! @brief Format value for bitfield AIPS_PACRE_TP4. */ 03925 #define BF_AIPS_PACRE_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP4) & BM_AIPS_PACRE_TP4) 03926 03927 /*! @brief Set the TP4 field to a new value. */ 03928 #define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v)) 03929 /*@}*/ 03930 03931 /*! 03932 * @name Register AIPS_PACRE, field WP4[13] (RW) 03933 * 03934 * Determines whether the peripheral allows write accesses. When this field is 03935 * set and a write access is attempted, access terminates with an error response 03936 * and no peripheral access initiates. 03937 * 03938 * Values: 03939 * - 0 - This peripheral allows write accesses. 03940 * - 1 - This peripheral is write protected. 03941 */ 03942 /*@{*/ 03943 #define BP_AIPS_PACRE_WP4 (13U) /*!< Bit position for AIPS_PACRE_WP4. */ 03944 #define BM_AIPS_PACRE_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRE_WP4. */ 03945 #define BS_AIPS_PACRE_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP4. */ 03946 03947 /*! @brief Read current value of the AIPS_PACRE_WP4 field. */ 03948 #define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4)) 03949 03950 /*! @brief Format value for bitfield AIPS_PACRE_WP4. */ 03951 #define BF_AIPS_PACRE_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP4) & BM_AIPS_PACRE_WP4) 03952 03953 /*! @brief Set the WP4 field to a new value. */ 03954 #define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v)) 03955 /*@}*/ 03956 03957 /*! 03958 * @name Register AIPS_PACRE, field SP4[14] (RW) 03959 * 03960 * Determines whether the peripheral requires supervisor privilege level for 03961 * access. When this bit is set, the master privilege level must indicate the 03962 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 03963 * set. If not, access terminates with an error response and no peripheral access 03964 * initiates. 03965 * 03966 * Values: 03967 * - 0 - This peripheral does not require supervisor privilege level for 03968 * accesses. 03969 * - 1 - This peripheral requires supervisor privilege level for accesses. 03970 */ 03971 /*@{*/ 03972 #define BP_AIPS_PACRE_SP4 (14U) /*!< Bit position for AIPS_PACRE_SP4. */ 03973 #define BM_AIPS_PACRE_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRE_SP4. */ 03974 #define BS_AIPS_PACRE_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP4. */ 03975 03976 /*! @brief Read current value of the AIPS_PACRE_SP4 field. */ 03977 #define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4)) 03978 03979 /*! @brief Format value for bitfield AIPS_PACRE_SP4. */ 03980 #define BF_AIPS_PACRE_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP4) & BM_AIPS_PACRE_SP4) 03981 03982 /*! @brief Set the SP4 field to a new value. */ 03983 #define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v)) 03984 /*@}*/ 03985 03986 /*! 03987 * @name Register AIPS_PACRE, field TP3[16] (RW) 03988 * 03989 * Determines whether the peripheral allows accesses from an untrusted master. 03990 * When this field is set and an access is attempted by an untrusted master, the 03991 * access terminates with an error response and no peripheral access initiates. 03992 * 03993 * Values: 03994 * - 0 - Accesses from an untrusted master are allowed. 03995 * - 1 - Accesses from an untrusted master are not allowed. 03996 */ 03997 /*@{*/ 03998 #define BP_AIPS_PACRE_TP3 (16U) /*!< Bit position for AIPS_PACRE_TP3. */ 03999 #define BM_AIPS_PACRE_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRE_TP3. */ 04000 #define BS_AIPS_PACRE_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP3. */ 04001 04002 /*! @brief Read current value of the AIPS_PACRE_TP3 field. */ 04003 #define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3)) 04004 04005 /*! @brief Format value for bitfield AIPS_PACRE_TP3. */ 04006 #define BF_AIPS_PACRE_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP3) & BM_AIPS_PACRE_TP3) 04007 04008 /*! @brief Set the TP3 field to a new value. */ 04009 #define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v)) 04010 /*@}*/ 04011 04012 /*! 04013 * @name Register AIPS_PACRE, field WP3[17] (RW) 04014 * 04015 * Determines whether the peripheral allows write accesss. When this bit is set 04016 * and a write access is attempted, access terminates with an error response and 04017 * no peripheral access initiates. 04018 * 04019 * Values: 04020 * - 0 - This peripheral allows write accesses. 04021 * - 1 - This peripheral is write protected. 04022 */ 04023 /*@{*/ 04024 #define BP_AIPS_PACRE_WP3 (17U) /*!< Bit position for AIPS_PACRE_WP3. */ 04025 #define BM_AIPS_PACRE_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRE_WP3. */ 04026 #define BS_AIPS_PACRE_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP3. */ 04027 04028 /*! @brief Read current value of the AIPS_PACRE_WP3 field. */ 04029 #define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3)) 04030 04031 /*! @brief Format value for bitfield AIPS_PACRE_WP3. */ 04032 #define BF_AIPS_PACRE_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP3) & BM_AIPS_PACRE_WP3) 04033 04034 /*! @brief Set the WP3 field to a new value. */ 04035 #define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v)) 04036 /*@}*/ 04037 04038 /*! 04039 * @name Register AIPS_PACRE, field SP3[18] (RW) 04040 * 04041 * Determines whether the peripheral requires supervisor privilege level for 04042 * accesses. When this field is set, the master privilege level must indicate the 04043 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04044 * must be set. If not, access terminates with an error response and no peripheral 04045 * access initiates. 04046 * 04047 * Values: 04048 * - 0 - This peripheral does not require supervisor privilege level for 04049 * accesses. 04050 * - 1 - This peripheral requires supervisor privilege level for accesses. 04051 */ 04052 /*@{*/ 04053 #define BP_AIPS_PACRE_SP3 (18U) /*!< Bit position for AIPS_PACRE_SP3. */ 04054 #define BM_AIPS_PACRE_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRE_SP3. */ 04055 #define BS_AIPS_PACRE_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP3. */ 04056 04057 /*! @brief Read current value of the AIPS_PACRE_SP3 field. */ 04058 #define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3)) 04059 04060 /*! @brief Format value for bitfield AIPS_PACRE_SP3. */ 04061 #define BF_AIPS_PACRE_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP3) & BM_AIPS_PACRE_SP3) 04062 04063 /*! @brief Set the SP3 field to a new value. */ 04064 #define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v)) 04065 /*@}*/ 04066 04067 /*! 04068 * @name Register AIPS_PACRE, field TP2[20] (RW) 04069 * 04070 * Determines whether the peripheral allows accesses from an untrusted master. 04071 * When this bit is set and an access is attempted by an untrusted master, the 04072 * access terminates with an error response and no peripheral access initiates. 04073 * 04074 * Values: 04075 * - 0 - Accesses from an untrusted master are allowed. 04076 * - 1 - Accesses from an untrusted master are not allowed. 04077 */ 04078 /*@{*/ 04079 #define BP_AIPS_PACRE_TP2 (20U) /*!< Bit position for AIPS_PACRE_TP2. */ 04080 #define BM_AIPS_PACRE_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRE_TP2. */ 04081 #define BS_AIPS_PACRE_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP2. */ 04082 04083 /*! @brief Read current value of the AIPS_PACRE_TP2 field. */ 04084 #define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2)) 04085 04086 /*! @brief Format value for bitfield AIPS_PACRE_TP2. */ 04087 #define BF_AIPS_PACRE_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP2) & BM_AIPS_PACRE_TP2) 04088 04089 /*! @brief Set the TP2 field to a new value. */ 04090 #define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v)) 04091 /*@}*/ 04092 04093 /*! 04094 * @name Register AIPS_PACRE, field WP2[21] (RW) 04095 * 04096 * Determines whether the peripheral allows write accesses. When this field is 04097 * set and a write access is attempted, access terminates with an error response 04098 * and no peripheral access initiates. 04099 * 04100 * Values: 04101 * - 0 - This peripheral allows write accesses. 04102 * - 1 - This peripheral is write protected. 04103 */ 04104 /*@{*/ 04105 #define BP_AIPS_PACRE_WP2 (21U) /*!< Bit position for AIPS_PACRE_WP2. */ 04106 #define BM_AIPS_PACRE_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRE_WP2. */ 04107 #define BS_AIPS_PACRE_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP2. */ 04108 04109 /*! @brief Read current value of the AIPS_PACRE_WP2 field. */ 04110 #define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2)) 04111 04112 /*! @brief Format value for bitfield AIPS_PACRE_WP2. */ 04113 #define BF_AIPS_PACRE_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP2) & BM_AIPS_PACRE_WP2) 04114 04115 /*! @brief Set the WP2 field to a new value. */ 04116 #define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v)) 04117 /*@}*/ 04118 04119 /*! 04120 * @name Register AIPS_PACRE, field SP2[22] (RW) 04121 * 04122 * Determines whether the peripheral requires supervisor privilege level for 04123 * access. When this bit is set, the master privilege level must indicate the 04124 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04125 * set. If not, access terminates with an error response and no peripheral access 04126 * initiates. 04127 * 04128 * Values: 04129 * - 0 - This peripheral does not require supervisor privilege level for 04130 * accesses. 04131 * - 1 - This peripheral requires supervisor privilege level for accesses. 04132 */ 04133 /*@{*/ 04134 #define BP_AIPS_PACRE_SP2 (22U) /*!< Bit position for AIPS_PACRE_SP2. */ 04135 #define BM_AIPS_PACRE_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRE_SP2. */ 04136 #define BS_AIPS_PACRE_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP2. */ 04137 04138 /*! @brief Read current value of the AIPS_PACRE_SP2 field. */ 04139 #define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2)) 04140 04141 /*! @brief Format value for bitfield AIPS_PACRE_SP2. */ 04142 #define BF_AIPS_PACRE_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP2) & BM_AIPS_PACRE_SP2) 04143 04144 /*! @brief Set the SP2 field to a new value. */ 04145 #define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v)) 04146 /*@}*/ 04147 04148 /*! 04149 * @name Register AIPS_PACRE, field TP1[24] (RW) 04150 * 04151 * Determines whether the peripheral allows accesses from an untrusted master. 04152 * When this field is set and an access is attempted by an untrusted master, the 04153 * access terminates with an error response and no peripheral access initiates. 04154 * 04155 * Values: 04156 * - 0 - Accesses from an untrusted master are allowed. 04157 * - 1 - Accesses from an untrusted master are not allowed. 04158 */ 04159 /*@{*/ 04160 #define BP_AIPS_PACRE_TP1 (24U) /*!< Bit position for AIPS_PACRE_TP1. */ 04161 #define BM_AIPS_PACRE_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRE_TP1. */ 04162 #define BS_AIPS_PACRE_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP1. */ 04163 04164 /*! @brief Read current value of the AIPS_PACRE_TP1 field. */ 04165 #define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1)) 04166 04167 /*! @brief Format value for bitfield AIPS_PACRE_TP1. */ 04168 #define BF_AIPS_PACRE_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP1) & BM_AIPS_PACRE_TP1) 04169 04170 /*! @brief Set the TP1 field to a new value. */ 04171 #define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v)) 04172 /*@}*/ 04173 04174 /*! 04175 * @name Register AIPS_PACRE, field WP1[25] (RW) 04176 * 04177 * Determines whether the peripheral allows write accesses. When this field is 04178 * set and a write access is attempted, access terminates with an error response 04179 * and no peripheral access initiates. 04180 * 04181 * Values: 04182 * - 0 - This peripheral allows write accesses. 04183 * - 1 - This peripheral is write protected. 04184 */ 04185 /*@{*/ 04186 #define BP_AIPS_PACRE_WP1 (25U) /*!< Bit position for AIPS_PACRE_WP1. */ 04187 #define BM_AIPS_PACRE_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRE_WP1. */ 04188 #define BS_AIPS_PACRE_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP1. */ 04189 04190 /*! @brief Read current value of the AIPS_PACRE_WP1 field. */ 04191 #define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1)) 04192 04193 /*! @brief Format value for bitfield AIPS_PACRE_WP1. */ 04194 #define BF_AIPS_PACRE_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP1) & BM_AIPS_PACRE_WP1) 04195 04196 /*! @brief Set the WP1 field to a new value. */ 04197 #define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v)) 04198 /*@}*/ 04199 04200 /*! 04201 * @name Register AIPS_PACRE, field SP1[26] (RW) 04202 * 04203 * Determines whether the peripheral requires supervisor privilege level for 04204 * access. When this field is set, the master privilege level must indicate the 04205 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 04206 * be set. If not, access terminates with an error response and no peripheral 04207 * access initiates. 04208 * 04209 * Values: 04210 * - 0 - This peripheral does not require supervisor privilege level for 04211 * accesses. 04212 * - 1 - This peripheral requires supervisor privilege level for accesses. 04213 */ 04214 /*@{*/ 04215 #define BP_AIPS_PACRE_SP1 (26U) /*!< Bit position for AIPS_PACRE_SP1. */ 04216 #define BM_AIPS_PACRE_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRE_SP1. */ 04217 #define BS_AIPS_PACRE_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP1. */ 04218 04219 /*! @brief Read current value of the AIPS_PACRE_SP1 field. */ 04220 #define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1)) 04221 04222 /*! @brief Format value for bitfield AIPS_PACRE_SP1. */ 04223 #define BF_AIPS_PACRE_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP1) & BM_AIPS_PACRE_SP1) 04224 04225 /*! @brief Set the SP1 field to a new value. */ 04226 #define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v)) 04227 /*@}*/ 04228 04229 /*! 04230 * @name Register AIPS_PACRE, field TP0[28] (RW) 04231 * 04232 * Determines whether the peripheral allows accesses from an untrusted master. 04233 * When this bit is set and an access is attempted by an untrusted master, the 04234 * access terminates with an error response and no peripheral access initiates. 04235 * 04236 * Values: 04237 * - 0 - Accesses from an untrusted master are allowed. 04238 * - 1 - Accesses from an untrusted master are not allowed. 04239 */ 04240 /*@{*/ 04241 #define BP_AIPS_PACRE_TP0 (28U) /*!< Bit position for AIPS_PACRE_TP0. */ 04242 #define BM_AIPS_PACRE_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRE_TP0. */ 04243 #define BS_AIPS_PACRE_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP0. */ 04244 04245 /*! @brief Read current value of the AIPS_PACRE_TP0 field. */ 04246 #define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0)) 04247 04248 /*! @brief Format value for bitfield AIPS_PACRE_TP0. */ 04249 #define BF_AIPS_PACRE_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP0) & BM_AIPS_PACRE_TP0) 04250 04251 /*! @brief Set the TP0 field to a new value. */ 04252 #define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v)) 04253 /*@}*/ 04254 04255 /*! 04256 * @name Register AIPS_PACRE, field WP0[29] (RW) 04257 * 04258 * Determines whether the peripheral allows write accesses. When this field is 04259 * set and a write access is attempted, access terminates with an error response 04260 * and no peripheral access initiates. 04261 * 04262 * Values: 04263 * - 0 - This peripheral allows write accesses. 04264 * - 1 - This peripheral is write protected. 04265 */ 04266 /*@{*/ 04267 #define BP_AIPS_PACRE_WP0 (29U) /*!< Bit position for AIPS_PACRE_WP0. */ 04268 #define BM_AIPS_PACRE_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRE_WP0. */ 04269 #define BS_AIPS_PACRE_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP0. */ 04270 04271 /*! @brief Read current value of the AIPS_PACRE_WP0 field. */ 04272 #define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0)) 04273 04274 /*! @brief Format value for bitfield AIPS_PACRE_WP0. */ 04275 #define BF_AIPS_PACRE_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP0) & BM_AIPS_PACRE_WP0) 04276 04277 /*! @brief Set the WP0 field to a new value. */ 04278 #define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v)) 04279 /*@}*/ 04280 04281 /*! 04282 * @name Register AIPS_PACRE, field SP0[30] (RW) 04283 * 04284 * Determines whether the peripheral requires supervisor privilege level for 04285 * accesses. When this field is set, the master privilege level must indicate the 04286 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04287 * must be set. If not, access terminates with an error response and no peripheral 04288 * access initiates. 04289 * 04290 * Values: 04291 * - 0 - This peripheral does not require supervisor privilege level for 04292 * accesses. 04293 * - 1 - This peripheral requires supervisor privilege level for accesses. 04294 */ 04295 /*@{*/ 04296 #define BP_AIPS_PACRE_SP0 (30U) /*!< Bit position for AIPS_PACRE_SP0. */ 04297 #define BM_AIPS_PACRE_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRE_SP0. */ 04298 #define BS_AIPS_PACRE_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP0. */ 04299 04300 /*! @brief Read current value of the AIPS_PACRE_SP0 field. */ 04301 #define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0)) 04302 04303 /*! @brief Format value for bitfield AIPS_PACRE_SP0. */ 04304 #define BF_AIPS_PACRE_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP0) & BM_AIPS_PACRE_SP0) 04305 04306 /*! @brief Set the SP0 field to a new value. */ 04307 #define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v)) 04308 /*@}*/ 04309 04310 /******************************************************************************* 04311 * HW_AIPS_PACRF - Peripheral Access Control Register 04312 ******************************************************************************/ 04313 04314 /*! 04315 * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) 04316 * 04317 * Reset value: 0x44444444U 04318 * 04319 * This section describes PACR registers E-P, which control peripheral slots 04320 * 32-127. See PACRPeripheral Access Control Register for the description of these 04321 * registers. 04322 */ 04323 typedef union _hw_aips_pacrf 04324 { 04325 uint32_t U; 04326 struct _hw_aips_pacrf_bitfields 04327 { 04328 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 04329 uint32_t WP7 : 1; /*!< [1] Write Protect */ 04330 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 04331 uint32_t RESERVED0 : 1; /*!< [3] */ 04332 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 04333 uint32_t WP6 : 1; /*!< [5] Write Protect */ 04334 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 04335 uint32_t RESERVED1 : 1; /*!< [7] */ 04336 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 04337 uint32_t WP5 : 1; /*!< [9] Write Protect */ 04338 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 04339 uint32_t RESERVED2 : 1; /*!< [11] */ 04340 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 04341 uint32_t WP4 : 1; /*!< [13] Write Protect */ 04342 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 04343 uint32_t RESERVED3 : 1; /*!< [15] */ 04344 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 04345 uint32_t WP3 : 1; /*!< [17] Write Protect */ 04346 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 04347 uint32_t RESERVED4 : 1; /*!< [19] */ 04348 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 04349 uint32_t WP2 : 1; /*!< [21] Write Protect */ 04350 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 04351 uint32_t RESERVED5 : 1; /*!< [23] */ 04352 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 04353 uint32_t WP1 : 1; /*!< [25] Write Protect */ 04354 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 04355 uint32_t RESERVED6 : 1; /*!< [27] */ 04356 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 04357 uint32_t WP0 : 1; /*!< [29] Write Protect */ 04358 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 04359 uint32_t RESERVED7 : 1; /*!< [31] */ 04360 } B; 04361 } hw_aips_pacrf_t; 04362 04363 /*! 04364 * @name Constants and macros for entire AIPS_PACRF register 04365 */ 04366 /*@{*/ 04367 #define HW_AIPS_PACRF_ADDR(x) ((x) + 0x44U) 04368 04369 #define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) 04370 #define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U) 04371 #define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v)) 04372 #define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) 04373 #define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) 04374 #define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) 04375 /*@}*/ 04376 04377 /* 04378 * Constants & macros for individual AIPS_PACRF bitfields 04379 */ 04380 04381 /*! 04382 * @name Register AIPS_PACRF, field TP7[0] (RW) 04383 * 04384 * Determines whether the peripheral allows accesses from an untrusted master. 04385 * When this field is set and an access is attempted by an untrusted master, the 04386 * access terminates with an error response and no peripheral access initiates. 04387 * 04388 * Values: 04389 * - 0 - Accesses from an untrusted master are allowed. 04390 * - 1 - Accesses from an untrusted master are not allowed. 04391 */ 04392 /*@{*/ 04393 #define BP_AIPS_PACRF_TP7 (0U) /*!< Bit position for AIPS_PACRF_TP7. */ 04394 #define BM_AIPS_PACRF_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRF_TP7. */ 04395 #define BS_AIPS_PACRF_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP7. */ 04396 04397 /*! @brief Read current value of the AIPS_PACRF_TP7 field. */ 04398 #define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7)) 04399 04400 /*! @brief Format value for bitfield AIPS_PACRF_TP7. */ 04401 #define BF_AIPS_PACRF_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP7) & BM_AIPS_PACRF_TP7) 04402 04403 /*! @brief Set the TP7 field to a new value. */ 04404 #define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v)) 04405 /*@}*/ 04406 04407 /*! 04408 * @name Register AIPS_PACRF, field WP7[1] (RW) 04409 * 04410 * Determines whether the peripheral allows write accesses. When this field is 04411 * set and a write access is attempted, access terminates with an error response 04412 * and no peripheral access initiates. 04413 * 04414 * Values: 04415 * - 0 - This peripheral allows write accesses. 04416 * - 1 - This peripheral is write protected. 04417 */ 04418 /*@{*/ 04419 #define BP_AIPS_PACRF_WP7 (1U) /*!< Bit position for AIPS_PACRF_WP7. */ 04420 #define BM_AIPS_PACRF_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRF_WP7. */ 04421 #define BS_AIPS_PACRF_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP7. */ 04422 04423 /*! @brief Read current value of the AIPS_PACRF_WP7 field. */ 04424 #define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7)) 04425 04426 /*! @brief Format value for bitfield AIPS_PACRF_WP7. */ 04427 #define BF_AIPS_PACRF_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP7) & BM_AIPS_PACRF_WP7) 04428 04429 /*! @brief Set the WP7 field to a new value. */ 04430 #define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v)) 04431 /*@}*/ 04432 04433 /*! 04434 * @name Register AIPS_PACRF, field SP7[2] (RW) 04435 * 04436 * Determines whether the peripheral requires supervisor privilege level for 04437 * accesses. When this field is set, the master privilege level must indicate the 04438 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04439 * must be set. If not, access terminates with an error response and no peripheral 04440 * access initiates. 04441 * 04442 * Values: 04443 * - 0 - This peripheral does not require supervisor privilege level for 04444 * accesses. 04445 * - 1 - This peripheral requires supervisor privilege level for accesses. 04446 */ 04447 /*@{*/ 04448 #define BP_AIPS_PACRF_SP7 (2U) /*!< Bit position for AIPS_PACRF_SP7. */ 04449 #define BM_AIPS_PACRF_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRF_SP7. */ 04450 #define BS_AIPS_PACRF_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP7. */ 04451 04452 /*! @brief Read current value of the AIPS_PACRF_SP7 field. */ 04453 #define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7)) 04454 04455 /*! @brief Format value for bitfield AIPS_PACRF_SP7. */ 04456 #define BF_AIPS_PACRF_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP7) & BM_AIPS_PACRF_SP7) 04457 04458 /*! @brief Set the SP7 field to a new value. */ 04459 #define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v)) 04460 /*@}*/ 04461 04462 /*! 04463 * @name Register AIPS_PACRF, field TP6[4] (RW) 04464 * 04465 * Determines whether the peripheral allows accesses from an untrusted master. 04466 * When this field is set and an access is attempted by an untrusted master, the 04467 * access terminates with an error response and no peripheral access initiates. 04468 * 04469 * Values: 04470 * - 0 - Accesses from an untrusted master are allowed. 04471 * - 1 - Accesses from an untrusted master are not allowed. 04472 */ 04473 /*@{*/ 04474 #define BP_AIPS_PACRF_TP6 (4U) /*!< Bit position for AIPS_PACRF_TP6. */ 04475 #define BM_AIPS_PACRF_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRF_TP6. */ 04476 #define BS_AIPS_PACRF_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP6. */ 04477 04478 /*! @brief Read current value of the AIPS_PACRF_TP6 field. */ 04479 #define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6)) 04480 04481 /*! @brief Format value for bitfield AIPS_PACRF_TP6. */ 04482 #define BF_AIPS_PACRF_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP6) & BM_AIPS_PACRF_TP6) 04483 04484 /*! @brief Set the TP6 field to a new value. */ 04485 #define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v)) 04486 /*@}*/ 04487 04488 /*! 04489 * @name Register AIPS_PACRF, field WP6[5] (RW) 04490 * 04491 * Determines whether the peripheral allows write accesses. When this field is 04492 * set and a write access is attempted, access terminates with an error response 04493 * and no peripheral access initiates. 04494 * 04495 * Values: 04496 * - 0 - This peripheral allows write accesses. 04497 * - 1 - This peripheral is write protected. 04498 */ 04499 /*@{*/ 04500 #define BP_AIPS_PACRF_WP6 (5U) /*!< Bit position for AIPS_PACRF_WP6. */ 04501 #define BM_AIPS_PACRF_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRF_WP6. */ 04502 #define BS_AIPS_PACRF_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP6. */ 04503 04504 /*! @brief Read current value of the AIPS_PACRF_WP6 field. */ 04505 #define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6)) 04506 04507 /*! @brief Format value for bitfield AIPS_PACRF_WP6. */ 04508 #define BF_AIPS_PACRF_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP6) & BM_AIPS_PACRF_WP6) 04509 04510 /*! @brief Set the WP6 field to a new value. */ 04511 #define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v)) 04512 /*@}*/ 04513 04514 /*! 04515 * @name Register AIPS_PACRF, field SP6[6] (RW) 04516 * 04517 * Determines whether the peripheral requires supervisor privilege level for 04518 * accesses. When this field is set, the master privilege level must indicate the 04519 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04520 * must be set. If not, access terminates with an error response and no peripheral 04521 * access initiates. 04522 * 04523 * Values: 04524 * - 0 - This peripheral does not require supervisor privilege level for 04525 * accesses. 04526 * - 1 - This peripheral requires supervisor privilege level for accesses. 04527 */ 04528 /*@{*/ 04529 #define BP_AIPS_PACRF_SP6 (6U) /*!< Bit position for AIPS_PACRF_SP6. */ 04530 #define BM_AIPS_PACRF_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRF_SP6. */ 04531 #define BS_AIPS_PACRF_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP6. */ 04532 04533 /*! @brief Read current value of the AIPS_PACRF_SP6 field. */ 04534 #define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6)) 04535 04536 /*! @brief Format value for bitfield AIPS_PACRF_SP6. */ 04537 #define BF_AIPS_PACRF_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP6) & BM_AIPS_PACRF_SP6) 04538 04539 /*! @brief Set the SP6 field to a new value. */ 04540 #define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v)) 04541 /*@}*/ 04542 04543 /*! 04544 * @name Register AIPS_PACRF, field TP5[8] (RW) 04545 * 04546 * Determines whether the peripheral allows accesses from an untrusted master. 04547 * When this field is set and an access is attempted by an untrusted master, the 04548 * access terminates with an error response and no peripheral access initiates. 04549 * 04550 * Values: 04551 * - 0 - Accesses from an untrusted master are allowed. 04552 * - 1 - Accesses from an untrusted master are not allowed. 04553 */ 04554 /*@{*/ 04555 #define BP_AIPS_PACRF_TP5 (8U) /*!< Bit position for AIPS_PACRF_TP5. */ 04556 #define BM_AIPS_PACRF_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRF_TP5. */ 04557 #define BS_AIPS_PACRF_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP5. */ 04558 04559 /*! @brief Read current value of the AIPS_PACRF_TP5 field. */ 04560 #define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5)) 04561 04562 /*! @brief Format value for bitfield AIPS_PACRF_TP5. */ 04563 #define BF_AIPS_PACRF_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP5) & BM_AIPS_PACRF_TP5) 04564 04565 /*! @brief Set the TP5 field to a new value. */ 04566 #define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v)) 04567 /*@}*/ 04568 04569 /*! 04570 * @name Register AIPS_PACRF, field WP5[9] (RW) 04571 * 04572 * Determines whether the peripheral allows write accesses. When this field is 04573 * set and a write access is attempted, access terminates with an error response 04574 * and no peripheral access initiates. 04575 * 04576 * Values: 04577 * - 0 - This peripheral allows write accesses. 04578 * - 1 - This peripheral is write protected. 04579 */ 04580 /*@{*/ 04581 #define BP_AIPS_PACRF_WP5 (9U) /*!< Bit position for AIPS_PACRF_WP5. */ 04582 #define BM_AIPS_PACRF_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRF_WP5. */ 04583 #define BS_AIPS_PACRF_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP5. */ 04584 04585 /*! @brief Read current value of the AIPS_PACRF_WP5 field. */ 04586 #define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5)) 04587 04588 /*! @brief Format value for bitfield AIPS_PACRF_WP5. */ 04589 #define BF_AIPS_PACRF_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP5) & BM_AIPS_PACRF_WP5) 04590 04591 /*! @brief Set the WP5 field to a new value. */ 04592 #define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v)) 04593 /*@}*/ 04594 04595 /*! 04596 * @name Register AIPS_PACRF, field SP5[10] (RW) 04597 * 04598 * Determines whether the peripheral requires supervisor privilege level for 04599 * accesses. When this field is set, the master privilege level must indicate the 04600 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04601 * must be set. If not, access terminates with an error response and no peripheral 04602 * access initiates. 04603 * 04604 * Values: 04605 * - 0 - This peripheral does not require supervisor privilege level for 04606 * accesses. 04607 * - 1 - This peripheral requires supervisor privilege level for accesses. 04608 */ 04609 /*@{*/ 04610 #define BP_AIPS_PACRF_SP5 (10U) /*!< Bit position for AIPS_PACRF_SP5. */ 04611 #define BM_AIPS_PACRF_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRF_SP5. */ 04612 #define BS_AIPS_PACRF_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP5. */ 04613 04614 /*! @brief Read current value of the AIPS_PACRF_SP5 field. */ 04615 #define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5)) 04616 04617 /*! @brief Format value for bitfield AIPS_PACRF_SP5. */ 04618 #define BF_AIPS_PACRF_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP5) & BM_AIPS_PACRF_SP5) 04619 04620 /*! @brief Set the SP5 field to a new value. */ 04621 #define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v)) 04622 /*@}*/ 04623 04624 /*! 04625 * @name Register AIPS_PACRF, field TP4[12] (RW) 04626 * 04627 * Determines whether the peripheral allows accesses from an untrusted master. 04628 * When this bit is set and an access is attempted by an untrusted master, the 04629 * access terminates with an error response and no peripheral access initiates. 04630 * 04631 * Values: 04632 * - 0 - Accesses from an untrusted master are allowed. 04633 * - 1 - Accesses from an untrusted master are not allowed. 04634 */ 04635 /*@{*/ 04636 #define BP_AIPS_PACRF_TP4 (12U) /*!< Bit position for AIPS_PACRF_TP4. */ 04637 #define BM_AIPS_PACRF_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRF_TP4. */ 04638 #define BS_AIPS_PACRF_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP4. */ 04639 04640 /*! @brief Read current value of the AIPS_PACRF_TP4 field. */ 04641 #define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4)) 04642 04643 /*! @brief Format value for bitfield AIPS_PACRF_TP4. */ 04644 #define BF_AIPS_PACRF_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP4) & BM_AIPS_PACRF_TP4) 04645 04646 /*! @brief Set the TP4 field to a new value. */ 04647 #define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v)) 04648 /*@}*/ 04649 04650 /*! 04651 * @name Register AIPS_PACRF, field WP4[13] (RW) 04652 * 04653 * Determines whether the peripheral allows write accesses. When this field is 04654 * set and a write access is attempted, access terminates with an error response 04655 * and no peripheral access initiates. 04656 * 04657 * Values: 04658 * - 0 - This peripheral allows write accesses. 04659 * - 1 - This peripheral is write protected. 04660 */ 04661 /*@{*/ 04662 #define BP_AIPS_PACRF_WP4 (13U) /*!< Bit position for AIPS_PACRF_WP4. */ 04663 #define BM_AIPS_PACRF_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRF_WP4. */ 04664 #define BS_AIPS_PACRF_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP4. */ 04665 04666 /*! @brief Read current value of the AIPS_PACRF_WP4 field. */ 04667 #define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4)) 04668 04669 /*! @brief Format value for bitfield AIPS_PACRF_WP4. */ 04670 #define BF_AIPS_PACRF_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP4) & BM_AIPS_PACRF_WP4) 04671 04672 /*! @brief Set the WP4 field to a new value. */ 04673 #define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v)) 04674 /*@}*/ 04675 04676 /*! 04677 * @name Register AIPS_PACRF, field SP4[14] (RW) 04678 * 04679 * Determines whether the peripheral requires supervisor privilege level for 04680 * access. When this bit is set, the master privilege level must indicate the 04681 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04682 * set. If not, access terminates with an error response and no peripheral access 04683 * initiates. 04684 * 04685 * Values: 04686 * - 0 - This peripheral does not require supervisor privilege level for 04687 * accesses. 04688 * - 1 - This peripheral requires supervisor privilege level for accesses. 04689 */ 04690 /*@{*/ 04691 #define BP_AIPS_PACRF_SP4 (14U) /*!< Bit position for AIPS_PACRF_SP4. */ 04692 #define BM_AIPS_PACRF_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRF_SP4. */ 04693 #define BS_AIPS_PACRF_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP4. */ 04694 04695 /*! @brief Read current value of the AIPS_PACRF_SP4 field. */ 04696 #define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4)) 04697 04698 /*! @brief Format value for bitfield AIPS_PACRF_SP4. */ 04699 #define BF_AIPS_PACRF_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP4) & BM_AIPS_PACRF_SP4) 04700 04701 /*! @brief Set the SP4 field to a new value. */ 04702 #define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v)) 04703 /*@}*/ 04704 04705 /*! 04706 * @name Register AIPS_PACRF, field TP3[16] (RW) 04707 * 04708 * Determines whether the peripheral allows accesses from an untrusted master. 04709 * When this field is set and an access is attempted by an untrusted master, the 04710 * access terminates with an error response and no peripheral access initiates. 04711 * 04712 * Values: 04713 * - 0 - Accesses from an untrusted master are allowed. 04714 * - 1 - Accesses from an untrusted master are not allowed. 04715 */ 04716 /*@{*/ 04717 #define BP_AIPS_PACRF_TP3 (16U) /*!< Bit position for AIPS_PACRF_TP3. */ 04718 #define BM_AIPS_PACRF_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRF_TP3. */ 04719 #define BS_AIPS_PACRF_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP3. */ 04720 04721 /*! @brief Read current value of the AIPS_PACRF_TP3 field. */ 04722 #define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3)) 04723 04724 /*! @brief Format value for bitfield AIPS_PACRF_TP3. */ 04725 #define BF_AIPS_PACRF_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP3) & BM_AIPS_PACRF_TP3) 04726 04727 /*! @brief Set the TP3 field to a new value. */ 04728 #define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v)) 04729 /*@}*/ 04730 04731 /*! 04732 * @name Register AIPS_PACRF, field WP3[17] (RW) 04733 * 04734 * Determines whether the peripheral allows write accesss. When this bit is set 04735 * and a write access is attempted, access terminates with an error response and 04736 * no peripheral access initiates. 04737 * 04738 * Values: 04739 * - 0 - This peripheral allows write accesses. 04740 * - 1 - This peripheral is write protected. 04741 */ 04742 /*@{*/ 04743 #define BP_AIPS_PACRF_WP3 (17U) /*!< Bit position for AIPS_PACRF_WP3. */ 04744 #define BM_AIPS_PACRF_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRF_WP3. */ 04745 #define BS_AIPS_PACRF_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP3. */ 04746 04747 /*! @brief Read current value of the AIPS_PACRF_WP3 field. */ 04748 #define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3)) 04749 04750 /*! @brief Format value for bitfield AIPS_PACRF_WP3. */ 04751 #define BF_AIPS_PACRF_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP3) & BM_AIPS_PACRF_WP3) 04752 04753 /*! @brief Set the WP3 field to a new value. */ 04754 #define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v)) 04755 /*@}*/ 04756 04757 /*! 04758 * @name Register AIPS_PACRF, field SP3[18] (RW) 04759 * 04760 * Determines whether the peripheral requires supervisor privilege level for 04761 * accesses. When this field is set, the master privilege level must indicate the 04762 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04763 * must be set. If not, access terminates with an error response and no peripheral 04764 * access initiates. 04765 * 04766 * Values: 04767 * - 0 - This peripheral does not require supervisor privilege level for 04768 * accesses. 04769 * - 1 - This peripheral requires supervisor privilege level for accesses. 04770 */ 04771 /*@{*/ 04772 #define BP_AIPS_PACRF_SP3 (18U) /*!< Bit position for AIPS_PACRF_SP3. */ 04773 #define BM_AIPS_PACRF_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRF_SP3. */ 04774 #define BS_AIPS_PACRF_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP3. */ 04775 04776 /*! @brief Read current value of the AIPS_PACRF_SP3 field. */ 04777 #define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3)) 04778 04779 /*! @brief Format value for bitfield AIPS_PACRF_SP3. */ 04780 #define BF_AIPS_PACRF_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP3) & BM_AIPS_PACRF_SP3) 04781 04782 /*! @brief Set the SP3 field to a new value. */ 04783 #define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v)) 04784 /*@}*/ 04785 04786 /*! 04787 * @name Register AIPS_PACRF, field TP2[20] (RW) 04788 * 04789 * Determines whether the peripheral allows accesses from an untrusted master. 04790 * When this bit is set and an access is attempted by an untrusted master, the 04791 * access terminates with an error response and no peripheral access initiates. 04792 * 04793 * Values: 04794 * - 0 - Accesses from an untrusted master are allowed. 04795 * - 1 - Accesses from an untrusted master are not allowed. 04796 */ 04797 /*@{*/ 04798 #define BP_AIPS_PACRF_TP2 (20U) /*!< Bit position for AIPS_PACRF_TP2. */ 04799 #define BM_AIPS_PACRF_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRF_TP2. */ 04800 #define BS_AIPS_PACRF_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP2. */ 04801 04802 /*! @brief Read current value of the AIPS_PACRF_TP2 field. */ 04803 #define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2)) 04804 04805 /*! @brief Format value for bitfield AIPS_PACRF_TP2. */ 04806 #define BF_AIPS_PACRF_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP2) & BM_AIPS_PACRF_TP2) 04807 04808 /*! @brief Set the TP2 field to a new value. */ 04809 #define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v)) 04810 /*@}*/ 04811 04812 /*! 04813 * @name Register AIPS_PACRF, field WP2[21] (RW) 04814 * 04815 * Determines whether the peripheral allows write accesses. When this field is 04816 * set and a write access is attempted, access terminates with an error response 04817 * and no peripheral access initiates. 04818 * 04819 * Values: 04820 * - 0 - This peripheral allows write accesses. 04821 * - 1 - This peripheral is write protected. 04822 */ 04823 /*@{*/ 04824 #define BP_AIPS_PACRF_WP2 (21U) /*!< Bit position for AIPS_PACRF_WP2. */ 04825 #define BM_AIPS_PACRF_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRF_WP2. */ 04826 #define BS_AIPS_PACRF_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP2. */ 04827 04828 /*! @brief Read current value of the AIPS_PACRF_WP2 field. */ 04829 #define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2)) 04830 04831 /*! @brief Format value for bitfield AIPS_PACRF_WP2. */ 04832 #define BF_AIPS_PACRF_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP2) & BM_AIPS_PACRF_WP2) 04833 04834 /*! @brief Set the WP2 field to a new value. */ 04835 #define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v)) 04836 /*@}*/ 04837 04838 /*! 04839 * @name Register AIPS_PACRF, field SP2[22] (RW) 04840 * 04841 * Determines whether the peripheral requires supervisor privilege level for 04842 * access. When this bit is set, the master privilege level must indicate the 04843 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04844 * set. If not, access terminates with an error response and no peripheral access 04845 * initiates. 04846 * 04847 * Values: 04848 * - 0 - This peripheral does not require supervisor privilege level for 04849 * accesses. 04850 * - 1 - This peripheral requires supervisor privilege level for accesses. 04851 */ 04852 /*@{*/ 04853 #define BP_AIPS_PACRF_SP2 (22U) /*!< Bit position for AIPS_PACRF_SP2. */ 04854 #define BM_AIPS_PACRF_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRF_SP2. */ 04855 #define BS_AIPS_PACRF_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP2. */ 04856 04857 /*! @brief Read current value of the AIPS_PACRF_SP2 field. */ 04858 #define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2)) 04859 04860 /*! @brief Format value for bitfield AIPS_PACRF_SP2. */ 04861 #define BF_AIPS_PACRF_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP2) & BM_AIPS_PACRF_SP2) 04862 04863 /*! @brief Set the SP2 field to a new value. */ 04864 #define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v)) 04865 /*@}*/ 04866 04867 /*! 04868 * @name Register AIPS_PACRF, field TP1[24] (RW) 04869 * 04870 * Determines whether the peripheral allows accesses from an untrusted master. 04871 * When this field is set and an access is attempted by an untrusted master, the 04872 * access terminates with an error response and no peripheral access initiates. 04873 * 04874 * Values: 04875 * - 0 - Accesses from an untrusted master are allowed. 04876 * - 1 - Accesses from an untrusted master are not allowed. 04877 */ 04878 /*@{*/ 04879 #define BP_AIPS_PACRF_TP1 (24U) /*!< Bit position for AIPS_PACRF_TP1. */ 04880 #define BM_AIPS_PACRF_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRF_TP1. */ 04881 #define BS_AIPS_PACRF_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP1. */ 04882 04883 /*! @brief Read current value of the AIPS_PACRF_TP1 field. */ 04884 #define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1)) 04885 04886 /*! @brief Format value for bitfield AIPS_PACRF_TP1. */ 04887 #define BF_AIPS_PACRF_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP1) & BM_AIPS_PACRF_TP1) 04888 04889 /*! @brief Set the TP1 field to a new value. */ 04890 #define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v)) 04891 /*@}*/ 04892 04893 /*! 04894 * @name Register AIPS_PACRF, field WP1[25] (RW) 04895 * 04896 * Determines whether the peripheral allows write accesses. When this field is 04897 * set and a write access is attempted, access terminates with an error response 04898 * and no peripheral access initiates. 04899 * 04900 * Values: 04901 * - 0 - This peripheral allows write accesses. 04902 * - 1 - This peripheral is write protected. 04903 */ 04904 /*@{*/ 04905 #define BP_AIPS_PACRF_WP1 (25U) /*!< Bit position for AIPS_PACRF_WP1. */ 04906 #define BM_AIPS_PACRF_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRF_WP1. */ 04907 #define BS_AIPS_PACRF_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP1. */ 04908 04909 /*! @brief Read current value of the AIPS_PACRF_WP1 field. */ 04910 #define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1)) 04911 04912 /*! @brief Format value for bitfield AIPS_PACRF_WP1. */ 04913 #define BF_AIPS_PACRF_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP1) & BM_AIPS_PACRF_WP1) 04914 04915 /*! @brief Set the WP1 field to a new value. */ 04916 #define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v)) 04917 /*@}*/ 04918 04919 /*! 04920 * @name Register AIPS_PACRF, field SP1[26] (RW) 04921 * 04922 * Determines whether the peripheral requires supervisor privilege level for 04923 * access. When this field is set, the master privilege level must indicate the 04924 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 04925 * be set. If not, access terminates with an error response and no peripheral 04926 * access initiates. 04927 * 04928 * Values: 04929 * - 0 - This peripheral does not require supervisor privilege level for 04930 * accesses. 04931 * - 1 - This peripheral requires supervisor privilege level for accesses. 04932 */ 04933 /*@{*/ 04934 #define BP_AIPS_PACRF_SP1 (26U) /*!< Bit position for AIPS_PACRF_SP1. */ 04935 #define BM_AIPS_PACRF_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRF_SP1. */ 04936 #define BS_AIPS_PACRF_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP1. */ 04937 04938 /*! @brief Read current value of the AIPS_PACRF_SP1 field. */ 04939 #define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1)) 04940 04941 /*! @brief Format value for bitfield AIPS_PACRF_SP1. */ 04942 #define BF_AIPS_PACRF_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP1) & BM_AIPS_PACRF_SP1) 04943 04944 /*! @brief Set the SP1 field to a new value. */ 04945 #define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v)) 04946 /*@}*/ 04947 04948 /*! 04949 * @name Register AIPS_PACRF, field TP0[28] (RW) 04950 * 04951 * Determines whether the peripheral allows accesses from an untrusted master. 04952 * When this bit is set and an access is attempted by an untrusted master, the 04953 * access terminates with an error response and no peripheral access initiates. 04954 * 04955 * Values: 04956 * - 0 - Accesses from an untrusted master are allowed. 04957 * - 1 - Accesses from an untrusted master are not allowed. 04958 */ 04959 /*@{*/ 04960 #define BP_AIPS_PACRF_TP0 (28U) /*!< Bit position for AIPS_PACRF_TP0. */ 04961 #define BM_AIPS_PACRF_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRF_TP0. */ 04962 #define BS_AIPS_PACRF_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP0. */ 04963 04964 /*! @brief Read current value of the AIPS_PACRF_TP0 field. */ 04965 #define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0)) 04966 04967 /*! @brief Format value for bitfield AIPS_PACRF_TP0. */ 04968 #define BF_AIPS_PACRF_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP0) & BM_AIPS_PACRF_TP0) 04969 04970 /*! @brief Set the TP0 field to a new value. */ 04971 #define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v)) 04972 /*@}*/ 04973 04974 /*! 04975 * @name Register AIPS_PACRF, field WP0[29] (RW) 04976 * 04977 * Determines whether the peripheral allows write accesses. When this field is 04978 * set and a write access is attempted, access terminates with an error response 04979 * and no peripheral access initiates. 04980 * 04981 * Values: 04982 * - 0 - This peripheral allows write accesses. 04983 * - 1 - This peripheral is write protected. 04984 */ 04985 /*@{*/ 04986 #define BP_AIPS_PACRF_WP0 (29U) /*!< Bit position for AIPS_PACRF_WP0. */ 04987 #define BM_AIPS_PACRF_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRF_WP0. */ 04988 #define BS_AIPS_PACRF_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP0. */ 04989 04990 /*! @brief Read current value of the AIPS_PACRF_WP0 field. */ 04991 #define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0)) 04992 04993 /*! @brief Format value for bitfield AIPS_PACRF_WP0. */ 04994 #define BF_AIPS_PACRF_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP0) & BM_AIPS_PACRF_WP0) 04995 04996 /*! @brief Set the WP0 field to a new value. */ 04997 #define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v)) 04998 /*@}*/ 04999 05000 /*! 05001 * @name Register AIPS_PACRF, field SP0[30] (RW) 05002 * 05003 * Determines whether the peripheral requires supervisor privilege level for 05004 * accesses. When this field is set, the master privilege level must indicate the 05005 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05006 * must be set. If not, access terminates with an error response and no peripheral 05007 * access initiates. 05008 * 05009 * Values: 05010 * - 0 - This peripheral does not require supervisor privilege level for 05011 * accesses. 05012 * - 1 - This peripheral requires supervisor privilege level for accesses. 05013 */ 05014 /*@{*/ 05015 #define BP_AIPS_PACRF_SP0 (30U) /*!< Bit position for AIPS_PACRF_SP0. */ 05016 #define BM_AIPS_PACRF_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRF_SP0. */ 05017 #define BS_AIPS_PACRF_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP0. */ 05018 05019 /*! @brief Read current value of the AIPS_PACRF_SP0 field. */ 05020 #define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0)) 05021 05022 /*! @brief Format value for bitfield AIPS_PACRF_SP0. */ 05023 #define BF_AIPS_PACRF_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP0) & BM_AIPS_PACRF_SP0) 05024 05025 /*! @brief Set the SP0 field to a new value. */ 05026 #define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v)) 05027 /*@}*/ 05028 05029 /******************************************************************************* 05030 * HW_AIPS_PACRG - Peripheral Access Control Register 05031 ******************************************************************************/ 05032 05033 /*! 05034 * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) 05035 * 05036 * Reset value: 0x44444444U 05037 * 05038 * This section describes PACR registers E-P, which control peripheral slots 05039 * 32-127. See PACRPeripheral Access Control Register for the description of these 05040 * registers. 05041 */ 05042 typedef union _hw_aips_pacrg 05043 { 05044 uint32_t U; 05045 struct _hw_aips_pacrg_bitfields 05046 { 05047 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 05048 uint32_t WP7 : 1; /*!< [1] Write Protect */ 05049 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 05050 uint32_t RESERVED0 : 1; /*!< [3] */ 05051 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 05052 uint32_t WP6 : 1; /*!< [5] Write Protect */ 05053 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 05054 uint32_t RESERVED1 : 1; /*!< [7] */ 05055 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 05056 uint32_t WP5 : 1; /*!< [9] Write Protect */ 05057 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 05058 uint32_t RESERVED2 : 1; /*!< [11] */ 05059 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 05060 uint32_t WP4 : 1; /*!< [13] Write Protect */ 05061 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 05062 uint32_t RESERVED3 : 1; /*!< [15] */ 05063 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 05064 uint32_t WP3 : 1; /*!< [17] Write Protect */ 05065 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 05066 uint32_t RESERVED4 : 1; /*!< [19] */ 05067 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 05068 uint32_t WP2 : 1; /*!< [21] Write Protect */ 05069 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 05070 uint32_t RESERVED5 : 1; /*!< [23] */ 05071 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 05072 uint32_t WP1 : 1; /*!< [25] Write Protect */ 05073 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 05074 uint32_t RESERVED6 : 1; /*!< [27] */ 05075 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 05076 uint32_t WP0 : 1; /*!< [29] Write Protect */ 05077 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 05078 uint32_t RESERVED7 : 1; /*!< [31] */ 05079 } B; 05080 } hw_aips_pacrg_t; 05081 05082 /*! 05083 * @name Constants and macros for entire AIPS_PACRG register 05084 */ 05085 /*@{*/ 05086 #define HW_AIPS_PACRG_ADDR(x) ((x) + 0x48U) 05087 05088 #define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) 05089 #define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U) 05090 #define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v)) 05091 #define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) 05092 #define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) 05093 #define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) 05094 /*@}*/ 05095 05096 /* 05097 * Constants & macros for individual AIPS_PACRG bitfields 05098 */ 05099 05100 /*! 05101 * @name Register AIPS_PACRG, field TP7[0] (RW) 05102 * 05103 * Determines whether the peripheral allows accesses from an untrusted master. 05104 * When this field is set and an access is attempted by an untrusted master, the 05105 * access terminates with an error response and no peripheral access initiates. 05106 * 05107 * Values: 05108 * - 0 - Accesses from an untrusted master are allowed. 05109 * - 1 - Accesses from an untrusted master are not allowed. 05110 */ 05111 /*@{*/ 05112 #define BP_AIPS_PACRG_TP7 (0U) /*!< Bit position for AIPS_PACRG_TP7. */ 05113 #define BM_AIPS_PACRG_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRG_TP7. */ 05114 #define BS_AIPS_PACRG_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP7. */ 05115 05116 /*! @brief Read current value of the AIPS_PACRG_TP7 field. */ 05117 #define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7)) 05118 05119 /*! @brief Format value for bitfield AIPS_PACRG_TP7. */ 05120 #define BF_AIPS_PACRG_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP7) & BM_AIPS_PACRG_TP7) 05121 05122 /*! @brief Set the TP7 field to a new value. */ 05123 #define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v)) 05124 /*@}*/ 05125 05126 /*! 05127 * @name Register AIPS_PACRG, field WP7[1] (RW) 05128 * 05129 * Determines whether the peripheral allows write accesses. When this field is 05130 * set and a write access is attempted, access terminates with an error response 05131 * and no peripheral access initiates. 05132 * 05133 * Values: 05134 * - 0 - This peripheral allows write accesses. 05135 * - 1 - This peripheral is write protected. 05136 */ 05137 /*@{*/ 05138 #define BP_AIPS_PACRG_WP7 (1U) /*!< Bit position for AIPS_PACRG_WP7. */ 05139 #define BM_AIPS_PACRG_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRG_WP7. */ 05140 #define BS_AIPS_PACRG_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP7. */ 05141 05142 /*! @brief Read current value of the AIPS_PACRG_WP7 field. */ 05143 #define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7)) 05144 05145 /*! @brief Format value for bitfield AIPS_PACRG_WP7. */ 05146 #define BF_AIPS_PACRG_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP7) & BM_AIPS_PACRG_WP7) 05147 05148 /*! @brief Set the WP7 field to a new value. */ 05149 #define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v)) 05150 /*@}*/ 05151 05152 /*! 05153 * @name Register AIPS_PACRG, field SP7[2] (RW) 05154 * 05155 * Determines whether the peripheral requires supervisor privilege level for 05156 * accesses. When this field is set, the master privilege level must indicate the 05157 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05158 * must be set. If not, access terminates with an error response and no peripheral 05159 * access initiates. 05160 * 05161 * Values: 05162 * - 0 - This peripheral does not require supervisor privilege level for 05163 * accesses. 05164 * - 1 - This peripheral requires supervisor privilege level for accesses. 05165 */ 05166 /*@{*/ 05167 #define BP_AIPS_PACRG_SP7 (2U) /*!< Bit position for AIPS_PACRG_SP7. */ 05168 #define BM_AIPS_PACRG_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRG_SP7. */ 05169 #define BS_AIPS_PACRG_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP7. */ 05170 05171 /*! @brief Read current value of the AIPS_PACRG_SP7 field. */ 05172 #define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7)) 05173 05174 /*! @brief Format value for bitfield AIPS_PACRG_SP7. */ 05175 #define BF_AIPS_PACRG_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP7) & BM_AIPS_PACRG_SP7) 05176 05177 /*! @brief Set the SP7 field to a new value. */ 05178 #define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v)) 05179 /*@}*/ 05180 05181 /*! 05182 * @name Register AIPS_PACRG, field TP6[4] (RW) 05183 * 05184 * Determines whether the peripheral allows accesses from an untrusted master. 05185 * When this field is set and an access is attempted by an untrusted master, the 05186 * access terminates with an error response and no peripheral access initiates. 05187 * 05188 * Values: 05189 * - 0 - Accesses from an untrusted master are allowed. 05190 * - 1 - Accesses from an untrusted master are not allowed. 05191 */ 05192 /*@{*/ 05193 #define BP_AIPS_PACRG_TP6 (4U) /*!< Bit position for AIPS_PACRG_TP6. */ 05194 #define BM_AIPS_PACRG_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRG_TP6. */ 05195 #define BS_AIPS_PACRG_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP6. */ 05196 05197 /*! @brief Read current value of the AIPS_PACRG_TP6 field. */ 05198 #define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6)) 05199 05200 /*! @brief Format value for bitfield AIPS_PACRG_TP6. */ 05201 #define BF_AIPS_PACRG_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP6) & BM_AIPS_PACRG_TP6) 05202 05203 /*! @brief Set the TP6 field to a new value. */ 05204 #define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v)) 05205 /*@}*/ 05206 05207 /*! 05208 * @name Register AIPS_PACRG, field WP6[5] (RW) 05209 * 05210 * Determines whether the peripheral allows write accesses. When this field is 05211 * set and a write access is attempted, access terminates with an error response 05212 * and no peripheral access initiates. 05213 * 05214 * Values: 05215 * - 0 - This peripheral allows write accesses. 05216 * - 1 - This peripheral is write protected. 05217 */ 05218 /*@{*/ 05219 #define BP_AIPS_PACRG_WP6 (5U) /*!< Bit position for AIPS_PACRG_WP6. */ 05220 #define BM_AIPS_PACRG_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRG_WP6. */ 05221 #define BS_AIPS_PACRG_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP6. */ 05222 05223 /*! @brief Read current value of the AIPS_PACRG_WP6 field. */ 05224 #define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6)) 05225 05226 /*! @brief Format value for bitfield AIPS_PACRG_WP6. */ 05227 #define BF_AIPS_PACRG_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP6) & BM_AIPS_PACRG_WP6) 05228 05229 /*! @brief Set the WP6 field to a new value. */ 05230 #define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v)) 05231 /*@}*/ 05232 05233 /*! 05234 * @name Register AIPS_PACRG, field SP6[6] (RW) 05235 * 05236 * Determines whether the peripheral requires supervisor privilege level for 05237 * accesses. When this field is set, the master privilege level must indicate the 05238 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05239 * must be set. If not, access terminates with an error response and no peripheral 05240 * access initiates. 05241 * 05242 * Values: 05243 * - 0 - This peripheral does not require supervisor privilege level for 05244 * accesses. 05245 * - 1 - This peripheral requires supervisor privilege level for accesses. 05246 */ 05247 /*@{*/ 05248 #define BP_AIPS_PACRG_SP6 (6U) /*!< Bit position for AIPS_PACRG_SP6. */ 05249 #define BM_AIPS_PACRG_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRG_SP6. */ 05250 #define BS_AIPS_PACRG_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP6. */ 05251 05252 /*! @brief Read current value of the AIPS_PACRG_SP6 field. */ 05253 #define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6)) 05254 05255 /*! @brief Format value for bitfield AIPS_PACRG_SP6. */ 05256 #define BF_AIPS_PACRG_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP6) & BM_AIPS_PACRG_SP6) 05257 05258 /*! @brief Set the SP6 field to a new value. */ 05259 #define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v)) 05260 /*@}*/ 05261 05262 /*! 05263 * @name Register AIPS_PACRG, field TP5[8] (RW) 05264 * 05265 * Determines whether the peripheral allows accesses from an untrusted master. 05266 * When this field is set and an access is attempted by an untrusted master, the 05267 * access terminates with an error response and no peripheral access initiates. 05268 * 05269 * Values: 05270 * - 0 - Accesses from an untrusted master are allowed. 05271 * - 1 - Accesses from an untrusted master are not allowed. 05272 */ 05273 /*@{*/ 05274 #define BP_AIPS_PACRG_TP5 (8U) /*!< Bit position for AIPS_PACRG_TP5. */ 05275 #define BM_AIPS_PACRG_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRG_TP5. */ 05276 #define BS_AIPS_PACRG_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP5. */ 05277 05278 /*! @brief Read current value of the AIPS_PACRG_TP5 field. */ 05279 #define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5)) 05280 05281 /*! @brief Format value for bitfield AIPS_PACRG_TP5. */ 05282 #define BF_AIPS_PACRG_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP5) & BM_AIPS_PACRG_TP5) 05283 05284 /*! @brief Set the TP5 field to a new value. */ 05285 #define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v)) 05286 /*@}*/ 05287 05288 /*! 05289 * @name Register AIPS_PACRG, field WP5[9] (RW) 05290 * 05291 * Determines whether the peripheral allows write accesses. When this field is 05292 * set and a write access is attempted, access terminates with an error response 05293 * and no peripheral access initiates. 05294 * 05295 * Values: 05296 * - 0 - This peripheral allows write accesses. 05297 * - 1 - This peripheral is write protected. 05298 */ 05299 /*@{*/ 05300 #define BP_AIPS_PACRG_WP5 (9U) /*!< Bit position for AIPS_PACRG_WP5. */ 05301 #define BM_AIPS_PACRG_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRG_WP5. */ 05302 #define BS_AIPS_PACRG_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP5. */ 05303 05304 /*! @brief Read current value of the AIPS_PACRG_WP5 field. */ 05305 #define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5)) 05306 05307 /*! @brief Format value for bitfield AIPS_PACRG_WP5. */ 05308 #define BF_AIPS_PACRG_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP5) & BM_AIPS_PACRG_WP5) 05309 05310 /*! @brief Set the WP5 field to a new value. */ 05311 #define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v)) 05312 /*@}*/ 05313 05314 /*! 05315 * @name Register AIPS_PACRG, field SP5[10] (RW) 05316 * 05317 * Determines whether the peripheral requires supervisor privilege level for 05318 * accesses. When this field is set, the master privilege level must indicate the 05319 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05320 * must be set. If not, access terminates with an error response and no peripheral 05321 * access initiates. 05322 * 05323 * Values: 05324 * - 0 - This peripheral does not require supervisor privilege level for 05325 * accesses. 05326 * - 1 - This peripheral requires supervisor privilege level for accesses. 05327 */ 05328 /*@{*/ 05329 #define BP_AIPS_PACRG_SP5 (10U) /*!< Bit position for AIPS_PACRG_SP5. */ 05330 #define BM_AIPS_PACRG_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRG_SP5. */ 05331 #define BS_AIPS_PACRG_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP5. */ 05332 05333 /*! @brief Read current value of the AIPS_PACRG_SP5 field. */ 05334 #define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5)) 05335 05336 /*! @brief Format value for bitfield AIPS_PACRG_SP5. */ 05337 #define BF_AIPS_PACRG_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP5) & BM_AIPS_PACRG_SP5) 05338 05339 /*! @brief Set the SP5 field to a new value. */ 05340 #define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v)) 05341 /*@}*/ 05342 05343 /*! 05344 * @name Register AIPS_PACRG, field TP4[12] (RW) 05345 * 05346 * Determines whether the peripheral allows accesses from an untrusted master. 05347 * When this bit is set and an access is attempted by an untrusted master, the 05348 * access terminates with an error response and no peripheral access initiates. 05349 * 05350 * Values: 05351 * - 0 - Accesses from an untrusted master are allowed. 05352 * - 1 - Accesses from an untrusted master are not allowed. 05353 */ 05354 /*@{*/ 05355 #define BP_AIPS_PACRG_TP4 (12U) /*!< Bit position for AIPS_PACRG_TP4. */ 05356 #define BM_AIPS_PACRG_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRG_TP4. */ 05357 #define BS_AIPS_PACRG_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP4. */ 05358 05359 /*! @brief Read current value of the AIPS_PACRG_TP4 field. */ 05360 #define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4)) 05361 05362 /*! @brief Format value for bitfield AIPS_PACRG_TP4. */ 05363 #define BF_AIPS_PACRG_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP4) & BM_AIPS_PACRG_TP4) 05364 05365 /*! @brief Set the TP4 field to a new value. */ 05366 #define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v)) 05367 /*@}*/ 05368 05369 /*! 05370 * @name Register AIPS_PACRG, field WP4[13] (RW) 05371 * 05372 * Determines whether the peripheral allows write accesses. When this field is 05373 * set and a write access is attempted, access terminates with an error response 05374 * and no peripheral access initiates. 05375 * 05376 * Values: 05377 * - 0 - This peripheral allows write accesses. 05378 * - 1 - This peripheral is write protected. 05379 */ 05380 /*@{*/ 05381 #define BP_AIPS_PACRG_WP4 (13U) /*!< Bit position for AIPS_PACRG_WP4. */ 05382 #define BM_AIPS_PACRG_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRG_WP4. */ 05383 #define BS_AIPS_PACRG_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP4. */ 05384 05385 /*! @brief Read current value of the AIPS_PACRG_WP4 field. */ 05386 #define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4)) 05387 05388 /*! @brief Format value for bitfield AIPS_PACRG_WP4. */ 05389 #define BF_AIPS_PACRG_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP4) & BM_AIPS_PACRG_WP4) 05390 05391 /*! @brief Set the WP4 field to a new value. */ 05392 #define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v)) 05393 /*@}*/ 05394 05395 /*! 05396 * @name Register AIPS_PACRG, field SP4[14] (RW) 05397 * 05398 * Determines whether the peripheral requires supervisor privilege level for 05399 * access. When this bit is set, the master privilege level must indicate the 05400 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 05401 * set. If not, access terminates with an error response and no peripheral access 05402 * initiates. 05403 * 05404 * Values: 05405 * - 0 - This peripheral does not require supervisor privilege level for 05406 * accesses. 05407 * - 1 - This peripheral requires supervisor privilege level for accesses. 05408 */ 05409 /*@{*/ 05410 #define BP_AIPS_PACRG_SP4 (14U) /*!< Bit position for AIPS_PACRG_SP4. */ 05411 #define BM_AIPS_PACRG_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRG_SP4. */ 05412 #define BS_AIPS_PACRG_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP4. */ 05413 05414 /*! @brief Read current value of the AIPS_PACRG_SP4 field. */ 05415 #define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4)) 05416 05417 /*! @brief Format value for bitfield AIPS_PACRG_SP4. */ 05418 #define BF_AIPS_PACRG_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP4) & BM_AIPS_PACRG_SP4) 05419 05420 /*! @brief Set the SP4 field to a new value. */ 05421 #define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v)) 05422 /*@}*/ 05423 05424 /*! 05425 * @name Register AIPS_PACRG, field TP3[16] (RW) 05426 * 05427 * Determines whether the peripheral allows accesses from an untrusted master. 05428 * When this field is set and an access is attempted by an untrusted master, the 05429 * access terminates with an error response and no peripheral access initiates. 05430 * 05431 * Values: 05432 * - 0 - Accesses from an untrusted master are allowed. 05433 * - 1 - Accesses from an untrusted master are not allowed. 05434 */ 05435 /*@{*/ 05436 #define BP_AIPS_PACRG_TP3 (16U) /*!< Bit position for AIPS_PACRG_TP3. */ 05437 #define BM_AIPS_PACRG_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRG_TP3. */ 05438 #define BS_AIPS_PACRG_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP3. */ 05439 05440 /*! @brief Read current value of the AIPS_PACRG_TP3 field. */ 05441 #define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3)) 05442 05443 /*! @brief Format value for bitfield AIPS_PACRG_TP3. */ 05444 #define BF_AIPS_PACRG_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP3) & BM_AIPS_PACRG_TP3) 05445 05446 /*! @brief Set the TP3 field to a new value. */ 05447 #define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v)) 05448 /*@}*/ 05449 05450 /*! 05451 * @name Register AIPS_PACRG, field WP3[17] (RW) 05452 * 05453 * Determines whether the peripheral allows write accesss. When this bit is set 05454 * and a write access is attempted, access terminates with an error response and 05455 * no peripheral access initiates. 05456 * 05457 * Values: 05458 * - 0 - This peripheral allows write accesses. 05459 * - 1 - This peripheral is write protected. 05460 */ 05461 /*@{*/ 05462 #define BP_AIPS_PACRG_WP3 (17U) /*!< Bit position for AIPS_PACRG_WP3. */ 05463 #define BM_AIPS_PACRG_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRG_WP3. */ 05464 #define BS_AIPS_PACRG_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP3. */ 05465 05466 /*! @brief Read current value of the AIPS_PACRG_WP3 field. */ 05467 #define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3)) 05468 05469 /*! @brief Format value for bitfield AIPS_PACRG_WP3. */ 05470 #define BF_AIPS_PACRG_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP3) & BM_AIPS_PACRG_WP3) 05471 05472 /*! @brief Set the WP3 field to a new value. */ 05473 #define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v)) 05474 /*@}*/ 05475 05476 /*! 05477 * @name Register AIPS_PACRG, field SP3[18] (RW) 05478 * 05479 * Determines whether the peripheral requires supervisor privilege level for 05480 * accesses. When this field is set, the master privilege level must indicate the 05481 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05482 * must be set. If not, access terminates with an error response and no peripheral 05483 * access initiates. 05484 * 05485 * Values: 05486 * - 0 - This peripheral does not require supervisor privilege level for 05487 * accesses. 05488 * - 1 - This peripheral requires supervisor privilege level for accesses. 05489 */ 05490 /*@{*/ 05491 #define BP_AIPS_PACRG_SP3 (18U) /*!< Bit position for AIPS_PACRG_SP3. */ 05492 #define BM_AIPS_PACRG_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRG_SP3. */ 05493 #define BS_AIPS_PACRG_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP3. */ 05494 05495 /*! @brief Read current value of the AIPS_PACRG_SP3 field. */ 05496 #define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3)) 05497 05498 /*! @brief Format value for bitfield AIPS_PACRG_SP3. */ 05499 #define BF_AIPS_PACRG_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP3) & BM_AIPS_PACRG_SP3) 05500 05501 /*! @brief Set the SP3 field to a new value. */ 05502 #define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v)) 05503 /*@}*/ 05504 05505 /*! 05506 * @name Register AIPS_PACRG, field TP2[20] (RW) 05507 * 05508 * Determines whether the peripheral allows accesses from an untrusted master. 05509 * When this bit is set and an access is attempted by an untrusted master, the 05510 * access terminates with an error response and no peripheral access initiates. 05511 * 05512 * Values: 05513 * - 0 - Accesses from an untrusted master are allowed. 05514 * - 1 - Accesses from an untrusted master are not allowed. 05515 */ 05516 /*@{*/ 05517 #define BP_AIPS_PACRG_TP2 (20U) /*!< Bit position for AIPS_PACRG_TP2. */ 05518 #define BM_AIPS_PACRG_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRG_TP2. */ 05519 #define BS_AIPS_PACRG_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP2. */ 05520 05521 /*! @brief Read current value of the AIPS_PACRG_TP2 field. */ 05522 #define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2)) 05523 05524 /*! @brief Format value for bitfield AIPS_PACRG_TP2. */ 05525 #define BF_AIPS_PACRG_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP2) & BM_AIPS_PACRG_TP2) 05526 05527 /*! @brief Set the TP2 field to a new value. */ 05528 #define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v)) 05529 /*@}*/ 05530 05531 /*! 05532 * @name Register AIPS_PACRG, field WP2[21] (RW) 05533 * 05534 * Determines whether the peripheral allows write accesses. When this field is 05535 * set and a write access is attempted, access terminates with an error response 05536 * and no peripheral access initiates. 05537 * 05538 * Values: 05539 * - 0 - This peripheral allows write accesses. 05540 * - 1 - This peripheral is write protected. 05541 */ 05542 /*@{*/ 05543 #define BP_AIPS_PACRG_WP2 (21U) /*!< Bit position for AIPS_PACRG_WP2. */ 05544 #define BM_AIPS_PACRG_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRG_WP2. */ 05545 #define BS_AIPS_PACRG_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP2. */ 05546 05547 /*! @brief Read current value of the AIPS_PACRG_WP2 field. */ 05548 #define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2)) 05549 05550 /*! @brief Format value for bitfield AIPS_PACRG_WP2. */ 05551 #define BF_AIPS_PACRG_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP2) & BM_AIPS_PACRG_WP2) 05552 05553 /*! @brief Set the WP2 field to a new value. */ 05554 #define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v)) 05555 /*@}*/ 05556 05557 /*! 05558 * @name Register AIPS_PACRG, field SP2[22] (RW) 05559 * 05560 * Determines whether the peripheral requires supervisor privilege level for 05561 * access. When this bit is set, the master privilege level must indicate the 05562 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 05563 * set. If not, access terminates with an error response and no peripheral access 05564 * initiates. 05565 * 05566 * Values: 05567 * - 0 - This peripheral does not require supervisor privilege level for 05568 * accesses. 05569 * - 1 - This peripheral requires supervisor privilege level for accesses. 05570 */ 05571 /*@{*/ 05572 #define BP_AIPS_PACRG_SP2 (22U) /*!< Bit position for AIPS_PACRG_SP2. */ 05573 #define BM_AIPS_PACRG_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRG_SP2. */ 05574 #define BS_AIPS_PACRG_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP2. */ 05575 05576 /*! @brief Read current value of the AIPS_PACRG_SP2 field. */ 05577 #define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2)) 05578 05579 /*! @brief Format value for bitfield AIPS_PACRG_SP2. */ 05580 #define BF_AIPS_PACRG_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP2) & BM_AIPS_PACRG_SP2) 05581 05582 /*! @brief Set the SP2 field to a new value. */ 05583 #define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v)) 05584 /*@}*/ 05585 05586 /*! 05587 * @name Register AIPS_PACRG, field TP1[24] (RW) 05588 * 05589 * Determines whether the peripheral allows accesses from an untrusted master. 05590 * When this field is set and an access is attempted by an untrusted master, the 05591 * access terminates with an error response and no peripheral access initiates. 05592 * 05593 * Values: 05594 * - 0 - Accesses from an untrusted master are allowed. 05595 * - 1 - Accesses from an untrusted master are not allowed. 05596 */ 05597 /*@{*/ 05598 #define BP_AIPS_PACRG_TP1 (24U) /*!< Bit position for AIPS_PACRG_TP1. */ 05599 #define BM_AIPS_PACRG_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRG_TP1. */ 05600 #define BS_AIPS_PACRG_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP1. */ 05601 05602 /*! @brief Read current value of the AIPS_PACRG_TP1 field. */ 05603 #define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1)) 05604 05605 /*! @brief Format value for bitfield AIPS_PACRG_TP1. */ 05606 #define BF_AIPS_PACRG_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP1) & BM_AIPS_PACRG_TP1) 05607 05608 /*! @brief Set the TP1 field to a new value. */ 05609 #define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v)) 05610 /*@}*/ 05611 05612 /*! 05613 * @name Register AIPS_PACRG, field WP1[25] (RW) 05614 * 05615 * Determines whether the peripheral allows write accesses. When this field is 05616 * set and a write access is attempted, access terminates with an error response 05617 * and no peripheral access initiates. 05618 * 05619 * Values: 05620 * - 0 - This peripheral allows write accesses. 05621 * - 1 - This peripheral is write protected. 05622 */ 05623 /*@{*/ 05624 #define BP_AIPS_PACRG_WP1 (25U) /*!< Bit position for AIPS_PACRG_WP1. */ 05625 #define BM_AIPS_PACRG_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRG_WP1. */ 05626 #define BS_AIPS_PACRG_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP1. */ 05627 05628 /*! @brief Read current value of the AIPS_PACRG_WP1 field. */ 05629 #define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1)) 05630 05631 /*! @brief Format value for bitfield AIPS_PACRG_WP1. */ 05632 #define BF_AIPS_PACRG_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP1) & BM_AIPS_PACRG_WP1) 05633 05634 /*! @brief Set the WP1 field to a new value. */ 05635 #define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v)) 05636 /*@}*/ 05637 05638 /*! 05639 * @name Register AIPS_PACRG, field SP1[26] (RW) 05640 * 05641 * Determines whether the peripheral requires supervisor privilege level for 05642 * access. When this field is set, the master privilege level must indicate the 05643 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 05644 * be set. If not, access terminates with an error response and no peripheral 05645 * access initiates. 05646 * 05647 * Values: 05648 * - 0 - This peripheral does not require supervisor privilege level for 05649 * accesses. 05650 * - 1 - This peripheral requires supervisor privilege level for accesses. 05651 */ 05652 /*@{*/ 05653 #define BP_AIPS_PACRG_SP1 (26U) /*!< Bit position for AIPS_PACRG_SP1. */ 05654 #define BM_AIPS_PACRG_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRG_SP1. */ 05655 #define BS_AIPS_PACRG_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP1. */ 05656 05657 /*! @brief Read current value of the AIPS_PACRG_SP1 field. */ 05658 #define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1)) 05659 05660 /*! @brief Format value for bitfield AIPS_PACRG_SP1. */ 05661 #define BF_AIPS_PACRG_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP1) & BM_AIPS_PACRG_SP1) 05662 05663 /*! @brief Set the SP1 field to a new value. */ 05664 #define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v)) 05665 /*@}*/ 05666 05667 /*! 05668 * @name Register AIPS_PACRG, field TP0[28] (RW) 05669 * 05670 * Determines whether the peripheral allows accesses from an untrusted master. 05671 * When this bit is set and an access is attempted by an untrusted master, the 05672 * access terminates with an error response and no peripheral access initiates. 05673 * 05674 * Values: 05675 * - 0 - Accesses from an untrusted master are allowed. 05676 * - 1 - Accesses from an untrusted master are not allowed. 05677 */ 05678 /*@{*/ 05679 #define BP_AIPS_PACRG_TP0 (28U) /*!< Bit position for AIPS_PACRG_TP0. */ 05680 #define BM_AIPS_PACRG_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRG_TP0. */ 05681 #define BS_AIPS_PACRG_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP0. */ 05682 05683 /*! @brief Read current value of the AIPS_PACRG_TP0 field. */ 05684 #define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0)) 05685 05686 /*! @brief Format value for bitfield AIPS_PACRG_TP0. */ 05687 #define BF_AIPS_PACRG_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP0) & BM_AIPS_PACRG_TP0) 05688 05689 /*! @brief Set the TP0 field to a new value. */ 05690 #define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v)) 05691 /*@}*/ 05692 05693 /*! 05694 * @name Register AIPS_PACRG, field WP0[29] (RW) 05695 * 05696 * Determines whether the peripheral allows write accesses. When this field is 05697 * set and a write access is attempted, access terminates with an error response 05698 * and no peripheral access initiates. 05699 * 05700 * Values: 05701 * - 0 - This peripheral allows write accesses. 05702 * - 1 - This peripheral is write protected. 05703 */ 05704 /*@{*/ 05705 #define BP_AIPS_PACRG_WP0 (29U) /*!< Bit position for AIPS_PACRG_WP0. */ 05706 #define BM_AIPS_PACRG_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRG_WP0. */ 05707 #define BS_AIPS_PACRG_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP0. */ 05708 05709 /*! @brief Read current value of the AIPS_PACRG_WP0 field. */ 05710 #define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0)) 05711 05712 /*! @brief Format value for bitfield AIPS_PACRG_WP0. */ 05713 #define BF_AIPS_PACRG_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP0) & BM_AIPS_PACRG_WP0) 05714 05715 /*! @brief Set the WP0 field to a new value. */ 05716 #define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v)) 05717 /*@}*/ 05718 05719 /*! 05720 * @name Register AIPS_PACRG, field SP0[30] (RW) 05721 * 05722 * Determines whether the peripheral requires supervisor privilege level for 05723 * accesses. When this field is set, the master privilege level must indicate the 05724 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05725 * must be set. If not, access terminates with an error response and no peripheral 05726 * access initiates. 05727 * 05728 * Values: 05729 * - 0 - This peripheral does not require supervisor privilege level for 05730 * accesses. 05731 * - 1 - This peripheral requires supervisor privilege level for accesses. 05732 */ 05733 /*@{*/ 05734 #define BP_AIPS_PACRG_SP0 (30U) /*!< Bit position for AIPS_PACRG_SP0. */ 05735 #define BM_AIPS_PACRG_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRG_SP0. */ 05736 #define BS_AIPS_PACRG_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP0. */ 05737 05738 /*! @brief Read current value of the AIPS_PACRG_SP0 field. */ 05739 #define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0)) 05740 05741 /*! @brief Format value for bitfield AIPS_PACRG_SP0. */ 05742 #define BF_AIPS_PACRG_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP0) & BM_AIPS_PACRG_SP0) 05743 05744 /*! @brief Set the SP0 field to a new value. */ 05745 #define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v)) 05746 /*@}*/ 05747 05748 /******************************************************************************* 05749 * HW_AIPS_PACRH - Peripheral Access Control Register 05750 ******************************************************************************/ 05751 05752 /*! 05753 * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) 05754 * 05755 * Reset value: 0x44444444U 05756 * 05757 * This section describes PACR registers E-P, which control peripheral slots 05758 * 32-127. See PACRPeripheral Access Control Register for the description of these 05759 * registers. 05760 */ 05761 typedef union _hw_aips_pacrh 05762 { 05763 uint32_t U; 05764 struct _hw_aips_pacrh_bitfields 05765 { 05766 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 05767 uint32_t WP7 : 1; /*!< [1] Write Protect */ 05768 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 05769 uint32_t RESERVED0 : 1; /*!< [3] */ 05770 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 05771 uint32_t WP6 : 1; /*!< [5] Write Protect */ 05772 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 05773 uint32_t RESERVED1 : 1; /*!< [7] */ 05774 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 05775 uint32_t WP5 : 1; /*!< [9] Write Protect */ 05776 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 05777 uint32_t RESERVED2 : 1; /*!< [11] */ 05778 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 05779 uint32_t WP4 : 1; /*!< [13] Write Protect */ 05780 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 05781 uint32_t RESERVED3 : 1; /*!< [15] */ 05782 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 05783 uint32_t WP3 : 1; /*!< [17] Write Protect */ 05784 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 05785 uint32_t RESERVED4 : 1; /*!< [19] */ 05786 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 05787 uint32_t WP2 : 1; /*!< [21] Write Protect */ 05788 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 05789 uint32_t RESERVED5 : 1; /*!< [23] */ 05790 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 05791 uint32_t WP1 : 1; /*!< [25] Write Protect */ 05792 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 05793 uint32_t RESERVED6 : 1; /*!< [27] */ 05794 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 05795 uint32_t WP0 : 1; /*!< [29] Write Protect */ 05796 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 05797 uint32_t RESERVED7 : 1; /*!< [31] */ 05798 } B; 05799 } hw_aips_pacrh_t; 05800 05801 /*! 05802 * @name Constants and macros for entire AIPS_PACRH register 05803 */ 05804 /*@{*/ 05805 #define HW_AIPS_PACRH_ADDR(x) ((x) + 0x4CU) 05806 05807 #define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) 05808 #define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U) 05809 #define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v)) 05810 #define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) 05811 #define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) 05812 #define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) 05813 /*@}*/ 05814 05815 /* 05816 * Constants & macros for individual AIPS_PACRH bitfields 05817 */ 05818 05819 /*! 05820 * @name Register AIPS_PACRH, field TP7[0] (RW) 05821 * 05822 * Determines whether the peripheral allows accesses from an untrusted master. 05823 * When this field is set and an access is attempted by an untrusted master, the 05824 * access terminates with an error response and no peripheral access initiates. 05825 * 05826 * Values: 05827 * - 0 - Accesses from an untrusted master are allowed. 05828 * - 1 - Accesses from an untrusted master are not allowed. 05829 */ 05830 /*@{*/ 05831 #define BP_AIPS_PACRH_TP7 (0U) /*!< Bit position for AIPS_PACRH_TP7. */ 05832 #define BM_AIPS_PACRH_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRH_TP7. */ 05833 #define BS_AIPS_PACRH_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP7. */ 05834 05835 /*! @brief Read current value of the AIPS_PACRH_TP7 field. */ 05836 #define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7)) 05837 05838 /*! @brief Format value for bitfield AIPS_PACRH_TP7. */ 05839 #define BF_AIPS_PACRH_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP7) & BM_AIPS_PACRH_TP7) 05840 05841 /*! @brief Set the TP7 field to a new value. */ 05842 #define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v)) 05843 /*@}*/ 05844 05845 /*! 05846 * @name Register AIPS_PACRH, field WP7[1] (RW) 05847 * 05848 * Determines whether the peripheral allows write accesses. When this field is 05849 * set and a write access is attempted, access terminates with an error response 05850 * and no peripheral access initiates. 05851 * 05852 * Values: 05853 * - 0 - This peripheral allows write accesses. 05854 * - 1 - This peripheral is write protected. 05855 */ 05856 /*@{*/ 05857 #define BP_AIPS_PACRH_WP7 (1U) /*!< Bit position for AIPS_PACRH_WP7. */ 05858 #define BM_AIPS_PACRH_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRH_WP7. */ 05859 #define BS_AIPS_PACRH_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP7. */ 05860 05861 /*! @brief Read current value of the AIPS_PACRH_WP7 field. */ 05862 #define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7)) 05863 05864 /*! @brief Format value for bitfield AIPS_PACRH_WP7. */ 05865 #define BF_AIPS_PACRH_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP7) & BM_AIPS_PACRH_WP7) 05866 05867 /*! @brief Set the WP7 field to a new value. */ 05868 #define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v)) 05869 /*@}*/ 05870 05871 /*! 05872 * @name Register AIPS_PACRH, field SP7[2] (RW) 05873 * 05874 * Determines whether the peripheral requires supervisor privilege level for 05875 * accesses. When this field is set, the master privilege level must indicate the 05876 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05877 * must be set. If not, access terminates with an error response and no peripheral 05878 * access initiates. 05879 * 05880 * Values: 05881 * - 0 - This peripheral does not require supervisor privilege level for 05882 * accesses. 05883 * - 1 - This peripheral requires supervisor privilege level for accesses. 05884 */ 05885 /*@{*/ 05886 #define BP_AIPS_PACRH_SP7 (2U) /*!< Bit position for AIPS_PACRH_SP7. */ 05887 #define BM_AIPS_PACRH_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRH_SP7. */ 05888 #define BS_AIPS_PACRH_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP7. */ 05889 05890 /*! @brief Read current value of the AIPS_PACRH_SP7 field. */ 05891 #define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7)) 05892 05893 /*! @brief Format value for bitfield AIPS_PACRH_SP7. */ 05894 #define BF_AIPS_PACRH_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP7) & BM_AIPS_PACRH_SP7) 05895 05896 /*! @brief Set the SP7 field to a new value. */ 05897 #define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v)) 05898 /*@}*/ 05899 05900 /*! 05901 * @name Register AIPS_PACRH, field TP6[4] (RW) 05902 * 05903 * Determines whether the peripheral allows accesses from an untrusted master. 05904 * When this field is set and an access is attempted by an untrusted master, the 05905 * access terminates with an error response and no peripheral access initiates. 05906 * 05907 * Values: 05908 * - 0 - Accesses from an untrusted master are allowed. 05909 * - 1 - Accesses from an untrusted master are not allowed. 05910 */ 05911 /*@{*/ 05912 #define BP_AIPS_PACRH_TP6 (4U) /*!< Bit position for AIPS_PACRH_TP6. */ 05913 #define BM_AIPS_PACRH_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRH_TP6. */ 05914 #define BS_AIPS_PACRH_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP6. */ 05915 05916 /*! @brief Read current value of the AIPS_PACRH_TP6 field. */ 05917 #define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6)) 05918 05919 /*! @brief Format value for bitfield AIPS_PACRH_TP6. */ 05920 #define BF_AIPS_PACRH_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP6) & BM_AIPS_PACRH_TP6) 05921 05922 /*! @brief Set the TP6 field to a new value. */ 05923 #define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v)) 05924 /*@}*/ 05925 05926 /*! 05927 * @name Register AIPS_PACRH, field WP6[5] (RW) 05928 * 05929 * Determines whether the peripheral allows write accesses. When this field is 05930 * set and a write access is attempted, access terminates with an error response 05931 * and no peripheral access initiates. 05932 * 05933 * Values: 05934 * - 0 - This peripheral allows write accesses. 05935 * - 1 - This peripheral is write protected. 05936 */ 05937 /*@{*/ 05938 #define BP_AIPS_PACRH_WP6 (5U) /*!< Bit position for AIPS_PACRH_WP6. */ 05939 #define BM_AIPS_PACRH_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRH_WP6. */ 05940 #define BS_AIPS_PACRH_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP6. */ 05941 05942 /*! @brief Read current value of the AIPS_PACRH_WP6 field. */ 05943 #define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6)) 05944 05945 /*! @brief Format value for bitfield AIPS_PACRH_WP6. */ 05946 #define BF_AIPS_PACRH_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP6) & BM_AIPS_PACRH_WP6) 05947 05948 /*! @brief Set the WP6 field to a new value. */ 05949 #define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v)) 05950 /*@}*/ 05951 05952 /*! 05953 * @name Register AIPS_PACRH, field SP6[6] (RW) 05954 * 05955 * Determines whether the peripheral requires supervisor privilege level for 05956 * accesses. When this field is set, the master privilege level must indicate the 05957 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05958 * must be set. If not, access terminates with an error response and no peripheral 05959 * access initiates. 05960 * 05961 * Values: 05962 * - 0 - This peripheral does not require supervisor privilege level for 05963 * accesses. 05964 * - 1 - This peripheral requires supervisor privilege level for accesses. 05965 */ 05966 /*@{*/ 05967 #define BP_AIPS_PACRH_SP6 (6U) /*!< Bit position for AIPS_PACRH_SP6. */ 05968 #define BM_AIPS_PACRH_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRH_SP6. */ 05969 #define BS_AIPS_PACRH_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP6. */ 05970 05971 /*! @brief Read current value of the AIPS_PACRH_SP6 field. */ 05972 #define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6)) 05973 05974 /*! @brief Format value for bitfield AIPS_PACRH_SP6. */ 05975 #define BF_AIPS_PACRH_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP6) & BM_AIPS_PACRH_SP6) 05976 05977 /*! @brief Set the SP6 field to a new value. */ 05978 #define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v)) 05979 /*@}*/ 05980 05981 /*! 05982 * @name Register AIPS_PACRH, field TP5[8] (RW) 05983 * 05984 * Determines whether the peripheral allows accesses from an untrusted master. 05985 * When this field is set and an access is attempted by an untrusted master, the 05986 * access terminates with an error response and no peripheral access initiates. 05987 * 05988 * Values: 05989 * - 0 - Accesses from an untrusted master are allowed. 05990 * - 1 - Accesses from an untrusted master are not allowed. 05991 */ 05992 /*@{*/ 05993 #define BP_AIPS_PACRH_TP5 (8U) /*!< Bit position for AIPS_PACRH_TP5. */ 05994 #define BM_AIPS_PACRH_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRH_TP5. */ 05995 #define BS_AIPS_PACRH_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP5. */ 05996 05997 /*! @brief Read current value of the AIPS_PACRH_TP5 field. */ 05998 #define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5)) 05999 06000 /*! @brief Format value for bitfield AIPS_PACRH_TP5. */ 06001 #define BF_AIPS_PACRH_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP5) & BM_AIPS_PACRH_TP5) 06002 06003 /*! @brief Set the TP5 field to a new value. */ 06004 #define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v)) 06005 /*@}*/ 06006 06007 /*! 06008 * @name Register AIPS_PACRH, field WP5[9] (RW) 06009 * 06010 * Determines whether the peripheral allows write accesses. When this field is 06011 * set and a write access is attempted, access terminates with an error response 06012 * and no peripheral access initiates. 06013 * 06014 * Values: 06015 * - 0 - This peripheral allows write accesses. 06016 * - 1 - This peripheral is write protected. 06017 */ 06018 /*@{*/ 06019 #define BP_AIPS_PACRH_WP5 (9U) /*!< Bit position for AIPS_PACRH_WP5. */ 06020 #define BM_AIPS_PACRH_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRH_WP5. */ 06021 #define BS_AIPS_PACRH_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP5. */ 06022 06023 /*! @brief Read current value of the AIPS_PACRH_WP5 field. */ 06024 #define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5)) 06025 06026 /*! @brief Format value for bitfield AIPS_PACRH_WP5. */ 06027 #define BF_AIPS_PACRH_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP5) & BM_AIPS_PACRH_WP5) 06028 06029 /*! @brief Set the WP5 field to a new value. */ 06030 #define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v)) 06031 /*@}*/ 06032 06033 /*! 06034 * @name Register AIPS_PACRH, field SP5[10] (RW) 06035 * 06036 * Determines whether the peripheral requires supervisor privilege level for 06037 * accesses. When this field is set, the master privilege level must indicate the 06038 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06039 * must be set. If not, access terminates with an error response and no peripheral 06040 * access initiates. 06041 * 06042 * Values: 06043 * - 0 - This peripheral does not require supervisor privilege level for 06044 * accesses. 06045 * - 1 - This peripheral requires supervisor privilege level for accesses. 06046 */ 06047 /*@{*/ 06048 #define BP_AIPS_PACRH_SP5 (10U) /*!< Bit position for AIPS_PACRH_SP5. */ 06049 #define BM_AIPS_PACRH_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRH_SP5. */ 06050 #define BS_AIPS_PACRH_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP5. */ 06051 06052 /*! @brief Read current value of the AIPS_PACRH_SP5 field. */ 06053 #define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5)) 06054 06055 /*! @brief Format value for bitfield AIPS_PACRH_SP5. */ 06056 #define BF_AIPS_PACRH_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP5) & BM_AIPS_PACRH_SP5) 06057 06058 /*! @brief Set the SP5 field to a new value. */ 06059 #define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v)) 06060 /*@}*/ 06061 06062 /*! 06063 * @name Register AIPS_PACRH, field TP4[12] (RW) 06064 * 06065 * Determines whether the peripheral allows accesses from an untrusted master. 06066 * When this bit is set and an access is attempted by an untrusted master, the 06067 * access terminates with an error response and no peripheral access initiates. 06068 * 06069 * Values: 06070 * - 0 - Accesses from an untrusted master are allowed. 06071 * - 1 - Accesses from an untrusted master are not allowed. 06072 */ 06073 /*@{*/ 06074 #define BP_AIPS_PACRH_TP4 (12U) /*!< Bit position for AIPS_PACRH_TP4. */ 06075 #define BM_AIPS_PACRH_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRH_TP4. */ 06076 #define BS_AIPS_PACRH_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP4. */ 06077 06078 /*! @brief Read current value of the AIPS_PACRH_TP4 field. */ 06079 #define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4)) 06080 06081 /*! @brief Format value for bitfield AIPS_PACRH_TP4. */ 06082 #define BF_AIPS_PACRH_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP4) & BM_AIPS_PACRH_TP4) 06083 06084 /*! @brief Set the TP4 field to a new value. */ 06085 #define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v)) 06086 /*@}*/ 06087 06088 /*! 06089 * @name Register AIPS_PACRH, field WP4[13] (RW) 06090 * 06091 * Determines whether the peripheral allows write accesses. When this field is 06092 * set and a write access is attempted, access terminates with an error response 06093 * and no peripheral access initiates. 06094 * 06095 * Values: 06096 * - 0 - This peripheral allows write accesses. 06097 * - 1 - This peripheral is write protected. 06098 */ 06099 /*@{*/ 06100 #define BP_AIPS_PACRH_WP4 (13U) /*!< Bit position for AIPS_PACRH_WP4. */ 06101 #define BM_AIPS_PACRH_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRH_WP4. */ 06102 #define BS_AIPS_PACRH_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP4. */ 06103 06104 /*! @brief Read current value of the AIPS_PACRH_WP4 field. */ 06105 #define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4)) 06106 06107 /*! @brief Format value for bitfield AIPS_PACRH_WP4. */ 06108 #define BF_AIPS_PACRH_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP4) & BM_AIPS_PACRH_WP4) 06109 06110 /*! @brief Set the WP4 field to a new value. */ 06111 #define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v)) 06112 /*@}*/ 06113 06114 /*! 06115 * @name Register AIPS_PACRH, field SP4[14] (RW) 06116 * 06117 * Determines whether the peripheral requires supervisor privilege level for 06118 * access. When this bit is set, the master privilege level must indicate the 06119 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06120 * set. If not, access terminates with an error response and no peripheral access 06121 * initiates. 06122 * 06123 * Values: 06124 * - 0 - This peripheral does not require supervisor privilege level for 06125 * accesses. 06126 * - 1 - This peripheral requires supervisor privilege level for accesses. 06127 */ 06128 /*@{*/ 06129 #define BP_AIPS_PACRH_SP4 (14U) /*!< Bit position for AIPS_PACRH_SP4. */ 06130 #define BM_AIPS_PACRH_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRH_SP4. */ 06131 #define BS_AIPS_PACRH_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP4. */ 06132 06133 /*! @brief Read current value of the AIPS_PACRH_SP4 field. */ 06134 #define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4)) 06135 06136 /*! @brief Format value for bitfield AIPS_PACRH_SP4. */ 06137 #define BF_AIPS_PACRH_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP4) & BM_AIPS_PACRH_SP4) 06138 06139 /*! @brief Set the SP4 field to a new value. */ 06140 #define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v)) 06141 /*@}*/ 06142 06143 /*! 06144 * @name Register AIPS_PACRH, field TP3[16] (RW) 06145 * 06146 * Determines whether the peripheral allows accesses from an untrusted master. 06147 * When this field is set and an access is attempted by an untrusted master, the 06148 * access terminates with an error response and no peripheral access initiates. 06149 * 06150 * Values: 06151 * - 0 - Accesses from an untrusted master are allowed. 06152 * - 1 - Accesses from an untrusted master are not allowed. 06153 */ 06154 /*@{*/ 06155 #define BP_AIPS_PACRH_TP3 (16U) /*!< Bit position for AIPS_PACRH_TP3. */ 06156 #define BM_AIPS_PACRH_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRH_TP3. */ 06157 #define BS_AIPS_PACRH_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP3. */ 06158 06159 /*! @brief Read current value of the AIPS_PACRH_TP3 field. */ 06160 #define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3)) 06161 06162 /*! @brief Format value for bitfield AIPS_PACRH_TP3. */ 06163 #define BF_AIPS_PACRH_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP3) & BM_AIPS_PACRH_TP3) 06164 06165 /*! @brief Set the TP3 field to a new value. */ 06166 #define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v)) 06167 /*@}*/ 06168 06169 /*! 06170 * @name Register AIPS_PACRH, field WP3[17] (RW) 06171 * 06172 * Determines whether the peripheral allows write accesss. When this bit is set 06173 * and a write access is attempted, access terminates with an error response and 06174 * no peripheral access initiates. 06175 * 06176 * Values: 06177 * - 0 - This peripheral allows write accesses. 06178 * - 1 - This peripheral is write protected. 06179 */ 06180 /*@{*/ 06181 #define BP_AIPS_PACRH_WP3 (17U) /*!< Bit position for AIPS_PACRH_WP3. */ 06182 #define BM_AIPS_PACRH_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRH_WP3. */ 06183 #define BS_AIPS_PACRH_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP3. */ 06184 06185 /*! @brief Read current value of the AIPS_PACRH_WP3 field. */ 06186 #define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3)) 06187 06188 /*! @brief Format value for bitfield AIPS_PACRH_WP3. */ 06189 #define BF_AIPS_PACRH_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP3) & BM_AIPS_PACRH_WP3) 06190 06191 /*! @brief Set the WP3 field to a new value. */ 06192 #define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v)) 06193 /*@}*/ 06194 06195 /*! 06196 * @name Register AIPS_PACRH, field SP3[18] (RW) 06197 * 06198 * Determines whether the peripheral requires supervisor privilege level for 06199 * accesses. When this field is set, the master privilege level must indicate the 06200 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06201 * must be set. If not, access terminates with an error response and no peripheral 06202 * access initiates. 06203 * 06204 * Values: 06205 * - 0 - This peripheral does not require supervisor privilege level for 06206 * accesses. 06207 * - 1 - This peripheral requires supervisor privilege level for accesses. 06208 */ 06209 /*@{*/ 06210 #define BP_AIPS_PACRH_SP3 (18U) /*!< Bit position for AIPS_PACRH_SP3. */ 06211 #define BM_AIPS_PACRH_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRH_SP3. */ 06212 #define BS_AIPS_PACRH_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP3. */ 06213 06214 /*! @brief Read current value of the AIPS_PACRH_SP3 field. */ 06215 #define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3)) 06216 06217 /*! @brief Format value for bitfield AIPS_PACRH_SP3. */ 06218 #define BF_AIPS_PACRH_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP3) & BM_AIPS_PACRH_SP3) 06219 06220 /*! @brief Set the SP3 field to a new value. */ 06221 #define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v)) 06222 /*@}*/ 06223 06224 /*! 06225 * @name Register AIPS_PACRH, field TP2[20] (RW) 06226 * 06227 * Determines whether the peripheral allows accesses from an untrusted master. 06228 * When this bit is set and an access is attempted by an untrusted master, the 06229 * access terminates with an error response and no peripheral access initiates. 06230 * 06231 * Values: 06232 * - 0 - Accesses from an untrusted master are allowed. 06233 * - 1 - Accesses from an untrusted master are not allowed. 06234 */ 06235 /*@{*/ 06236 #define BP_AIPS_PACRH_TP2 (20U) /*!< Bit position for AIPS_PACRH_TP2. */ 06237 #define BM_AIPS_PACRH_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRH_TP2. */ 06238 #define BS_AIPS_PACRH_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP2. */ 06239 06240 /*! @brief Read current value of the AIPS_PACRH_TP2 field. */ 06241 #define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2)) 06242 06243 /*! @brief Format value for bitfield AIPS_PACRH_TP2. */ 06244 #define BF_AIPS_PACRH_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP2) & BM_AIPS_PACRH_TP2) 06245 06246 /*! @brief Set the TP2 field to a new value. */ 06247 #define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v)) 06248 /*@}*/ 06249 06250 /*! 06251 * @name Register AIPS_PACRH, field WP2[21] (RW) 06252 * 06253 * Determines whether the peripheral allows write accesses. When this field is 06254 * set and a write access is attempted, access terminates with an error response 06255 * and no peripheral access initiates. 06256 * 06257 * Values: 06258 * - 0 - This peripheral allows write accesses. 06259 * - 1 - This peripheral is write protected. 06260 */ 06261 /*@{*/ 06262 #define BP_AIPS_PACRH_WP2 (21U) /*!< Bit position for AIPS_PACRH_WP2. */ 06263 #define BM_AIPS_PACRH_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRH_WP2. */ 06264 #define BS_AIPS_PACRH_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP2. */ 06265 06266 /*! @brief Read current value of the AIPS_PACRH_WP2 field. */ 06267 #define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2)) 06268 06269 /*! @brief Format value for bitfield AIPS_PACRH_WP2. */ 06270 #define BF_AIPS_PACRH_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP2) & BM_AIPS_PACRH_WP2) 06271 06272 /*! @brief Set the WP2 field to a new value. */ 06273 #define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v)) 06274 /*@}*/ 06275 06276 /*! 06277 * @name Register AIPS_PACRH, field SP2[22] (RW) 06278 * 06279 * Determines whether the peripheral requires supervisor privilege level for 06280 * access. When this bit is set, the master privilege level must indicate the 06281 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06282 * set. If not, access terminates with an error response and no peripheral access 06283 * initiates. 06284 * 06285 * Values: 06286 * - 0 - This peripheral does not require supervisor privilege level for 06287 * accesses. 06288 * - 1 - This peripheral requires supervisor privilege level for accesses. 06289 */ 06290 /*@{*/ 06291 #define BP_AIPS_PACRH_SP2 (22U) /*!< Bit position for AIPS_PACRH_SP2. */ 06292 #define BM_AIPS_PACRH_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRH_SP2. */ 06293 #define BS_AIPS_PACRH_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP2. */ 06294 06295 /*! @brief Read current value of the AIPS_PACRH_SP2 field. */ 06296 #define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2)) 06297 06298 /*! @brief Format value for bitfield AIPS_PACRH_SP2. */ 06299 #define BF_AIPS_PACRH_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP2) & BM_AIPS_PACRH_SP2) 06300 06301 /*! @brief Set the SP2 field to a new value. */ 06302 #define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v)) 06303 /*@}*/ 06304 06305 /*! 06306 * @name Register AIPS_PACRH, field TP1[24] (RW) 06307 * 06308 * Determines whether the peripheral allows accesses from an untrusted master. 06309 * When this field is set and an access is attempted by an untrusted master, the 06310 * access terminates with an error response and no peripheral access initiates. 06311 * 06312 * Values: 06313 * - 0 - Accesses from an untrusted master are allowed. 06314 * - 1 - Accesses from an untrusted master are not allowed. 06315 */ 06316 /*@{*/ 06317 #define BP_AIPS_PACRH_TP1 (24U) /*!< Bit position for AIPS_PACRH_TP1. */ 06318 #define BM_AIPS_PACRH_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRH_TP1. */ 06319 #define BS_AIPS_PACRH_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP1. */ 06320 06321 /*! @brief Read current value of the AIPS_PACRH_TP1 field. */ 06322 #define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1)) 06323 06324 /*! @brief Format value for bitfield AIPS_PACRH_TP1. */ 06325 #define BF_AIPS_PACRH_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP1) & BM_AIPS_PACRH_TP1) 06326 06327 /*! @brief Set the TP1 field to a new value. */ 06328 #define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v)) 06329 /*@}*/ 06330 06331 /*! 06332 * @name Register AIPS_PACRH, field WP1[25] (RW) 06333 * 06334 * Determines whether the peripheral allows write accesses. When this field is 06335 * set and a write access is attempted, access terminates with an error response 06336 * and no peripheral access initiates. 06337 * 06338 * Values: 06339 * - 0 - This peripheral allows write accesses. 06340 * - 1 - This peripheral is write protected. 06341 */ 06342 /*@{*/ 06343 #define BP_AIPS_PACRH_WP1 (25U) /*!< Bit position for AIPS_PACRH_WP1. */ 06344 #define BM_AIPS_PACRH_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRH_WP1. */ 06345 #define BS_AIPS_PACRH_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP1. */ 06346 06347 /*! @brief Read current value of the AIPS_PACRH_WP1 field. */ 06348 #define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1)) 06349 06350 /*! @brief Format value for bitfield AIPS_PACRH_WP1. */ 06351 #define BF_AIPS_PACRH_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP1) & BM_AIPS_PACRH_WP1) 06352 06353 /*! @brief Set the WP1 field to a new value. */ 06354 #define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v)) 06355 /*@}*/ 06356 06357 /*! 06358 * @name Register AIPS_PACRH, field SP1[26] (RW) 06359 * 06360 * Determines whether the peripheral requires supervisor privilege level for 06361 * access. When this field is set, the master privilege level must indicate the 06362 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 06363 * be set. If not, access terminates with an error response and no peripheral 06364 * access initiates. 06365 * 06366 * Values: 06367 * - 0 - This peripheral does not require supervisor privilege level for 06368 * accesses. 06369 * - 1 - This peripheral requires supervisor privilege level for accesses. 06370 */ 06371 /*@{*/ 06372 #define BP_AIPS_PACRH_SP1 (26U) /*!< Bit position for AIPS_PACRH_SP1. */ 06373 #define BM_AIPS_PACRH_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRH_SP1. */ 06374 #define BS_AIPS_PACRH_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP1. */ 06375 06376 /*! @brief Read current value of the AIPS_PACRH_SP1 field. */ 06377 #define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1)) 06378 06379 /*! @brief Format value for bitfield AIPS_PACRH_SP1. */ 06380 #define BF_AIPS_PACRH_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP1) & BM_AIPS_PACRH_SP1) 06381 06382 /*! @brief Set the SP1 field to a new value. */ 06383 #define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v)) 06384 /*@}*/ 06385 06386 /*! 06387 * @name Register AIPS_PACRH, field TP0[28] (RW) 06388 * 06389 * Determines whether the peripheral allows accesses from an untrusted master. 06390 * When this bit is set and an access is attempted by an untrusted master, the 06391 * access terminates with an error response and no peripheral access initiates. 06392 * 06393 * Values: 06394 * - 0 - Accesses from an untrusted master are allowed. 06395 * - 1 - Accesses from an untrusted master are not allowed. 06396 */ 06397 /*@{*/ 06398 #define BP_AIPS_PACRH_TP0 (28U) /*!< Bit position for AIPS_PACRH_TP0. */ 06399 #define BM_AIPS_PACRH_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRH_TP0. */ 06400 #define BS_AIPS_PACRH_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP0. */ 06401 06402 /*! @brief Read current value of the AIPS_PACRH_TP0 field. */ 06403 #define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0)) 06404 06405 /*! @brief Format value for bitfield AIPS_PACRH_TP0. */ 06406 #define BF_AIPS_PACRH_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP0) & BM_AIPS_PACRH_TP0) 06407 06408 /*! @brief Set the TP0 field to a new value. */ 06409 #define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v)) 06410 /*@}*/ 06411 06412 /*! 06413 * @name Register AIPS_PACRH, field WP0[29] (RW) 06414 * 06415 * Determines whether the peripheral allows write accesses. When this field is 06416 * set and a write access is attempted, access terminates with an error response 06417 * and no peripheral access initiates. 06418 * 06419 * Values: 06420 * - 0 - This peripheral allows write accesses. 06421 * - 1 - This peripheral is write protected. 06422 */ 06423 /*@{*/ 06424 #define BP_AIPS_PACRH_WP0 (29U) /*!< Bit position for AIPS_PACRH_WP0. */ 06425 #define BM_AIPS_PACRH_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRH_WP0. */ 06426 #define BS_AIPS_PACRH_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP0. */ 06427 06428 /*! @brief Read current value of the AIPS_PACRH_WP0 field. */ 06429 #define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0)) 06430 06431 /*! @brief Format value for bitfield AIPS_PACRH_WP0. */ 06432 #define BF_AIPS_PACRH_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP0) & BM_AIPS_PACRH_WP0) 06433 06434 /*! @brief Set the WP0 field to a new value. */ 06435 #define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v)) 06436 /*@}*/ 06437 06438 /*! 06439 * @name Register AIPS_PACRH, field SP0[30] (RW) 06440 * 06441 * Determines whether the peripheral requires supervisor privilege level for 06442 * accesses. When this field is set, the master privilege level must indicate the 06443 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06444 * must be set. If not, access terminates with an error response and no peripheral 06445 * access initiates. 06446 * 06447 * Values: 06448 * - 0 - This peripheral does not require supervisor privilege level for 06449 * accesses. 06450 * - 1 - This peripheral requires supervisor privilege level for accesses. 06451 */ 06452 /*@{*/ 06453 #define BP_AIPS_PACRH_SP0 (30U) /*!< Bit position for AIPS_PACRH_SP0. */ 06454 #define BM_AIPS_PACRH_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRH_SP0. */ 06455 #define BS_AIPS_PACRH_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP0. */ 06456 06457 /*! @brief Read current value of the AIPS_PACRH_SP0 field. */ 06458 #define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0)) 06459 06460 /*! @brief Format value for bitfield AIPS_PACRH_SP0. */ 06461 #define BF_AIPS_PACRH_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP0) & BM_AIPS_PACRH_SP0) 06462 06463 /*! @brief Set the SP0 field to a new value. */ 06464 #define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v)) 06465 /*@}*/ 06466 06467 /******************************************************************************* 06468 * HW_AIPS_PACRI - Peripheral Access Control Register 06469 ******************************************************************************/ 06470 06471 /*! 06472 * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) 06473 * 06474 * Reset value: 0x44444444U 06475 * 06476 * This section describes PACR registers E-P, which control peripheral slots 06477 * 32-127. See PACRPeripheral Access Control Register for the description of these 06478 * registers. 06479 */ 06480 typedef union _hw_aips_pacri 06481 { 06482 uint32_t U; 06483 struct _hw_aips_pacri_bitfields 06484 { 06485 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 06486 uint32_t WP7 : 1; /*!< [1] Write Protect */ 06487 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 06488 uint32_t RESERVED0 : 1; /*!< [3] */ 06489 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 06490 uint32_t WP6 : 1; /*!< [5] Write Protect */ 06491 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 06492 uint32_t RESERVED1 : 1; /*!< [7] */ 06493 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 06494 uint32_t WP5 : 1; /*!< [9] Write Protect */ 06495 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 06496 uint32_t RESERVED2 : 1; /*!< [11] */ 06497 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 06498 uint32_t WP4 : 1; /*!< [13] Write Protect */ 06499 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 06500 uint32_t RESERVED3 : 1; /*!< [15] */ 06501 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 06502 uint32_t WP3 : 1; /*!< [17] Write Protect */ 06503 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 06504 uint32_t RESERVED4 : 1; /*!< [19] */ 06505 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 06506 uint32_t WP2 : 1; /*!< [21] Write Protect */ 06507 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 06508 uint32_t RESERVED5 : 1; /*!< [23] */ 06509 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 06510 uint32_t WP1 : 1; /*!< [25] Write Protect */ 06511 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 06512 uint32_t RESERVED6 : 1; /*!< [27] */ 06513 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 06514 uint32_t WP0 : 1; /*!< [29] Write Protect */ 06515 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 06516 uint32_t RESERVED7 : 1; /*!< [31] */ 06517 } B; 06518 } hw_aips_pacri_t; 06519 06520 /*! 06521 * @name Constants and macros for entire AIPS_PACRI register 06522 */ 06523 /*@{*/ 06524 #define HW_AIPS_PACRI_ADDR(x) ((x) + 0x50U) 06525 06526 #define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) 06527 #define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U) 06528 #define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v)) 06529 #define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) 06530 #define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) 06531 #define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) 06532 /*@}*/ 06533 06534 /* 06535 * Constants & macros for individual AIPS_PACRI bitfields 06536 */ 06537 06538 /*! 06539 * @name Register AIPS_PACRI, field TP7[0] (RW) 06540 * 06541 * Determines whether the peripheral allows accesses from an untrusted master. 06542 * When this field is set and an access is attempted by an untrusted master, the 06543 * access terminates with an error response and no peripheral access initiates. 06544 * 06545 * Values: 06546 * - 0 - Accesses from an untrusted master are allowed. 06547 * - 1 - Accesses from an untrusted master are not allowed. 06548 */ 06549 /*@{*/ 06550 #define BP_AIPS_PACRI_TP7 (0U) /*!< Bit position for AIPS_PACRI_TP7. */ 06551 #define BM_AIPS_PACRI_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRI_TP7. */ 06552 #define BS_AIPS_PACRI_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP7. */ 06553 06554 /*! @brief Read current value of the AIPS_PACRI_TP7 field. */ 06555 #define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7)) 06556 06557 /*! @brief Format value for bitfield AIPS_PACRI_TP7. */ 06558 #define BF_AIPS_PACRI_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP7) & BM_AIPS_PACRI_TP7) 06559 06560 /*! @brief Set the TP7 field to a new value. */ 06561 #define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v)) 06562 /*@}*/ 06563 06564 /*! 06565 * @name Register AIPS_PACRI, field WP7[1] (RW) 06566 * 06567 * Determines whether the peripheral allows write accesses. When this field is 06568 * set and a write access is attempted, access terminates with an error response 06569 * and no peripheral access initiates. 06570 * 06571 * Values: 06572 * - 0 - This peripheral allows write accesses. 06573 * - 1 - This peripheral is write protected. 06574 */ 06575 /*@{*/ 06576 #define BP_AIPS_PACRI_WP7 (1U) /*!< Bit position for AIPS_PACRI_WP7. */ 06577 #define BM_AIPS_PACRI_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRI_WP7. */ 06578 #define BS_AIPS_PACRI_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP7. */ 06579 06580 /*! @brief Read current value of the AIPS_PACRI_WP7 field. */ 06581 #define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7)) 06582 06583 /*! @brief Format value for bitfield AIPS_PACRI_WP7. */ 06584 #define BF_AIPS_PACRI_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP7) & BM_AIPS_PACRI_WP7) 06585 06586 /*! @brief Set the WP7 field to a new value. */ 06587 #define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v)) 06588 /*@}*/ 06589 06590 /*! 06591 * @name Register AIPS_PACRI, field SP7[2] (RW) 06592 * 06593 * Determines whether the peripheral requires supervisor privilege level for 06594 * accesses. When this field is set, the master privilege level must indicate the 06595 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06596 * must be set. If not, access terminates with an error response and no peripheral 06597 * access initiates. 06598 * 06599 * Values: 06600 * - 0 - This peripheral does not require supervisor privilege level for 06601 * accesses. 06602 * - 1 - This peripheral requires supervisor privilege level for accesses. 06603 */ 06604 /*@{*/ 06605 #define BP_AIPS_PACRI_SP7 (2U) /*!< Bit position for AIPS_PACRI_SP7. */ 06606 #define BM_AIPS_PACRI_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRI_SP7. */ 06607 #define BS_AIPS_PACRI_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP7. */ 06608 06609 /*! @brief Read current value of the AIPS_PACRI_SP7 field. */ 06610 #define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7)) 06611 06612 /*! @brief Format value for bitfield AIPS_PACRI_SP7. */ 06613 #define BF_AIPS_PACRI_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP7) & BM_AIPS_PACRI_SP7) 06614 06615 /*! @brief Set the SP7 field to a new value. */ 06616 #define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v)) 06617 /*@}*/ 06618 06619 /*! 06620 * @name Register AIPS_PACRI, field TP6[4] (RW) 06621 * 06622 * Determines whether the peripheral allows accesses from an untrusted master. 06623 * When this field is set and an access is attempted by an untrusted master, the 06624 * access terminates with an error response and no peripheral access initiates. 06625 * 06626 * Values: 06627 * - 0 - Accesses from an untrusted master are allowed. 06628 * - 1 - Accesses from an untrusted master are not allowed. 06629 */ 06630 /*@{*/ 06631 #define BP_AIPS_PACRI_TP6 (4U) /*!< Bit position for AIPS_PACRI_TP6. */ 06632 #define BM_AIPS_PACRI_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRI_TP6. */ 06633 #define BS_AIPS_PACRI_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP6. */ 06634 06635 /*! @brief Read current value of the AIPS_PACRI_TP6 field. */ 06636 #define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6)) 06637 06638 /*! @brief Format value for bitfield AIPS_PACRI_TP6. */ 06639 #define BF_AIPS_PACRI_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP6) & BM_AIPS_PACRI_TP6) 06640 06641 /*! @brief Set the TP6 field to a new value. */ 06642 #define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v)) 06643 /*@}*/ 06644 06645 /*! 06646 * @name Register AIPS_PACRI, field WP6[5] (RW) 06647 * 06648 * Determines whether the peripheral allows write accesses. When this field is 06649 * set and a write access is attempted, access terminates with an error response 06650 * and no peripheral access initiates. 06651 * 06652 * Values: 06653 * - 0 - This peripheral allows write accesses. 06654 * - 1 - This peripheral is write protected. 06655 */ 06656 /*@{*/ 06657 #define BP_AIPS_PACRI_WP6 (5U) /*!< Bit position for AIPS_PACRI_WP6. */ 06658 #define BM_AIPS_PACRI_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRI_WP6. */ 06659 #define BS_AIPS_PACRI_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP6. */ 06660 06661 /*! @brief Read current value of the AIPS_PACRI_WP6 field. */ 06662 #define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6)) 06663 06664 /*! @brief Format value for bitfield AIPS_PACRI_WP6. */ 06665 #define BF_AIPS_PACRI_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP6) & BM_AIPS_PACRI_WP6) 06666 06667 /*! @brief Set the WP6 field to a new value. */ 06668 #define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v)) 06669 /*@}*/ 06670 06671 /*! 06672 * @name Register AIPS_PACRI, field SP6[6] (RW) 06673 * 06674 * Determines whether the peripheral requires supervisor privilege level for 06675 * accesses. When this field is set, the master privilege level must indicate the 06676 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06677 * must be set. If not, access terminates with an error response and no peripheral 06678 * access initiates. 06679 * 06680 * Values: 06681 * - 0 - This peripheral does not require supervisor privilege level for 06682 * accesses. 06683 * - 1 - This peripheral requires supervisor privilege level for accesses. 06684 */ 06685 /*@{*/ 06686 #define BP_AIPS_PACRI_SP6 (6U) /*!< Bit position for AIPS_PACRI_SP6. */ 06687 #define BM_AIPS_PACRI_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRI_SP6. */ 06688 #define BS_AIPS_PACRI_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP6. */ 06689 06690 /*! @brief Read current value of the AIPS_PACRI_SP6 field. */ 06691 #define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6)) 06692 06693 /*! @brief Format value for bitfield AIPS_PACRI_SP6. */ 06694 #define BF_AIPS_PACRI_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP6) & BM_AIPS_PACRI_SP6) 06695 06696 /*! @brief Set the SP6 field to a new value. */ 06697 #define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v)) 06698 /*@}*/ 06699 06700 /*! 06701 * @name Register AIPS_PACRI, field TP5[8] (RW) 06702 * 06703 * Determines whether the peripheral allows accesses from an untrusted master. 06704 * When this field is set and an access is attempted by an untrusted master, the 06705 * access terminates with an error response and no peripheral access initiates. 06706 * 06707 * Values: 06708 * - 0 - Accesses from an untrusted master are allowed. 06709 * - 1 - Accesses from an untrusted master are not allowed. 06710 */ 06711 /*@{*/ 06712 #define BP_AIPS_PACRI_TP5 (8U) /*!< Bit position for AIPS_PACRI_TP5. */ 06713 #define BM_AIPS_PACRI_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRI_TP5. */ 06714 #define BS_AIPS_PACRI_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP5. */ 06715 06716 /*! @brief Read current value of the AIPS_PACRI_TP5 field. */ 06717 #define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5)) 06718 06719 /*! @brief Format value for bitfield AIPS_PACRI_TP5. */ 06720 #define BF_AIPS_PACRI_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP5) & BM_AIPS_PACRI_TP5) 06721 06722 /*! @brief Set the TP5 field to a new value. */ 06723 #define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v)) 06724 /*@}*/ 06725 06726 /*! 06727 * @name Register AIPS_PACRI, field WP5[9] (RW) 06728 * 06729 * Determines whether the peripheral allows write accesses. When this field is 06730 * set and a write access is attempted, access terminates with an error response 06731 * and no peripheral access initiates. 06732 * 06733 * Values: 06734 * - 0 - This peripheral allows write accesses. 06735 * - 1 - This peripheral is write protected. 06736 */ 06737 /*@{*/ 06738 #define BP_AIPS_PACRI_WP5 (9U) /*!< Bit position for AIPS_PACRI_WP5. */ 06739 #define BM_AIPS_PACRI_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRI_WP5. */ 06740 #define BS_AIPS_PACRI_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP5. */ 06741 06742 /*! @brief Read current value of the AIPS_PACRI_WP5 field. */ 06743 #define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5)) 06744 06745 /*! @brief Format value for bitfield AIPS_PACRI_WP5. */ 06746 #define BF_AIPS_PACRI_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP5) & BM_AIPS_PACRI_WP5) 06747 06748 /*! @brief Set the WP5 field to a new value. */ 06749 #define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v)) 06750 /*@}*/ 06751 06752 /*! 06753 * @name Register AIPS_PACRI, field SP5[10] (RW) 06754 * 06755 * Determines whether the peripheral requires supervisor privilege level for 06756 * accesses. When this field is set, the master privilege level must indicate the 06757 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06758 * must be set. If not, access terminates with an error response and no peripheral 06759 * access initiates. 06760 * 06761 * Values: 06762 * - 0 - This peripheral does not require supervisor privilege level for 06763 * accesses. 06764 * - 1 - This peripheral requires supervisor privilege level for accesses. 06765 */ 06766 /*@{*/ 06767 #define BP_AIPS_PACRI_SP5 (10U) /*!< Bit position for AIPS_PACRI_SP5. */ 06768 #define BM_AIPS_PACRI_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRI_SP5. */ 06769 #define BS_AIPS_PACRI_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP5. */ 06770 06771 /*! @brief Read current value of the AIPS_PACRI_SP5 field. */ 06772 #define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5)) 06773 06774 /*! @brief Format value for bitfield AIPS_PACRI_SP5. */ 06775 #define BF_AIPS_PACRI_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP5) & BM_AIPS_PACRI_SP5) 06776 06777 /*! @brief Set the SP5 field to a new value. */ 06778 #define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v)) 06779 /*@}*/ 06780 06781 /*! 06782 * @name Register AIPS_PACRI, field TP4[12] (RW) 06783 * 06784 * Determines whether the peripheral allows accesses from an untrusted master. 06785 * When this bit is set and an access is attempted by an untrusted master, the 06786 * access terminates with an error response and no peripheral access initiates. 06787 * 06788 * Values: 06789 * - 0 - Accesses from an untrusted master are allowed. 06790 * - 1 - Accesses from an untrusted master are not allowed. 06791 */ 06792 /*@{*/ 06793 #define BP_AIPS_PACRI_TP4 (12U) /*!< Bit position for AIPS_PACRI_TP4. */ 06794 #define BM_AIPS_PACRI_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRI_TP4. */ 06795 #define BS_AIPS_PACRI_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP4. */ 06796 06797 /*! @brief Read current value of the AIPS_PACRI_TP4 field. */ 06798 #define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4)) 06799 06800 /*! @brief Format value for bitfield AIPS_PACRI_TP4. */ 06801 #define BF_AIPS_PACRI_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP4) & BM_AIPS_PACRI_TP4) 06802 06803 /*! @brief Set the TP4 field to a new value. */ 06804 #define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v)) 06805 /*@}*/ 06806 06807 /*! 06808 * @name Register AIPS_PACRI, field WP4[13] (RW) 06809 * 06810 * Determines whether the peripheral allows write accesses. When this field is 06811 * set and a write access is attempted, access terminates with an error response 06812 * and no peripheral access initiates. 06813 * 06814 * Values: 06815 * - 0 - This peripheral allows write accesses. 06816 * - 1 - This peripheral is write protected. 06817 */ 06818 /*@{*/ 06819 #define BP_AIPS_PACRI_WP4 (13U) /*!< Bit position for AIPS_PACRI_WP4. */ 06820 #define BM_AIPS_PACRI_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRI_WP4. */ 06821 #define BS_AIPS_PACRI_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP4. */ 06822 06823 /*! @brief Read current value of the AIPS_PACRI_WP4 field. */ 06824 #define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4)) 06825 06826 /*! @brief Format value for bitfield AIPS_PACRI_WP4. */ 06827 #define BF_AIPS_PACRI_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP4) & BM_AIPS_PACRI_WP4) 06828 06829 /*! @brief Set the WP4 field to a new value. */ 06830 #define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v)) 06831 /*@}*/ 06832 06833 /*! 06834 * @name Register AIPS_PACRI, field SP4[14] (RW) 06835 * 06836 * Determines whether the peripheral requires supervisor privilege level for 06837 * access. When this bit is set, the master privilege level must indicate the 06838 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06839 * set. If not, access terminates with an error response and no peripheral access 06840 * initiates. 06841 * 06842 * Values: 06843 * - 0 - This peripheral does not require supervisor privilege level for 06844 * accesses. 06845 * - 1 - This peripheral requires supervisor privilege level for accesses. 06846 */ 06847 /*@{*/ 06848 #define BP_AIPS_PACRI_SP4 (14U) /*!< Bit position for AIPS_PACRI_SP4. */ 06849 #define BM_AIPS_PACRI_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRI_SP4. */ 06850 #define BS_AIPS_PACRI_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP4. */ 06851 06852 /*! @brief Read current value of the AIPS_PACRI_SP4 field. */ 06853 #define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4)) 06854 06855 /*! @brief Format value for bitfield AIPS_PACRI_SP4. */ 06856 #define BF_AIPS_PACRI_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP4) & BM_AIPS_PACRI_SP4) 06857 06858 /*! @brief Set the SP4 field to a new value. */ 06859 #define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v)) 06860 /*@}*/ 06861 06862 /*! 06863 * @name Register AIPS_PACRI, field TP3[16] (RW) 06864 * 06865 * Determines whether the peripheral allows accesses from an untrusted master. 06866 * When this field is set and an access is attempted by an untrusted master, the 06867 * access terminates with an error response and no peripheral access initiates. 06868 * 06869 * Values: 06870 * - 0 - Accesses from an untrusted master are allowed. 06871 * - 1 - Accesses from an untrusted master are not allowed. 06872 */ 06873 /*@{*/ 06874 #define BP_AIPS_PACRI_TP3 (16U) /*!< Bit position for AIPS_PACRI_TP3. */ 06875 #define BM_AIPS_PACRI_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRI_TP3. */ 06876 #define BS_AIPS_PACRI_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP3. */ 06877 06878 /*! @brief Read current value of the AIPS_PACRI_TP3 field. */ 06879 #define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3)) 06880 06881 /*! @brief Format value for bitfield AIPS_PACRI_TP3. */ 06882 #define BF_AIPS_PACRI_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP3) & BM_AIPS_PACRI_TP3) 06883 06884 /*! @brief Set the TP3 field to a new value. */ 06885 #define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v)) 06886 /*@}*/ 06887 06888 /*! 06889 * @name Register AIPS_PACRI, field WP3[17] (RW) 06890 * 06891 * Determines whether the peripheral allows write accesss. When this bit is set 06892 * and a write access is attempted, access terminates with an error response and 06893 * no peripheral access initiates. 06894 * 06895 * Values: 06896 * - 0 - This peripheral allows write accesses. 06897 * - 1 - This peripheral is write protected. 06898 */ 06899 /*@{*/ 06900 #define BP_AIPS_PACRI_WP3 (17U) /*!< Bit position for AIPS_PACRI_WP3. */ 06901 #define BM_AIPS_PACRI_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRI_WP3. */ 06902 #define BS_AIPS_PACRI_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP3. */ 06903 06904 /*! @brief Read current value of the AIPS_PACRI_WP3 field. */ 06905 #define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3)) 06906 06907 /*! @brief Format value for bitfield AIPS_PACRI_WP3. */ 06908 #define BF_AIPS_PACRI_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP3) & BM_AIPS_PACRI_WP3) 06909 06910 /*! @brief Set the WP3 field to a new value. */ 06911 #define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v)) 06912 /*@}*/ 06913 06914 /*! 06915 * @name Register AIPS_PACRI, field SP3[18] (RW) 06916 * 06917 * Determines whether the peripheral requires supervisor privilege level for 06918 * accesses. When this field is set, the master privilege level must indicate the 06919 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06920 * must be set. If not, access terminates with an error response and no peripheral 06921 * access initiates. 06922 * 06923 * Values: 06924 * - 0 - This peripheral does not require supervisor privilege level for 06925 * accesses. 06926 * - 1 - This peripheral requires supervisor privilege level for accesses. 06927 */ 06928 /*@{*/ 06929 #define BP_AIPS_PACRI_SP3 (18U) /*!< Bit position for AIPS_PACRI_SP3. */ 06930 #define BM_AIPS_PACRI_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRI_SP3. */ 06931 #define BS_AIPS_PACRI_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP3. */ 06932 06933 /*! @brief Read current value of the AIPS_PACRI_SP3 field. */ 06934 #define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3)) 06935 06936 /*! @brief Format value for bitfield AIPS_PACRI_SP3. */ 06937 #define BF_AIPS_PACRI_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP3) & BM_AIPS_PACRI_SP3) 06938 06939 /*! @brief Set the SP3 field to a new value. */ 06940 #define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v)) 06941 /*@}*/ 06942 06943 /*! 06944 * @name Register AIPS_PACRI, field TP2[20] (RW) 06945 * 06946 * Determines whether the peripheral allows accesses from an untrusted master. 06947 * When this bit is set and an access is attempted by an untrusted master, the 06948 * access terminates with an error response and no peripheral access initiates. 06949 * 06950 * Values: 06951 * - 0 - Accesses from an untrusted master are allowed. 06952 * - 1 - Accesses from an untrusted master are not allowed. 06953 */ 06954 /*@{*/ 06955 #define BP_AIPS_PACRI_TP2 (20U) /*!< Bit position for AIPS_PACRI_TP2. */ 06956 #define BM_AIPS_PACRI_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRI_TP2. */ 06957 #define BS_AIPS_PACRI_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP2. */ 06958 06959 /*! @brief Read current value of the AIPS_PACRI_TP2 field. */ 06960 #define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2)) 06961 06962 /*! @brief Format value for bitfield AIPS_PACRI_TP2. */ 06963 #define BF_AIPS_PACRI_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP2) & BM_AIPS_PACRI_TP2) 06964 06965 /*! @brief Set the TP2 field to a new value. */ 06966 #define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v)) 06967 /*@}*/ 06968 06969 /*! 06970 * @name Register AIPS_PACRI, field WP2[21] (RW) 06971 * 06972 * Determines whether the peripheral allows write accesses. When this field is 06973 * set and a write access is attempted, access terminates with an error response 06974 * and no peripheral access initiates. 06975 * 06976 * Values: 06977 * - 0 - This peripheral allows write accesses. 06978 * - 1 - This peripheral is write protected. 06979 */ 06980 /*@{*/ 06981 #define BP_AIPS_PACRI_WP2 (21U) /*!< Bit position for AIPS_PACRI_WP2. */ 06982 #define BM_AIPS_PACRI_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRI_WP2. */ 06983 #define BS_AIPS_PACRI_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP2. */ 06984 06985 /*! @brief Read current value of the AIPS_PACRI_WP2 field. */ 06986 #define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2)) 06987 06988 /*! @brief Format value for bitfield AIPS_PACRI_WP2. */ 06989 #define BF_AIPS_PACRI_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP2) & BM_AIPS_PACRI_WP2) 06990 06991 /*! @brief Set the WP2 field to a new value. */ 06992 #define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v)) 06993 /*@}*/ 06994 06995 /*! 06996 * @name Register AIPS_PACRI, field SP2[22] (RW) 06997 * 06998 * Determines whether the peripheral requires supervisor privilege level for 06999 * access. When this bit is set, the master privilege level must indicate the 07000 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07001 * set. If not, access terminates with an error response and no peripheral access 07002 * initiates. 07003 * 07004 * Values: 07005 * - 0 - This peripheral does not require supervisor privilege level for 07006 * accesses. 07007 * - 1 - This peripheral requires supervisor privilege level for accesses. 07008 */ 07009 /*@{*/ 07010 #define BP_AIPS_PACRI_SP2 (22U) /*!< Bit position for AIPS_PACRI_SP2. */ 07011 #define BM_AIPS_PACRI_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRI_SP2. */ 07012 #define BS_AIPS_PACRI_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP2. */ 07013 07014 /*! @brief Read current value of the AIPS_PACRI_SP2 field. */ 07015 #define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2)) 07016 07017 /*! @brief Format value for bitfield AIPS_PACRI_SP2. */ 07018 #define BF_AIPS_PACRI_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP2) & BM_AIPS_PACRI_SP2) 07019 07020 /*! @brief Set the SP2 field to a new value. */ 07021 #define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v)) 07022 /*@}*/ 07023 07024 /*! 07025 * @name Register AIPS_PACRI, field TP1[24] (RW) 07026 * 07027 * Determines whether the peripheral allows accesses from an untrusted master. 07028 * When this field is set and an access is attempted by an untrusted master, the 07029 * access terminates with an error response and no peripheral access initiates. 07030 * 07031 * Values: 07032 * - 0 - Accesses from an untrusted master are allowed. 07033 * - 1 - Accesses from an untrusted master are not allowed. 07034 */ 07035 /*@{*/ 07036 #define BP_AIPS_PACRI_TP1 (24U) /*!< Bit position for AIPS_PACRI_TP1. */ 07037 #define BM_AIPS_PACRI_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRI_TP1. */ 07038 #define BS_AIPS_PACRI_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP1. */ 07039 07040 /*! @brief Read current value of the AIPS_PACRI_TP1 field. */ 07041 #define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1)) 07042 07043 /*! @brief Format value for bitfield AIPS_PACRI_TP1. */ 07044 #define BF_AIPS_PACRI_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP1) & BM_AIPS_PACRI_TP1) 07045 07046 /*! @brief Set the TP1 field to a new value. */ 07047 #define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v)) 07048 /*@}*/ 07049 07050 /*! 07051 * @name Register AIPS_PACRI, field WP1[25] (RW) 07052 * 07053 * Determines whether the peripheral allows write accesses. When this field is 07054 * set and a write access is attempted, access terminates with an error response 07055 * and no peripheral access initiates. 07056 * 07057 * Values: 07058 * - 0 - This peripheral allows write accesses. 07059 * - 1 - This peripheral is write protected. 07060 */ 07061 /*@{*/ 07062 #define BP_AIPS_PACRI_WP1 (25U) /*!< Bit position for AIPS_PACRI_WP1. */ 07063 #define BM_AIPS_PACRI_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRI_WP1. */ 07064 #define BS_AIPS_PACRI_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP1. */ 07065 07066 /*! @brief Read current value of the AIPS_PACRI_WP1 field. */ 07067 #define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1)) 07068 07069 /*! @brief Format value for bitfield AIPS_PACRI_WP1. */ 07070 #define BF_AIPS_PACRI_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP1) & BM_AIPS_PACRI_WP1) 07071 07072 /*! @brief Set the WP1 field to a new value. */ 07073 #define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v)) 07074 /*@}*/ 07075 07076 /*! 07077 * @name Register AIPS_PACRI, field SP1[26] (RW) 07078 * 07079 * Determines whether the peripheral requires supervisor privilege level for 07080 * access. When this field is set, the master privilege level must indicate the 07081 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 07082 * be set. If not, access terminates with an error response and no peripheral 07083 * access initiates. 07084 * 07085 * Values: 07086 * - 0 - This peripheral does not require supervisor privilege level for 07087 * accesses. 07088 * - 1 - This peripheral requires supervisor privilege level for accesses. 07089 */ 07090 /*@{*/ 07091 #define BP_AIPS_PACRI_SP1 (26U) /*!< Bit position for AIPS_PACRI_SP1. */ 07092 #define BM_AIPS_PACRI_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRI_SP1. */ 07093 #define BS_AIPS_PACRI_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP1. */ 07094 07095 /*! @brief Read current value of the AIPS_PACRI_SP1 field. */ 07096 #define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1)) 07097 07098 /*! @brief Format value for bitfield AIPS_PACRI_SP1. */ 07099 #define BF_AIPS_PACRI_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP1) & BM_AIPS_PACRI_SP1) 07100 07101 /*! @brief Set the SP1 field to a new value. */ 07102 #define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v)) 07103 /*@}*/ 07104 07105 /*! 07106 * @name Register AIPS_PACRI, field TP0[28] (RW) 07107 * 07108 * Determines whether the peripheral allows accesses from an untrusted master. 07109 * When this bit is set and an access is attempted by an untrusted master, the 07110 * access terminates with an error response and no peripheral access initiates. 07111 * 07112 * Values: 07113 * - 0 - Accesses from an untrusted master are allowed. 07114 * - 1 - Accesses from an untrusted master are not allowed. 07115 */ 07116 /*@{*/ 07117 #define BP_AIPS_PACRI_TP0 (28U) /*!< Bit position for AIPS_PACRI_TP0. */ 07118 #define BM_AIPS_PACRI_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRI_TP0. */ 07119 #define BS_AIPS_PACRI_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP0. */ 07120 07121 /*! @brief Read current value of the AIPS_PACRI_TP0 field. */ 07122 #define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0)) 07123 07124 /*! @brief Format value for bitfield AIPS_PACRI_TP0. */ 07125 #define BF_AIPS_PACRI_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP0) & BM_AIPS_PACRI_TP0) 07126 07127 /*! @brief Set the TP0 field to a new value. */ 07128 #define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v)) 07129 /*@}*/ 07130 07131 /*! 07132 * @name Register AIPS_PACRI, field WP0[29] (RW) 07133 * 07134 * Determines whether the peripheral allows write accesses. When this field is 07135 * set and a write access is attempted, access terminates with an error response 07136 * and no peripheral access initiates. 07137 * 07138 * Values: 07139 * - 0 - This peripheral allows write accesses. 07140 * - 1 - This peripheral is write protected. 07141 */ 07142 /*@{*/ 07143 #define BP_AIPS_PACRI_WP0 (29U) /*!< Bit position for AIPS_PACRI_WP0. */ 07144 #define BM_AIPS_PACRI_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRI_WP0. */ 07145 #define BS_AIPS_PACRI_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP0. */ 07146 07147 /*! @brief Read current value of the AIPS_PACRI_WP0 field. */ 07148 #define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0)) 07149 07150 /*! @brief Format value for bitfield AIPS_PACRI_WP0. */ 07151 #define BF_AIPS_PACRI_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP0) & BM_AIPS_PACRI_WP0) 07152 07153 /*! @brief Set the WP0 field to a new value. */ 07154 #define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v)) 07155 /*@}*/ 07156 07157 /*! 07158 * @name Register AIPS_PACRI, field SP0[30] (RW) 07159 * 07160 * Determines whether the peripheral requires supervisor privilege level for 07161 * accesses. When this field is set, the master privilege level must indicate the 07162 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07163 * must be set. If not, access terminates with an error response and no peripheral 07164 * access initiates. 07165 * 07166 * Values: 07167 * - 0 - This peripheral does not require supervisor privilege level for 07168 * accesses. 07169 * - 1 - This peripheral requires supervisor privilege level for accesses. 07170 */ 07171 /*@{*/ 07172 #define BP_AIPS_PACRI_SP0 (30U) /*!< Bit position for AIPS_PACRI_SP0. */ 07173 #define BM_AIPS_PACRI_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRI_SP0. */ 07174 #define BS_AIPS_PACRI_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP0. */ 07175 07176 /*! @brief Read current value of the AIPS_PACRI_SP0 field. */ 07177 #define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0)) 07178 07179 /*! @brief Format value for bitfield AIPS_PACRI_SP0. */ 07180 #define BF_AIPS_PACRI_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP0) & BM_AIPS_PACRI_SP0) 07181 07182 /*! @brief Set the SP0 field to a new value. */ 07183 #define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v)) 07184 /*@}*/ 07185 07186 /******************************************************************************* 07187 * HW_AIPS_PACRJ - Peripheral Access Control Register 07188 ******************************************************************************/ 07189 07190 /*! 07191 * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) 07192 * 07193 * Reset value: 0x44444444U 07194 * 07195 * This section describes PACR registers E-P, which control peripheral slots 07196 * 32-127. See PACRPeripheral Access Control Register for the description of these 07197 * registers. 07198 */ 07199 typedef union _hw_aips_pacrj 07200 { 07201 uint32_t U; 07202 struct _hw_aips_pacrj_bitfields 07203 { 07204 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 07205 uint32_t WP7 : 1; /*!< [1] Write Protect */ 07206 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 07207 uint32_t RESERVED0 : 1; /*!< [3] */ 07208 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 07209 uint32_t WP6 : 1; /*!< [5] Write Protect */ 07210 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 07211 uint32_t RESERVED1 : 1; /*!< [7] */ 07212 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 07213 uint32_t WP5 : 1; /*!< [9] Write Protect */ 07214 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 07215 uint32_t RESERVED2 : 1; /*!< [11] */ 07216 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 07217 uint32_t WP4 : 1; /*!< [13] Write Protect */ 07218 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 07219 uint32_t RESERVED3 : 1; /*!< [15] */ 07220 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 07221 uint32_t WP3 : 1; /*!< [17] Write Protect */ 07222 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 07223 uint32_t RESERVED4 : 1; /*!< [19] */ 07224 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 07225 uint32_t WP2 : 1; /*!< [21] Write Protect */ 07226 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 07227 uint32_t RESERVED5 : 1; /*!< [23] */ 07228 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 07229 uint32_t WP1 : 1; /*!< [25] Write Protect */ 07230 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 07231 uint32_t RESERVED6 : 1; /*!< [27] */ 07232 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 07233 uint32_t WP0 : 1; /*!< [29] Write Protect */ 07234 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 07235 uint32_t RESERVED7 : 1; /*!< [31] */ 07236 } B; 07237 } hw_aips_pacrj_t; 07238 07239 /*! 07240 * @name Constants and macros for entire AIPS_PACRJ register 07241 */ 07242 /*@{*/ 07243 #define HW_AIPS_PACRJ_ADDR(x) ((x) + 0x54U) 07244 07245 #define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) 07246 #define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U) 07247 #define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v)) 07248 #define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) 07249 #define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) 07250 #define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) 07251 /*@}*/ 07252 07253 /* 07254 * Constants & macros for individual AIPS_PACRJ bitfields 07255 */ 07256 07257 /*! 07258 * @name Register AIPS_PACRJ, field TP7[0] (RW) 07259 * 07260 * Determines whether the peripheral allows accesses from an untrusted master. 07261 * When this field is set and an access is attempted by an untrusted master, the 07262 * access terminates with an error response and no peripheral access initiates. 07263 * 07264 * Values: 07265 * - 0 - Accesses from an untrusted master are allowed. 07266 * - 1 - Accesses from an untrusted master are not allowed. 07267 */ 07268 /*@{*/ 07269 #define BP_AIPS_PACRJ_TP7 (0U) /*!< Bit position for AIPS_PACRJ_TP7. */ 07270 #define BM_AIPS_PACRJ_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRJ_TP7. */ 07271 #define BS_AIPS_PACRJ_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP7. */ 07272 07273 /*! @brief Read current value of the AIPS_PACRJ_TP7 field. */ 07274 #define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7)) 07275 07276 /*! @brief Format value for bitfield AIPS_PACRJ_TP7. */ 07277 #define BF_AIPS_PACRJ_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP7) & BM_AIPS_PACRJ_TP7) 07278 07279 /*! @brief Set the TP7 field to a new value. */ 07280 #define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v)) 07281 /*@}*/ 07282 07283 /*! 07284 * @name Register AIPS_PACRJ, field WP7[1] (RW) 07285 * 07286 * Determines whether the peripheral allows write accesses. When this field is 07287 * set and a write access is attempted, access terminates with an error response 07288 * and no peripheral access initiates. 07289 * 07290 * Values: 07291 * - 0 - This peripheral allows write accesses. 07292 * - 1 - This peripheral is write protected. 07293 */ 07294 /*@{*/ 07295 #define BP_AIPS_PACRJ_WP7 (1U) /*!< Bit position for AIPS_PACRJ_WP7. */ 07296 #define BM_AIPS_PACRJ_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRJ_WP7. */ 07297 #define BS_AIPS_PACRJ_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP7. */ 07298 07299 /*! @brief Read current value of the AIPS_PACRJ_WP7 field. */ 07300 #define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7)) 07301 07302 /*! @brief Format value for bitfield AIPS_PACRJ_WP7. */ 07303 #define BF_AIPS_PACRJ_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP7) & BM_AIPS_PACRJ_WP7) 07304 07305 /*! @brief Set the WP7 field to a new value. */ 07306 #define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v)) 07307 /*@}*/ 07308 07309 /*! 07310 * @name Register AIPS_PACRJ, field SP7[2] (RW) 07311 * 07312 * Determines whether the peripheral requires supervisor privilege level for 07313 * accesses. When this field is set, the master privilege level must indicate the 07314 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07315 * must be set. If not, access terminates with an error response and no peripheral 07316 * access initiates. 07317 * 07318 * Values: 07319 * - 0 - This peripheral does not require supervisor privilege level for 07320 * accesses. 07321 * - 1 - This peripheral requires supervisor privilege level for accesses. 07322 */ 07323 /*@{*/ 07324 #define BP_AIPS_PACRJ_SP7 (2U) /*!< Bit position for AIPS_PACRJ_SP7. */ 07325 #define BM_AIPS_PACRJ_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRJ_SP7. */ 07326 #define BS_AIPS_PACRJ_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP7. */ 07327 07328 /*! @brief Read current value of the AIPS_PACRJ_SP7 field. */ 07329 #define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7)) 07330 07331 /*! @brief Format value for bitfield AIPS_PACRJ_SP7. */ 07332 #define BF_AIPS_PACRJ_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP7) & BM_AIPS_PACRJ_SP7) 07333 07334 /*! @brief Set the SP7 field to a new value. */ 07335 #define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v)) 07336 /*@}*/ 07337 07338 /*! 07339 * @name Register AIPS_PACRJ, field TP6[4] (RW) 07340 * 07341 * Determines whether the peripheral allows accesses from an untrusted master. 07342 * When this field is set and an access is attempted by an untrusted master, the 07343 * access terminates with an error response and no peripheral access initiates. 07344 * 07345 * Values: 07346 * - 0 - Accesses from an untrusted master are allowed. 07347 * - 1 - Accesses from an untrusted master are not allowed. 07348 */ 07349 /*@{*/ 07350 #define BP_AIPS_PACRJ_TP6 (4U) /*!< Bit position for AIPS_PACRJ_TP6. */ 07351 #define BM_AIPS_PACRJ_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRJ_TP6. */ 07352 #define BS_AIPS_PACRJ_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP6. */ 07353 07354 /*! @brief Read current value of the AIPS_PACRJ_TP6 field. */ 07355 #define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6)) 07356 07357 /*! @brief Format value for bitfield AIPS_PACRJ_TP6. */ 07358 #define BF_AIPS_PACRJ_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP6) & BM_AIPS_PACRJ_TP6) 07359 07360 /*! @brief Set the TP6 field to a new value. */ 07361 #define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v)) 07362 /*@}*/ 07363 07364 /*! 07365 * @name Register AIPS_PACRJ, field WP6[5] (RW) 07366 * 07367 * Determines whether the peripheral allows write accesses. When this field is 07368 * set and a write access is attempted, access terminates with an error response 07369 * and no peripheral access initiates. 07370 * 07371 * Values: 07372 * - 0 - This peripheral allows write accesses. 07373 * - 1 - This peripheral is write protected. 07374 */ 07375 /*@{*/ 07376 #define BP_AIPS_PACRJ_WP6 (5U) /*!< Bit position for AIPS_PACRJ_WP6. */ 07377 #define BM_AIPS_PACRJ_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRJ_WP6. */ 07378 #define BS_AIPS_PACRJ_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP6. */ 07379 07380 /*! @brief Read current value of the AIPS_PACRJ_WP6 field. */ 07381 #define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6)) 07382 07383 /*! @brief Format value for bitfield AIPS_PACRJ_WP6. */ 07384 #define BF_AIPS_PACRJ_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP6) & BM_AIPS_PACRJ_WP6) 07385 07386 /*! @brief Set the WP6 field to a new value. */ 07387 #define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v)) 07388 /*@}*/ 07389 07390 /*! 07391 * @name Register AIPS_PACRJ, field SP6[6] (RW) 07392 * 07393 * Determines whether the peripheral requires supervisor privilege level for 07394 * accesses. When this field is set, the master privilege level must indicate the 07395 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07396 * must be set. If not, access terminates with an error response and no peripheral 07397 * access initiates. 07398 * 07399 * Values: 07400 * - 0 - This peripheral does not require supervisor privilege level for 07401 * accesses. 07402 * - 1 - This peripheral requires supervisor privilege level for accesses. 07403 */ 07404 /*@{*/ 07405 #define BP_AIPS_PACRJ_SP6 (6U) /*!< Bit position for AIPS_PACRJ_SP6. */ 07406 #define BM_AIPS_PACRJ_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRJ_SP6. */ 07407 #define BS_AIPS_PACRJ_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP6. */ 07408 07409 /*! @brief Read current value of the AIPS_PACRJ_SP6 field. */ 07410 #define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6)) 07411 07412 /*! @brief Format value for bitfield AIPS_PACRJ_SP6. */ 07413 #define BF_AIPS_PACRJ_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP6) & BM_AIPS_PACRJ_SP6) 07414 07415 /*! @brief Set the SP6 field to a new value. */ 07416 #define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v)) 07417 /*@}*/ 07418 07419 /*! 07420 * @name Register AIPS_PACRJ, field TP5[8] (RW) 07421 * 07422 * Determines whether the peripheral allows accesses from an untrusted master. 07423 * When this field is set and an access is attempted by an untrusted master, the 07424 * access terminates with an error response and no peripheral access initiates. 07425 * 07426 * Values: 07427 * - 0 - Accesses from an untrusted master are allowed. 07428 * - 1 - Accesses from an untrusted master are not allowed. 07429 */ 07430 /*@{*/ 07431 #define BP_AIPS_PACRJ_TP5 (8U) /*!< Bit position for AIPS_PACRJ_TP5. */ 07432 #define BM_AIPS_PACRJ_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRJ_TP5. */ 07433 #define BS_AIPS_PACRJ_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP5. */ 07434 07435 /*! @brief Read current value of the AIPS_PACRJ_TP5 field. */ 07436 #define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5)) 07437 07438 /*! @brief Format value for bitfield AIPS_PACRJ_TP5. */ 07439 #define BF_AIPS_PACRJ_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP5) & BM_AIPS_PACRJ_TP5) 07440 07441 /*! @brief Set the TP5 field to a new value. */ 07442 #define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v)) 07443 /*@}*/ 07444 07445 /*! 07446 * @name Register AIPS_PACRJ, field WP5[9] (RW) 07447 * 07448 * Determines whether the peripheral allows write accesses. When this field is 07449 * set and a write access is attempted, access terminates with an error response 07450 * and no peripheral access initiates. 07451 * 07452 * Values: 07453 * - 0 - This peripheral allows write accesses. 07454 * - 1 - This peripheral is write protected. 07455 */ 07456 /*@{*/ 07457 #define BP_AIPS_PACRJ_WP5 (9U) /*!< Bit position for AIPS_PACRJ_WP5. */ 07458 #define BM_AIPS_PACRJ_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRJ_WP5. */ 07459 #define BS_AIPS_PACRJ_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP5. */ 07460 07461 /*! @brief Read current value of the AIPS_PACRJ_WP5 field. */ 07462 #define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5)) 07463 07464 /*! @brief Format value for bitfield AIPS_PACRJ_WP5. */ 07465 #define BF_AIPS_PACRJ_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP5) & BM_AIPS_PACRJ_WP5) 07466 07467 /*! @brief Set the WP5 field to a new value. */ 07468 #define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v)) 07469 /*@}*/ 07470 07471 /*! 07472 * @name Register AIPS_PACRJ, field SP5[10] (RW) 07473 * 07474 * Determines whether the peripheral requires supervisor privilege level for 07475 * accesses. When this field is set, the master privilege level must indicate the 07476 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07477 * must be set. If not, access terminates with an error response and no peripheral 07478 * access initiates. 07479 * 07480 * Values: 07481 * - 0 - This peripheral does not require supervisor privilege level for 07482 * accesses. 07483 * - 1 - This peripheral requires supervisor privilege level for accesses. 07484 */ 07485 /*@{*/ 07486 #define BP_AIPS_PACRJ_SP5 (10U) /*!< Bit position for AIPS_PACRJ_SP5. */ 07487 #define BM_AIPS_PACRJ_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRJ_SP5. */ 07488 #define BS_AIPS_PACRJ_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP5. */ 07489 07490 /*! @brief Read current value of the AIPS_PACRJ_SP5 field. */ 07491 #define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5)) 07492 07493 /*! @brief Format value for bitfield AIPS_PACRJ_SP5. */ 07494 #define BF_AIPS_PACRJ_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP5) & BM_AIPS_PACRJ_SP5) 07495 07496 /*! @brief Set the SP5 field to a new value. */ 07497 #define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v)) 07498 /*@}*/ 07499 07500 /*! 07501 * @name Register AIPS_PACRJ, field TP4[12] (RW) 07502 * 07503 * Determines whether the peripheral allows accesses from an untrusted master. 07504 * When this bit is set and an access is attempted by an untrusted master, the 07505 * access terminates with an error response and no peripheral access initiates. 07506 * 07507 * Values: 07508 * - 0 - Accesses from an untrusted master are allowed. 07509 * - 1 - Accesses from an untrusted master are not allowed. 07510 */ 07511 /*@{*/ 07512 #define BP_AIPS_PACRJ_TP4 (12U) /*!< Bit position for AIPS_PACRJ_TP4. */ 07513 #define BM_AIPS_PACRJ_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRJ_TP4. */ 07514 #define BS_AIPS_PACRJ_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP4. */ 07515 07516 /*! @brief Read current value of the AIPS_PACRJ_TP4 field. */ 07517 #define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4)) 07518 07519 /*! @brief Format value for bitfield AIPS_PACRJ_TP4. */ 07520 #define BF_AIPS_PACRJ_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP4) & BM_AIPS_PACRJ_TP4) 07521 07522 /*! @brief Set the TP4 field to a new value. */ 07523 #define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v)) 07524 /*@}*/ 07525 07526 /*! 07527 * @name Register AIPS_PACRJ, field WP4[13] (RW) 07528 * 07529 * Determines whether the peripheral allows write accesses. When this field is 07530 * set and a write access is attempted, access terminates with an error response 07531 * and no peripheral access initiates. 07532 * 07533 * Values: 07534 * - 0 - This peripheral allows write accesses. 07535 * - 1 - This peripheral is write protected. 07536 */ 07537 /*@{*/ 07538 #define BP_AIPS_PACRJ_WP4 (13U) /*!< Bit position for AIPS_PACRJ_WP4. */ 07539 #define BM_AIPS_PACRJ_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRJ_WP4. */ 07540 #define BS_AIPS_PACRJ_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP4. */ 07541 07542 /*! @brief Read current value of the AIPS_PACRJ_WP4 field. */ 07543 #define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4)) 07544 07545 /*! @brief Format value for bitfield AIPS_PACRJ_WP4. */ 07546 #define BF_AIPS_PACRJ_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP4) & BM_AIPS_PACRJ_WP4) 07547 07548 /*! @brief Set the WP4 field to a new value. */ 07549 #define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v)) 07550 /*@}*/ 07551 07552 /*! 07553 * @name Register AIPS_PACRJ, field SP4[14] (RW) 07554 * 07555 * Determines whether the peripheral requires supervisor privilege level for 07556 * access. When this bit is set, the master privilege level must indicate the 07557 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07558 * set. If not, access terminates with an error response and no peripheral access 07559 * initiates. 07560 * 07561 * Values: 07562 * - 0 - This peripheral does not require supervisor privilege level for 07563 * accesses. 07564 * - 1 - This peripheral requires supervisor privilege level for accesses. 07565 */ 07566 /*@{*/ 07567 #define BP_AIPS_PACRJ_SP4 (14U) /*!< Bit position for AIPS_PACRJ_SP4. */ 07568 #define BM_AIPS_PACRJ_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRJ_SP4. */ 07569 #define BS_AIPS_PACRJ_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP4. */ 07570 07571 /*! @brief Read current value of the AIPS_PACRJ_SP4 field. */ 07572 #define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4)) 07573 07574 /*! @brief Format value for bitfield AIPS_PACRJ_SP4. */ 07575 #define BF_AIPS_PACRJ_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP4) & BM_AIPS_PACRJ_SP4) 07576 07577 /*! @brief Set the SP4 field to a new value. */ 07578 #define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v)) 07579 /*@}*/ 07580 07581 /*! 07582 * @name Register AIPS_PACRJ, field TP3[16] (RW) 07583 * 07584 * Determines whether the peripheral allows accesses from an untrusted master. 07585 * When this field is set and an access is attempted by an untrusted master, the 07586 * access terminates with an error response and no peripheral access initiates. 07587 * 07588 * Values: 07589 * - 0 - Accesses from an untrusted master are allowed. 07590 * - 1 - Accesses from an untrusted master are not allowed. 07591 */ 07592 /*@{*/ 07593 #define BP_AIPS_PACRJ_TP3 (16U) /*!< Bit position for AIPS_PACRJ_TP3. */ 07594 #define BM_AIPS_PACRJ_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRJ_TP3. */ 07595 #define BS_AIPS_PACRJ_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP3. */ 07596 07597 /*! @brief Read current value of the AIPS_PACRJ_TP3 field. */ 07598 #define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3)) 07599 07600 /*! @brief Format value for bitfield AIPS_PACRJ_TP3. */ 07601 #define BF_AIPS_PACRJ_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP3) & BM_AIPS_PACRJ_TP3) 07602 07603 /*! @brief Set the TP3 field to a new value. */ 07604 #define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v)) 07605 /*@}*/ 07606 07607 /*! 07608 * @name Register AIPS_PACRJ, field WP3[17] (RW) 07609 * 07610 * Determines whether the peripheral allows write accesss. When this bit is set 07611 * and a write access is attempted, access terminates with an error response and 07612 * no peripheral access initiates. 07613 * 07614 * Values: 07615 * - 0 - This peripheral allows write accesses. 07616 * - 1 - This peripheral is write protected. 07617 */ 07618 /*@{*/ 07619 #define BP_AIPS_PACRJ_WP3 (17U) /*!< Bit position for AIPS_PACRJ_WP3. */ 07620 #define BM_AIPS_PACRJ_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRJ_WP3. */ 07621 #define BS_AIPS_PACRJ_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP3. */ 07622 07623 /*! @brief Read current value of the AIPS_PACRJ_WP3 field. */ 07624 #define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3)) 07625 07626 /*! @brief Format value for bitfield AIPS_PACRJ_WP3. */ 07627 #define BF_AIPS_PACRJ_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP3) & BM_AIPS_PACRJ_WP3) 07628 07629 /*! @brief Set the WP3 field to a new value. */ 07630 #define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v)) 07631 /*@}*/ 07632 07633 /*! 07634 * @name Register AIPS_PACRJ, field SP3[18] (RW) 07635 * 07636 * Determines whether the peripheral requires supervisor privilege level for 07637 * accesses. When this field is set, the master privilege level must indicate the 07638 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07639 * must be set. If not, access terminates with an error response and no peripheral 07640 * access initiates. 07641 * 07642 * Values: 07643 * - 0 - This peripheral does not require supervisor privilege level for 07644 * accesses. 07645 * - 1 - This peripheral requires supervisor privilege level for accesses. 07646 */ 07647 /*@{*/ 07648 #define BP_AIPS_PACRJ_SP3 (18U) /*!< Bit position for AIPS_PACRJ_SP3. */ 07649 #define BM_AIPS_PACRJ_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRJ_SP3. */ 07650 #define BS_AIPS_PACRJ_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP3. */ 07651 07652 /*! @brief Read current value of the AIPS_PACRJ_SP3 field. */ 07653 #define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3)) 07654 07655 /*! @brief Format value for bitfield AIPS_PACRJ_SP3. */ 07656 #define BF_AIPS_PACRJ_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP3) & BM_AIPS_PACRJ_SP3) 07657 07658 /*! @brief Set the SP3 field to a new value. */ 07659 #define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v)) 07660 /*@}*/ 07661 07662 /*! 07663 * @name Register AIPS_PACRJ, field TP2[20] (RW) 07664 * 07665 * Determines whether the peripheral allows accesses from an untrusted master. 07666 * When this bit is set and an access is attempted by an untrusted master, the 07667 * access terminates with an error response and no peripheral access initiates. 07668 * 07669 * Values: 07670 * - 0 - Accesses from an untrusted master are allowed. 07671 * - 1 - Accesses from an untrusted master are not allowed. 07672 */ 07673 /*@{*/ 07674 #define BP_AIPS_PACRJ_TP2 (20U) /*!< Bit position for AIPS_PACRJ_TP2. */ 07675 #define BM_AIPS_PACRJ_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRJ_TP2. */ 07676 #define BS_AIPS_PACRJ_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP2. */ 07677 07678 /*! @brief Read current value of the AIPS_PACRJ_TP2 field. */ 07679 #define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2)) 07680 07681 /*! @brief Format value for bitfield AIPS_PACRJ_TP2. */ 07682 #define BF_AIPS_PACRJ_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP2) & BM_AIPS_PACRJ_TP2) 07683 07684 /*! @brief Set the TP2 field to a new value. */ 07685 #define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v)) 07686 /*@}*/ 07687 07688 /*! 07689 * @name Register AIPS_PACRJ, field WP2[21] (RW) 07690 * 07691 * Determines whether the peripheral allows write accesses. When this field is 07692 * set and a write access is attempted, access terminates with an error response 07693 * and no peripheral access initiates. 07694 * 07695 * Values: 07696 * - 0 - This peripheral allows write accesses. 07697 * - 1 - This peripheral is write protected. 07698 */ 07699 /*@{*/ 07700 #define BP_AIPS_PACRJ_WP2 (21U) /*!< Bit position for AIPS_PACRJ_WP2. */ 07701 #define BM_AIPS_PACRJ_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRJ_WP2. */ 07702 #define BS_AIPS_PACRJ_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP2. */ 07703 07704 /*! @brief Read current value of the AIPS_PACRJ_WP2 field. */ 07705 #define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2)) 07706 07707 /*! @brief Format value for bitfield AIPS_PACRJ_WP2. */ 07708 #define BF_AIPS_PACRJ_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP2) & BM_AIPS_PACRJ_WP2) 07709 07710 /*! @brief Set the WP2 field to a new value. */ 07711 #define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v)) 07712 /*@}*/ 07713 07714 /*! 07715 * @name Register AIPS_PACRJ, field SP2[22] (RW) 07716 * 07717 * Determines whether the peripheral requires supervisor privilege level for 07718 * access. When this bit is set, the master privilege level must indicate the 07719 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07720 * set. If not, access terminates with an error response and no peripheral access 07721 * initiates. 07722 * 07723 * Values: 07724 * - 0 - This peripheral does not require supervisor privilege level for 07725 * accesses. 07726 * - 1 - This peripheral requires supervisor privilege level for accesses. 07727 */ 07728 /*@{*/ 07729 #define BP_AIPS_PACRJ_SP2 (22U) /*!< Bit position for AIPS_PACRJ_SP2. */ 07730 #define BM_AIPS_PACRJ_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRJ_SP2. */ 07731 #define BS_AIPS_PACRJ_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP2. */ 07732 07733 /*! @brief Read current value of the AIPS_PACRJ_SP2 field. */ 07734 #define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2)) 07735 07736 /*! @brief Format value for bitfield AIPS_PACRJ_SP2. */ 07737 #define BF_AIPS_PACRJ_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP2) & BM_AIPS_PACRJ_SP2) 07738 07739 /*! @brief Set the SP2 field to a new value. */ 07740 #define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v)) 07741 /*@}*/ 07742 07743 /*! 07744 * @name Register AIPS_PACRJ, field TP1[24] (RW) 07745 * 07746 * Determines whether the peripheral allows accesses from an untrusted master. 07747 * When this field is set and an access is attempted by an untrusted master, the 07748 * access terminates with an error response and no peripheral access initiates. 07749 * 07750 * Values: 07751 * - 0 - Accesses from an untrusted master are allowed. 07752 * - 1 - Accesses from an untrusted master are not allowed. 07753 */ 07754 /*@{*/ 07755 #define BP_AIPS_PACRJ_TP1 (24U) /*!< Bit position for AIPS_PACRJ_TP1. */ 07756 #define BM_AIPS_PACRJ_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRJ_TP1. */ 07757 #define BS_AIPS_PACRJ_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP1. */ 07758 07759 /*! @brief Read current value of the AIPS_PACRJ_TP1 field. */ 07760 #define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1)) 07761 07762 /*! @brief Format value for bitfield AIPS_PACRJ_TP1. */ 07763 #define BF_AIPS_PACRJ_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP1) & BM_AIPS_PACRJ_TP1) 07764 07765 /*! @brief Set the TP1 field to a new value. */ 07766 #define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v)) 07767 /*@}*/ 07768 07769 /*! 07770 * @name Register AIPS_PACRJ, field WP1[25] (RW) 07771 * 07772 * Determines whether the peripheral allows write accesses. When this field is 07773 * set and a write access is attempted, access terminates with an error response 07774 * and no peripheral access initiates. 07775 * 07776 * Values: 07777 * - 0 - This peripheral allows write accesses. 07778 * - 1 - This peripheral is write protected. 07779 */ 07780 /*@{*/ 07781 #define BP_AIPS_PACRJ_WP1 (25U) /*!< Bit position for AIPS_PACRJ_WP1. */ 07782 #define BM_AIPS_PACRJ_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRJ_WP1. */ 07783 #define BS_AIPS_PACRJ_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP1. */ 07784 07785 /*! @brief Read current value of the AIPS_PACRJ_WP1 field. */ 07786 #define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1)) 07787 07788 /*! @brief Format value for bitfield AIPS_PACRJ_WP1. */ 07789 #define BF_AIPS_PACRJ_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP1) & BM_AIPS_PACRJ_WP1) 07790 07791 /*! @brief Set the WP1 field to a new value. */ 07792 #define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v)) 07793 /*@}*/ 07794 07795 /*! 07796 * @name Register AIPS_PACRJ, field SP1[26] (RW) 07797 * 07798 * Determines whether the peripheral requires supervisor privilege level for 07799 * access. When this field is set, the master privilege level must indicate the 07800 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 07801 * be set. If not, access terminates with an error response and no peripheral 07802 * access initiates. 07803 * 07804 * Values: 07805 * - 0 - This peripheral does not require supervisor privilege level for 07806 * accesses. 07807 * - 1 - This peripheral requires supervisor privilege level for accesses. 07808 */ 07809 /*@{*/ 07810 #define BP_AIPS_PACRJ_SP1 (26U) /*!< Bit position for AIPS_PACRJ_SP1. */ 07811 #define BM_AIPS_PACRJ_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRJ_SP1. */ 07812 #define BS_AIPS_PACRJ_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP1. */ 07813 07814 /*! @brief Read current value of the AIPS_PACRJ_SP1 field. */ 07815 #define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1)) 07816 07817 /*! @brief Format value for bitfield AIPS_PACRJ_SP1. */ 07818 #define BF_AIPS_PACRJ_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP1) & BM_AIPS_PACRJ_SP1) 07819 07820 /*! @brief Set the SP1 field to a new value. */ 07821 #define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v)) 07822 /*@}*/ 07823 07824 /*! 07825 * @name Register AIPS_PACRJ, field TP0[28] (RW) 07826 * 07827 * Determines whether the peripheral allows accesses from an untrusted master. 07828 * When this bit is set and an access is attempted by an untrusted master, the 07829 * access terminates with an error response and no peripheral access initiates. 07830 * 07831 * Values: 07832 * - 0 - Accesses from an untrusted master are allowed. 07833 * - 1 - Accesses from an untrusted master are not allowed. 07834 */ 07835 /*@{*/ 07836 #define BP_AIPS_PACRJ_TP0 (28U) /*!< Bit position for AIPS_PACRJ_TP0. */ 07837 #define BM_AIPS_PACRJ_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRJ_TP0. */ 07838 #define BS_AIPS_PACRJ_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP0. */ 07839 07840 /*! @brief Read current value of the AIPS_PACRJ_TP0 field. */ 07841 #define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0)) 07842 07843 /*! @brief Format value for bitfield AIPS_PACRJ_TP0. */ 07844 #define BF_AIPS_PACRJ_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP0) & BM_AIPS_PACRJ_TP0) 07845 07846 /*! @brief Set the TP0 field to a new value. */ 07847 #define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v)) 07848 /*@}*/ 07849 07850 /*! 07851 * @name Register AIPS_PACRJ, field WP0[29] (RW) 07852 * 07853 * Determines whether the peripheral allows write accesses. When this field is 07854 * set and a write access is attempted, access terminates with an error response 07855 * and no peripheral access initiates. 07856 * 07857 * Values: 07858 * - 0 - This peripheral allows write accesses. 07859 * - 1 - This peripheral is write protected. 07860 */ 07861 /*@{*/ 07862 #define BP_AIPS_PACRJ_WP0 (29U) /*!< Bit position for AIPS_PACRJ_WP0. */ 07863 #define BM_AIPS_PACRJ_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRJ_WP0. */ 07864 #define BS_AIPS_PACRJ_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP0. */ 07865 07866 /*! @brief Read current value of the AIPS_PACRJ_WP0 field. */ 07867 #define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0)) 07868 07869 /*! @brief Format value for bitfield AIPS_PACRJ_WP0. */ 07870 #define BF_AIPS_PACRJ_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP0) & BM_AIPS_PACRJ_WP0) 07871 07872 /*! @brief Set the WP0 field to a new value. */ 07873 #define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v)) 07874 /*@}*/ 07875 07876 /*! 07877 * @name Register AIPS_PACRJ, field SP0[30] (RW) 07878 * 07879 * Determines whether the peripheral requires supervisor privilege level for 07880 * accesses. When this field is set, the master privilege level must indicate the 07881 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07882 * must be set. If not, access terminates with an error response and no peripheral 07883 * access initiates. 07884 * 07885 * Values: 07886 * - 0 - This peripheral does not require supervisor privilege level for 07887 * accesses. 07888 * - 1 - This peripheral requires supervisor privilege level for accesses. 07889 */ 07890 /*@{*/ 07891 #define BP_AIPS_PACRJ_SP0 (30U) /*!< Bit position for AIPS_PACRJ_SP0. */ 07892 #define BM_AIPS_PACRJ_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRJ_SP0. */ 07893 #define BS_AIPS_PACRJ_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP0. */ 07894 07895 /*! @brief Read current value of the AIPS_PACRJ_SP0 field. */ 07896 #define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0)) 07897 07898 /*! @brief Format value for bitfield AIPS_PACRJ_SP0. */ 07899 #define BF_AIPS_PACRJ_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP0) & BM_AIPS_PACRJ_SP0) 07900 07901 /*! @brief Set the SP0 field to a new value. */ 07902 #define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v)) 07903 /*@}*/ 07904 07905 /******************************************************************************* 07906 * HW_AIPS_PACRK - Peripheral Access Control Register 07907 ******************************************************************************/ 07908 07909 /*! 07910 * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) 07911 * 07912 * Reset value: 0x44444444U 07913 * 07914 * This section describes PACR registers E-P, which control peripheral slots 07915 * 32-127. See PACRPeripheral Access Control Register for the description of these 07916 * registers. 07917 */ 07918 typedef union _hw_aips_pacrk 07919 { 07920 uint32_t U; 07921 struct _hw_aips_pacrk_bitfields 07922 { 07923 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 07924 uint32_t WP7 : 1; /*!< [1] Write Protect */ 07925 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 07926 uint32_t RESERVED0 : 1; /*!< [3] */ 07927 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 07928 uint32_t WP6 : 1; /*!< [5] Write Protect */ 07929 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 07930 uint32_t RESERVED1 : 1; /*!< [7] */ 07931 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 07932 uint32_t WP5 : 1; /*!< [9] Write Protect */ 07933 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 07934 uint32_t RESERVED2 : 1; /*!< [11] */ 07935 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 07936 uint32_t WP4 : 1; /*!< [13] Write Protect */ 07937 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 07938 uint32_t RESERVED3 : 1; /*!< [15] */ 07939 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 07940 uint32_t WP3 : 1; /*!< [17] Write Protect */ 07941 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 07942 uint32_t RESERVED4 : 1; /*!< [19] */ 07943 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 07944 uint32_t WP2 : 1; /*!< [21] Write Protect */ 07945 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 07946 uint32_t RESERVED5 : 1; /*!< [23] */ 07947 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 07948 uint32_t WP1 : 1; /*!< [25] Write Protect */ 07949 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 07950 uint32_t RESERVED6 : 1; /*!< [27] */ 07951 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 07952 uint32_t WP0 : 1; /*!< [29] Write Protect */ 07953 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 07954 uint32_t RESERVED7 : 1; /*!< [31] */ 07955 } B; 07956 } hw_aips_pacrk_t; 07957 07958 /*! 07959 * @name Constants and macros for entire AIPS_PACRK register 07960 */ 07961 /*@{*/ 07962 #define HW_AIPS_PACRK_ADDR(x) ((x) + 0x58U) 07963 07964 #define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) 07965 #define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U) 07966 #define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v)) 07967 #define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) 07968 #define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) 07969 #define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) 07970 /*@}*/ 07971 07972 /* 07973 * Constants & macros for individual AIPS_PACRK bitfields 07974 */ 07975 07976 /*! 07977 * @name Register AIPS_PACRK, field TP7[0] (RW) 07978 * 07979 * Determines whether the peripheral allows accesses from an untrusted master. 07980 * When this field is set and an access is attempted by an untrusted master, the 07981 * access terminates with an error response and no peripheral access initiates. 07982 * 07983 * Values: 07984 * - 0 - Accesses from an untrusted master are allowed. 07985 * - 1 - Accesses from an untrusted master are not allowed. 07986 */ 07987 /*@{*/ 07988 #define BP_AIPS_PACRK_TP7 (0U) /*!< Bit position for AIPS_PACRK_TP7. */ 07989 #define BM_AIPS_PACRK_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRK_TP7. */ 07990 #define BS_AIPS_PACRK_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP7. */ 07991 07992 /*! @brief Read current value of the AIPS_PACRK_TP7 field. */ 07993 #define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7)) 07994 07995 /*! @brief Format value for bitfield AIPS_PACRK_TP7. */ 07996 #define BF_AIPS_PACRK_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP7) & BM_AIPS_PACRK_TP7) 07997 07998 /*! @brief Set the TP7 field to a new value. */ 07999 #define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v)) 08000 /*@}*/ 08001 08002 /*! 08003 * @name Register AIPS_PACRK, field WP7[1] (RW) 08004 * 08005 * Determines whether the peripheral allows write accesses. When this field is 08006 * set and a write access is attempted, access terminates with an error response 08007 * and no peripheral access initiates. 08008 * 08009 * Values: 08010 * - 0 - This peripheral allows write accesses. 08011 * - 1 - This peripheral is write protected. 08012 */ 08013 /*@{*/ 08014 #define BP_AIPS_PACRK_WP7 (1U) /*!< Bit position for AIPS_PACRK_WP7. */ 08015 #define BM_AIPS_PACRK_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRK_WP7. */ 08016 #define BS_AIPS_PACRK_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP7. */ 08017 08018 /*! @brief Read current value of the AIPS_PACRK_WP7 field. */ 08019 #define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7)) 08020 08021 /*! @brief Format value for bitfield AIPS_PACRK_WP7. */ 08022 #define BF_AIPS_PACRK_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP7) & BM_AIPS_PACRK_WP7) 08023 08024 /*! @brief Set the WP7 field to a new value. */ 08025 #define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v)) 08026 /*@}*/ 08027 08028 /*! 08029 * @name Register AIPS_PACRK, field SP7[2] (RW) 08030 * 08031 * Determines whether the peripheral requires supervisor privilege level for 08032 * accesses. When this field is set, the master privilege level must indicate the 08033 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08034 * must be set. If not, access terminates with an error response and no peripheral 08035 * access initiates. 08036 * 08037 * Values: 08038 * - 0 - This peripheral does not require supervisor privilege level for 08039 * accesses. 08040 * - 1 - This peripheral requires supervisor privilege level for accesses. 08041 */ 08042 /*@{*/ 08043 #define BP_AIPS_PACRK_SP7 (2U) /*!< Bit position for AIPS_PACRK_SP7. */ 08044 #define BM_AIPS_PACRK_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRK_SP7. */ 08045 #define BS_AIPS_PACRK_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP7. */ 08046 08047 /*! @brief Read current value of the AIPS_PACRK_SP7 field. */ 08048 #define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7)) 08049 08050 /*! @brief Format value for bitfield AIPS_PACRK_SP7. */ 08051 #define BF_AIPS_PACRK_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP7) & BM_AIPS_PACRK_SP7) 08052 08053 /*! @brief Set the SP7 field to a new value. */ 08054 #define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v)) 08055 /*@}*/ 08056 08057 /*! 08058 * @name Register AIPS_PACRK, field TP6[4] (RW) 08059 * 08060 * Determines whether the peripheral allows accesses from an untrusted master. 08061 * When this field is set and an access is attempted by an untrusted master, the 08062 * access terminates with an error response and no peripheral access initiates. 08063 * 08064 * Values: 08065 * - 0 - Accesses from an untrusted master are allowed. 08066 * - 1 - Accesses from an untrusted master are not allowed. 08067 */ 08068 /*@{*/ 08069 #define BP_AIPS_PACRK_TP6 (4U) /*!< Bit position for AIPS_PACRK_TP6. */ 08070 #define BM_AIPS_PACRK_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRK_TP6. */ 08071 #define BS_AIPS_PACRK_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP6. */ 08072 08073 /*! @brief Read current value of the AIPS_PACRK_TP6 field. */ 08074 #define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6)) 08075 08076 /*! @brief Format value for bitfield AIPS_PACRK_TP6. */ 08077 #define BF_AIPS_PACRK_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP6) & BM_AIPS_PACRK_TP6) 08078 08079 /*! @brief Set the TP6 field to a new value. */ 08080 #define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v)) 08081 /*@}*/ 08082 08083 /*! 08084 * @name Register AIPS_PACRK, field WP6[5] (RW) 08085 * 08086 * Determines whether the peripheral allows write accesses. When this field is 08087 * set and a write access is attempted, access terminates with an error response 08088 * and no peripheral access initiates. 08089 * 08090 * Values: 08091 * - 0 - This peripheral allows write accesses. 08092 * - 1 - This peripheral is write protected. 08093 */ 08094 /*@{*/ 08095 #define BP_AIPS_PACRK_WP6 (5U) /*!< Bit position for AIPS_PACRK_WP6. */ 08096 #define BM_AIPS_PACRK_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRK_WP6. */ 08097 #define BS_AIPS_PACRK_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP6. */ 08098 08099 /*! @brief Read current value of the AIPS_PACRK_WP6 field. */ 08100 #define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6)) 08101 08102 /*! @brief Format value for bitfield AIPS_PACRK_WP6. */ 08103 #define BF_AIPS_PACRK_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP6) & BM_AIPS_PACRK_WP6) 08104 08105 /*! @brief Set the WP6 field to a new value. */ 08106 #define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v)) 08107 /*@}*/ 08108 08109 /*! 08110 * @name Register AIPS_PACRK, field SP6[6] (RW) 08111 * 08112 * Determines whether the peripheral requires supervisor privilege level for 08113 * accesses. When this field is set, the master privilege level must indicate the 08114 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08115 * must be set. If not, access terminates with an error response and no peripheral 08116 * access initiates. 08117 * 08118 * Values: 08119 * - 0 - This peripheral does not require supervisor privilege level for 08120 * accesses. 08121 * - 1 - This peripheral requires supervisor privilege level for accesses. 08122 */ 08123 /*@{*/ 08124 #define BP_AIPS_PACRK_SP6 (6U) /*!< Bit position for AIPS_PACRK_SP6. */ 08125 #define BM_AIPS_PACRK_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRK_SP6. */ 08126 #define BS_AIPS_PACRK_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP6. */ 08127 08128 /*! @brief Read current value of the AIPS_PACRK_SP6 field. */ 08129 #define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6)) 08130 08131 /*! @brief Format value for bitfield AIPS_PACRK_SP6. */ 08132 #define BF_AIPS_PACRK_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP6) & BM_AIPS_PACRK_SP6) 08133 08134 /*! @brief Set the SP6 field to a new value. */ 08135 #define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v)) 08136 /*@}*/ 08137 08138 /*! 08139 * @name Register AIPS_PACRK, field TP5[8] (RW) 08140 * 08141 * Determines whether the peripheral allows accesses from an untrusted master. 08142 * When this field is set and an access is attempted by an untrusted master, the 08143 * access terminates with an error response and no peripheral access initiates. 08144 * 08145 * Values: 08146 * - 0 - Accesses from an untrusted master are allowed. 08147 * - 1 - Accesses from an untrusted master are not allowed. 08148 */ 08149 /*@{*/ 08150 #define BP_AIPS_PACRK_TP5 (8U) /*!< Bit position for AIPS_PACRK_TP5. */ 08151 #define BM_AIPS_PACRK_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRK_TP5. */ 08152 #define BS_AIPS_PACRK_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP5. */ 08153 08154 /*! @brief Read current value of the AIPS_PACRK_TP5 field. */ 08155 #define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5)) 08156 08157 /*! @brief Format value for bitfield AIPS_PACRK_TP5. */ 08158 #define BF_AIPS_PACRK_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP5) & BM_AIPS_PACRK_TP5) 08159 08160 /*! @brief Set the TP5 field to a new value. */ 08161 #define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v)) 08162 /*@}*/ 08163 08164 /*! 08165 * @name Register AIPS_PACRK, field WP5[9] (RW) 08166 * 08167 * Determines whether the peripheral allows write accesses. When this field is 08168 * set and a write access is attempted, access terminates with an error response 08169 * and no peripheral access initiates. 08170 * 08171 * Values: 08172 * - 0 - This peripheral allows write accesses. 08173 * - 1 - This peripheral is write protected. 08174 */ 08175 /*@{*/ 08176 #define BP_AIPS_PACRK_WP5 (9U) /*!< Bit position for AIPS_PACRK_WP5. */ 08177 #define BM_AIPS_PACRK_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRK_WP5. */ 08178 #define BS_AIPS_PACRK_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP5. */ 08179 08180 /*! @brief Read current value of the AIPS_PACRK_WP5 field. */ 08181 #define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5)) 08182 08183 /*! @brief Format value for bitfield AIPS_PACRK_WP5. */ 08184 #define BF_AIPS_PACRK_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP5) & BM_AIPS_PACRK_WP5) 08185 08186 /*! @brief Set the WP5 field to a new value. */ 08187 #define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v)) 08188 /*@}*/ 08189 08190 /*! 08191 * @name Register AIPS_PACRK, field SP5[10] (RW) 08192 * 08193 * Determines whether the peripheral requires supervisor privilege level for 08194 * accesses. When this field is set, the master privilege level must indicate the 08195 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08196 * must be set. If not, access terminates with an error response and no peripheral 08197 * access initiates. 08198 * 08199 * Values: 08200 * - 0 - This peripheral does not require supervisor privilege level for 08201 * accesses. 08202 * - 1 - This peripheral requires supervisor privilege level for accesses. 08203 */ 08204 /*@{*/ 08205 #define BP_AIPS_PACRK_SP5 (10U) /*!< Bit position for AIPS_PACRK_SP5. */ 08206 #define BM_AIPS_PACRK_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRK_SP5. */ 08207 #define BS_AIPS_PACRK_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP5. */ 08208 08209 /*! @brief Read current value of the AIPS_PACRK_SP5 field. */ 08210 #define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5)) 08211 08212 /*! @brief Format value for bitfield AIPS_PACRK_SP5. */ 08213 #define BF_AIPS_PACRK_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP5) & BM_AIPS_PACRK_SP5) 08214 08215 /*! @brief Set the SP5 field to a new value. */ 08216 #define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v)) 08217 /*@}*/ 08218 08219 /*! 08220 * @name Register AIPS_PACRK, field TP4[12] (RW) 08221 * 08222 * Determines whether the peripheral allows accesses from an untrusted master. 08223 * When this bit is set and an access is attempted by an untrusted master, the 08224 * access terminates with an error response and no peripheral access initiates. 08225 * 08226 * Values: 08227 * - 0 - Accesses from an untrusted master are allowed. 08228 * - 1 - Accesses from an untrusted master are not allowed. 08229 */ 08230 /*@{*/ 08231 #define BP_AIPS_PACRK_TP4 (12U) /*!< Bit position for AIPS_PACRK_TP4. */ 08232 #define BM_AIPS_PACRK_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRK_TP4. */ 08233 #define BS_AIPS_PACRK_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP4. */ 08234 08235 /*! @brief Read current value of the AIPS_PACRK_TP4 field. */ 08236 #define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4)) 08237 08238 /*! @brief Format value for bitfield AIPS_PACRK_TP4. */ 08239 #define BF_AIPS_PACRK_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP4) & BM_AIPS_PACRK_TP4) 08240 08241 /*! @brief Set the TP4 field to a new value. */ 08242 #define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v)) 08243 /*@}*/ 08244 08245 /*! 08246 * @name Register AIPS_PACRK, field WP4[13] (RW) 08247 * 08248 * Determines whether the peripheral allows write accesses. When this field is 08249 * set and a write access is attempted, access terminates with an error response 08250 * and no peripheral access initiates. 08251 * 08252 * Values: 08253 * - 0 - This peripheral allows write accesses. 08254 * - 1 - This peripheral is write protected. 08255 */ 08256 /*@{*/ 08257 #define BP_AIPS_PACRK_WP4 (13U) /*!< Bit position for AIPS_PACRK_WP4. */ 08258 #define BM_AIPS_PACRK_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRK_WP4. */ 08259 #define BS_AIPS_PACRK_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP4. */ 08260 08261 /*! @brief Read current value of the AIPS_PACRK_WP4 field. */ 08262 #define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4)) 08263 08264 /*! @brief Format value for bitfield AIPS_PACRK_WP4. */ 08265 #define BF_AIPS_PACRK_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP4) & BM_AIPS_PACRK_WP4) 08266 08267 /*! @brief Set the WP4 field to a new value. */ 08268 #define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v)) 08269 /*@}*/ 08270 08271 /*! 08272 * @name Register AIPS_PACRK, field SP4[14] (RW) 08273 * 08274 * Determines whether the peripheral requires supervisor privilege level for 08275 * access. When this bit is set, the master privilege level must indicate the 08276 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 08277 * set. If not, access terminates with an error response and no peripheral access 08278 * initiates. 08279 * 08280 * Values: 08281 * - 0 - This peripheral does not require supervisor privilege level for 08282 * accesses. 08283 * - 1 - This peripheral requires supervisor privilege level for accesses. 08284 */ 08285 /*@{*/ 08286 #define BP_AIPS_PACRK_SP4 (14U) /*!< Bit position for AIPS_PACRK_SP4. */ 08287 #define BM_AIPS_PACRK_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRK_SP4. */ 08288 #define BS_AIPS_PACRK_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP4. */ 08289 08290 /*! @brief Read current value of the AIPS_PACRK_SP4 field. */ 08291 #define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4)) 08292 08293 /*! @brief Format value for bitfield AIPS_PACRK_SP4. */ 08294 #define BF_AIPS_PACRK_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP4) & BM_AIPS_PACRK_SP4) 08295 08296 /*! @brief Set the SP4 field to a new value. */ 08297 #define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v)) 08298 /*@}*/ 08299 08300 /*! 08301 * @name Register AIPS_PACRK, field TP3[16] (RW) 08302 * 08303 * Determines whether the peripheral allows accesses from an untrusted master. 08304 * When this field is set and an access is attempted by an untrusted master, the 08305 * access terminates with an error response and no peripheral access initiates. 08306 * 08307 * Values: 08308 * - 0 - Accesses from an untrusted master are allowed. 08309 * - 1 - Accesses from an untrusted master are not allowed. 08310 */ 08311 /*@{*/ 08312 #define BP_AIPS_PACRK_TP3 (16U) /*!< Bit position for AIPS_PACRK_TP3. */ 08313 #define BM_AIPS_PACRK_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRK_TP3. */ 08314 #define BS_AIPS_PACRK_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP3. */ 08315 08316 /*! @brief Read current value of the AIPS_PACRK_TP3 field. */ 08317 #define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3)) 08318 08319 /*! @brief Format value for bitfield AIPS_PACRK_TP3. */ 08320 #define BF_AIPS_PACRK_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP3) & BM_AIPS_PACRK_TP3) 08321 08322 /*! @brief Set the TP3 field to a new value. */ 08323 #define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v)) 08324 /*@}*/ 08325 08326 /*! 08327 * @name Register AIPS_PACRK, field WP3[17] (RW) 08328 * 08329 * Determines whether the peripheral allows write accesss. When this bit is set 08330 * and a write access is attempted, access terminates with an error response and 08331 * no peripheral access initiates. 08332 * 08333 * Values: 08334 * - 0 - This peripheral allows write accesses. 08335 * - 1 - This peripheral is write protected. 08336 */ 08337 /*@{*/ 08338 #define BP_AIPS_PACRK_WP3 (17U) /*!< Bit position for AIPS_PACRK_WP3. */ 08339 #define BM_AIPS_PACRK_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRK_WP3. */ 08340 #define BS_AIPS_PACRK_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP3. */ 08341 08342 /*! @brief Read current value of the AIPS_PACRK_WP3 field. */ 08343 #define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3)) 08344 08345 /*! @brief Format value for bitfield AIPS_PACRK_WP3. */ 08346 #define BF_AIPS_PACRK_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP3) & BM_AIPS_PACRK_WP3) 08347 08348 /*! @brief Set the WP3 field to a new value. */ 08349 #define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v)) 08350 /*@}*/ 08351 08352 /*! 08353 * @name Register AIPS_PACRK, field SP3[18] (RW) 08354 * 08355 * Determines whether the peripheral requires supervisor privilege level for 08356 * accesses. When this field is set, the master privilege level must indicate the 08357 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08358 * must be set. If not, access terminates with an error response and no peripheral 08359 * access initiates. 08360 * 08361 * Values: 08362 * - 0 - This peripheral does not require supervisor privilege level for 08363 * accesses. 08364 * - 1 - This peripheral requires supervisor privilege level for accesses. 08365 */ 08366 /*@{*/ 08367 #define BP_AIPS_PACRK_SP3 (18U) /*!< Bit position for AIPS_PACRK_SP3. */ 08368 #define BM_AIPS_PACRK_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRK_SP3. */ 08369 #define BS_AIPS_PACRK_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP3. */ 08370 08371 /*! @brief Read current value of the AIPS_PACRK_SP3 field. */ 08372 #define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3)) 08373 08374 /*! @brief Format value for bitfield AIPS_PACRK_SP3. */ 08375 #define BF_AIPS_PACRK_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP3) & BM_AIPS_PACRK_SP3) 08376 08377 /*! @brief Set the SP3 field to a new value. */ 08378 #define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v)) 08379 /*@}*/ 08380 08381 /*! 08382 * @name Register AIPS_PACRK, field TP2[20] (RW) 08383 * 08384 * Determines whether the peripheral allows accesses from an untrusted master. 08385 * When this bit is set and an access is attempted by an untrusted master, the 08386 * access terminates with an error response and no peripheral access initiates. 08387 * 08388 * Values: 08389 * - 0 - Accesses from an untrusted master are allowed. 08390 * - 1 - Accesses from an untrusted master are not allowed. 08391 */ 08392 /*@{*/ 08393 #define BP_AIPS_PACRK_TP2 (20U) /*!< Bit position for AIPS_PACRK_TP2. */ 08394 #define BM_AIPS_PACRK_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRK_TP2. */ 08395 #define BS_AIPS_PACRK_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP2. */ 08396 08397 /*! @brief Read current value of the AIPS_PACRK_TP2 field. */ 08398 #define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2)) 08399 08400 /*! @brief Format value for bitfield AIPS_PACRK_TP2. */ 08401 #define BF_AIPS_PACRK_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP2) & BM_AIPS_PACRK_TP2) 08402 08403 /*! @brief Set the TP2 field to a new value. */ 08404 #define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v)) 08405 /*@}*/ 08406 08407 /*! 08408 * @name Register AIPS_PACRK, field WP2[21] (RW) 08409 * 08410 * Determines whether the peripheral allows write accesses. When this field is 08411 * set and a write access is attempted, access terminates with an error response 08412 * and no peripheral access initiates. 08413 * 08414 * Values: 08415 * - 0 - This peripheral allows write accesses. 08416 * - 1 - This peripheral is write protected. 08417 */ 08418 /*@{*/ 08419 #define BP_AIPS_PACRK_WP2 (21U) /*!< Bit position for AIPS_PACRK_WP2. */ 08420 #define BM_AIPS_PACRK_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRK_WP2. */ 08421 #define BS_AIPS_PACRK_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP2. */ 08422 08423 /*! @brief Read current value of the AIPS_PACRK_WP2 field. */ 08424 #define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2)) 08425 08426 /*! @brief Format value for bitfield AIPS_PACRK_WP2. */ 08427 #define BF_AIPS_PACRK_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP2) & BM_AIPS_PACRK_WP2) 08428 08429 /*! @brief Set the WP2 field to a new value. */ 08430 #define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v)) 08431 /*@}*/ 08432 08433 /*! 08434 * @name Register AIPS_PACRK, field SP2[22] (RW) 08435 * 08436 * Determines whether the peripheral requires supervisor privilege level for 08437 * access. When this bit is set, the master privilege level must indicate the 08438 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 08439 * set. If not, access terminates with an error response and no peripheral access 08440 * initiates. 08441 * 08442 * Values: 08443 * - 0 - This peripheral does not require supervisor privilege level for 08444 * accesses. 08445 * - 1 - This peripheral requires supervisor privilege level for accesses. 08446 */ 08447 /*@{*/ 08448 #define BP_AIPS_PACRK_SP2 (22U) /*!< Bit position for AIPS_PACRK_SP2. */ 08449 #define BM_AIPS_PACRK_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRK_SP2. */ 08450 #define BS_AIPS_PACRK_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP2. */ 08451 08452 /*! @brief Read current value of the AIPS_PACRK_SP2 field. */ 08453 #define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2)) 08454 08455 /*! @brief Format value for bitfield AIPS_PACRK_SP2. */ 08456 #define BF_AIPS_PACRK_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP2) & BM_AIPS_PACRK_SP2) 08457 08458 /*! @brief Set the SP2 field to a new value. */ 08459 #define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v)) 08460 /*@}*/ 08461 08462 /*! 08463 * @name Register AIPS_PACRK, field TP1[24] (RW) 08464 * 08465 * Determines whether the peripheral allows accesses from an untrusted master. 08466 * When this field is set and an access is attempted by an untrusted master, the 08467 * access terminates with an error response and no peripheral access initiates. 08468 * 08469 * Values: 08470 * - 0 - Accesses from an untrusted master are allowed. 08471 * - 1 - Accesses from an untrusted master are not allowed. 08472 */ 08473 /*@{*/ 08474 #define BP_AIPS_PACRK_TP1 (24U) /*!< Bit position for AIPS_PACRK_TP1. */ 08475 #define BM_AIPS_PACRK_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRK_TP1. */ 08476 #define BS_AIPS_PACRK_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP1. */ 08477 08478 /*! @brief Read current value of the AIPS_PACRK_TP1 field. */ 08479 #define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1)) 08480 08481 /*! @brief Format value for bitfield AIPS_PACRK_TP1. */ 08482 #define BF_AIPS_PACRK_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP1) & BM_AIPS_PACRK_TP1) 08483 08484 /*! @brief Set the TP1 field to a new value. */ 08485 #define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v)) 08486 /*@}*/ 08487 08488 /*! 08489 * @name Register AIPS_PACRK, field WP1[25] (RW) 08490 * 08491 * Determines whether the peripheral allows write accesses. When this field is 08492 * set and a write access is attempted, access terminates with an error response 08493 * and no peripheral access initiates. 08494 * 08495 * Values: 08496 * - 0 - This peripheral allows write accesses. 08497 * - 1 - This peripheral is write protected. 08498 */ 08499 /*@{*/ 08500 #define BP_AIPS_PACRK_WP1 (25U) /*!< Bit position for AIPS_PACRK_WP1. */ 08501 #define BM_AIPS_PACRK_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRK_WP1. */ 08502 #define BS_AIPS_PACRK_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP1. */ 08503 08504 /*! @brief Read current value of the AIPS_PACRK_WP1 field. */ 08505 #define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1)) 08506 08507 /*! @brief Format value for bitfield AIPS_PACRK_WP1. */ 08508 #define BF_AIPS_PACRK_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP1) & BM_AIPS_PACRK_WP1) 08509 08510 /*! @brief Set the WP1 field to a new value. */ 08511 #define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v)) 08512 /*@}*/ 08513 08514 /*! 08515 * @name Register AIPS_PACRK, field SP1[26] (RW) 08516 * 08517 * Determines whether the peripheral requires supervisor privilege level for 08518 * access. When this field is set, the master privilege level must indicate the 08519 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 08520 * be set. If not, access terminates with an error response and no peripheral 08521 * access initiates. 08522 * 08523 * Values: 08524 * - 0 - This peripheral does not require supervisor privilege level for 08525 * accesses. 08526 * - 1 - This peripheral requires supervisor privilege level for accesses. 08527 */ 08528 /*@{*/ 08529 #define BP_AIPS_PACRK_SP1 (26U) /*!< Bit position for AIPS_PACRK_SP1. */ 08530 #define BM_AIPS_PACRK_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRK_SP1. */ 08531 #define BS_AIPS_PACRK_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP1. */ 08532 08533 /*! @brief Read current value of the AIPS_PACRK_SP1 field. */ 08534 #define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1)) 08535 08536 /*! @brief Format value for bitfield AIPS_PACRK_SP1. */ 08537 #define BF_AIPS_PACRK_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP1) & BM_AIPS_PACRK_SP1) 08538 08539 /*! @brief Set the SP1 field to a new value. */ 08540 #define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v)) 08541 /*@}*/ 08542 08543 /*! 08544 * @name Register AIPS_PACRK, field TP0[28] (RW) 08545 * 08546 * Determines whether the peripheral allows accesses from an untrusted master. 08547 * When this bit is set and an access is attempted by an untrusted master, the 08548 * access terminates with an error response and no peripheral access initiates. 08549 * 08550 * Values: 08551 * - 0 - Accesses from an untrusted master are allowed. 08552 * - 1 - Accesses from an untrusted master are not allowed. 08553 */ 08554 /*@{*/ 08555 #define BP_AIPS_PACRK_TP0 (28U) /*!< Bit position for AIPS_PACRK_TP0. */ 08556 #define BM_AIPS_PACRK_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRK_TP0. */ 08557 #define BS_AIPS_PACRK_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP0. */ 08558 08559 /*! @brief Read current value of the AIPS_PACRK_TP0 field. */ 08560 #define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0)) 08561 08562 /*! @brief Format value for bitfield AIPS_PACRK_TP0. */ 08563 #define BF_AIPS_PACRK_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP0) & BM_AIPS_PACRK_TP0) 08564 08565 /*! @brief Set the TP0 field to a new value. */ 08566 #define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v)) 08567 /*@}*/ 08568 08569 /*! 08570 * @name Register AIPS_PACRK, field WP0[29] (RW) 08571 * 08572 * Determines whether the peripheral allows write accesses. When this field is 08573 * set and a write access is attempted, access terminates with an error response 08574 * and no peripheral access initiates. 08575 * 08576 * Values: 08577 * - 0 - This peripheral allows write accesses. 08578 * - 1 - This peripheral is write protected. 08579 */ 08580 /*@{*/ 08581 #define BP_AIPS_PACRK_WP0 (29U) /*!< Bit position for AIPS_PACRK_WP0. */ 08582 #define BM_AIPS_PACRK_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRK_WP0. */ 08583 #define BS_AIPS_PACRK_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP0. */ 08584 08585 /*! @brief Read current value of the AIPS_PACRK_WP0 field. */ 08586 #define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0)) 08587 08588 /*! @brief Format value for bitfield AIPS_PACRK_WP0. */ 08589 #define BF_AIPS_PACRK_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP0) & BM_AIPS_PACRK_WP0) 08590 08591 /*! @brief Set the WP0 field to a new value. */ 08592 #define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v)) 08593 /*@}*/ 08594 08595 /*! 08596 * @name Register AIPS_PACRK, field SP0[30] (RW) 08597 * 08598 * Determines whether the peripheral requires supervisor privilege level for 08599 * accesses. When this field is set, the master privilege level must indicate the 08600 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08601 * must be set. If not, access terminates with an error response and no peripheral 08602 * access initiates. 08603 * 08604 * Values: 08605 * - 0 - This peripheral does not require supervisor privilege level for 08606 * accesses. 08607 * - 1 - This peripheral requires supervisor privilege level for accesses. 08608 */ 08609 /*@{*/ 08610 #define BP_AIPS_PACRK_SP0 (30U) /*!< Bit position for AIPS_PACRK_SP0. */ 08611 #define BM_AIPS_PACRK_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRK_SP0. */ 08612 #define BS_AIPS_PACRK_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP0. */ 08613 08614 /*! @brief Read current value of the AIPS_PACRK_SP0 field. */ 08615 #define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0)) 08616 08617 /*! @brief Format value for bitfield AIPS_PACRK_SP0. */ 08618 #define BF_AIPS_PACRK_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP0) & BM_AIPS_PACRK_SP0) 08619 08620 /*! @brief Set the SP0 field to a new value. */ 08621 #define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v)) 08622 /*@}*/ 08623 08624 /******************************************************************************* 08625 * HW_AIPS_PACRL - Peripheral Access Control Register 08626 ******************************************************************************/ 08627 08628 /*! 08629 * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) 08630 * 08631 * Reset value: 0x44444444U 08632 * 08633 * This section describes PACR registers E-P, which control peripheral slots 08634 * 32-127. See PACRPeripheral Access Control Register for the description of these 08635 * registers. 08636 */ 08637 typedef union _hw_aips_pacrl 08638 { 08639 uint32_t U; 08640 struct _hw_aips_pacrl_bitfields 08641 { 08642 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 08643 uint32_t WP7 : 1; /*!< [1] Write Protect */ 08644 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 08645 uint32_t RESERVED0 : 1; /*!< [3] */ 08646 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 08647 uint32_t WP6 : 1; /*!< [5] Write Protect */ 08648 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 08649 uint32_t RESERVED1 : 1; /*!< [7] */ 08650 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 08651 uint32_t WP5 : 1; /*!< [9] Write Protect */ 08652 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 08653 uint32_t RESERVED2 : 1; /*!< [11] */ 08654 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 08655 uint32_t WP4 : 1; /*!< [13] Write Protect */ 08656 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 08657 uint32_t RESERVED3 : 1; /*!< [15] */ 08658 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 08659 uint32_t WP3 : 1; /*!< [17] Write Protect */ 08660 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 08661 uint32_t RESERVED4 : 1; /*!< [19] */ 08662 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 08663 uint32_t WP2 : 1; /*!< [21] Write Protect */ 08664 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 08665 uint32_t RESERVED5 : 1; /*!< [23] */ 08666 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 08667 uint32_t WP1 : 1; /*!< [25] Write Protect */ 08668 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 08669 uint32_t RESERVED6 : 1; /*!< [27] */ 08670 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 08671 uint32_t WP0 : 1; /*!< [29] Write Protect */ 08672 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 08673 uint32_t RESERVED7 : 1; /*!< [31] */ 08674 } B; 08675 } hw_aips_pacrl_t; 08676 08677 /*! 08678 * @name Constants and macros for entire AIPS_PACRL register 08679 */ 08680 /*@{*/ 08681 #define HW_AIPS_PACRL_ADDR(x) ((x) + 0x5CU) 08682 08683 #define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) 08684 #define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U) 08685 #define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v)) 08686 #define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) 08687 #define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) 08688 #define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) 08689 /*@}*/ 08690 08691 /* 08692 * Constants & macros for individual AIPS_PACRL bitfields 08693 */ 08694 08695 /*! 08696 * @name Register AIPS_PACRL, field TP7[0] (RW) 08697 * 08698 * Determines whether the peripheral allows accesses from an untrusted master. 08699 * When this field is set and an access is attempted by an untrusted master, the 08700 * access terminates with an error response and no peripheral access initiates. 08701 * 08702 * Values: 08703 * - 0 - Accesses from an untrusted master are allowed. 08704 * - 1 - Accesses from an untrusted master are not allowed. 08705 */ 08706 /*@{*/ 08707 #define BP_AIPS_PACRL_TP7 (0U) /*!< Bit position for AIPS_PACRL_TP7. */ 08708 #define BM_AIPS_PACRL_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRL_TP7. */ 08709 #define BS_AIPS_PACRL_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP7. */ 08710 08711 /*! @brief Read current value of the AIPS_PACRL_TP7 field. */ 08712 #define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7)) 08713 08714 /*! @brief Format value for bitfield AIPS_PACRL_TP7. */ 08715 #define BF_AIPS_PACRL_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP7) & BM_AIPS_PACRL_TP7) 08716 08717 /*! @brief Set the TP7 field to a new value. */ 08718 #define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v)) 08719 /*@}*/ 08720 08721 /*! 08722 * @name Register AIPS_PACRL, field WP7[1] (RW) 08723 * 08724 * Determines whether the peripheral allows write accesses. When this field is 08725 * set and a write access is attempted, access terminates with an error response 08726 * and no peripheral access initiates. 08727 * 08728 * Values: 08729 * - 0 - This peripheral allows write accesses. 08730 * - 1 - This peripheral is write protected. 08731 */ 08732 /*@{*/ 08733 #define BP_AIPS_PACRL_WP7 (1U) /*!< Bit position for AIPS_PACRL_WP7. */ 08734 #define BM_AIPS_PACRL_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRL_WP7. */ 08735 #define BS_AIPS_PACRL_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP7. */ 08736 08737 /*! @brief Read current value of the AIPS_PACRL_WP7 field. */ 08738 #define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7)) 08739 08740 /*! @brief Format value for bitfield AIPS_PACRL_WP7. */ 08741 #define BF_AIPS_PACRL_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP7) & BM_AIPS_PACRL_WP7) 08742 08743 /*! @brief Set the WP7 field to a new value. */ 08744 #define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v)) 08745 /*@}*/ 08746 08747 /*! 08748 * @name Register AIPS_PACRL, field SP7[2] (RW) 08749 * 08750 * Determines whether the peripheral requires supervisor privilege level for 08751 * accesses. When this field is set, the master privilege level must indicate the 08752 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08753 * must be set. If not, access terminates with an error response and no peripheral 08754 * access initiates. 08755 * 08756 * Values: 08757 * - 0 - This peripheral does not require supervisor privilege level for 08758 * accesses. 08759 * - 1 - This peripheral requires supervisor privilege level for accesses. 08760 */ 08761 /*@{*/ 08762 #define BP_AIPS_PACRL_SP7 (2U) /*!< Bit position for AIPS_PACRL_SP7. */ 08763 #define BM_AIPS_PACRL_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRL_SP7. */ 08764 #define BS_AIPS_PACRL_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP7. */ 08765 08766 /*! @brief Read current value of the AIPS_PACRL_SP7 field. */ 08767 #define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7)) 08768 08769 /*! @brief Format value for bitfield AIPS_PACRL_SP7. */ 08770 #define BF_AIPS_PACRL_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP7) & BM_AIPS_PACRL_SP7) 08771 08772 /*! @brief Set the SP7 field to a new value. */ 08773 #define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v)) 08774 /*@}*/ 08775 08776 /*! 08777 * @name Register AIPS_PACRL, field TP6[4] (RW) 08778 * 08779 * Determines whether the peripheral allows accesses from an untrusted master. 08780 * When this field is set and an access is attempted by an untrusted master, the 08781 * access terminates with an error response and no peripheral access initiates. 08782 * 08783 * Values: 08784 * - 0 - Accesses from an untrusted master are allowed. 08785 * - 1 - Accesses from an untrusted master are not allowed. 08786 */ 08787 /*@{*/ 08788 #define BP_AIPS_PACRL_TP6 (4U) /*!< Bit position for AIPS_PACRL_TP6. */ 08789 #define BM_AIPS_PACRL_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRL_TP6. */ 08790 #define BS_AIPS_PACRL_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP6. */ 08791 08792 /*! @brief Read current value of the AIPS_PACRL_TP6 field. */ 08793 #define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6)) 08794 08795 /*! @brief Format value for bitfield AIPS_PACRL_TP6. */ 08796 #define BF_AIPS_PACRL_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP6) & BM_AIPS_PACRL_TP6) 08797 08798 /*! @brief Set the TP6 field to a new value. */ 08799 #define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v)) 08800 /*@}*/ 08801 08802 /*! 08803 * @name Register AIPS_PACRL, field WP6[5] (RW) 08804 * 08805 * Determines whether the peripheral allows write accesses. When this field is 08806 * set and a write access is attempted, access terminates with an error response 08807 * and no peripheral access initiates. 08808 * 08809 * Values: 08810 * - 0 - This peripheral allows write accesses. 08811 * - 1 - This peripheral is write protected. 08812 */ 08813 /*@{*/ 08814 #define BP_AIPS_PACRL_WP6 (5U) /*!< Bit position for AIPS_PACRL_WP6. */ 08815 #define BM_AIPS_PACRL_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRL_WP6. */ 08816 #define BS_AIPS_PACRL_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP6. */ 08817 08818 /*! @brief Read current value of the AIPS_PACRL_WP6 field. */ 08819 #define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6)) 08820 08821 /*! @brief Format value for bitfield AIPS_PACRL_WP6. */ 08822 #define BF_AIPS_PACRL_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP6) & BM_AIPS_PACRL_WP6) 08823 08824 /*! @brief Set the WP6 field to a new value. */ 08825 #define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v)) 08826 /*@}*/ 08827 08828 /*! 08829 * @name Register AIPS_PACRL, field SP6[6] (RW) 08830 * 08831 * Determines whether the peripheral requires supervisor privilege level for 08832 * accesses. When this field is set, the master privilege level must indicate the 08833 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08834 * must be set. If not, access terminates with an error response and no peripheral 08835 * access initiates. 08836 * 08837 * Values: 08838 * - 0 - This peripheral does not require supervisor privilege level for 08839 * accesses. 08840 * - 1 - This peripheral requires supervisor privilege level for accesses. 08841 */ 08842 /*@{*/ 08843 #define BP_AIPS_PACRL_SP6 (6U) /*!< Bit position for AIPS_PACRL_SP6. */ 08844 #define BM_AIPS_PACRL_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRL_SP6. */ 08845 #define BS_AIPS_PACRL_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP6. */ 08846 08847 /*! @brief Read current value of the AIPS_PACRL_SP6 field. */ 08848 #define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6)) 08849 08850 /*! @brief Format value for bitfield AIPS_PACRL_SP6. */ 08851 #define BF_AIPS_PACRL_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP6) & BM_AIPS_PACRL_SP6) 08852 08853 /*! @brief Set the SP6 field to a new value. */ 08854 #define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v)) 08855 /*@}*/ 08856 08857 /*! 08858 * @name Register AIPS_PACRL, field TP5[8] (RW) 08859 * 08860 * Determines whether the peripheral allows accesses from an untrusted master. 08861 * When this field is set and an access is attempted by an untrusted master, the 08862 * access terminates with an error response and no peripheral access initiates. 08863 * 08864 * Values: 08865 * - 0 - Accesses from an untrusted master are allowed. 08866 * - 1 - Accesses from an untrusted master are not allowed. 08867 */ 08868 /*@{*/ 08869 #define BP_AIPS_PACRL_TP5 (8U) /*!< Bit position for AIPS_PACRL_TP5. */ 08870 #define BM_AIPS_PACRL_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRL_TP5. */ 08871 #define BS_AIPS_PACRL_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP5. */ 08872 08873 /*! @brief Read current value of the AIPS_PACRL_TP5 field. */ 08874 #define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5)) 08875 08876 /*! @brief Format value for bitfield AIPS_PACRL_TP5. */ 08877 #define BF_AIPS_PACRL_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP5) & BM_AIPS_PACRL_TP5) 08878 08879 /*! @brief Set the TP5 field to a new value. */ 08880 #define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v)) 08881 /*@}*/ 08882 08883 /*! 08884 * @name Register AIPS_PACRL, field WP5[9] (RW) 08885 * 08886 * Determines whether the peripheral allows write accesses. When this field is 08887 * set and a write access is attempted, access terminates with an error response 08888 * and no peripheral access initiates. 08889 * 08890 * Values: 08891 * - 0 - This peripheral allows write accesses. 08892 * - 1 - This peripheral is write protected. 08893 */ 08894 /*@{*/ 08895 #define BP_AIPS_PACRL_WP5 (9U) /*!< Bit position for AIPS_PACRL_WP5. */ 08896 #define BM_AIPS_PACRL_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRL_WP5. */ 08897 #define BS_AIPS_PACRL_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP5. */ 08898 08899 /*! @brief Read current value of the AIPS_PACRL_WP5 field. */ 08900 #define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5)) 08901 08902 /*! @brief Format value for bitfield AIPS_PACRL_WP5. */ 08903 #define BF_AIPS_PACRL_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP5) & BM_AIPS_PACRL_WP5) 08904 08905 /*! @brief Set the WP5 field to a new value. */ 08906 #define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v)) 08907 /*@}*/ 08908 08909 /*! 08910 * @name Register AIPS_PACRL, field SP5[10] (RW) 08911 * 08912 * Determines whether the peripheral requires supervisor privilege level for 08913 * accesses. When this field is set, the master privilege level must indicate the 08914 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08915 * must be set. If not, access terminates with an error response and no peripheral 08916 * access initiates. 08917 * 08918 * Values: 08919 * - 0 - This peripheral does not require supervisor privilege level for 08920 * accesses. 08921 * - 1 - This peripheral requires supervisor privilege level for accesses. 08922 */ 08923 /*@{*/ 08924 #define BP_AIPS_PACRL_SP5 (10U) /*!< Bit position for AIPS_PACRL_SP5. */ 08925 #define BM_AIPS_PACRL_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRL_SP5. */ 08926 #define BS_AIPS_PACRL_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP5. */ 08927 08928 /*! @brief Read current value of the AIPS_PACRL_SP5 field. */ 08929 #define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5)) 08930 08931 /*! @brief Format value for bitfield AIPS_PACRL_SP5. */ 08932 #define BF_AIPS_PACRL_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP5) & BM_AIPS_PACRL_SP5) 08933 08934 /*! @brief Set the SP5 field to a new value. */ 08935 #define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v)) 08936 /*@}*/ 08937 08938 /*! 08939 * @name Register AIPS_PACRL, field TP4[12] (RW) 08940 * 08941 * Determines whether the peripheral allows accesses from an untrusted master. 08942 * When this bit is set and an access is attempted by an untrusted master, the 08943 * access terminates with an error response and no peripheral access initiates. 08944 * 08945 * Values: 08946 * - 0 - Accesses from an untrusted master are allowed. 08947 * - 1 - Accesses from an untrusted master are not allowed. 08948 */ 08949 /*@{*/ 08950 #define BP_AIPS_PACRL_TP4 (12U) /*!< Bit position for AIPS_PACRL_TP4. */ 08951 #define BM_AIPS_PACRL_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRL_TP4. */ 08952 #define BS_AIPS_PACRL_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP4. */ 08953 08954 /*! @brief Read current value of the AIPS_PACRL_TP4 field. */ 08955 #define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4)) 08956 08957 /*! @brief Format value for bitfield AIPS_PACRL_TP4. */ 08958 #define BF_AIPS_PACRL_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP4) & BM_AIPS_PACRL_TP4) 08959 08960 /*! @brief Set the TP4 field to a new value. */ 08961 #define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v)) 08962 /*@}*/ 08963 08964 /*! 08965 * @name Register AIPS_PACRL, field WP4[13] (RW) 08966 * 08967 * Determines whether the peripheral allows write accesses. When this field is 08968 * set and a write access is attempted, access terminates with an error response 08969 * and no peripheral access initiates. 08970 * 08971 * Values: 08972 * - 0 - This peripheral allows write accesses. 08973 * - 1 - This peripheral is write protected. 08974 */ 08975 /*@{*/ 08976 #define BP_AIPS_PACRL_WP4 (13U) /*!< Bit position for AIPS_PACRL_WP4. */ 08977 #define BM_AIPS_PACRL_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRL_WP4. */ 08978 #define BS_AIPS_PACRL_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP4. */ 08979 08980 /*! @brief Read current value of the AIPS_PACRL_WP4 field. */ 08981 #define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4)) 08982 08983 /*! @brief Format value for bitfield AIPS_PACRL_WP4. */ 08984 #define BF_AIPS_PACRL_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP4) & BM_AIPS_PACRL_WP4) 08985 08986 /*! @brief Set the WP4 field to a new value. */ 08987 #define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v)) 08988 /*@}*/ 08989 08990 /*! 08991 * @name Register AIPS_PACRL, field SP4[14] (RW) 08992 * 08993 * Determines whether the peripheral requires supervisor privilege level for 08994 * access. When this bit is set, the master privilege level must indicate the 08995 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 08996 * set. If not, access terminates with an error response and no peripheral access 08997 * initiates. 08998 * 08999 * Values: 09000 * - 0 - This peripheral does not require supervisor privilege level for 09001 * accesses. 09002 * - 1 - This peripheral requires supervisor privilege level for accesses. 09003 */ 09004 /*@{*/ 09005 #define BP_AIPS_PACRL_SP4 (14U) /*!< Bit position for AIPS_PACRL_SP4. */ 09006 #define BM_AIPS_PACRL_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRL_SP4. */ 09007 #define BS_AIPS_PACRL_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP4. */ 09008 09009 /*! @brief Read current value of the AIPS_PACRL_SP4 field. */ 09010 #define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4)) 09011 09012 /*! @brief Format value for bitfield AIPS_PACRL_SP4. */ 09013 #define BF_AIPS_PACRL_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP4) & BM_AIPS_PACRL_SP4) 09014 09015 /*! @brief Set the SP4 field to a new value. */ 09016 #define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v)) 09017 /*@}*/ 09018 09019 /*! 09020 * @name Register AIPS_PACRL, field TP3[16] (RW) 09021 * 09022 * Determines whether the peripheral allows accesses from an untrusted master. 09023 * When this field is set and an access is attempted by an untrusted master, the 09024 * access terminates with an error response and no peripheral access initiates. 09025 * 09026 * Values: 09027 * - 0 - Accesses from an untrusted master are allowed. 09028 * - 1 - Accesses from an untrusted master are not allowed. 09029 */ 09030 /*@{*/ 09031 #define BP_AIPS_PACRL_TP3 (16U) /*!< Bit position for AIPS_PACRL_TP3. */ 09032 #define BM_AIPS_PACRL_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRL_TP3. */ 09033 #define BS_AIPS_PACRL_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP3. */ 09034 09035 /*! @brief Read current value of the AIPS_PACRL_TP3 field. */ 09036 #define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3)) 09037 09038 /*! @brief Format value for bitfield AIPS_PACRL_TP3. */ 09039 #define BF_AIPS_PACRL_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP3) & BM_AIPS_PACRL_TP3) 09040 09041 /*! @brief Set the TP3 field to a new value. */ 09042 #define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v)) 09043 /*@}*/ 09044 09045 /*! 09046 * @name Register AIPS_PACRL, field WP3[17] (RW) 09047 * 09048 * Determines whether the peripheral allows write accesss. When this bit is set 09049 * and a write access is attempted, access terminates with an error response and 09050 * no peripheral access initiates. 09051 * 09052 * Values: 09053 * - 0 - This peripheral allows write accesses. 09054 * - 1 - This peripheral is write protected. 09055 */ 09056 /*@{*/ 09057 #define BP_AIPS_PACRL_WP3 (17U) /*!< Bit position for AIPS_PACRL_WP3. */ 09058 #define BM_AIPS_PACRL_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRL_WP3. */ 09059 #define BS_AIPS_PACRL_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP3. */ 09060 09061 /*! @brief Read current value of the AIPS_PACRL_WP3 field. */ 09062 #define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3)) 09063 09064 /*! @brief Format value for bitfield AIPS_PACRL_WP3. */ 09065 #define BF_AIPS_PACRL_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP3) & BM_AIPS_PACRL_WP3) 09066 09067 /*! @brief Set the WP3 field to a new value. */ 09068 #define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v)) 09069 /*@}*/ 09070 09071 /*! 09072 * @name Register AIPS_PACRL, field SP3[18] (RW) 09073 * 09074 * Determines whether the peripheral requires supervisor privilege level for 09075 * accesses. When this field is set, the master privilege level must indicate the 09076 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09077 * must be set. If not, access terminates with an error response and no peripheral 09078 * access initiates. 09079 * 09080 * Values: 09081 * - 0 - This peripheral does not require supervisor privilege level for 09082 * accesses. 09083 * - 1 - This peripheral requires supervisor privilege level for accesses. 09084 */ 09085 /*@{*/ 09086 #define BP_AIPS_PACRL_SP3 (18U) /*!< Bit position for AIPS_PACRL_SP3. */ 09087 #define BM_AIPS_PACRL_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRL_SP3. */ 09088 #define BS_AIPS_PACRL_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP3. */ 09089 09090 /*! @brief Read current value of the AIPS_PACRL_SP3 field. */ 09091 #define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3)) 09092 09093 /*! @brief Format value for bitfield AIPS_PACRL_SP3. */ 09094 #define BF_AIPS_PACRL_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP3) & BM_AIPS_PACRL_SP3) 09095 09096 /*! @brief Set the SP3 field to a new value. */ 09097 #define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v)) 09098 /*@}*/ 09099 09100 /*! 09101 * @name Register AIPS_PACRL, field TP2[20] (RW) 09102 * 09103 * Determines whether the peripheral allows accesses from an untrusted master. 09104 * When this bit is set and an access is attempted by an untrusted master, the 09105 * access terminates with an error response and no peripheral access initiates. 09106 * 09107 * Values: 09108 * - 0 - Accesses from an untrusted master are allowed. 09109 * - 1 - Accesses from an untrusted master are not allowed. 09110 */ 09111 /*@{*/ 09112 #define BP_AIPS_PACRL_TP2 (20U) /*!< Bit position for AIPS_PACRL_TP2. */ 09113 #define BM_AIPS_PACRL_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRL_TP2. */ 09114 #define BS_AIPS_PACRL_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP2. */ 09115 09116 /*! @brief Read current value of the AIPS_PACRL_TP2 field. */ 09117 #define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2)) 09118 09119 /*! @brief Format value for bitfield AIPS_PACRL_TP2. */ 09120 #define BF_AIPS_PACRL_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP2) & BM_AIPS_PACRL_TP2) 09121 09122 /*! @brief Set the TP2 field to a new value. */ 09123 #define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v)) 09124 /*@}*/ 09125 09126 /*! 09127 * @name Register AIPS_PACRL, field WP2[21] (RW) 09128 * 09129 * Determines whether the peripheral allows write accesses. When this field is 09130 * set and a write access is attempted, access terminates with an error response 09131 * and no peripheral access initiates. 09132 * 09133 * Values: 09134 * - 0 - This peripheral allows write accesses. 09135 * - 1 - This peripheral is write protected. 09136 */ 09137 /*@{*/ 09138 #define BP_AIPS_PACRL_WP2 (21U) /*!< Bit position for AIPS_PACRL_WP2. */ 09139 #define BM_AIPS_PACRL_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRL_WP2. */ 09140 #define BS_AIPS_PACRL_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP2. */ 09141 09142 /*! @brief Read current value of the AIPS_PACRL_WP2 field. */ 09143 #define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2)) 09144 09145 /*! @brief Format value for bitfield AIPS_PACRL_WP2. */ 09146 #define BF_AIPS_PACRL_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP2) & BM_AIPS_PACRL_WP2) 09147 09148 /*! @brief Set the WP2 field to a new value. */ 09149 #define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v)) 09150 /*@}*/ 09151 09152 /*! 09153 * @name Register AIPS_PACRL, field SP2[22] (RW) 09154 * 09155 * Determines whether the peripheral requires supervisor privilege level for 09156 * access. When this bit is set, the master privilege level must indicate the 09157 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09158 * set. If not, access terminates with an error response and no peripheral access 09159 * initiates. 09160 * 09161 * Values: 09162 * - 0 - This peripheral does not require supervisor privilege level for 09163 * accesses. 09164 * - 1 - This peripheral requires supervisor privilege level for accesses. 09165 */ 09166 /*@{*/ 09167 #define BP_AIPS_PACRL_SP2 (22U) /*!< Bit position for AIPS_PACRL_SP2. */ 09168 #define BM_AIPS_PACRL_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRL_SP2. */ 09169 #define BS_AIPS_PACRL_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP2. */ 09170 09171 /*! @brief Read current value of the AIPS_PACRL_SP2 field. */ 09172 #define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2)) 09173 09174 /*! @brief Format value for bitfield AIPS_PACRL_SP2. */ 09175 #define BF_AIPS_PACRL_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP2) & BM_AIPS_PACRL_SP2) 09176 09177 /*! @brief Set the SP2 field to a new value. */ 09178 #define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v)) 09179 /*@}*/ 09180 09181 /*! 09182 * @name Register AIPS_PACRL, field TP1[24] (RW) 09183 * 09184 * Determines whether the peripheral allows accesses from an untrusted master. 09185 * When this field is set and an access is attempted by an untrusted master, the 09186 * access terminates with an error response and no peripheral access initiates. 09187 * 09188 * Values: 09189 * - 0 - Accesses from an untrusted master are allowed. 09190 * - 1 - Accesses from an untrusted master are not allowed. 09191 */ 09192 /*@{*/ 09193 #define BP_AIPS_PACRL_TP1 (24U) /*!< Bit position for AIPS_PACRL_TP1. */ 09194 #define BM_AIPS_PACRL_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRL_TP1. */ 09195 #define BS_AIPS_PACRL_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP1. */ 09196 09197 /*! @brief Read current value of the AIPS_PACRL_TP1 field. */ 09198 #define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1)) 09199 09200 /*! @brief Format value for bitfield AIPS_PACRL_TP1. */ 09201 #define BF_AIPS_PACRL_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP1) & BM_AIPS_PACRL_TP1) 09202 09203 /*! @brief Set the TP1 field to a new value. */ 09204 #define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v)) 09205 /*@}*/ 09206 09207 /*! 09208 * @name Register AIPS_PACRL, field WP1[25] (RW) 09209 * 09210 * Determines whether the peripheral allows write accesses. When this field is 09211 * set and a write access is attempted, access terminates with an error response 09212 * and no peripheral access initiates. 09213 * 09214 * Values: 09215 * - 0 - This peripheral allows write accesses. 09216 * - 1 - This peripheral is write protected. 09217 */ 09218 /*@{*/ 09219 #define BP_AIPS_PACRL_WP1 (25U) /*!< Bit position for AIPS_PACRL_WP1. */ 09220 #define BM_AIPS_PACRL_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRL_WP1. */ 09221 #define BS_AIPS_PACRL_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP1. */ 09222 09223 /*! @brief Read current value of the AIPS_PACRL_WP1 field. */ 09224 #define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1)) 09225 09226 /*! @brief Format value for bitfield AIPS_PACRL_WP1. */ 09227 #define BF_AIPS_PACRL_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP1) & BM_AIPS_PACRL_WP1) 09228 09229 /*! @brief Set the WP1 field to a new value. */ 09230 #define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v)) 09231 /*@}*/ 09232 09233 /*! 09234 * @name Register AIPS_PACRL, field SP1[26] (RW) 09235 * 09236 * Determines whether the peripheral requires supervisor privilege level for 09237 * access. When this field is set, the master privilege level must indicate the 09238 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 09239 * be set. If not, access terminates with an error response and no peripheral 09240 * access initiates. 09241 * 09242 * Values: 09243 * - 0 - This peripheral does not require supervisor privilege level for 09244 * accesses. 09245 * - 1 - This peripheral requires supervisor privilege level for accesses. 09246 */ 09247 /*@{*/ 09248 #define BP_AIPS_PACRL_SP1 (26U) /*!< Bit position for AIPS_PACRL_SP1. */ 09249 #define BM_AIPS_PACRL_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRL_SP1. */ 09250 #define BS_AIPS_PACRL_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP1. */ 09251 09252 /*! @brief Read current value of the AIPS_PACRL_SP1 field. */ 09253 #define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1)) 09254 09255 /*! @brief Format value for bitfield AIPS_PACRL_SP1. */ 09256 #define BF_AIPS_PACRL_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP1) & BM_AIPS_PACRL_SP1) 09257 09258 /*! @brief Set the SP1 field to a new value. */ 09259 #define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v)) 09260 /*@}*/ 09261 09262 /*! 09263 * @name Register AIPS_PACRL, field TP0[28] (RW) 09264 * 09265 * Determines whether the peripheral allows accesses from an untrusted master. 09266 * When this bit is set and an access is attempted by an untrusted master, the 09267 * access terminates with an error response and no peripheral access initiates. 09268 * 09269 * Values: 09270 * - 0 - Accesses from an untrusted master are allowed. 09271 * - 1 - Accesses from an untrusted master are not allowed. 09272 */ 09273 /*@{*/ 09274 #define BP_AIPS_PACRL_TP0 (28U) /*!< Bit position for AIPS_PACRL_TP0. */ 09275 #define BM_AIPS_PACRL_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRL_TP0. */ 09276 #define BS_AIPS_PACRL_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP0. */ 09277 09278 /*! @brief Read current value of the AIPS_PACRL_TP0 field. */ 09279 #define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0)) 09280 09281 /*! @brief Format value for bitfield AIPS_PACRL_TP0. */ 09282 #define BF_AIPS_PACRL_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP0) & BM_AIPS_PACRL_TP0) 09283 09284 /*! @brief Set the TP0 field to a new value. */ 09285 #define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v)) 09286 /*@}*/ 09287 09288 /*! 09289 * @name Register AIPS_PACRL, field WP0[29] (RW) 09290 * 09291 * Determines whether the peripheral allows write accesses. When this field is 09292 * set and a write access is attempted, access terminates with an error response 09293 * and no peripheral access initiates. 09294 * 09295 * Values: 09296 * - 0 - This peripheral allows write accesses. 09297 * - 1 - This peripheral is write protected. 09298 */ 09299 /*@{*/ 09300 #define BP_AIPS_PACRL_WP0 (29U) /*!< Bit position for AIPS_PACRL_WP0. */ 09301 #define BM_AIPS_PACRL_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRL_WP0. */ 09302 #define BS_AIPS_PACRL_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP0. */ 09303 09304 /*! @brief Read current value of the AIPS_PACRL_WP0 field. */ 09305 #define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0)) 09306 09307 /*! @brief Format value for bitfield AIPS_PACRL_WP0. */ 09308 #define BF_AIPS_PACRL_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP0) & BM_AIPS_PACRL_WP0) 09309 09310 /*! @brief Set the WP0 field to a new value. */ 09311 #define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v)) 09312 /*@}*/ 09313 09314 /*! 09315 * @name Register AIPS_PACRL, field SP0[30] (RW) 09316 * 09317 * Determines whether the peripheral requires supervisor privilege level for 09318 * accesses. When this field is set, the master privilege level must indicate the 09319 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09320 * must be set. If not, access terminates with an error response and no peripheral 09321 * access initiates. 09322 * 09323 * Values: 09324 * - 0 - This peripheral does not require supervisor privilege level for 09325 * accesses. 09326 * - 1 - This peripheral requires supervisor privilege level for accesses. 09327 */ 09328 /*@{*/ 09329 #define BP_AIPS_PACRL_SP0 (30U) /*!< Bit position for AIPS_PACRL_SP0. */ 09330 #define BM_AIPS_PACRL_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRL_SP0. */ 09331 #define BS_AIPS_PACRL_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP0. */ 09332 09333 /*! @brief Read current value of the AIPS_PACRL_SP0 field. */ 09334 #define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0)) 09335 09336 /*! @brief Format value for bitfield AIPS_PACRL_SP0. */ 09337 #define BF_AIPS_PACRL_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP0) & BM_AIPS_PACRL_SP0) 09338 09339 /*! @brief Set the SP0 field to a new value. */ 09340 #define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v)) 09341 /*@}*/ 09342 09343 /******************************************************************************* 09344 * HW_AIPS_PACRM - Peripheral Access Control Register 09345 ******************************************************************************/ 09346 09347 /*! 09348 * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) 09349 * 09350 * Reset value: 0x44444444U 09351 * 09352 * This section describes PACR registers E-P, which control peripheral slots 09353 * 32-127. See PACRPeripheral Access Control Register for the description of these 09354 * registers. 09355 */ 09356 typedef union _hw_aips_pacrm 09357 { 09358 uint32_t U; 09359 struct _hw_aips_pacrm_bitfields 09360 { 09361 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 09362 uint32_t WP7 : 1; /*!< [1] Write Protect */ 09363 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 09364 uint32_t RESERVED0 : 1; /*!< [3] */ 09365 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 09366 uint32_t WP6 : 1; /*!< [5] Write Protect */ 09367 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 09368 uint32_t RESERVED1 : 1; /*!< [7] */ 09369 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 09370 uint32_t WP5 : 1; /*!< [9] Write Protect */ 09371 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 09372 uint32_t RESERVED2 : 1; /*!< [11] */ 09373 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 09374 uint32_t WP4 : 1; /*!< [13] Write Protect */ 09375 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 09376 uint32_t RESERVED3 : 1; /*!< [15] */ 09377 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 09378 uint32_t WP3 : 1; /*!< [17] Write Protect */ 09379 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 09380 uint32_t RESERVED4 : 1; /*!< [19] */ 09381 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 09382 uint32_t WP2 : 1; /*!< [21] Write Protect */ 09383 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 09384 uint32_t RESERVED5 : 1; /*!< [23] */ 09385 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 09386 uint32_t WP1 : 1; /*!< [25] Write Protect */ 09387 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 09388 uint32_t RESERVED6 : 1; /*!< [27] */ 09389 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 09390 uint32_t WP0 : 1; /*!< [29] Write Protect */ 09391 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 09392 uint32_t RESERVED7 : 1; /*!< [31] */ 09393 } B; 09394 } hw_aips_pacrm_t; 09395 09396 /*! 09397 * @name Constants and macros for entire AIPS_PACRM register 09398 */ 09399 /*@{*/ 09400 #define HW_AIPS_PACRM_ADDR(x) ((x) + 0x60U) 09401 09402 #define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) 09403 #define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U) 09404 #define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v)) 09405 #define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) 09406 #define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) 09407 #define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) 09408 /*@}*/ 09409 09410 /* 09411 * Constants & macros for individual AIPS_PACRM bitfields 09412 */ 09413 09414 /*! 09415 * @name Register AIPS_PACRM, field TP7[0] (RW) 09416 * 09417 * Determines whether the peripheral allows accesses from an untrusted master. 09418 * When this field is set and an access is attempted by an untrusted master, the 09419 * access terminates with an error response and no peripheral access initiates. 09420 * 09421 * Values: 09422 * - 0 - Accesses from an untrusted master are allowed. 09423 * - 1 - Accesses from an untrusted master are not allowed. 09424 */ 09425 /*@{*/ 09426 #define BP_AIPS_PACRM_TP7 (0U) /*!< Bit position for AIPS_PACRM_TP7. */ 09427 #define BM_AIPS_PACRM_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRM_TP7. */ 09428 #define BS_AIPS_PACRM_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP7. */ 09429 09430 /*! @brief Read current value of the AIPS_PACRM_TP7 field. */ 09431 #define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7)) 09432 09433 /*! @brief Format value for bitfield AIPS_PACRM_TP7. */ 09434 #define BF_AIPS_PACRM_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP7) & BM_AIPS_PACRM_TP7) 09435 09436 /*! @brief Set the TP7 field to a new value. */ 09437 #define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v)) 09438 /*@}*/ 09439 09440 /*! 09441 * @name Register AIPS_PACRM, field WP7[1] (RW) 09442 * 09443 * Determines whether the peripheral allows write accesses. When this field is 09444 * set and a write access is attempted, access terminates with an error response 09445 * and no peripheral access initiates. 09446 * 09447 * Values: 09448 * - 0 - This peripheral allows write accesses. 09449 * - 1 - This peripheral is write protected. 09450 */ 09451 /*@{*/ 09452 #define BP_AIPS_PACRM_WP7 (1U) /*!< Bit position for AIPS_PACRM_WP7. */ 09453 #define BM_AIPS_PACRM_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRM_WP7. */ 09454 #define BS_AIPS_PACRM_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP7. */ 09455 09456 /*! @brief Read current value of the AIPS_PACRM_WP7 field. */ 09457 #define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7)) 09458 09459 /*! @brief Format value for bitfield AIPS_PACRM_WP7. */ 09460 #define BF_AIPS_PACRM_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP7) & BM_AIPS_PACRM_WP7) 09461 09462 /*! @brief Set the WP7 field to a new value. */ 09463 #define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v)) 09464 /*@}*/ 09465 09466 /*! 09467 * @name Register AIPS_PACRM, field SP7[2] (RW) 09468 * 09469 * Determines whether the peripheral requires supervisor privilege level for 09470 * accesses. When this field is set, the master privilege level must indicate the 09471 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09472 * must be set. If not, access terminates with an error response and no peripheral 09473 * access initiates. 09474 * 09475 * Values: 09476 * - 0 - This peripheral does not require supervisor privilege level for 09477 * accesses. 09478 * - 1 - This peripheral requires supervisor privilege level for accesses. 09479 */ 09480 /*@{*/ 09481 #define BP_AIPS_PACRM_SP7 (2U) /*!< Bit position for AIPS_PACRM_SP7. */ 09482 #define BM_AIPS_PACRM_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRM_SP7. */ 09483 #define BS_AIPS_PACRM_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP7. */ 09484 09485 /*! @brief Read current value of the AIPS_PACRM_SP7 field. */ 09486 #define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7)) 09487 09488 /*! @brief Format value for bitfield AIPS_PACRM_SP7. */ 09489 #define BF_AIPS_PACRM_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP7) & BM_AIPS_PACRM_SP7) 09490 09491 /*! @brief Set the SP7 field to a new value. */ 09492 #define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v)) 09493 /*@}*/ 09494 09495 /*! 09496 * @name Register AIPS_PACRM, field TP6[4] (RW) 09497 * 09498 * Determines whether the peripheral allows accesses from an untrusted master. 09499 * When this field is set and an access is attempted by an untrusted master, the 09500 * access terminates with an error response and no peripheral access initiates. 09501 * 09502 * Values: 09503 * - 0 - Accesses from an untrusted master are allowed. 09504 * - 1 - Accesses from an untrusted master are not allowed. 09505 */ 09506 /*@{*/ 09507 #define BP_AIPS_PACRM_TP6 (4U) /*!< Bit position for AIPS_PACRM_TP6. */ 09508 #define BM_AIPS_PACRM_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRM_TP6. */ 09509 #define BS_AIPS_PACRM_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP6. */ 09510 09511 /*! @brief Read current value of the AIPS_PACRM_TP6 field. */ 09512 #define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6)) 09513 09514 /*! @brief Format value for bitfield AIPS_PACRM_TP6. */ 09515 #define BF_AIPS_PACRM_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP6) & BM_AIPS_PACRM_TP6) 09516 09517 /*! @brief Set the TP6 field to a new value. */ 09518 #define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v)) 09519 /*@}*/ 09520 09521 /*! 09522 * @name Register AIPS_PACRM, field WP6[5] (RW) 09523 * 09524 * Determines whether the peripheral allows write accesses. When this field is 09525 * set and a write access is attempted, access terminates with an error response 09526 * and no peripheral access initiates. 09527 * 09528 * Values: 09529 * - 0 - This peripheral allows write accesses. 09530 * - 1 - This peripheral is write protected. 09531 */ 09532 /*@{*/ 09533 #define BP_AIPS_PACRM_WP6 (5U) /*!< Bit position for AIPS_PACRM_WP6. */ 09534 #define BM_AIPS_PACRM_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRM_WP6. */ 09535 #define BS_AIPS_PACRM_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP6. */ 09536 09537 /*! @brief Read current value of the AIPS_PACRM_WP6 field. */ 09538 #define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6)) 09539 09540 /*! @brief Format value for bitfield AIPS_PACRM_WP6. */ 09541 #define BF_AIPS_PACRM_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP6) & BM_AIPS_PACRM_WP6) 09542 09543 /*! @brief Set the WP6 field to a new value. */ 09544 #define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v)) 09545 /*@}*/ 09546 09547 /*! 09548 * @name Register AIPS_PACRM, field SP6[6] (RW) 09549 * 09550 * Determines whether the peripheral requires supervisor privilege level for 09551 * accesses. When this field is set, the master privilege level must indicate the 09552 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09553 * must be set. If not, access terminates with an error response and no peripheral 09554 * access initiates. 09555 * 09556 * Values: 09557 * - 0 - This peripheral does not require supervisor privilege level for 09558 * accesses. 09559 * - 1 - This peripheral requires supervisor privilege level for accesses. 09560 */ 09561 /*@{*/ 09562 #define BP_AIPS_PACRM_SP6 (6U) /*!< Bit position for AIPS_PACRM_SP6. */ 09563 #define BM_AIPS_PACRM_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRM_SP6. */ 09564 #define BS_AIPS_PACRM_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP6. */ 09565 09566 /*! @brief Read current value of the AIPS_PACRM_SP6 field. */ 09567 #define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6)) 09568 09569 /*! @brief Format value for bitfield AIPS_PACRM_SP6. */ 09570 #define BF_AIPS_PACRM_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP6) & BM_AIPS_PACRM_SP6) 09571 09572 /*! @brief Set the SP6 field to a new value. */ 09573 #define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v)) 09574 /*@}*/ 09575 09576 /*! 09577 * @name Register AIPS_PACRM, field TP5[8] (RW) 09578 * 09579 * Determines whether the peripheral allows accesses from an untrusted master. 09580 * When this field is set and an access is attempted by an untrusted master, the 09581 * access terminates with an error response and no peripheral access initiates. 09582 * 09583 * Values: 09584 * - 0 - Accesses from an untrusted master are allowed. 09585 * - 1 - Accesses from an untrusted master are not allowed. 09586 */ 09587 /*@{*/ 09588 #define BP_AIPS_PACRM_TP5 (8U) /*!< Bit position for AIPS_PACRM_TP5. */ 09589 #define BM_AIPS_PACRM_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRM_TP5. */ 09590 #define BS_AIPS_PACRM_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP5. */ 09591 09592 /*! @brief Read current value of the AIPS_PACRM_TP5 field. */ 09593 #define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5)) 09594 09595 /*! @brief Format value for bitfield AIPS_PACRM_TP5. */ 09596 #define BF_AIPS_PACRM_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP5) & BM_AIPS_PACRM_TP5) 09597 09598 /*! @brief Set the TP5 field to a new value. */ 09599 #define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v)) 09600 /*@}*/ 09601 09602 /*! 09603 * @name Register AIPS_PACRM, field WP5[9] (RW) 09604 * 09605 * Determines whether the peripheral allows write accesses. When this field is 09606 * set and a write access is attempted, access terminates with an error response 09607 * and no peripheral access initiates. 09608 * 09609 * Values: 09610 * - 0 - This peripheral allows write accesses. 09611 * - 1 - This peripheral is write protected. 09612 */ 09613 /*@{*/ 09614 #define BP_AIPS_PACRM_WP5 (9U) /*!< Bit position for AIPS_PACRM_WP5. */ 09615 #define BM_AIPS_PACRM_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRM_WP5. */ 09616 #define BS_AIPS_PACRM_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP5. */ 09617 09618 /*! @brief Read current value of the AIPS_PACRM_WP5 field. */ 09619 #define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5)) 09620 09621 /*! @brief Format value for bitfield AIPS_PACRM_WP5. */ 09622 #define BF_AIPS_PACRM_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP5) & BM_AIPS_PACRM_WP5) 09623 09624 /*! @brief Set the WP5 field to a new value. */ 09625 #define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v)) 09626 /*@}*/ 09627 09628 /*! 09629 * @name Register AIPS_PACRM, field SP5[10] (RW) 09630 * 09631 * Determines whether the peripheral requires supervisor privilege level for 09632 * accesses. When this field is set, the master privilege level must indicate the 09633 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09634 * must be set. If not, access terminates with an error response and no peripheral 09635 * access initiates. 09636 * 09637 * Values: 09638 * - 0 - This peripheral does not require supervisor privilege level for 09639 * accesses. 09640 * - 1 - This peripheral requires supervisor privilege level for accesses. 09641 */ 09642 /*@{*/ 09643 #define BP_AIPS_PACRM_SP5 (10U) /*!< Bit position for AIPS_PACRM_SP5. */ 09644 #define BM_AIPS_PACRM_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRM_SP5. */ 09645 #define BS_AIPS_PACRM_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP5. */ 09646 09647 /*! @brief Read current value of the AIPS_PACRM_SP5 field. */ 09648 #define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5)) 09649 09650 /*! @brief Format value for bitfield AIPS_PACRM_SP5. */ 09651 #define BF_AIPS_PACRM_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP5) & BM_AIPS_PACRM_SP5) 09652 09653 /*! @brief Set the SP5 field to a new value. */ 09654 #define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v)) 09655 /*@}*/ 09656 09657 /*! 09658 * @name Register AIPS_PACRM, field TP4[12] (RW) 09659 * 09660 * Determines whether the peripheral allows accesses from an untrusted master. 09661 * When this bit is set and an access is attempted by an untrusted master, the 09662 * access terminates with an error response and no peripheral access initiates. 09663 * 09664 * Values: 09665 * - 0 - Accesses from an untrusted master are allowed. 09666 * - 1 - Accesses from an untrusted master are not allowed. 09667 */ 09668 /*@{*/ 09669 #define BP_AIPS_PACRM_TP4 (12U) /*!< Bit position for AIPS_PACRM_TP4. */ 09670 #define BM_AIPS_PACRM_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRM_TP4. */ 09671 #define BS_AIPS_PACRM_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP4. */ 09672 09673 /*! @brief Read current value of the AIPS_PACRM_TP4 field. */ 09674 #define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4)) 09675 09676 /*! @brief Format value for bitfield AIPS_PACRM_TP4. */ 09677 #define BF_AIPS_PACRM_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP4) & BM_AIPS_PACRM_TP4) 09678 09679 /*! @brief Set the TP4 field to a new value. */ 09680 #define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v)) 09681 /*@}*/ 09682 09683 /*! 09684 * @name Register AIPS_PACRM, field WP4[13] (RW) 09685 * 09686 * Determines whether the peripheral allows write accesses. When this field is 09687 * set and a write access is attempted, access terminates with an error response 09688 * and no peripheral access initiates. 09689 * 09690 * Values: 09691 * - 0 - This peripheral allows write accesses. 09692 * - 1 - This peripheral is write protected. 09693 */ 09694 /*@{*/ 09695 #define BP_AIPS_PACRM_WP4 (13U) /*!< Bit position for AIPS_PACRM_WP4. */ 09696 #define BM_AIPS_PACRM_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRM_WP4. */ 09697 #define BS_AIPS_PACRM_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP4. */ 09698 09699 /*! @brief Read current value of the AIPS_PACRM_WP4 field. */ 09700 #define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4)) 09701 09702 /*! @brief Format value for bitfield AIPS_PACRM_WP4. */ 09703 #define BF_AIPS_PACRM_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP4) & BM_AIPS_PACRM_WP4) 09704 09705 /*! @brief Set the WP4 field to a new value. */ 09706 #define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v)) 09707 /*@}*/ 09708 09709 /*! 09710 * @name Register AIPS_PACRM, field SP4[14] (RW) 09711 * 09712 * Determines whether the peripheral requires supervisor privilege level for 09713 * access. When this bit is set, the master privilege level must indicate the 09714 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09715 * set. If not, access terminates with an error response and no peripheral access 09716 * initiates. 09717 * 09718 * Values: 09719 * - 0 - This peripheral does not require supervisor privilege level for 09720 * accesses. 09721 * - 1 - This peripheral requires supervisor privilege level for accesses. 09722 */ 09723 /*@{*/ 09724 #define BP_AIPS_PACRM_SP4 (14U) /*!< Bit position for AIPS_PACRM_SP4. */ 09725 #define BM_AIPS_PACRM_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRM_SP4. */ 09726 #define BS_AIPS_PACRM_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP4. */ 09727 09728 /*! @brief Read current value of the AIPS_PACRM_SP4 field. */ 09729 #define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4)) 09730 09731 /*! @brief Format value for bitfield AIPS_PACRM_SP4. */ 09732 #define BF_AIPS_PACRM_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP4) & BM_AIPS_PACRM_SP4) 09733 09734 /*! @brief Set the SP4 field to a new value. */ 09735 #define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v)) 09736 /*@}*/ 09737 09738 /*! 09739 * @name Register AIPS_PACRM, field TP3[16] (RW) 09740 * 09741 * Determines whether the peripheral allows accesses from an untrusted master. 09742 * When this field is set and an access is attempted by an untrusted master, the 09743 * access terminates with an error response and no peripheral access initiates. 09744 * 09745 * Values: 09746 * - 0 - Accesses from an untrusted master are allowed. 09747 * - 1 - Accesses from an untrusted master are not allowed. 09748 */ 09749 /*@{*/ 09750 #define BP_AIPS_PACRM_TP3 (16U) /*!< Bit position for AIPS_PACRM_TP3. */ 09751 #define BM_AIPS_PACRM_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRM_TP3. */ 09752 #define BS_AIPS_PACRM_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP3. */ 09753 09754 /*! @brief Read current value of the AIPS_PACRM_TP3 field. */ 09755 #define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3)) 09756 09757 /*! @brief Format value for bitfield AIPS_PACRM_TP3. */ 09758 #define BF_AIPS_PACRM_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP3) & BM_AIPS_PACRM_TP3) 09759 09760 /*! @brief Set the TP3 field to a new value. */ 09761 #define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v)) 09762 /*@}*/ 09763 09764 /*! 09765 * @name Register AIPS_PACRM, field WP3[17] (RW) 09766 * 09767 * Determines whether the peripheral allows write accesss. When this bit is set 09768 * and a write access is attempted, access terminates with an error response and 09769 * no peripheral access initiates. 09770 * 09771 * Values: 09772 * - 0 - This peripheral allows write accesses. 09773 * - 1 - This peripheral is write protected. 09774 */ 09775 /*@{*/ 09776 #define BP_AIPS_PACRM_WP3 (17U) /*!< Bit position for AIPS_PACRM_WP3. */ 09777 #define BM_AIPS_PACRM_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRM_WP3. */ 09778 #define BS_AIPS_PACRM_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP3. */ 09779 09780 /*! @brief Read current value of the AIPS_PACRM_WP3 field. */ 09781 #define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3)) 09782 09783 /*! @brief Format value for bitfield AIPS_PACRM_WP3. */ 09784 #define BF_AIPS_PACRM_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP3) & BM_AIPS_PACRM_WP3) 09785 09786 /*! @brief Set the WP3 field to a new value. */ 09787 #define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v)) 09788 /*@}*/ 09789 09790 /*! 09791 * @name Register AIPS_PACRM, field SP3[18] (RW) 09792 * 09793 * Determines whether the peripheral requires supervisor privilege level for 09794 * accesses. When this field is set, the master privilege level must indicate the 09795 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09796 * must be set. If not, access terminates with an error response and no peripheral 09797 * access initiates. 09798 * 09799 * Values: 09800 * - 0 - This peripheral does not require supervisor privilege level for 09801 * accesses. 09802 * - 1 - This peripheral requires supervisor privilege level for accesses. 09803 */ 09804 /*@{*/ 09805 #define BP_AIPS_PACRM_SP3 (18U) /*!< Bit position for AIPS_PACRM_SP3. */ 09806 #define BM_AIPS_PACRM_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRM_SP3. */ 09807 #define BS_AIPS_PACRM_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP3. */ 09808 09809 /*! @brief Read current value of the AIPS_PACRM_SP3 field. */ 09810 #define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3)) 09811 09812 /*! @brief Format value for bitfield AIPS_PACRM_SP3. */ 09813 #define BF_AIPS_PACRM_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP3) & BM_AIPS_PACRM_SP3) 09814 09815 /*! @brief Set the SP3 field to a new value. */ 09816 #define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v)) 09817 /*@}*/ 09818 09819 /*! 09820 * @name Register AIPS_PACRM, field TP2[20] (RW) 09821 * 09822 * Determines whether the peripheral allows accesses from an untrusted master. 09823 * When this bit is set and an access is attempted by an untrusted master, the 09824 * access terminates with an error response and no peripheral access initiates. 09825 * 09826 * Values: 09827 * - 0 - Accesses from an untrusted master are allowed. 09828 * - 1 - Accesses from an untrusted master are not allowed. 09829 */ 09830 /*@{*/ 09831 #define BP_AIPS_PACRM_TP2 (20U) /*!< Bit position for AIPS_PACRM_TP2. */ 09832 #define BM_AIPS_PACRM_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRM_TP2. */ 09833 #define BS_AIPS_PACRM_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP2. */ 09834 09835 /*! @brief Read current value of the AIPS_PACRM_TP2 field. */ 09836 #define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2)) 09837 09838 /*! @brief Format value for bitfield AIPS_PACRM_TP2. */ 09839 #define BF_AIPS_PACRM_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP2) & BM_AIPS_PACRM_TP2) 09840 09841 /*! @brief Set the TP2 field to a new value. */ 09842 #define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v)) 09843 /*@}*/ 09844 09845 /*! 09846 * @name Register AIPS_PACRM, field WP2[21] (RW) 09847 * 09848 * Determines whether the peripheral allows write accesses. When this field is 09849 * set and a write access is attempted, access terminates with an error response 09850 * and no peripheral access initiates. 09851 * 09852 * Values: 09853 * - 0 - This peripheral allows write accesses. 09854 * - 1 - This peripheral is write protected. 09855 */ 09856 /*@{*/ 09857 #define BP_AIPS_PACRM_WP2 (21U) /*!< Bit position for AIPS_PACRM_WP2. */ 09858 #define BM_AIPS_PACRM_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRM_WP2. */ 09859 #define BS_AIPS_PACRM_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP2. */ 09860 09861 /*! @brief Read current value of the AIPS_PACRM_WP2 field. */ 09862 #define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2)) 09863 09864 /*! @brief Format value for bitfield AIPS_PACRM_WP2. */ 09865 #define BF_AIPS_PACRM_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP2) & BM_AIPS_PACRM_WP2) 09866 09867 /*! @brief Set the WP2 field to a new value. */ 09868 #define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v)) 09869 /*@}*/ 09870 09871 /*! 09872 * @name Register AIPS_PACRM, field SP2[22] (RW) 09873 * 09874 * Determines whether the peripheral requires supervisor privilege level for 09875 * access. When this bit is set, the master privilege level must indicate the 09876 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09877 * set. If not, access terminates with an error response and no peripheral access 09878 * initiates. 09879 * 09880 * Values: 09881 * - 0 - This peripheral does not require supervisor privilege level for 09882 * accesses. 09883 * - 1 - This peripheral requires supervisor privilege level for accesses. 09884 */ 09885 /*@{*/ 09886 #define BP_AIPS_PACRM_SP2 (22U) /*!< Bit position for AIPS_PACRM_SP2. */ 09887 #define BM_AIPS_PACRM_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRM_SP2. */ 09888 #define BS_AIPS_PACRM_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP2. */ 09889 09890 /*! @brief Read current value of the AIPS_PACRM_SP2 field. */ 09891 #define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2)) 09892 09893 /*! @brief Format value for bitfield AIPS_PACRM_SP2. */ 09894 #define BF_AIPS_PACRM_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP2) & BM_AIPS_PACRM_SP2) 09895 09896 /*! @brief Set the SP2 field to a new value. */ 09897 #define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v)) 09898 /*@}*/ 09899 09900 /*! 09901 * @name Register AIPS_PACRM, field TP1[24] (RW) 09902 * 09903 * Determines whether the peripheral allows accesses from an untrusted master. 09904 * When this field is set and an access is attempted by an untrusted master, the 09905 * access terminates with an error response and no peripheral access initiates. 09906 * 09907 * Values: 09908 * - 0 - Accesses from an untrusted master are allowed. 09909 * - 1 - Accesses from an untrusted master are not allowed. 09910 */ 09911 /*@{*/ 09912 #define BP_AIPS_PACRM_TP1 (24U) /*!< Bit position for AIPS_PACRM_TP1. */ 09913 #define BM_AIPS_PACRM_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRM_TP1. */ 09914 #define BS_AIPS_PACRM_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP1. */ 09915 09916 /*! @brief Read current value of the AIPS_PACRM_TP1 field. */ 09917 #define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1)) 09918 09919 /*! @brief Format value for bitfield AIPS_PACRM_TP1. */ 09920 #define BF_AIPS_PACRM_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP1) & BM_AIPS_PACRM_TP1) 09921 09922 /*! @brief Set the TP1 field to a new value. */ 09923 #define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v)) 09924 /*@}*/ 09925 09926 /*! 09927 * @name Register AIPS_PACRM, field WP1[25] (RW) 09928 * 09929 * Determines whether the peripheral allows write accesses. When this field is 09930 * set and a write access is attempted, access terminates with an error response 09931 * and no peripheral access initiates. 09932 * 09933 * Values: 09934 * - 0 - This peripheral allows write accesses. 09935 * - 1 - This peripheral is write protected. 09936 */ 09937 /*@{*/ 09938 #define BP_AIPS_PACRM_WP1 (25U) /*!< Bit position for AIPS_PACRM_WP1. */ 09939 #define BM_AIPS_PACRM_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRM_WP1. */ 09940 #define BS_AIPS_PACRM_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP1. */ 09941 09942 /*! @brief Read current value of the AIPS_PACRM_WP1 field. */ 09943 #define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1)) 09944 09945 /*! @brief Format value for bitfield AIPS_PACRM_WP1. */ 09946 #define BF_AIPS_PACRM_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP1) & BM_AIPS_PACRM_WP1) 09947 09948 /*! @brief Set the WP1 field to a new value. */ 09949 #define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v)) 09950 /*@}*/ 09951 09952 /*! 09953 * @name Register AIPS_PACRM, field SP1[26] (RW) 09954 * 09955 * Determines whether the peripheral requires supervisor privilege level for 09956 * access. When this field is set, the master privilege level must indicate the 09957 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 09958 * be set. If not, access terminates with an error response and no peripheral 09959 * access initiates. 09960 * 09961 * Values: 09962 * - 0 - This peripheral does not require supervisor privilege level for 09963 * accesses. 09964 * - 1 - This peripheral requires supervisor privilege level for accesses. 09965 */ 09966 /*@{*/ 09967 #define BP_AIPS_PACRM_SP1 (26U) /*!< Bit position for AIPS_PACRM_SP1. */ 09968 #define BM_AIPS_PACRM_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRM_SP1. */ 09969 #define BS_AIPS_PACRM_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP1. */ 09970 09971 /*! @brief Read current value of the AIPS_PACRM_SP1 field. */ 09972 #define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1)) 09973 09974 /*! @brief Format value for bitfield AIPS_PACRM_SP1. */ 09975 #define BF_AIPS_PACRM_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP1) & BM_AIPS_PACRM_SP1) 09976 09977 /*! @brief Set the SP1 field to a new value. */ 09978 #define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v)) 09979 /*@}*/ 09980 09981 /*! 09982 * @name Register AIPS_PACRM, field TP0[28] (RW) 09983 * 09984 * Determines whether the peripheral allows accesses from an untrusted master. 09985 * When this bit is set and an access is attempted by an untrusted master, the 09986 * access terminates with an error response and no peripheral access initiates. 09987 * 09988 * Values: 09989 * - 0 - Accesses from an untrusted master are allowed. 09990 * - 1 - Accesses from an untrusted master are not allowed. 09991 */ 09992 /*@{*/ 09993 #define BP_AIPS_PACRM_TP0 (28U) /*!< Bit position for AIPS_PACRM_TP0. */ 09994 #define BM_AIPS_PACRM_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRM_TP0. */ 09995 #define BS_AIPS_PACRM_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP0. */ 09996 09997 /*! @brief Read current value of the AIPS_PACRM_TP0 field. */ 09998 #define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0)) 09999 10000 /*! @brief Format value for bitfield AIPS_PACRM_TP0. */ 10001 #define BF_AIPS_PACRM_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP0) & BM_AIPS_PACRM_TP0) 10002 10003 /*! @brief Set the TP0 field to a new value. */ 10004 #define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v)) 10005 /*@}*/ 10006 10007 /*! 10008 * @name Register AIPS_PACRM, field WP0[29] (RW) 10009 * 10010 * Determines whether the peripheral allows write accesses. When this field is 10011 * set and a write access is attempted, access terminates with an error response 10012 * and no peripheral access initiates. 10013 * 10014 * Values: 10015 * - 0 - This peripheral allows write accesses. 10016 * - 1 - This peripheral is write protected. 10017 */ 10018 /*@{*/ 10019 #define BP_AIPS_PACRM_WP0 (29U) /*!< Bit position for AIPS_PACRM_WP0. */ 10020 #define BM_AIPS_PACRM_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRM_WP0. */ 10021 #define BS_AIPS_PACRM_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP0. */ 10022 10023 /*! @brief Read current value of the AIPS_PACRM_WP0 field. */ 10024 #define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0)) 10025 10026 /*! @brief Format value for bitfield AIPS_PACRM_WP0. */ 10027 #define BF_AIPS_PACRM_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP0) & BM_AIPS_PACRM_WP0) 10028 10029 /*! @brief Set the WP0 field to a new value. */ 10030 #define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v)) 10031 /*@}*/ 10032 10033 /*! 10034 * @name Register AIPS_PACRM, field SP0[30] (RW) 10035 * 10036 * Determines whether the peripheral requires supervisor privilege level for 10037 * accesses. When this field is set, the master privilege level must indicate the 10038 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10039 * must be set. If not, access terminates with an error response and no peripheral 10040 * access initiates. 10041 * 10042 * Values: 10043 * - 0 - This peripheral does not require supervisor privilege level for 10044 * accesses. 10045 * - 1 - This peripheral requires supervisor privilege level for accesses. 10046 */ 10047 /*@{*/ 10048 #define BP_AIPS_PACRM_SP0 (30U) /*!< Bit position for AIPS_PACRM_SP0. */ 10049 #define BM_AIPS_PACRM_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRM_SP0. */ 10050 #define BS_AIPS_PACRM_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP0. */ 10051 10052 /*! @brief Read current value of the AIPS_PACRM_SP0 field. */ 10053 #define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0)) 10054 10055 /*! @brief Format value for bitfield AIPS_PACRM_SP0. */ 10056 #define BF_AIPS_PACRM_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP0) & BM_AIPS_PACRM_SP0) 10057 10058 /*! @brief Set the SP0 field to a new value. */ 10059 #define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v)) 10060 /*@}*/ 10061 10062 /******************************************************************************* 10063 * HW_AIPS_PACRN - Peripheral Access Control Register 10064 ******************************************************************************/ 10065 10066 /*! 10067 * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) 10068 * 10069 * Reset value: 0x44444444U 10070 * 10071 * This section describes PACR registers E-P, which control peripheral slots 10072 * 32-127. See PACRPeripheral Access Control Register for the description of these 10073 * registers. 10074 */ 10075 typedef union _hw_aips_pacrn 10076 { 10077 uint32_t U; 10078 struct _hw_aips_pacrn_bitfields 10079 { 10080 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 10081 uint32_t WP7 : 1; /*!< [1] Write Protect */ 10082 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 10083 uint32_t RESERVED0 : 1; /*!< [3] */ 10084 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 10085 uint32_t WP6 : 1; /*!< [5] Write Protect */ 10086 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 10087 uint32_t RESERVED1 : 1; /*!< [7] */ 10088 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 10089 uint32_t WP5 : 1; /*!< [9] Write Protect */ 10090 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 10091 uint32_t RESERVED2 : 1; /*!< [11] */ 10092 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 10093 uint32_t WP4 : 1; /*!< [13] Write Protect */ 10094 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 10095 uint32_t RESERVED3 : 1; /*!< [15] */ 10096 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 10097 uint32_t WP3 : 1; /*!< [17] Write Protect */ 10098 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 10099 uint32_t RESERVED4 : 1; /*!< [19] */ 10100 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 10101 uint32_t WP2 : 1; /*!< [21] Write Protect */ 10102 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 10103 uint32_t RESERVED5 : 1; /*!< [23] */ 10104 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 10105 uint32_t WP1 : 1; /*!< [25] Write Protect */ 10106 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 10107 uint32_t RESERVED6 : 1; /*!< [27] */ 10108 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 10109 uint32_t WP0 : 1; /*!< [29] Write Protect */ 10110 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 10111 uint32_t RESERVED7 : 1; /*!< [31] */ 10112 } B; 10113 } hw_aips_pacrn_t; 10114 10115 /*! 10116 * @name Constants and macros for entire AIPS_PACRN register 10117 */ 10118 /*@{*/ 10119 #define HW_AIPS_PACRN_ADDR(x) ((x) + 0x64U) 10120 10121 #define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) 10122 #define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U) 10123 #define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v)) 10124 #define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) 10125 #define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) 10126 #define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) 10127 /*@}*/ 10128 10129 /* 10130 * Constants & macros for individual AIPS_PACRN bitfields 10131 */ 10132 10133 /*! 10134 * @name Register AIPS_PACRN, field TP7[0] (RW) 10135 * 10136 * Determines whether the peripheral allows accesses from an untrusted master. 10137 * When this field is set and an access is attempted by an untrusted master, the 10138 * access terminates with an error response and no peripheral access initiates. 10139 * 10140 * Values: 10141 * - 0 - Accesses from an untrusted master are allowed. 10142 * - 1 - Accesses from an untrusted master are not allowed. 10143 */ 10144 /*@{*/ 10145 #define BP_AIPS_PACRN_TP7 (0U) /*!< Bit position for AIPS_PACRN_TP7. */ 10146 #define BM_AIPS_PACRN_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRN_TP7. */ 10147 #define BS_AIPS_PACRN_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP7. */ 10148 10149 /*! @brief Read current value of the AIPS_PACRN_TP7 field. */ 10150 #define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7)) 10151 10152 /*! @brief Format value for bitfield AIPS_PACRN_TP7. */ 10153 #define BF_AIPS_PACRN_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP7) & BM_AIPS_PACRN_TP7) 10154 10155 /*! @brief Set the TP7 field to a new value. */ 10156 #define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v)) 10157 /*@}*/ 10158 10159 /*! 10160 * @name Register AIPS_PACRN, field WP7[1] (RW) 10161 * 10162 * Determines whether the peripheral allows write accesses. When this field is 10163 * set and a write access is attempted, access terminates with an error response 10164 * and no peripheral access initiates. 10165 * 10166 * Values: 10167 * - 0 - This peripheral allows write accesses. 10168 * - 1 - This peripheral is write protected. 10169 */ 10170 /*@{*/ 10171 #define BP_AIPS_PACRN_WP7 (1U) /*!< Bit position for AIPS_PACRN_WP7. */ 10172 #define BM_AIPS_PACRN_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRN_WP7. */ 10173 #define BS_AIPS_PACRN_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP7. */ 10174 10175 /*! @brief Read current value of the AIPS_PACRN_WP7 field. */ 10176 #define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7)) 10177 10178 /*! @brief Format value for bitfield AIPS_PACRN_WP7. */ 10179 #define BF_AIPS_PACRN_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP7) & BM_AIPS_PACRN_WP7) 10180 10181 /*! @brief Set the WP7 field to a new value. */ 10182 #define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v)) 10183 /*@}*/ 10184 10185 /*! 10186 * @name Register AIPS_PACRN, field SP7[2] (RW) 10187 * 10188 * Determines whether the peripheral requires supervisor privilege level for 10189 * accesses. When this field is set, the master privilege level must indicate the 10190 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10191 * must be set. If not, access terminates with an error response and no peripheral 10192 * access initiates. 10193 * 10194 * Values: 10195 * - 0 - This peripheral does not require supervisor privilege level for 10196 * accesses. 10197 * - 1 - This peripheral requires supervisor privilege level for accesses. 10198 */ 10199 /*@{*/ 10200 #define BP_AIPS_PACRN_SP7 (2U) /*!< Bit position for AIPS_PACRN_SP7. */ 10201 #define BM_AIPS_PACRN_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRN_SP7. */ 10202 #define BS_AIPS_PACRN_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP7. */ 10203 10204 /*! @brief Read current value of the AIPS_PACRN_SP7 field. */ 10205 #define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7)) 10206 10207 /*! @brief Format value for bitfield AIPS_PACRN_SP7. */ 10208 #define BF_AIPS_PACRN_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP7) & BM_AIPS_PACRN_SP7) 10209 10210 /*! @brief Set the SP7 field to a new value. */ 10211 #define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v)) 10212 /*@}*/ 10213 10214 /*! 10215 * @name Register AIPS_PACRN, field TP6[4] (RW) 10216 * 10217 * Determines whether the peripheral allows accesses from an untrusted master. 10218 * When this field is set and an access is attempted by an untrusted master, the 10219 * access terminates with an error response and no peripheral access initiates. 10220 * 10221 * Values: 10222 * - 0 - Accesses from an untrusted master are allowed. 10223 * - 1 - Accesses from an untrusted master are not allowed. 10224 */ 10225 /*@{*/ 10226 #define BP_AIPS_PACRN_TP6 (4U) /*!< Bit position for AIPS_PACRN_TP6. */ 10227 #define BM_AIPS_PACRN_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRN_TP6. */ 10228 #define BS_AIPS_PACRN_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP6. */ 10229 10230 /*! @brief Read current value of the AIPS_PACRN_TP6 field. */ 10231 #define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6)) 10232 10233 /*! @brief Format value for bitfield AIPS_PACRN_TP6. */ 10234 #define BF_AIPS_PACRN_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP6) & BM_AIPS_PACRN_TP6) 10235 10236 /*! @brief Set the TP6 field to a new value. */ 10237 #define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v)) 10238 /*@}*/ 10239 10240 /*! 10241 * @name Register AIPS_PACRN, field WP6[5] (RW) 10242 * 10243 * Determines whether the peripheral allows write accesses. When this field is 10244 * set and a write access is attempted, access terminates with an error response 10245 * and no peripheral access initiates. 10246 * 10247 * Values: 10248 * - 0 - This peripheral allows write accesses. 10249 * - 1 - This peripheral is write protected. 10250 */ 10251 /*@{*/ 10252 #define BP_AIPS_PACRN_WP6 (5U) /*!< Bit position for AIPS_PACRN_WP6. */ 10253 #define BM_AIPS_PACRN_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRN_WP6. */ 10254 #define BS_AIPS_PACRN_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP6. */ 10255 10256 /*! @brief Read current value of the AIPS_PACRN_WP6 field. */ 10257 #define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6)) 10258 10259 /*! @brief Format value for bitfield AIPS_PACRN_WP6. */ 10260 #define BF_AIPS_PACRN_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP6) & BM_AIPS_PACRN_WP6) 10261 10262 /*! @brief Set the WP6 field to a new value. */ 10263 #define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v)) 10264 /*@}*/ 10265 10266 /*! 10267 * @name Register AIPS_PACRN, field SP6[6] (RW) 10268 * 10269 * Determines whether the peripheral requires supervisor privilege level for 10270 * accesses. When this field is set, the master privilege level must indicate the 10271 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10272 * must be set. If not, access terminates with an error response and no peripheral 10273 * access initiates. 10274 * 10275 * Values: 10276 * - 0 - This peripheral does not require supervisor privilege level for 10277 * accesses. 10278 * - 1 - This peripheral requires supervisor privilege level for accesses. 10279 */ 10280 /*@{*/ 10281 #define BP_AIPS_PACRN_SP6 (6U) /*!< Bit position for AIPS_PACRN_SP6. */ 10282 #define BM_AIPS_PACRN_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRN_SP6. */ 10283 #define BS_AIPS_PACRN_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP6. */ 10284 10285 /*! @brief Read current value of the AIPS_PACRN_SP6 field. */ 10286 #define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6)) 10287 10288 /*! @brief Format value for bitfield AIPS_PACRN_SP6. */ 10289 #define BF_AIPS_PACRN_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP6) & BM_AIPS_PACRN_SP6) 10290 10291 /*! @brief Set the SP6 field to a new value. */ 10292 #define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v)) 10293 /*@}*/ 10294 10295 /*! 10296 * @name Register AIPS_PACRN, field TP5[8] (RW) 10297 * 10298 * Determines whether the peripheral allows accesses from an untrusted master. 10299 * When this field is set and an access is attempted by an untrusted master, the 10300 * access terminates with an error response and no peripheral access initiates. 10301 * 10302 * Values: 10303 * - 0 - Accesses from an untrusted master are allowed. 10304 * - 1 - Accesses from an untrusted master are not allowed. 10305 */ 10306 /*@{*/ 10307 #define BP_AIPS_PACRN_TP5 (8U) /*!< Bit position for AIPS_PACRN_TP5. */ 10308 #define BM_AIPS_PACRN_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRN_TP5. */ 10309 #define BS_AIPS_PACRN_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP5. */ 10310 10311 /*! @brief Read current value of the AIPS_PACRN_TP5 field. */ 10312 #define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5)) 10313 10314 /*! @brief Format value for bitfield AIPS_PACRN_TP5. */ 10315 #define BF_AIPS_PACRN_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP5) & BM_AIPS_PACRN_TP5) 10316 10317 /*! @brief Set the TP5 field to a new value. */ 10318 #define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v)) 10319 /*@}*/ 10320 10321 /*! 10322 * @name Register AIPS_PACRN, field WP5[9] (RW) 10323 * 10324 * Determines whether the peripheral allows write accesses. When this field is 10325 * set and a write access is attempted, access terminates with an error response 10326 * and no peripheral access initiates. 10327 * 10328 * Values: 10329 * - 0 - This peripheral allows write accesses. 10330 * - 1 - This peripheral is write protected. 10331 */ 10332 /*@{*/ 10333 #define BP_AIPS_PACRN_WP5 (9U) /*!< Bit position for AIPS_PACRN_WP5. */ 10334 #define BM_AIPS_PACRN_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRN_WP5. */ 10335 #define BS_AIPS_PACRN_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP5. */ 10336 10337 /*! @brief Read current value of the AIPS_PACRN_WP5 field. */ 10338 #define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5)) 10339 10340 /*! @brief Format value for bitfield AIPS_PACRN_WP5. */ 10341 #define BF_AIPS_PACRN_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP5) & BM_AIPS_PACRN_WP5) 10342 10343 /*! @brief Set the WP5 field to a new value. */ 10344 #define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v)) 10345 /*@}*/ 10346 10347 /*! 10348 * @name Register AIPS_PACRN, field SP5[10] (RW) 10349 * 10350 * Determines whether the peripheral requires supervisor privilege level for 10351 * accesses. When this field is set, the master privilege level must indicate the 10352 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10353 * must be set. If not, access terminates with an error response and no peripheral 10354 * access initiates. 10355 * 10356 * Values: 10357 * - 0 - This peripheral does not require supervisor privilege level for 10358 * accesses. 10359 * - 1 - This peripheral requires supervisor privilege level for accesses. 10360 */ 10361 /*@{*/ 10362 #define BP_AIPS_PACRN_SP5 (10U) /*!< Bit position for AIPS_PACRN_SP5. */ 10363 #define BM_AIPS_PACRN_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRN_SP5. */ 10364 #define BS_AIPS_PACRN_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP5. */ 10365 10366 /*! @brief Read current value of the AIPS_PACRN_SP5 field. */ 10367 #define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5)) 10368 10369 /*! @brief Format value for bitfield AIPS_PACRN_SP5. */ 10370 #define BF_AIPS_PACRN_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP5) & BM_AIPS_PACRN_SP5) 10371 10372 /*! @brief Set the SP5 field to a new value. */ 10373 #define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v)) 10374 /*@}*/ 10375 10376 /*! 10377 * @name Register AIPS_PACRN, field TP4[12] (RW) 10378 * 10379 * Determines whether the peripheral allows accesses from an untrusted master. 10380 * When this bit is set and an access is attempted by an untrusted master, the 10381 * access terminates with an error response and no peripheral access initiates. 10382 * 10383 * Values: 10384 * - 0 - Accesses from an untrusted master are allowed. 10385 * - 1 - Accesses from an untrusted master are not allowed. 10386 */ 10387 /*@{*/ 10388 #define BP_AIPS_PACRN_TP4 (12U) /*!< Bit position for AIPS_PACRN_TP4. */ 10389 #define BM_AIPS_PACRN_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRN_TP4. */ 10390 #define BS_AIPS_PACRN_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP4. */ 10391 10392 /*! @brief Read current value of the AIPS_PACRN_TP4 field. */ 10393 #define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4)) 10394 10395 /*! @brief Format value for bitfield AIPS_PACRN_TP4. */ 10396 #define BF_AIPS_PACRN_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP4) & BM_AIPS_PACRN_TP4) 10397 10398 /*! @brief Set the TP4 field to a new value. */ 10399 #define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v)) 10400 /*@}*/ 10401 10402 /*! 10403 * @name Register AIPS_PACRN, field WP4[13] (RW) 10404 * 10405 * Determines whether the peripheral allows write accesses. When this field is 10406 * set and a write access is attempted, access terminates with an error response 10407 * and no peripheral access initiates. 10408 * 10409 * Values: 10410 * - 0 - This peripheral allows write accesses. 10411 * - 1 - This peripheral is write protected. 10412 */ 10413 /*@{*/ 10414 #define BP_AIPS_PACRN_WP4 (13U) /*!< Bit position for AIPS_PACRN_WP4. */ 10415 #define BM_AIPS_PACRN_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRN_WP4. */ 10416 #define BS_AIPS_PACRN_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP4. */ 10417 10418 /*! @brief Read current value of the AIPS_PACRN_WP4 field. */ 10419 #define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4)) 10420 10421 /*! @brief Format value for bitfield AIPS_PACRN_WP4. */ 10422 #define BF_AIPS_PACRN_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP4) & BM_AIPS_PACRN_WP4) 10423 10424 /*! @brief Set the WP4 field to a new value. */ 10425 #define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v)) 10426 /*@}*/ 10427 10428 /*! 10429 * @name Register AIPS_PACRN, field SP4[14] (RW) 10430 * 10431 * Determines whether the peripheral requires supervisor privilege level for 10432 * access. When this bit is set, the master privilege level must indicate the 10433 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 10434 * set. If not, access terminates with an error response and no peripheral access 10435 * initiates. 10436 * 10437 * Values: 10438 * - 0 - This peripheral does not require supervisor privilege level for 10439 * accesses. 10440 * - 1 - This peripheral requires supervisor privilege level for accesses. 10441 */ 10442 /*@{*/ 10443 #define BP_AIPS_PACRN_SP4 (14U) /*!< Bit position for AIPS_PACRN_SP4. */ 10444 #define BM_AIPS_PACRN_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRN_SP4. */ 10445 #define BS_AIPS_PACRN_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP4. */ 10446 10447 /*! @brief Read current value of the AIPS_PACRN_SP4 field. */ 10448 #define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4)) 10449 10450 /*! @brief Format value for bitfield AIPS_PACRN_SP4. */ 10451 #define BF_AIPS_PACRN_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP4) & BM_AIPS_PACRN_SP4) 10452 10453 /*! @brief Set the SP4 field to a new value. */ 10454 #define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v)) 10455 /*@}*/ 10456 10457 /*! 10458 * @name Register AIPS_PACRN, field TP3[16] (RW) 10459 * 10460 * Determines whether the peripheral allows accesses from an untrusted master. 10461 * When this field is set and an access is attempted by an untrusted master, the 10462 * access terminates with an error response and no peripheral access initiates. 10463 * 10464 * Values: 10465 * - 0 - Accesses from an untrusted master are allowed. 10466 * - 1 - Accesses from an untrusted master are not allowed. 10467 */ 10468 /*@{*/ 10469 #define BP_AIPS_PACRN_TP3 (16U) /*!< Bit position for AIPS_PACRN_TP3. */ 10470 #define BM_AIPS_PACRN_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRN_TP3. */ 10471 #define BS_AIPS_PACRN_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP3. */ 10472 10473 /*! @brief Read current value of the AIPS_PACRN_TP3 field. */ 10474 #define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3)) 10475 10476 /*! @brief Format value for bitfield AIPS_PACRN_TP3. */ 10477 #define BF_AIPS_PACRN_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP3) & BM_AIPS_PACRN_TP3) 10478 10479 /*! @brief Set the TP3 field to a new value. */ 10480 #define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v)) 10481 /*@}*/ 10482 10483 /*! 10484 * @name Register AIPS_PACRN, field WP3[17] (RW) 10485 * 10486 * Determines whether the peripheral allows write accesss. When this bit is set 10487 * and a write access is attempted, access terminates with an error response and 10488 * no peripheral access initiates. 10489 * 10490 * Values: 10491 * - 0 - This peripheral allows write accesses. 10492 * - 1 - This peripheral is write protected. 10493 */ 10494 /*@{*/ 10495 #define BP_AIPS_PACRN_WP3 (17U) /*!< Bit position for AIPS_PACRN_WP3. */ 10496 #define BM_AIPS_PACRN_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRN_WP3. */ 10497 #define BS_AIPS_PACRN_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP3. */ 10498 10499 /*! @brief Read current value of the AIPS_PACRN_WP3 field. */ 10500 #define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3)) 10501 10502 /*! @brief Format value for bitfield AIPS_PACRN_WP3. */ 10503 #define BF_AIPS_PACRN_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP3) & BM_AIPS_PACRN_WP3) 10504 10505 /*! @brief Set the WP3 field to a new value. */ 10506 #define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v)) 10507 /*@}*/ 10508 10509 /*! 10510 * @name Register AIPS_PACRN, field SP3[18] (RW) 10511 * 10512 * Determines whether the peripheral requires supervisor privilege level for 10513 * accesses. When this field is set, the master privilege level must indicate the 10514 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10515 * must be set. If not, access terminates with an error response and no peripheral 10516 * access initiates. 10517 * 10518 * Values: 10519 * - 0 - This peripheral does not require supervisor privilege level for 10520 * accesses. 10521 * - 1 - This peripheral requires supervisor privilege level for accesses. 10522 */ 10523 /*@{*/ 10524 #define BP_AIPS_PACRN_SP3 (18U) /*!< Bit position for AIPS_PACRN_SP3. */ 10525 #define BM_AIPS_PACRN_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRN_SP3. */ 10526 #define BS_AIPS_PACRN_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP3. */ 10527 10528 /*! @brief Read current value of the AIPS_PACRN_SP3 field. */ 10529 #define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3)) 10530 10531 /*! @brief Format value for bitfield AIPS_PACRN_SP3. */ 10532 #define BF_AIPS_PACRN_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP3) & BM_AIPS_PACRN_SP3) 10533 10534 /*! @brief Set the SP3 field to a new value. */ 10535 #define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v)) 10536 /*@}*/ 10537 10538 /*! 10539 * @name Register AIPS_PACRN, field TP2[20] (RW) 10540 * 10541 * Determines whether the peripheral allows accesses from an untrusted master. 10542 * When this bit is set and an access is attempted by an untrusted master, the 10543 * access terminates with an error response and no peripheral access initiates. 10544 * 10545 * Values: 10546 * - 0 - Accesses from an untrusted master are allowed. 10547 * - 1 - Accesses from an untrusted master are not allowed. 10548 */ 10549 /*@{*/ 10550 #define BP_AIPS_PACRN_TP2 (20U) /*!< Bit position for AIPS_PACRN_TP2. */ 10551 #define BM_AIPS_PACRN_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRN_TP2. */ 10552 #define BS_AIPS_PACRN_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP2. */ 10553 10554 /*! @brief Read current value of the AIPS_PACRN_TP2 field. */ 10555 #define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2)) 10556 10557 /*! @brief Format value for bitfield AIPS_PACRN_TP2. */ 10558 #define BF_AIPS_PACRN_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP2) & BM_AIPS_PACRN_TP2) 10559 10560 /*! @brief Set the TP2 field to a new value. */ 10561 #define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v)) 10562 /*@}*/ 10563 10564 /*! 10565 * @name Register AIPS_PACRN, field WP2[21] (RW) 10566 * 10567 * Determines whether the peripheral allows write accesses. When this field is 10568 * set and a write access is attempted, access terminates with an error response 10569 * and no peripheral access initiates. 10570 * 10571 * Values: 10572 * - 0 - This peripheral allows write accesses. 10573 * - 1 - This peripheral is write protected. 10574 */ 10575 /*@{*/ 10576 #define BP_AIPS_PACRN_WP2 (21U) /*!< Bit position for AIPS_PACRN_WP2. */ 10577 #define BM_AIPS_PACRN_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRN_WP2. */ 10578 #define BS_AIPS_PACRN_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP2. */ 10579 10580 /*! @brief Read current value of the AIPS_PACRN_WP2 field. */ 10581 #define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2)) 10582 10583 /*! @brief Format value for bitfield AIPS_PACRN_WP2. */ 10584 #define BF_AIPS_PACRN_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP2) & BM_AIPS_PACRN_WP2) 10585 10586 /*! @brief Set the WP2 field to a new value. */ 10587 #define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v)) 10588 /*@}*/ 10589 10590 /*! 10591 * @name Register AIPS_PACRN, field SP2[22] (RW) 10592 * 10593 * Determines whether the peripheral requires supervisor privilege level for 10594 * access. When this bit is set, the master privilege level must indicate the 10595 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 10596 * set. If not, access terminates with an error response and no peripheral access 10597 * initiates. 10598 * 10599 * Values: 10600 * - 0 - This peripheral does not require supervisor privilege level for 10601 * accesses. 10602 * - 1 - This peripheral requires supervisor privilege level for accesses. 10603 */ 10604 /*@{*/ 10605 #define BP_AIPS_PACRN_SP2 (22U) /*!< Bit position for AIPS_PACRN_SP2. */ 10606 #define BM_AIPS_PACRN_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRN_SP2. */ 10607 #define BS_AIPS_PACRN_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP2. */ 10608 10609 /*! @brief Read current value of the AIPS_PACRN_SP2 field. */ 10610 #define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2)) 10611 10612 /*! @brief Format value for bitfield AIPS_PACRN_SP2. */ 10613 #define BF_AIPS_PACRN_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP2) & BM_AIPS_PACRN_SP2) 10614 10615 /*! @brief Set the SP2 field to a new value. */ 10616 #define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v)) 10617 /*@}*/ 10618 10619 /*! 10620 * @name Register AIPS_PACRN, field TP1[24] (RW) 10621 * 10622 * Determines whether the peripheral allows accesses from an untrusted master. 10623 * When this field is set and an access is attempted by an untrusted master, the 10624 * access terminates with an error response and no peripheral access initiates. 10625 * 10626 * Values: 10627 * - 0 - Accesses from an untrusted master are allowed. 10628 * - 1 - Accesses from an untrusted master are not allowed. 10629 */ 10630 /*@{*/ 10631 #define BP_AIPS_PACRN_TP1 (24U) /*!< Bit position for AIPS_PACRN_TP1. */ 10632 #define BM_AIPS_PACRN_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRN_TP1. */ 10633 #define BS_AIPS_PACRN_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP1. */ 10634 10635 /*! @brief Read current value of the AIPS_PACRN_TP1 field. */ 10636 #define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1)) 10637 10638 /*! @brief Format value for bitfield AIPS_PACRN_TP1. */ 10639 #define BF_AIPS_PACRN_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP1) & BM_AIPS_PACRN_TP1) 10640 10641 /*! @brief Set the TP1 field to a new value. */ 10642 #define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v)) 10643 /*@}*/ 10644 10645 /*! 10646 * @name Register AIPS_PACRN, field WP1[25] (RW) 10647 * 10648 * Determines whether the peripheral allows write accesses. When this field is 10649 * set and a write access is attempted, access terminates with an error response 10650 * and no peripheral access initiates. 10651 * 10652 * Values: 10653 * - 0 - This peripheral allows write accesses. 10654 * - 1 - This peripheral is write protected. 10655 */ 10656 /*@{*/ 10657 #define BP_AIPS_PACRN_WP1 (25U) /*!< Bit position for AIPS_PACRN_WP1. */ 10658 #define BM_AIPS_PACRN_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRN_WP1. */ 10659 #define BS_AIPS_PACRN_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP1. */ 10660 10661 /*! @brief Read current value of the AIPS_PACRN_WP1 field. */ 10662 #define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1)) 10663 10664 /*! @brief Format value for bitfield AIPS_PACRN_WP1. */ 10665 #define BF_AIPS_PACRN_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP1) & BM_AIPS_PACRN_WP1) 10666 10667 /*! @brief Set the WP1 field to a new value. */ 10668 #define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v)) 10669 /*@}*/ 10670 10671 /*! 10672 * @name Register AIPS_PACRN, field SP1[26] (RW) 10673 * 10674 * Determines whether the peripheral requires supervisor privilege level for 10675 * access. When this field is set, the master privilege level must indicate the 10676 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 10677 * be set. If not, access terminates with an error response and no peripheral 10678 * access initiates. 10679 * 10680 * Values: 10681 * - 0 - This peripheral does not require supervisor privilege level for 10682 * accesses. 10683 * - 1 - This peripheral requires supervisor privilege level for accesses. 10684 */ 10685 /*@{*/ 10686 #define BP_AIPS_PACRN_SP1 (26U) /*!< Bit position for AIPS_PACRN_SP1. */ 10687 #define BM_AIPS_PACRN_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRN_SP1. */ 10688 #define BS_AIPS_PACRN_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP1. */ 10689 10690 /*! @brief Read current value of the AIPS_PACRN_SP1 field. */ 10691 #define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1)) 10692 10693 /*! @brief Format value for bitfield AIPS_PACRN_SP1. */ 10694 #define BF_AIPS_PACRN_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP1) & BM_AIPS_PACRN_SP1) 10695 10696 /*! @brief Set the SP1 field to a new value. */ 10697 #define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v)) 10698 /*@}*/ 10699 10700 /*! 10701 * @name Register AIPS_PACRN, field TP0[28] (RW) 10702 * 10703 * Determines whether the peripheral allows accesses from an untrusted master. 10704 * When this bit is set and an access is attempted by an untrusted master, the 10705 * access terminates with an error response and no peripheral access initiates. 10706 * 10707 * Values: 10708 * - 0 - Accesses from an untrusted master are allowed. 10709 * - 1 - Accesses from an untrusted master are not allowed. 10710 */ 10711 /*@{*/ 10712 #define BP_AIPS_PACRN_TP0 (28U) /*!< Bit position for AIPS_PACRN_TP0. */ 10713 #define BM_AIPS_PACRN_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRN_TP0. */ 10714 #define BS_AIPS_PACRN_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP0. */ 10715 10716 /*! @brief Read current value of the AIPS_PACRN_TP0 field. */ 10717 #define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0)) 10718 10719 /*! @brief Format value for bitfield AIPS_PACRN_TP0. */ 10720 #define BF_AIPS_PACRN_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP0) & BM_AIPS_PACRN_TP0) 10721 10722 /*! @brief Set the TP0 field to a new value. */ 10723 #define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v)) 10724 /*@}*/ 10725 10726 /*! 10727 * @name Register AIPS_PACRN, field WP0[29] (RW) 10728 * 10729 * Determines whether the peripheral allows write accesses. When this field is 10730 * set and a write access is attempted, access terminates with an error response 10731 * and no peripheral access initiates. 10732 * 10733 * Values: 10734 * - 0 - This peripheral allows write accesses. 10735 * - 1 - This peripheral is write protected. 10736 */ 10737 /*@{*/ 10738 #define BP_AIPS_PACRN_WP0 (29U) /*!< Bit position for AIPS_PACRN_WP0. */ 10739 #define BM_AIPS_PACRN_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRN_WP0. */ 10740 #define BS_AIPS_PACRN_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP0. */ 10741 10742 /*! @brief Read current value of the AIPS_PACRN_WP0 field. */ 10743 #define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0)) 10744 10745 /*! @brief Format value for bitfield AIPS_PACRN_WP0. */ 10746 #define BF_AIPS_PACRN_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP0) & BM_AIPS_PACRN_WP0) 10747 10748 /*! @brief Set the WP0 field to a new value. */ 10749 #define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v)) 10750 /*@}*/ 10751 10752 /*! 10753 * @name Register AIPS_PACRN, field SP0[30] (RW) 10754 * 10755 * Determines whether the peripheral requires supervisor privilege level for 10756 * accesses. When this field is set, the master privilege level must indicate the 10757 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10758 * must be set. If not, access terminates with an error response and no peripheral 10759 * access initiates. 10760 * 10761 * Values: 10762 * - 0 - This peripheral does not require supervisor privilege level for 10763 * accesses. 10764 * - 1 - This peripheral requires supervisor privilege level for accesses. 10765 */ 10766 /*@{*/ 10767 #define BP_AIPS_PACRN_SP0 (30U) /*!< Bit position for AIPS_PACRN_SP0. */ 10768 #define BM_AIPS_PACRN_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRN_SP0. */ 10769 #define BS_AIPS_PACRN_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP0. */ 10770 10771 /*! @brief Read current value of the AIPS_PACRN_SP0 field. */ 10772 #define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0)) 10773 10774 /*! @brief Format value for bitfield AIPS_PACRN_SP0. */ 10775 #define BF_AIPS_PACRN_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP0) & BM_AIPS_PACRN_SP0) 10776 10777 /*! @brief Set the SP0 field to a new value. */ 10778 #define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v)) 10779 /*@}*/ 10780 10781 /******************************************************************************* 10782 * HW_AIPS_PACRO - Peripheral Access Control Register 10783 ******************************************************************************/ 10784 10785 /*! 10786 * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) 10787 * 10788 * Reset value: 0x44444444U 10789 * 10790 * This section describes PACR registers E-P, which control peripheral slots 10791 * 32-127. See PACRPeripheral Access Control Register for the description of these 10792 * registers. 10793 */ 10794 typedef union _hw_aips_pacro 10795 { 10796 uint32_t U; 10797 struct _hw_aips_pacro_bitfields 10798 { 10799 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 10800 uint32_t WP7 : 1; /*!< [1] Write Protect */ 10801 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 10802 uint32_t RESERVED0 : 1; /*!< [3] */ 10803 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 10804 uint32_t WP6 : 1; /*!< [5] Write Protect */ 10805 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 10806 uint32_t RESERVED1 : 1; /*!< [7] */ 10807 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 10808 uint32_t WP5 : 1; /*!< [9] Write Protect */ 10809 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 10810 uint32_t RESERVED2 : 1; /*!< [11] */ 10811 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 10812 uint32_t WP4 : 1; /*!< [13] Write Protect */ 10813 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 10814 uint32_t RESERVED3 : 1; /*!< [15] */ 10815 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 10816 uint32_t WP3 : 1; /*!< [17] Write Protect */ 10817 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 10818 uint32_t RESERVED4 : 1; /*!< [19] */ 10819 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 10820 uint32_t WP2 : 1; /*!< [21] Write Protect */ 10821 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 10822 uint32_t RESERVED5 : 1; /*!< [23] */ 10823 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 10824 uint32_t WP1 : 1; /*!< [25] Write Protect */ 10825 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 10826 uint32_t RESERVED6 : 1; /*!< [27] */ 10827 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 10828 uint32_t WP0 : 1; /*!< [29] Write Protect */ 10829 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 10830 uint32_t RESERVED7 : 1; /*!< [31] */ 10831 } B; 10832 } hw_aips_pacro_t; 10833 10834 /*! 10835 * @name Constants and macros for entire AIPS_PACRO register 10836 */ 10837 /*@{*/ 10838 #define HW_AIPS_PACRO_ADDR(x) ((x) + 0x68U) 10839 10840 #define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) 10841 #define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U) 10842 #define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v)) 10843 #define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) 10844 #define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) 10845 #define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) 10846 /*@}*/ 10847 10848 /* 10849 * Constants & macros for individual AIPS_PACRO bitfields 10850 */ 10851 10852 /*! 10853 * @name Register AIPS_PACRO, field TP7[0] (RW) 10854 * 10855 * Determines whether the peripheral allows accesses from an untrusted master. 10856 * When this field is set and an access is attempted by an untrusted master, the 10857 * access terminates with an error response and no peripheral access initiates. 10858 * 10859 * Values: 10860 * - 0 - Accesses from an untrusted master are allowed. 10861 * - 1 - Accesses from an untrusted master are not allowed. 10862 */ 10863 /*@{*/ 10864 #define BP_AIPS_PACRO_TP7 (0U) /*!< Bit position for AIPS_PACRO_TP7. */ 10865 #define BM_AIPS_PACRO_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRO_TP7. */ 10866 #define BS_AIPS_PACRO_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP7. */ 10867 10868 /*! @brief Read current value of the AIPS_PACRO_TP7 field. */ 10869 #define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7)) 10870 10871 /*! @brief Format value for bitfield AIPS_PACRO_TP7. */ 10872 #define BF_AIPS_PACRO_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP7) & BM_AIPS_PACRO_TP7) 10873 10874 /*! @brief Set the TP7 field to a new value. */ 10875 #define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v)) 10876 /*@}*/ 10877 10878 /*! 10879 * @name Register AIPS_PACRO, field WP7[1] (RW) 10880 * 10881 * Determines whether the peripheral allows write accesses. When this field is 10882 * set and a write access is attempted, access terminates with an error response 10883 * and no peripheral access initiates. 10884 * 10885 * Values: 10886 * - 0 - This peripheral allows write accesses. 10887 * - 1 - This peripheral is write protected. 10888 */ 10889 /*@{*/ 10890 #define BP_AIPS_PACRO_WP7 (1U) /*!< Bit position for AIPS_PACRO_WP7. */ 10891 #define BM_AIPS_PACRO_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRO_WP7. */ 10892 #define BS_AIPS_PACRO_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP7. */ 10893 10894 /*! @brief Read current value of the AIPS_PACRO_WP7 field. */ 10895 #define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7)) 10896 10897 /*! @brief Format value for bitfield AIPS_PACRO_WP7. */ 10898 #define BF_AIPS_PACRO_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP7) & BM_AIPS_PACRO_WP7) 10899 10900 /*! @brief Set the WP7 field to a new value. */ 10901 #define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v)) 10902 /*@}*/ 10903 10904 /*! 10905 * @name Register AIPS_PACRO, field SP7[2] (RW) 10906 * 10907 * Determines whether the peripheral requires supervisor privilege level for 10908 * accesses. When this field is set, the master privilege level must indicate the 10909 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10910 * must be set. If not, access terminates with an error response and no peripheral 10911 * access initiates. 10912 * 10913 * Values: 10914 * - 0 - This peripheral does not require supervisor privilege level for 10915 * accesses. 10916 * - 1 - This peripheral requires supervisor privilege level for accesses. 10917 */ 10918 /*@{*/ 10919 #define BP_AIPS_PACRO_SP7 (2U) /*!< Bit position for AIPS_PACRO_SP7. */ 10920 #define BM_AIPS_PACRO_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRO_SP7. */ 10921 #define BS_AIPS_PACRO_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP7. */ 10922 10923 /*! @brief Read current value of the AIPS_PACRO_SP7 field. */ 10924 #define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7)) 10925 10926 /*! @brief Format value for bitfield AIPS_PACRO_SP7. */ 10927 #define BF_AIPS_PACRO_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP7) & BM_AIPS_PACRO_SP7) 10928 10929 /*! @brief Set the SP7 field to a new value. */ 10930 #define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v)) 10931 /*@}*/ 10932 10933 /*! 10934 * @name Register AIPS_PACRO, field TP6[4] (RW) 10935 * 10936 * Determines whether the peripheral allows accesses from an untrusted master. 10937 * When this field is set and an access is attempted by an untrusted master, the 10938 * access terminates with an error response and no peripheral access initiates. 10939 * 10940 * Values: 10941 * - 0 - Accesses from an untrusted master are allowed. 10942 * - 1 - Accesses from an untrusted master are not allowed. 10943 */ 10944 /*@{*/ 10945 #define BP_AIPS_PACRO_TP6 (4U) /*!< Bit position for AIPS_PACRO_TP6. */ 10946 #define BM_AIPS_PACRO_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRO_TP6. */ 10947 #define BS_AIPS_PACRO_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP6. */ 10948 10949 /*! @brief Read current value of the AIPS_PACRO_TP6 field. */ 10950 #define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6)) 10951 10952 /*! @brief Format value for bitfield AIPS_PACRO_TP6. */ 10953 #define BF_AIPS_PACRO_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP6) & BM_AIPS_PACRO_TP6) 10954 10955 /*! @brief Set the TP6 field to a new value. */ 10956 #define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v)) 10957 /*@}*/ 10958 10959 /*! 10960 * @name Register AIPS_PACRO, field WP6[5] (RW) 10961 * 10962 * Determines whether the peripheral allows write accesses. When this field is 10963 * set and a write access is attempted, access terminates with an error response 10964 * and no peripheral access initiates. 10965 * 10966 * Values: 10967 * - 0 - This peripheral allows write accesses. 10968 * - 1 - This peripheral is write protected. 10969 */ 10970 /*@{*/ 10971 #define BP_AIPS_PACRO_WP6 (5U) /*!< Bit position for AIPS_PACRO_WP6. */ 10972 #define BM_AIPS_PACRO_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRO_WP6. */ 10973 #define BS_AIPS_PACRO_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP6. */ 10974 10975 /*! @brief Read current value of the AIPS_PACRO_WP6 field. */ 10976 #define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6)) 10977 10978 /*! @brief Format value for bitfield AIPS_PACRO_WP6. */ 10979 #define BF_AIPS_PACRO_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP6) & BM_AIPS_PACRO_WP6) 10980 10981 /*! @brief Set the WP6 field to a new value. */ 10982 #define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v)) 10983 /*@}*/ 10984 10985 /*! 10986 * @name Register AIPS_PACRO, field SP6[6] (RW) 10987 * 10988 * Determines whether the peripheral requires supervisor privilege level for 10989 * accesses. When this field is set, the master privilege level must indicate the 10990 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10991 * must be set. If not, access terminates with an error response and no peripheral 10992 * access initiates. 10993 * 10994 * Values: 10995 * - 0 - This peripheral does not require supervisor privilege level for 10996 * accesses. 10997 * - 1 - This peripheral requires supervisor privilege level for accesses. 10998 */ 10999 /*@{*/ 11000 #define BP_AIPS_PACRO_SP6 (6U) /*!< Bit position for AIPS_PACRO_SP6. */ 11001 #define BM_AIPS_PACRO_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRO_SP6. */ 11002 #define BS_AIPS_PACRO_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP6. */ 11003 11004 /*! @brief Read current value of the AIPS_PACRO_SP6 field. */ 11005 #define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6)) 11006 11007 /*! @brief Format value for bitfield AIPS_PACRO_SP6. */ 11008 #define BF_AIPS_PACRO_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP6) & BM_AIPS_PACRO_SP6) 11009 11010 /*! @brief Set the SP6 field to a new value. */ 11011 #define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v)) 11012 /*@}*/ 11013 11014 /*! 11015 * @name Register AIPS_PACRO, field TP5[8] (RW) 11016 * 11017 * Determines whether the peripheral allows accesses from an untrusted master. 11018 * When this field is set and an access is attempted by an untrusted master, the 11019 * access terminates with an error response and no peripheral access initiates. 11020 * 11021 * Values: 11022 * - 0 - Accesses from an untrusted master are allowed. 11023 * - 1 - Accesses from an untrusted master are not allowed. 11024 */ 11025 /*@{*/ 11026 #define BP_AIPS_PACRO_TP5 (8U) /*!< Bit position for AIPS_PACRO_TP5. */ 11027 #define BM_AIPS_PACRO_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRO_TP5. */ 11028 #define BS_AIPS_PACRO_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP5. */ 11029 11030 /*! @brief Read current value of the AIPS_PACRO_TP5 field. */ 11031 #define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5)) 11032 11033 /*! @brief Format value for bitfield AIPS_PACRO_TP5. */ 11034 #define BF_AIPS_PACRO_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP5) & BM_AIPS_PACRO_TP5) 11035 11036 /*! @brief Set the TP5 field to a new value. */ 11037 #define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v)) 11038 /*@}*/ 11039 11040 /*! 11041 * @name Register AIPS_PACRO, field WP5[9] (RW) 11042 * 11043 * Determines whether the peripheral allows write accesses. When this field is 11044 * set and a write access is attempted, access terminates with an error response 11045 * and no peripheral access initiates. 11046 * 11047 * Values: 11048 * - 0 - This peripheral allows write accesses. 11049 * - 1 - This peripheral is write protected. 11050 */ 11051 /*@{*/ 11052 #define BP_AIPS_PACRO_WP5 (9U) /*!< Bit position for AIPS_PACRO_WP5. */ 11053 #define BM_AIPS_PACRO_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRO_WP5. */ 11054 #define BS_AIPS_PACRO_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP5. */ 11055 11056 /*! @brief Read current value of the AIPS_PACRO_WP5 field. */ 11057 #define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5)) 11058 11059 /*! @brief Format value for bitfield AIPS_PACRO_WP5. */ 11060 #define BF_AIPS_PACRO_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP5) & BM_AIPS_PACRO_WP5) 11061 11062 /*! @brief Set the WP5 field to a new value. */ 11063 #define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v)) 11064 /*@}*/ 11065 11066 /*! 11067 * @name Register AIPS_PACRO, field SP5[10] (RW) 11068 * 11069 * Determines whether the peripheral requires supervisor privilege level for 11070 * accesses. When this field is set, the master privilege level must indicate the 11071 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11072 * must be set. If not, access terminates with an error response and no peripheral 11073 * access initiates. 11074 * 11075 * Values: 11076 * - 0 - This peripheral does not require supervisor privilege level for 11077 * accesses. 11078 * - 1 - This peripheral requires supervisor privilege level for accesses. 11079 */ 11080 /*@{*/ 11081 #define BP_AIPS_PACRO_SP5 (10U) /*!< Bit position for AIPS_PACRO_SP5. */ 11082 #define BM_AIPS_PACRO_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRO_SP5. */ 11083 #define BS_AIPS_PACRO_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP5. */ 11084 11085 /*! @brief Read current value of the AIPS_PACRO_SP5 field. */ 11086 #define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5)) 11087 11088 /*! @brief Format value for bitfield AIPS_PACRO_SP5. */ 11089 #define BF_AIPS_PACRO_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP5) & BM_AIPS_PACRO_SP5) 11090 11091 /*! @brief Set the SP5 field to a new value. */ 11092 #define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v)) 11093 /*@}*/ 11094 11095 /*! 11096 * @name Register AIPS_PACRO, field TP4[12] (RW) 11097 * 11098 * Determines whether the peripheral allows accesses from an untrusted master. 11099 * When this bit is set and an access is attempted by an untrusted master, the 11100 * access terminates with an error response and no peripheral access initiates. 11101 * 11102 * Values: 11103 * - 0 - Accesses from an untrusted master are allowed. 11104 * - 1 - Accesses from an untrusted master are not allowed. 11105 */ 11106 /*@{*/ 11107 #define BP_AIPS_PACRO_TP4 (12U) /*!< Bit position for AIPS_PACRO_TP4. */ 11108 #define BM_AIPS_PACRO_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRO_TP4. */ 11109 #define BS_AIPS_PACRO_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP4. */ 11110 11111 /*! @brief Read current value of the AIPS_PACRO_TP4 field. */ 11112 #define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4)) 11113 11114 /*! @brief Format value for bitfield AIPS_PACRO_TP4. */ 11115 #define BF_AIPS_PACRO_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP4) & BM_AIPS_PACRO_TP4) 11116 11117 /*! @brief Set the TP4 field to a new value. */ 11118 #define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v)) 11119 /*@}*/ 11120 11121 /*! 11122 * @name Register AIPS_PACRO, field WP4[13] (RW) 11123 * 11124 * Determines whether the peripheral allows write accesses. When this field is 11125 * set and a write access is attempted, access terminates with an error response 11126 * and no peripheral access initiates. 11127 * 11128 * Values: 11129 * - 0 - This peripheral allows write accesses. 11130 * - 1 - This peripheral is write protected. 11131 */ 11132 /*@{*/ 11133 #define BP_AIPS_PACRO_WP4 (13U) /*!< Bit position for AIPS_PACRO_WP4. */ 11134 #define BM_AIPS_PACRO_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRO_WP4. */ 11135 #define BS_AIPS_PACRO_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP4. */ 11136 11137 /*! @brief Read current value of the AIPS_PACRO_WP4 field. */ 11138 #define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4)) 11139 11140 /*! @brief Format value for bitfield AIPS_PACRO_WP4. */ 11141 #define BF_AIPS_PACRO_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP4) & BM_AIPS_PACRO_WP4) 11142 11143 /*! @brief Set the WP4 field to a new value. */ 11144 #define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v)) 11145 /*@}*/ 11146 11147 /*! 11148 * @name Register AIPS_PACRO, field SP4[14] (RW) 11149 * 11150 * Determines whether the peripheral requires supervisor privilege level for 11151 * access. When this bit is set, the master privilege level must indicate the 11152 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11153 * set. If not, access terminates with an error response and no peripheral access 11154 * initiates. 11155 * 11156 * Values: 11157 * - 0 - This peripheral does not require supervisor privilege level for 11158 * accesses. 11159 * - 1 - This peripheral requires supervisor privilege level for accesses. 11160 */ 11161 /*@{*/ 11162 #define BP_AIPS_PACRO_SP4 (14U) /*!< Bit position for AIPS_PACRO_SP4. */ 11163 #define BM_AIPS_PACRO_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRO_SP4. */ 11164 #define BS_AIPS_PACRO_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP4. */ 11165 11166 /*! @brief Read current value of the AIPS_PACRO_SP4 field. */ 11167 #define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4)) 11168 11169 /*! @brief Format value for bitfield AIPS_PACRO_SP4. */ 11170 #define BF_AIPS_PACRO_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP4) & BM_AIPS_PACRO_SP4) 11171 11172 /*! @brief Set the SP4 field to a new value. */ 11173 #define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v)) 11174 /*@}*/ 11175 11176 /*! 11177 * @name Register AIPS_PACRO, field TP3[16] (RW) 11178 * 11179 * Determines whether the peripheral allows accesses from an untrusted master. 11180 * When this field is set and an access is attempted by an untrusted master, the 11181 * access terminates with an error response and no peripheral access initiates. 11182 * 11183 * Values: 11184 * - 0 - Accesses from an untrusted master are allowed. 11185 * - 1 - Accesses from an untrusted master are not allowed. 11186 */ 11187 /*@{*/ 11188 #define BP_AIPS_PACRO_TP3 (16U) /*!< Bit position for AIPS_PACRO_TP3. */ 11189 #define BM_AIPS_PACRO_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRO_TP3. */ 11190 #define BS_AIPS_PACRO_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP3. */ 11191 11192 /*! @brief Read current value of the AIPS_PACRO_TP3 field. */ 11193 #define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3)) 11194 11195 /*! @brief Format value for bitfield AIPS_PACRO_TP3. */ 11196 #define BF_AIPS_PACRO_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP3) & BM_AIPS_PACRO_TP3) 11197 11198 /*! @brief Set the TP3 field to a new value. */ 11199 #define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v)) 11200 /*@}*/ 11201 11202 /*! 11203 * @name Register AIPS_PACRO, field WP3[17] (RW) 11204 * 11205 * Determines whether the peripheral allows write accesss. When this bit is set 11206 * and a write access is attempted, access terminates with an error response and 11207 * no peripheral access initiates. 11208 * 11209 * Values: 11210 * - 0 - This peripheral allows write accesses. 11211 * - 1 - This peripheral is write protected. 11212 */ 11213 /*@{*/ 11214 #define BP_AIPS_PACRO_WP3 (17U) /*!< Bit position for AIPS_PACRO_WP3. */ 11215 #define BM_AIPS_PACRO_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRO_WP3. */ 11216 #define BS_AIPS_PACRO_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP3. */ 11217 11218 /*! @brief Read current value of the AIPS_PACRO_WP3 field. */ 11219 #define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3)) 11220 11221 /*! @brief Format value for bitfield AIPS_PACRO_WP3. */ 11222 #define BF_AIPS_PACRO_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP3) & BM_AIPS_PACRO_WP3) 11223 11224 /*! @brief Set the WP3 field to a new value. */ 11225 #define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v)) 11226 /*@}*/ 11227 11228 /*! 11229 * @name Register AIPS_PACRO, field SP3[18] (RW) 11230 * 11231 * Determines whether the peripheral requires supervisor privilege level for 11232 * accesses. When this field is set, the master privilege level must indicate the 11233 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11234 * must be set. If not, access terminates with an error response and no peripheral 11235 * access initiates. 11236 * 11237 * Values: 11238 * - 0 - This peripheral does not require supervisor privilege level for 11239 * accesses. 11240 * - 1 - This peripheral requires supervisor privilege level for accesses. 11241 */ 11242 /*@{*/ 11243 #define BP_AIPS_PACRO_SP3 (18U) /*!< Bit position for AIPS_PACRO_SP3. */ 11244 #define BM_AIPS_PACRO_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRO_SP3. */ 11245 #define BS_AIPS_PACRO_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP3. */ 11246 11247 /*! @brief Read current value of the AIPS_PACRO_SP3 field. */ 11248 #define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3)) 11249 11250 /*! @brief Format value for bitfield AIPS_PACRO_SP3. */ 11251 #define BF_AIPS_PACRO_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP3) & BM_AIPS_PACRO_SP3) 11252 11253 /*! @brief Set the SP3 field to a new value. */ 11254 #define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v)) 11255 /*@}*/ 11256 11257 /*! 11258 * @name Register AIPS_PACRO, field TP2[20] (RW) 11259 * 11260 * Determines whether the peripheral allows accesses from an untrusted master. 11261 * When this bit is set and an access is attempted by an untrusted master, the 11262 * access terminates with an error response and no peripheral access initiates. 11263 * 11264 * Values: 11265 * - 0 - Accesses from an untrusted master are allowed. 11266 * - 1 - Accesses from an untrusted master are not allowed. 11267 */ 11268 /*@{*/ 11269 #define BP_AIPS_PACRO_TP2 (20U) /*!< Bit position for AIPS_PACRO_TP2. */ 11270 #define BM_AIPS_PACRO_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRO_TP2. */ 11271 #define BS_AIPS_PACRO_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP2. */ 11272 11273 /*! @brief Read current value of the AIPS_PACRO_TP2 field. */ 11274 #define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2)) 11275 11276 /*! @brief Format value for bitfield AIPS_PACRO_TP2. */ 11277 #define BF_AIPS_PACRO_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP2) & BM_AIPS_PACRO_TP2) 11278 11279 /*! @brief Set the TP2 field to a new value. */ 11280 #define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v)) 11281 /*@}*/ 11282 11283 /*! 11284 * @name Register AIPS_PACRO, field WP2[21] (RW) 11285 * 11286 * Determines whether the peripheral allows write accesses. When this field is 11287 * set and a write access is attempted, access terminates with an error response 11288 * and no peripheral access initiates. 11289 * 11290 * Values: 11291 * - 0 - This peripheral allows write accesses. 11292 * - 1 - This peripheral is write protected. 11293 */ 11294 /*@{*/ 11295 #define BP_AIPS_PACRO_WP2 (21U) /*!< Bit position for AIPS_PACRO_WP2. */ 11296 #define BM_AIPS_PACRO_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRO_WP2. */ 11297 #define BS_AIPS_PACRO_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP2. */ 11298 11299 /*! @brief Read current value of the AIPS_PACRO_WP2 field. */ 11300 #define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2)) 11301 11302 /*! @brief Format value for bitfield AIPS_PACRO_WP2. */ 11303 #define BF_AIPS_PACRO_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP2) & BM_AIPS_PACRO_WP2) 11304 11305 /*! @brief Set the WP2 field to a new value. */ 11306 #define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v)) 11307 /*@}*/ 11308 11309 /*! 11310 * @name Register AIPS_PACRO, field SP2[22] (RW) 11311 * 11312 * Determines whether the peripheral requires supervisor privilege level for 11313 * access. When this bit is set, the master privilege level must indicate the 11314 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11315 * set. If not, access terminates with an error response and no peripheral access 11316 * initiates. 11317 * 11318 * Values: 11319 * - 0 - This peripheral does not require supervisor privilege level for 11320 * accesses. 11321 * - 1 - This peripheral requires supervisor privilege level for accesses. 11322 */ 11323 /*@{*/ 11324 #define BP_AIPS_PACRO_SP2 (22U) /*!< Bit position for AIPS_PACRO_SP2. */ 11325 #define BM_AIPS_PACRO_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRO_SP2. */ 11326 #define BS_AIPS_PACRO_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP2. */ 11327 11328 /*! @brief Read current value of the AIPS_PACRO_SP2 field. */ 11329 #define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2)) 11330 11331 /*! @brief Format value for bitfield AIPS_PACRO_SP2. */ 11332 #define BF_AIPS_PACRO_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP2) & BM_AIPS_PACRO_SP2) 11333 11334 /*! @brief Set the SP2 field to a new value. */ 11335 #define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v)) 11336 /*@}*/ 11337 11338 /*! 11339 * @name Register AIPS_PACRO, field TP1[24] (RW) 11340 * 11341 * Determines whether the peripheral allows accesses from an untrusted master. 11342 * When this field is set and an access is attempted by an untrusted master, the 11343 * access terminates with an error response and no peripheral access initiates. 11344 * 11345 * Values: 11346 * - 0 - Accesses from an untrusted master are allowed. 11347 * - 1 - Accesses from an untrusted master are not allowed. 11348 */ 11349 /*@{*/ 11350 #define BP_AIPS_PACRO_TP1 (24U) /*!< Bit position for AIPS_PACRO_TP1. */ 11351 #define BM_AIPS_PACRO_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRO_TP1. */ 11352 #define BS_AIPS_PACRO_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP1. */ 11353 11354 /*! @brief Read current value of the AIPS_PACRO_TP1 field. */ 11355 #define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1)) 11356 11357 /*! @brief Format value for bitfield AIPS_PACRO_TP1. */ 11358 #define BF_AIPS_PACRO_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP1) & BM_AIPS_PACRO_TP1) 11359 11360 /*! @brief Set the TP1 field to a new value. */ 11361 #define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v)) 11362 /*@}*/ 11363 11364 /*! 11365 * @name Register AIPS_PACRO, field WP1[25] (RW) 11366 * 11367 * Determines whether the peripheral allows write accesses. When this field is 11368 * set and a write access is attempted, access terminates with an error response 11369 * and no peripheral access initiates. 11370 * 11371 * Values: 11372 * - 0 - This peripheral allows write accesses. 11373 * - 1 - This peripheral is write protected. 11374 */ 11375 /*@{*/ 11376 #define BP_AIPS_PACRO_WP1 (25U) /*!< Bit position for AIPS_PACRO_WP1. */ 11377 #define BM_AIPS_PACRO_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRO_WP1. */ 11378 #define BS_AIPS_PACRO_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP1. */ 11379 11380 /*! @brief Read current value of the AIPS_PACRO_WP1 field. */ 11381 #define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1)) 11382 11383 /*! @brief Format value for bitfield AIPS_PACRO_WP1. */ 11384 #define BF_AIPS_PACRO_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP1) & BM_AIPS_PACRO_WP1) 11385 11386 /*! @brief Set the WP1 field to a new value. */ 11387 #define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v)) 11388 /*@}*/ 11389 11390 /*! 11391 * @name Register AIPS_PACRO, field SP1[26] (RW) 11392 * 11393 * Determines whether the peripheral requires supervisor privilege level for 11394 * access. When this field is set, the master privilege level must indicate the 11395 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 11396 * be set. If not, access terminates with an error response and no peripheral 11397 * access initiates. 11398 * 11399 * Values: 11400 * - 0 - This peripheral does not require supervisor privilege level for 11401 * accesses. 11402 * - 1 - This peripheral requires supervisor privilege level for accesses. 11403 */ 11404 /*@{*/ 11405 #define BP_AIPS_PACRO_SP1 (26U) /*!< Bit position for AIPS_PACRO_SP1. */ 11406 #define BM_AIPS_PACRO_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRO_SP1. */ 11407 #define BS_AIPS_PACRO_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP1. */ 11408 11409 /*! @brief Read current value of the AIPS_PACRO_SP1 field. */ 11410 #define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1)) 11411 11412 /*! @brief Format value for bitfield AIPS_PACRO_SP1. */ 11413 #define BF_AIPS_PACRO_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP1) & BM_AIPS_PACRO_SP1) 11414 11415 /*! @brief Set the SP1 field to a new value. */ 11416 #define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v)) 11417 /*@}*/ 11418 11419 /*! 11420 * @name Register AIPS_PACRO, field TP0[28] (RW) 11421 * 11422 * Determines whether the peripheral allows accesses from an untrusted master. 11423 * When this bit is set and an access is attempted by an untrusted master, the 11424 * access terminates with an error response and no peripheral access initiates. 11425 * 11426 * Values: 11427 * - 0 - Accesses from an untrusted master are allowed. 11428 * - 1 - Accesses from an untrusted master are not allowed. 11429 */ 11430 /*@{*/ 11431 #define BP_AIPS_PACRO_TP0 (28U) /*!< Bit position for AIPS_PACRO_TP0. */ 11432 #define BM_AIPS_PACRO_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRO_TP0. */ 11433 #define BS_AIPS_PACRO_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP0. */ 11434 11435 /*! @brief Read current value of the AIPS_PACRO_TP0 field. */ 11436 #define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0)) 11437 11438 /*! @brief Format value for bitfield AIPS_PACRO_TP0. */ 11439 #define BF_AIPS_PACRO_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP0) & BM_AIPS_PACRO_TP0) 11440 11441 /*! @brief Set the TP0 field to a new value. */ 11442 #define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v)) 11443 /*@}*/ 11444 11445 /*! 11446 * @name Register AIPS_PACRO, field WP0[29] (RW) 11447 * 11448 * Determines whether the peripheral allows write accesses. When this field is 11449 * set and a write access is attempted, access terminates with an error response 11450 * and no peripheral access initiates. 11451 * 11452 * Values: 11453 * - 0 - This peripheral allows write accesses. 11454 * - 1 - This peripheral is write protected. 11455 */ 11456 /*@{*/ 11457 #define BP_AIPS_PACRO_WP0 (29U) /*!< Bit position for AIPS_PACRO_WP0. */ 11458 #define BM_AIPS_PACRO_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRO_WP0. */ 11459 #define BS_AIPS_PACRO_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP0. */ 11460 11461 /*! @brief Read current value of the AIPS_PACRO_WP0 field. */ 11462 #define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0)) 11463 11464 /*! @brief Format value for bitfield AIPS_PACRO_WP0. */ 11465 #define BF_AIPS_PACRO_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP0) & BM_AIPS_PACRO_WP0) 11466 11467 /*! @brief Set the WP0 field to a new value. */ 11468 #define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v)) 11469 /*@}*/ 11470 11471 /*! 11472 * @name Register AIPS_PACRO, field SP0[30] (RW) 11473 * 11474 * Determines whether the peripheral requires supervisor privilege level for 11475 * accesses. When this field is set, the master privilege level must indicate the 11476 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11477 * must be set. If not, access terminates with an error response and no peripheral 11478 * access initiates. 11479 * 11480 * Values: 11481 * - 0 - This peripheral does not require supervisor privilege level for 11482 * accesses. 11483 * - 1 - This peripheral requires supervisor privilege level for accesses. 11484 */ 11485 /*@{*/ 11486 #define BP_AIPS_PACRO_SP0 (30U) /*!< Bit position for AIPS_PACRO_SP0. */ 11487 #define BM_AIPS_PACRO_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRO_SP0. */ 11488 #define BS_AIPS_PACRO_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP0. */ 11489 11490 /*! @brief Read current value of the AIPS_PACRO_SP0 field. */ 11491 #define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0)) 11492 11493 /*! @brief Format value for bitfield AIPS_PACRO_SP0. */ 11494 #define BF_AIPS_PACRO_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP0) & BM_AIPS_PACRO_SP0) 11495 11496 /*! @brief Set the SP0 field to a new value. */ 11497 #define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v)) 11498 /*@}*/ 11499 11500 /******************************************************************************* 11501 * HW_AIPS_PACRP - Peripheral Access Control Register 11502 ******************************************************************************/ 11503 11504 /*! 11505 * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) 11506 * 11507 * Reset value: 0x44444444U 11508 * 11509 * This section describes PACR registers E-P, which control peripheral slots 11510 * 32-127. See PACRPeripheral Access Control Register for the description of these 11511 * registers. 11512 */ 11513 typedef union _hw_aips_pacrp 11514 { 11515 uint32_t U; 11516 struct _hw_aips_pacrp_bitfields 11517 { 11518 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 11519 uint32_t WP7 : 1; /*!< [1] Write Protect */ 11520 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 11521 uint32_t RESERVED0 : 1; /*!< [3] */ 11522 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 11523 uint32_t WP6 : 1; /*!< [5] Write Protect */ 11524 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 11525 uint32_t RESERVED1 : 1; /*!< [7] */ 11526 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 11527 uint32_t WP5 : 1; /*!< [9] Write Protect */ 11528 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 11529 uint32_t RESERVED2 : 1; /*!< [11] */ 11530 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 11531 uint32_t WP4 : 1; /*!< [13] Write Protect */ 11532 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 11533 uint32_t RESERVED3 : 1; /*!< [15] */ 11534 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 11535 uint32_t WP3 : 1; /*!< [17] Write Protect */ 11536 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 11537 uint32_t RESERVED4 : 1; /*!< [19] */ 11538 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 11539 uint32_t WP2 : 1; /*!< [21] Write Protect */ 11540 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 11541 uint32_t RESERVED5 : 1; /*!< [23] */ 11542 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 11543 uint32_t WP1 : 1; /*!< [25] Write Protect */ 11544 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 11545 uint32_t RESERVED6 : 1; /*!< [27] */ 11546 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 11547 uint32_t WP0 : 1; /*!< [29] Write Protect */ 11548 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 11549 uint32_t RESERVED7 : 1; /*!< [31] */ 11550 } B; 11551 } hw_aips_pacrp_t; 11552 11553 /*! 11554 * @name Constants and macros for entire AIPS_PACRP register 11555 */ 11556 /*@{*/ 11557 #define HW_AIPS_PACRP_ADDR(x) ((x) + 0x6CU) 11558 11559 #define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) 11560 #define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U) 11561 #define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v)) 11562 #define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) 11563 #define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) 11564 #define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) 11565 /*@}*/ 11566 11567 /* 11568 * Constants & macros for individual AIPS_PACRP bitfields 11569 */ 11570 11571 /*! 11572 * @name Register AIPS_PACRP, field TP7[0] (RW) 11573 * 11574 * Determines whether the peripheral allows accesses from an untrusted master. 11575 * When this field is set and an access is attempted by an untrusted master, the 11576 * access terminates with an error response and no peripheral access initiates. 11577 * 11578 * Values: 11579 * - 0 - Accesses from an untrusted master are allowed. 11580 * - 1 - Accesses from an untrusted master are not allowed. 11581 */ 11582 /*@{*/ 11583 #define BP_AIPS_PACRP_TP7 (0U) /*!< Bit position for AIPS_PACRP_TP7. */ 11584 #define BM_AIPS_PACRP_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRP_TP7. */ 11585 #define BS_AIPS_PACRP_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP7. */ 11586 11587 /*! @brief Read current value of the AIPS_PACRP_TP7 field. */ 11588 #define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7)) 11589 11590 /*! @brief Format value for bitfield AIPS_PACRP_TP7. */ 11591 #define BF_AIPS_PACRP_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP7) & BM_AIPS_PACRP_TP7) 11592 11593 /*! @brief Set the TP7 field to a new value. */ 11594 #define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v)) 11595 /*@}*/ 11596 11597 /*! 11598 * @name Register AIPS_PACRP, field WP7[1] (RW) 11599 * 11600 * Determines whether the peripheral allows write accesses. When this field is 11601 * set and a write access is attempted, access terminates with an error response 11602 * and no peripheral access initiates. 11603 * 11604 * Values: 11605 * - 0 - This peripheral allows write accesses. 11606 * - 1 - This peripheral is write protected. 11607 */ 11608 /*@{*/ 11609 #define BP_AIPS_PACRP_WP7 (1U) /*!< Bit position for AIPS_PACRP_WP7. */ 11610 #define BM_AIPS_PACRP_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRP_WP7. */ 11611 #define BS_AIPS_PACRP_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP7. */ 11612 11613 /*! @brief Read current value of the AIPS_PACRP_WP7 field. */ 11614 #define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7)) 11615 11616 /*! @brief Format value for bitfield AIPS_PACRP_WP7. */ 11617 #define BF_AIPS_PACRP_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP7) & BM_AIPS_PACRP_WP7) 11618 11619 /*! @brief Set the WP7 field to a new value. */ 11620 #define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v)) 11621 /*@}*/ 11622 11623 /*! 11624 * @name Register AIPS_PACRP, field SP7[2] (RW) 11625 * 11626 * Determines whether the peripheral requires supervisor privilege level for 11627 * accesses. When this field is set, the master privilege level must indicate the 11628 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11629 * must be set. If not, access terminates with an error response and no peripheral 11630 * access initiates. 11631 * 11632 * Values: 11633 * - 0 - This peripheral does not require supervisor privilege level for 11634 * accesses. 11635 * - 1 - This peripheral requires supervisor privilege level for accesses. 11636 */ 11637 /*@{*/ 11638 #define BP_AIPS_PACRP_SP7 (2U) /*!< Bit position for AIPS_PACRP_SP7. */ 11639 #define BM_AIPS_PACRP_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRP_SP7. */ 11640 #define BS_AIPS_PACRP_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP7. */ 11641 11642 /*! @brief Read current value of the AIPS_PACRP_SP7 field. */ 11643 #define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7)) 11644 11645 /*! @brief Format value for bitfield AIPS_PACRP_SP7. */ 11646 #define BF_AIPS_PACRP_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP7) & BM_AIPS_PACRP_SP7) 11647 11648 /*! @brief Set the SP7 field to a new value. */ 11649 #define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v)) 11650 /*@}*/ 11651 11652 /*! 11653 * @name Register AIPS_PACRP, field TP6[4] (RW) 11654 * 11655 * Determines whether the peripheral allows accesses from an untrusted master. 11656 * When this field is set and an access is attempted by an untrusted master, the 11657 * access terminates with an error response and no peripheral access initiates. 11658 * 11659 * Values: 11660 * - 0 - Accesses from an untrusted master are allowed. 11661 * - 1 - Accesses from an untrusted master are not allowed. 11662 */ 11663 /*@{*/ 11664 #define BP_AIPS_PACRP_TP6 (4U) /*!< Bit position for AIPS_PACRP_TP6. */ 11665 #define BM_AIPS_PACRP_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRP_TP6. */ 11666 #define BS_AIPS_PACRP_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP6. */ 11667 11668 /*! @brief Read current value of the AIPS_PACRP_TP6 field. */ 11669 #define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6)) 11670 11671 /*! @brief Format value for bitfield AIPS_PACRP_TP6. */ 11672 #define BF_AIPS_PACRP_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP6) & BM_AIPS_PACRP_TP6) 11673 11674 /*! @brief Set the TP6 field to a new value. */ 11675 #define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v)) 11676 /*@}*/ 11677 11678 /*! 11679 * @name Register AIPS_PACRP, field WP6[5] (RW) 11680 * 11681 * Determines whether the peripheral allows write accesses. When this field is 11682 * set and a write access is attempted, access terminates with an error response 11683 * and no peripheral access initiates. 11684 * 11685 * Values: 11686 * - 0 - This peripheral allows write accesses. 11687 * - 1 - This peripheral is write protected. 11688 */ 11689 /*@{*/ 11690 #define BP_AIPS_PACRP_WP6 (5U) /*!< Bit position for AIPS_PACRP_WP6. */ 11691 #define BM_AIPS_PACRP_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRP_WP6. */ 11692 #define BS_AIPS_PACRP_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP6. */ 11693 11694 /*! @brief Read current value of the AIPS_PACRP_WP6 field. */ 11695 #define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6)) 11696 11697 /*! @brief Format value for bitfield AIPS_PACRP_WP6. */ 11698 #define BF_AIPS_PACRP_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP6) & BM_AIPS_PACRP_WP6) 11699 11700 /*! @brief Set the WP6 field to a new value. */ 11701 #define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v)) 11702 /*@}*/ 11703 11704 /*! 11705 * @name Register AIPS_PACRP, field SP6[6] (RW) 11706 * 11707 * Determines whether the peripheral requires supervisor privilege level for 11708 * accesses. When this field is set, the master privilege level must indicate the 11709 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11710 * must be set. If not, access terminates with an error response and no peripheral 11711 * access initiates. 11712 * 11713 * Values: 11714 * - 0 - This peripheral does not require supervisor privilege level for 11715 * accesses. 11716 * - 1 - This peripheral requires supervisor privilege level for accesses. 11717 */ 11718 /*@{*/ 11719 #define BP_AIPS_PACRP_SP6 (6U) /*!< Bit position for AIPS_PACRP_SP6. */ 11720 #define BM_AIPS_PACRP_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRP_SP6. */ 11721 #define BS_AIPS_PACRP_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP6. */ 11722 11723 /*! @brief Read current value of the AIPS_PACRP_SP6 field. */ 11724 #define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6)) 11725 11726 /*! @brief Format value for bitfield AIPS_PACRP_SP6. */ 11727 #define BF_AIPS_PACRP_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP6) & BM_AIPS_PACRP_SP6) 11728 11729 /*! @brief Set the SP6 field to a new value. */ 11730 #define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v)) 11731 /*@}*/ 11732 11733 /*! 11734 * @name Register AIPS_PACRP, field TP5[8] (RW) 11735 * 11736 * Determines whether the peripheral allows accesses from an untrusted master. 11737 * When this field is set and an access is attempted by an untrusted master, the 11738 * access terminates with an error response and no peripheral access initiates. 11739 * 11740 * Values: 11741 * - 0 - Accesses from an untrusted master are allowed. 11742 * - 1 - Accesses from an untrusted master are not allowed. 11743 */ 11744 /*@{*/ 11745 #define BP_AIPS_PACRP_TP5 (8U) /*!< Bit position for AIPS_PACRP_TP5. */ 11746 #define BM_AIPS_PACRP_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRP_TP5. */ 11747 #define BS_AIPS_PACRP_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP5. */ 11748 11749 /*! @brief Read current value of the AIPS_PACRP_TP5 field. */ 11750 #define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5)) 11751 11752 /*! @brief Format value for bitfield AIPS_PACRP_TP5. */ 11753 #define BF_AIPS_PACRP_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP5) & BM_AIPS_PACRP_TP5) 11754 11755 /*! @brief Set the TP5 field to a new value. */ 11756 #define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v)) 11757 /*@}*/ 11758 11759 /*! 11760 * @name Register AIPS_PACRP, field WP5[9] (RW) 11761 * 11762 * Determines whether the peripheral allows write accesses. When this field is 11763 * set and a write access is attempted, access terminates with an error response 11764 * and no peripheral access initiates. 11765 * 11766 * Values: 11767 * - 0 - This peripheral allows write accesses. 11768 * - 1 - This peripheral is write protected. 11769 */ 11770 /*@{*/ 11771 #define BP_AIPS_PACRP_WP5 (9U) /*!< Bit position for AIPS_PACRP_WP5. */ 11772 #define BM_AIPS_PACRP_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRP_WP5. */ 11773 #define BS_AIPS_PACRP_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP5. */ 11774 11775 /*! @brief Read current value of the AIPS_PACRP_WP5 field. */ 11776 #define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5)) 11777 11778 /*! @brief Format value for bitfield AIPS_PACRP_WP5. */ 11779 #define BF_AIPS_PACRP_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP5) & BM_AIPS_PACRP_WP5) 11780 11781 /*! @brief Set the WP5 field to a new value. */ 11782 #define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v)) 11783 /*@}*/ 11784 11785 /*! 11786 * @name Register AIPS_PACRP, field SP5[10] (RW) 11787 * 11788 * Determines whether the peripheral requires supervisor privilege level for 11789 * accesses. When this field is set, the master privilege level must indicate the 11790 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11791 * must be set. If not, access terminates with an error response and no peripheral 11792 * access initiates. 11793 * 11794 * Values: 11795 * - 0 - This peripheral does not require supervisor privilege level for 11796 * accesses. 11797 * - 1 - This peripheral requires supervisor privilege level for accesses. 11798 */ 11799 /*@{*/ 11800 #define BP_AIPS_PACRP_SP5 (10U) /*!< Bit position for AIPS_PACRP_SP5. */ 11801 #define BM_AIPS_PACRP_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRP_SP5. */ 11802 #define BS_AIPS_PACRP_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP5. */ 11803 11804 /*! @brief Read current value of the AIPS_PACRP_SP5 field. */ 11805 #define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5)) 11806 11807 /*! @brief Format value for bitfield AIPS_PACRP_SP5. */ 11808 #define BF_AIPS_PACRP_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP5) & BM_AIPS_PACRP_SP5) 11809 11810 /*! @brief Set the SP5 field to a new value. */ 11811 #define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v)) 11812 /*@}*/ 11813 11814 /*! 11815 * @name Register AIPS_PACRP, field TP4[12] (RW) 11816 * 11817 * Determines whether the peripheral allows accesses from an untrusted master. 11818 * When this bit is set and an access is attempted by an untrusted master, the 11819 * access terminates with an error response and no peripheral access initiates. 11820 * 11821 * Values: 11822 * - 0 - Accesses from an untrusted master are allowed. 11823 * - 1 - Accesses from an untrusted master are not allowed. 11824 */ 11825 /*@{*/ 11826 #define BP_AIPS_PACRP_TP4 (12U) /*!< Bit position for AIPS_PACRP_TP4. */ 11827 #define BM_AIPS_PACRP_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRP_TP4. */ 11828 #define BS_AIPS_PACRP_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP4. */ 11829 11830 /*! @brief Read current value of the AIPS_PACRP_TP4 field. */ 11831 #define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4)) 11832 11833 /*! @brief Format value for bitfield AIPS_PACRP_TP4. */ 11834 #define BF_AIPS_PACRP_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP4) & BM_AIPS_PACRP_TP4) 11835 11836 /*! @brief Set the TP4 field to a new value. */ 11837 #define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v)) 11838 /*@}*/ 11839 11840 /*! 11841 * @name Register AIPS_PACRP, field WP4[13] (RW) 11842 * 11843 * Determines whether the peripheral allows write accesses. When this field is 11844 * set and a write access is attempted, access terminates with an error response 11845 * and no peripheral access initiates. 11846 * 11847 * Values: 11848 * - 0 - This peripheral allows write accesses. 11849 * - 1 - This peripheral is write protected. 11850 */ 11851 /*@{*/ 11852 #define BP_AIPS_PACRP_WP4 (13U) /*!< Bit position for AIPS_PACRP_WP4. */ 11853 #define BM_AIPS_PACRP_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRP_WP4. */ 11854 #define BS_AIPS_PACRP_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP4. */ 11855 11856 /*! @brief Read current value of the AIPS_PACRP_WP4 field. */ 11857 #define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4)) 11858 11859 /*! @brief Format value for bitfield AIPS_PACRP_WP4. */ 11860 #define BF_AIPS_PACRP_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP4) & BM_AIPS_PACRP_WP4) 11861 11862 /*! @brief Set the WP4 field to a new value. */ 11863 #define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v)) 11864 /*@}*/ 11865 11866 /*! 11867 * @name Register AIPS_PACRP, field SP4[14] (RW) 11868 * 11869 * Determines whether the peripheral requires supervisor privilege level for 11870 * access. When this bit is set, the master privilege level must indicate the 11871 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11872 * set. If not, access terminates with an error response and no peripheral access 11873 * initiates. 11874 * 11875 * Values: 11876 * - 0 - This peripheral does not require supervisor privilege level for 11877 * accesses. 11878 * - 1 - This peripheral requires supervisor privilege level for accesses. 11879 */ 11880 /*@{*/ 11881 #define BP_AIPS_PACRP_SP4 (14U) /*!< Bit position for AIPS_PACRP_SP4. */ 11882 #define BM_AIPS_PACRP_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRP_SP4. */ 11883 #define BS_AIPS_PACRP_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP4. */ 11884 11885 /*! @brief Read current value of the AIPS_PACRP_SP4 field. */ 11886 #define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4)) 11887 11888 /*! @brief Format value for bitfield AIPS_PACRP_SP4. */ 11889 #define BF_AIPS_PACRP_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP4) & BM_AIPS_PACRP_SP4) 11890 11891 /*! @brief Set the SP4 field to a new value. */ 11892 #define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v)) 11893 /*@}*/ 11894 11895 /*! 11896 * @name Register AIPS_PACRP, field TP3[16] (RW) 11897 * 11898 * Determines whether the peripheral allows accesses from an untrusted master. 11899 * When this field is set and an access is attempted by an untrusted master, the 11900 * access terminates with an error response and no peripheral access initiates. 11901 * 11902 * Values: 11903 * - 0 - Accesses from an untrusted master are allowed. 11904 * - 1 - Accesses from an untrusted master are not allowed. 11905 */ 11906 /*@{*/ 11907 #define BP_AIPS_PACRP_TP3 (16U) /*!< Bit position for AIPS_PACRP_TP3. */ 11908 #define BM_AIPS_PACRP_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRP_TP3. */ 11909 #define BS_AIPS_PACRP_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP3. */ 11910 11911 /*! @brief Read current value of the AIPS_PACRP_TP3 field. */ 11912 #define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3)) 11913 11914 /*! @brief Format value for bitfield AIPS_PACRP_TP3. */ 11915 #define BF_AIPS_PACRP_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP3) & BM_AIPS_PACRP_TP3) 11916 11917 /*! @brief Set the TP3 field to a new value. */ 11918 #define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v)) 11919 /*@}*/ 11920 11921 /*! 11922 * @name Register AIPS_PACRP, field WP3[17] (RW) 11923 * 11924 * Determines whether the peripheral allows write accesss. When this bit is set 11925 * and a write access is attempted, access terminates with an error response and 11926 * no peripheral access initiates. 11927 * 11928 * Values: 11929 * - 0 - This peripheral allows write accesses. 11930 * - 1 - This peripheral is write protected. 11931 */ 11932 /*@{*/ 11933 #define BP_AIPS_PACRP_WP3 (17U) /*!< Bit position for AIPS_PACRP_WP3. */ 11934 #define BM_AIPS_PACRP_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRP_WP3. */ 11935 #define BS_AIPS_PACRP_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP3. */ 11936 11937 /*! @brief Read current value of the AIPS_PACRP_WP3 field. */ 11938 #define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3)) 11939 11940 /*! @brief Format value for bitfield AIPS_PACRP_WP3. */ 11941 #define BF_AIPS_PACRP_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP3) & BM_AIPS_PACRP_WP3) 11942 11943 /*! @brief Set the WP3 field to a new value. */ 11944 #define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v)) 11945 /*@}*/ 11946 11947 /*! 11948 * @name Register AIPS_PACRP, field SP3[18] (RW) 11949 * 11950 * Determines whether the peripheral requires supervisor privilege level for 11951 * accesses. When this field is set, the master privilege level must indicate the 11952 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11953 * must be set. If not, access terminates with an error response and no peripheral 11954 * access initiates. 11955 * 11956 * Values: 11957 * - 0 - This peripheral does not require supervisor privilege level for 11958 * accesses. 11959 * - 1 - This peripheral requires supervisor privilege level for accesses. 11960 */ 11961 /*@{*/ 11962 #define BP_AIPS_PACRP_SP3 (18U) /*!< Bit position for AIPS_PACRP_SP3. */ 11963 #define BM_AIPS_PACRP_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRP_SP3. */ 11964 #define BS_AIPS_PACRP_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP3. */ 11965 11966 /*! @brief Read current value of the AIPS_PACRP_SP3 field. */ 11967 #define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3)) 11968 11969 /*! @brief Format value for bitfield AIPS_PACRP_SP3. */ 11970 #define BF_AIPS_PACRP_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP3) & BM_AIPS_PACRP_SP3) 11971 11972 /*! @brief Set the SP3 field to a new value. */ 11973 #define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v)) 11974 /*@}*/ 11975 11976 /*! 11977 * @name Register AIPS_PACRP, field TP2[20] (RW) 11978 * 11979 * Determines whether the peripheral allows accesses from an untrusted master. 11980 * When this bit is set and an access is attempted by an untrusted master, the 11981 * access terminates with an error response and no peripheral access initiates. 11982 * 11983 * Values: 11984 * - 0 - Accesses from an untrusted master are allowed. 11985 * - 1 - Accesses from an untrusted master are not allowed. 11986 */ 11987 /*@{*/ 11988 #define BP_AIPS_PACRP_TP2 (20U) /*!< Bit position for AIPS_PACRP_TP2. */ 11989 #define BM_AIPS_PACRP_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRP_TP2. */ 11990 #define BS_AIPS_PACRP_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP2. */ 11991 11992 /*! @brief Read current value of the AIPS_PACRP_TP2 field. */ 11993 #define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2)) 11994 11995 /*! @brief Format value for bitfield AIPS_PACRP_TP2. */ 11996 #define BF_AIPS_PACRP_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP2) & BM_AIPS_PACRP_TP2) 11997 11998 /*! @brief Set the TP2 field to a new value. */ 11999 #define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v)) 12000 /*@}*/ 12001 12002 /*! 12003 * @name Register AIPS_PACRP, field WP2[21] (RW) 12004 * 12005 * Determines whether the peripheral allows write accesses. When this field is 12006 * set and a write access is attempted, access terminates with an error response 12007 * and no peripheral access initiates. 12008 * 12009 * Values: 12010 * - 0 - This peripheral allows write accesses. 12011 * - 1 - This peripheral is write protected. 12012 */ 12013 /*@{*/ 12014 #define BP_AIPS_PACRP_WP2 (21U) /*!< Bit position for AIPS_PACRP_WP2. */ 12015 #define BM_AIPS_PACRP_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRP_WP2. */ 12016 #define BS_AIPS_PACRP_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP2. */ 12017 12018 /*! @brief Read current value of the AIPS_PACRP_WP2 field. */ 12019 #define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2)) 12020 12021 /*! @brief Format value for bitfield AIPS_PACRP_WP2. */ 12022 #define BF_AIPS_PACRP_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP2) & BM_AIPS_PACRP_WP2) 12023 12024 /*! @brief Set the WP2 field to a new value. */ 12025 #define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v)) 12026 /*@}*/ 12027 12028 /*! 12029 * @name Register AIPS_PACRP, field SP2[22] (RW) 12030 * 12031 * Determines whether the peripheral requires supervisor privilege level for 12032 * access. When this bit is set, the master privilege level must indicate the 12033 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 12034 * set. If not, access terminates with an error response and no peripheral access 12035 * initiates. 12036 * 12037 * Values: 12038 * - 0 - This peripheral does not require supervisor privilege level for 12039 * accesses. 12040 * - 1 - This peripheral requires supervisor privilege level for accesses. 12041 */ 12042 /*@{*/ 12043 #define BP_AIPS_PACRP_SP2 (22U) /*!< Bit position for AIPS_PACRP_SP2. */ 12044 #define BM_AIPS_PACRP_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRP_SP2. */ 12045 #define BS_AIPS_PACRP_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP2. */ 12046 12047 /*! @brief Read current value of the AIPS_PACRP_SP2 field. */ 12048 #define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2)) 12049 12050 /*! @brief Format value for bitfield AIPS_PACRP_SP2. */ 12051 #define BF_AIPS_PACRP_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP2) & BM_AIPS_PACRP_SP2) 12052 12053 /*! @brief Set the SP2 field to a new value. */ 12054 #define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v)) 12055 /*@}*/ 12056 12057 /*! 12058 * @name Register AIPS_PACRP, field TP1[24] (RW) 12059 * 12060 * Determines whether the peripheral allows accesses from an untrusted master. 12061 * When this field is set and an access is attempted by an untrusted master, the 12062 * access terminates with an error response and no peripheral access initiates. 12063 * 12064 * Values: 12065 * - 0 - Accesses from an untrusted master are allowed. 12066 * - 1 - Accesses from an untrusted master are not allowed. 12067 */ 12068 /*@{*/ 12069 #define BP_AIPS_PACRP_TP1 (24U) /*!< Bit position for AIPS_PACRP_TP1. */ 12070 #define BM_AIPS_PACRP_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRP_TP1. */ 12071 #define BS_AIPS_PACRP_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP1. */ 12072 12073 /*! @brief Read current value of the AIPS_PACRP_TP1 field. */ 12074 #define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1)) 12075 12076 /*! @brief Format value for bitfield AIPS_PACRP_TP1. */ 12077 #define BF_AIPS_PACRP_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP1) & BM_AIPS_PACRP_TP1) 12078 12079 /*! @brief Set the TP1 field to a new value. */ 12080 #define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v)) 12081 /*@}*/ 12082 12083 /*! 12084 * @name Register AIPS_PACRP, field WP1[25] (RW) 12085 * 12086 * Determines whether the peripheral allows write accesses. When this field is 12087 * set and a write access is attempted, access terminates with an error response 12088 * and no peripheral access initiates. 12089 * 12090 * Values: 12091 * - 0 - This peripheral allows write accesses. 12092 * - 1 - This peripheral is write protected. 12093 */ 12094 /*@{*/ 12095 #define BP_AIPS_PACRP_WP1 (25U) /*!< Bit position for AIPS_PACRP_WP1. */ 12096 #define BM_AIPS_PACRP_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRP_WP1. */ 12097 #define BS_AIPS_PACRP_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP1. */ 12098 12099 /*! @brief Read current value of the AIPS_PACRP_WP1 field. */ 12100 #define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1)) 12101 12102 /*! @brief Format value for bitfield AIPS_PACRP_WP1. */ 12103 #define BF_AIPS_PACRP_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP1) & BM_AIPS_PACRP_WP1) 12104 12105 /*! @brief Set the WP1 field to a new value. */ 12106 #define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v)) 12107 /*@}*/ 12108 12109 /*! 12110 * @name Register AIPS_PACRP, field SP1[26] (RW) 12111 * 12112 * Determines whether the peripheral requires supervisor privilege level for 12113 * access. When this field is set, the master privilege level must indicate the 12114 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 12115 * be set. If not, access terminates with an error response and no peripheral 12116 * access initiates. 12117 * 12118 * Values: 12119 * - 0 - This peripheral does not require supervisor privilege level for 12120 * accesses. 12121 * - 1 - This peripheral requires supervisor privilege level for accesses. 12122 */ 12123 /*@{*/ 12124 #define BP_AIPS_PACRP_SP1 (26U) /*!< Bit position for AIPS_PACRP_SP1. */ 12125 #define BM_AIPS_PACRP_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRP_SP1. */ 12126 #define BS_AIPS_PACRP_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP1. */ 12127 12128 /*! @brief Read current value of the AIPS_PACRP_SP1 field. */ 12129 #define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1)) 12130 12131 /*! @brief Format value for bitfield AIPS_PACRP_SP1. */ 12132 #define BF_AIPS_PACRP_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP1) & BM_AIPS_PACRP_SP1) 12133 12134 /*! @brief Set the SP1 field to a new value. */ 12135 #define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v)) 12136 /*@}*/ 12137 12138 /*! 12139 * @name Register AIPS_PACRP, field TP0[28] (RW) 12140 * 12141 * Determines whether the peripheral allows accesses from an untrusted master. 12142 * When this bit is set and an access is attempted by an untrusted master, the 12143 * access terminates with an error response and no peripheral access initiates. 12144 * 12145 * Values: 12146 * - 0 - Accesses from an untrusted master are allowed. 12147 * - 1 - Accesses from an untrusted master are not allowed. 12148 */ 12149 /*@{*/ 12150 #define BP_AIPS_PACRP_TP0 (28U) /*!< Bit position for AIPS_PACRP_TP0. */ 12151 #define BM_AIPS_PACRP_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRP_TP0. */ 12152 #define BS_AIPS_PACRP_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP0. */ 12153 12154 /*! @brief Read current value of the AIPS_PACRP_TP0 field. */ 12155 #define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0)) 12156 12157 /*! @brief Format value for bitfield AIPS_PACRP_TP0. */ 12158 #define BF_AIPS_PACRP_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP0) & BM_AIPS_PACRP_TP0) 12159 12160 /*! @brief Set the TP0 field to a new value. */ 12161 #define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v)) 12162 /*@}*/ 12163 12164 /*! 12165 * @name Register AIPS_PACRP, field WP0[29] (RW) 12166 * 12167 * Determines whether the peripheral allows write accesses. When this field is 12168 * set and a write access is attempted, access terminates with an error response 12169 * and no peripheral access initiates. 12170 * 12171 * Values: 12172 * - 0 - This peripheral allows write accesses. 12173 * - 1 - This peripheral is write protected. 12174 */ 12175 /*@{*/ 12176 #define BP_AIPS_PACRP_WP0 (29U) /*!< Bit position for AIPS_PACRP_WP0. */ 12177 #define BM_AIPS_PACRP_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRP_WP0. */ 12178 #define BS_AIPS_PACRP_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP0. */ 12179 12180 /*! @brief Read current value of the AIPS_PACRP_WP0 field. */ 12181 #define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0)) 12182 12183 /*! @brief Format value for bitfield AIPS_PACRP_WP0. */ 12184 #define BF_AIPS_PACRP_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP0) & BM_AIPS_PACRP_WP0) 12185 12186 /*! @brief Set the WP0 field to a new value. */ 12187 #define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v)) 12188 /*@}*/ 12189 12190 /*! 12191 * @name Register AIPS_PACRP, field SP0[30] (RW) 12192 * 12193 * Determines whether the peripheral requires supervisor privilege level for 12194 * accesses. When this field is set, the master privilege level must indicate the 12195 * supervisor access attribute, and the MPRx[MPLn] control field for the master 12196 * must be set. If not, access terminates with an error response and no peripheral 12197 * access initiates. 12198 * 12199 * Values: 12200 * - 0 - This peripheral does not require supervisor privilege level for 12201 * accesses. 12202 * - 1 - This peripheral requires supervisor privilege level for accesses. 12203 */ 12204 /*@{*/ 12205 #define BP_AIPS_PACRP_SP0 (30U) /*!< Bit position for AIPS_PACRP_SP0. */ 12206 #define BM_AIPS_PACRP_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRP_SP0. */ 12207 #define BS_AIPS_PACRP_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP0. */ 12208 12209 /*! @brief Read current value of the AIPS_PACRP_SP0 field. */ 12210 #define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0)) 12211 12212 /*! @brief Format value for bitfield AIPS_PACRP_SP0. */ 12213 #define BF_AIPS_PACRP_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP0) & BM_AIPS_PACRP_SP0) 12214 12215 /*! @brief Set the SP0 field to a new value. */ 12216 #define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v)) 12217 /*@}*/ 12218 12219 /******************************************************************************* 12220 * HW_AIPS_PACRU - Peripheral Access Control Register 12221 ******************************************************************************/ 12222 12223 /*! 12224 * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) 12225 * 12226 * Reset value: 0x44000000U 12227 * 12228 * PACRU defines the access levels for the two global spaces. 12229 */ 12230 typedef union _hw_aips_pacru 12231 { 12232 uint32_t U; 12233 struct _hw_aips_pacru_bitfields 12234 { 12235 uint32_t RESERVED0 : 24; /*!< [23:0] */ 12236 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 12237 uint32_t WP1 : 1; /*!< [25] Write Protect */ 12238 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 12239 uint32_t RESERVED1 : 1; /*!< [27] */ 12240 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 12241 uint32_t WP0 : 1; /*!< [29] Write Protect */ 12242 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 12243 uint32_t RESERVED2 : 1; /*!< [31] */ 12244 } B; 12245 } hw_aips_pacru_t; 12246 12247 /*! 12248 * @name Constants and macros for entire AIPS_PACRU register 12249 */ 12250 /*@{*/ 12251 #define HW_AIPS_PACRU_ADDR(x) ((x) + 0x80U) 12252 12253 #define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) 12254 #define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U) 12255 #define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v)) 12256 #define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) 12257 #define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) 12258 #define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) 12259 /*@}*/ 12260 12261 /* 12262 * Constants & macros for individual AIPS_PACRU bitfields 12263 */ 12264 12265 /*! 12266 * @name Register AIPS_PACRU, field TP1[24] (RW) 12267 * 12268 * Determines whether the peripheral allows accesses from an untrusted master. 12269 * When this field is set and an access is attempted by an untrusted master, the 12270 * access terminates with an error response and no peripheral access initiates. 12271 * 12272 * Values: 12273 * - 0 - Accesses from an untrusted master are allowed. 12274 * - 1 - Accesses from an untrusted master are not allowed. 12275 */ 12276 /*@{*/ 12277 #define BP_AIPS_PACRU_TP1 (24U) /*!< Bit position for AIPS_PACRU_TP1. */ 12278 #define BM_AIPS_PACRU_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRU_TP1. */ 12279 #define BS_AIPS_PACRU_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP1. */ 12280 12281 /*! @brief Read current value of the AIPS_PACRU_TP1 field. */ 12282 #define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1)) 12283 12284 /*! @brief Format value for bitfield AIPS_PACRU_TP1. */ 12285 #define BF_AIPS_PACRU_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP1) & BM_AIPS_PACRU_TP1) 12286 12287 /*! @brief Set the TP1 field to a new value. */ 12288 #define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v)) 12289 /*@}*/ 12290 12291 /*! 12292 * @name Register AIPS_PACRU, field WP1[25] (RW) 12293 * 12294 * Determines whether the peripheral allows write accesss. When this bit is set 12295 * and a write access is attempted, access terminates with an error response and 12296 * no peripheral access initiates. 12297 * 12298 * Values: 12299 * - 0 - This peripheral allows write accesses. 12300 * - 1 - This peripheral is write protected. 12301 */ 12302 /*@{*/ 12303 #define BP_AIPS_PACRU_WP1 (25U) /*!< Bit position for AIPS_PACRU_WP1. */ 12304 #define BM_AIPS_PACRU_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRU_WP1. */ 12305 #define BS_AIPS_PACRU_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP1. */ 12306 12307 /*! @brief Read current value of the AIPS_PACRU_WP1 field. */ 12308 #define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1)) 12309 12310 /*! @brief Format value for bitfield AIPS_PACRU_WP1. */ 12311 #define BF_AIPS_PACRU_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP1) & BM_AIPS_PACRU_WP1) 12312 12313 /*! @brief Set the WP1 field to a new value. */ 12314 #define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v)) 12315 /*@}*/ 12316 12317 /*! 12318 * @name Register AIPS_PACRU, field SP1[26] (RW) 12319 * 12320 * Determines whether the peripheral requires supervisor privilege level for 12321 * accesses. When this field is set, the master privilege level must indicate the 12322 * supervisor access attribute, and the MPRx[MPLn] control field for the master 12323 * must be set. If not, access terminates with an error response and no peripheral 12324 * access initiates. 12325 * 12326 * Values: 12327 * - 0 - This peripheral does not require supervisor privilege level for 12328 * accesses. 12329 * - 1 - This peripheral requires supervisor privilege level for accesses. 12330 */ 12331 /*@{*/ 12332 #define BP_AIPS_PACRU_SP1 (26U) /*!< Bit position for AIPS_PACRU_SP1. */ 12333 #define BM_AIPS_PACRU_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRU_SP1. */ 12334 #define BS_AIPS_PACRU_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP1. */ 12335 12336 /*! @brief Read current value of the AIPS_PACRU_SP1 field. */ 12337 #define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1)) 12338 12339 /*! @brief Format value for bitfield AIPS_PACRU_SP1. */ 12340 #define BF_AIPS_PACRU_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP1) & BM_AIPS_PACRU_SP1) 12341 12342 /*! @brief Set the SP1 field to a new value. */ 12343 #define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v)) 12344 /*@}*/ 12345 12346 /*! 12347 * @name Register AIPS_PACRU, field TP0[28] (RW) 12348 * 12349 * Determines whether the peripheral allows accesses from an untrusted master. 12350 * When this field is set and an access is attempted by an untrusted master, the 12351 * access terminates with an error response and no peripheral access initiates. 12352 * 12353 * Values: 12354 * - 0 - Accesses from an untrusted master are allowed. 12355 * - 1 - Accesses from an untrusted master are not allowed. 12356 */ 12357 /*@{*/ 12358 #define BP_AIPS_PACRU_TP0 (28U) /*!< Bit position for AIPS_PACRU_TP0. */ 12359 #define BM_AIPS_PACRU_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRU_TP0. */ 12360 #define BS_AIPS_PACRU_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP0. */ 12361 12362 /*! @brief Read current value of the AIPS_PACRU_TP0 field. */ 12363 #define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0)) 12364 12365 /*! @brief Format value for bitfield AIPS_PACRU_TP0. */ 12366 #define BF_AIPS_PACRU_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP0) & BM_AIPS_PACRU_TP0) 12367 12368 /*! @brief Set the TP0 field to a new value. */ 12369 #define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v)) 12370 /*@}*/ 12371 12372 /*! 12373 * @name Register AIPS_PACRU, field WP0[29] (RW) 12374 * 12375 * Determines whether the peripheral allows write accesses. When this field is 12376 * set and a write access is attempted, access terminates with an error response 12377 * and no peripheral access initiates. 12378 * 12379 * Values: 12380 * - 0 - This peripheral allows write accesses. 12381 * - 1 - This peripheral is write protected. 12382 */ 12383 /*@{*/ 12384 #define BP_AIPS_PACRU_WP0 (29U) /*!< Bit position for AIPS_PACRU_WP0. */ 12385 #define BM_AIPS_PACRU_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRU_WP0. */ 12386 #define BS_AIPS_PACRU_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP0. */ 12387 12388 /*! @brief Read current value of the AIPS_PACRU_WP0 field. */ 12389 #define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0)) 12390 12391 /*! @brief Format value for bitfield AIPS_PACRU_WP0. */ 12392 #define BF_AIPS_PACRU_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP0) & BM_AIPS_PACRU_WP0) 12393 12394 /*! @brief Set the WP0 field to a new value. */ 12395 #define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v)) 12396 /*@}*/ 12397 12398 /*! 12399 * @name Register AIPS_PACRU, field SP0[30] (RW) 12400 * 12401 * Determines whether the peripheral requires supervisor privilege level for 12402 * access. When this bit is set, the master privilege level must indicate the 12403 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 12404 * set. If not, access terminates with an error response and no peripheral access 12405 * initiates. 12406 * 12407 * Values: 12408 * - 0 - This peripheral does not require supervisor privilege level for 12409 * accesses. 12410 * - 1 - This peripheral requires supervisor privilege level for accesses. 12411 */ 12412 /*@{*/ 12413 #define BP_AIPS_PACRU_SP0 (30U) /*!< Bit position for AIPS_PACRU_SP0. */ 12414 #define BM_AIPS_PACRU_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRU_SP0. */ 12415 #define BS_AIPS_PACRU_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP0. */ 12416 12417 /*! @brief Read current value of the AIPS_PACRU_SP0 field. */ 12418 #define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0)) 12419 12420 /*! @brief Format value for bitfield AIPS_PACRU_SP0. */ 12421 #define BF_AIPS_PACRU_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP0) & BM_AIPS_PACRU_SP0) 12422 12423 /*! @brief Set the SP0 field to a new value. */ 12424 #define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v)) 12425 /*@}*/ 12426 12427 /******************************************************************************* 12428 * hw_aips_t - module struct 12429 ******************************************************************************/ 12430 /*! 12431 * @brief All AIPS module registers. 12432 */ 12433 #pragma pack(1) 12434 typedef struct _hw_aips 12435 { 12436 __IO hw_aips_mpra_t MPRA ; /*!< [0x0] Master Privilege Register A */ 12437 uint8_t _reserved0[28]; 12438 __IO hw_aips_pacra_t PACRA ; /*!< [0x20] Peripheral Access Control Register */ 12439 __IO hw_aips_pacrb_t PACRB ; /*!< [0x24] Peripheral Access Control Register */ 12440 __IO hw_aips_pacrc_t PACRC ; /*!< [0x28] Peripheral Access Control Register */ 12441 __IO hw_aips_pacrd_t PACRD ; /*!< [0x2C] Peripheral Access Control Register */ 12442 uint8_t _reserved1[16]; 12443 __IO hw_aips_pacre_t PACRE ; /*!< [0x40] Peripheral Access Control Register */ 12444 __IO hw_aips_pacrf_t PACRF ; /*!< [0x44] Peripheral Access Control Register */ 12445 __IO hw_aips_pacrg_t PACRG ; /*!< [0x48] Peripheral Access Control Register */ 12446 __IO hw_aips_pacrh_t PACRH ; /*!< [0x4C] Peripheral Access Control Register */ 12447 __IO hw_aips_pacri_t PACRI ; /*!< [0x50] Peripheral Access Control Register */ 12448 __IO hw_aips_pacrj_t PACRJ ; /*!< [0x54] Peripheral Access Control Register */ 12449 __IO hw_aips_pacrk_t PACRK ; /*!< [0x58] Peripheral Access Control Register */ 12450 __IO hw_aips_pacrl_t PACRL ; /*!< [0x5C] Peripheral Access Control Register */ 12451 __IO hw_aips_pacrm_t PACRM ; /*!< [0x60] Peripheral Access Control Register */ 12452 __IO hw_aips_pacrn_t PACRN ; /*!< [0x64] Peripheral Access Control Register */ 12453 __IO hw_aips_pacro_t PACRO ; /*!< [0x68] Peripheral Access Control Register */ 12454 __IO hw_aips_pacrp_t PACRP ; /*!< [0x6C] Peripheral Access Control Register */ 12455 uint8_t _reserved2[16]; 12456 __IO hw_aips_pacru_t PACRU ; /*!< [0x80] Peripheral Access Control Register */ 12457 } hw_aips_t; 12458 #pragma pack() 12459 12460 /*! @brief Macro to access all AIPS registers. */ 12461 /*! @param x AIPS module instance base address. */ 12462 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 12463 * use the '&' operator, like <code>&HW_AIPS(AIPS0_BASE)</code>. */ 12464 #define HW_AIPS(x) (*(hw_aips_t *)(x)) 12465 12466 #endif /* __HW_AIPS_REGISTERS_H__ */ 12467 /* EOF */
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