Morpheus
/
target-freescale-ksdk
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of target-freescale-ksdk by
Revision 0:e4d670b91a9a, committed 2016-03-23
- Comitter:
- screamer
- Date:
- Wed Mar 23 21:26:50 2016 +0000
- Commit message:
- Initial revision
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/PeripheralPins.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/PortNames.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,267 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_phy_driver.h"
+
+#ifndef MBED_NO_ENET
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Define Phy API structure for MAC application*/
+const enet_phy_api_t g_enetPhyApi =
+{
+ phy_auto_discover,
+ phy_init,
+ phy_get_link_speed,
+ phy_get_link_status,
+ phy_get_link_duplex,
+};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: phy_init
+ * Return Value: The execution status.
+ * Description: Initialize Phy.
+ * This interface provides initialize functions for Phy, This is called by enet
+ * initialize function. Phy is usually deault auto-negotiation. so there is no
+ * need to do the intialize about this. we just need to check the loop mode.
+ *END*********************************************************************/
+uint32_t phy_init(enet_dev_if_t * enetIfPtr)
+{
+ uint32_t data;
+ uint32_t counter;
+ uint32_t result;
+
+ /* Check input parameters*/
+ if (!enetIfPtr)
+ {
+ return kStatus_PHY_InvaildInput;
+ }
+
+ /* Reset Phy*/
+ if ((result = (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR,&data))) == kStatus_PHY_Success)
+ {
+ if ((data & kEnetPhyAutoNegAble) != 0)
+ {
+ /* Set Autonegotiation*/
+ enetIfPtr->macApiPtr->enet_mii_write(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr, kEnetPhyCR, kEnetPhyAutoNeg);
+ for (counter = 0; counter < kPhyTimeout; counter++)
+ {
+ if (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR,&data)== kStatus_PHY_Success)
+ {
+ if ((data & kEnetPhyAutoNegComplete) != 0)
+ {
+ break;
+ }
+ }
+ }
+
+ if (counter == kPhyTimeout)
+ {
+ return kStatus_PHY_TimeOut;
+ }
+ }
+ }
+
+ if (enetIfPtr->phyCfgPtr->isLoopEnabled)
+ {
+ /* First read the current status in control register*/
+ if (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,&data))
+ {
+ result = enetIfPtr->macApiPtr->enet_mii_write(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,(data|kEnetPhyLoop));
+ }
+ }
+
+ return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: phy_auto_discover
+ * Return Value: The execution status.
+ * Description: Phy address auto discover.
+ * This function provides a interface to get phy address using phy address auto
+ * discovering, this interface is used when the phy address is unknown.
+ *END*********************************************************************/
+uint32_t phy_auto_discover(enet_dev_if_t * enetIfPtr)
+{
+ uint32_t addrIdx,data;
+ uint32_t result = kStatus_PHY_Fail;
+
+ /* Check input parameters*/
+ if (!enetIfPtr)
+ {
+ return kStatus_PHY_InvaildInput;
+ }
+
+ for (addrIdx = 0; addrIdx < 32; addrIdx++)
+ {
+ enetIfPtr->phyCfgPtr->phyAddr = addrIdx;
+ result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyId1,&data);
+ if ((result == kStatus_PHY_Success) && (data != 0) && (data != 0xffff) )
+ {
+ return kStatus_PHY_Success;
+ }
+ }
+
+ return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: phy_get_link_speed
+ * Return Value: The execution status.
+ * Description: Get phy link speed.
+ * This function provides a interface to get link speed.
+ *END*********************************************************************/
+uint32_t phy_get_link_speed(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *status)
+{
+ uint32_t result = kStatus_PHY_Success;
+ uint32_t data;
+
+ /* Check input parameters*/
+ if ((!enetIfPtr) || (!status))
+ {
+ return kStatus_PHY_InvaildInput;
+ }
+
+ result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr, kEnetPhyCt2,&data);
+ if (result == kStatus_PHY_Success)
+ {
+ data &= kEnetPhySpeedDulpexMask;
+ if ((kEnetPhy100HalfDuplex == data) || (kEnetPhy100FullDuplex == data))
+ {
+ *status = kEnetSpeed100M;
+ }
+ else
+ {
+ *status = kEnetSpeed10M;
+ }
+ }
+
+ return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: phy_get_link_status
+ * Return Value: The execution status.
+ * Description: Get phy link status.
+ * This function provides a interface to get link status to see if the link
+ * status is on or off.
+ *END*********************************************************************/
+ uint32_t phy_get_link_status(enet_dev_if_t * enetIfPtr, bool *status)
+{
+ uint32_t result = kStatus_PHY_Success;
+ uint32_t data;
+
+ /* Check input parameters*/
+ if ((!enetIfPtr) || (!status))
+ {
+ return kStatus_PHY_InvaildInput;
+ }
+
+ result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,&data);
+ if ((result == kStatus_PHY_Success) && (!(data & kEnetPhyReset)))
+ {
+ data = 0;
+ result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR, &data);
+ if (result == kStatus_PHY_Success)
+ {
+ if (!(kEnetPhyLinkStatus & data))
+ {
+ *status = false;
+ }
+ else
+ {
+ *status = true;
+ }
+ }
+ }
+
+ return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: phy_get_link_duplex
+ * Return Value: The execution status.
+ * Description: Get phy link duplex.
+ * This function provides a interface to get link duplex to see if the link
+ * duplex is full or half.
+ *END*********************************************************************/
+uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *status)
+{
+ uint32_t result = kStatus_PHY_Success;
+ uint32_t data;
+
+ /* Check input parameters*/
+ if ((!enetIfPtr) || (!status))
+ {
+ return kStatus_PHY_InvaildInput;
+ }
+
+ result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber,
+ enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCt2,&data);
+ if (result == kStatus_PHY_Success)
+ {
+ data &= kEnetPhySpeedDulpexMask;
+ if ((kEnetPhy10FullDuplex == data) || (kEnetPhy100FullDuplex == data))
+ {
+ *status = kEnetFullDuplex;
+ }
+ else
+ {
+ *status = kEnetHalfDuplex;
+ }
+ }
+
+ return result;
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PHY_DRIVER_H__
+#define __FSL_PHY_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_enet_driver.h"
+
+#ifndef MBED_NO_ENET
+
+/*!
+ * @addtogroup phy_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines the PHY return status. */
+typedef enum _phy_status
+{
+ kStatus_PHY_Success = 0, /*!< Success*/
+ kStatus_PHY_InvaildInput = 1, /*!< Invalid PHY input parameter*/
+ kStatus_PHY_TimeOut = 2, /*!< PHY timeout*/
+ kStatus_PHY_Fail = 3 /*!< PHY fail*/
+} phy_status_t;
+
+/*! @brief Defines the ENET timeout.*/
+typedef enum _phy_timeout
+{
+ kPhyTimeout = 0x10000, /*!< ENET resets timeout.*/
+} phy_timeout_t;
+
+/*! @brief Defines the PHY register.*/
+typedef enum _enet_phy_register
+{
+ kEnetPhyCR = 0, /*!< PHY control register */
+ kEnetPhySR = 1, /*!< PHY status register*/
+ kEnetPhyId1 = 2, /*!< PHY identification register 1*/
+ kEnetPhyId2 = 3, /*!< PHY identification register 2*/
+ kEnetPhyCt2 = 0x1e /*!< PHY control2 register*/
+} enet_phy_register_t;
+
+/*! @brief Defines the control flag.*/
+typedef enum _enet_phy_control
+{
+ kEnetPhyAutoNeg = 0x1000,/*!< ENET PHY auto negotiation control*/
+ kEnetPhySpeed = 0x2000, /*! ENET PHY speed control*/
+ kEnetPhyLoop = 0x4000, /*!< ENET PHY loop control*/
+ kEnetPhyReset = 0x8000, /*!< ENET PHY reset control*/
+ kEnetPhy10HalfDuplex = 0x01, /*!< ENET PHY 10 M half duplex*/
+ kEnetPhy100HalfDuplex = 0x02,/*!< ENET PHY 100 M half duplex*/
+ kEnetPhy10FullDuplex = 0x05,/*!< ENET PHY 10 M full duplex*/
+ kEnetPhy100FullDuplex = 0x06/*!< ENET PHY 100 M full duplex*/
+} enet_phy_control_t;
+
+/*! @brief Defines the PHY link speed. */
+typedef enum _enet_phy_speed
+{
+ kEnetSpeed10M = 0, /*!< ENET PHY 10 M speed*/
+ kEnetSpeed100M = 1 /*!< ENET PHY 100 M speed*/
+} enet_phy_speed_t;
+
+/*! @brief Defines the PHY link duplex.*/
+typedef enum _enet_phy_duplex
+{
+ kEnetHalfDuplex = 0, /*!< ENET PHY half duplex*/
+ kEnetFullDuplex = 1 /*!< ENET PHY full duplex*/
+} enet_phy_duplex_t;
+
+/*! @brief Defines the PHY status.*/
+typedef enum _enet_phy_status
+{
+ kEnetPhyLinkStatus = 0x4, /*!< ENET PHY link status bit*/
+ kEnetPhyAutoNegAble = 0x08, /*!< ENET PHY auto negotiation ability*/
+ kEnetPhyAutoNegComplete = 0x20, /*!< ENET PHY auto negotiation complete*/
+ kEnetPhySpeedDulpexMask = 0x07 /*!< ENET PHY speed mask on status register 2*/
+} enet_phy_status_t;
+
+/*! @brief Defines the basic PHY application.*/
+typedef struct ENETPhyApi
+{
+ uint32_t (* phy_auto_discover)(enet_dev_if_t * enetIfPtr);/*!< PHY auto discover*/
+ uint32_t (* phy_init)(enet_dev_if_t * enetIfPtr);/*!< PHY initialize*/
+ uint32_t (* phy_get_link_speed)(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *speed);/*!< Get PHY speed*/
+ uint32_t (* phy_get_link_status)(enet_dev_if_t * enetIfPtr, bool *status);/*! Get PHY link status*/
+ uint32_t (* phy_get_link_duplex)(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *duplex);/*!< Get PHY link duplex*/
+} enet_phy_api_t;
+
+/*******************************************************************************
+ * Global variables
+ ******************************************************************************/
+extern const enet_phy_api_t g_enetPhyApi;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name PHY Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes PHY.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t phy_init(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief PHY address auto discover.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t phy_auto_discover(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Gets the PHY link speed.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param status The link speed of PHY.
+ * @return The execution status.
+ */
+uint32_t phy_get_link_speed(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *status);
+
+/*!
+ * @brief Gets the PHY link status.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param status The link on or down status of the PHY.
+ * @return The execution status.
+ */
+uint32_t phy_get_link_status(enet_dev_if_t * enetIfPtr, bool *status);
+
+/*!
+ * @brief Gets the PHY link duplex.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param status The link duplex status of PHY.
+ * @return The execution status.
+ */
+uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *status);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PHY_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Table of base addresses for instances. */
+const uint32_t g_simBaseAddr[] = SIM_BASE_ADDRS;
+const uint32_t g_mcgBaseAddr[] = MCG_BASE_ADDRS;
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+ uint32_t *frequency)
+{
+ /* system clock out divider*/
+ uint32_t divider;
+
+ const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+ /* check if we need to use a reference clock*/
+ if (table->useOtherRefClock)
+ {
+ /* get other specified ref clock*/
+ if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+ frequency) )
+ {
+ return kClockManagerNoSuchClockName;
+ }
+ }
+ else
+ {
+ /* get default ref clock */
+ *frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]);
+ }
+
+ /* get system clock divider*/
+ if ( CLOCK_HAL_GetDivider(g_simBaseAddr[0], table->dividerName, ÷r) == kSimHalSuccess)
+ {
+ /* get the frequency for the specified clock*/
+ *frequency = (*frequency) / (divider + 1);
+ return kClockManagerSuccess;
+ }
+ else
+ {
+ return kClockManagerNoSuchDivider;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFreq
+ * Description : Internal function to get the frequency by clock name
+ * This function will get/calculate the clock frequency based on clock name
+ * and current configuration of clock generator.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+ uint32_t *frequency)
+{
+ clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+ /* branch according to clock name */
+ switch(clockName)
+ {
+ /* osc clock*/
+ case kOsc32kClock:
+ *frequency = CPU_XTAL32k_CLK_HZ;
+ break;
+ case kOsc0ErClock:
+#if FSL_FEATURE_MCG_HAS_OSC1
+ /* System oscillator 0 drives MCG clock */
+ *frequency = CPU_XTAL0_CLK_HZ;
+#else
+ /* System oscillator 0 drives MCG clock */
+ *frequency = CPU_XTAL_CLK_HZ;
+#endif
+ break;
+
+#if FSL_FEATURE_MCG_HAS_OSC1
+ case kOsc1ErClock:
+ *frequency = CPU_XTAL1_CLK_HZ;
+ break;
+#endif
+
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+ /* irc clock*/
+ case kIrc48mClock:
+ *frequency = CPU_INT_IRC_CLK_HZ;
+ break;
+#endif
+
+ /* rtc clock*/
+ case kRtc32kClock:
+ *frequency = CPU_XTAL32k_CLK_HZ;
+ break;
+
+ case kRtc1hzClock:
+ *frequency = CPU_XTAL1hz_CLK_HZ; // defined in fsl_clock_manager.h for now
+ break;
+
+ /* lpo clcok*/
+ case kLpoClock:
+ *frequency = CPU_LPO_CLK_HZ; // defined in fsl_clock_manager.h for now
+ break;
+
+ /* mcg clocks, calling mcg clock functions */
+ case kMcgFfClock:
+ *frequency = CLOCK_HAL_GetFllRefClk(g_mcgBaseAddr[0]);
+ break;
+ case kMcgFllClock:
+ *frequency = CLOCK_HAL_GetFllClk(g_mcgBaseAddr[0]);
+ break;
+#if FSL_FEATURE_MCG_HAS_PLL
+ case kMcgPll0Clock:
+ *frequency = CLOCK_HAL_GetPll0Clk(g_mcgBaseAddr[0]);
+ break;
+#endif
+ case kMcgOutClock:
+ *frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]);
+ break;
+ case kMcgIrClock:
+ *frequency = CLOCK_HAL_GetInternalRefClk(g_mcgBaseAddr[0]);
+ break;
+
+ case kSDHC0_CLKIN:
+ *frequency = SDHC0_CLKIN; // defined in fsl_clock_manager.h for now
+ break;
+ case kENET_1588_CLKIN:
+ *frequency = ENET_1588_CLKIN; // defined in fsl_clock_manager.h for now
+ break;
+ case kEXTAL_Clock:
+ *frequency = EXTAL_Clock; // defined in fsl_clock_manager.h for now
+ break;
+ case kEXTAL1_Clock:
+ *frequency = EXTAL1_Clock; // defined in fsl_clock_manager.h for now
+ break;
+ case kUSB_CLKIN:
+ *frequency = USB_CLKIN; // defined in fsl_clock_manager.h for now
+ break;
+
+ /* system clocks */
+ case kCoreClock:
+ case kSystemClock:
+ case kPlatformClock:
+ case kBusClock:
+ case kFlexBusClock:
+ case kFlashClock:
+ returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+ break;
+ /* reserved value*/
+ case kReserved:
+ default:
+ *frequency = 55555; /* for testing use purpose*/
+ returnCode = kClockManagerNoSuchClockName;
+ break;
+ }
+
+ return returnCode;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSource
+ * Description : Set clock source setting
+ * This function will set the settings for specified clock source. Each clock
+ * source has its clock selection settings. Refer to reference manual for
+ * details of settings for each clock source. Refer to clock_source_names_t
+ * for clock sources.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource,
+ uint8_t setting)
+{
+ clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+ if (CLOCK_HAL_SetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess)
+ {
+ returnCode = kClockManagerNoSuchClockSource;
+ }
+
+ return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSource
+ * Description : Get clock source setting
+ * This function will get the settings for specified clock source. Each clock
+ * source has its clock selection settings. Refer to reference manual for
+ * details of settings for each clock source. Refer to clock_source_names_t
+ * for clock sources.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource,
+ uint8_t *setting)
+{
+ clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+ if (CLOCK_HAL_GetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess)
+ {
+ returnCode = kClockManagerNoSuchClockSource;
+ }
+
+ return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetDivider
+ * Description : Set clock divider setting
+ * This function will set the setting for specified clock divider. Refer to
+ * reference manual for supported clock divider and value range. Refer to
+ * clock_divider_names_t for dividers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider,
+ uint32_t setting)
+{
+ clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+ if (CLOCK_HAL_SetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess)
+ {
+ returnCode = kClockManagerNoSuchDivider;
+ }
+
+ return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDivider
+ * Description : Get clock divider setting
+ * This function will get the setting for specified clock divider. Refer to
+ * reference manual for supported clock divider and value range. Refer to
+ * clock_divider_names_t for dividers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider,
+ uint32_t *setting)
+{
+ clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+ if (CLOCK_HAL_GetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess)
+ {
+ returnCode = kClockManagerNoSuchDivider;
+ }
+
+ return returnCode;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,429 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_MANAGER_H__)
+#define __FSL_CLOCK_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* system clocks definition (should be moved to other proper place) */
+#define CPU_XTAL1hz_CLK_HZ 1
+#define CPU_LPO_CLK_HZ 1000
+
+/* external clock definition (should be moved to other proper place) */
+
+#define SDHC0_CLKIN 0 /* kSimSDHC0_CLKIN */
+#define ENET_1588_CLKIN 0 /* kSimENET_1588_CLKIN */
+#define EXTAL_Clock 0 /* kSimEXTAL_Clock */
+#define EXTAL1_Clock 0 /* kSimEXTAL1_Clock */
+#define USB_CLKIN 0 /* kSimUSB_CLKIN */
+
+/* Table of base addresses for instances. */
+extern const uint32_t g_simBaseAddr[];
+extern const uint32_t g_mcgBaseAddr[];
+
+/*!
+ * @brief Error code definition for the clock manager APIs
+ */
+typedef enum _clock_manager_error_code {
+ kClockManagerSuccess, /*!< success */
+ kClockManagerNoSuchClockName, /*!< cannot find the clock name */
+ kClockManagerNoSuchClockModule, /*!< cannot find the clock module name */
+ kClockManagerNoSuchClockSource, /*!< cannot find the clock source name */
+ kClockManagerNoSuchDivider, /*!< cannot find the divider name */
+ kClockManagerUnknown /*!< unknown error*/
+} clock_manager_error_code_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Clock Frequencies*/
+/*@{*/
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_names_t.
+ * The MCG must be properly configured before using this function. See
+ * the reference manual for supported clock names for different chip families.
+ * The returned value is in Hertz. If it cannot find the clock name
+ * or the name is not supported for a specific chip family, it returns an
+ * error.
+ *
+ * @param clockName Clock names defined in clock_names_t
+ * @param frequency Returned clock frequency value in Hertz
+ * @return status Error code defined in clock_manager_error_code_t
+ */
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+ uint32_t *frequency);
+
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function sets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the chip reference manual for
+ * clock source detailed settings and the sim_clock_source_names_t
+ * for clock sources.
+ *
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting Setting value
+ * @return status If the clock source doesn't exist, it returns an error.
+ */
+clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource,
+ uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the sim_clock_source_names_t
+ * for clock sources.
+ *
+ * @param clockSource Clock source name
+ * @param setting Current setting for the clock source
+ * @return status If the clock source doesn't exist, it returns an error.
+ */
+clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource,
+ uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * sim_clock_divider_names_t for dividers.
+ *
+ * @param clockDivider Clock divider name
+ * @param divider Divider setting
+ * @return status If the clock divider doesn't exist, it returns an error.
+ */
+clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider,
+ uint32_t setting);
+
+/*!
+ * @brief Gets the clock divider setting.
+ *
+ * This function gets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param clockDivider Clock divider name
+ * @param divider Divider value pointer
+ * @return status If the clock divider doesn't exist, it returns an error.
+ */
+clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider,
+ uint32_t *setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param outdiv1 Outdivider1 setting
+ * @param outdiv2 Outdivider2 setting
+ * @param outdiv3 Outdivider3 setting
+ * @param outdiv4 Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDividers(uint32_t outdiv1, uint32_t outdiv2,
+ uint32_t outdiv3, uint32_t outdiv4)
+{
+ CLOCK_HAL_SetOutDividers(g_simBaseAddr[0], outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+/*
+ * Include the cpu specific clock API header files.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+ defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+ #define K02F12810_SERIES
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+ defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+ defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+ defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+ defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+ defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+ defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+ defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+ defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+ defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+ #define K20D5_SERIES
+
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+ defined(CPU_MK22FN128VMP10))
+
+ #define K22F12810_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F12810/fsl_clock_K22F12810.h"
+
+#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \
+ defined(CPU_MK22FN256VMP12))
+
+ #define K22F25612_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F25612/fsl_clock_K22F25612.h"
+
+
+
+#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12))
+
+ #define K22F51212_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F51212/fsl_clock_K22F51212.h"
+
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12))
+
+ #define K24F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK24F12/fsl_clock_K24F12.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+ #define K24F25612_SERIES
+
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+ #define K63F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK63F12/fsl_clock_K63F12.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+ defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+ defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+ #define K64F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK64F12/fsl_clock_K64F12.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+ defined(CPU_MK65FX1M0VMI18))
+
+ #define K65F18_SERIES
+
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+ defined(CPU_MK66FX1M0VMD18))
+
+ #define K66F18_SERIES
+
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+ defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+ defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+ #define K70F12_SERIES
+
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+ defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+ defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+ #define K70F15_SERIES
+
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+ defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+ defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+ #define KL02Z4_SERIES
+
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+ defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+ defined(CPU_MKL03Z32VFK4))
+
+ #define KL03Z4_SERIES
+
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+ defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+ defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+ defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+ #define KL05Z4_SERIES
+
+
+#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \
+ defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \
+ defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
+ defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4))
+
+ #define KL13Z4_SERIES
+
+
+#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \
+ defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \
+ defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
+ defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4))
+
+ #define KL23Z4_SERIES
+
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+ defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+ defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+ defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+ #define KL25Z4_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKL25Z4/fsl_clock_KL25Z4.h"
+
+#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \
+ defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \
+ defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
+ defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \
+ defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4))
+
+ #define KL26Z4_SERIES
+
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+ defined(CPU_MKL33Z256VMP4))
+
+ #define KL33Z4_SERIES
+
+
+#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \
+ defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4))
+
+ #define KL43Z4_SERIES
+
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+ defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4))
+
+ #define KL46Z4_SERIES
+
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+ defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+ #define KV30F12810_SERIES
+
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+ #define KV31F12810_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F12810/fsl_clock_KV31F12810.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+ #define KV31F25612_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F25612/fsl_clock_KV31F25612.h"
+
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+ #define KV31F51212_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F51212/fsl_clock_KV31F51212.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+ defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+ #define KV40F15_SERIES
+
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+ #define KV43F15_SERIES
+
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+ #define KV44F15_SERIES
+
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+ defined(CPU_MKV45F256VLL15))
+
+ #define KV45F15_SERIES
+
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+ defined(CPU_MKV46F256VLL15))
+
+ #define KV46F15_SERIES
+
+#else
+ #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_CLOCK_MANAGER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,952 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_ENET_DRIVER_H__
+#define __FSL_ENET_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_enet_hal.h"
+#include "fsl_os_abstraction.h"
+
+#ifndef MBED_NO_ENET
+
+/*!
+ * @addtogroup enet_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+
+ ******************************************************************************/
+/*! @brief Defines the approach: ENET interrupt handler do receive */
+#define ENET_RECEIVE_ALL_INTERRUPT 0
+
+/*! @brief Defines the statistic enable macro.*/
+#define ENET_ENABLE_DETAIL_STATS 0
+
+/*! @brief Defines the alignment operation.*/
+#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1)))
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*! @brief Defines the PTP IOCTL macro.*/
+typedef enum _enet_ptp_ioctl
+{
+ kEnetPtpGetRxTimestamp = 0, /*!< ENET PTP gets receive timestamp*/
+ kEnetPtpGetTxTimestamp, /*!< ENET PTP gets transmit timestamp*/
+ kEnetPtpGetCurrentTime, /*!< ENET PTP gets current time*/
+ kEnetPtpSetCurrentTime, /*!< ENET PTP sets current time*/
+ kEnetPtpFlushTimestamp, /*!< ENET PTP flushes timestamp*/
+ kEnetPtpCorrectTime, /*!< ENET PTP time correction*/
+ kEnetPtpSendEthernetPtpV2, /*!< ENET PTPv2 sends Ethernet frame*/
+ kEnetPtpReceiveEthernetPtpV2 /*!< ENET PTPv2 receives with Ethernet frame*/
+} enet_ptp_ioctl_t;
+
+/*! @brief Defines the PTP message buffer number.*/
+typedef enum _enet_ptp_buffer_number
+{
+ kEnetPtpL2bufferNumber = 10, /*!< PTP layer2 frame buffer number*/
+ kEnetPtpRingNumber = 25 /*!< PTP Ring buffer number*/
+} enet_ptp_buffer_number_t;
+
+/*! @brief Defines the ENET PTP message related constant.*/
+typedef enum _enet_ptp_event_type
+{
+ kEnetPtpSourcePortIdLen = 10, /*!< PTP message sequence id length*/
+ kEnetPtpEventMsgType = 3, /*!< PTP event message type*/
+ kEnetPtpEventPort = 319, /*!< PTP event port number*/
+ kEnetPtpGnrlPort = 320 /*!< PTP general port number*/
+} enet_ptp_event_type_t;
+
+/*! @brief Defines all ENET PTP content offsets in the IPv4 PTP UDP/IP multicast message.*/
+typedef enum _enet_ipv4_ptp_content_offset
+{
+ kEnetPtpIpVersionOffset = 0xe, /*!< IPv4 PTP message IP version offset*/
+ kEnetPtpUdpProtocolOffset = 0x17,/*!< IPv4 PTP message UDP protocol offset*/
+ kEnetPtpUdpPortOffset = 0x24, /*!< IPv4 PTP message UDP port offset*/
+ kEnetPtpUdpMsgTypeOffset = 0x2a, /*!< IPv4 PTP message UDP message type offset*/
+ kEnetPtpUdpVersionoffset = 0x2b, /*!< IPv4 PTP message UDP version offset*/
+ kEnetPtpUdpClockIdOffset = 0x3e, /*!< IPv4 PTP message UDP clock id offset*/
+ kEnetPtpUdpSequenIdOffset = 0x48,/*!< IPv4 PTP message UDP sequence id offset*/
+ kEnetPtpUdpCtlOffset = 0x4a /*!< IPv4 PTP message UDP control offset*/
+} enet_ipv4_ptp_content_offset_t;
+
+/*! @brief Defines all ENET PTP content offset in THE IPv6 PTP UDP/IP multicast message.*/
+typedef enum _enet_ipv6_ptp_content_offset
+{
+ kEnetPtpIpv6UdpProtocolOffset = 0x14, /*!< IPv6 PTP message UDP protocol offset*/
+ kEnetPtpIpv6UdpPortOffset = 0x38, /*!< IPv6 PTP message UDP port offset*/
+ kEnetPtpIpv6UdpMsgTypeOffset = 0x3e, /*!< IPv6 PTP message UDP message type offset*/
+ kEnetPtpIpv6UdpVersionOffset = 0x3f, /*!< IPv6 PTP message UDP version offset*/
+ kEnetPtpIpv6UdpClockIdOffset = 0x52, /*!< IPv6 PTP message UDP clock id offset*/
+ kEnetPtpIpv6UdpSequenceIdOffset = 0x5c,/*!< IPv6 PTP message UDP sequence id offset*/
+ kEnetPtpIpv6UdpCtlOffset = 0x5e /*!< IPv6 PTP message UDP control offset*/
+} enet_ipv6_ptp_content_offset_t;
+
+/*! @brief Defines all ENET PTP content offset in the PTP Layer2 Ethernet message.*/
+typedef enum _enet_ethernet_ptp_content_offset
+{
+ kEnetPtpEtherPktTypeOffset = 0x0c, /*!< PTPv2 message Ethernet packet type offset*/
+ kEnetPtpEtherMsgTypeOffset = 0x0e, /*!< PTPv2 message Ethernet message type offset*/
+ kEnetPtpEtherVersionOffset = 0x0f, /*!< PTPv2 message Ethernet version type offset*/
+ kEnetPtpEtherClockIdOffset = 0x22, /*!< PTPv2 message Ethernet clock id offset*/
+ kEnetPtpEtherSequenceIdOffset = 0x2c,/*!< PTPv2 message Ethernet sequence id offset*/
+ kEnetPtpEtherCtlOffset = 0x2e /*!< PTPv2 message Ethernet control offset*/
+} enet_ethernet_ptp_content_offset_t;
+
+/*! @brief Defines the 1588 timer parameters.*/
+typedef enum _enet_ptp_timer_wrap_period
+{
+ kEnetPtpAtperVaule = 1000000000, /*!< PTP timer wrap around one second */
+ kEnetBaseIncreaseUnit = 2 /*!< PTP timer adjusts clock and increases value to 2*/
+} enet_ptp_timer_wrap_period_t;
+#endif
+
+/*! @brief Defines the interrupt source index for the interrupt vector change table.*/
+typedef enum _enet_interrupt_number
+{
+ kEnetTstimerInt = 0, /*!< Timestamp interrupt*/
+ kEnetTsAvailInt, /*!< TS-avail interrupt*/
+ kEnetWakeUpInt, /*!< Wakeup interrupt*/
+ kEnetPlrInt, /*!< Plr interrupt*/
+ kEnetUnInt, /*!< Un interrupt*/
+ kEnetRlInt, /*!< RL interrupt*/
+ kEnetLcInt, /*!< LC interrupt*/
+ kEnetEberrInt, /*!< Eberr interrupt*/
+ kEnetMiiInt, /*!< MII interrupt*/
+ kEnetRxbInt , /*!< Receive byte interrupt*/
+ kEnetRxfInt, /*!< Receive frame interrupt*/
+ kEnetTxbInt, /*!< Transmit byte interrupt*/
+ kEnetTxfInt, /*!< Transmit frame interrupt*/
+ kEnetGraInt, /*!< Gra interrupt*/
+ kEnetBabtInt, /*!< Babt interrupt*/
+ kEnetBabrInt, /*!< Babr interrupt*/
+ kEnetIntNum /*!< Interrupt number*/
+} enet_interrupt_number_t;
+
+/*! @brief Defines the ENET main constant.*/
+typedef enum _enet_frame_max
+{
+ kEnetMaxTimeout = 0x10000, /*!< Maximum timeout*/
+ kEnetMaxFrameSize = 1518, /*!< Maximum frame size*/
+ kEnetMaxFrameVlanSize = 1522, /*!< Maximum VLAN frame size*/
+ kEnetMaxFrameDateSize = 1500, /*!< Maximum frame data size*/
+ kEnetMaxFrameBdNumbers = 7, /*!< Maximum buffer descriptor numbers of a frame*/
+ kEnetFrameFcsLen = 4, /*!< FCS length*/
+ kEnetEthernetHeadLen = 14 /*!< Ethernet Frame header length*/
+} enet_frame_max_t;
+
+/*! @brief Defines the CRC data for a hash value calculation.*/
+typedef enum _enet_crc_parameter
+{
+ kEnetCrcData = 0xFFFFFFFFU, /*!< CRC-32 maximum data */
+ kEnetCrcOffset = 8, /*!< CRC-32 offset2*/
+ kEnetCrcMask1 = 0x3F /*!< CRC-32 mask*/
+} enet_crc_parameter_t;
+
+/*! @brief Defines the ENET protocol type and main parameters.*/
+typedef enum _enet_protocol_type
+{
+ kEnetProtocolIeee8023 = 0x88F7, /*!< Packet type Ethernet ieee802.3*/
+ kEnetProtocolIpv4 = 0x0800, /*!< Packet type IPv4*/
+ kEnetProtocolIpv6 = 0x86dd, /*!< Packet type IPv6*/
+ kEnetProtocol8021QVlan = 0x8100, /*!< Packet type VLAN*/
+ kEnetPacketUdpVersion = 0x11, /*!< UDP protocol type*/
+ kEnetPacketIpv4Version = 0x4, /*!< Packet IP version IPv4*/
+ kEnetPacketIpv6Version = 0x6 /*!< Packet IP version IPv6*/
+} enet_protocol_type_t;
+
+/*! @brief Defines the ENET MAC control Configure*/
+typedef enum _enet_mac_control_flag
+{
+ kEnetSleepModeEnable = 0x1, /*!< ENET control sleep mode Enable*/
+ kEnetPayloadlenCheckEnable = 0x2, /*!< ENET receive payload length check Enable*/
+ kEnetRxFlowControlEnable = 0x4, /*!< ENET flow control, receiver detects PAUSE frames and stops transmitting data when a PAUSE frame is detected*/
+ kEnetRxCrcFwdEnable = 0x8, /*!< Received frame crc is stripped from the frame*/
+ kEnetRxPauseFwdEnable = 0x10,/*!< Pause frames are forwarded to the user application*/
+ kEnetRxPadRemoveEnable = 0x20, /*!< Padding is removed from received frames*/
+ kEnetRxBcRejectEnable = 0x40, /*!< Broadcast frame reject*/
+ kEnetRxPromiscuousEnable = 0x80, /*!< Promiscuous mode enabled*/
+ kEnetRxMiiLoopback = 0x100, /*!< MAC MII loopback mode*/
+} enet_mac_control_flag_t;
+
+/*! @brief Defines the multicast group structure for the ENET device. */
+typedef struct ENETMulticastGroup
+{
+ enetMacAddr groupAdddr; /*!< Multicast group address*/
+ uint32_t hash; /*!< Hash value of the multicast group address*/
+ struct ENETMulticastGroup *next; /*!< Pointer of the next group structure*/
+ struct ENETMulticastGroup *prv; /*!< Pointer of the previous structure*/
+} enet_multicast_group_t;
+
+/*! @brief Defines the receive buffer descriptor configure structure.*/
+typedef struct ENETRxBdConfig
+{
+ uint8_t *rxBdPtrAlign; /*!< Aligned receive buffer descriptor pointer */
+ uint8_t *rxBufferAlign; /*!< Aligned receive data buffer pointer */
+ uint8_t *rxLargeBufferAlign; /*!< Aligned receive large data buffer pointer*/
+ uint8_t rxBdNum; /*!< Aligned receive buffer descriptor pointer*/
+ uint8_t rxBufferNum; /*!< Receive buffer number*/
+ uint8_t rxLargeBufferNum; /*!< Large receive buffer number*/
+ uint32_t rxLargeBufferSizeAlign; /*!< Aligned large receive buffer size*/
+}enet_rxbd_config_t;
+
+/*! @brief Defines the transmit buffer descriptor configure structure.*/
+typedef struct ENETTxBdConfig
+{
+ uint8_t *txBdPtrAlign; /*!< Aligned transmit buffer descriptor pointer*/
+ uint8_t *txBufferAlign; /*!< Aligned transmit buffer descriptor pointer*/
+ uint8_t txBufferNum; /*!< Transmit buffer number*/
+ uint32_t txBufferSizeAlign; /*!< Aligned transmit buffer size*/
+}enet_txbd_config_t;
+
+/*! @brief Defines the basic configuration structure for the ENET device.*/
+typedef struct ENETMacConfig
+{
+ uint16_t rxBufferSize; /*!< Receive buffer size*/
+ uint16_t rxLargeBufferNumber; /*!< Receive large buffer number; Needed only when the BD size is smaller than the maximum frame length.*/
+ uint16_t rxBdNumber; /*!< Receive buffer descriptor number*/
+ uint16_t txBdNumber; /*!< Transmit buffer descriptor number*/
+ enetMacAddr macAddr; /*!< MAC hardware address*/
+ enet_config_rmii_t rmiiCfgMode;/*!< RMII configure mode*/
+ enet_config_speed_t speed; /*!< Speed configuration*/
+ enet_config_duplex_t duplex; /*!< Duplex configuration*/
+ /*!< Mac control configure, it is recommended to use enet_mac_control_flag_t
+ it is special control set for loop mode, sleep mode, crc forward/terminate etc*/
+ uint32_t macCtlConfigure;
+ bool isTxAccelEnabled;/*!< Switcher to enable transmit accelerator*/
+ bool isRxAccelEnabled;/*!< Switcher to enable receive accelerator*/
+ bool isStoreAndFwEnabled; /*!< Switcher to enable store and forward*/
+ enet_config_rx_accelerator_t rxAcceler; /*!< Receive accelerator configure*/
+ enet_config_tx_accelerator_t txAcceler; /*!< Transmit accelerator configure*/
+ bool isVlanEnabled; /*!< Switcher to enable VLAN frame*/
+ bool isPhyAutoDiscover;/*!< Switcher to use PHY auto discover*/
+ uint32_t miiClock; /*!< MII speed*/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+ uint16_t ptpRingBufferNumber; /*!< PTP ring buffer number*/
+ bool isSlaveModeEnabled; /*!< PTP timer configuration*/
+#endif
+} enet_mac_config_t;
+
+/*! @brief Defines the basic configuration for PHY.*/
+typedef struct ENETPhyConfig
+{
+ uint8_t phyAddr; /*!< PHY address*/
+ bool isLoopEnabled; /*!< Switcher to enable the HY loop mode*/
+} enet_phy_config_t;
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*! @brief Defines the ENET Mac PTP timestamp structure.*/
+typedef struct ENETMacPtpTime
+{
+ uint64_t second; /*!< Second*/
+ uint32_t nanosecond; /*!< Nanosecond*/
+} enet_mac_ptp_time_t;
+
+/*! @brief Defines the ENET PTP timer drift structure.*/
+typedef struct ENETPtpDrift
+{
+ int32_t drift; /*!< Drift for the PTP timer to adjust*/
+} enet_ptp_drift_t;
+
+/*! @brief Defines the ENET MAC PTP time parameter.*/
+typedef struct ENETPtpMasterTimeData
+{
+ uint8_t masterPtpInstance;/*!< PTP master timer instance*/
+ uint64_t second; /*!< PTP master timer second */
+} enet_ptp_master_time_data_t;
+
+/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/
+typedef struct ENETMacPtpTsData
+{
+ uint8_t version; /*!< PTP version*/
+ uint8_t sourcePortId[kEnetPtpSourcePortIdLen];/*!< PTP source port ID*/
+ uint16_t sequenceId; /*!< PTP sequence ID*/
+ uint8_t messageType; /*!< PTP message type*/
+ enet_mac_ptp_time_t timeStamp;/*!< PTP timestamp*/
+} enet_mac_ptp_ts_data_t;
+
+/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/
+typedef struct ENETMacPtpTsRing
+{
+ uint32_t front; /*!< The first index of the ring*/
+ uint32_t end; /*!< The end index of the ring*/
+ uint32_t size; /*!< The size of the ring*/
+ enet_mac_ptp_ts_data_t *ptpTsDataPtr;/*!< PTP message data structure*/
+} enet_mac_ptp_ts_ring_t;
+
+/*! @brief Defines the ENET packet for the PTP version2 message using the layer2 Ethernet frame.*/
+typedef struct ENETPtpL2packet
+{
+ uint8_t packet[kEnetMaxFrameDateSize]; /*!< Buffer for ptpv2 message*/
+ uint16_t length; /*!< PTP message length*/
+} enet_ptp_l2packet_t;
+
+/*! @brief Defines the ENET PTPv2 packet queue using the layer2 Ethernet frame.*/
+typedef struct ENETPtpL2queue
+{
+ enet_ptp_l2packet_t l2Packet[kEnetPtpL2bufferNumber]; /*!< PTP layer2 packet*/
+ uint16_t writeIdex; /*!< Queue write index*/
+ uint16_t readIdx; /*!< Queue read index*/
+} enet_ptp_l2queue_t;
+
+/*! @brief Defines the ENET PTP layer2 Ethernet frame structure.*/
+typedef struct ENETPtpL2Ethernet
+{
+ uint8_t *ptpMsg; /*!< PTP message*/
+ uint16_t length; /*!< Length of the PTP message*/
+ enetMacAddr hwAddr; /*!< Destination hardware address*/
+} enet_ptp_l2_ethernet_t;
+
+/*! @brief Defines the ENET PTP buffer structure for all 1588 data.*/
+typedef struct ENETPrivatePtpBuffer
+{
+ enet_mac_ptp_ts_ring_t rxTimeStamp;/*!< Data structure for receive message*/
+ enet_mac_ptp_ts_ring_t txTimeStamp;/*!< Data structure for transmit timestamp*/
+ enet_ptp_l2queue_t *l2QueuePtr; /*!< Data structure for layer2 Ethernet queue*/
+ uint64_t masterSecond; /*!< PTP time second when it's master time*/
+} enet_private_ptp_buffer_t;
+#endif
+
+/*! @brief Defines the ENET header structure. */
+typedef struct ENETEthernetHeader
+{
+ enetMacAddr destAddr; /*!< Destination address */
+ enetMacAddr sourceAddr;/*!< Source address*/
+ uint16_t type; /*!< Protocol type*/
+} enet_ethernet_header_t;
+
+/*! @brief Defines the ENET VLAN frame header structure. */
+typedef struct ENET8021vlanHeader
+{
+ enetMacAddr destAddr; /*!< Destination address */
+ enetMacAddr sourceAddr;/*!< Source address*/
+ uint16_t tpidtag; /*!< ENET 8021tag header tag region*/
+ uint16_t othertag; /*!< ENET 8021tag header type region*/
+ uint16_t type; /*!< Protocol type*/
+} enet_8021vlan_header_t;
+
+/*! @brief Defines the ENET MAC context structure for the buffer address, buffer descriptor address, etc.*/
+typedef struct ENETMacContext
+{
+ uint8_t *rxBufferPtr; /*!< Receive buffer pointer*/
+ uint8_t *rxLargeBufferPtr; /*!< Receive large buffer descriptor*/
+ uint8_t *txBufferPtr; /*!< Transmit buffer pointer*/
+ uint8_t *rxBdBasePtr; /*!< Receive buffer descriptor base address pointer*/
+ uint8_t *rxBdCurPtr; /*!< Current receive buffer descriptor pointer*/
+ uint8_t *rxBdDirtyPtr; /*!< Receive dirty buffer descriptor*/
+ uint8_t *txBdBasePtr; /*!< Transmit buffer descriptor base address pointer*/
+ uint8_t *txBdCurPtr; /*!< Current transmit buffer descriptor pointer*/
+ uint8_t *txBdDirtyPtr; /*!< Last cleaned transmit buffer descriptor pointer*/
+ bool isTxFull; /*!< Transmit buffer descriptor full*/
+ bool isRxFull; /*!< Receive buffer descriptor full*/
+ uint32_t bufferdescSize; /*!< ENET buffer descriptor size*/
+ uint16_t rxBufferSizeAligned; /*!< Receive buffer alignment size*/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+ enet_private_ptp_buffer_t privatePtp;/*!< PTP private buffer*/
+#endif
+} enet_mac_context_t;
+
+/*! @brief Defines the ENET packets statistic structure.*/
+typedef struct ENETMacStats
+{
+ uint32_t statsRxTotal; /*!< Total number of receive packets*/
+ uint32_t statsRxMissed; /*!< Total number of receive packets*/
+ uint32_t statsRxDiscard; /*!< Receive discarded with error */
+ uint32_t statsRxError; /*!< Receive discarded with error packets*/
+ uint32_t statsTxTotal; /*!< Total number of transmit packets*/
+ uint32_t statsTxMissed; /*!< Transmit missed*/
+ uint32_t statsTxDiscard; /*!< Transmit discarded with error */
+ uint32_t statsTxError; /*!< Transmit error*/
+ uint32_t statsRxAlign; /*!< Receive non-octet alignment*/
+ uint32_t statsRxFcs; /*!< Receive CRC error*/
+ uint32_t statsRxTruncate;/*!< Receive truncate*/
+ uint32_t statsRxLengthGreater; /*!< Receive length greater than RCR[MAX_FL] */
+ uint32_t statsRxCollision; /*!< Receive collision*/
+ uint32_t statsRxOverRun; /*!< Receive over run*/
+ uint32_t statsTxOverFlow; /*!< Transmit overflow*/
+ uint32_t statsTxLateCollision; /*!< Transmit late collision*/
+ uint32_t statsTxExcessCollision;/*!< Transmit excess collision*/
+ uint32_t statsTxUnderFlow; /*!< Transmit under flow*/
+ uint32_t statsTxLarge; /*!< Transmit large packet*/
+ uint32_t statsTxSmall; /*!< Transmit small packet*/
+} enet_stats_t;
+
+/*! @brief Defines the ENET MAC packet buffer structure.*/
+typedef struct ENETMacPacketBuffer
+{
+ uint8_t *data;
+ uint16_t length;
+} enet_mac_packet_buffer_t;
+
+#if ENET_RECEIVE_ALL_INTERRUPT
+typedef uint32_t (* enet_netif_callback_t)(void *enetPtr, enet_mac_packet_buffer_t *packetBuffer);
+#endif
+
+/*! @brief Defines the ENET device data structure for the ENET.*/
+typedef struct ENETDevIf
+{
+ struct ENETDevIf *next; /*!< Next device structure address*/
+ void *netIfPtr; /*!< Store the connected upper layer in the structure*/
+#if ENET_RECEIVE_ALL_INTERRUPT
+ void *enetNetifService; /*!< Service function*/
+#endif
+ enet_multicast_group_t *multiGroupPtr; /*!< Multicast group chain*/
+ uint32_t deviceNumber; /*!< Device number*/
+ bool isInitialized; /*!< Device initialized*/
+ uint16_t maxFrameSize; /*!< MAC maximum frame size*/
+ enet_mac_config_t *macCfgPtr;/*!< MAC configuration structure*/
+ enet_phy_config_t *phyCfgPtr;/*!< PHY configuration structure*/
+ const struct ENETMacApi *macApiPtr; /*!< MAC application interface structure*/
+ void *phyApiPtr; /*!< PHY application interface structure*/
+ enet_mac_context_t *macContextPtr; /*!< MAC context pointer*/
+#if ENET_ENABLE_DETAIL_STATS
+ enet_stats_t stats; /*!< Packets statistic*/
+#endif
+#if ENET_RECEIVE_ALL_INTERRUPT
+ enet_netif_callback_t enetNetifcall; /*!< Receive callback function to the upper layer*/
+#else
+ event_object_t enetReceiveSync; /*!< Receive sync signal*/
+#endif
+ lock_object_t enetContextSync; /*!< Sync signal*/
+} enet_dev_if_t;
+
+/*! @brief Defines the basic application for the ENET device.*/
+typedef struct ENETMacApi
+{
+ uint32_t (* enet_mac_init)(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg, enet_txbd_config_t *txbdCfg);/*!< MAC initialize interface*/
+ uint32_t (* enet_mac_deinit)(enet_dev_if_t * enetIfPtr);/*!< MAC close interface*/
+ uint32_t (* enet_mac_send)(enet_dev_if_t * enetIfPtr, uint8_t *packet, uint32_t size);/*!< MAC send packets*/
+#if !ENET_RECEIVE_ALL_INTERRUPT
+ uint32_t (* enet_mac_receive)(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer);/*!< MAC receive interface*/
+#endif
+ uint32_t (* enet_mii_read)(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);/*!< MII reads PHY*/
+ uint32_t (* enet_mii_write)(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t data);/*!< MII writes PHY*/
+ uint32_t (* enet_add_multicast_group)(uint32_t instance, enet_multicast_group_t *multiGroupPtr, uint8_t *groupAddr);/*!< Add multicast group*/
+ uint32_t (* enet_leave_multicast_group)(uint32_t instance, enet_multicast_group_t *multiGroupPtr, uint8_t *groupAddr);/*!< Leave multicast group*/
+} enet_mac_api_t;
+
+/*******************************************************************
+* Global variables
+
+***********************************************************************/
+extern const enet_mac_api_t g_enetMacApi;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name ENET Driver
+ * @{
+ */
+
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*!
+ * @brief Initializes the ENET PTP context structure with the basic configuration.
+ *
+ * @param macContextPtr The pointer to the ENET MAC macContext structure.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_init(enet_private_ptp_buffer_t *privatePtpPtr, uint32_t ptpRxBufferNum, enet_mac_ptp_ts_data_t *ptpTsRxDataPtr, uint32_t ptpTxBufferNum, enet_mac_ptp_ts_data_t *ptpTsTxDataPtr);
+
+/*!
+ * @brief Initializes the ENET PTP timer with the basic configuration.
+ *
+ * After the PTP starts, the 1588 timer also starts running. If the user wants the 1588 timer
+ * as the slave, enable the isSlaveEnabled flag.
+ *
+ * @param instance The ENET instance number.
+ * @param ptpCfgPtr The pointer to the basic PTP timer configuration structure.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_start(uint32_t instance, bool isSlaveEnabled);
+
+/*!
+ * @brief Parses the ENET packet.
+ *
+ * Parses the ENET message and checks if it is a PTP message. If it is a PTP message,
+ * the message is stored in the PTP information structure. Message parsing
+ * decides whether timestamp processing is done after that.
+ *
+ * @param packet The ENET packet.
+ * @param ptpTsPtr The pointer to the PTP data structure.
+ * @param isPtpMsg The PTP message flag.
+ * @param isFastEnabled The fast operation flag. If set, only check if it is a ptp message
+ * and doesn't store any ptp message.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_parse(uint8_t *packet, enet_mac_ptp_ts_data_t *ptpTsPtr, bool *isPtpMsg, bool isFastEnabled);
+
+/*!
+ * @brief Gets the current value of the ENET PTP time.
+ *
+ * @param ptpTimerPtr The PTP timer structure.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_get_time(enet_mac_ptp_time_t *ptpTimerPtr);
+
+/*!
+ * @brief Sets the current value of the ENET PTP time.
+ *
+ * @param ptpTimerPtr The PTP timer structure.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_set_time(enet_mac_ptp_time_t *ptpTimerPtr);
+
+/*!
+ * @brief Adjusts the ENET PTP time.
+ *
+ * @param instance The ENET instance number.
+ * @param drift The PTP timer drift value.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_correction_time(uint32_t instance, int32_t drift);
+
+
+/*!
+ * @brief Stores the transmit timestamp.
+ *
+ * @param ptpBuffer The PTP buffer pointer.
+ * @param bdPtr The current transmit buffer descriptor.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_store_tx_timestamp(enet_private_ptp_buffer_t *ptpBuffer,void *bdPtr);
+
+/*!
+ * @brief Stores receive timestamp.
+ *
+ * @param ptpBuffer The PTP buffer pointer.
+ * @param packet The current receive packet.
+ * @param bdPtr The current receive buffer descriptor.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_store_rx_timestamp(enet_private_ptp_buffer_t *ptpBuffer, uint8_t *packet, void *bdPtr);
+
+/*!
+ * @brief Initializes the buffer queue for the PTP layer2 Ethernet packets.
+ *
+ * @param ptpBuffer The PTP buffer pointer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_l2queue_init(enet_private_ptp_buffer_t *ptpBuffer, enet_ptp_l2queue_t *ptpL2QuePtr);
+
+/*!
+ * @brief Adds the PTP layer2 Ethernet packet to the PTP Ethernet packet queue.
+ *
+ * @param ptpQuePtr The ENET private ptp layer2 buffer queue structure pointer.
+ * @param packet The packet buffer pointer.
+ * @param length The packet length.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_service_l2packet(enet_ptp_l2queue_t * ptpQuePtr, uint8_t *packet, uint16_t length);
+
+/*!
+ * @brief Sends the PTP layer2 Ethernet packet to the Net.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param paramPtr The buffer from upper layer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_send_l2packet(enet_dev_if_t * enetIfPtr, void *paramPtr);
+
+/*!
+ * @brief Receives the PTP layer2 Ethernet packet from the Net.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param paramPtr The buffer receive from net and will send to upper layer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_receive_l2packet(enet_dev_if_t * enetIfPtr,void *paramPtr);
+
+/*!
+ * @brief Provides the handler for the 1588 stack to do PTP IOCTL.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param commandId The command id.
+ * @param inOutPtr The data buffer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_ioctl(enet_dev_if_t * enetIfPtr, uint32_t commandId, void *inOutPtr);
+
+/*!
+ * @brief Stops the ENET PTP timer.
+ *
+ * @param instance The ENET instance number.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_stop(uint32_t instance);
+
+/*!
+ * @brief Checks whether the PTP ring buffer is full.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @return True if the PTP ring buffer is full. Otherwise, false.
+ */
+bool enet_ptp_ring_is_full(enet_mac_ptp_ts_ring_t *ptpTsRingPtr);
+
+/*!
+ * @brief Updates the latest ring buffers.
+ *
+ * Adds the PTP message data to the PTP ring buffers and increases the
+ * PTP ring buffer index.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @param data The PTP data buffer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_ring_update(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data);
+
+/*!
+ * @brief Searches the element in ring buffers with the message ID and Clock ID.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @param data The PTP data buffer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_ring_search(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data);
+
+/*!
+ * @brief Calculates the ENET PTP ring buffer index.
+ *
+ * @param size The ring size.
+ * @param curIdx The current ring index.
+ * @param offset The offset index.
+ * @return The execution status.
+ */
+static inline uint32_t enet_ptp_ring_index(uint32_t size, uint32_t curIdx, uint32_t offset)
+{
+ return ((curIdx + offset) % size);
+}
+
+/*!
+ * @brief Frees all ring buffers.
+ *
+ * @param enetContextPtr The ENET MAC context buffer.
+ * @return The execution status.
+ */
+uint32_t enet_ptp_deinit(enet_mac_context_t *enetContextPtr);
+
+/*!
+ * @brief The ENET PTP time interrupt handler.
+ *
+ * @param enetIfPtr The ENET context structure pointer.
+ */
+void enet_mac_ts_isr(void *enetIfPtr);
+#endif
+/*!
+ * @brief(R)MII Read function.
+ *
+ * @param instance The ENET instance number.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param dataPtr The data read from MII.
+ * @return The execution status.
+ */
+uint32_t enet_mii_read(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
+
+/*!
+ * @brief(R)MII Read function.
+ *
+ * @param instance The ENET instance number.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param data The data write to MII.
+ * @return The execution status.
+ */
+uint32_t enet_mii_write(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/*!
+ * @brief Initializes ENET buffer descriptors.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_bd_init(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Initializes the ENET MAC MII(MDC/MDIO) interface.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_mii_init(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Initialize the ENET receive buffer descriptors.
+ *
+ * If you open ENET_RECEIVE_ALL_INTERRUPT to do receive
+ * data buffer numbers can be the same as the receive descriptor numbers.
+ * But if you close ENET_RECEIVE_ALL_INTERRUPT and choose polling receive
+ * frames please make sure the receive data buffers are more than
+ * buffer descriptor numbers to guarantee a good performance.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param rxbdCfg The receive buffer descriptor configuration.
+ * @return The execution status.
+ */
+uint32_t enet_mac_rxbd_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg);
+
+/*!
+ * @brief Deinitialize the ENET receive buffer descriptors.
+ *
+ * Deinitialize the ENET receive buffer descriptors.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+
+uint32_t enet_mac_rxbd_deinit(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Initialize the ENET transmit buffer descriptors.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param txbdCfg The transmit buffer descriptor configuration.
+ * @return The execution status.
+ */
+uint32_t enet_mac_txbd_init(enet_dev_if_t * enetIfPtr, enet_txbd_config_t *txbdCfg);
+
+/*!
+ * @brief Deinitialize the ENET transmit buffer descriptors.
+ *
+ * Deinitialize the ENET transmit buffer descriptors.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_txbd_deinit(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Initializes ENET MAC FIFO and accelerator with the basic configuration.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_configure_fifo_accel(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief the ENET controller with the basic configuration.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_configure_controller(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Deinit the ENET device.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_deinit(enet_dev_if_t * enetIfPtr);
+
+#if !ENET_RECEIVE_ALL_INTERRUPT
+/*!
+ * @brief Updates the receive buffer descriptor.
+ *
+ * This updates the used receive buffer descriptor ring to
+ * ensure that the used BDS is correctly used again. It cleans
+ * the status region and sets the control region of the used receive buffer
+ * descriptor. If the isBufferUpdate flag is set, the data buffer in the
+ * buffer descriptor is updated.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param isBufferUpdate The data buffer update flag.
+ * @return The execution status.
+ */
+uint32_t enet_mac_update_rxbd(enet_dev_if_t * enetIfPtr, bool isBufferUpdate);
+#else
+/*!
+ * @brief Updates the receive buffer descriptor.
+ *
+ * Clears the status region and sets the control region of the current receive buffer
+ * descriptor to ensure that it is used correctly again. It increases the buffer
+ * descriptor index to the next buffer descriptor.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_update_rxbd(enet_dev_if_t * enetIfPtr);
+#endif
+/*!
+ * @brief Processes the ENET receive frame error statistics.
+ *
+ * This interface gets the error statistics of the received frame.
+ * Because the error information is in the last BD of a frame, this interface
+ * should be called when processing the last BD of a frame.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param data The current control and status data of the buffer descriptor.
+ * @return The frame error status.
+ * - True if the frame has an error.
+ * - False if the frame does not have an error.
+ */
+bool enet_mac_rx_error_stats(enet_dev_if_t * enetIfPtr, uint32_t data);
+
+/*!
+ * @brief Processes the ENET transmit frame statistics.
+ *
+ * This interface gets the error statistics of the transmit frame.
+ * Because the error information is in the last BD of a frame, this interface
+ * should be called when processing the last BD of a frame.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param curBd The current buffer descriptor.
+ */
+void enet_mac_tx_error_stats(enet_dev_if_t * enetIfPtr,void *curBd);
+
+/*!
+ * @brief ENET transmit buffer descriptor cleanup.
+ *
+ * First, store the transmit frame error statistic and PTP timestamp of the transmitted packets.
+ * Second, clean up the used transmit buffer descriptors.
+ * If the PTP 1588 feature is open, this interface captures the 1588 timestamp.
+ * It is called by the transmit interrupt handler.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_tx_cleanup(enet_dev_if_t * enetIfPtr);
+#if !ENET_RECEIVE_ALL_INTERRUPT
+/*!
+ * @brief Receives ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param packBuffer The received data buffer.
+ * @return The execution status.
+ */
+uint32_t enet_mac_receive(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer);
+#else
+/*!
+ * @brief Receives ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_receive(enet_dev_if_t * enetIfPtr);
+#endif
+/*!
+ * @brief Transmits ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param packet The frame to be transmitted.
+ * @param size The frame size.
+ * @return The execution status.
+ */
+uint32_t enet_mac_send(enet_dev_if_t * enetIfPtr, uint8_t *packet, uint32_t size);
+
+/*!
+ * @brief The ENET receive interrupt handler.
+ *
+ * @param enetIfPtr The ENET context structure pointer.
+ */
+void enet_mac_rx_isr(void *enetIfPtr);
+
+/*!
+ * @brief The ENET transmit interrupt handler.
+ *
+ * @param enetIfPtr The ENET context structure pointer.
+ */
+void enet_mac_tx_isr(void *enetIfPtr);
+
+/*!
+ * @brief Calculates the CRC hash value.
+ *
+ * @param address The ENET MAC hardware address.
+ * @param crcVlaue The calculated CRC value of the Mac address.
+ */
+void enet_mac_calculate_crc32(enetMacAddr address, uint32_t *crcValue);
+
+/*!
+ * @brief Adds the ENET device to a multicast group.
+ *
+ * @param instance The ENET instance number.
+ * @param multiGroupPtr The ENET multicast group structure.
+ * @param address The ENET MAC hardware address.
+ * @return The execution status.
+ */
+uint32_t enet_mac_add_multicast_group(uint32_t instance, enet_multicast_group_t *multiGroupPtr, enetMacAddr address);
+
+/*!
+ * @brief Moves the ENET device from a multicast group.
+ *
+ * @param instance The ENET instance number.
+ * @param multiGroupPtr The ENET multicast group structure.
+ * @param address The ENET MAC hardware address.
+ * @return The execution status.
+ */
+uint32_t enet_mac_leave_multicast_group(uint32_t instance, enet_multicast_group_t *multiGroupPtr, enetMacAddr address);
+
+/*!
+ * @brief Initializes the ENET with the basic configuration.
+ *
+ * @param enetIfPtr The pointer to the basic configuration structure.
+ * @return The execution status.
+ */
+uint32_t enet_mac_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg,
+ enet_txbd_config_t *txbdCfg);
+
+/*!
+ * @brief Enqueues a data buffer to the buffer queue.
+ *
+ * @param queue The buffer queue.
+ * @param buffer The buffer to add to the buffer queue.
+ */
+void enet_mac_enqueue_buffer( void **queue, void *buffer);
+
+/*!
+ * @brief Dequeues a buffer from the buffer queue.
+ *
+ * @param queue The buffer queue.
+ * @return The dequeued data buffer.
+ */
+void *enet_mac_dequeue_buffer( void **queue);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_ENET_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ENET_RTCS_ADAPTOR_H__
+#define __FSL_ENET_RTCS_ADAPTOR_H__
+
+#include "fsl_enet_hal.h"
+
+#ifndef MBED_NO_ENET
+
+#ifdef FSL_RTOS_MQX
+ #include "rtcs.h"
+ #include "pcb.h"
+#endif
+/*!
+ * @addtogroup enet_rtcs_adaptor
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Definitions of the task parameter*/
+#ifndef FSL_RTOS_MQX
+ extern unsigned long _RTCSTASK_priority;
+#endif
+#define ENET_RECEIVE_TASK_PRIO (1)
+#define ENET_TASK_STACK_SIZE (800)
+#define ENET_PCB_NUM (16)
+
+/*! @brief Definitions of the configuration parameter*/
+#define ENET_RXBD_NUM (8)
+#define ENET_TXBD_NUM (4)
+#define ENET_EXTRXBD_NUM (4)
+#define ENET_RXBuff_SIZE (kEnetMaxFrameSize)
+#define ENET_TXBuff_SIZE (kEnetMaxFrameSize)
+#define ENET_RXRTCSBUFF_NUM (8)
+#define ENET_RX_BUFFER_ALIGNMENT (16)
+#define ENET_TX_BUFFER_ALIGNMENT (16)
+#define ENET_BD_ALIGNMENT (16)
+#define ENET_RXBuffSizeAlign(n) ENET_ALIGN(n, ENET_RX_BUFFER_ALIGNMENT)
+#define ENET_TXBuffSizeAlign(n) ENET_ALIGN(n, ENET_TX_BUFFER_ALIGNMENT)
+#define ENET_MII_CLOCK (2500000L)
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+#define ENET_PTP_TXTS_RING_LEN (25)
+#define ENET_PTP_RXTS_RING_LEN (25)
+#endif
+
+/*! @brief Definitions of the error codes */
+#define ENET_OK (0)
+#define ENET_ERROR (0xff) /* General ENET error */
+
+#define ENETERR_INVALID_DEVICE (kStatus_ENET_InvalidDevice) /* Device number out of range */
+#define ENETERR_INIT_DEVICE (kStatus_ENET_Initialized) /* Device already initialized */
+
+/*! @brief Definitions of the ENET protocol parameter*/
+#define ENETPROT_IP 0x0800
+#define ENETPROT_ARP 0x0806
+#define ENETPROT_8021Q 0x8100
+#define ENETPROT_IP6 0x86DD
+#define ENETPROT_ETHERNET 0x88F7
+#define ENET_OPT_8023 0x0001
+#define ENET_OPT_8021QTAG 0x0002
+#define ENET_SETOPT_8021QPRIO(p) (ENET_OPT_8021QTAG | (((uint_32)(p) & 0x7) << 2))
+#define ENET_GETOPT_8021QPRIO(f) ((((unsigned int)f) >> 2) & 0x7)
+
+/*! @brief Definitions of the ENET option macro*/
+#define ENET_OPTION_HW_TX_IP_CHECKSUM 0x00001000
+#define ENET_OPTION_HW_TX_PROTOCOL_CHECKSUM 0x00002000
+#define ENET_OPTION_HW_RX_IP_CHECKSUM 0x00004000
+#define ENET_OPTION_HW_RX_PROTOCOL_CHECKSUM 0x00008000
+#define ENET_OPTION_HW_RX_MAC_ERR 0x00010000
+
+/*! @brief Definitions of the ENET default Mac*/
+#define ENET_DEFAULT_MAC_ADD { 0x00, 0x00, 0x5E, 0, 0, 0 }
+#define PCB_MINIMUM_SIZE (sizeof(PCB2))
+#define PCB_free(pcb_ptr) ((pcb_ptr)->FREE(pcb_ptr))
+
+/*! @brief Definitions of the macro for byte-swap*/
+#if SYSTEM_LITTLE_ENDIAN
+#define RTCS_HTONS(n) BSWAP_16(n)
+#define RTCS_HTONL(n) BSWAP_32(n)
+#define RTCS_NTOHS(n) BSWAP_16(n)
+#define RTCS_NTOHL(n) BSWAP_32(n)
+#else
+#define RTCS_HTONS(n) (n)
+#define RTCS_HTONL(n) (n)
+#define RTCS_NTOHS(n) (n)
+#define RTCS_NTOHL(n) (n)
+#endif
+
+#ifndef FSL_RTOS_MQX
+ #define htonl(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 24) & 0xFF, \
+ ((uint_8_ptr)(p))[1] = ((x) >> 16) & 0xFF, \
+ ((uint_8_ptr)(p))[2] = ((x) >> 8) & 0xFF, \
+ ((uint_8_ptr)(p))[3] = (x) & 0xFF, \
+ (x))
+
+#define htons(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 8) & 0xFF, \
+ ((uint_8_ptr)(p))[1] = (x) & 0xFF, \
+ (x))
+
+#define htonc(p,x) (((uint_8_ptr)(p))[0] = (x) & 0xFF, \
+ (x))
+
+#define ntohl(p) (\
+ (((uint_32)(((uint_8_ptr)(p))[0])) << 24) | \
+ (((uint_32)(((uint_8_ptr)(p))[1])) << 16) | \
+ (((uint_32)(((uint_8_ptr)(p))[2])) << 8) | \
+ ( (uint_32)(((uint_8_ptr)(p))[3])) \
+ )
+
+#define ntohs(p) (\
+ (((uint_16)(((uint_8_ptr)(p))[0])) << 8) | \
+ ( (uint_16)(((uint_8_ptr)(p))[1])) \
+ )
+
+#define ntohc(p) ((uint_8)(((uint_8_ptr)(p))[0]))
+#endif
+#define htone(p,x) ((p)[0] = (x)[0], \
+ (p)[1] = (x)[1], \
+ (p)[2] = (x)[2], \
+ (p)[3] = (x)[3], \
+ (p)[4] = (x)[4], \
+ (p)[5] = (x)[5] \
+ )
+
+#define ntohe(p,x) ((x)[0] = (p)[0] & 0xFF, \
+ (x)[1] = (p)[1] & 0xFF, \
+ (x)[2] = (p)[2] & 0xFF, \
+ (x)[3] = (p)[3] & 0xFF, \
+ (x)[4] = (p)[4] & 0xFF, \
+ (x)[5] = (p)[5] & 0xFF \
+ )
+
+/*! @brief Definitions of the add to queue*/
+#define QUEUEADD(head,tail,pcb) \
+ if ((head) == NULL) { \
+ (head) = (pcb); \
+ } else { \
+ (tail)->PRIVATE = (pcb); \
+ } \
+ (tail) = (pcb); \
+ (pcb)->PRIVATE = NULL
+
+/*! @brief Definitions of the get from queue*/
+#define QUEUEGET(head,tail,pcb) \
+ (pcb) = (head); \
+ if (head) { \
+ (head) = (head)->PRIVATE; \
+ if ((head) == NULL) { \
+ (tail) = NULL; \
+ } \
+ }
+
+/*! @brief Definition for ENET six-byte Mac type*/
+typedef unsigned char _enet_address[6];
+
+/*! @brief Definition of the IPCFG structure*/
+typedef void * _enet_handle;
+
+#ifndef FSL_RTOS_MQX
+ struct pcb;
+ typedef void (* PCB_FREE_FPTR)(struct pcb *);
+#endif
+
+/*! @brief Definition of the Ethernet packet header structure*/
+typedef struct enet_header
+{
+ _enet_address DEST; /*!< destination Mac address*/
+ _enet_address SOURCE; /*!< source Mac address*/
+ unsigned char TYPE[2]; /*!< protocol type*/
+} ENET_HEADER, * ENET_HEADER_PTR;
+
+#ifndef FSL_RTOS_MQX
+
+/*! @brief Definition of the fragment PCB structure*/
+typedef struct pcb_fragment
+{
+ uint32_t LENGTH; /*!< Packet fragment length*/
+ unsigned char *FRAGMENT; /*!< brief Pointer to fragment*/
+} PCB_FRAGMENT, * PCB_FRAGMENT_PTR;
+
+/*! @brief Definition of the PCB structure for the RTCS adaptor*/
+typedef struct pcb
+{
+ PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/
+ void *PRIVATE; /*!< Private PCB information*/
+ PCB_FRAGMENT FRAG[1]; /*!< Pointer to PCB fragment*/
+} PCB, * PCB_PTR;
+
+/*! @brief Definition of the two fragment PCB structure*/
+typedef struct pcb2
+{
+ PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/
+ void *PRIVATE; /*!< Private PCB information*/
+ PCB_FRAGMENT FRAG[2]; /*!< Pointers to two PCB fragments*/
+} PCB2, *PCB2_PTR;
+
+#endif
+
+/*! @brief Definition of the two fragment PCB structure*/
+typedef struct pcb_queue
+{
+ PCB *pcbHead; /*!< PCB buffer head*/
+ PCB *pcbTail; /*!< PCB buffer tail*/
+}pcb_queue;
+
+/*! @brief Definition of the ECB structure, which contains the protocol type and it's related service function*/
+typedef struct ENETEcbStruct
+{
+ uint16_t TYPE;
+ void (* SERVICE)(PCB_PTR, void *);
+ void *PRIVATE;
+ struct ENETEcbStruct *NEXT;
+} enet_ecb_struct_t;
+
+/*! @brief Definition of the 8022 header*/
+typedef struct enet_8022_header
+{
+ uint8_t dsap[1]; /*!< DSAP region*/
+ uint8_t ssap[1]; /*!< SSAP region*/
+ uint8_t command[1]; /*!< Command region*/
+ uint8_t oui[3]; /*!< OUI region*/
+ uint16_t type; /*!< type region*/
+}enet_8022_header_t, *enet_8022_header_ptr;
+
+/*! @brief Definition of the common status structure*/
+typedef struct enet_commom_stats_struct {
+ uint32_t ST_RX_TOTAL; /*!< Total number of received packets*/
+ uint32_t ST_RX_MISSED; /*!< Number of missed packets*/
+ uint32_t ST_RX_DISCARDED; /*!< Discarded a protocol that was not recognized*/
+ uint32_t ST_RX_ERRORS; /*!< Discarded error during reception*/
+ uint32_t ST_TX_TOTAL; /*!< Total number of transmitted packets*/
+ uint32_t ST_TX_MISSED; /*!< Discarded transmit ring full*/
+ uint32_t ST_TX_DISCARDED; /*!< Discarded bad packet*/
+ uint32_t ST_TX_ERRORS; /*!< Error during transmission*/
+} ENET_COMMON_STATS_STRUCT, * ENET_COMMON_STATS_STRUCT_PTR;
+
+typedef struct enet_stats {
+ ENET_COMMON_STATS_STRUCT COMMON; /*!< Common status structure*/
+ uint32_t ST_RX_ALIGN; /*!< Frame Alignment error*/
+ uint32_t ST_RX_FCS; /*!< CRC error */
+ uint32_t ST_RX_RUNT; /*!< Runt packet received */
+ uint32_t ST_RX_GIANT; /*!< Giant packet received*/
+ uint32_t ST_RX_LATECOLL; /*!< Late collision */
+ uint32_t ST_RX_OVERRUN; /*!< DMA overrun*/
+ uint32_t ST_TX_SQE; /*!< Heartbeat lost*/
+ uint32_t ST_TX_DEFERRED; /*!< Transmission deferred*/
+ uint32_t ST_TX_LATECOLL; /*!< Late collision*/
+ uint32_t ST_TX_EXCESSCOLL; /*!< Excessive collisions*/
+ uint32_t ST_TX_CARRIER; /*!< Carrier sense lost*/
+ uint32_t ST_TX_UNDERRUN; /*!< DMA underrun*/
+ /* Following stats are collected by the Ethernet driver */
+ uint32_t ST_RX_COPY_SMALL; /*!< Driver had to copy packet */
+ uint32_t ST_RX_COPY_LARGE; /*!< Driver had to copy packet */
+ uint32_t ST_TX_COPY_SMALL; /*!< Driver had to copy packet */
+ uint32_t ST_TX_COPY_LARGE; /*!< Driver had to copy packet */
+ uint32_t RX_FRAGS_EXCEEDED;
+ uint32_t RX_PCBS_EXHAUSTED;
+ uint32_t RX_LARGE_BUFFERS_EXHAUSTED;
+ uint32_t TX_ALIGNED;
+ uint32_t TX_ALL_ALIGNED;
+#if BSPCFG_ENABLE_ENET_HISTOGRAM
+ uint32_t RX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES];
+ uint32_t TX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES];
+#endif
+
+} ENET_STATS, * ENET_STATS_PTR;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name ENET RTCS ADAPTOR
+ * @{
+ */
+
+ /*!
+ * @brief Initializes the ENET device.
+ *
+ * @param device The ENET device number.
+ * @param address The hardware address.
+ * @param flag The flag for upper layer.
+ * @param handle The address pointer for ENET device structure.
+ * @return The execution status.
+ */
+uint32_t ENET_initialize(uint32_t device, _enet_address address,uint32_t flag, _enet_handle *handle);
+
+/*!
+ * @brief Opens the ENET device.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param type The ENET protocol type.
+ * @param service The service function for type.
+ * @param private The private data for ENET device.
+ * @return The execution status.
+ */
+uint32_t ENET_open(_enet_handle handle, uint16_t type, void (* service)(PCB_PTR, void *), void *private);
+
+/*!
+ * @brief Shuts down the ENET device.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The execution status.
+ */
+uint32_t ENET_shutdown(_enet_handle handle);
+#if !ENET_RECEIVE_ALL_INTERRUPT
+/*!
+ * @brief ENET frame receive.
+ *
+ * @param enetIfPtr The address pointer for ENET device structure.
+ */
+static void ENET_receive(task_param_t param);
+#endif
+/*!
+ * @brief ENET frame transmit.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param packet The ENET packet buffer.
+ * @param type The ENET protocol type.
+ * @param dest The destination hardware address.
+ * @param flag The flag for upper layer.
+ * @return The execution status.
+ */
+uint32_t ENET_send(_enet_handle handle, PCB_PTR packet, uint32_t type, _enet_address dest, uint32_t flags) ;
+
+/*!
+ * @brief The ENET gets the address with the initialized device.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param address The destination hardware address.
+ * @return The execution status.
+ */
+uint32_t ENET_get_address(_enet_handle handle, _enet_address address);
+
+/*!
+ * @brief The ENET gets the address with an uninitialized device.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param value The value to change the last three bytes of hardware.
+ * @param address The destination hardware address.
+ * @return True if the execution status is success else false.
+ */
+uint32_t ENET_get_mac_address(uint32_t device, uint32_t value, _enet_address address);
+/*!
+ * @brief The ENET joins a multicast group address.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param type The ENET protocol type.
+ * @param address The destination hardware address.
+ * @return The execution status.
+ */
+uint32_t ENET_join(_enet_handle handle, uint16_t type, _enet_address address);
+
+/*!
+ * @brief The ENET leaves a multicast group address.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param type The ENET protocol type.
+ * @param address The destination hardware address.
+ * @return The execution status.
+ */
+uint32_t ENET_leave(_enet_handle handle, uint16_t type, _enet_address address);
+#if BSPCFG_ENABLE_ENET_STATS
+/*!
+ * @brief The ENET gets the packet statistic.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The statistic.
+ */
+ENET_STATS_PTR ENET_get_stats(_enet_handle handle);
+#endif
+/*!
+ * @brief The ENET gets the link status.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The link status.
+ */
+bool ENET_link_status(_enet_handle handle);
+
+/*!
+ * @brief The ENET gets the link speed.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The link speed.
+ */
+uint32_t ENET_get_speed(_enet_handle handle);
+
+/*!
+ * @brief The ENET gets the MTU.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The link MTU
+ */
+uint32_t ENET_get_MTU(_enet_handle handle);
+
+/*!
+ * @brief Gets the ENET PHY registers.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param numRegs The number of registers.
+ * @param regPtr The buffer for data read from PHY registers.
+ * @return True if all numRegs registers are read succeed else false.
+ */
+bool ENET_phy_registers(_enet_handle handle, uint32_t numRegs, uint32_t *regPtr);
+
+/*!
+ * @brief Gets ENET options.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return ENET options.
+ */
+uint32_t ENET_get_options(_enet_handle handle);
+
+/*!
+ * @brief Unregisters a protocol type on an Ethernet channel.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return ENET options.
+ */
+uint32_t ENET_close(_enet_handle handle, uint16_t type);
+
+/*!
+ * @brief ENET mediactl.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @param The command ID.
+ * @param The buffer for input or output parameters.
+ * @return ENET options.
+ */
+uint32_t ENET_mediactl(_enet_handle handle, uint32_t commandId, void *inOutParam);
+
+/*!
+ * @brief Gets the next ENET device handle address.
+ *
+ * @param handle The address pointer for ENET device structure.
+ * @return The address of next ENET device handle.
+ */
+_enet_handle ENET_get_next_device_handle(_enet_handle handle);
+
+/*!
+ * @brief ENET free.
+ *
+ * @param packet The buffer address.
+ */
+void ENET_free(PCB_PTR packet);
+
+/*!
+ * @brief ENET error description.
+ *
+ * @param error The ENET error code.
+ * @return The error string.
+ */
+const char * ENET_strerror(uint32_t error);
+
+
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* MBED_NO_ENET */
+
+#endif /* __FSL_ENET_RTCS_ADAPTOR_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
+
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/enet/src/fsl_enet_irq.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_enet_driver.h"
+#include "fsl_clock_manager.h"
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+
+/* Internal irq number*/
+typedef enum _enet_irq_number
+{
+ kEnetTsTimerNumber = 0, /*!< ENET ts_timer irq number*/
+ kEnetReceiveNumber = 1, /*!< ENET receive irq number*/
+ kEnetTransmitNumber = 2, /*!< ENET transmit irq number*/
+ kEnetMiiErrorNumber = 3 /*!< ENET mii error irq number*/
+}enet_irq_number_t;
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+extern enet_ptp_master_time_data_t g_ptpMasterTime;
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT
+#define ENET_TIMER_CHANNEL_NUM 2
+#endif
+#endif
+
+#if defined (K64F12_SERIES) || defined (K70F12_SERIES)
+IRQn_Type enet_irq_ids[HW_ENET_INSTANCE_COUNT][FSL_FEATURE_ENET_INTERRUPT_COUNT] =
+{
+ { ENET_1588_Timer_IRQn, ENET_Receive_IRQn, ENET_Transmit_IRQn, ENET_Error_IRQn}
+};
+
+uint8_t enetIntMap[kEnetIntNum] =
+{
+ kEnetTsTimerNumber,
+ kEnetTsTimerNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetReceiveNumber,
+ kEnetReceiveNumber,
+ kEnetTransmitNumber,
+ kEnetTransmitNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber,
+ kEnetMiiErrorNumber
+};
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* The code was moved to k64f mac file (eth) */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/drivers/enet/subdir.mk Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,4 @@ +ENET_DRIVER_DIR := $(SDK_ROOT)/platform/drivers/enet +SOURCES += $(ENET_DRIVER_DIR)/src/fsl_enet_driver.c \ + $(ENET_DRIVER_DIR)/src/fsl_enet_irq.c +INCLUDES += $(ENET_DRIVER_DIR)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,126 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140526 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_INTERRUPT_FEATURES_H__) +#define __FSL_INTERRUPT_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (73) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ + defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || \ + defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV45F128VLL15) || \ + defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ + defined(CPU_MKV46F256VLL15) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (99) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \ + defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ + defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ + defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || \ + defined(CPU_MKL17Z128VFT4) || defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4) || \ + defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \ + defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL33Z128VLH4) || \ + defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || \ + defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || \ + defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ + defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15) + /* @brief Lowest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) + /* @brief Highest interrupt request number. */ + #define FSL_FEATURE_INTERRUPT_IRQ_MAX (92) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_INTERRUPT_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_INTERRUPT_MANAGER_H__)
+#define __FSL_INTERRUPT_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_interrupt_features.h"
+#include "device/fsl_device_registers.h"
+
+/*! @addtogroup interrupt_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name interrupt_manager APIs*/
+/*@{*/
+
+/*!
+ * @brief Installs an interrupt handler routine for a given IRQ number.
+ *
+ * This function lets the application register/replace the interrupt
+ * handler for a specified IRQ number. The IRQ number is different than the vector
+ * number. IRQ 0 starts from the vector 16 address. See a chip-specific reference
+ * manual for details and the startup_MKxxxx.s file for each chip
+ * family to find out the default interrupt handler for each device. This
+ * function converts the IRQ number to the vector number by adding 16 to
+ * it.
+ *
+ * @param irqNumber IRQ number
+ * @param handler Interrupt handler routine address pointer
+ */
+void INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void));
+
+/*!
+ * @brief Enables an interrupt for a given IRQ number.
+ *
+ * This function enables the individual interrupt for a specified IRQ
+ * number. It calls the system NVIC API to access the interrupt control
+ * register. The input IRQ number does not include the core interrupt, only
+ * the peripheral interrupt, from 0 to a maximum supported IRQ.
+ *
+ * @param irqNumber IRQ number
+ */
+static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
+{
+ /* check IRQ number */
+ assert(0 <= irqNumber);
+ assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
+
+ /* call core API to enable the IRQ*/
+ NVIC_EnableIRQ(irqNumber);
+}
+
+/*!
+ * @brief Disables an interrupt for a given IRQ number.
+ *
+ * This function enables the individual interrupt for a specified IRQ
+ * number. It calls the system NVIC API to access the interrupt control
+ * register.
+ *
+ * @param irqNumber IRQ number
+ */
+static inline void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
+{
+ /* check IRQ number */
+ assert(0 <= irqNumber);
+ assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
+
+ /* call core API to disable the IRQ*/
+ NVIC_DisableIRQ(irqNumber);
+}
+
+/*!
+ * @brief Enables system interrupt.
+ *
+ * This function enables the global interrupt by calling the core API.
+ *
+ */
+void INT_SYS_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable system interrupt.
+ *
+ * This function disables the global interrupt by calling the core API.
+ *
+ */
+void INT_SYS_DisableIRQGlobal(void);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_INTERRUPT_MANAGER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit_features.h" +#include "fsl_device_registers.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Table of base addresses for pit instances. */ +const uint32_t g_pitBaseAddr[] = PIT_BASE_ADDRS; + +/* Table to save PIT IRQ enum numbers defined in CMSIS files. */ +const IRQn_Type g_pitIrqId[] = PIT_IRQS; + +/******************************************************************************* + * EOF + ******************************************************************************/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_PIT_COMMON_H__) +#define __FSL_PIT_COMMON_H__ + +#include <stdint.h> +#include "fsl_device_registers.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Table of base addresses for pit instances. */ +extern const uint32_t g_pitBaseAddr[]; + +/*! @brief Table to save pit IRQ enum numbers defined in CMSIS header file. */ +extern const IRQn_Type g_pitIrqId[]; + +#endif /* __FSL_PIT_COMMON_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PIT_DRIVER_H__
+#define __FSL_PIT_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_pit_hal.h"
+
+/*!
+ * @addtogroup pit_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief PIT timer configuration structure
+ *
+ * Define structure PitConfig and use the PIT_DRV_InitChannel() function to make necessary
+ * initializations. You may also use the remaining functions for PIT configuration.
+ *
+ * @note The timer chain feature is not valid in all devices. Check the
+ * fsl_pit_features.h for accurate settings. If it's not valid, the value set here
+ * will be bypassed inside the PIT_DRV_InitChannel() function.
+ */
+typedef struct PitUserConfig {
+ bool isInterruptEnabled; /*!< Timer interrupt 0-disable/1-enable*/
+ bool isTimerChained; /*!< Chained with previous timer, 0-not/1-chained*/
+ uint32_t periodUs; /*!< Timer period in unit of microseconds*/
+} pit_user_config_t;
+
+/*! @brief PIT ISR callback function typedef */
+typedef void (*pit_isr_callback_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialize and Shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes the PIT module.
+ *
+ * This function must be called before calling all the other PIT driver functions.
+ * This function un-gates the PIT clock and enables the PIT module. The isRunInDebug
+ * passed into function affects all timer channels.
+ *
+ * @param instance PIT module instance number.
+ * @param isRunInDebug Timers run or stop in debug mode.
+ * - true: Timers continue to run in debug mode.
+ * - false: Timers stop in debug mode.
+ */
+void PIT_DRV_Init(uint32_t instance, bool isRunInDebug);
+
+/*!
+ * @brief Disables the PIT module and gate control.
+ *
+ * This function disables all PIT interrupts and PIT clock. It then gates the
+ * PIT clock control. PIT_DRV_Init must be called if you want to use PIT again.
+ *
+ * @param instance PIT module instance number.
+ */
+void PIT_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Initializes the PIT channel.
+ *
+ * This function initializes the PIT timers by using a channel. Pass in the timer number and its
+ * configuration structure. Timers do not start counting by default after calling this
+ * function. The function PIT_DRV_StartTimer must be called to start the timer counting.
+ * Call the PIT_DRV_SetTimerPeriodByUs to re-set the period.
+ *
+ * This is an example demonstrating how to define a PIT channel configuration structure:
+ @code
+ pit_user_config_t pitTestInit = {
+ .isInterruptEnabled = true,
+ // Only takes effect when chain feature is available.
+ // Otherwise, pass in arbitrary value(true/false).
+ .isTimerChained = false,
+ // In unit of microseconds.
+ .periodUs = 1000,
+ };
+ @endcode
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @param config PIT channel configuration structure.
+ */
+void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config);
+
+/* @} */
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the timeout interrupt flag.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ */
+void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops every timer counting. Timers reload their periods
+ * respectively after the next time they call the PIT_DRV_StartTimer.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ */
+void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel);
+
+/* @} */
+
+/*!
+ * @name Timer Period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in microseconds.
+ *
+ * The period range depends on the frequency of the PIT source clock. If the required period
+ * is out of range, use the lifetime timer.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @param us Timer period in microseconds.
+ */
+void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us);
+
+/*!
+ * @brief Reads the current timer value in microseconds.
+ *
+ * This function returns an absolute time stamp in microseconds.
+ * One common use of this function is to measure the running time of a part of
+ * code. Call this function at both the beginning and end of code. The time
+ * difference between these two time stamps is the running time. Make sure the
+ * running time does not exceed the timer period. The time stamp returned is
+ * up-counting.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @return Current timer value in microseconds.
+ */
+uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel);
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*!
+ * @brief Sets the lifetime timer period.
+ *
+ * Timer 1 must be chained with timer 0 before using the lifetime timer. The period
+ * range is restricted by "period * pitSourceClock < max of an uint64_t integer",
+ * or it may cause an overflow and be unable to set the correct period.
+ *
+ * @param instance PIT module instance number.
+ * @param period Lifetime timer period in microseconds.
+ */
+void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us);
+
+/*!
+ * @brief Reads the current lifetime value in microseconds.
+ *
+ * This feature returns an absolute time stamp in microseconds. The time stamp
+ * value does not exceed the timer period. The timer is up-counting.
+ *
+ * @param instance PIT module instance number.
+ * @return Current lifetime timer value in microseconds.
+ */
+uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance);
+#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/* @} */
+
+/*!
+ * @name ISR Callback Function
+ * @{
+ */
+
+/*!
+ * @brief Registers the PIT ISR callback function.
+ *
+ * System default ISR interfaces are already defined in the fsl_pit_irq.c. Users
+ * can either edit these ISRs or use this function to register a callback
+ * function. The default ISR runs the callback function if there is one
+ * installed.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @param function Pointer to pit ISR callback function.
+ */
+void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PIT_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pit_common.h"
+#include "fsl_pit_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* pit source clock variable which will be updated in PIT_DRV_Init. */
+uint64_t pitSourceClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_Init
+ * Description : Initialize PIT module.
+ * This function must be called before calling all the other PIT driver functions.
+ * This function un-gates the PIT clock and enables the PIT module. The isRunInDebug
+ * passed into function will affect all timer channels.
+ *
+ *END**************************************************************************/
+void PIT_DRV_Init(uint32_t instance, bool isRunInDebug)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+
+ /* Un-gate pit clock*/
+ CLOCK_SYS_EnablePitClock( 0U);
+
+ /* Enable PIT module clock*/
+ PIT_HAL_Enable(baseAddr);
+
+ /* Set timer run or stop in debug mode*/
+ PIT_HAL_SetTimerRunInDebugCmd(baseAddr, isRunInDebug);
+
+ /* Finally, update pit source clock frequency.*/
+ pitSourceClock = CLOCK_SYS_GetPitFreq(0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_InitChannel
+ * Description : Initialize PIT channel.
+ * This function initialize PIT timers by channel. Pass in timer number and its
+ * config structure. Timers do not start counting by default after calling this
+ * function. Function PIT_DRV_StartTimer must be called to start timer counting.
+ * Call PIT_DRV_SetTimerPeriodByUs to re-set the period.
+ *
+ *END**************************************************************************/
+void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ /* Set timer period.*/
+ PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs);
+
+ #if FSL_FEATURE_PIT_HAS_CHAIN_MODE
+ /* Configure timer chained or not.*/
+ PIT_HAL_SetTimerChainCmd(baseAddr, channel, config->isTimerChained);
+ #endif
+
+ /* Enable or disable interrupt.*/
+ PIT_HAL_SetIntCmd(baseAddr, channel, config->isInterruptEnabled);
+
+ /* Configure NVIC*/
+ if (config->isInterruptEnabled)
+ {
+ /* Enable PIT interrupt.*/
+ INT_SYS_EnableIRQ(g_pitIrqId[channel]);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_Deinit
+ * Description : Disable PIT module and gate control
+ * This function will disable all PIT interrupts and PIT clock. Then gate the
+ * PIT clock control. pit_init must be called in order to use PIT again.
+ *
+ *END**************************************************************************/
+void PIT_DRV_Deinit(uint32_t instance)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ uint32_t i;
+
+ /* Disable all PIT interrupts. */
+ for (i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+ {
+ PIT_HAL_SetIntCmd(baseAddr, i, false);
+ INT_SYS_DisableIRQ(g_pitIrqId[i]);
+ }
+
+ /* Disable PIT module clock*/
+ PIT_HAL_Disable(baseAddr);
+
+ /* Gate PIT clock control*/
+ CLOCK_SYS_DisablePitClock( 0U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_StartTimer
+ * Description : Start timer counting.
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it will generate a trigger pulse and set the timeout interrupt flag.
+ *
+ *END**************************************************************************/
+void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ PIT_HAL_StartTimer(baseAddr, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_StopTimer
+ * Description : Stop timer counting.
+ * This function will stop every timer counting. Timers will reload their periods
+ * respectively after calling PIT_DRV_StartTimer next time.
+ *
+ *END**************************************************************************/
+void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ PIT_HAL_StopTimer(baseAddr, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_SetTimerPeriodByUs
+ * Description : Set timer period in microseconds unit.
+ * The period range depends on the frequency of PIT source clock. If required
+ * period is out the range, try to use lifetime timer if applicable.
+ *
+ *END**************************************************************************/
+void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ /* Calculate the count value, assign it to timer counter register.*/
+ uint32_t count = (uint32_t)(us * pitSourceClock / 1000000U - 1U);
+ PIT_HAL_SetTimerPeriodByCount(baseAddr, channel, count);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ReadTimerUs
+ * Description : Read current timer value in microseconds unit.
+ * This function will return an absolute time stamp in the unit of microseconds.
+ * One common use of this function is to measure the running time of part of
+ * code. Just call this function at both the beginning and end of code, the time
+ * difference between these two time stamp will be the running time (Need to
+ * make sure the running time will not exceed the timer period). Also, the time
+ * stamp returned is up-counting.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ /* Get current timer count, and reverse it to up-counting.*/
+ uint64_t currentTime = (~PIT_HAL_ReadTimerCount(baseAddr, channel));
+
+ /* Convert count numbers to microseconds unit.*/
+ currentTime = (currentTime * 1000000U) / pitSourceClock;
+ return (uint32_t)currentTime;
+}
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_SetLifetimeTimerPeriodByUs
+ * Description : Set lifetime timer period (Timers must be chained).
+ * Timer 1 must be chained with timer 0 before using lifetime timer. The period
+ * range is restricted by "period * pitSourceClock < max of an uint64_t integer",
+ * or it may cause a overflow and is not able to set correct period.
+ *
+ *END**************************************************************************/
+void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ uint64_t lifeTimeCount;
+
+ /* Calculate the counter value.*/
+ lifeTimeCount = us * pitSourceClock / 1000000U - 1U;
+
+ /* Assign to timers.*/
+ PIT_HAL_SetTimerPeriodByCount(baseAddr, 0U, (uint32_t)lifeTimeCount);
+ PIT_HAL_SetTimerPeriodByCount(baseAddr, 1U, (uint32_t)(lifeTimeCount >> 32U));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ReadLifetimeTimerUs
+ * Description : Read current lifetime value in microseconds unit.
+ * Return an absolute time stamp in the unit of microseconds. The time stamp
+ * value will not exceed the timer period. Also, the timer is up-counting.
+ *
+ *END**************************************************************************/
+uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance)
+{
+ assert(instance < HW_PIT_INSTANCE_COUNT);
+
+ uint32_t baseAddr = g_pitBaseAddr[instance];
+ /* Get current lifetime timer count, and reverse it to up-counting.*/
+ uint64_t currentTime = (~PIT_HAL_ReadLifetimeTimerCount(baseAddr));
+
+ /* Convert count numbers to microseconds unit.*/
+ /* Note: using currentTime * 1000 rather than 1000000 to avoid short time overflow. */
+ return currentTime = (currentTime * 1000U) / (pitSourceClock / 1000U);
+}
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <assert.h>
+#include "fsl_pit_common.h"
+#include "fsl_pit_driver.h"
+
+/*!
+ * @addtogroup pit_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*!
+ * @brief Function table to save PIT isr callback function pointers.
+ *
+ * Call PIT_DRV_InstallCallback to install isr callback functions.
+ */
+static pit_isr_callback_t pitIsrCallbackTable[HW_PIT_INSTANCE_COUNT][FSL_FEATURE_PIT_TIMER_COUNT] = {{NULL}};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined (KL25Z4_SERIES)
+/*!
+ * @brief System default IRQ handler defined in startup code.
+ *
+ * Users can either edit this handler or define a callback function. Furthermore,
+ * interrupt manager could be used to re-map the IRQ handler to another function.
+ */
+void PIT_IRQHandler(void)
+{
+ uint32_t i;
+ for(i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+ {
+ /* Clear interrupt flag.*/
+ PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], i);
+
+ /* Run callback function if it exists.*/
+ if (pitIsrCallbackTable[0][i])
+ {
+ (*pitIsrCallbackTable[0][i])();
+ }
+ }
+}
+
+#elif defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \
+ defined (K22F12810_SERIES) || defined (K22F25612_SERIES) || defined (K22F51212_SERIES) || \
+ defined (KV31F12810_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F51212_SERIES) || \
+ defined (K70F12_SERIES)
+void PIT0_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 0U);
+
+ /* Run callback function if it exists.*/
+ if (pitIsrCallbackTable[0][0])
+ {
+ (*pitIsrCallbackTable[0][0])();
+ }
+}
+
+void PIT1_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 1U);
+
+ /* Run callback function if it exists.*/
+ if (pitIsrCallbackTable[0][1])
+ {
+ (*pitIsrCallbackTable[0][1])();
+ }
+}
+
+void PIT2_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 2U);
+
+ /* Run callback function if it exists.*/
+ if (pitIsrCallbackTable[0][2])
+ {
+ (*pitIsrCallbackTable[0][2])();
+ }
+}
+
+void PIT3_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 3U);
+
+ /* Run callback function if it exists.*/
+ if (pitIsrCallbackTable[0][3])
+ {
+ (*pitIsrCallbackTable[0][3])();
+ }
+}
+#endif
+
+/*! @} */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_InstallCallback
+ * Description : Register pit isr callback function.
+ * System default ISR interfaces are already defined in fsl_pit_irq.c. Users
+ * can either edit these ISRs or use this function to register a callback
+ * function. The default ISR will run the callback function it there is one
+ * installed here.
+
+ *END**************************************************************************/
+void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ assert(function != NULL);
+
+ pitIsrCallbackTable[instance][channel] = function;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,220 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_ADC_FEATURES_H__) +#define __FSL_ADC_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \ + defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ + defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \ + defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC_HAS_PGA (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) +#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC_HAS_PGA (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC_HAS_PGA (1) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC_HAS_PGA (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC_HAS_DMA (0) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC_MAX_RESOLUTION (12) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC_HAS_PGA (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC_MAX_RESOLUTION (12) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_ADC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc_hal.h"
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC_HAL_Init
+ * Description :Reset all the registers into a known state for ADC
+ * module. This known state is the default value indicated by the Reference
+ * manual. It is strongly recommended to call this API before any operations
+ * when initializing the ADC module. Note registers for calibration would not
+ * be cleared in this function.
+ *
+ *END*************************************************************************/
+void ADC_HAL_Init(uint32_t baseAddr)
+{
+ HW_ADC_CFG1_WR(baseAddr, 0U);
+ HW_ADC_CFG2_WR(baseAddr, 0U);
+ HW_ADC_CV1_WR(baseAddr, 0U);
+ HW_ADC_CV2_WR(baseAddr, 0U);
+ HW_ADC_SC2_WR(baseAddr, 0U);
+ HW_ADC_SC3_WR(baseAddr, 0U);
+#if FSL_FEATURE_ADC_HAS_PGA
+ HW_ADC_PGA_WR(baseAddr, 0U);
+#endif /* FSL_FEATURE_ADC_HAS_PGA */
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC_HAL_SetHwCmpMode
+ * Description :Set the asserted compare range when enabling hardware
+ * compare function. About the selection of range mode, see to the description
+ * for "adc_hw_cmp_range_mode_t".
+ *
+ *END*************************************************************************/
+void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode)
+{
+ switch (mode)
+ {
+ case kAdcHwCmpRangeModeOf1:
+ ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false);
+ ADC_HAL_SetHwCmpRangeCmd(baseAddr, false);
+ break;
+ case kAdcHwCmpRangeModeOf2:
+ ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true);
+ ADC_HAL_SetHwCmpRangeCmd(baseAddr, false);
+ break;
+ case kAdcHwCmpRangeModeOf3:
+ ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false);
+ ADC_HAL_SetHwCmpRangeCmd(baseAddr, true);
+ break;
+ case kAdcHwCmpRangeModeOf4:
+ ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true);
+ ADC_HAL_SetHwCmpRangeCmd(baseAddr, true);
+ break;
+ default:
+ break;
+ }
+}
+
+#if FSL_FEATURE_ADC_HAS_CALIBRATION
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC_HAL_GetAutoPlusSideGainValue
+ * Description : Get the values of CLP0 - CLP4 and CLPS internally,
+ * accumulate them, and return the value that can be used to be set in PG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration has been done.
+ *
+ *END*************************************************************************/
+uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr)
+{
+ uint16_t cal_var;
+
+ /* Calculate plus-side calibration */
+ cal_var = 0U;
+ cal_var += BR_ADC_CLP0_CLP0(baseAddr);
+ cal_var += BR_ADC_CLP1_CLP1(baseAddr);
+ cal_var += BR_ADC_CLP2_CLP2(baseAddr);
+ cal_var += BR_ADC_CLP3_CLP3(baseAddr);
+ cal_var += BR_ADC_CLP4_CLP4(baseAddr);
+ cal_var += BR_ADC_CLPS_CLPS(baseAddr);
+ cal_var = 0x8000U | (cal_var>>1U);
+
+ return cal_var;
+}
+
+#if FSL_FEATURE_ADC_HAS_DIFF_MODE
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC_HAL_GetAutoMinusSideGainValue
+ * Description : Get the values of CLM0 - CLM4 and CLMS internally,
+ * accumulate them, and return the value that can be used to be set in MG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration has been done.
+ *
+ *END*************************************************************************/
+uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr)
+{
+ uint16_t cal_var;
+
+ /* Calculate minus-side calibration */
+ cal_var = 0U;
+ cal_var += BR_ADC_CLM0_CLM0(baseAddr);
+ cal_var += BR_ADC_CLM1_CLM1(baseAddr);
+ cal_var += BR_ADC_CLM2_CLM2(baseAddr);
+ cal_var += BR_ADC_CLM3_CLM3(baseAddr);
+ cal_var += BR_ADC_CLM4_CLM4(baseAddr);
+ cal_var += BR_ADC_CLMS_CLMS(baseAddr);
+ cal_var = 0x8000U | (cal_var>>1U);
+
+ return cal_var;
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
+
+#endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC_HAL_H__
+#define __FSL_ADC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_adc_features.h"
+
+/*!
+ * @addtogroup adc_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*!
+ * @brief ADC status return codes.
+ */
+typedef enum _adc_status
+{
+ kStatus_ADC_Success = 0U, /*!< Success. */
+ kStatus_ADC_InvalidArgument = 1U, /*!< Invalid argument existed. */
+ kStatus_ADC_Failed = 2U /*!< Execution failed. */
+} adc_status_t;
+
+#if FSL_FEATURE_ADC_HAS_MUX_SELECT
+
+/*!
+ * @brief Defines the type of the enumerating channel multiplexer mode for each channel.
+ *
+ * For some ADC channels, there are two selections for the channel multiplexer. For
+ * example, ADC0_SE4a and ADC0_SE4b are the different channels but share the same
+ * channel number.
+ */
+typedef enum _adc_chn_mux_mode
+{
+ kAdcChnMuxOfA = 0U, /*!< For channel with channel mux a. */
+ kAdcChnMuxOfB = 1U, /*!< For channel with channel mux b. */
+ kAdcChnMuxOfDefault = kAdcChnMuxOfA /*!< For channel without any channel mux identifier. */
+} adc_chn_mux_mode_t;
+#endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */
+
+/*!
+ * @brief Defines the type of the enumerating divider for the converter.
+ */
+typedef enum _adc_clk_divider_mode
+{
+ kAdcClkDividerInputOf1 = 0U, /*!< For divider 1 from the input clock to ADC. */
+ kAdcClkDividerInputOf2 = 1U, /*!< For divider 2 from the input clock to ADC. */
+ kAdcClkDividerInputOf4 = 2U, /*!< For divider 4 from the input clock to ADC. */
+ kAdcClkDividerInputOf8 = 3U /*!< For divider 8 from the input clock to ADC. */
+} adc_clk_divider_mode_t;
+
+/*!
+ *@brief Defines the type of the enumerating resolution for the converter.
+ */
+typedef enum _adc_resolution_mode
+{
+ kAdcResolutionBitOf8or9 = 0U,
+ /*!< 8-bit for single end sample, or 9-bit for differential sample. */
+ kAdcResolutionBitOfSingleEndAs8 = kAdcResolutionBitOf8or9, /*!< 8-bit for single end sample. */
+ kAdcResolutionBitOfDiffModeAs9 = kAdcResolutionBitOf8or9, /*!< 9-bit for differential sample. */
+
+ kAdcResolutionBitOf12or13 = 1U,
+ /*!< 12-bit for single end sample, or 13-bit for differential sample. */
+ kAdcResolutionBitOfSingleEndAs12 = kAdcResolutionBitOf12or13, /*!< 12-bit for single end sample. */
+ kAdcResolutionBitOfDiffModeAs13 = kAdcResolutionBitOf12or13, /*!< 13-bit for differential sample. */
+
+ kAdcResolutionBitOf10or11 = 2U,
+ /*!< 10-bit for single end sample, or 11-bit for differential sample. */
+ kAdcResolutionBitOfSingleEndAs10 = kAdcResolutionBitOf10or11, /*!< 10-bit for single end sample. */
+ kAdcResolutionBitOfDiffModeAs11 = kAdcResolutionBitOf10or11 /*!< 11-bit for differential sample. */
+#if (FSL_FEATURE_ADC_MAX_RESOLUTION>=16)
+ , kAdcResolutionBitOf16 = 3U,
+ /*!< 16-bit for both single end sample and differential sample. */
+ kAdcResolutionBitOfSingleEndAs16 = kAdcResolutionBitOf16, /*!< 16-bit for single end sample. */
+ kAdcResolutionBitOfDiffModeAs16 = kAdcResolutionBitOf16 /*!< 16-bit for differential sample. */
+
+#endif /* FSL_FEATURE_ADC_MAX_RESOLUTION */
+} adc_resolution_mode_t;
+
+/*!
+ * @brief Defines the type of the enumerating source of the input clock.
+ */
+typedef enum _adc_clk_src_mode
+{
+ kAdcClkSrcOfBusClk = 0U, /*!< For input as bus clock. */
+ kAdcClkSrcOfBusOrAltClk2 = 1U, /*!< For input as bus clock /2 or AltClk2. */
+ kAdcClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). */
+ kAdcClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). */
+} adc_clk_src_mode_t;
+
+/*
+ * @brief Defines the type of the enumerating long sample cycles.
+ */
+typedef enum _adc_long_sample_cycle_mode
+{
+ kAdcLongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
+ kAdcLongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
+ kAdcLongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
+ kAdcLongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
+} adc_long_sample_cycle_mode_t;
+
+/*
+ * @brief Defines the type of the enumerating reference voltage source.
+ */
+typedef enum _adc_ref_volt_src_mode
+{
+ kAdcRefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
+ kAdcRefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL.*/
+} adc_ref_volt_src_mode_t;
+
+#if FSL_FEATURE_ADC_HAS_HW_AVERAGE
+
+/*
+ * @brief Defines the type of the enumerating hardware average mode.
+ */
+typedef enum _adc_hw_average_count_mode
+{
+ kAdcHwAverageCountOf4 = 0U, /*!< For hardware average with 4 samples. */
+ kAdcHwAverageCountOf8 = 1U, /*!< For hardware average with 8 samples. */
+ kAdcHwAverageCountOf16 = 2U, /*!< For hardware average with 16 samples. */
+ kAdcHwAverageCountOf32 = 3U /*!< For hardware average with 32 samples. */
+} adc_hw_average_count_mode_t;
+
+#endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */
+
+/*!
+ * @brief Defines the type of the enumerating asserted range in the hardware compare.
+ *
+ * When the internal CMP is enabled, the COCO flag, which represents the complement
+ * of the conversion, is not asserted if the sample value is not in the indicated
+ * range. Eventually, the data of conversion result is not kept in the result
+ * data register. The two values, cmpValue1 and cmpValue2, mark
+ * the thresholds with the comparator feature.
+ * kAdcHwCmpRangeModeOf1:
+ * Both greater than and in range switchers are disabled.
+ * The available range is "< cmpValue1".
+ * kAdcHwCmpRangeModeOf2:
+ * Greater than switcher is enabled while the in range switcher is disabled.
+ * The available range is " > cmpValue1".
+ * kAdcHwCmpRangeModeOf3:
+ * Greater than switcher is disabled while in range switcher is enabled.
+ * The available range is "< cmpValue1" or "> cmpValue2" when
+ * cmpValue1 <= cmpValue2, or "< cmpValue1" and "> cmpValue2" when
+ * cmpValue1 >= cmpValue2.
+ * kAdcHwCmpRangeModeOf4:
+ * Both greater than and in range switchers are enabled.
+ * The available range is "> cmpValue1" and "< cmpValue2" when
+ * cmpValue1 <= cmpValue2, or "> cmpValue1" or "< cmpValue2" when
+ * cmpValue1 < cmpValue2.
+ */
+typedef enum _adc_hw_cmp_range_mode
+{
+ kAdcHwCmpRangeModeOf1 = 0U, /*!< For selection mode 1. */
+ kAdcHwCmpRangeModeOf2 = 1U, /*!< For selection mode 2. */
+ kAdcHwCmpRangeModeOf3 = 2U, /*!< For selection mode 3. */
+ kAdcHwCmpRangeModeOf4 = 3U /*!< For selection mode 4. */
+} adc_hw_cmp_range_mode_t;
+
+#if FSL_FEATURE_ADC_HAS_PGA
+
+/*!
+ * @brief Defines the type of enumerating PGA's Gain mode.
+ */
+typedef enum _adc_pga_gain_mode
+{
+ kAdcPgaGainValueOf1 = 0U, /*!< For amplifier gain of 1.*/
+ kAdcPgaGainValueOf2 = 1U, /*!< For amplifier gain of 2.*/
+ kAdcPgaGainValueOf4 = 2U, /*!< For amplifier gain of 4.*/
+ kAdcPgaGainValueOf8 = 3U, /*!< For amplifier gain of 8.*/
+ kAdcPgaGainValueOf16 = 4U, /*!< For amplifier gain of 16.*/
+ kAdcPgaGainValueOf32 = 5U, /*!< For amplifier gain of 32.*/
+ kAdcPgaGainValueOf64 = 6U /*!< For amplifier gain of 64.*/
+} adc_pga_gain_mode_t;
+
+#endif /* FSL_FEATURE_ADC_HAS_PGA */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+/*!
+ * @brief Resets all registers into a known state for the ADC module.
+ *
+ * This function resets all registers into a known state for the ADC
+ * module. This known state is the reset value indicated by the Reference
+ * manual. It is strongly recommended to call this API before any other operation
+ * when initializing the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+void ADC_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Configures the conversion channel for the ADC module.
+ *
+ * This function configures the channel for the ADC module. At any point,
+ * only one of the configuration groups takes effect. The other channel mux of
+ * the first group (group A, 0) is only for the hardware trigger. Both software and
+ * hardware trigger can be used to the first group. When in software trigger
+ * mode, once the available channel is set, the conversion begins to execute.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @param intEnable Switcher to enable interrupt when conversion is completed.
+ * @param diffEnable Switcher to enable differential channel mode.
+ * @param chnNum ADC channel for next conversion.
+ */
+static inline void ADC_HAL_ConfigChn(uint32_t baseAddr, uint32_t chnGroup,
+ bool intEnable, bool diffEnable, uint8_t chnNum)
+{
+ assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
+
+#if FSL_FEATURE_ADC_HAS_DIFF_MODE
+ HW_ADC_SC1n_WR(baseAddr, chnGroup, \
+ ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \
+ | ( (diffEnable)? BM_ADC_SC1n_DIFF : 0U) \
+ | BF_ADC_SC1n_ADCH(chnNum) \
+ ) );
+#else
+ HW_ADC_SC1n_WR(baseAddr, chnGroup, \
+ ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \
+ | BF_ADC_SC1n_ADCH(chnNum) \
+ ) );
+
+#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
+
+}
+
+#if FSL_FEATURE_ADC_HAS_DIFF_MODE
+
+/*!
+ * @brief Checks whether the channel differential mode is enabled.
+ *
+ * This function checks whether the channel differential mode for
+ * is enabled.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @return Assertion of enabling differential mode.
+ */
+static inline bool ADC_HAL_GetChnDiffCmd(uint32_t baseAddr, uint32_t chnGroup)
+{
+ assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
+ return (1U == BR_ADC_SC1n_DIFF(baseAddr, chnGroup));
+}
+#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
+
+/*!
+ * @brief Checks whether the channel conversion is completed.
+ *
+ * This function checks whether the channel conversion for the ADC
+ * module is completed.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @return Assertion of completed conversion mode.
+ */
+static inline bool ADC_HAL_GetChnConvCompletedCmd(uint32_t baseAddr, uint32_t chnGroup)
+{
+ assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
+ return (1U == BR_ADC_SC1n_COCO(baseAddr, chnGroup) );
+}
+
+/*!
+ * @brief Switches to enable the low power mode for ADC module.
+ *
+ * This function switches to enable the low power mode for ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_CFG1_ADLPC(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Selects the clock divider mode for the ADC module.
+ *
+ * This function selects the clock divider mode for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode enumeration. See to "adc_clk_divider_mode_t".
+ */
+static inline void ADC_HAL_SetClkDividerMode(uint32_t baseAddr, adc_clk_divider_mode_t mode)
+{
+ BW_ADC_CFG1_ADIV(baseAddr, (uint32_t)mode );
+}
+
+/*!
+ * @brief Switches to enable the long sample mode for the ADC module.
+ *
+ * This function switches to enable the long sample mode for the ADC module.
+ * This function adjusts the sample period to allow the higher impedance inputs to
+ * be accurately sampled or to maximize the conversion speed for the lower impedance
+ * inputs. Longer sample times can also be used to lower overall power
+ * consumption if the continuous conversions are enabled and the high conversion rates
+ * are not required. If the long sample mode is enabled, more configuration
+ * is set by calling the "ADC_HAL_SetLongSampleCycleMode()" function.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetLongSampleCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_CFG1_ADLSMP(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Selects the conversion resolution mode for ADC module.
+ *
+ * This function selects the conversion resolution mode for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode enumeration. See to "adc_resolution_mode_t".
+ */
+static inline void ADC_HAL_SetResolutionMode(uint32_t baseAddr, adc_resolution_mode_t mode)
+{
+ BW_ADC_CFG1_MODE(baseAddr, (uint32_t)mode );
+}
+
+/*!
+ * @brief Gets the conversion resolution mode for ADC module.
+ *
+ * This function gets the conversion resolution mode for the ADC module.
+ * It is specially used when processing the conversion result of RAW format.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return Current conversion resolution mode.
+ */
+static inline adc_resolution_mode_t ADC_HAL_GetResolutionMode(uint32_t baseAddr)
+{
+ return (adc_resolution_mode_t)( BR_ADC_CFG1_MODE(baseAddr) );
+}
+
+/*!
+ * @brief Selects the input clock source for the ADC module.
+ *
+ * This function selects the input clock source for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode enumeration. See to "adc_clk_src_mode_t".
+ */
+static inline void ADC_HAL_SetClkSrcMode(uint32_t baseAddr, adc_clk_src_mode_t mode)
+{
+ BW_ADC_CFG1_ADICLK(baseAddr, (uint32_t)mode );
+}
+
+#if FSL_FEATURE_ADC_HAS_MUX_SELECT
+
+/*!
+ * @brief Selects the channel mux mode for the ADC module.
+ *
+ * This function selects the channel mux mode for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode enumeration. See to "adc_chn_mux_mode_t".
+ */
+static inline void ADC_HAL_SetChnMuxMode(uint32_t baseAddr, adc_chn_mux_mode_t mode)
+{
+ BW_ADC_CFG2_MUXSEL(baseAddr, ((kAdcChnMuxOfA == mode) ? 0U : 1U) );
+}
+
+/*!
+ * @brief Gets the current channel mux mode for the ADC module.
+ *
+ * This function selects the channel mux mode for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return Selection of mode enumeration. See to "adc_chn_mux_mode_t".
+ */
+static inline adc_chn_mux_mode_t ADC_HAL_GetChnMuxMode(uint32_t baseAddr)
+{
+ return (adc_chn_mux_mode_t)(BR_ADC_CFG2_MUXSEL(baseAddr) );
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */
+
+/*!
+ * @brief Switches to enable the asynchronous clock for the ADC module.
+ *
+ * This function switches to enable the asynchronous clock for the ADC module.
+ * It enables the ADC's asynchronous clock source and the clock source
+ * output regardless of the conversion and the input clock select status of the
+ * ADC. Asserting this function allows the clock to be used even while the ADC
+ * is idle or operating from a different clock source. Also, latency of
+ * initiating a single or first-continuous conversion with the asynchronous
+ * clock selected is reduced since the ADC internal clock has been already
+ * operational.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetAsyncClkCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_CFG2_ADACKEN(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Switches to enable the high speed mode for the ADC module.
+ *
+ * This function switches to enable the high speed mode for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHighSpeedCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_CFG2_ADHSC(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Selects the long sample cycle mode for the ADC module.
+ *
+ * This function selects the long sample cycle mode for the ADC module.
+ * This function should be called along with "ADC_HAL_SetLongSampleCmd()".
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of long sample cycle mode. See the "adc_long_sample_cycle_mode_t".
+ */
+static inline void ADC_HAL_SetLongSampleCycleMode(uint32_t baseAddr,
+ adc_long_sample_cycle_mode_t mode)
+{
+ BW_ADC_CFG2_ADLSTS(baseAddr, (uint32_t)mode );
+}
+
+/*!
+ * @brief Gets the raw result data of channel conversion for the ADC module.
+ *
+ * This function gets the result data of conversion for the ADC module.
+ * The return value is raw data that is not processed. The unavailable bits would be
+ * filled with "0" in single-ended mode and sign bit in differential mode.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @return Conversion value of RAW.
+ */
+static inline uint16_t ADC_HAL_GetChnConvValueRAW(uint32_t baseAddr,
+ uint32_t chnGroup )
+{
+ assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
+ return (uint16_t)(BR_ADC_Rn_D(baseAddr, chnGroup) );
+}
+
+/*!
+ * @brief Sets the compare value of the lower limitation for the ADC module.
+ *
+ * This function sets the compare value of the lower limitation for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value Setting value.
+ */
+static inline void ADC_HAL_SetHwCmpValue1(uint32_t baseAddr, uint16_t value)
+{
+ BW_ADC_CV1_CV(baseAddr,value);
+}
+
+/*!
+ * @brief Sets the compare value of the higher limitation for the ADC module.
+ *
+ * This function sets the compare value of the higher limitation for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value Setting value.
+ */
+static inline void ADC_HAL_SetHwCmpValue2(uint32_t baseAddr, uint16_t value)
+{
+ BW_ADC_CV2_CV(baseAddr,value);
+}
+
+/*!
+ * @brief Checks whether the converter is active for the ADC module.
+ *
+ * This function checks whether the converter is active for the ADC
+ * module. If it is dis-asserted when the conversion is completed, one of the
+ * completed flag is asserted for the indicated group mux. See the
+ * "ADC_HAL_GetChnConvCompletedCmd()".
+ *
+ * @param baseAddr Register base address for the module.
+ * @return Assertion of that the converter is active.
+ */
+static inline bool ADC_HAL_GetConvActiveCmd(uint32_t baseAddr)
+{
+ return (1U == BR_ADC_SC2_ADACT(baseAddr) );
+}
+
+/*!
+ * @brief Switches to enable the hardware trigger mode for the ADC module.
+ *
+ * This function switches to enable the hardware trigger mode for the ADC
+ * module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHwTriggerCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC2_ADTRG(baseAddr,(enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Switches to enable the hardware comparator for the ADC module.
+ *
+ * This function switches to enable the hardware comparator for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHwCmpCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC2_ACFE(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Switches to enable the setting that is greater than the hardware comparator.
+ *
+ * This function switches to enable the setting that is greater than the
+ * hardware comparator.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHwCmpGreaterCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC2_ACFGT(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Switches to enable the setting of the range for hardware comparator.
+ *
+ * This function switches to enable the setting of range for the hardware
+ * comparator.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHwCmpRangeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC2_ACREN(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Configures the asserted range of the hardware comparator for the ADC module.
+ *
+ * This function configures the asserted range of the hardware comparator for the
+ * ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of range mode, see to "adc_hw_cmp_range_mode_t".
+ */
+void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode);
+
+#if FSL_FEATURE_ADC_HAS_DMA
+
+/*!
+ * @brief Switches to enable the DMA for the ADC module.
+ *
+ * This function switches to enable the DMA for the ADC module. When enabled, the
+ * DMA request is asserted during the ADC conversion complete event, which is noted
+ * by the assertion of any of the ADC channel completed flags.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC2_DMAEN(baseAddr, (enable ? 1U : 0U) );
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_DMA */
+
+/*!
+ * @brief Selects the reference voltage source for the ADC module.
+ *
+ * This function selects the reference voltage source for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of asserted the feature.
+ */
+static inline void ADC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, adc_ref_volt_src_mode_t mode)
+{
+ BW_ADC_SC2_REFSEL(baseAddr, (uint32_t)mode );
+}
+
+#if FSL_FEATURE_ADC_HAS_CALIBRATION
+
+/*!
+ * @brief Switches to enable the hardware calibration for the ADC module.
+ *
+ * This function launches the hardware calibration for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetAutoCalibrationCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC3_CAL(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Gets the hardware calibration status for the ADC module.
+ *
+ * This function gets the status whether the hardware calibration is active
+ * for the ADC module. The return value holds on as asserted during the hardware
+ * calibration. Then, it is cleared and dis-asserted after the
+ * calibration.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline bool ADC_HAL_GetAutoCalibrationActiveCmd(uint32_t baseAddr)
+{
+ return (1U == BR_ADC_SC3_CAL(baseAddr) );
+}
+
+/*!
+ * @brief Gets the hardware calibration status for the ADC module.
+ *
+ * This function gets the status whether the hardware calibration has failed
+ * for the ADC module. The return value is asserted if there is anything wrong
+ * with the hardware calibration.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline bool ADC_HAL_GetAutoCalibrationFailedCmd(uint32_t baseAddr)
+{
+ return (1U == BR_ADC_SC3_CALF(baseAddr) );
+}
+
+/*!
+ * @brief Gets and calculates the plus side calibration parameter from the auto calibration.
+ *
+ * This function gets the values of CLP0 - CLP4 and CLPS internally,
+ * accumulates them, and returns the value that can be used to be set in the PG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration is complete.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return value that can be set into PG directly.
+ */
+uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr);
+
+/*!
+ * @brief Sets the plus side gain calibration value for the ADC module.
+ *
+ * This function sets the plus side gain calibration value for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value Setting value for plus side gain.
+ */
+static inline void ADC_HAL_SetPlusSideGainValue(uint32_t baseAddr, uint16_t value)
+{
+ BW_ADC_PG_PG(baseAddr, value);
+}
+
+#if FSL_FEATURE_ADC_HAS_DIFF_MODE
+
+/*!
+ * @brief Gets and calculates the minus side calibration parameter from the auto calibration.
+ *
+ * This function gets the values of CLM0 - CLM4 and CLMS internally,
+ * accumulates them, and returns the value that can be used to be set in the MG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration is complete.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return value that can be set into MG directly.
+ */
+uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr);
+
+/*!
+ * @brief Sets the minus side gain calibration value for the ADC module.
+ *
+ * This function sets the minus side gain calibration value for the ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value Setting value for minus side gain.
+ */
+static inline void ADC_HAL_SetMinusSideGainValue(uint32_t baseAddr, uint16_t value)
+{
+ BW_ADC_MG_MG(baseAddr, value);
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
+
+#endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */
+
+#if FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION
+
+/*!
+ * @brief Gets the offset correction value for the ADC module.
+ *
+ * This function gets the offset correction value for the ADC module.
+ * When auto calibration is executed, the OFS register holds the new value
+ * generated by the calibration. It can be left as default or modified
+ * according to the use case.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return current value for OFS.
+ */
+static inline uint16_t ADC_HAL_GetOffsetValue(uint32_t baseAddr)
+{
+ return (uint16_t)(BR_ADC_OFS_OFS(baseAddr) );
+}
+
+/*!
+ * @brief Sets the offset correction value for the ADC module.
+ *
+ * This function sets the offset correction value for the ADC module. The ADC
+ * offset correction register (OFS) contains the user-selected or calibration-generated
+ * offset error correction value. The value in the offset correction
+ * registers (OFS) is subtracted from the conversion and the result is
+ * transferred into the result registers (Rn). If the result is above the
+ * maximum or below the minimum result value, it is forced to the appropriate
+ * limit for the current mode of operation.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value Setting value for OFS.
+ */
+static inline void ADC_HAL_SetOffsetValue(uint32_t baseAddr, uint16_t value)
+{
+ BW_ADC_OFS_OFS(baseAddr, value);
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION */
+
+/*!
+ * @brief Switches to enable the continuous conversion mode for the ADC module.
+ *
+ * This function switches to enable the continuous conversion mode for the ADC
+ * module. Once enabled, continuous conversions, or sets of conversions if the
+ * hardware average function, is enabled after initiating a conversion.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetContinuousConvCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC3_ADCO(baseAddr, (enable ? 1U : 0U) );
+}
+
+#if FSL_FEATURE_ADC_HAS_HW_AVERAGE
+
+/*!
+ * @brief Switches to enable the hardware average for the ADC module.
+ *
+ * This function switches to enable the hardware average for the ADC module.
+ * Once enabled, the conversion does not stop before the average
+ * count has been reached.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC_HAL_SetHwAverageCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_SC3_AVGE(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Selects the hardware average mode for the ADC module.
+ *
+ * This function switches to select the hardware average mode for the ADC
+ * module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of hardware average count mode, see to "adc_hw_average_count_mode_t".
+ */
+static inline void ADC_HAL_SetHwAverageMode(uint32_t baseAddr, adc_hw_average_count_mode_t mode)
+{
+ BW_ADC_SC3_AVGS(baseAddr, (uint32_t)mode );
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */
+
+#if FSL_FEATURE_ADC_HAS_PGA
+
+/*!
+ * @brief Switches to enable the Programmable Gain Amplifier for ADC module.
+ *
+ * This function enables the PGA for the ADC module. The Programmable Gain
+ * Amplifier (PGA) is designed to increase the dynamic range by amplifying the
+ * low-amplitude signals before they are fed to the 16 bit SAR ADC.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted feature.
+ */
+static inline void ADC_HAL_SetPgaCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_PGA_PGAEN(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Switches to enable the PGA chopping mode for the ADC module.
+ *
+ * This function switches to enable the PGA chopping mode for the ADC module.
+ * The PGA employs chopping to remove/reduce offset and 1/f noise and offers an
+ * offset measurement configuration that aids the offset calibration.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted feature.
+ */
+static inline void ADC_HAL_SetPgaChoppingCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_PGA_PGACHPb(baseAddr, (enable ? 0U : 1U) );
+}
+
+/*!
+ * @brief Switches to enable the PGA working in low power mode for the ADC module.
+ *
+ * This function switches to enable the PGA working in low power mode for
+ * ADC module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted feature.
+ */
+static inline void ADC_HAL_SetPgaLowPowerCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_PGA_PGALPb(baseAddr, (enable ? 0U : 1U) );
+}
+
+/*!
+ * @brief Selects the amplifier mode for the PGA.
+ *
+ * This function selects the amplifier mode for the PGA.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of asserted feature. See to "adc_pga_gain_mode_t".
+ */
+static inline void ADC_HAL_SetPgaGainMode(uint32_t baseAddr, adc_pga_gain_mode_t mode)
+{
+ BW_ADC_PGA_PGAG(baseAddr, (uint32_t)mode );
+}
+
+/*!
+ * @brief Switches to enable the offset measurement mode for the ADC module.
+ *
+ * This function switches to enable the offset measurement mode for the ADC
+ * module. When asserted, the PGA disconnects from the external inputs and
+ * auto-configures into offset measurement mode. With this function asserted,
+ * run the ADC in recommended settings and enable maximum hardware averaging
+ * to get the PGA offset number. The output is the (PGA offset * (64+1))
+ * for a given setting.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable Switcher to asserted feature.
+ */
+static inline void ADC_HAL_SetPgaOffsetMeasurementCmd(uint32_t baseAddr, bool enable)
+{
+ BW_ADC_PGA_PGAOFSM(baseAddr, (enable ? 1U : 0U) );
+}
+
+#endif /* FSL_FEATURE_ADC_HAS_PGA */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_ADC_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,119 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140516 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_FLEXCAN_FEATURES_H__) +#define __FSL_FLEXCAN_FEATURES_H__ + +#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) + /* @brief Message buffer size */ + #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) + /* @brief Has doze mode support (register bit field MCR[DOZE]). */ + #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) + /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ + #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) + /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) + /* @brief Has extended bit timing register (register CBT). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) + /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ + #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) + /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ + #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) + /* @brief Number of interrupt vectors. */ + #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Message buffer size */ + #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) + /* @brief Has doze mode support (register bit field MCR[DOZE]). */ + #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) + /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ + #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0) + /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) + /* @brief Has extended bit timing register (register CBT). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) + /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ + #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) + /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ + #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (0) + /* @brief Number of interrupt vectors. */ + #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Message buffer size */ + #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) + /* @brief Has doze mode support (register bit field MCR[DOZE]). */ + #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) + /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ + #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) + /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) + /* @brief Has extended bit timing register (register CBT). */ + #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (1) + /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ + #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) + /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ + #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) + /* @brief Number of interrupt vectors. */ + #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) +#else + #define MBED_NO_FLEXCAN +#endif + +#endif /* __FSL_FLEXCAN_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1845 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_flexcan_hal.h"
+
+#ifndef MBED_NO_FLEXCAN
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format A extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format A extended shift.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format A standard mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format A standard shift.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x3FF8U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B standard mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B standard shift1.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format B standard shift2.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format C mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format C shift1.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format C shift2.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format C shift3.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U) /*!< FlexCAN RX FIFO ID filter*/
+ /*! format C shift4.*/
+#define FLEXCAN_ALL_INT (0x0007U) /*!< Masks for wakeup, error, bus off*/
+ /*! interrupts*/
+#define FLEXCAN_BYTE_DATA_FIELD_MASK (0xFFU) /*!< Masks for byte data field.*/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Enable
+ * Description : Enable FlexCAN module.
+ * This function will enable FlexCAN module clock.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Enable(uint32_t canBaseAddr)
+{
+ /* Check for low power mode*/
+ if(BR_CAN_MCR_LPMACK(canBaseAddr))
+ {
+ /* Enable clock*/
+ HW_CAN_MCR_CLR(canBaseAddr, BM_CAN_MCR_MDIS);
+ /* Wait until enabled*/
+ while (BR_CAN_MCR_LPMACK(canBaseAddr)){}
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Disable
+ * Description : Disable FlexCAN module.
+ * This function will disable FlexCAN module clock.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Disable(uint32_t canBaseAddr)
+{
+ /* To access the memory mapped registers*/
+ /* Entre disable mode (hard reset).*/
+ if(BR_CAN_MCR_MDIS(canBaseAddr) == 0x0)
+ {
+ /* Clock disable (module)*/
+ BW_CAN_MCR_MDIS(canBaseAddr, 0x1);
+
+ /* Wait until disable mode acknowledged*/
+ while (!(BR_CAN_MCR_LPMACK(canBaseAddr))){}
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SelectClock
+ * Description : Select FlexCAN clock source.
+ * This function will select either internal bus clock or external clock as
+ * FlexCAN clock source.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SelectClock(
+ uint32_t canBaseAddr,
+ flexcan_clk_source_t clk)
+{
+ if (clk == kFlexCanClkSource_Ipbus)
+ {
+ /* Internal bus clock (fsys/2)*/
+ BW_CAN_CTRL1_CLKSRC(canBaseAddr, 0x1);
+ }
+ else if (clk == kFlexCanClkSource_Osc)
+ {
+ /* External clock*/
+ BW_CAN_CTRL1_CLKSRC(canBaseAddr, 0x0);
+ }
+ else
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Init
+ * Description : Initialize FlexCAN module.
+ * This function will reset FlexCAN module, set maximum number of message
+ * buffers, initialize all message buffers as inactive, enable RX FIFO
+ * if needed, mask all mask bits, and disable all MB interrupts.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Init(uint32_t canBaseAddr, const flexcan_user_config_t *data)
+{
+ uint32_t i;
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ assert(data);
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ /* Reset the FLEXCAN*/
+ BW_CAN_MCR_SOFTRST(canBaseAddr, 0x1);
+
+ /* Wait for reset cycle to complete*/
+ while (BR_CAN_MCR_SOFTRST(canBaseAddr)){}
+
+ /* Set Freeze, Halt*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* check for freeze Ack*/
+ while ((!BR_CAN_MCR_FRZACK(canBaseAddr)) ||
+ (!BR_CAN_MCR_NOTRDY(canBaseAddr))){}
+
+ /* Set maximum number of message buffers*/
+ BW_CAN_MCR_MAXMB(canBaseAddr, data->max_num_mb);
+
+ /* Initialize all message buffers as inactive*/
+ for (i = 0; i < data->max_num_mb; i++)
+ {
+ flexcan_reg_ptr->MB[i].CS = 0x0;
+ flexcan_reg_ptr->MB[i].ID = 0x0;
+ flexcan_reg_ptr->MB[i].WORD0 = 0x0;
+ flexcan_reg_ptr->MB[i].WORD1 = 0x0;
+ }
+
+ /* Enable RX FIFO if need*/
+ if (data->is_rx_fifo_needed)
+ {
+ /* Enable RX FIFO*/
+ BW_CAN_MCR_RFEN(canBaseAddr, 0x1);
+ /* Set the number of the RX FIFO filters needed*/
+ BW_CAN_CTRL2_RFFN(canBaseAddr, data->num_id_filters);
+ /* RX FIFO global mask*/
+ HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RXFGMASK_FGM_MASK));
+ for (i = 0; i < data->max_num_mb; i++)
+ {
+ /* RX individual mask*/
+ HW_CAN_RXIMRn_WR(canBaseAddr, i, CAN_ID_EXT(CAN_RXIMR_MI_MASK));
+ }
+ }
+
+ /* Rx global mask*/
+ HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RXMGMASK_MG_MASK));
+
+ /* Rx reg 14 mask*/
+ HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RX14MASK_RX14M_MASK));
+
+ /* Rx reg 15 mask*/
+ HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RX15MASK_RX15M_MASK));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while(BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ /* Disable all MB interrupts*/
+ HW_CAN_IMASK1_WR(canBaseAddr, 0x0);
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetTimeSegments
+ * Description : Set FlexCAN time segments.
+ * This function will set all FlexCAN time segments which define the length of
+ * Propagation Segment in the bit time, the length of Phase Buffer Segment 2 in
+ * the bit time, the length of Phase Buffer Segment 1 in the bit time, the ratio
+ * between the PE clock frequency and the Serial Clock (Sclock) frequency, and
+ * the maximum number of time quanta that a bit time can be changed by one
+ * resynchronization. (One time quantum is equal to the Sclock period.)
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetTimeSegments(
+ uint32_t canBaseAddr,
+ flexcan_time_segment_t *time_seg)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while(!(BR_CAN_MCR_FRZACK(canBaseAddr))) {}
+
+ /* Set FlexCAN time segments*/
+ HW_CAN_CTRL1_CLR(canBaseAddr, (CAN_CTRL1_PROPSEG_MASK | CAN_CTRL1_PSEG2_MASK |
+ CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PRESDIV_MASK) |
+ CAN_CTRL1_RJW_MASK);
+ HW_CAN_CTRL1_SET(canBaseAddr, (CAN_CTRL1_PROPSEG(time_seg->propseg) |
+ CAN_CTRL1_PSEG2(time_seg->pseg2) |
+ CAN_CTRL1_PSEG1(time_seg->pseg1) |
+ CAN_CTRL1_PRESDIV(time_seg->pre_divider) |
+ CAN_CTRL1_RJW(time_seg->rjw)));
+
+ /* De-assert Freeze mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while(BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetTimeSegments
+ * Description : Get FlexCAN time segments.
+ * This function will get all FlexCAN time segments defined.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_GetTimeSegments(
+ uint32_t canBaseAddr,
+ flexcan_time_segment_t *time_seg)
+{
+ time_seg->pre_divider = BR_CAN_CTRL1_PRESDIV(canBaseAddr);
+ time_seg->propseg = BR_CAN_CTRL1_PROPSEG(canBaseAddr);
+ time_seg->pseg1 = BR_CAN_CTRL1_PSEG1(canBaseAddr);
+ time_seg->pseg2 = BR_CAN_CTRL1_PSEG2(canBaseAddr);
+ time_seg->rjw = BR_CAN_CTRL1_RJW(canBaseAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMbTx
+ * Description : Configure a message buffer for transmission.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will copy user's buffer into the
+ * message buffer data area and configure the message buffer as required for
+ * transmission.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetMbTx(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_code_status_t *cs,
+ uint32_t msg_id,
+ uint8_t *mb_data)
+{
+ uint32_t i;
+ uint32_t val1, val2 = 1, temp, temp1;
+
+ assert(data);
+
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Check if RX FIFO is enabled*/
+ if (BR_CAN_MCR_RFEN(canBaseAddr))
+ {
+ /* Get the number of RX FIFO Filters*/
+ val1 = (BR_CAN_CTRL2_RFFN(canBaseAddr));
+ /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+ /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+ /* Every number of RFFN means 8 number of RX FIFO filters*/
+ /* and every 4 number of RX FIFO filters occupied one MB*/
+ val2 = 6 + (val1 + 1) * 8 / 4;
+
+ if (mb_idx <= (val2 - 1))
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+ }
+
+ /* Copy user's buffer into the message buffer data area*/
+ if (mb_data != NULL)
+ {
+ flexcan_reg_ptr->MB[mb_idx].WORD0 = 0x0;
+ flexcan_reg_ptr->MB[mb_idx].WORD1 = 0x0;
+
+ for (i = 0; i < cs->data_length; i++ )
+ {
+ temp1 = (*(mb_data + i));
+ if (i < 4)
+ {
+ temp = temp1 << ((3 - i) * 8);
+ flexcan_reg_ptr->MB[mb_idx].WORD0 |= temp;
+ }
+ else
+ {
+ temp = temp1 << ((7 - i) * 8);
+ flexcan_reg_ptr->MB[mb_idx].WORD1 |= temp;
+ }
+ }
+ }
+
+ /* Set the ID according the format structure*/
+ if (cs->msg_id_type == kFlexCanMbId_Ext)
+ {
+ /* ID [28-0]*/
+ flexcan_reg_ptr->MB[mb_idx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
+ flexcan_reg_ptr->MB[mb_idx].ID |= (msg_id & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
+
+ /* Set IDE*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_IDE_MASK;
+
+ /* Clear SRR bit*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_SRR_MASK;
+
+ /* Set the length of data in bytes*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_DLC(cs->data_length);
+
+ /* Set MB CODE*/
+ /* Reset the code*/
+ if (cs->code != kFlexCanTX_NotUsed)
+ {
+ if (cs->code == kFlexCanTX_Remote)
+ {
+ /* Set RTR bit*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_RTR_MASK;
+ cs->code = kFlexCanTX_Data;
+ }
+
+ /* Reset the code*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_CODE_MASK);
+
+ /* Activating message buffer*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code);
+ }
+ }
+ else if(cs->msg_id_type == kFlexCanMbId_Std)
+ {
+ /* ID[28-18]*/
+ flexcan_reg_ptr->MB[mb_idx].ID &= ~CAN_ID_STD_MASK;
+ flexcan_reg_ptr->MB[mb_idx].ID |= CAN_ID_STD(msg_id);
+
+ /* make sure IDE and SRR are not set*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
+
+ /* Set the length of data in bytes*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= (cs->data_length) << CAN_CS_DLC_SHIFT;
+
+ /* Set MB CODE*/
+ if (cs->code != kFlexCanTX_NotUsed)
+ {
+ if (cs->code == kFlexCanTX_Remote)
+ {
+ /* Set RTR bit*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_RTR_MASK;
+ cs->code = kFlexCanTX_Data;
+ }
+
+ /* Reset the code*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK;
+
+ /* Set the code*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code);
+ }
+ }
+ else
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMbRx
+ * Description : Configure a message buffer for receiving.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will configure the message buffer as
+ * required for receiving.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetMbRx(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_code_status_t *cs,
+ uint32_t msg_id)
+{
+ uint32_t val1, val2 = 1;
+
+ assert(data);
+
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Check if RX FIFO is enabled*/
+ if (BR_CAN_MCR_RFEN(canBaseAddr))
+ {
+ /* Get the number of RX FIFO Filters*/
+ val1 = BR_CAN_CTRL2_RFFN(canBaseAddr);
+ /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+ /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+ /* Every number of RFFN means 8 number of RX FIFO filters*/
+ /* and every 4 number of RX FIFO filters occupied one MB*/
+ val2 = 6 + (val1 + 1) * 8 / 4;
+
+ if (mb_idx <= (val2 - 1))
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+ }
+
+ /* Set the ID according the format structure*/
+ if (cs->msg_id_type == kFlexCanMbId_Ext)
+ {
+ /* Set IDE*/
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_IDE_MASK;
+
+ /* Clear SRR bit*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_SRR_MASK;
+
+ /* Set the length of data in bytes*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_DLC(cs->data_length);
+
+ /* ID [28-0]*/
+ flexcan_reg_ptr->MB[mb_idx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
+ flexcan_reg_ptr->MB[mb_idx].ID |= (msg_id & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
+
+ /* Set MB CODE*/
+ if (cs->code != kFlexCanRX_NotUsed)
+ {
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code);
+ }
+ }
+ else if(cs->msg_id_type == kFlexCanMbId_Std)
+ {
+ /* Make sure IDE and SRR are not set*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
+
+ /* Set the length of data in bytes*/
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= (cs->data_length) << CAN_CS_DLC_SHIFT;
+
+ /* ID[28-18]*/
+ flexcan_reg_ptr->MB[mb_idx].ID &= ~CAN_ID_STD_MASK;
+ flexcan_reg_ptr->MB[mb_idx].ID |= CAN_ID_STD(msg_id);
+
+ /* Set MB CODE*/
+ if (cs->code != kFlexCanRX_NotUsed)
+ {
+ flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK;
+ flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code);
+ }
+ }
+ else
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetMb
+ * Description : Get a message buffer field values.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will get the message buffer field
+ * values and copy the MB data field into user's buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_GetMb(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_t *mb)
+{
+ uint32_t i;
+ uint32_t val1, val2 = 1;
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ assert(data);
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Check if RX FIFO is enabled*/
+ if (BR_CAN_MCR_RFEN(canBaseAddr))
+ {
+ /* Get the number of RX FIFO Filters*/
+ val1 = BR_CAN_CTRL2_RFFN(canBaseAddr);
+ /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+ /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+ /* Every number of RFFN means 8 number of RX FIFO filters*/
+ /* and every 4 number of RX FIFO filters occupied one MB*/
+ val2 = 6 + (val1 + 1) * 8 / 4;
+
+ if (mb_idx <= (val2 - 1))
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+ }
+
+ /* Get a MB field values*/
+ mb->cs = flexcan_reg_ptr->MB[mb_idx].CS;
+ if ((mb->cs) & CAN_CS_IDE_MASK)
+ {
+ mb->msg_id = flexcan_reg_ptr->MB[mb_idx].ID;
+ }
+ else
+ {
+ mb->msg_id = (flexcan_reg_ptr->MB[mb_idx].ID) >> CAN_ID_STD_SHIFT;
+ }
+
+ /* Copy MB data field into user's buffer*/
+ for (i = 0 ; i < kFlexCanMessageSize ; i++)
+ {
+ if (i < 4)
+ {
+ mb->data[3 - i] = ((flexcan_reg_ptr->MB[mb_idx].WORD0) >> (i * 8)) &
+ FLEXCAN_BYTE_DATA_FIELD_MASK;
+ }
+ else
+ {
+ mb->data[11 - i] = ((flexcan_reg_ptr->MB[mb_idx].WORD1) >> ((i - 4) * 8)) &
+ FLEXCAN_BYTE_DATA_FIELD_MASK;
+ }
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_LockRxMb
+ * Description : Lock the RX message buffer.
+ * This function will the RX message buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_LockRxMb(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx)
+{
+ assert(data);
+
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Lock the mailbox*/
+ flexcan_reg_ptr->MB[mb_idx].CS;
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableRxFifo
+ * Description : Enable Rx FIFO feature.
+ * This function will enable the Rx FIFO feature.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableRxFifo(uint32_t canBaseAddr)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* Enable RX FIFO*/
+ BW_CAN_MCR_RFEN(canBaseAddr, 0x1);
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableRxFifo
+ * Description : Disable Rx FIFO feature.
+ * This function will disable the Rx FIFO feature.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableRxFifo(uint32_t canBaseAddr)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* Disable RX FIFO*/
+ BW_CAN_MCR_RFEN(canBaseAddr, 0x0);
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoFiltersNumber
+ * Description : Set the number of Rx FIFO filters.
+ * This function will define the number of Rx FIFO filters.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoFiltersNumber(
+ uint32_t canBaseAddr,
+ uint32_t number)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* Set the number of RX FIFO ID filters*/
+ BW_CAN_CTRL2_RFFN(canBaseAddr, number);
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMaxMbNumber
+ * Description : Set the number of the last Message Buffers.
+ * This function will define the number of the last Message Buffers
+ *
+*END**************************************************************************/
+void FLEXCAN_HAL_SetMaxMbNumber(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data)
+{
+ assert(data);
+
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* Set the maximum number of MBs*/
+ BW_CAN_MCR_MAXMB(canBaseAddr, data->max_num_mb);
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetIdFilterTableElements
+ * Description : Set ID filter table elements.
+ * This function will set up ID filter table elements.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetIdFilterTableElements(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ flexcan_rx_fifo_id_element_format_t id_format,
+ flexcan_id_table_t *id_filter_table)
+{
+ uint32_t i, j;
+ uint32_t val1, val2, val;
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ assert(data);
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ switch(id_format)
+ {
+ case (kFlexCanRxFifoIdElementFormat_A):
+ /* One full ID (standard and extended) per ID Filter Table element.*/
+ BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_A);
+ if (id_filter_table->is_remote_mb)
+ {
+ val = 1U << 31U;
+ }
+ if (id_filter_table->is_extended_mb)
+ {
+ val |= 1 << 30;
+ j = 0;
+ for (i = 0; i < (data->num_id_filters + 1) * 8; i += 4)
+ {
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS = val +
+ ((*(id_filter_table->id_filter + i)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID = val +
+ ((*(id_filter_table->id_filter + i + 1)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val +
+ ((*(id_filter_table->id_filter + i + 2)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val +
+ ((*(id_filter_table->id_filter + i + 3)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK);
+ j++;
+ }
+ }
+ else
+ {
+ j = 0;
+ for (i = 0; i < (data->num_id_filters + 1) * 8; i += 4)
+ {
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS = val +
+ ((*(id_filter_table->id_filter + i)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID = val +
+ ((*(id_filter_table->id_filter + i + 1)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val +
+ ((*(id_filter_table->id_filter + i + 2)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val +
+ ((*(id_filter_table->id_filter + i + 3)) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK);
+ j++;
+ }
+ }
+ break;
+ case (kFlexCanRxFifoIdElementFormat_B):
+ /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/
+ /* per ID Filter Table element.*/
+ BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_B);
+ if (id_filter_table->is_remote_mb)
+ {
+ val1 = 1U << 31U;
+ val2 = 1 << 15;
+ }
+ if (id_filter_table->is_extended_mb)
+ {
+ val1 |= 1 << 30;
+ val2 |= 1 << 14;
+ j = 0;
+ for (i = 0; i < (data->num_id_filters + 1) * 8; i += 8)
+ {
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS = val1 +
+ ((*(id_filter_table->id_filter + i)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS |= val2 +
+ ((*(id_filter_table->id_filter + i + 1)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID = val1 +
+ ((*(id_filter_table->id_filter + i + 2)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID |= val2 +
+ ((*(id_filter_table->id_filter + i + 3)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val1 +
+ ((*(id_filter_table->id_filter + i + 4)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= val2 +
+ ((*(id_filter_table->id_filter + i + 5)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val1 +
+ ((*(id_filter_table->id_filter + i + 6)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= val2 +
+ ((*(id_filter_table->id_filter + i + 7)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2);
+ j++;
+ }
+ }
+ else
+ {
+ j = 0;
+ for (i = 0; i < (data->num_id_filters + 1) * 8; i += 8)
+ {
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS = val1 +
+ (((*(id_filter_table->id_filter + i)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS |= val2 +
+ (((*(id_filter_table->id_filter + i + 1)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID = val1 +
+ (((*(id_filter_table->id_filter + i + 2)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID |= val2 +
+ (((*(id_filter_table->id_filter + i + 3)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val1 +
+ (((*(id_filter_table->id_filter + i + 4)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= val2 +
+ (((*(id_filter_table->id_filter + i + 5)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val1 +
+ (((*(id_filter_table->id_filter + i + 6)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= val2 +
+ (((*(id_filter_table->id_filter + i + 7)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2);
+ j++;
+ }
+ }
+ break;
+ case (kFlexCanRxFifoIdElementFormat_C):
+ /* Four partial 8-bit Standard IDs per ID Filter Table element.*/
+ BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_C);
+ j = 0;
+ for (i = 0; i < (data->num_id_filters + 1) * 8; i += 16)
+ {
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS = ((*(id_filter_table->id_filter + i)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 1)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2);
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 2)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3);
+ flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 3)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID = ((*(id_filter_table->id_filter + i + 4)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 5)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 6)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3);
+ flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 7)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = ((*(id_filter_table->id_filter + i + 8)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 9)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 10)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 11)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4);
+
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = ((*(id_filter_table->id_filter + i + 12)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 13)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 14)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3);
+ flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 15)) &
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK <<
+ FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4);
+
+ j++;
+ }
+ break;
+ case (kFlexCanRxFifoIdElementFormat_D):
+ /* All frames rejected.*/
+ BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_D);
+ break;
+ default:
+ return kStatus_FLEXCAN_InvalidArgument;
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifo
+ * Description : Confgure RX FIFO ID filter table elements.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxFifo(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ flexcan_rx_fifo_id_element_format_t id_format,
+ flexcan_id_table_t *id_filter_table)
+{
+ assert(data);
+
+ if (!data->is_rx_fifo_needed)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ /* Set RX FIFO ID filter table elements*/
+ return FLEXCAN_HAL_SetIdFilterTableElements(canBaseAddr, data, id_format, id_filter_table);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableMbInt
+ * Description : Enable the corresponding Message Buffer interrupt.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_EnableMbInt(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx)
+{
+ assert(data);
+ uint32_t temp;
+
+ if ( mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Enable the corresponding message buffer Interrupt*/
+ temp = 0x1 << mb_idx;
+ HW_CAN_IMASK1_SET(canBaseAddr, temp);
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableMbInt
+ * Description : Disable the corresponding Message Buffer interrupt.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_DisableMbInt(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx)
+{
+ assert(data);
+ uint32_t temp;
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Disable the corresponding message buffer Interrupt*/
+ temp = 0x1 << mb_idx;
+ HW_CAN_IMASK1_CLR(canBaseAddr, temp);
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableErrInt
+ * Description : Enable the error interrupts.
+ * This function will enable Error interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableErrInt(uint32_t canBaseAddr)
+{
+ /* Enable Error interrupt*/
+ BW_CAN_CTRL1_ERRMSK(canBaseAddr, 0x1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableErrorInt
+ * Description : Disable the error interrupts.
+ * This function will disable Error interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableErrInt(uint32_t canBaseAddr)
+{
+ /* Disable Error interrupt*/
+ BW_CAN_CTRL1_ERRMSK(canBaseAddr, 0x0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableBusOffInt
+ * Description : Enable the Bus off interrupts.
+ * This function will enable Bus Off interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableBusOffInt(uint32_t canBaseAddr)
+{
+ /* Enable Bus Off interrupt*/
+ BW_CAN_CTRL1_BOFFMSK(canBaseAddr, 0x1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableBusOffInt
+ * Description : Disable the Bus off interrupts.
+ * This function will disable Bus Off interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableBusOffInt(uint32_t canBaseAddr)
+{
+ /* Disable Bus Off interrupt*/
+ BW_CAN_CTRL1_BOFFMSK(canBaseAddr, 0x0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableWakeupInt
+ * Description : Enable the wakeup interrupts.
+ * This function will enable Wake up interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableWakeupInt(uint32_t canBaseAddr)
+{
+ /* Enable Wake Up interrupt*/
+ BW_CAN_MCR_WAKMSK(canBaseAddr, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableWakeupInt
+ * Description : Disable the wakeup interrupts.
+ * This function will disable Wake up interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableWakeupInt(uint32_t canBaseAddr)
+{
+ /* Disable Wake Up interrupt*/
+ BW_CAN_MCR_WAKMSK(canBaseAddr, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableTxWarningInt
+ * Description : Enable the TX warning interrupts.
+ * This function will enable TX warning interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableTxWarningInt(uint32_t canBaseAddr)
+{
+ /* Enable TX warning interrupt*/
+ BW_CAN_CTRL1_TWRNMSK(canBaseAddr, 0x1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableTxWarningInt
+ * Description : Disable the TX warning interrupts.
+ * This function will disable TX warning interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableTxWarningInt(uint32_t canBaseAddr)
+{
+ /* Disable TX warning interrupt*/
+ BW_CAN_CTRL1_TWRNMSK(canBaseAddr, 0x0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableRxWarningInt
+ * Description : Enable the RX warning interrupts.
+ * This function will enable RX warning interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableRxWarningInt(uint32_t canBaseAddr)
+{
+ /* Enable RX warning interrupt*/
+ BW_CAN_CTRL1_RWRNMSK(canBaseAddr, 0x1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableRxWarningInt
+ * Description : Disable the RX warning interrupts.
+ * This function will disable RX warning interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableRxWarningInt(uint32_t canBaseAddr)
+{
+ /* Disable RX warning interrupt*/
+ BW_CAN_CTRL1_RWRNMSK(canBaseAddr, 0x0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ExitFreezeMode
+ * Description : Exit of freeze mode.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_ExitFreezeMode(uint32_t canBaseAddr)
+{
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnterFreezeMode
+ * Description : Enter the freeze mode.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnterFreezeMode(uint32_t canBaseAddr)
+{
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetMbIntFlag
+ * Description : Get the corresponding message buffer interrupt flag.
+ *
+ *END**************************************************************************/
+uint8_t FLEXCAN_HAL_GetMbIntFlag(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx)
+{
+ assert(data);
+ assert(mb_idx < data->max_num_mb);
+ uint32_t temp;
+
+ /* Get the corresponding message buffer interrupt flag*/
+ temp = 0x1 << mb_idx;
+ if (HW_CAN_IFLAG1_RD(canBaseAddr) & temp)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetErrCounter
+ * Description : Get transmit error counter and receive error counter.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_GetErrCounter(
+ uint32_t canBaseAddr,
+ flexcan_berr_counter_t *err_cnt)
+{
+ /* Get transmit error counter and receive error counter*/
+ err_cnt->rxerr = HW_CAN_ECR(canBaseAddr).B.RXERRCNT;
+ err_cnt->txerr = HW_CAN_ECR(canBaseAddr).B.TXERRCNT;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ClearErrIntStatus
+ * Description : Clear all error interrupt status.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_ClearErrIntStatus(uint32_t canBaseAddr)
+{
+ if(HW_CAN_ESR1_RD(canBaseAddr) & FLEXCAN_ALL_INT)
+ {
+ HW_CAN_ESR1_SET(canBaseAddr, FLEXCAN_ALL_INT);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ReadFifo
+ * Description : Read Rx FIFO data.
+ * This function will copy MB[0] data field into user's buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_ReadFifo(
+ uint32_t canBaseAddr,
+ flexcan_mb_t *rx_fifo)
+{
+ uint32_t i;
+ volatile CAN_Type *flexcan_reg_ptr;
+
+ flexcan_reg_ptr = ((CAN_Type *)canBaseAddr);
+ if (NULL == flexcan_reg_ptr)
+ {
+ return (kStatus_FLEXCAN_InvalidArgument);
+ }
+
+ rx_fifo->cs = flexcan_reg_ptr->MB[0].CS;
+
+ if ((rx_fifo->cs) & CAN_CS_IDE_MASK)
+ {
+ rx_fifo->msg_id = flexcan_reg_ptr->MB[0].ID;
+ }
+ else
+ {
+ rx_fifo->msg_id = (flexcan_reg_ptr->MB[0].ID) >> CAN_ID_STD_SHIFT;
+ }
+
+ /* Copy MB[0] data field into user's buffer*/
+ for ( i=0 ; i < kFlexCanMessageSize ; i++ )
+ {
+ if (i < 4)
+ {
+ rx_fifo->data[3 - i] = ((flexcan_reg_ptr->MB[0].WORD0) >> (i * 8)) &
+ FLEXCAN_BYTE_DATA_FIELD_MASK;
+ }
+ else
+ {
+ rx_fifo->data[11 - i] = ((flexcan_reg_ptr->MB[0].WORD1) >> ((i - 4) * 8)) &
+ FLEXCAN_BYTE_DATA_FIELD_MASK;
+ }
+ }
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMaskType
+ * Description : Set RX masking type.
+ * This function will set RX masking type as RX global mask or RX individual
+ * mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetMaskType(
+ uint32_t canBaseAddr,
+ flexcan_rx_mask_type_t type)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* Set RX masking type (RX global mask or RX individual mask)*/
+ if (type == kFlexCanRxMask_Global)
+ {
+ /* Enable Global RX masking*/
+ BW_CAN_MCR_IRMQ(canBaseAddr, 0x0);
+ }
+ else
+ {
+ /* Enable Individual Rx Masking and Queue*/
+ BW_CAN_MCR_IRMQ(canBaseAddr, 0x1);
+ }
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoGlobalStdMask
+ * Description : Set Rx FIFO global mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoGlobalStdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 11 bit standard mask*/
+ HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_STD(std_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoGlobalExtMask
+ * Description : Set Rx FIFO global mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoGlobalExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 29-bit extended mask*/
+ HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxIndividualStdMask
+ * Description : Set Rx individual mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t * data,
+ uint32_t mb_idx,
+ uint32_t std_mask)
+{
+ assert(data);
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 11 bit standard mask*/
+ HW_CAN_RXIMRn_WR(canBaseAddr, mb_idx, CAN_ID_STD(std_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxIndividualExtMask
+ * Description : Set Rx individual mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t * data,
+ uint32_t mb_idx,
+ uint32_t ext_mask)
+{
+ assert(data);
+
+ if (mb_idx >= data->max_num_mb)
+ {
+ return (kStatus_FLEXCAN_OutOfRange);
+ }
+
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 29-bit extended mask*/
+ HW_CAN_RXIMRn_WR(canBaseAddr, mb_idx, CAN_ID_EXT(ext_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbGlobalStdMask
+ * Description : Set Rx Message Buffer global mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbGlobalStdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 11 bit standard mask*/
+ HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_STD(std_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf14StdMask
+ * Description : Set Rx Message Buffer 14 mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbBuf14StdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 11 bit standard mask*/
+ HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_STD(std_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf15StdMask
+ * Description : Set Rx Message Buffer 15 mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbBuf15StdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 11 bit standard mask*/
+ HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_STD(std_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbGlobalExtMask
+ * Description : Set Rx Message Buffer global mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbGlobalExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(HW_CAN_MCR_RD(canBaseAddr))){}
+
+ /* 29-bit extended mask*/
+ HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf14ExtMask
+ * Description : Set Rx Message Buffer 14 mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbBuf14ExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 29-bit extended mask*/
+ HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf15ExtMask
+ * Description : Set Rx Message Buffer 15 mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMbBuf15ExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask)
+{
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ /* 29-bit extended mask*/
+ HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask));
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableOperationMode
+ * Description : Enable a FlexCAN operation mode.
+ * This function will enable one of the modes listed in flexcan_operation_modes_t.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_EnableOperationMode(
+ uint32_t canBaseAddr,
+ flexcan_operation_modes_t mode)
+{
+ if (mode == kFlexCanFreezeMode)
+ {
+ /* Debug mode, Halt and Freeze*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ return (kStatus_FLEXCAN_Success);
+ }
+ else if (mode == kFlexCanDisableMode)
+ {
+ /* Debug mode, Halt and Freeze*/
+ BW_CAN_MCR_MDIS(canBaseAddr, 0x1);
+ return (kStatus_FLEXCAN_Success);
+ }
+
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ if (mode == kFlexCanNormalMode)
+ {
+ BW_CAN_MCR_SUPV(canBaseAddr, 0x0);
+ }
+ else if (mode == kFlexCanListenOnlyMode)
+ {
+ BW_CAN_CTRL1_LOM(canBaseAddr, 0x1);
+ }
+ else if (mode == kFlexCanLoopBackMode)
+ {
+ BW_CAN_CTRL1_LPB(canBaseAddr, 0x1);
+ }
+ else
+ {
+ return kStatus_FLEXCAN_InvalidArgument;
+ }
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableOperationMode
+ * Description : Disable a FlexCAN operation mode.
+ * This function will disable one of the modes listed in flexcan_operation_modes_t.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_DisableOperationMode(
+ uint32_t canBaseAddr,
+ flexcan_operation_modes_t mode)
+{
+ if (mode == kFlexCanFreezeMode)
+ {
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ return (kStatus_FLEXCAN_Success);
+ }
+ else if (mode == kFlexCanDisableMode)
+ {
+ /* Disable module mode*/
+ BW_CAN_MCR_MDIS(canBaseAddr, 0x0);
+ return (kStatus_FLEXCAN_Success);
+ }
+
+ /* Set Freeze mode*/
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x1);
+ BW_CAN_MCR_HALT(canBaseAddr, 0x1);
+
+ /* Wait for entering the freeze mode*/
+ while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){}
+
+ if (mode == kFlexCanNormalMode)
+ {
+ BW_CAN_MCR_SUPV(canBaseAddr, 0x1);
+ }
+ else if (mode == kFlexCanListenOnlyMode)
+ {
+ BW_CAN_CTRL1_LOM(canBaseAddr, 0x0);
+ }
+ else if (mode == kFlexCanLoopBackMode)
+ {
+ BW_CAN_CTRL1_LPB(canBaseAddr, 0x0);
+ }
+ else
+ {
+ return kStatus_FLEXCAN_InvalidArgument;
+ }
+
+ /* De-assert Freeze Mode*/
+ BW_CAN_MCR_HALT(canBaseAddr, 0x0);
+ BW_CAN_MCR_FRZ(canBaseAddr, 0x0);
+
+ /* Wait till exit of freeze mode*/
+ while (BR_CAN_MCR_FRZACK(canBaseAddr)){}
+
+ return (kStatus_FLEXCAN_Success);
+}
+
+#endif /* MBED_NO_FLEXCAN */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,837 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXCAN_HAL_H__
+#define __FSL_FLEXCAN_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_flexcan_features.h"
+#include "fsl_device_registers.h"
+
+#ifndef MBED_NO_FLEXCAN
+
+/*!
+ * @addtogroup flexcan_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief FlexCAN constants*/
+enum _flexcan_constants
+{
+ kFlexCanMessageSize = 8, /*!< FlexCAN message buffer data size in bytes*/
+};
+
+/*! @brief The Status enum is used to report current status of the FlexCAN interface.*/
+enum _flexcan_err_status
+{
+ kFlexCan_RxWrn = 0x0080, /*!< Reached warning level for RX errors*/
+ kFlexCan_TxWrn = 0x0100, /*!< Reached warning level for TX errors*/
+ kFlexCan_StfErr = 0x0200, /*!< Stuffing Error*/
+ kFlexCan_FrmErr = 0x0400, /*!< Form Error*/
+ kFlexCan_CrcErr = 0x0800, /*!< Cyclic Redundancy Check Error*/
+ kFlexCan_AckErr = 0x1000, /*!< Received no ACK on transmission*/
+ kFlexCan_Bit0Err = 0x2000, /*!< Unable to send dominant bit*/
+ kFlexCan_Bit1Err = 0x4000, /*!< Unable to send recessive bit*/
+};
+
+/*! @brief FlexCAN status return codes*/
+typedef enum _flexcan_status
+{
+ kStatus_FLEXCAN_Success = 0,
+ kStatus_FLEXCAN_OutOfRange,
+ kStatus_FLEXCAN_UnknownProperty,
+ kStatus_FLEXCAN_InvalidArgument,
+ kStatus_FLEXCAN_Fail,
+ kStatus_FLEXCAN_TimeOut,
+} flexcan_status_t;
+
+
+/*! @brief FlexCAN operation modes*/
+typedef enum _flexcan_operation_modes {
+ kFlexCanNormalMode, /*!< Normal mode or user mode*/
+ kFlexCanListenOnlyMode, /*!< Listen-only mode*/
+ kFlexCanLoopBackMode, /*!< Loop-back mode*/
+ kFlexCanFreezeMode, /*!< Freeze mode*/
+ kFlexCanDisableMode, /*!< Module disable mode*/
+} flexcan_operation_modes_t;
+
+/*! @brief FlexCAN message buffer CODE for Rx buffers*/
+typedef enum _flexcan_mb_code_rx {
+ kFlexCanRX_Inactive = 0x0, /*!< MB is not active.*/
+ kFlexCanRX_Full = 0x2, /*!< MB is full.*/
+ kFlexCanRX_Empty = 0x4, /*!< MB is active and empty.*/
+ kFlexCanRX_Overrun = 0x6, /*!< MB is overwritten into a full buffer.*/
+ kFlexCanRX_Busy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
+ /*! The CPU must not access the MB.*/
+ kFlexCanRX_Ranswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/
+ /*! and transmit a Response Frame in return.*/
+ kFlexCanRX_NotUsed = 0xF, /*!< Not used*/
+} flexcan_mb_code_rx_t;
+
+/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/
+typedef enum _flexcan_mb_code_tx {
+ kFlexCanTX_Inactive = 0x08, /*!< MB is not active.*/
+ kFlexCanTX_Abort = 0x09, /*!< MB is aborted.*/
+ kFlexCanTX_Data = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/
+ kFlexCanTX_Remote = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/
+ kFlexCanTX_Tanswer = 0x0E, /*!< MB is a TX Response Request Frame from.*/
+ /*! an incoming Remote Request Frame.*/
+ kFlexCanTX_NotUsed = 0xF, /*!< Not used*/
+} flexcan_mb_code_tx_t;
+
+/*! @brief FlexCAN message buffer transmission types*/
+typedef enum _flexcan_mb_transmission_type {
+ kFlexCanMBStatusType_TX, /*!< Transmit MB*/
+ kFlexCanMBStatusType_TXRemote, /*!< Transmit remote request MB*/
+ kFlexCanMBStatusType_RX, /*!< Receive MB*/
+ kFlexCanMBStatusType_RXRemote, /*!< Receive remote request MB*/
+ kFlexCanMBStatusType_RXTXRemote, /*!< FlexCAN remote frame receives remote request and*/
+ /*! transmits MB.*/
+} flexcan_mb_transmission_type_t;
+
+typedef enum _flexcan_rx_fifo_id_element_format {
+ kFlexCanRxFifoIdElementFormat_A, /*!< One full ID (standard and extended) per ID Filter Table*/
+ /*! element.*/
+ kFlexCanRxFifoIdElementFormat_B, /*!< Two full standard IDs or two partial 14-bit (standard and*/
+ /*! extended) IDs per ID Filter Table element.*/
+ kFlexCanRxFifoIdElementFormat_C, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/
+ /*! element.*/
+ kFlexCanRxFifoIdElementFormat_D, /*!< All frames rejected.*/
+} flexcan_rx_fifo_id_element_format_t;
+
+/*! @brief FlexCAN Rx FIFO filters number*/
+typedef enum _flexcan_rx_fifo_id_filter_number {
+ kFlexCanRxFifoIDFilters_8 = 0x0, /*!< 8 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_16 = 0x1, /*!< 16 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_24 = 0x2, /*!< 24 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_32 = 0x3, /*!< 32 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_40 = 0x4, /*!< 40 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_48 = 0x5, /*!< 48 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_56 = 0x6, /*!< 56 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_64 = 0x7, /*!< 64 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_72 = 0x8, /*!< 72 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_80 = 0x9, /*!< 80 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_88 = 0xA, /*!< 88 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_96 = 0xB, /*!< 96 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_104 = 0xC, /*!< 104 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_112 = 0xD, /*!< 112 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_120 = 0xE, /*!< 120 Rx FIFO Filters*/
+ kFlexCanRxFifoIDFilters_128 = 0xF /*!< 128 Rx FIFO Filters*/
+} flexcan_rx_fifo_id_filter_num_t;
+
+/*! @brief FlexCAN RX FIFO ID filter table structure*/
+typedef struct FLEXCANIdTable {
+ bool is_remote_mb; /*!< Remote frame*/
+ bool is_extended_mb; /*!< Extended frame*/
+ uint32_t *id_filter; /*!< Rx FIFO ID filter elements*/
+} flexcan_id_table_t;
+
+/*! @brief FlexCAN RX mask type.*/
+typedef enum _flexcan_rx_mask_type {
+ kFlexCanRxMask_Global, /*!< Rx global mask*/
+ kFlexCanRxMask_Individual, /*!< Rx individual mask*/
+} flexcan_rx_mask_type_t;
+
+/*! @brief FlexCAN MB ID type*/
+typedef enum _flexcan_mb_id_type {
+ kFlexCanMbId_Std, /*!< Standard ID*/
+ kFlexCanMbId_Ext, /*!< Extended ID*/
+} flexcan_mb_id_type_t;
+
+/*! @brief FlexCAN clock source*/
+typedef enum _flexcan_clk_source {
+ kFlexCanClkSource_Osc, /*!< Oscillator clock*/
+ kFlexCanClkSource_Ipbus, /*!< Peripheral clock*/
+} flexcan_clk_source_t;
+
+/*! @brief FlexCAN error interrupt types*/
+typedef enum _flexcan_int_type {
+ kFlexCanInt_Buf, /*!< OR'd message buffers interrupt*/
+ kFlexCanInt_Err, /*!< Error interrupt*/
+ kFlexCanInt_Boff, /*!< Bus off interrupt*/
+ kFlexCanInt_Wakeup, /*!< Wakeup interrupt*/
+ kFlexCanInt_Txwarning, /*!< TX warning interrupt*/
+ kFlexCanInt_Rxwarning, /*!< RX warning interrupt*/
+} flexcan_int_type_t;
+
+/*! @brief FlexCAN bus error counters*/
+typedef struct FLEXCANBerrCounter {
+ uint16_t txerr; /*!< Transmit error counter*/
+ uint16_t rxerr; /*!< Receive error counter*/
+} flexcan_berr_counter_t;
+
+/*! @brief FlexCAN MB code and status for transmit and receive */
+typedef struct FLEXCANMbCodeStatus {
+ uint32_t code; /*!< MB code for TX or RX buffers.
+ Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */
+ flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
+ uint32_t data_length; /*!< Length of Data in Bytes*/
+} flexcan_mb_code_status_t;
+
+/*! @brief FlexCAN message buffer structure*/
+typedef struct FLEXCANMb {
+ uint32_t cs; /*!< Code and Status*/
+ uint32_t msg_id; /*!< Message Buffer ID*/
+ uint8_t data[kFlexCanMessageSize]; /*!< Bytes of the FlexCAN message*/
+} flexcan_mb_t;
+
+/*! @brief FlexCAN configuration*/
+typedef struct FLEXCANUserConfig {
+ uint32_t max_num_mb; /*!< The maximum number of Message Buffers*/
+ flexcan_rx_fifo_id_filter_num_t num_id_filters; /*!< The number of Rx FIFO ID filters needed*/
+ bool is_rx_fifo_needed; /*!< 1 if needed; 0 if not*/
+} flexcan_user_config_t;
+
+/*! @brief FlexCAN timing related structures*/
+typedef struct FLEXCANTimeSegment {
+ uint32_t propseg; /*!< Propagation segment*/
+ uint32_t pseg1; /*!< Phase segment 1*/
+ uint32_t pseg2; /*!< Phase segment 2*/
+ uint32_t pre_divider; /*!< Clock pre divider*/
+ uint32_t rjw; /*!< Resync jump width*/
+} flexcan_time_segment_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Enables FlexCAN controller.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Enable(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables FlexCAN controller.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Disable(uint32_t canBaseAddr);
+
+/*!
+ * @brief Checks whether the FlexCAN is enabled or disabled.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return State of FlexCAN enable(0)/disable(1)
+ */
+static inline bool FLEXCAN_HAL_IsEnabled(uint32_t canBaseAddr)
+{
+ return BR_CAN_MCR_MDIS(canBaseAddr);
+}
+
+/*!
+ * @brief Selects the clock source for FlexCAN.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param clk The FlexCAN clock source
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SelectClock(uint32_t canBaseAddr, flexcan_clk_source_t clk);
+
+/*!
+ * @brief Initializes the FlexCAN controller.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data.
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Init(uint32_t canBaseAddr, const flexcan_user_config_t *data);
+
+/*!
+ * @brief Sets the FlexCAN time segments for setting up bit rate.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param time_seg FlexCAN time segments, which need to be set for the bit rate.
+ * @return 0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_SetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg);
+
+/*!
+ * @brief Gets the FlexCAN time segments to calculate the bit rate.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param time_seg FlexCAN time segments read for bit rate
+ * @return 0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_GetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg);
+
+/*!
+ * @brief Un freezes the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return 0 if successful; non-zero failed.
+ */
+void FLEXCAN_HAL_ExitFreezeMode(uint32_t canBaseAddr);
+
+/*!
+ * @brief Freezes the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnterFreezeMode(uint32_t canBaseAddr);
+
+/*!
+ * @brief Enables operation mode.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param mode An operation mode to be enabled
+ * @return 0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_EnableOperationMode(
+ uint32_t canBaseAddr,
+ flexcan_operation_modes_t mode);
+
+/*!
+ * @brief Disables operation mode.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param mode An operation mode to be disabled
+ * @return 0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_DisableOperationMode(
+ uint32_t canBaseAddr,
+ flexcan_operation_modes_t mode);
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Sets the FlexCAN message buffer fields for transmitting.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @param cs CODE/status values (TX)
+ * @param msg_id ID of the message to transmit
+ * @param mb_data Bytes of the FlexCAN message
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetMbTx(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_code_status_t *cs,
+ uint32_t msg_id,
+ uint8_t *mb_data);
+
+/*!
+ * @brief Sets the FlexCAN message buffer fields for receiving.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @param cs CODE/status values (RX)
+ * @param msg_id ID of the message to receive
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetMbRx(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_code_status_t *cs,
+ uint32_t msg_id);
+
+/*!
+ * @brief Gets the FlexCAN message buffer fields.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @param mb The fields of the message buffer
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_GetMb(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx,
+ flexcan_mb_t *mb);
+
+/*!
+ * @brief Locks the FlexCAN Rx message buffer.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_LockRxMb(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx);
+
+/*!
+ * @brief Unlocks the FlexCAN Rx message buffer.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return 0 if successful; non-zero failed
+ */
+static inline void FLEXCAN_HAL_UnlockRxMb(uint32_t canBaseAddr)
+{
+ /* Unlock the mailbox */
+ HW_CAN_TIMER_RD(canBaseAddr);
+}
+
+/*!
+ * @brief Enables the Rx FIFO.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableRxFifo(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables the Rx FIFO.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableRxFifo(uint32_t canBaseAddr);
+
+/*!
+ * @brief Sets the number of the Rx FIFO filters.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param number The number of Rx FIFO filters
+ */
+void FLEXCAN_HAL_SetRxFifoFiltersNumber(uint32_t canBaseAddr, uint32_t number);
+
+/*!
+ * @brief Sets the maximum number of Message Buffers.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ */
+void FLEXCAN_HAL_SetMaxMbNumber(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data);
+
+/*!
+ * @brief Sets the Rx FIFO ID filter table elements.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param id_format The format of the Rx FIFO ID Filter Table Elements
+ * @param id_filter_table The ID filter table elements which contain if RTR bit,
+ * IDE bit and RX message ID need to be set.
+ * @return 0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_SetIdFilterTableElements(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ flexcan_rx_fifo_id_element_format_t id_format,
+ flexcan_id_table_t *id_filter_table);
+
+/*!
+ * @brief Sets the FlexCAN Rx FIFO fields.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param id_format The format of the Rx FIFO ID Filter Table Elements
+ * @param id_filter_table The ID filter table elements which contain RTR bit, IDE bit,
+ * and RX message ID.
+ * @return 0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_SetRxFifo(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ flexcan_rx_fifo_id_element_format_t id_format,
+ flexcan_id_table_t *id_filter_table);
+
+/*!
+ * @brief Gets the FlexCAN Rx FIFO data.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param rx_fifo The FlexCAN receive FIFO data
+ * @return 0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_ReadFifo(
+ uint32_t canBaseAddr,
+ flexcan_mb_t *rx_fifo);
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexCAN Message Buffer interrupt.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_EnableMbInt(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx);
+
+/*!
+ * @brief Disables the FlexCAN Message Buffer interrupt.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @return 0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_DisableMbInt(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx);
+
+/*!
+ * @brief Enables error interrupt of the FlexCAN module.
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableErrInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables error interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableErrInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Enables Bus off interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableBusOffInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables Bus off interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableBusOffInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Enables Wakeup interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableWakeupInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables Wakeup interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableWakeupInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Enables TX warning interrupt of the FlexCAN module
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableTxWarningInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables TX warning interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableTxWarningInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Enables RX warning interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnableRxWarningInt(uint32_t canBaseAddr);
+
+/*!
+ * @brief Disables RX warning interrupt of the FlexCAN module.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableRxWarningInt(uint32_t canBaseAddr);
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the value of FlexCAN freeze ACK.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return freeze ACK state (1-freeze mode, 0-not in freeze mode).
+ */
+static inline uint32_t FLEXCAN_HAL_GetFreezeAck(uint32_t canBaseAddr)
+{
+ return HW_CAN_MCR(canBaseAddr).B.FRZACK;
+}
+
+/*!
+ * @brief Gets the individual FlexCAN MB interrupt flag.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @return the individual MB interrupt flag (0 and 1 are the flag value)
+ */
+uint8_t FLEXCAN_HAL_GetMbIntFlag(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t *data,
+ uint32_t mb_idx);
+
+/*!
+ * @brief Gets all FlexCAN MB interrupt flags.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return all MB interrupt flags
+ */
+static inline uint32_t FLEXCAN_HAL_GetAllMbIntFlags(uint32_t canBaseAddr)
+{
+ return HW_CAN_IFLAG1_RD(canBaseAddr);
+}
+
+/*!
+ * @brief Clears the interrupt flag of the message buffers.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param reg_val The value to be written to the interrupt flag1 register.
+ */
+/* See fsl_flexcan_hal.h for documentation of this function.*/
+static inline void FLEXCAN_HAL_ClearMbIntFlag(
+ uint32_t canBaseAddr,
+ uint32_t reg_val)
+{
+ /* Clear the corresponding message buffer interrupt flag*/
+ HW_CAN_IFLAG1_SET(canBaseAddr, reg_val);
+}
+
+/*!
+ * @brief Gets the transmit error counter and receives the error counter.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param err_cnt Transmit error counter and receive error counter
+ */
+void FLEXCAN_HAL_GetErrCounter(
+ uint32_t canBaseAddr,
+ flexcan_berr_counter_t *err_cnt);
+
+/*!
+ * @brief Gets error and status.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return The current error and status
+ */
+static inline uint32_t FLEXCAN_HAL_GetErrStatus(uint32_t canBaseAddr)
+{
+ return HW_CAN_ESR1_RD(canBaseAddr);
+}
+
+/*!
+ * @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
+ *
+ * @param canBaseAddr The FlexCAN base address
+ */
+void FLEXCAN_HAL_ClearErrIntStatus(uint32_t canBaseAddr);
+
+/*@}*/
+
+/*!
+ * @name Mask
+ * @{
+ */
+
+/*!
+ * @brief Sets the Rx masking type.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param type The FlexCAN Rx mask type
+ */
+void FLEXCAN_HAL_SetMaskType(uint32_t canBaseAddr, flexcan_rx_mask_type_t type);
+
+/*!
+ * @brief Sets the FlexCAN RX FIFO global standard mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param std_mask Standard mask
+ */
+void FLEXCAN_HAL_SetRxFifoGlobalStdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask);
+
+/*!
+ * @brief Sets the FlexCAN Rx FIFO global extended mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param ext_mask Extended mask
+ */
+void FLEXCAN_HAL_SetRxFifoGlobalExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask);
+
+/*!
+ * @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @param std_mask Individual standard mask
+ * @return 0 if successful; non-zero failed
+*/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t * data,
+ uint32_t mb_idx,
+ uint32_t std_mask);
+
+/*!
+ * @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx MBs and the Rx FIFO.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param data The FlexCAN platform data
+ * @param mb_idx Index of the message buffer
+ * @param ext_mask Individual extended mask
+ * @return 0 if successful; non-zero failed
+*/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask(
+ uint32_t canBaseAddr,
+ const flexcan_user_config_t * data,
+ uint32_t mb_idx,
+ uint32_t ext_mask);
+
+/*!
+ * @brief Sets the FlexCAN Rx MB global standard mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param std_mask Standard mask
+ */
+void FLEXCAN_HAL_SetRxMbGlobalStdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB BUF14 standard mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param std_mask Standard mask
+ */
+void FLEXCAN_HAL_SetRxMbBuf14StdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask);
+
+/*!
+ * @brief Sets the FlexCAN Rx MB BUF15 standard mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param std_mask Standard mask
+ * @return 0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_SetRxMbBuf15StdMask(
+ uint32_t canBaseAddr,
+ uint32_t std_mask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB global extended mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param ext_mask Extended mask
+ */
+void FLEXCAN_HAL_SetRxMbGlobalExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB BUF14 extended mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param ext_mask Extended mask
+ */
+void FLEXCAN_HAL_SetRxMbBuf14ExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB BUF15 extended mask.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @param ext_mask Extended mask
+ */
+void FLEXCAN_HAL_SetRxMbBuf15ExtMask(
+ uint32_t canBaseAddr,
+ uint32_t ext_mask);
+
+/*!
+ * @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO.
+ *
+ * @param canBaseAddr The FlexCAN base address
+ * @return RX FIFO information
+ */
+static inline uint32_t FLEXCAN_HAL_GetIdAcceptanceFilterRxFifo(uint32_t canBaseAddr)
+{
+ return BR_CAN_RXFIR_IDHIT(canBaseAddr);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* MBED_NO_FLEXCAN */
+
+#endif /* __FSL_FLEXCAN_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,100 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_DAC_FEATURES_H__) +#define __FSL_DAC_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || \ + defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || \ + defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || \ + defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || \ + defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ + defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV44F128VLH15) || \ + defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ + defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Define the size of hardware buffer */ + #define FSL_FEATURE_DAC_BUFFER_SIZE (16) + /* @brief Define has watermark event detection or not. */ + #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Define the size of hardware buffer */ + #define FSL_FEATURE_DAC_BUFFER_SIZE (2) + /* @brief Define has watermark event detection or not. */ + #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DAC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dac_hal.h"
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_Init
+ * Description : Reset all the configurable registers to be reset state for DAC.
+ * It should be called before configuring the DAC module.
+ *
+ *END*************************************************************************/
+void DAC_HAL_Init(uint32_t baseAddr)
+{
+ /* DACx_DATL and DACx_DATH */
+ HW_DAC_DATnL_WR(baseAddr, 0U, 0U); HW_DAC_DATnH_WR(baseAddr, 0U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 1U, 0U); HW_DAC_DATnH_WR(baseAddr, 1U, 0U);
+#if (HW_DAC_DATnL_COUNT > 2U)
+ HW_DAC_DATnL_WR(baseAddr, 2U, 0U); HW_DAC_DATnH_WR(baseAddr, 2U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 3U, 0U); HW_DAC_DATnH_WR(baseAddr, 3U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 4U, 0U); HW_DAC_DATnH_WR(baseAddr, 4U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 5U, 0U); HW_DAC_DATnH_WR(baseAddr, 5U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 6U, 0U); HW_DAC_DATnH_WR(baseAddr, 6U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 7U, 0U); HW_DAC_DATnH_WR(baseAddr, 7U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 8U, 0U); HW_DAC_DATnH_WR(baseAddr, 8U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 9U, 0U); HW_DAC_DATnH_WR(baseAddr, 9U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 10U, 0U); HW_DAC_DATnH_WR(baseAddr, 10U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 11U, 0U); HW_DAC_DATnH_WR(baseAddr, 11U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 12U, 0U); HW_DAC_DATnH_WR(baseAddr, 12U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 13U, 0U); HW_DAC_DATnH_WR(baseAddr, 13U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 14U, 0U); HW_DAC_DATnH_WR(baseAddr, 14U, 0U);
+ HW_DAC_DATnL_WR(baseAddr, 15U, 0U); HW_DAC_DATnH_WR(baseAddr, 15U, 0U);
+#endif /* HW_DAC_DATnL_COUNT */
+ /* DACx_SR. */
+ HW_DAC_SR_WR(baseAddr, 0U); /* Clear all flags. */
+ /* DACx_C0. */
+ HW_DAC_C0_WR(baseAddr, 0U);
+ /* DACx_C1. */
+ HW_DAC_C1_WR(baseAddr, 0U);
+ /* DACx_C2. */
+ HW_DAC_C2_WR(baseAddr, 15U);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_SetBuffValue
+ * Description : Set the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in buffer.
+ *
+ *END*************************************************************************/
+void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value)
+{
+ assert(index < HW_DAC_DATnL_COUNT);
+ BW_DAC_DATnL_DATA0(baseAddr, index, (uint8_t)(0xFFU & value) );
+ BW_DAC_DATnH_DATA1(baseAddr, index, (uint8_t)((0xF00U & value)>>8U) );
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_GetBuffValue
+ * Description : Get the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in buffer.
+ *
+ *END*************************************************************************/
+uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index)
+{
+ assert(index < HW_DAC_DATnL_COUNT);
+ uint16_t ret16;
+ ret16 = BR_DAC_DATnH_DATA1(baseAddr, index);
+ ret16 <<= 8U;
+ ret16 |= BR_DAC_DATnL_DATA0(baseAddr, index);
+ return ret16;
+}
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,488 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_DAC_HAL_H__
+#define __FSL_DAC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_dac_features.h"
+
+/*!
+ * @addtogroup dac_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*!
+ * @brief DAC status return codes.
+ */
+typedef enum _dac_status
+{
+ kStatus_DAC_Success = 0U, /*!< Success. */
+ kStatus_DAC_InvalidArgument = 1U, /*!< Invalid argument existed. */
+ kStatus_DAC_Failed = 2U /*!< Execution failed. */
+} dac_status_t;
+
+/*!
+ * @brief Defines the type of selection for DAC module's reference voltage source.
+ *
+ * See the appropriate SoC Reference Manual for actual connections.
+ */
+typedef enum _dac_ref_volt_src_mode
+{
+ kDacRefVoltSrcOfVref1 = 0U, /*!< Select DACREF_1 as the reference voltage. */
+ kDacRefVoltSrcOfVref2 = 1U, /*!< Select DACREF_2 as the reference voltage. */
+} dac_ref_volt_src_mode_t;
+
+/*!
+ * @brief Defines the type of selection for DAC module trigger mode.
+ */
+typedef enum _dac_trigger_mode
+{
+ kDacTriggerByHardware = 0U, /*!< Select hardware trigger. */
+ kDacTriggerBySoftware = 1U /*!< Select software trigger. */
+} dac_trigger_mode_t;
+
+/*!
+ * @brief Defines the type of selection for buffer watermark mode.
+ *
+ * If the buffer feature for DAC module is enabled, a watermark event will
+ * occur when the buffer index hits the watermark.
+ */
+typedef enum _dac_buff_watermark_mode
+{
+ kDacBuffWatermarkFromUpperAs1Word = 0U, /*!< Select 1 word away from the upper of buffer. */
+ kDacBuffWatermarkFromUpperAs2Word = 1U, /*!< Select 2 word away from the upper of buffer. */
+ kDacBuffWatermarkFromUpperAs3Word = 2U, /*!< Select 3 word away from the upper of buffer. */
+ kDacBuffWatermarkFromUpperAs4Word = 3U, /*!< Select 4 word away from the upper of buffer. */
+} dac_buff_watermark_mode_t;
+
+/*!
+ * @brief Defines the type of selection for buffer work mode.
+ *
+ * There are three kinds of work modes when the DAC buffer is enabled.
+ * Normal mode - When the buffer index hits the upper level, it
+ * starts (0) on the next trigger.
+ * Swing mode - When the buffer index hits the upper level, it goes backward to
+ * the start and is reduced one-by-one on the next trigger. When the buffer index
+ * hits the start, it goes backward to the upper level and increases one-by-one
+ * on the next trigger.
+ * One-Time-Scan mode - The buffer index can only be increased on the next trigger.
+ * When the buffer index hits the upper level, it is not updated by the trigger.
+ * FIFO mode
+ */
+typedef enum _dac_buff_work_mode
+{
+ kDacBuffWorkAsNormalMode = 0U, /*!< Buffer works as Normal. */
+ kDacBuffWorkAsSwingMode = 1U, /*!< Buffer works as swing. */
+ kDacBuffWorkAsOneTimeScanMode = 2U, /*!< Buffer works as one time scan.*/
+ kDacBuffWorkAsFIFOMode = 3U /*!< Buffer works as FIFO.*/
+} dac_buff_work_mode_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Resets all configurable registers to be in the reset state for DAC.
+ *
+ * This function resets all configurable registers to be in the reset state for DAC.
+ * It should be called before configuring the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+void DAC_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Sets the 12-bit value for the DAC items in the buffer.
+ *
+ * This function sets the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in the buffer.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param index Buffer index.
+ * @param value Setting value.
+ */
+void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value);
+
+/*!
+ * @brief Gets the 12-bit value from the DAC item in the buffer.
+ *
+ * This function gets the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in the buffer.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param index Buffer index.
+ * @return Current setting value.
+ */
+uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index);
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * bottom position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+static inline void DAC_HAL_ClearBuffIndexUpperFlag(uint32_t baseAddr)
+{
+ BW_DAC_SR_DACBFRPBF(baseAddr, 0U);
+}
+
+/*!
+ * @brief Gets the flag of DAC buffer read pointer when it hits the bottom position.
+ *
+ * This function gets the flag of DAC buffer read pointer when it hits the
+ * bottom position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIndexUpperFlag(uint32_t baseAddr)
+{
+ return ( 1U == BR_DAC_SR_DACBFRPBF(baseAddr) );
+}
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer when it hits the top position.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * top position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+static inline void DAC_HAL_ClearBuffIndexStartFlag(uint32_t baseAddr)
+{
+ BW_DAC_SR_DACBFRPTF(baseAddr, 0U);
+}
+
+/*!
+ * @brief Gets the flag of the DAC buffer read pointer when it hits the top position.
+ *
+ * This function gets the flag of the DAC buffer read pointer when it hits the
+ * top position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIndexStartFlag(uint32_t baseAddr)
+{
+ return ( 1U == BR_DAC_SR_DACBFRPTF(baseAddr) );
+}
+
+#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+
+/*!
+ * @brief Gets the flag of the DAC buffer read pointer when it hits the watermark position.
+ *
+ * This function gets the flag of the DAC buffer read pointer when it hits the
+ * watermark position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIndexWatermarkFlag(uint32_t baseAddr)
+{
+ return ( 1U == BR_DAC_SR_DACBFWMF(baseAddr) );
+}
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer when it hits the watermark position.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * watermark position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline void DAC_HAL_ClearBuffIndexWatermarkFlag(uint32_t baseAddr)
+{
+ BW_DAC_SR_DACBFWMF(baseAddr, 0U);
+}
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+
+/*!
+ * @brief Enables the Programmable Reference Generator.
+ *
+ * This function enables the Programmable Reference Generator. Then the
+ * DAC system is enabled.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+static inline void DAC_HAL_Enable(uint32_t baseAddr)
+{
+ BW_DAC_C0_DACEN(baseAddr, 1U);
+}
+
+/*!
+ * @brief Disables the Programmable Reference Generator.
+ *
+ * This function disables the Programmable Reference Generator. Then the
+ * DAC system is disabled.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+static inline void DAC_HAL_Disable(uint32_t baseAddr)
+{
+ BW_DAC_C0_DACEN(baseAddr, 0U);
+}
+
+/*!
+ * @brief Sets the reference voltage source mode for the DAC module.
+ *
+ * This function sets the reference voltage source mode for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param mode Selection of enumeration mode. See to "dac_ref_volt_src_mode_t".
+ */
+static inline void DAC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, dac_ref_volt_src_mode_t mode)
+{
+ BW_DAC_C0_DACRFS(baseAddr, ((kDacRefVoltSrcOfVref1==mode)?0U:1U) );
+}
+
+/*!
+ * @brief Sets the trigger mode for the DAC module.
+ *
+ * This function sets the trigger mode for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param mode Selection of enumeration mode. See to "dac_trigger_mode_t".
+ */
+static inline void DAC_HAL_SetTriggerMode(uint32_t baseAddr, dac_trigger_mode_t mode)
+{
+ BW_DAC_C0_DACTRGSEL(baseAddr, ((kDacTriggerByHardware==mode)?0U:1U) );
+}
+
+/*!
+ * @brief Triggers the converter with software.
+ *
+ * This function triggers the converter with software. If the DAC software
+ * trigger is selected and buffer enabled, calling this API advances the
+ * buffer read pointer once.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ */
+static inline void DAC_HAL_SetSoftTriggerCmd(uint32_t baseAddr)
+{
+ BW_DAC_C0_DACSWTRG(baseAddr, 1U);
+}
+
+/*!
+ * @brief Switches to enable working in low power mode for the DAC module.
+ *
+ * This function switches to enable working in low power mode for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C0_LPEN(baseAddr, (enable?1U:0U) );
+}
+
+#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+/*!
+ * @brief Switches to enable the interrupt when buffer read pointer hits the watermark position.
+ *
+ * This function switches to enable the interrupt when the buffer read pointer hits
+ * the watermark position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetBuffIndexWatermarkIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C0_DACBWIEN(baseAddr, (enable?1U:0U) );
+}
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+
+/*!
+ * @brief Switches to enable the interrupt when the buffer read pointer hits the top position.
+ *
+ * This function switches to enable the interrupt when the buffer read pointer hits
+ * the top position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetBuffIndexStartIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C0_DACBTIEN(baseAddr, (enable?1U:0U) );
+}
+
+/*!
+ * @brief Switches to enable the interrupt when the buffer read pointer hits the bottom position.
+ *
+ * This function switches to enable the interrupt when the buffer read pointer hits
+ * the bottom position.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetBuffIndexUpperIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C0_DACBBIEN(baseAddr, (enable?1U:0U) );
+}
+
+/*!
+ * @brief Switches to enable the DMA for DAC.
+ *
+ * This function switches to enable the DMA for the DAC module. When the DMA is enabled,
+ * DMA request is generated by the original interrupts, which are
+ * not presented on this module at the same time.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C1_DMAEN(baseAddr, (enable?1U:0U) );
+}
+
+#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+/*!
+ * @brief Sets the watermark mode of the buffer for the DAC module.
+ *
+ * This function sets the watermark mode of the buffer for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param mode Selection of enumeration mode. See to "dac_buff_watermark_mode_t".
+ */
+static inline void DAC_HAL_SetBuffWatermarkMode(uint32_t baseAddr, dac_buff_watermark_mode_t mode)
+{
+ BW_DAC_C1_DACBFWM(baseAddr, (uint8_t)mode);
+}
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+
+/*!
+ * @brief Sets the work mode of the buffer for the DAC module.
+ *
+ * This function sets the work mode of the buffer for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param mode Selection of enumeration mode. See to "dac_buff_work_mode_t".
+ */
+static inline void DAC_HAL_SetBuffWorkMode(uint32_t baseAddr, dac_buff_work_mode_t mode)
+{
+ BW_DAC_C1_DACBFMD(baseAddr, (uint8_t)mode );
+}
+
+/*!
+ * @brief Switches to enable the buffer for the DAC module.
+ *
+ * This function switches to enable the buffer for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void DAC_HAL_SetBuffCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DAC_C1_DACBFEN(baseAddr, (enable?1U:0U) );
+}
+
+/*!
+ * @brief Gets the buffer index upper limitation for the DAC module.
+ *
+ * This function gets the upper buffer index upper limitation for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Value of buffer index upper limitation.
+ */
+static inline uint8_t DAC_HAL_GetBuffUpperIndex(uint32_t baseAddr)
+{
+ return BR_DAC_C2_DACBFUP(baseAddr);
+}
+
+/*!
+ * @brief Sets the buffer index upper limitation for the DAC module.
+ *
+ * This function sets the upper buffer index upper limitation for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @param index Setting value of upper limitation for buffer index.
+ */
+static inline void DAC_HAL_SetBuffUpperIndex(uint32_t baseAddr, uint8_t index)
+{
+ assert(index < HW_DAC_DATnL_COUNT);
+ BW_DAC_C2_DACBFUP(baseAddr , index);
+}
+
+/*!
+ * @brief Gets the current buffer index upper limitation for the DAC module.
+ *
+ * This function gets the current buffer index for the DAC module.
+ *
+ * @param baseAddr The DAC peripheral base address.
+ * @return Value of current buffer index.
+ */
+static inline uint8_t DAC_HAL_GetBuffCurrentIndex(uint32_t baseAddr)
+{
+ return BR_DAC_C2_DACBFRP(baseAddr);
+}
+
+/*!
+ * @brief Sets the buffer index for the DAC module.
+ *
+ * This function sets the upper buffer index for the DAC module.
+ *
+ * @param baseAddr the DAC peripheral base address.
+ * @param index Setting value for buffer index.
+ */
+static inline void DAC_HAL_SetBuffCurrentIndex(uint32_t baseAddr, uint8_t index)
+{
+ assert(index < HW_DAC_DATnL_COUNT);
+ BW_DAC_C2_DACBFRP(baseAddr, index);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_DAC_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,114 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_DMAMUX_FEATURES_H__) +#define __FSL_DMAMUX_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \ + defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ + defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) + /* @brief Number of DMA channels (related to number of register CHCFGn). */ + #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 4) +#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ + defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ + defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ + defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ + defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Number of DMA channels (related to number of register CHCFGn). */ + #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 16) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Number of DMA channels (related to number of register CHCFGn). */ + #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 32) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DMAMUX_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,56 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include "fsl_dmamux_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : dmamux_hal_init
+ * Description : Initialize the dmamux module to the reset state.
+ *
+ *END**************************************************************************/
+void DMAMUX_HAL_Init(uint32_t baseAddr)
+{
+ int i;
+
+ for (i = 0; i < FSL_FEATURE_DMAMUX_MODULE_CHANNEL; i++)
+ {
+ BW_DMAMUX_CHCFGn_ENBL(baseAddr, i, 0U);
+ BW_DMAMUX_CHCFGn_SOURCE(baseAddr, i, 0U);
+ }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DMAMUX_HAL_H__
+#define __FSL_DMAMUX_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_dmamux_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup dmamux_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief A constant for the length of the DMA hardware source. This structure is used inside
+ * the DMA driver.
+ */
+typedef enum _dmamux_source {
+ kDmamuxDmaRequestSource = 64U /*!< Maximum number of the DMA requests allowed for the DMA mux. */
+} dmamux_dma_request_source;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMAMUX HAL function
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMAMUX module to the reset state.
+ *
+ * Initializes the DMAMUX module to the reset state.
+ *
+ * @param baseAddr Register base address for DMAMUX module.
+ */
+void DMAMUX_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Enables/Disables the DMAMUX channel.
+ *
+ * Enables the hardware request. If enabled, the hardware request is sent to
+ * the corresponding DMA channel.
+ *
+ * @param baseAddr Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param enable Enables (true) or Disables (false) DMAMUX channel.
+ */
+static inline void DMAMUX_HAL_SetChannelCmd(uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+ BW_DMAMUX_CHCFGn_ENBL(baseAddr, channel, enable);
+}
+
+
+/*!
+ * @brief Enables/Disables the period trigger.
+ *
+ * @param baseAddr Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param enable Enables (true) or Disables (false) period trigger.
+ */
+static inline void DMAMUX_HAL_SetPeriodTriggerCmd(uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+ BW_DMAMUX_CHCFGn_TRIG(baseAddr, channel, enable);
+}
+
+
+/*!
+ * @brief Configures the DMA request for the DMAMUX channel.
+ *
+ * Sets the trigger source for the DMA channel. The trigger source is in the file
+ * fsl_dma_request.h.
+ *
+ * @param baseAddr Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param source DMA request source.
+ */
+static inline void DMAMUX_HAL_SetTriggerSource(uint32_t baseAddr, uint32_t channel, uint8_t source)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+ BW_DMAMUX_CHCFGn_SOURCE(baseAddr, channel, source);
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_DMAMUX_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,247 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_DSPI_FEATURES_H__) +#define __FSL_DSPI_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : (-1)) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (4) : (-1)) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || \ + defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : (-1)) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (5) : (-1)) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLL12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLL12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (6) : \ + ((x) == 1 ? (4) : (-1))) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VLH12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F512VLH12) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (5) : \ + ((x) == 1 ? (2) : (-1))) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (6) : \ + ((x) == 1 ? (4) : \ + ((x) == 2 ? (2) : (-1)))) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (6) : \ + ((x) == 1 ? (4) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : \ + ((x) == 1 ? (4) : \ + ((x) == 2 ? (4) : (-1)))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (6) : \ + ((x) == 1 ? (4) : \ + ((x) == 2 ? (2) : (-1)))) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : (-1)) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (5) : (-1)) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV44F128VLL15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZE (4) + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == 0 ? (4) : (-1)) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ + ((x) == 0 ? (6) : (-1)) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DSPI_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,604 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dspi_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_Init
+ * Description : Restore DSPI to reset configuration.
+ * This function basically resets all of the DSPI registers to their default setting including
+ * disabling the module.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_Init(uint32_t baseAddr)
+{
+ /* first, make sure the module is enabled to allow writes to certain registers*/
+ DSPI_HAL_Enable(baseAddr);
+
+ /* Halt all transfers*/
+ DSPI_HAL_StopTransfer(baseAddr);
+
+ /* set the registers to their default states*/
+ /* clear the status bits (write-1-to-clear)*/
+ HW_SPI_SR_WR(baseAddr, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF |
+ BM_SPI_SR_TFFF | BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
+ HW_SPI_TCR_WR(baseAddr, 0);
+ HW_SPI_CTARn_WR(baseAddr, 0, 0x78000000); /* CTAR0*/
+ HW_SPI_CTARn_WR(baseAddr, 1, 0x78000000); /* CTAR1*/
+ HW_SPI_RSER_WR(baseAddr, 0);
+
+ /* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be
+ * sure the flush the FIFOs afterwards
+ */
+ HW_SPI_PUSHR_WR(baseAddr, 0);
+
+ /* flush the fifos*/
+ DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true);
+
+ /* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */
+ HW_SPI_MCR_WR(baseAddr, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetBaudRate
+ * Description : Set the DSPI baud rate in bits per second.
+ * This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
+ * possible baud rate without exceeding the desired baud rate, and will return the calculated
+ * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hz).
+ *
+ *END**************************************************************************/
+uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+ uint32_t bitsPerSec, uint32_t sourceClockInHz)
+{
+ /* for master mode configuration, if slave mode detected, return 0*/
+ if (!DSPI_HAL_IsMaster(baseAddr))
+ {
+ return 0;
+ }
+
+ uint32_t prescaler, bestPrescaler;
+ uint32_t scaler, bestScaler;
+ uint32_t dbr, bestDbr;
+ uint32_t realBaudrate, bestBaudrate;
+ uint32_t diff, min_diff;
+ uint32_t baudrate = bitsPerSec;
+
+ /* find combination of prescaler and scaler resulting in baudrate closest to the */
+ /* requested value */
+ min_diff = 0xFFFFFFFFU;
+ bestPrescaler = 0;
+ bestScaler = 0;
+ bestDbr = 1;
+ bestBaudrate = 0; /* required to avoid compilation warning */
+
+ /* In all for loops, if min_diff = 0, the exit for loop*/
+ for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+ {
+ for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+ {
+ for (dbr = 1; (dbr < 3) && min_diff; dbr++)
+ {
+ realBaudrate = ((sourceClockInHz * dbr) /
+ (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
+
+ /* calculate the baud rate difference based on the conditional statement*/
+ /* that states that the calculated baud rate must not exceed the desired baud rate*/
+ if (baudrate >= realBaudrate)
+ {
+ diff = baudrate-realBaudrate;
+ if (min_diff > diff)
+ {
+ /* a better match found */
+ min_diff = diff;
+ bestPrescaler = prescaler;
+ bestScaler = scaler;
+ bestBaudrate = realBaudrate;
+ bestDbr = dbr;
+ }
+ }
+ }
+ }
+ }
+
+ /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
+ BW_SPI_CTARn_DBR(baseAddr, whichCtar, (bestDbr - 1));
+ BW_SPI_CTARn_PBR(baseAddr, whichCtar, bestPrescaler);
+ BW_SPI_CTARn_BR(baseAddr, whichCtar, bestScaler);
+
+ /* return the actual calculated baud rate*/
+ return bestBaudrate;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetBaudDivisors
+ * Description : Configure the baud rate divisors manually.
+ * This function allows the caller to manually set the baud rate divisors in the event that
+ * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
+ dspi_ctar_selection_t whichCtar,
+ const dspi_baud_rate_divisors_t * divisors)
+{
+ /* these settings are only relevant in master mode*/
+ if (DSPI_HAL_IsMaster(baseAddr))
+ {
+ BW_SPI_CTARn_DBR(baseAddr, whichCtar, divisors->doubleBaudRate);
+ BW_SPI_CTARn_PBR(baseAddr, whichCtar, divisors->prescaleDivisor);
+ BW_SPI_CTARn_BR(baseAddr, whichCtar, divisors->baudRateDivisor);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetPcsPolarityMode
+ * Description : Configure DSPI peripheral chip select polarity.
+ * This function will take in the desired peripheral chip select (PCS) and it's
+ * corresponding desired polarity and will configure the PCS signal to operate with the
+ * desired characteristic.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
+ dspi_pcs_polarity_config_t activeLowOrHigh)
+{
+ uint32_t temp;
+
+ temp = BR_SPI_MCR_PCSIS(baseAddr);
+
+ if (activeLowOrHigh == kDspiPcs_ActiveLow)
+ {
+ temp |= pcs;
+ }
+ else /* kDspiPcsPolarity_ActiveHigh*/
+ {
+ temp &= ~(unsigned)pcs;
+ }
+
+ BW_SPI_MCR_PCSIS(baseAddr, temp);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetFifoCmd
+ * Description : Enables (or disables) the DSPI FIFOs.
+ * This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
+ * configuration. To enable, the caller must pass in a logic 1 (true).
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo)
+{
+ /* first see if MDIS is set or cleared */
+ uint32_t isMdisSet = BR_SPI_MCR_MDIS(baseAddr);
+
+ if (isMdisSet)
+ {
+ /* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */
+ DSPI_HAL_Enable(baseAddr);
+ }
+
+ /* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable
+ * the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the
+ * FIFO
+ */
+ BW_SPI_MCR_DIS_TXF(baseAddr, ~(enableTxFifo == true));
+ BW_SPI_MCR_DIS_RXF(baseAddr, ~(enableRxFifo == true));
+
+ /* set MDIS (disable DSPI) if it was set to begin with */
+ if (isMdisSet)
+ {
+ DSPI_HAL_Disable(baseAddr);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetFlushFifoCmd
+ * Description : Flush DSPI fifos.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo)
+{
+ BW_SPI_MCR_CLR_TXF(baseAddr, (enableFlushTxFifo == true));
+ BW_SPI_MCR_CLR_RXF(baseAddr, (enableFlushRxFifo == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetDataFormat
+ * Description : Configure the data format for a particular CTAR.
+ * This function configures the bits-per-frame, polarity, phase, and shift direction for a
+ * particular CTAR. An example use case is as follows:
+ * dspi_data_format_config_t dataFormat;
+ * dataFormat.bitsPerFrame = 16;
+ * dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
+ * dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
+ * dataFormat.direction = kDspiMsbFirst;
+ * DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &dataFormat);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
+ dspi_ctar_selection_t whichCtar,
+ const dspi_data_format_config_t * config)
+{
+ /* check bits-per-frame value to make sure it it within the proper range*/
+ /* in either master or slave mode*/
+ if ((config->bitsPerFrame < 4) ||
+ ((config->bitsPerFrame > 16) && (HW_SPI_MCR(baseAddr).B.MSTR == 1)) ||
+ ((config->bitsPerFrame > 32) && (HW_SPI_MCR(baseAddr).B.MSTR == 0)))
+ {
+ return kStatus_DSPI_InvalidBitCount;
+ }
+
+ /* for master mode configuration*/
+ if (DSPI_HAL_IsMaster(baseAddr))
+ {
+ BW_SPI_CTARn_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
+ BW_SPI_CTARn_CPOL(baseAddr, whichCtar, config->clkPolarity);
+ BW_SPI_CTARn_CPHA(baseAddr, whichCtar, config->clkPhase);
+ BW_SPI_CTARn_LSBFE(baseAddr, whichCtar, config->direction);
+ }
+ else /* for slave mode configuration*/
+ {
+ BW_SPI_CTARn_SLAVE_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
+ BW_SPI_CTARn_SLAVE_CPOL(baseAddr, whichCtar, config->clkPolarity);
+ BW_SPI_CTARn_SLAVE_CPHA(baseAddr, whichCtar, config->clkPhase);
+ }
+ return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetDelay
+ * Description : Manually configures the delay prescaler and scaler for a particular CTAR.
+ * This function configures the:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
+ * After SCK delay pre-scalar (PASC) and scalar (ASC),
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the prescaler and scaler value.
+ * This basically allows the user to directly set the prescaler/scaler values if they have
+ * pre-calculated them or if they simply wish to manually increment either value.
+ *END**************************************************************************/
+void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
+ uint32_t scaler, dspi_delay_type_t whichDelay)
+{
+ /* these settings are only relevant in master mode*/
+ if (DSPI_HAL_IsMaster(baseAddr))
+ {
+ if (whichDelay == kDspiPcsToSck)
+ {
+ BW_SPI_CTARn_PCSSCK(baseAddr, whichCtar, prescaler);
+ BW_SPI_CTARn_CSSCK(baseAddr, whichCtar, scaler);
+ }
+
+ if (whichDelay == kDspiLastSckToPcs)
+ {
+ BW_SPI_CTARn_PASC(baseAddr, whichCtar, prescaler);
+ BW_SPI_CTARn_ASC(baseAddr, whichCtar, scaler);
+ }
+
+ if (whichDelay == kDspiAfterTransfer)
+ {
+ BW_SPI_CTARn_PDT(baseAddr, whichCtar, prescaler);
+ BW_SPI_CTARn_DT(baseAddr, whichCtar, scaler);
+ }
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_CalculateDelay
+ * Description : Calculates the delay prescaler and scaler based on desired delay input in
+ * nano-seconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in
+ * nano-seconds. The function will calculate the values needed for the prescaler and scaler and
+ * will return the actual calculated delay as an exact delay match may not be acheivable. In this
+ * case, the closest match will be calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay will be returned. It will be up to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *END**************************************************************************/
+uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+ dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
+ uint32_t delayInNanoSec)
+{
+ /* for master mode configuration, if slave mode detected, return 0*/
+ if (!DSPI_HAL_IsMaster(baseAddr))
+ {
+ return 0;
+ }
+
+ uint32_t prescaler, bestPrescaler;
+ uint32_t scaler, bestScaler;
+ uint32_t realDelay, bestDelay;
+ uint32_t diff, min_diff;
+ uint32_t initialDelayNanoSec;
+
+ /* find combination of prescaler and scaler resulting in the delay closest to the
+ * requested value
+ */
+ min_diff = 0xFFFFFFFFU;
+ /* Initialize prescaler and scaler to their max values to generate the max delay */
+ bestPrescaler = 0x3;
+ bestScaler = 0xF;
+ bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] *
+ s_delayScaler[bestScaler];
+
+ /* First calculate the initial, default delay */
+ initialDelayNanoSec = 1000000000/sourceClockInHz * 2;
+
+ /* If the initial, default delay is already greater than the desired delay, then
+ * set the delays to their initial value (0) and return the delay. In other words,
+ * there is no way to decrease the delay value further.
+ */
+ if (initialDelayNanoSec >= delayInNanoSec)
+ {
+ DSPI_HAL_SetDelay(baseAddr, whichCtar, 0, 0, whichDelay);
+ return initialDelayNanoSec;
+ }
+
+
+ /* In all for loops, if min_diff = 0, the exit for loop*/
+ for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+ {
+ for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+ {
+ realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] *
+ s_delayScaler[scaler];
+
+ /* calculate the delay difference based on the conditional statement
+ * that states that the calculated delay must not be less then the desired delay
+ */
+ if (realDelay >= delayInNanoSec)
+ {
+ diff = realDelay-delayInNanoSec;
+ if (min_diff > diff)
+ {
+ /* a better match found */
+ min_diff = diff;
+ bestPrescaler = prescaler;
+ bestScaler = scaler;
+ bestDelay = realDelay;
+ }
+ }
+ }
+ }
+
+ /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
+ DSPI_HAL_SetDelay(baseAddr, whichCtar, bestPrescaler, bestScaler, whichDelay);
+
+ /* return the actual calculated baud rate*/
+ return bestDelay;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode
+ * Description : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests.
+ * This function configures the DSPI Tx FIFO Fill flag to generate either
+ * an interrupt or DMA request. The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ *
+ * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
+{
+ BW_SPI_RSER_TFFF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
+ BW_SPI_RSER_TFFF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode
+ * Description : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
+ * This function configures the DSPI Rx FIFO Drain flag to generate either
+ * an interrupt or DMA request. The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ *
+ * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
+{
+ BW_SPI_RSER_RFDF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
+ BW_SPI_RSER_RFDF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetIntMode
+ * Description : Configure DSPI interrupts.
+ * This function configures the various interrupt sources of the DSPI. The parameters are
+ * baseAddr, interrupt source, and enable/disable setting.
+ * The interrupt source is a typedef enum whose value is the bit position of the
+ * interrupt source setting within the RSER register. In the DSPI, all interrupt
+ * configuration settings are in one register. The typedef enum equates each
+ * interrupt source to the bit position defined in the device header file.
+ * The function uses these bit positions in its algorithm to enable/disable the
+ * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
+ * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
+ * these requests can generate either an interrupt or DMA request.
+ *
+ * DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetIntMode(uint32_t baseAddr,
+ dspi_status_and_interrupt_request_t interruptSrc,
+ bool enable)
+{
+ uint32_t temp;
+
+ temp = (HW_SPI_RSER_RD(baseAddr) & ~(0x1U << interruptSrc)) |
+ ((uint32_t)enable << interruptSrc);
+ HW_SPI_RSER_WR(baseAddr, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_GetFifoData
+ * Description : Read fifo registers for debug purposes.
+ *
+ *END**************************************************************************/
+uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
+{
+ if (whichFifo == kDspiTxFifo)
+ {
+ return HW_SPI_TXFRn_RD(baseAddr, whichFifoEntry);
+ }
+ else
+ {
+ return HW_SPI_RXFRn_RD(baseAddr, whichFifoEntry);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataMastermode
+ * Description : Write data into the data buffer, master mode.
+ * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
+ * provides characteristics of the data being sent such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). An example use case is as follows:
+ * dspi_command_config_t commandConfig;
+ * commandConfig.isChipSelectContinuous = true;
+ * commandConfig.whichCtar = kDspiCtar0;
+ * commandConfig.whichPcs = kDspiPcs1;
+ * commandConfig.clearTransferCount = false;
+ * commandConfig.isEndOfQueue = false;
+ * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
+ dspi_command_config_t * command,
+ uint16_t data)
+{
+ uint32_t temp;
+
+ /* First, build up the 32-bit word then write it to the PUSHR */
+ temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
+ BF_SPI_PUSHR_CTAS(command->whichCtar) |
+ BF_SPI_PUSHR_PCS(command->whichPcs) |
+ BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
+ BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
+ BF_SPI_PUSHR_TXDATA(data);
+
+ HW_SPI_PUSHR_WR(baseAddr, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataMastermode
+ * Description : Write data into the data buffer, master mode and waits till complete to return.
+ * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
+ * provides characteristics of the data being sent such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). An example use case is as follows:
+ * dspi_command_config_t commandConfig;
+ * commandConfig.isChipSelectContinuous = true;
+ * commandConfig.whichCtar = kDspiCtar0;
+ * commandConfig.whichPcs = kDspiPcs1;
+ * commandConfig.clearTransferCount = false;
+ * commandConfig.isEndOfQueue = false;
+ * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
+ *
+ * Note that this function will not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data will be available when transmit completes.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
+ dspi_command_config_t * command,
+ uint16_t data)
+{
+ uint32_t temp;
+
+ /* First, clear Transmit Complete Flag (TCF) */
+ BW_SPI_SR_TCF(baseAddr, 1);
+
+ /* First, build up the 32-bit word then write it to the PUSHR */
+ temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
+ BF_SPI_PUSHR_CTAS(command->whichCtar) |
+ BF_SPI_PUSHR_PCS(command->whichPcs) |
+ BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
+ BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
+ BF_SPI_PUSHR_TXDATA(data);
+
+ HW_SPI_PUSHR_WR(baseAddr, temp);
+
+ /* Wait till TCF sets */
+ while(BR_SPI_SR_TCF(baseAddr) == 0) { }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,900 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_HAL_H__)
+#define __FSL_DSPI_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_dspi_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup dspi_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
+static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
+static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
+ 4096, 8192, 16384, 32768 };
+
+static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 };
+static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
+ 4096, 8192, 16384, 32768, 65536 };
+
+
+/*! @brief Error codes for the DSPI driver.*/
+typedef enum _dspi_status
+{
+ kStatus_DSPI_Success = 0,
+ kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/
+ kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/
+ kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/
+ kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a
+ transfer.*/
+ kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer
+ was in progress*/
+ kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
+ kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
+ kStatus_DSPI_OutOfRange /*!< DSPI out-of-range error used in slave callback */
+} dspi_status_t;
+
+/*! @brief DSPI master or slave configuration*/
+typedef enum _dspi_master_slave_mode {
+ kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/
+ kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/
+} dspi_master_slave_mode_t;
+
+/*! @brief DSPI clock polarity configuration for a given CTAR*/
+typedef enum _dspi_clock_polarity {
+ kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/
+ kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/
+} dspi_clock_polarity_t;
+
+/*! @brief DSPI clock phase configuration for a given CTAR*/
+typedef enum _dspi_clock_phase {
+ kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and
+ changed on the following edge.*/
+ kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and
+ captured on the following edge.*/
+} dspi_clock_phase_t;
+
+/*! @brief DSPI data shifter direction options for a given CTAR*/
+typedef enum _dspi_shift_direction {
+ kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/
+ kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/
+} dspi_shift_direction_t;
+
+/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/
+typedef enum _dspi_ctar_selection {
+ kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode*/
+ kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only*/
+} dspi_ctar_selection_t;
+
+/*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/
+typedef enum _dspi_pcs_polarity_config {
+ kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low)*/
+ kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high)*/
+} dspi_pcs_polarity_config_t;
+
+/*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/
+typedef enum _dspi_which_pcs_config {
+ kDspiPcs0 = 1 << 0, /*!< PCS[0] */
+ kDspiPcs1 = 1 << 1, /*!< PCS[1] */
+ kDspiPcs2 = 1 << 2, /*!< PCS[2] */
+ kDspiPcs3 = 1 << 3, /*!< PCS[3] */
+ kDspiPcs4 = 1 << 4, /*!< PCS[4] */
+ kDspiPcs5 = 1 << 5 /*!< PCS[5] */
+} dspi_which_pcs_config_t;
+
+/*!
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer
+ * Format. This field is valid only when CPHA bit in CTAR register is 0.
+ */
+typedef enum _dspi_master_sample_point {
+ kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/
+ kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/
+ kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/
+} dspi_master_sample_point_t;
+
+/*! @brief DSPI FIFO selects*/
+typedef enum _dspi_fifo {
+ kDspiTxFifo = 0, /*!< DSPI Tx FIFO*/
+ kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/
+} dspi_fifo_t;
+
+/*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */
+typedef enum _dspi_dma_or_int_mode {
+ kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */
+ kDspiGenerateDmaReq = 1 /*!< Desired flag generates a DMA request */
+} dspi_dma_or_int_mode_t;
+
+/*! @brief DSPI status flags and interrupt request enable*/
+typedef enum _dspi_status_and_interrupt_request {
+ kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */
+ kDspiTxAndRxStatus = BP_SPI_SR_TXRXS, /*!< TXRXS status only, no interrupt*/
+ kDspiEndOfQueue = BP_SPI_RSER_EOQF_RE, /*!< EOQF status/interrupt enable*/
+ kDspiTxFifoUnderflow = BP_SPI_RSER_TFUF_RE, /*!< TFUF status/interrupt enable*/
+ kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/
+ kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/
+ kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/
+} dspi_status_and_interrupt_request_t;
+
+/*! @brief DSPI FIFO counter or pointer defines based on bit positions*/
+typedef enum _dspi_fifo_counter_pointer {
+ kDspiRxFifoPointer = BP_SPI_SR_POPNXTPTR, /*!< Rx FIFO pointer*/
+ kDspiRxFifoCounter = BP_SPI_SR_RXCTR, /*!< Rx FIFO counter*/
+ kDspiTxFifoPointer = BP_SPI_SR_TXNXTPTR, /*!< Tx FIFO pointer*/
+ kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/
+} dspi_fifo_counter_pointer_t;
+
+/*! @brief DSPI delay type selection*/
+typedef enum _dspi_delay_type {
+ kDspiPcsToSck = 1, /*!< PCS-to-SCK delay */
+ kDspiLastSckToPcs = 2, /*!< Last SCK edge to PCS delay */
+ kDspiAfterTransfer = 3, /*!< Delay between transfers */
+} dspi_delay_type_t;
+
+/*!
+ * @brief DSPI data format settings configuration structure
+ *
+ * This structure contains the data format settings. These settings apply to a specific
+ * CTARn register, which the user must provide in this structure.
+ */
+typedef struct DspiDataFormatConfig {
+ uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 (master), 32 (slave) */
+ dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/
+ dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/
+ dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction
+ This setting relevant only in master mode and
+ can be ignored in slave mode */
+} dspi_data_format_config_t;
+
+/*!
+ * @brief DSPI hardware configuration settings for slave mode.
+ *
+ * Use an instance of this structure with the DSPI_HAL_SlaveInit() to configure the
+ * most common settings of the DSPI peripheral in slave mode with a single function call.
+ */
+typedef struct DspiSlaveConfig {
+ bool isEnabled; /*!< Set to true to enable the DSPI peripheral. */
+ dspi_data_format_config_t dataConfig; /*!< Data format configuration structure */
+ bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
+ bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
+} dspi_slave_config_t;
+
+/*!
+ * @brief DSPI baud rate divisors settings configuration structure.
+ *
+ * Note: These settings are relevant only in master mode.
+ * This structure contains the baud rate divisor settings, which provides the user with the option
+ * to explicitly set these baud rate divisors. In addition, the user must also set the
+ * CTARn register with the divisor settings.
+ */
+typedef struct DspiBaudRateDivisors {
+ bool doubleBaudRate; /*!< Double Baud rate parameter setting */
+ uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/
+ uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */
+} dspi_baud_rate_divisors_t;
+
+/*!
+ * @brief DSPI command and data configuration structure
+ *
+ * Note: This structure is used with the PUSHR register, which
+ * provides the means to write to the Tx FIFO. Data written to this register is
+ * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all
+ * 32 register bits to the Tx FIFO. The register structure is different in master and slave
+ * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx
+ * FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
+ * frame operation.
+ */
+typedef struct DspiCommandDataConfig {
+ bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select
+ between transfers*/
+ dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
+ Register (CTAR) to use for CTAS*/
+ dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/
+ bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/
+ bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/
+} dspi_command_config_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+extern const uint32_t spi_base_addr[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Restores the DSPI to reset the configuration.
+ *
+ * This function basically resets all of the DSPI registers to their default setting including
+ * disabling the module.
+ *
+ * @param baseAddr Module base address
+ */
+void DSPI_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
+ *
+ * @param baseAddr Module base address
+ */
+static inline void DSPI_HAL_Enable(uint32_t baseAddr)
+{
+ BW_SPI_MCR_MDIS(baseAddr, 0);
+}
+
+/*!
+ * @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
+ *
+ * @param baseAddr Module base address
+ */
+static inline void DSPI_HAL_Disable(uint32_t baseAddr)
+{
+ BW_SPI_MCR_MDIS(baseAddr, 1);
+}
+
+/*!
+ * @brief Sets the DSPI baud rate in bits per second.
+ *
+ * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
+ * possible baud rate without exceeding the desired baud rate, and returns the calculated
+ * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hertz).
+ *
+ * @param baseAddr Module base address
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
+ * dspi_ctar_selection_t
+ * @param bitsPerSec The desired baud rate in bits per second
+ * @param sourceClockInHz Module source input clock in Hertz
+ * @return The actual calculated baud rate
+ */
+uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+ uint32_t bitsPerSec, uint32_t sourceClockInHz);
+
+/*!
+ * @brief Configures the baud rate divisors manually.
+ *
+ * This function allows the caller to manually set the baud rate divisors in the event that
+ * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
+ *
+ * @param baseAddr Module base address
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ * dspi_ctar_selection_t
+ * @param divisors Pointer to a structure containing the user defined baud rate divisor settings
+ */
+void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
+ dspi_ctar_selection_t whichCtar,
+ const dspi_baud_rate_divisors_t * divisors);
+
+/*!
+ * @brief Configures the DSPI for master or slave.
+ *
+ * @param baseAddr Module base address
+ * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
+ */
+static inline void DSPI_HAL_SetMasterSlaveMode(uint32_t baseAddr, dspi_master_slave_mode_t mode)
+{
+ BW_SPI_MCR_MSTR(baseAddr, (uint32_t)mode);
+}
+
+/*!
+ * @brief Returns whether the DSPI module is in master mode.
+ *
+ * @param baseAddr Module base address
+ * @retval true The module is in master mode.
+ * @retval false The module is in slave mode.
+ */
+static inline bool DSPI_HAL_IsMaster(uint32_t baseAddr)
+{
+ return (bool)BR_SPI_MCR_MSTR(baseAddr);
+}
+
+/*!
+ * @brief Configures the DSPI for the continuous SCK operation.
+ *
+ * @param baseAddr Module base address
+ * @param enable Enables (true) or disables(false) continuous SCK operation.
+ */
+static inline void DSPI_HAL_SetContinuousSckCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_CONT_SCKE(baseAddr, (enable == true));
+}
+
+/*!
+ * @brief Configures the DSPI to enable modified timing format.
+ *
+ * @param baseAddr Module base address
+ * @param enable Enables (true) or disables(false) modified timing format.
+ */
+static inline void DSPI_HAL_SetModifiedTimingFormatCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_MTFE(baseAddr, (enable == true));
+}
+
+/*!
+ * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the
+ * active-low PCS Strobe output.
+ *
+ * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral
+ * Chip Select in master mode. When configured as a strobe, it provides a signal to an external
+ * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
+ *
+ * @param baseAddr Module base address
+ * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
+ * If disable (false), PCS[5] operates as a peripheral chip select
+ */
+static inline void DSPI_HAL_SetPcsStrobeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_PCSSE(baseAddr, (enable == true));
+}
+
+/*!
+ * @brief Configures the DSPI received FIFO overflow overwrite enable.
+ *
+ * When enabled, this function allows incoming receive data to overwrite the existing data in the
+ * receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data
+ * is ignored when the RX FIFO is full.
+ *
+ * @param baseAddr Module base address.
+ * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
+ * else incoming data is ignored.
+ */
+static inline void DSPI_HAL_SetRxFifoOverwriteCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_ROOE(baseAddr, (enable == true));
+}
+
+/*!
+ * @brief Configures the DSPI peripheral chip select polarity.
+ *
+ * This function takes in the desired peripheral chip select (PCS) and it's
+ * corresponding desired polarity and configures the PCS signal to operate with the
+ * desired characteristic.
+ *
+ * @param baseAddr Module base address
+ * @param pcs The particular peripheral chip select (parameter value is of type
+ * dspi_which_pcs_config_t) for which we wish to apply the active high or active
+ * low characteristic.
+ * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or
+ * "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
+ */
+void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
+ dspi_pcs_polarity_config_t activeLowOrHigh);
+
+/*!
+ * @brief Enables (or disables) the DSPI FIFOs.
+ *
+ * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
+ * configuration. To enable, the caller must pass in a logic 1 (true).
+ *
+ * @param baseAddr Module instance number
+ * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
+ * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
+ */
+void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo);
+
+/*!
+ * @brief Flushes the DSPI FIFOs.
+ *
+ * @param baseAddr Module base address
+ * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
+ * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
+ */
+void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo);
+
+
+/*!
+ * @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format.
+ *
+ * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
+ * Format. Note that this is valid only when the CPHA bit in the CTAR register is 0.
+ *
+ * @param baseAddr Module base address
+ * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
+ * This value selects either 0, 1, or 2 system clocks between the SCK edge
+ * and the SIN (data in) sample.
+ */
+static inline void DSPI_HAL_SetDatainSamplepointMode(uint32_t baseAddr,
+ dspi_master_sample_point_t samplePnt)
+{
+ BW_SPI_MCR_SMPL_PT(baseAddr, samplePnt);
+}
+
+
+/*!
+ * @brief Starts the DSPI transfers, clears HALT bit in MCR.
+ *
+ * This function call called whenever the module is ready to begin data transfers in either master
+ * or slave mode.
+ *
+ * @param baseAddr Module base address
+ */
+static inline void DSPI_HAL_StartTransfer(uint32_t baseAddr)
+{
+ BW_SPI_MCR_HALT(baseAddr, 0);
+}
+
+/*!
+ * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR.
+ *
+ * This function call stops data transfers in either master or slave mode.
+ *
+ * @param baseAddr Module base address
+ */
+static inline void DSPI_HAL_StopTransfer(uint32_t baseAddr)
+{
+ BW_SPI_MCR_HALT(baseAddr, 1);
+}
+
+/*!
+ * @brief Configures the data format for a particular CTAR.
+ *
+ * This function configures the bits-per-frame, polarity, phase, and shift direction for a
+ * particular CTAR. An example use case is as follows:
+ @code
+ dspi_data_format_config_t dataFormat;
+ dataFormat.bitsPerFrame = 16;
+ dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
+ dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
+ dataFormat.direction = kDspiMsbFirst;
+ DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ * dspi_ctar_selection_t.
+ * @param config Pointer to structure containing user defined data format configuration settings.
+ * @return An error code or kStatus_DSPI_Success
+ */
+dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
+ dspi_ctar_selection_t whichCtar,
+ const dspi_data_format_config_t * config);
+
+/*!
+ * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
+ *
+ * This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
+ * after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay
+ * after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the prescaler and scaler value.
+ * This allows the user to directly set the prescaler/scaler values if they have
+ * pre-calculated them or if they simply wish to manually increment either value.
+ *
+ * @param baseAddr Module base address
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ * dspi_ctar_selection_t.
+ * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
+ * @param prescaler The scaler delay value (can be any integer between 0 to 15).
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ */
+void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
+ uint32_t scaler, dspi_delay_type_t whichDelay);
+
+
+/*!
+ * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in
+ * nano-seconds. The function calculates the values needed for the prescaler and scaler and
+ * returning the actual calculated delay as an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay will be returned. It is to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *
+ * @param baseAddr Module base address
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ * dspi_ctar_selection_t.
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param sourceClockInHz Module source input clock in Hertz
+ * @param delayInNanoSec The desired delay value in nano-seconds.
+ * @return The actual calculated delay value.
+ */
+uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+ dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
+ uint32_t delayInNanoSec);
+
+/*@}*/
+
+/*!
+ * @name Low power
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI operation during doze mode.
+ *
+ * This function provides support for an externally controlled doze mode, power-saving, mechanism.
+ * When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode
+ * disables the DSPI.
+ *
+ * @param baseAddr Module base address
+ * @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true),
+ * the doze mode disables the DSPI.
+ */
+static inline void DSPI_HAL_SetDozemodeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_DOZE(baseAddr, (enable == true));
+}
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests.
+ *
+ * This function configures the DSPI Tx FIFO Fill flag to generate either
+ * an interrupt or DMA request. The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ @code
+ DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
+ @endcode
+ * @param baseAddr Module base address
+ * @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request
+ * @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests
+ */
+void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
+
+/*!
+ * @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
+ *
+ * This function configures the DSPI Rx FIFO Drain flag to generate either
+ * an interrupt or a DMA request. The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ @code
+ DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
+ @endcode
+ * @param baseAddr Module base address
+ * @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request
+ * @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests
+ */
+void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
+
+
+
+/*!
+ * @brief Configures the DSPI interrupts.
+ *
+ * This function configures the various interrupt sources of the DSPI. The parameters are
+ * baseAddr, interrupt source, and enable/disable setting.
+ * The interrupt source is a typedef enumeration whose value is the bit position of the
+ * interrupt source setting within the RSER register. In the DSPI, all interrupt
+ * configuration settings are in one register. The typedef enum equates each
+ * interrupt source to the bit position defined in the device header file.
+ * The function uses these bit positions in its algorithm to enable/disable the
+ * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
+ * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
+ * these requests can generate either an interrupt or DMA request.
+ @code
+ DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
+ * @param enable Enable (true) or disable (false) the interrupt source to generate requests
+ */
+void DSPI_HAL_SetIntMode(uint32_t baseAddr,
+ dspi_status_and_interrupt_request_t interruptSrc,
+ bool enable);
+
+
+/*!
+ * @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
+ *
+ * This function returns the requested interrupt source setting (enabled or disabled, of
+ * type bool). The parameters to pass in are baseAddr and interrupt source. It utilizes the
+ * same enumeration definitions for the interrupt sources as described in the "interrupt configuration"
+ * function. The function uses these bit positions in its algorithm to obtain the desired
+ * interrupt source setting.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their
+ * requests are enabled.
+ @code
+ getInterruptSetting = DSPI_HAL_GetIntMode(baseAddr, kDspiTxComplete);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
+ * @return Configuration of interrupt request: enable (true) or disable (false).
+ */
+static inline bool DSPI_HAL_GetIntMode(uint32_t baseAddr,
+ dspi_status_and_interrupt_request_t interruptSrc)
+{
+ return ((HW_SPI_RSER_RD(baseAddr) >> interruptSrc) & 0x1);
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the DSPI status flag state.
+ *
+ * The status flag is defined in the same enumeration as the interrupt source enable because the bit
+ * position of the interrupt source and corresponding status flag are the same in the RSER and
+ * SR registers. The function uses these bit positions in its algorithm to obtain the desired
+ * flag state, similar to the dspi_get_interrupt_config function.
+ @code
+ getStatus = DSPI_HAL_GetStatusFlag(baseAddr, kDspiTxComplete);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
+ * @return State of the status flag: asserted (true) or not-asserted (false)
+ */
+static inline bool DSPI_HAL_GetStatusFlag(uint32_t baseAddr,
+ dspi_status_and_interrupt_request_t statusFlag)
+{
+ return ((HW_SPI_SR_RD(baseAddr) >> statusFlag) & 0x1);
+}
+
+/*!
+ * @brief Clears the DSPI status flag.
+ *
+ * This function clears the desired status bit by using a write-1-to-clear. The user passes in
+ * the baseAddr and the desired status bit to clear. The list of status bits is defined in the
+ * dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm
+ * to clear the desired flag state. Example usage:
+ @code
+ DSPI_HAL_ClearStatusFlag(baseAddr, kDspiTxComplete);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
+ */
+static inline void DSPI_HAL_ClearStatusFlag(uint32_t baseAddr,
+ dspi_status_and_interrupt_request_t statusFlag)
+{
+ HW_SPI_SR_SET(baseAddr, (0x1U << statusFlag));
+}
+
+
+/*!
+ * @brief Gets the DSPI FIFO counter or pointer.
+ *
+ * This function returns the number of entries or the next pointer in the Tx or Rx FIFO.
+ * The parameters to pass in are the baseAddr and either the Tx or Rx FIFO counter or a
+ * pointer. The latter is an enumeration type defined as the bitmask of
+ * those particular bit fields found in the device header file. Example usage:
+ @code
+ DSPI_HAL_GetFifoCountOrPtr(baseAddr, kDspiRxFifoCounter);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t
+ */
+static inline uint32_t DSPI_HAL_GetFifoCountOrPtr(uint32_t baseAddr,
+ dspi_fifo_counter_pointer_t desiredParameter)
+{
+ return ((HW_SPI_SR_RD(baseAddr) >> desiredParameter) & 0xFU);
+}
+
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Reads data from the data buffer.
+ *
+ * @param baseAddr Module base address
+ */
+static inline uint32_t DSPI_HAL_ReadData(uint32_t baseAddr)
+{
+ return HW_SPI_POPR_RD(baseAddr);
+}
+
+/*!
+ * @brief Writes data into the data buffer, slave mode.
+ *
+ * In slave mode, up to 32-bit words may be written.
+ *
+ * @param baseAddr Module base address
+ * @param data The data to send
+ */
+static inline void DSPI_HAL_WriteDataSlavemode(uint32_t baseAddr, uint32_t data)
+{
+ HW_SPI_PUSHR_SLAVE_WR(baseAddr, data);
+}
+
+/*!
+ * @brief Writes data into the data buffer, master mode.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+ @code
+ dspi_command_config_t commandConfig;
+ commandConfig.isChipSelectContinuous = true;
+ commandConfig.whichCtar = kDspiCtar0;
+ commandConfig.whichPcs = kDspiPcs1;
+ commandConfig.clearTransferCount = false;
+ commandConfig.isEndOfQueue = false;
+ DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
+ @endcode
+ *
+ * @param baseAddr Module base address
+ * @param command Pointer to command structure
+ * @param data The data word to be sent
+ */
+void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
+ dspi_command_config_t * command,
+ uint16_t data);
+
+/*!
+ * @brief Writes data into the data buffer, master mode and waits till complete to return.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+ @code
+ dspi_command_config_t commandConfig;
+ commandConfig.isChipSelectContinuous = true;
+ commandConfig.whichCtar = kDspiCtar0;
+ commandConfig.whichPcs = kDspiPcs1;
+ commandConfig.clearTransferCount = false;
+ commandConfig.isEndOfQueue = false;
+ DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
+ @endcode
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data is available when transmit completes.
+ *
+ * @param baseAddr Module base address
+ * @param command Pointer to command structure
+ * @param data The data word to be sent
+ */
+void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
+ dspi_command_config_t * command,
+ uint16_t data);
+
+/*!
+ * @brief Gets the transfer count.
+ *
+ * This function returns the current value of the DSPI Transfer Count Register.
+ *
+ * @param baseAddr Module base address
+ * @return The current transfer count
+ */
+static inline uint32_t DSPI_HAL_GetTransferCount(uint32_t baseAddr)
+{
+ return BR_SPI_TCR_SPI_TCNT(baseAddr);
+}
+
+/*!
+ * @brief Pre-sets the transfer count.
+ *
+ * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
+ * to 65535; Incrementing past this resets the counter back to 0.
+ *
+ * @param baseAddr Module base address
+ * @param presetValue The desired pre-set value for the transfer counter
+ */
+static inline void DSPI_HAL_PresetTransferCount(uint32_t baseAddr, uint16_t presetValue)
+{
+ BW_SPI_TCR_SPI_TCNT(baseAddr, presetValue);
+}
+
+/*@}*/
+
+/*!
+ * @name Debug
+ * @{
+ */
+
+/*!
+ * @brief Reads FIFO registers for debug purposes.
+ *
+ * @param baseAddr Module base address
+ * @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t.
+ * @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3.
+ * @return The desired FIFO register contents
+ */
+uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
+
+/*!
+ * @brief Configures the DSPI to halt during debug mode.
+ *
+ * @param baseAddr Module base address
+ * @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer
+ * in debug mode.
+ */
+static inline void DSPI_HAL_SetHaltInDebugmodeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SPI_MCR_FRZ(baseAddr, (enable == true));
+}
+
+/* @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_DSPI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,135 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_EDMA_FEATURES_H__) +#define __FSL_EDMA_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) +#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \ + defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || \ + defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || \ + defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ + defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || \ + defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ + defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ + defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) + /* @brief Total number of DMA channels on all modules. */ + #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) + /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) + /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ + #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_EDMA_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,633 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include "fsl_edma_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_Init
+ * Description : Initializes eDMA module to known state.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_Init(uint32_t baseAddr)
+{
+ uint32_t i;
+
+ /* Risk there, in SoCs with more than 1 group, we can't set the CR
+ * register to 0, or fault may happens. Stange that in K70 spec,
+ * the RM tell the reset value is 0. */
+ HW_DMA_CR_WR(baseAddr, 0U);
+
+ for (i = 0; i < FSL_FEATURE_EDMA_MODULE_CHANNEL; i++)
+ {
+ EDMA_HAL_HTCDClearReg(baseAddr, i);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_CancelTransfer
+ * Description : Cancels the remaining data transfer.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_CancelTransfer(uint32_t baseAddr)
+{
+ BW_DMA_CR_CX(baseAddr, 1U);
+ while (BR_DMA_CR_CX(baseAddr))
+ {}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_ErrorCancelTransfer
+ * Description : Cancels the remaining data transfer and treat it as error.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_ErrorCancelTransfer(uint32_t baseAddr)
+{
+ BW_DMA_CR_ECX(baseAddr, 1U);
+ while (BR_DMA_CR_ECX(baseAddr))
+ {}
+}
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetGroupPriority
+ * Description :
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetGroupPriority(uint32_t baseAddr, edma_group_priority_t groupPriority)
+{
+
+ if (groupPriority == kEDMAGroup0PriorityLowGroup1PriorityHigh)
+ {
+ BW_DMA_CR_GRP0PRI(baseAddr, 0U);
+ BW_DMA_CR_GRP1PRI(baseAddr, 1U);
+ }
+ else
+ {
+ BW_DMA_CR_GRP0PRI(baseAddr, 1U);
+ BW_DMA_CR_GRP1PRI(baseAddr, 0U);
+ }
+
+}
+#endif
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetErrorIntCmd
+ * Description : Enable/Disable error interrupt for channels.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetErrorIntCmd(uint32_t baseAddr, bool enable, edma_channel_indicator_t channel)
+{
+
+ if (enable)
+ {
+ HW_DMA_SEEI_WR(baseAddr, channel);
+ }
+ else
+ {
+ HW_DMA_CEEI_WR(baseAddr, channel);
+ }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetDmaRequestCmd
+ * Description : Enable/Disable dma request for channel or all channels.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetDmaRequestCmd(uint32_t baseAddr, edma_channel_indicator_t channel,bool enable)
+{
+
+ if (enable)
+ {
+ HW_DMA_SERQ_WR(baseAddr, channel);
+ }
+ else
+ {
+ HW_DMA_CERQ_WR(baseAddr, channel);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_GetErrorIntCmd
+ * Description : Gets eDMA channel error interrupt enable status.
+ *
+ *END**************************************************************************/
+bool EDMA_HAL_GetErrorIntCmd(uint32_t baseAddr, uint32_t channel)
+{
+ return (bool)((HW_DMA_EEI_RD(baseAddr) >> channel) & 1U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDClearReg
+ * Description : Set registers to 0 for hardware TCD of eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDClearReg(uint32_t baseAddr,uint32_t channel)
+{
+ HW_DMA_TCDn_SADDR_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_SOFF_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_ATTR_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_NBYTES_MLNO_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_SLAST_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_DADDR_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_DOFF_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_CITER_ELINKNO_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_DLASTSGA_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_CSR_WR(baseAddr, channel, 0U);
+ HW_DMA_TCDn_BITER_ELINKNO_WR(baseAddr, channel, 0U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetAttribute
+ * Description : Configures the transfer attribute for eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetAttribute(
+ uint32_t baseAddr, uint32_t channel,
+ edma_modulo_t srcModulo, edma_modulo_t destModulo,
+ edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ HW_DMA_TCDn_ATTR_WR(baseAddr, channel,
+ BF_DMA_TCDn_ATTR_SMOD(srcModulo) | BF_DMA_TCDn_ATTR_DMOD(destModulo) |
+ BF_DMA_TCDn_ATTR_SSIZE(srcTransferSize) | BF_DMA_TCDn_ATTR_DSIZE(destTransferSize));
+
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetNbytes
+ * Description : Configures the nbytes for eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetNbytes(uint32_t baseAddr, uint32_t channel, uint32_t nbytes)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (BR_DMA_CR_EMLM(baseAddr))
+ {
+ if (!(BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(baseAddr, channel) ||
+ BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(baseAddr, channel)))
+ {
+ BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel, nbytes);
+ }
+ else
+ {
+ BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(baseAddr, channel, nbytes);
+ }
+
+ }
+ else
+ {
+ BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel, nbytes);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_GetHTCDNbytes
+ * Description : Get nbytes configuration data.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetNbytes(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (BR_DMA_CR_EMLM(baseAddr))
+ {
+ if (BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel) ||
+ BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel))
+ {
+ return BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(baseAddr, channel);
+ }
+ else
+ {
+ return BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel);
+ }
+ }
+ else
+ {
+ return BR_DMA_TCDn_NBYTES_MLNO_NBYTES(baseAddr, channel);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_SetMinorLoopOffset
+ * Description : Configures the minorloop offset for the hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetMinorLoopOffset(
+ uint32_t baseAddr, uint32_t channel, edma_minorloop_offset_config_t *config)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true))
+ {
+ BW_DMA_CR_EMLM(baseAddr, true);
+ BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel, config->enableSrcMinorloop);
+ BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(baseAddr, channel, config->enableDestMinorloop);
+ BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(baseAddr, channel, config->offset);
+ }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetScatterGatherLink
+ * Description : Configures the memory address for the next transfer TCD for the hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetScatterGatherLink(
+ uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_ESG(baseAddr, channel, true);
+ BW_DMA_TCDn_DLASTSGA_DLASTSGA(baseAddr, channel, (uint32_t)stcd);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_SetChannelMinorLink
+ * Description : Set Channel minor link for hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetChannelMinorLink(
+ uint32_t baseAddr, uint32_t channel, uint32_t linkChannel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (enable)
+ {
+ BW_DMA_TCDn_BITER_ELINKYES_ELINK(baseAddr, channel, enable);
+ BW_DMA_TCDn_BITER_ELINKYES_LINKCH(baseAddr, channel, linkChannel);
+ BW_DMA_TCDn_CITER_ELINKYES_ELINK(baseAddr, channel, enable);
+ BW_DMA_TCDn_CITER_ELINKYES_LINKCH(baseAddr, channel, linkChannel);
+ }
+ else
+ {
+ BW_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel, enable);
+ BW_DMA_TCDn_CITER_ELINKNO_ELINK(baseAddr, channel, enable);
+ }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_HTCDSetMajorCount
+ * Description : Sets the major iteration count according to minor loop channel link setting.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetMajorCount(uint32_t baseAddr, uint32_t channel, uint32_t count)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel))
+ {
+ BW_DMA_TCDn_BITER_ELINKYES_BITER(baseAddr, channel, count);
+ BW_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel, count);
+ }
+ else
+ {
+ BW_DMA_TCDn_BITER_ELINKNO_BITER(baseAddr, channel, count);
+ BW_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel, count);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_HTCDSetMajorCount
+ * Description : Gets the begin major iteration count according to minor loop channel link setting.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetBeginMajorCount(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel))
+ {
+ return BR_DMA_TCDn_BITER_ELINKYES_BITER(baseAddr, channel);
+ }
+ else
+ {
+ return BR_DMA_TCDn_BITER_ELINKNO_BITER(baseAddr, channel);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_HTCDGetCurrentMajorCount
+ * Description : Gets the current major iteration count according to minor loop channel link setting.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel))
+ {
+ return BR_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel);
+ }
+ else
+ {
+ return BR_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetUnfinishedBytes
+ * Description : Get the bytes number of bytes haven't been transferred for this hardware TCD.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t nbytes;
+
+ nbytes = EDMA_HAL_HTCDGetNbytes(baseAddr, channel);
+
+ if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel))
+ {
+ return (BR_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel) * nbytes);
+
+ }
+ else
+ {
+ return (BR_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel) * nbytes);
+
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetFinishedBytes
+ * Description : Get the bytes number of bytes already be transferred for this hardware TCD.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetFinishedBytes(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t nbytes, begin_majorcount, current_majorcount;
+
+ nbytes = EDMA_HAL_HTCDGetNbytes(baseAddr, channel);
+ begin_majorcount = EDMA_HAL_HTCDGetBeginMajorCount(baseAddr,channel);
+ current_majorcount = EDMA_HAL_HTCDGetCurrentMajorCount(baseAddr,channel);
+
+ return ((begin_majorcount - current_majorcount) * nbytes);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetAttribute
+ * Description : Configures the transfer attribute for software TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetAttribute(
+ edma_software_tcd_t *stcd,
+ edma_modulo_t srcModulo, edma_modulo_t destModulo,
+ edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
+{
+ assert(stcd);
+
+ stcd->ATTR = DMA_ATTR_SMOD(srcModulo) | DMA_ATTR_DMOD(destModulo) |
+ DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetNbytes
+ * Description : Configures the nbytes for software TCD
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetNbytes(uint32_t baseAddr, edma_software_tcd_t *stcd, uint32_t nbytes)
+{
+ assert(stcd);
+
+ if (BR_DMA_CR_EMLM(baseAddr))
+ {
+ if (stcd->NBYTES.MLOFFNO | (DMA_NBYTES_MLOFFNO_SMLOE_MASK | DMA_NBYTES_MLOFFNO_DMLOE_MASK))
+ {
+ stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES & ~DMA_NBYTES_MLOFFYES_NBYTES_MASK) |
+ DMA_NBYTES_MLOFFYES_NBYTES(nbytes);
+ }
+ else
+ {
+ stcd->NBYTES.MLOFFNO = (stcd->NBYTES.MLOFFNO & ~DMA_NBYTES_MLOFFNO_NBYTES_MASK) |
+ DMA_NBYTES_MLOFFNO_NBYTES(nbytes);
+ }
+ }
+ else
+ {
+ stcd->NBYTES.MLNO = (stcd->NBYTES.MLNO & ~DMA_NBYTES_MLNO_NBYTES_MASK) |
+ DMA_NBYTES_MLNO_NBYTES(nbytes);
+ }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetMinorLoopOffset
+ * Description :
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetMinorLoopOffset(
+ uint32_t baseAddr, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config)
+{
+ assert(stcd);
+ stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES &
+ ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) |
+ (((uint32_t)config->enableSrcMinorloop << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) |
+ ((uint32_t)config->enableDestMinorloop << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT));
+
+ if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true))
+ {
+ BW_DMA_CR_EMLM(baseAddr, true);
+ stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES & ~DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
+ DMA_NBYTES_MLOFFYES_MLOFF(config->offset);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name :
+ * Description :
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetScatterGatherLink(
+ edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd)
+{
+ assert(stcd);
+ assert(nextStcd);
+ EDMA_HAL_STCDSetScatterGatherCmd(stcd, true);
+ stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA((uint32_t)nextStcd);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetChannelMinorLink
+ * Description :
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetChannelMinorLink(
+ edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable)
+{
+ assert(stcd);
+
+ if (enable)
+ {
+ stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_ELINK_MASK) |
+ ((uint32_t)enable << DMA_BITER_ELINKYES_ELINK_SHIFT);
+ stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_LINKCH_MASK) |
+ DMA_BITER_ELINKYES_LINKCH(linkChannel);
+ stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_ELINK_MASK) |
+ ((uint32_t)enable << DMA_CITER_ELINKYES_ELINK_SHIFT);
+ stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_LINKCH_MASK) |
+ DMA_CITER_ELINKYES_LINKCH(linkChannel);
+ }
+ else
+ {
+ stcd->BITER.ELINKNO = (stcd->BITER.ELINKNO & ~DMA_BITER_ELINKNO_ELINK_MASK) |
+ ((uint32_t)enable << DMA_BITER_ELINKNO_ELINK_SHIFT);
+ stcd->CITER.ELINKNO = (stcd->CITER.ELINKNO & ~DMA_CITER_ELINKNO_ELINK_MASK) |
+ ((uint32_t)enable << DMA_CITER_ELINKNO_ELINK_SHIFT);
+ }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetMajorCount
+ * Description : Sets the major iteration count according to minor loop channel link setting.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count)
+{
+ assert(stcd);
+
+ if (stcd->BITER.ELINKNO & DMA_BITER_ELINKNO_ELINK_MASK)
+ {
+ stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_BITER_MASK) |
+ DMA_BITER_ELINKYES_BITER(count);
+ stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_CITER_MASK) |
+ DMA_CITER_ELINKYES_CITER(count);
+ }
+ else
+ {
+ stcd->BITER.ELINKNO = (stcd->BITER.ELINKNO & ~DMA_BITER_ELINKNO_BITER_MASK) |
+ DMA_BITER_ELINKNO_BITER(count);
+ stcd->CITER.ELINKNO = (stcd->CITER.ELINKNO & ~DMA_CITER_ELINKNO_CITER_MASK) |
+ DMA_CITER_ELINKNO_CITER(count);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_PushSTCDToHTCD
+ * Description : Copy the configuration data from the software TCD to hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_PushSTCDToHTCD(uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(stcd);
+
+ HW_DMA_TCDn_SADDR_WR(baseAddr, channel, stcd->SADDR);
+ HW_DMA_TCDn_SOFF_WR(baseAddr, channel, stcd->SOFF);
+ HW_DMA_TCDn_ATTR_WR(baseAddr, channel, stcd->ATTR);
+ HW_DMA_TCDn_NBYTES_MLNO_WR(baseAddr, channel, stcd->NBYTES.MLNO);
+ HW_DMA_TCDn_SLAST_WR(baseAddr, channel, stcd->SLAST);
+ HW_DMA_TCDn_DADDR_WR(baseAddr, channel, stcd->DADDR);
+ HW_DMA_TCDn_DOFF_WR(baseAddr, channel, stcd->DOFF);
+ HW_DMA_TCDn_CITER_ELINKYES_WR(baseAddr, channel, stcd->CITER.ELINKYES);
+ HW_DMA_TCDn_DLASTSGA_WR(baseAddr, channel, stcd->DLAST_SGA);
+ HW_DMA_TCDn_CSR_WR(baseAddr, channel, stcd->CSR);
+ HW_DMA_TCDn_BITER_ELINKYES_WR(baseAddr, channel, stcd->BITER.ELINKYES);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetSTCDBasicTransfer
+ * Description : Set the basic transfer for software TCD.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_HAL_STCDSetBasicTransfer(
+ uint32_t baseAddr, edma_software_tcd_t *stcd, edma_transfer_config_t *config,
+ bool enableInt, bool disableDmaRequest)
+{
+ assert(stcd);
+
+ EDMA_HAL_STCDSetSrcAddr(stcd, config->srcAddr);
+ EDMA_HAL_STCDSetDestAddr(stcd, config->destAddr);
+
+ EDMA_HAL_STCDSetSrcOffset(stcd, config->srcOffset);
+ EDMA_HAL_STCDSetDestOffset(stcd, config->destOffset);
+
+ EDMA_HAL_STCDSetAttribute(stcd, config->srcModulo, config->destModulo,
+ config->srcTransferSize, config->destTransferSize);
+
+ EDMA_HAL_STCDSetSrcLastAdjust(stcd, config->srcLastAddrAdjust);
+ EDMA_HAL_STCDSetDestLastAdjust(stcd, config->destLastAddrAdjust);
+ EDMA_HAL_STCDSetNbytes(baseAddr, stcd, config->minorLoopCount);
+ EDMA_HAL_STCDSetMajorCount(stcd, config->majorLoopCount);
+
+ EDMA_HAL_STCDSetIntCmd(stcd, enableInt);
+ EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(stcd, disableDmaRequest);
+ return kStatus_EDMA_Success;
+}
+
+#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetAsyncRequestInStopModeCmd
+ * Description : Enables/Disables an asynchronous request in stop mode.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetAsyncRequestInStopModeCmd(uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if(enable)
+ {
+ HW_DMA_EARS_SET(baseAddr, 1U << channel);
+ }
+ else
+ {
+ HW_DMA_EARS_CLR(baseAddr, 1U << channel);
+ }
+}
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1418 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __EDMA_HAL_H__
+#define __EDMA_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_edma_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup edma_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error code for the eDMA Driver. */
+typedef enum _edma_status {
+ kStatus_EDMA_Success = 0U,
+ kStatus_EDMA_InvalidArgument = 1U, /*!< Parameter is invalid. */
+ kStatus_EDMA_Fail = 2U /*!< Failed operation. */
+} edma_status_t;
+
+/*! @brief eDMA channel arbitration algorithm used for selection among channels. */
+typedef enum _edma_channel_arbitration {
+ kEDMAChnArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for selection
+ among channels. */
+ kEDMAChnArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection among
+ channels. */
+} edma_channel_arbitration_t;
+
+/*! @brief eDMA channel priority setting */
+typedef enum _edma_chn_priority {
+ kEDMAChnPriority0 = 0U,
+ kEDMAChnPriority1,
+ kEDMAChnPriority2,
+ kEDMAChnPriority3,
+ kEDMAChnPriority4,
+ kEDMAChnPriority5,
+ kEDMAChnPriority6,
+ kEDMAChnPriority7,
+ kEDMAChnPriority8,
+ kEDMAChnPriority9,
+ kEDMAChnPriority10,
+ kEDMAChnPriority11,
+ kEDMAChnPriority12,
+ kEDMAChnPriority13,
+ kEDMAChnPriority14,
+ kEDMAChnPriority15
+} edma_channel_priority_t;
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*! @brief eDMA group arbitration algorithm used for selection among channels. */
+typedef enum _edma_group_arbitration
+{
+ kEDMAGroupArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for
+ selection among eDMA groups. */
+ kEDMAGroupArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection
+ among eDMA channels. */
+} edma_group_arbitration_t;
+
+/*! @brief eDMA group priority setting */
+typedef enum _edma_group_priority {
+ kEDMAGroup0PriorityLowGroup1PriorityHigh, /*!< eDMA group 0's priority is lower priority.
+ eDMA group 1's priority is higher priority. */
+ kEDMAGroup0PriorityHighGroup1PriorityLow /*!< eDMA group 0's priority is higher priority.
+ eDMA group 1's priority is lower priority. */
+} edma_group_priority_t;
+#endif
+
+/*! @brief eDMA modulo configuration */
+typedef enum _edma_modulo {
+ kEDMAModuloDisable = 0U,
+ kEDMAModulo2bytes,
+ kEDMAModulo4bytes,
+ kEDMAModulo8bytes,
+ kEDMAModulo16bytes,
+ kEDMAModulo32bytes,
+ kEDMAModulo64bytes,
+ kEDMAModulo128bytes,
+ kEDMAModulo256bytes,
+ kEDMAModulo512bytes,
+ kEDMAModulo1Kbytes,
+ kEDMAModulo2Kbytes,
+ kEDMAModulo4Kbytes,
+ kEDMAModulo8Kbytes,
+ kEDMAModulo16Kbytes,
+ kEDMAModulo32Kbytes,
+ kEDMAModulo64Kbytes,
+ kEDMAModulo128Kbytes,
+ kEDMAModulo256Kbytes,
+ kEDMAModulo512Kbytes,
+ kEDMAModulo1Mbytes,
+ kEDMAModulo2Mbytes,
+ kEDMAModulo4Mbytes,
+ kEDMAModulo8Mbytes,
+ kEDMAModulo16Mbytes,
+ kEDMAModulo32Mbytes,
+ kEDMAModulo64Mbytes,
+ kEDMAModulo128Mbytes,
+ kEDMAModulo256Mbytes,
+ kEDMAModulo512Mbytes,
+ kEDMAModulo1Gbytes,
+ kEDMAModulo2Gbytes
+} edma_modulo_t;
+
+/*! @brief eDMA transfer configuration */
+typedef enum _edma_transfer_size {
+ kEDMATransferSize_1Bytes = 0x0U,
+ kEDMATransferSize_2Bytes = 0x1U,
+ kEDMATransferSize_4Bytes = 0x2U,
+ kEDMATransferSize_16Bytes = 0x4U,
+ kEDMATransferSize_32Bytes = 0x5U
+} edma_transfer_size_t;
+
+/*!
+ * @brief eDMA transfer size configuration.
+ *
+ * This structure configures the basic source/destination transfer attribute.
+ * This figure shows the eDMA's transfer model:
+ * _________________________________________________
+ * | Transfer Size | |
+ * Minor Loop |_______________| Major loop Count 1 |
+ * Count | Transfer Size | |
+ * ____________|_______________|____________________|--> Minor loop complete
+ * ____________________________________
+ * | | |
+ * |_______________| Major Loop Count 2 |
+ * | | |
+ * |_______________|____________________|--> Minor loop Complete
+ *
+ * ---------------------------------------------------------> Major loop complete
+ *
+ */
+typedef struct EDMATransferConfig {
+ uint32_t srcAddr; /*!< Memory address pointing to the source data. */
+ uint32_t destAddr; /*!< Memory address pointing to the destination data. */
+ edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */
+ edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
+ int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to
+ form the next-state value as each source read/write is
+ completed. */
+ int16_t destOffset;
+ uint32_t srcLastAddrAdjust; /*!< Last source address adjustment. */
+ uint32_t destLastAddrAdjust; /*!< Last destination address adjustment. Note here it is only
+ valid when scatter/gather feature is not enabled. */
+ edma_modulo_t srcModulo; /*!< Source address modulo. */
+ edma_modulo_t destModulo; /*!< Destination address modulo. */
+ uint32_t minorLoopCount; /*!< Minor bytes transfer count. Number of bytes to be transferred
+ in each service request of the channel. */
+ uint16_t majorLoopCount; /*!< Major iteration count. */
+} edma_transfer_config_t;
+
+/*! @brief eDMA channel configuration. */
+typedef enum _edma_channel_indicator {
+ kEDMAChannel0 = 0U, /*!< Channel 0. */
+ kEDMAChannel1 = 1U,
+ kEDMAChannel2 = 2U,
+ kEDMAChannel3 = 3U,
+#if (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U)
+ kEDMAChannel4 = 4U,
+ kEDMAChannel5 = 5U,
+ kEDMAChannel6 = 6U,
+ kEDMAChannel7 = 7U,
+ kEDMAChannel8 = 8U,
+ kEDMAChannel9 = 9U,
+ kEDMAChannel10 = 10U,
+ kEDMAChannel11 = 11U,
+ kEDMAChannel12 = 12U,
+ kEDMAChannel13 = 13U,
+ kEDMAChannel14 = 14U,
+ kEDMAChannel15 = 15U,
+#endif
+#if (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U)
+ kEDMAChannel16 = 16U,
+ kEDMAChannel17 = 17U,
+ kEDMAChannel18 = 18U,
+ kEDMAChannel19 = 19U,
+ kEDMAChannel20 = 20U,
+ kEDMAChannel21 = 21U,
+ kEDMAChannel22 = 22U,
+ kEDMAChannel23 = 23U,
+ kEDMAChannel24 = 24U,
+ kEDMAChannel25 = 25U,
+ kEDMAChannel26 = 26U,
+ kEDMAChannel27 = 27U,
+ kEDMAChannel28 = 28U,
+ kEDMAChannel29 = 29U,
+ kEDMAChannel30 = 30U,
+ kEDMAChannel31 = 31U,
+#endif
+ kEDMAAllChannel = 64U
+} edma_channel_indicator_t;
+
+/*! @brief eDMA TCD Minor loop mapping configuration */
+typedef struct EDMAMinorLoopOffsetConfig {
+ bool enableSrcMinorloop; /*!< Enable(true) or Disable(false) source minor loop offset. */
+ bool enableDestMinorloop; /*!< Enable(true) or Disable(false) destination minor loop offset. */
+ uint32_t offset; /*!< Offset for minor loop mapping. */
+} edma_minorloop_offset_config_t;
+
+/*! @brief Error status of the eDMA module */
+typedef union EDMAErrorStatusAll {
+ struct {
+ uint32_t destinationBusError : 1; /*!< Bus error on destination address */
+ uint32_t sourceBusError : 1; /*!< Bus error on the SRC address */
+ uint32_t scatterOrGatherConfigurationError : 1; /*!< Error on the Scatter/Gather address */
+ uint32_t nbyteOrCiterConfigurationError : 1; /*!< NBYTES/CITER configuration error */
+ uint32_t destinationOffsetError : 1; /*!< Destination offset error */
+ uint32_t destinationAddressError : 1; /*!< Destination address error */
+ uint32_t sourceOffsetError : 1; /*!< Source offset error */
+ uint32_t sourceAddressError : 1; /*!< Source address error */
+ uint32_t errorChannel : 5; /*!< Error channel number of the cancelled
+ channel number */
+ uint32_t _reserved1 : 1;
+ uint32_t channelPriorityError : 1; /*!< Channel priority error */
+ uint32_t groupPriorityError : 1; /*!< Group priority error */
+ uint32_t transferCancelledError : 1; /*!< Transfer cancelled */
+ uint32_t _reserved0 : 14;
+ uint32_t orOfAllError : 1; /*!< Logical OR all ERR status bits */
+ } U;
+ uint32_t B;
+} edma_error_status_all_t;
+
+/*! @brief Bandwidth control configuration */
+typedef enum _edma_bandwidth_config {
+ kEDMABandwidthStallNone = 0U, /*!< No eDMA engine stalls. */
+ kEDMABandwidthStall4Cycle = 2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
+ kEDMABandwidthStall8Cycle = 3U /*!< eDMA engine stalls for 8 cycles after each read/write. */
+} edma_bandwidth_config_t;
+
+/*! @brief eDMA TCD */
+typedef struct EDMASoftwareTcd {
+ uint32_t SADDR;
+ uint16_t SOFF;
+ uint16_t ATTR;
+ union {
+ uint32_t MLNO;
+ uint32_t MLOFFNO;
+ uint32_t MLOFFYES;
+ } NBYTES;
+ uint32_t SLAST;
+ uint32_t DADDR;
+ uint16_t DOFF;
+ union {
+ uint16_t ELINKNO;
+ uint16_t ELINKYES;
+ } CITER;
+ uint32_t DLAST_SGA;
+ uint16_t CSR;
+ union {
+ uint16_t ELINKNO;
+ uint16_t ELINKYES;
+ } BITER;
+} edma_software_tcd_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA HAL driver module level operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes eDMA module to known state.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ */
+void EDMA_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Cancels the remaining data transfer.
+ *
+ * This function stops the executing channel and forces the minor loop
+ * to finish. The cancellation takes effect after the last write of the
+ * current read/write sequence. The CX clears itself after the cancel has
+ * been honored. This cancel retires the channel normally as if the minor
+ * loop had completed.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ */
+void EDMA_HAL_CancelTransfer(uint32_t baseAddr);
+
+/*!
+ * @brief Cancels the remaining data transfer and treats it as an error condition.
+ *
+ * This function stops the executing channel and forces the minor loop
+ * to finish. The cancellation takes effect after the last write of the
+ * current read/write sequence. The CX clears itself after the cancel has
+ * been honored. This cancel retires the channel normally as if the minor
+ * loop had completed. Additional thing is to treat this operation as an error
+ * condition.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ */
+void EDMA_HAL_ErrorCancelTransfer(uint32_t baseAddr);
+
+/*!
+ * @brief Halts/Un-halts the DMA Operations.
+ *
+ * This function stalls/un-stalls the start of any new channels. Executing channels are allowed
+ * to be completed.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param halt Halts (true) or un-halts (false) eDMA transfer.
+ */
+static inline void EDMA_HAL_SetHaltCmd(uint32_t baseAddr, bool halt)
+{
+ BW_DMA_CR_HALT(baseAddr, halt);
+}
+
+/*!
+ * @brief Halts or does not halt the eDMA module when an error occurs.
+ *
+ * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the
+ * HALT bit is cleared.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param haltOnError Halts (true) or not halt (false) eDMA module when an error occurs.
+ */
+static inline void EDMA_HAL_SetHaltOnErrorCmd(uint32_t baseAddr, bool haltOnError)
+{
+ BW_DMA_CR_HOE(baseAddr, haltOnError);
+}
+
+/*!
+ * @brief Enables/Disables the eDMA DEBUG mode.
+ *
+ * This function enables/disables the eDMA Debug mode.
+ * When in debug mode, the DMA stalls the start of a new
+ * channel. Executing channels are allowed to complete. Channel execution resumes
+ * either when the system exits debug mode or when the EDBG bit is cleared.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enables (true) or Disable (false) eDMA module debug mode.
+ */
+static inline void EDMA_HAL_SetDebugCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DMA_CR_EDBG(baseAddr, enable);
+}
+/* @} */
+
+/*!
+ * @name eDMA HAL driver channel priority and arbitration configuration.
+ * @{
+ */
+/*!
+ * @brief Sets the preempt and preemption feature for the eDMA channel.
+ *
+ * This function sets the preempt and preemption features.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param preempt eDMA channel can't suspend a lower priority channel (true). eDMA channel can
+ * suspend a lower priority channel (false).
+ * @param preemption eDMA channel can be temporarily suspended by the service request of a higher
+ * priority channel (true). eDMA channel can't be suspended by a higher priority channel (false).
+ */
+static inline void EDMA_HAL_SetChannelPreemptMode(
+ uint32_t baseAddr, uint32_t channel, bool preempt, bool preemption)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_DCHPRIn_DPA(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), preempt);
+ BW_DMA_DCHPRIn_ECP(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), preemption);
+}
+
+/*!
+ * @brief Sets the eDMA channel priority.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param priority Priority of the DMA channel. Different channels should have different priority
+ * setting inside a group.
+ */
+static inline void EDMA_HAL_SetChannelPriority(
+ uint32_t baseAddr, uint32_t channel, edma_channel_priority_t priority)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_DCHPRIn_CHPRI(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), priority);
+}
+/*!
+ * @brief Sets the channel arbitration algorithm.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channelArbitration Round-Robin way for fixed priority way.
+ */
+static inline void EDMA_HAL_SetChannelArbitrationMode(
+ uint32_t baseAddr, edma_channel_arbitration_t channelArbitration)
+{
+ BW_DMA_CR_ERCA(baseAddr, channelArbitration);
+}
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*!
+ * @brief Configures the group priority.
+ *
+ * This function configures the priority for group 0 and group 1.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param groupPriority Group priority configuration. Note that each group get its own
+ * group priority.
+ */
+void EDMA_HAL_SetGroupPriority(uint32_t baseAddr, edma_group_priority_t groupPriority);
+
+/*!
+ * @brief Sets the eDMA group arbitration algorithm.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param groupArbitration Group arbitration way. Fixed-Priority way or Round-Robin way.
+ */
+static inline void EDMA_HAL_SetGroupArbitrationMode(
+ uint32_t baseAddr, edma_group_arbitration_t groupArbitration)
+{
+ BW_DMA_CR_ERGA(baseAddr, groupArbitration);
+}
+#endif
+/* @} */
+
+/*!
+ * @name eDMA HAL driver configuration and operation.
+ * @{
+ */
+/*!
+ * @brief Enables/Disables the minor loop mapping.
+ *
+ * This function enables/disables the minor loop mapping feature.
+ * If enabled, the NBYTES is redefined to include the individual enable fields and the NBYTES field. The
+ * individual enable fields allow the minor loop offset to be applied to the source address, the
+ * destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enables (true) or Disable (false) minor loop mapping.
+ */
+static inline void EDMA_HAL_SetMinorLoopMappingCmd(uint32_t baseAddr, bool enable)
+{
+ BW_DMA_CR_EMLM(baseAddr, enable);
+}
+
+/*!
+ * @brief Enables or disables the continuous transfer mode.
+ *
+ * This function enables or disables the continuous transfer. If set, a minor loop channel link
+ * does not go through the channel arbitration before being activated again. Upon minor loop
+ * completion, the channel activates again if that channel has a minor loop channel link enabled and
+ * the link channel is itself.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param continuous Enables (true) or Disable (false) continuous transfer mode.
+ */
+static inline void EDMA_HAL_SetContinuousLinkCmd(uint32_t baseAddr, bool continuous)
+{
+ BW_DMA_CR_CLM(baseAddr, continuous);
+}
+
+/*!
+ * @brief Gets the error status of the eDMA module.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @return Detailed information of the error type in the eDMA module.
+ */
+static inline uint32_t EDMA_HAL_GetErrorStatus(uint32_t baseAddr)
+{
+ return HW_DMA_ES_RD(baseAddr);
+}
+
+/*!
+ * @brief Enables/Disables the error interrupt for channels.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) error interrupt.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
+ * will be enabled/disabled.
+ */
+void EDMA_HAL_SetErrorIntCmd(uint32_t baseAddr, bool enable, edma_channel_indicator_t channel);
+
+/*!
+ * @brief Checks whether the eDMA channel error interrupt is enabled or disabled.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Error interrupt is enabled (true) or disabled (false).
+ */
+bool EDMA_HAL_GetErrorIntCmd(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Gets the eDMA error interrupt status.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return 32 bit variable indicating error channels. If error happens on eDMA channel n, the bit n
+ * of this variable is '1'. If not, the bit n of this variable is '0'.
+ */
+static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(uint32_t baseAddr)
+{
+ return HW_DMA_ERR_RD(baseAddr);
+}
+
+/*!
+ * @brief Clears the error interrupt status for the eDMA channel or channels.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) error interrupt.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
+ * status will be cleared.
+ */
+static inline void EDMA_HAL_ClearErrorIntStatusFlag(
+ uint32_t baseAddr, edma_channel_indicator_t channel)
+{
+ HW_DMA_CERR_WR(baseAddr, channel);
+}
+
+/*!
+ * @brief Enables/Disables the DMA request for the channel or all channels.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) DMA request.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels DMA request
+ * are enabled/disabled.
+ */
+void EDMA_HAL_SetDmaRequestCmd(uint32_t baseAddr, edma_channel_indicator_t channel,bool enable);
+
+/*!
+ * @brief Checks whether the eDMA channel DMA request is enabled or disabled.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return DMA request is enabled (true) or disabled (false).
+ */
+static inline bool EDMA_HAL_GetDmaRequestCmd(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ return ((HW_DMA_ERQ_RD(baseAddr) >> channel) & 1U);
+}
+
+/*!
+ * @brief Gets the eDMA channel DMA request status.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Hardware request is triggered in this eDMA channel (true) or not be triggered in this
+ * channel (false).
+ */
+static inline bool EDMA_HAL_GetDmaRequestStatusFlag(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ return (((uint32_t)HW_DMA_HRS_RD(baseAddr) >> channel) & 1U);
+}
+
+/*!
+ * @brief Clears the done status for a channel or all channels.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' done status will
+ * be cleared.
+ */
+static inline void EDMA_HAL_ClearDoneStatusFlag(uint32_t baseAddr, edma_channel_indicator_t channel)
+{
+ HW_DMA_CDNE_WR(baseAddr, channel);
+}
+
+/*!
+ * @brief Triggers the eDMA channel.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels are tirggere.
+ */
+static inline void EDMA_HAL_TriggerChannelStart(uint32_t baseAddr, edma_channel_indicator_t channel)
+{
+ HW_DMA_SSRT_WR(baseAddr, channel);
+}
+
+/*!
+ * @brief Gets the eDMA channel interrupt request status.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Interrupt request happens in this eDMA channel (true) or not happen in this
+ * channel (false).
+ */
+static inline bool EDMA_HAL_GetIntStatusFlag(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ return (((uint32_t)HW_DMA_INT_RD(baseAddr) >> channel) & 1U);
+}
+
+/*!
+ * @brief Gets the eDMA all channel's interrupt request status.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Interrupt status flag of all channels.
+ */
+static inline uint32_t EDMA_HAL_GetAllIntStatusFlag(uint32_t baseAddr)
+{
+ return (uint32_t)HW_DMA_INT_RD(baseAddr);
+}
+
+/*!
+ * @brief Clears the interrupt status for the eDMA channel or all channels.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) error interrupt.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' interrupt
+ * status will be cleared.
+ */
+static inline void EDMA_HAL_ClearIntStatusFlag(
+ uint32_t baseAddr, edma_channel_indicator_t channel)
+{
+ HW_DMA_CINT_WR(baseAddr, channel);
+}
+
+#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
+/*!
+ * @brief Enables/Disables an asynchronous request in stop mode.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) or Disable (false) async DMA request.
+ */
+void EDMA_HAL_SetAsyncRequestInStopModeCmd(uint32_t baseAddr, uint32_t channel, bool enable);
+#endif
+
+/* @} */
+
+/*!
+ * @name eDMA HAL driver hardware TCD configuration functions.
+ * @{
+ */
+
+/*!
+ * @brief Clears all registers to 0 for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ */
+void EDMA_HAL_HTCDClearReg(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Configures the source address for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param address The pointer to the source memory address.
+ */
+static inline void EDMA_HAL_HTCDSetSrcAddr(uint32_t baseAddr, uint32_t channel, uint32_t address)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_SADDR_SADDR(baseAddr, channel, address);
+}
+
+/*!
+ * @brief Configures the source address signed offset for the hardware TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * source read is complete.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param offset signed-offset for source address.
+ */
+static inline void EDMA_HAL_HTCDSetSrcOffset(uint32_t baseAddr, uint32_t channel, int16_t offset)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_SOFF_SOFF(baseAddr, channel, offset);
+}
+
+/*!
+ * @brief Configures the transfer attribute for the eDMA channel.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param srcModulo enumeration type for an allowed source modulo. The value defines a specific address range
+ * specified as the value after the SADDR + SOFF calculation is performed on the original register
+ * value. Setting this field provides the ability to implement a circular data. For data queues
+ * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
+ * field should be set to the appropriate value for the queue, freezing the desired number of upper
+ * address bits. The value programmed into this field specifies the number of the lower address bits
+ * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
+ * size to implement post-increment addressing with SMOD function restricting the addresses to a
+ * 0-modulo-size range.
+ * @param destModulo Enum type for an allowed destination modulo.
+ * @param srcTransferSize Enum type for source transfer size.
+ * @param destTransferSize Enum type for destination transfer size.
+ */
+void EDMA_HAL_HTCDSetAttribute(
+ uint32_t baseAddr, uint32_t channel,
+ edma_modulo_t srcModulo, edma_modulo_t destModulo,
+ edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize);
+
+/*!
+ * @brief Configures the nbytes for the eDMA channel.
+ *
+ * Note here that user need firstly configure the minor loop mapping feature and then call this
+ * function.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param nbytes Number of bytes to be transferred in each service request of the channel
+ */
+void EDMA_HAL_HTCDSetNbytes(uint32_t baseAddr, uint32_t channel, uint32_t nbytes);
+
+/*!
+ * @brief Gets the nbytes configuration data for the hardware TCD.
+ *
+ * This function decides whether the minor loop mapping is enabled or whether the source/dest
+ * minor loop mapping is enabled. Then, the nbytes are returned accordingly.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return nbytes configuration according to minor loop setting.
+ */
+uint32_t EDMA_HAL_HTCDGetNbytes(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Configures the minor loop offset for the hardware TCD.
+ *
+ * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled,
+ * offset is not configured. Note here if source or destination offset is required, the eDMA module
+ * EMLM bit will be set in this function. User need to know this side effect.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param config Configuration data structure for the minor loop offset
+ */
+void EDMA_HAL_HTCDSetMinorLoopOffset(
+ uint32_t baseAddr, uint32_t channel, edma_minorloop_offset_config_t *config);
+
+/*!
+ * @brief Configures the last source address adjustment for the hardware TCD.
+ *
+ * Adjustment value added to the source address at the completion of the major iteration count. This
+ * value can be applied to restore the source address to the initial value, or adjust the address to
+ * reference the next data structure.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param size adjustment value
+ */
+static inline void EDMA_HAL_HTCDSetSrcLastAdjust(uint32_t baseAddr, uint32_t channel, int32_t size)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_SLAST_SLAST(baseAddr, channel, size);
+}
+
+/*!
+ * @brief Configures the destination address for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param address The pointer to the destination address.
+ */
+static inline void EDMA_HAL_HTCDSetDestAddr(uint32_t baseAddr, uint32_t channel, uint32_t address)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_DADDR_DADDR(baseAddr, channel, address);
+}
+
+/*!
+ * @brief Configures the destination address signed offset for the hardware TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * destination write is complete.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param offset signed-offset
+ */
+static inline void EDMA_HAL_HTCDSetDestOffset(uint32_t baseAddr, uint32_t channel, int16_t offset)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_DOFF_DOFF(baseAddr, channel, offset);
+}
+
+/*!
+ * @brief Configures the last source address adjustment.
+ *
+ * This function adds an adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the initial value, or
+ * adjust the address to reference the next data structure.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param adjust adjustment value
+ */
+static inline void EDMA_HAL_HTCDSetDestLastAdjust(
+ uint32_t baseAddr, uint32_t channel, uint32_t adjust)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_DLASTSGA_DLASTSGA(baseAddr, channel, adjust);
+}
+
+/*!
+ * @brief Configures the memory address for the next transfer TCD for the hardware TCD.
+ *
+ *
+ * This function enables the scatter/gather feature for the hardware TCD and configures the next
+ * TCD's address. This address points to the beginning of a 0-modulo-32 byte region containing
+ * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
+ * a configuration error is reported.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param stcd The pointer to the TCD to be linked to this hardware TCD.
+ */
+void EDMA_HAL_HTCDSetScatterGatherLink(
+ uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd);
+
+/*!
+ * @brief Configures the bandwidth for the hardware TCD.
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
+ * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
+ * This field forces the eDMA to stall after the completion of each read/write access to control the
+ * bus request bandwidth seen by the crossbar switch.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param bandwidth enum type for bandwidth control
+ */
+static inline void EDMA_HAL_HTCDSetBandwidth(
+ uint32_t baseAddr, uint32_t channel, edma_bandwidth_config_t bandwidth)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_BWC(baseAddr, channel, bandwidth);
+}
+
+/*!
+ * @brief Configures the major channel link the hardware TCD.
+ *
+ * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
+ * channel service request at the channel defined by these six bits by setting that channel start
+ * bits.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param majorChannel channel number for major link
+ * @param enable Enables (true) or Disables (false) channel major link.
+ */
+static inline void EDMA_HAL_HTCDSetChannelMajorLink(
+ uint32_t baseAddr, uint32_t channel, uint32_t majorChannel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_MAJORLINKCH(baseAddr, channel, majorChannel);
+ BW_DMA_TCDn_CSR_MAJORELINK(baseAddr, channel, enable);
+}
+
+/*!
+ * @brief Gets the major link channel for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return major link channel number
+ */
+static inline uint32_t EDMA_HAL_HTCDGetMajorLinkChannel(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ return BR_DMA_TCDn_CSR_MAJORLINKCH(baseAddr, channel);
+}
+
+/*!
+ * @brief Enables/Disables the scatter/gather feature for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enables (true) /Disables (false) scatter/gather feature.
+ */
+static inline void EDMA_HAL_HTCDSetScatterGatherCmd(
+ uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_ESG(baseAddr, channel, enable);
+}
+
+/*!
+ * @brief Checks whether the scatter/gather feature is enabled for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return True stand for enabled. False stands for disabled.
+ */
+static inline bool EDMA_HAL_HTCDGetScatterGatherCmd(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ return BR_DMA_TCDn_CSR_ESG(baseAddr, channel);
+
+}
+
+/*!
+ * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD.
+ *
+ * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
+ * current major iteration count reaches zero.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param disable Disable (true)/Enable (true) DMA request after TCD complete.
+ */
+static inline void EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(
+ uint32_t baseAddr, uint32_t channel, bool disable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_DREQ(baseAddr, channel, disable);
+}
+
+/*!
+ * @brief Enables/Disables the half complete interrupt for the hardware TCD.
+ *
+ * If set, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches the halfway point. Specifically,
+ * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
+ * interrupt request is provided to support the double-buffered schemes or other types of data movement
+ * where the processor needs an early indication of the transfer's process.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) /Disable (false) half complete interrupt.
+ */
+static inline void EDMA_HAL_HTCDSetHalfCompleteIntCmd(
+ uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_INTHALF(baseAddr, channel, enable);
+}
+
+/*!
+ * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD.
+ *
+ * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches zero.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) /Disable (false) interrupt after TCD done.
+ */
+static inline void EDMA_HAL_HTCDSetIntCmd(
+ uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_INTMAJOR(baseAddr, channel, enable);
+}
+
+/*!
+ * @brief Triggers the start bits for the hardware TCD.
+ *
+ * The eDMA hardware automatically clears this flag after the channel begins execution.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_HAL_HTCDTriggerChannelStart(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ BW_DMA_TCDn_CSR_START(baseAddr, channel, true);
+}
+
+/*!
+ * @brief Checks whether the channel is running for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return True stands for running. False stands for not.
+ */
+static inline bool EDMA_HAL_HTCDGetChannelActiveStatus(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ return BR_DMA_TCDn_CSR_ACTIVE(baseAddr, channel);
+}
+
+/*!
+ * @brief Sets the channel minor link for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param linkChannel Channel to be linked on minor loop complete.
+ * @param enable Enable (true)/Disable (false) channel minor link.
+ */
+void EDMA_HAL_HTCDSetChannelMinorLink(
+ uint32_t baseAddr, uint32_t channel, uint32_t linkChannel, bool enable);
+
+/*!
+ * @brief Sets the major iteration count according to minor loop channel link setting.
+ *
+ * Note here that user need to first set the minor loop channel link and then call this function.
+ * The execute flow inside this function is dependent on the minor loop channel link setting.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param count major loop count
+ */
+void EDMA_HAL_HTCDSetMajorCount(uint32_t baseAddr, uint32_t channel, uint32_t count);
+
+/*!
+ * @brief Gets the number of beginning major counts for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Begin major counts.
+ */
+uint32_t EDMA_HAL_HTCDGetBeginMajorCount(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Gets the number of current major counts for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Current major counts.
+ */
+uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Gets the number of bytes already transferred for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return data bytes already transferred
+ */
+uint32_t EDMA_HAL_HTCDGetFinishedBytes(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Gets the number of bytes haven't transferred for the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return data bytes already transferred
+ */
+uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(uint32_t baseAddr, uint32_t channel);
+
+/*!
+ * @brief Gets the channel done status.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return If channel done.
+ */
+static inline bool EDMA_HAL_HTCDGetDoneStatusFlag(uint32_t baseAddr, uint32_t channel)
+{
+ return BR_DMA_TCDn_CSR_DONE(baseAddr,channel);
+}
+
+/* @} */
+
+/*!
+ * @name EDMA HAL driver software TCD configuration functions.
+ * @{
+ */
+/*!
+ * @brief Configures the source address for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param channel eDMA channel number.
+ * @param address The pointer to the source memory address.
+ */
+static inline void EDMA_HAL_STCDSetSrcAddr(edma_software_tcd_t *stcd, uint32_t address)
+{
+ assert(stcd);
+ stcd->SADDR = DMA_SADDR_SADDR(address);
+}
+
+/*!
+ * @brief Configures the source address signed offset for the software TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * source read is complete.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param offset signed-offset for source address.
+ */
+static inline void EDMA_HAL_STCDSetSrcOffset(edma_software_tcd_t *stcd, int16_t offset)
+{
+ assert(stcd);
+ stcd->SOFF = DMA_SOFF_SOFF(offset);
+}
+
+/*!
+ * @brief Configures the transfer attribute for software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param srcModulo enum type for an allowed source modulo. The value defines a specific address range
+ * specified as the value after the SADDR + SOFF calculation is performed on the original register
+ * value. Setting this field provides the ability to implement a circular data. For data queues
+ * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
+ * field should be set to the appropriate value for the queue, freezing the desired number of upper
+ * address bits. The value programmed into this field specifies the number of the lower address bits
+ * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
+ * size to implement post-increment addressing with SMOD function restricting the addresses to a
+ * 0-modulo-size range.
+ * @param destModulo Enum type for an allowed destination modulo.
+ * @param srcTransferSize Enum type for source transfer size.
+ * @param destTransferSize Enum type for destinatio transfer size.
+ */
+void EDMA_HAL_STCDSetAttribute(
+ edma_software_tcd_t *stcd,
+ edma_modulo_t srcModulo, edma_modulo_t destModulo,
+ edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize);
+
+/*!
+ * @brief Configures the nbytes for software TCD.
+ *
+ * Note here that user need firstly configure the minor loop mapping feature and then call this
+ * function.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param nbytes Number of bytes to be transferred in each service request of the channel
+ */
+void EDMA_HAL_STCDSetNbytes(uint32_t baseAddr, edma_software_tcd_t *stcd, uint32_t nbytes);
+
+/*!
+ * @brief Configures the minorloop offset for the software TCD.
+ *
+ * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled,
+ * offset is not configured. Note here if source or destination offset is requred, the eDMA module
+ * EMLM bit will be set in this function. User need to know this side effect.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param config Configuration data structure for the minorloop offset
+ */
+void EDMA_HAL_STCDSetMinorLoopOffset(
+ uint32_t baseAddr, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config);
+
+/*!
+ * @brief Configures the last source address adjustment for the software TCD.
+ *
+ * Adjustment value added to the source address at the completion of the major iteration count. This
+ * value can be applied to restore the source address to the initial value, or adjust the address to
+ * reference the next data structure.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param size adjustment value
+ */
+static inline void EDMA_HAL_STCDSetSrcLastAdjust(edma_software_tcd_t *stcd, int32_t size)
+{
+ assert(stcd);
+ stcd->SLAST = (stcd->SLAST & ~DMA_SLAST_SLAST_MASK) | DMA_SLAST_SLAST(size);
+}
+
+/*!
+ * @brief Configures the destination address for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param address The pointer to the destination addresss.
+ */
+static inline void EDMA_HAL_STCDSetDestAddr(edma_software_tcd_t *stcd, uint32_t address)
+{
+ assert(stcd);
+ stcd->DADDR = DMA_DADDR_DADDR(address);
+}
+
+/*!
+ * @brief Configures the destination address signed offset for the software TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * destination write is complete.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param offset signed-offset
+ */
+static inline void EDMA_HAL_STCDSetDestOffset(edma_software_tcd_t *stcd, int16_t offset)
+{
+ assert(stcd);
+ stcd->DOFF = DMA_DOFF_DOFF(offset);
+}
+
+/*!
+ * @brief Configures the last source address adjustment.
+ *
+ * This function add an adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the initial value, or
+ * adjust the address to reference the next data structure.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param adjust adjustment value
+ */
+static inline void EDMA_HAL_STCDSetDestLastAdjust(
+ edma_software_tcd_t *stcd, uint32_t adjust)
+{
+ assert(stcd);
+ stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(adjust);
+}
+
+/*!
+ * @brief Configures the memory address for the next transfer TCD for the software TCD.
+ *
+ *
+ * This function enable the scatter/gather feature for the software TCD and configure the next
+ * TCD's address.This address points to the beginning of a 0-modulo-32 byte region containing
+ * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
+ * a configuration error is reported.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param nextStcd The pointer to the TCD to be linked to this software TCD.
+ */
+void EDMA_HAL_STCDSetScatterGatherLink(
+ edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd);
+
+/*!
+ * @brief Configures the bandwidth for the software TCD.
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
+ * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
+ * This field forces the eDMA to stall after the completion of each read/write access to control the
+ * bus request bandwidth seen by the crossbar switch.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param bandwidth enum type for bandwidth control
+ */
+static inline void EDMA_HAL_STCDSetBandwidth(
+ edma_software_tcd_t *stcd, edma_bandwidth_config_t bandwidth)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_BWC_MASK) | DMA_CSR_BWC(bandwidth);
+}
+
+/*!
+ * @brief Configures the major channel link the software TCD.
+ *
+ * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
+ * channel service request at the channel defined by these six bits by setting that channel start
+ * bits.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param majorChannel channel number for major link
+ * @param enable Enables (true) or Disables (false) channel major link.
+ */
+static inline void EDMA_HAL_STCDSetChannelMajorLink(
+ edma_software_tcd_t *stcd, uint32_t majorChannel, bool enable)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORLINKCH_MASK) | DMA_CSR_MAJORLINKCH(majorChannel);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORELINK_MASK) |
+ ((uint32_t)enable << DMA_CSR_MAJORELINK_SHIFT);
+}
+
+
+/*!
+ * @brief Enables/Disables the scatter/gather feature for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enables (true) /Disables (false) scatter/gather feature.
+ */
+static inline void EDMA_HAL_STCDSetScatterGatherCmd(
+ edma_software_tcd_t *stcd, bool enable)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_ESG_MASK) | ((uint32_t)enable << DMA_CSR_ESG_SHIFT);
+}
+
+
+/*!
+ * @brief Disables/Enables the DMA request after the major loop completes for the software TCD.
+ *
+ * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
+ * current major iteration count reaches zero.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param disable Disable (true)/Enable (true) dma request after TCD complete.
+ */
+static inline void EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(
+ edma_software_tcd_t *stcd, bool disable)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_DREQ_MASK) | ((uint32_t)disable << DMA_CSR_DREQ_SHIFT);
+}
+
+/*!
+ * @brief Enables/Disables the half complete interrupt for the software TCD.
+ *
+ * If set, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches the halfway point. Specifically,
+ * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
+ * interrupt request is provided to support the double-buffered schemes or other types of data movement
+ * where the processor needs an early indication of the transfer's process.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enable (true) /Disable (false) half complete interrupt.
+ */
+static inline void EDMA_HAL_STCDSetHalfCompleteIntCmd(
+ edma_software_tcd_t *stcd, bool enable)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_INTHALF_MASK) | ((uint32_t)enable << DMA_CSR_INTHALF_SHIFT);
+}
+
+/*!
+ * @brief Enables/Disables the interrupt after the major loop completes for the software TCD.
+ *
+ * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches zero.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enable (true) /Disable (false) interrupt after TCD done.
+ */
+static inline void EDMA_HAL_STCDSetIntCmd(edma_software_tcd_t *stcd, bool enable)
+{
+ assert(stcd);
+ stcd->CSR = (stcd->CSR & ~DMA_CSR_INTMAJOR_MASK) | ((uint32_t)enable << DMA_CSR_INTMAJOR_SHIFT);
+}
+
+/*!
+ * @brief Triggers the start bits for the software TCD.
+ *
+ * The eDMA hardware automatically clears this flag after the channel begins execution.
+ *
+ * @param stcd The pointer to the software TCD.
+ */
+static inline void EDMA_HAL_STCDTriggerChannelStart(edma_software_tcd_t *stcd)
+{
+ assert(stcd);
+ stcd->CSR |= DMA_CSR_START_MASK;
+}
+
+/*!
+ * @brief Set Channel minor link for software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param linkChannel Channel to be linked on minor loop complete.
+ * @param enable Enable (true)/Disable (false) channel minor link.
+ */
+void EDMA_HAL_STCDSetChannelMinorLink(
+ edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable);
+
+/*!
+ * @brief Sets the major iteration count according to minor loop channel link setting.
+ *
+ * Note here that user need to first set the minor loop channel link and then call this function.
+ * The execute flow inside this function is dependent on the minor loop channel link setting.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param count major loop count
+ */
+void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count);
+
+/*!
+ * @brief Copy the software TCD configuration to the hardware TCD.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param stcd The pointer to the software TCD.
+ */
+void EDMA_HAL_PushSTCDToHTCD(uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd);
+
+/*!
+ * @brief Set the basic transfer for software TCD.
+ *
+ * This function is used to setup the basic transfer for software TCD. The minor loop setting is not
+ * involved here cause minor loop's configuration will lay a impact on the global eDMA setting. And
+ * the source minor loop offset is relevant to the dest minor loop offset. For these reasons, minor
+ * loop offset configuration is treated as an advanced configuration. User can call the
+ * EDMA_HAL_STCDSetMinorLoopOffset() to configure the minor loop offset feature.
+ *
+ * @param baseAddr Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param config The pointer to the transfer configuration structure.
+ * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete.
+ * @param disableDmaRequest Disables (true) or Enable (false) dma request on TCD complete.
+ */
+edma_status_t EDMA_HAL_STCDSetBasicTransfer(
+ uint32_t baseAddr, edma_software_tcd_t *stcd, edma_transfer_config_t *config,
+ bool enableInt, bool disableDmaRequest);
+
+
+/* @} */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __EDMA_HAL_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/enet/fsl_enet_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_ENET_FEATURES_H__) +#define __FSL_ENET_FEATURES_H__ + + +#if defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) + #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1) + #define FSL_FEATURE_ENET_SUPPORT_PTP (0) + #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) + #define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT (0) +#elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) + #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0) + #define FSL_FEATURE_ENET_SUPPORT_PTP (0) + #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) + #define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT (0) +#elif defined(CPU_MK70FN1M0VMJ12) + #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1) + #define FSL_FEATURE_ENET_SUPPORT_PTP (0) + #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) +#else + #define MBED_NO_ENET +#endif + + +#endif /* __FSL_ENET_FEATURES_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_enet_hal.h"
+
+#ifndef MBED_NO_ENET
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_set_mac_address
+ * Description: Set ENET mac physical address.
+ *
+ *END*********************************************************************/
+void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ uint32_t address, data;
+
+ address = (uint32_t)(((uint32_t)hwAddr[0] << 24U)|((uint32_t)hwAddr[1] << 16U)|((uint32_t)hwAddr[2] << 8U)| (uint32_t)hwAddr[3]) ;
+ HW_ENET_PALR_WR(instance,address); /* Set low physical address */
+ address = (uint32_t)(((uint32_t)hwAddr[4] << 24U)|((uint32_t)hwAddr[5] << 16U)) ;
+ data = HW_ENET_PAUR_RD(instance) & BM_ENET_PAUR_TYPE;
+ HW_ENET_PAUR_WR(instance, (data | address)); /* Set high physical address */
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_set_group_hashtable
+ * Description: Set multicast group address hash value to the mac register
+ * To join the multicast group address.
+ *END*********************************************************************/
+void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ switch (mode)
+ {
+ case kEnetSpecialAddressInit: /* Clear group address register on ENET initialize */
+ HW_ENET_GALR_WR(instance,0);
+ HW_ENET_GAUR_WR(instance,0);
+ break;
+ case kEnetSpecialAddressEnable: /* Enable a multicast group address*/
+ if (!((crcValue >> 31) & 1U))
+ {
+ HW_ENET_GALR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
+ }
+ else
+ {
+ HW_ENET_GAUR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
+ }
+ break;
+ case kEnetSpecialAddressDisable: /* Disable a multicast group address*/
+ if (!((crcValue >> 31) & 1U))
+ {
+ HW_ENET_GALR_CLR(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
+ }
+ else
+ {
+ HW_ENET_GAUR_CLR(instance,(1U << ((crcValue>>26) & kEnetHashValMask)));
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_set_individual_hashtable
+ * Description: Set a specific unicast address hash value to the mac register
+ * To receive frames with the individual destination address.
+ *END*********************************************************************/
+void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ switch (mode)
+ {
+ case kEnetSpecialAddressInit: /* Clear individual address register on ENET initialize */
+ HW_ENET_IALR_WR(instance,0);
+ HW_ENET_IAUR_WR(instance,0);
+ break;
+ case kEnetSpecialAddressEnable: /* Enable a special address*/
+ if (((crcValue >>31) & 1U) == 0)
+ {
+ HW_ENET_IALR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
+ }
+ else
+ {
+ HW_ENET_IAUR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
+ }
+ break;
+ case kEnetSpecialAddressDisable: /* Disable a special address*/
+ if (((crcValue >>31) & 1U) == 0)
+ {
+ HW_ENET_IALR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
+ }
+ else
+ {
+ HW_ENET_IAUR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_tx_fifo
+ * Description: Configure ENET transmit FIFO.
+ *END*********************************************************************/
+void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(thresholdCfg);
+
+ BW_ENET_TFWR_STRFWD(instance, thresholdCfg->isStoreForwardEnabled); /* Set store and forward mode*/
+ if(!thresholdCfg->isStoreForwardEnabled)
+ {
+ assert(thresholdCfg->txFifoWrite <= BM_ENET_TFWR_TFWR);
+ BW_ENET_TFWR_TFWR(instance, thresholdCfg->txFifoWrite); /* Set transmit FIFO write bytes*/
+ }
+ BW_ENET_TSEM_TX_SECTION_EMPTY(instance,thresholdCfg->txEmpty); /* Set transmit FIFO empty threshold*/
+ BW_ENET_TAEM_TX_ALMOST_EMPTY(instance,thresholdCfg->txAlmostEmpty); /* Set transmit FIFO almost empty threshold*/
+ BW_ENET_TAFL_TX_ALMOST_FULL(instance,thresholdCfg->txAlmostFull); /* Set transmit FIFO almost full threshold*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_rx_fifo
+ * Description: Configure ENET receive FIFO.
+ *END*********************************************************************/
+void enet_hal_config_rx_fifo(uint32_t instance,enet_config_rx_fifo_t *thresholdCfg )
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(thresholdCfg);
+ if(thresholdCfg->rxFull > 0)
+ {
+ assert(thresholdCfg->rxFull > thresholdCfg->rxAlmostEmpty);
+ }
+
+ BW_ENET_RSFL_RX_SECTION_FULL(instance,thresholdCfg->rxFull); /* Set receive FIFO full threshold*/
+ BW_ENET_RSEM_RX_SECTION_EMPTY(instance,thresholdCfg->rxEmpty); /* Set receive FIFO empty threshold*/
+ BW_ENET_RAEM_RX_ALMOST_EMPTY(instance,thresholdCfg->rxAlmostEmpty); /* Set receive FIFO almost empty threshold*/
+ BW_ENET_RAFL_RX_ALMOST_FULL(instance,thresholdCfg->rxAlmostFull); /* Set receive FIFO almost full threshold*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_init_rxbds
+ * Description: Initialize ENET receive buffer descriptors.
+ *END*********************************************************************/
+void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd)
+{
+ assert(rxBds);
+ assert(buffer);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds;
+
+ bdPtr->buffer = (uint8_t *)NTOHL((uint32_t)buffer); /* Set data buffer address */
+ bdPtr->length = 0; /* Initialize data length*/
+
+ /*The last buffer descriptor should be set with the wrap flag*/
+ if (isLastBd)
+ {
+ bdPtr->control |= kEnetRxBdWrap;
+ }
+ bdPtr->control |= kEnetRxBdEmpty; /* Initialize bd with empty bit*/
+ bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable receive interrupt*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_init_txbds
+ * Description: Initialize ENET transmit buffer descriptors.
+ *END*********************************************************************/
+void enet_hal_init_txbds(void *txBds, bool isLastBd)
+{
+ assert(txBds);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)txBds;
+
+ bdPtr->length = 0; /* Initialize data length*/
+
+ /*The last buffer descriptor should be set with the wrap flag*/
+ if (isLastBd)
+ {
+ bdPtr->control |= kEnetTxBdWrap;
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_update_rxbds
+ * Description: Update ENET receive buffer descriptors.
+ *END*********************************************************************/
+void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate)
+{
+ assert(rxBds);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds;
+
+ if (isbufferUpdate)
+ {
+ bdPtr->buffer = (uint8_t *)HTONL((uint32_t)data);
+ }
+ bdPtr->control &= kEnetRxBdWrap; /* Clear status*/
+ bdPtr->control |= kEnetRxBdEmpty; /* Set rx bd empty*/
+ bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable interrupt*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_update_txbds
+ * Description: Update ENET transmit buffer descriptors.
+ *END*********************************************************************/
+void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged)
+{
+ assert(txBds);
+ assert(buffer);
+
+ volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t *)txBds;
+
+ bdPtr->length = HTONS(length); /* Set data length*/
+ bdPtr->buffer = (uint8_t *)HTONL((uint32_t)buffer); /* Set data buffer*/
+ bdPtr->control |= kEnetTxBdLast | kEnetTxBdTransmitCrc | kEnetTxBdReady;/* set control */
+ if (isTxtsCfged)
+ {
+ /* Set receive and timestamp interrupt*/
+ bdPtr->controlExtend1 |= (kEnetTxBdTxInterrupt | kEnetTxBdTimeStamp);
+ }
+ else
+ {
+ /* Set receive interrupt*/
+ bdPtr->controlExtend1 |= kEnetTxBdTxInterrupt;
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_rxbd_control
+ * Description: Get receive buffer descriptor control and status region.
+ *END*********************************************************************/
+uint16_t enet_hal_get_rxbd_control(void *curBd)
+{
+ assert(curBd);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ return bdPtr->control;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_txbd_control
+ * Description: Get ENET transmit buffer descriptor control and status data.
+ *END*********************************************************************/
+uint16_t enet_hal_get_txbd_control(void *curBd)
+{
+ assert(curBd);
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ return bdPtr->control;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_bd_length
+ * Description: Get ENET data length of buffer descriptors.
+ *END*********************************************************************/
+uint16_t enet_hal_get_bd_length(void *curBd)
+{
+ assert(curBd);
+ uint16_t length;
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ length = bdPtr->length;
+ return NTOHS(length);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_bd_buffer
+ * Description: Get the buffer address of buffer descriptors.
+ *END*********************************************************************/
+uint8_t* enet_hal_get_bd_buffer(void *curBd)
+{
+ assert(curBd);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ uint32_t buffer = (uint32_t)(bdPtr->buffer);
+ return (uint8_t *)NTOHL(buffer);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_bd_timestamp
+ * Description: Get the timestamp of buffer descriptors.
+ *END*********************************************************************/
+uint32_t enet_hal_get_bd_timestamp(void *curBd)
+{
+ assert(curBd);
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ uint32_t timestamp = bdPtr->timestamp;
+ return NTOHL(timestamp);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_rxbd_control_extend
+ * Description: Get ENET receive buffer descriptor extended control region.
+ *END*********************************************************************/
+bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion)
+{
+ assert(curBd);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+
+#if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
+ if (((uint16_t)controlRegion > kEnetRxBdCtlJudge1) && ((uint16_t)controlRegion < kEnetRxBdCtlJudge2))
+ {
+ return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/
+ }
+ else
+ {
+ return ((bdPtr->controlExtend1 & controlRegion) != 0); /* Control extended1 region*/
+ }
+#else
+ if( (uint16_t)controlRegion < kEnetRxBdCtlJudge1)
+ {
+ return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/
+ }
+ else
+ {
+ return ((bdPtr->controlExtend1 & controlRegion) != 0);/* Control extended1 region*/
+ }
+#endif
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_txbd_control_extend
+ * Description: Get ENET transmit buffer descriptor extended control region.
+ *END*********************************************************************/
+uint16_t enet_hal_get_txbd_control_extend(void *curBd)
+{
+ assert(curBd);
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+
+ return bdPtr->controlExtend0;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_get_txbd_timestamp_flag
+ * Description: Get ENET transmit buffer descriptor timestamp region.
+ *END*********************************************************************/
+bool enet_hal_get_txbd_timestamp_flag(void *curBd)
+{
+ assert(curBd);
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ return ((bdPtr->controlExtend1 & kEnetTxBdTimeStamp) != 0);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_rmii
+ * Description: Configure (R)MII mode.
+ *END*********************************************************************/
+void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_RCR_MII_MODE(instance,1); /* Set mii mode */
+ BW_ENET_RCR_RMII_MODE(instance,mode);
+ BW_ENET_RCR_RMII_10T(instance,speed); /* Set speed mode */
+ BW_ENET_TCR_FDEN(instance,duplex); /* Set duplex mode*/
+ if ((!duplex) && isRxOnTxDisabled)
+ {
+ BW_ENET_RCR_DRT(instance,1); /* Disable receive on transmit*/
+ }
+
+ if (mode == kEnetCfgMii) /* Set internal loop only for mii mode*/
+ {
+ BW_ENET_RCR_LOOP(instance,isLoopEnabled);
+ }
+ else
+ {
+ BW_ENET_RCR_LOOP(instance, 0); /* Clear internal loop for rmii mode*/
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_set_mii_command
+ * Description: Set MII command.
+ *END*********************************************************************/
+void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ uint32_t mmfrValue = 0 ;
+
+ mmfrValue = BF_ENET_MMFR_ST(1)| BF_ENET_MMFR_OP(operation)| BF_ENET_MMFR_PA(phyAddr) | BF_ENET_MMFR_RA(phyReg)| BF_ENET_MMFR_TA(2) | (data&0xFFFF); /* mii command*/
+ HW_ENET_MMFR_WR(instance,mmfrValue);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_ethernet
+ * Description: Enable or disable normal Ethernet mode and enhanced mode.
+ *END*********************************************************************/
+void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_ECR_ETHEREN(instance,isEnabled); /* Enable/Disable Ethernet module*/
+ if (isEnhanced)
+ {
+ BW_ENET_ECR_EN1588(instance,isEnabled); /* Enable/Disable enhanced frame feature*/
+ }
+#if SYSTEM_LITTLE_ENDIAN && !FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
+ BW_ENET_ECR_DBSWP(instance,1); /* buffer descriptor byte swapping for little-endian system and endianness configurable IP*/
+#endif
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_interrupt
+ * Description: Enable or disable different Ethernet interrupts.
+ * the parameter source is the interrupt source and enet_interrupt_request_t
+ * enum types is recommended to be used as the interrupt sources.
+ *END*********************************************************************/
+void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ if (isEnabled)
+ {
+ HW_ENET_EIMR_SET(instance,source); /* Enable interrupt */
+ }
+ else
+ {
+ HW_ENET_EIMR_CLR(instance,source); /* Disable interrupt*/
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_tx_accelerator
+ * Description: Configure Ethernet transmit accelerator features.
+ *END*********************************************************************/
+void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(txCfgPtr);
+
+ HW_ENET_TACC_WR(instance,0); /* Clear all*/
+ BW_ENET_TACC_IPCHK(instance,txCfgPtr->isIpCheckEnabled); /* Insert ipheader checksum */
+ BW_ENET_TACC_PROCHK(instance,txCfgPtr->isProtocolCheckEnabled); /* Insert protocol checksum*/
+ BW_ENET_TACC_SHIFT16(instance,txCfgPtr->isShift16Enabled); /* Set tx fifo shift-16*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_config_rx_accelerator
+ * Description: Configure Ethernet receive accelerator features.
+ *END*********************************************************************/
+void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(rxCfgPtr);
+
+ HW_ENET_RACC_WR(instance,0); /* Clear all*/
+ BW_ENET_RACC_IPDIS(instance,rxCfgPtr->isIpcheckEnabled); /* Set ipchecksum field*/
+ BW_ENET_RACC_PRODIS(instance,rxCfgPtr->isProtocolCheckEnabled); /* Set protocol field*/
+ BW_ENET_RACC_LINEDIS(instance,rxCfgPtr->isMacCheckEnabled); /* Set maccheck field*/
+ BW_ENET_RACC_SHIFT16(instance,rxCfgPtr->isShift16Enabled); /* Set rx fifo shift field*/
+ BW_ENET_RACC_PADREM(instance,rxCfgPtr->isPadRemoveEnabled); /* Set rx padding remove field*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_set_txpause
+ * Return Value: The execution status.
+ * Description: Set the ENET transmit controller with pause duration and
+ * Set enet transmit PAUSE frame transmission.
+ * This should be called when a PAUSE frame is dynamically wanted.
+ *END*********************************************************************/
+void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
+ BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
+ BW_ENET_TCR_TFC_PAUSE(instance, 1);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_hal_init_ptp_timer
+ * Description: Initialize Ethernet ptp timer.
+ *END*********************************************************************/
+void enet_hal_init_ptp_timer(uint32_t instance,enet_config_ptp_timer_t *ptpCfgPtr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(ptpCfgPtr);
+
+ BW_ENET_ATINC_INC(instance, ptpCfgPtr->clockIncease); /* Set increase value for ptp timer*/
+ HW_ENET_ATPER_WR(instance, ptpCfgPtr->period); /* Set wrap time for ptp timer*/
+ /* set periodical event and the event signal output assertion*/
+ BW_ENET_ATCR_PEREN(instance, 1);
+ BW_ENET_ATCR_PINPER(instance, 1);
+ /* Set ptp timer slave/master mode*/
+ BW_ENET_ATCR_SLAVE(instance, ptpCfgPtr->isSlaveEnabled);
+}
+
+#endif /* MBED_NO_ENET */
+
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1420 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ENET_HAL_H__
+#define __FSL_ENET_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_enet_features.h"
+#include <assert.h>
+
+#ifndef MBED_NO_ENET
+
+/*!
+ * @addtogroup enet_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines the system endian type.*/
+#define SYSTEM_LITTLE_ENDIAN (1)
+
+/*! @brief Define macro to do the endianness swap*/
+#define BSWAP_16(x) (uint16_t)((uint16_t)(((uint16_t)(x) & (uint16_t)0xFF00) >> 0x8) | (uint16_t)(((uint16_t)(x) & (uint16_t)0xFF) << 0x8))
+#define BSWAP_32(x) (uint32_t)((((uint32_t)(x) & 0x00FFU) << 24) | (((uint32_t)(x) & 0x00FF00U) << 8) | (((uint32_t)(x) & 0xFF0000U) >> 8) | (((uint32_t)(x) & 0xFF000000U) >> 24))
+#if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
+#define HTONS(n) BSWAP_16(n)
+#define HTONL(n) BSWAP_32(n)
+#define NTOHS(n) BSWAP_16(n)
+#define NTOHL(n) BSWAP_32(n)
+#else
+#define HTONS(n) (n)
+#define HTONL(n) (n)
+#define NTOHS(n) (n)
+#define NTOHL(n) (n)
+#endif
+
+/*! @brief Defines the Status return codes.*/
+typedef enum _enet_status
+{
+ kStatus_ENET_Success = 0,
+ kStatus_ENET_InvalidInput, /*!< Invalid ENET input parameter */
+ kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/
+ kStatus_ENET_GetClockFreqFail, /*!< Get clock frequency failure*/
+ kStatus_ENET_Initialized, /*!< ENET device already initialized*/
+ kStatus_ENET_Layer2QueueNull, /*!< NULL L2 PTP buffer queue pointer*/
+ kStatus_ENET_Layer2OverLarge, /*!< Layer2 packet length over large*/
+ kStatus_ENET_Layer2BufferFull, /*!< Layer2 packet buffer full*/
+ kStatus_ENET_PtpringBufferFull, /*!< PTP ring buffer full*/
+ kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/
+ kStatus_ENET_Miiuninitialized, /*!< MII uninitialized*/
+ kStatus_ENET_RxbdInvalid, /*!< Receive buffer descriptor invalid*/
+ kStatus_ENET_RxbdEmpty, /*!< Receive buffer descriptor empty*/
+ kStatus_ENET_RxbdTrunc, /*!< Receive buffer descriptor truncate*/
+ kStatus_ENET_RxbdError, /*!< Receive buffer descriptor error*/
+ kStatus_ENET_RxBdFull, /*!< Receive buffer descriptor full*/
+ kStatus_ENET_SmallBdSize, /*!< Small receive buffer size*/
+ kStatus_ENET_LargeBufferFull, /*!< Receive large buffer full*/
+ kStatus_ENET_TxbdFull, /*!< Transmit buffer descriptor full*/
+ kStatus_ENET_TxbdNull, /*!< Transmit buffer descriptor Null*/
+ kStatus_ENET_TxBufferNull, /*!< Transmit data buffer Null*/
+ kStatus_ENET_NoRxBufferLeft, /*!< No more receive buffer left*/
+ kStatus_ENET_UnknownCommand, /*!< Invalid ENET PTP IOCTL command*/
+ kStatus_ENET_TimeOut, /*!< ENET Timeout*/
+ kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/
+ kStatus_ENET_AlreadyAddedMulticast /*!< Have Already added to multicast group*/
+} enet_status_t;
+
+
+#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY && SYSTEM_LITTLE_ENDIAN
+/*! @brief Defines the control and status regions of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_status
+{
+ kEnetRxBdBroadCast = 0x8000, /*!< Broadcast */
+ kEnetRxBdMultiCast = 0x4000, /*!< Multicast*/
+ kEnetRxBdLengthViolation = 0x2000, /*!< Receive length violation*/
+ kEnetRxBdNoOctet = 0x1000, /*!< Receive non-octet aligned frame*/
+ kEnetRxBdCrc = 0x0400, /*!< Receive CRC error*/
+ kEnetRxBdOverRun = 0x0200, /*!< Receive FIFO overrun*/
+ kEnetRxBdTrunc = 0x0100, /*!< Frame is truncated */
+ kEnetRxBdEmpty = 0x0080, /*!< Empty bit*/
+ kEnetRxBdRxSoftOwner1 = 0x0040, /*!< Receive software owner*/
+ kEnetRxBdWrap = 0x0020, /*!< Update buffer descriptor*/
+ kEnetRxBdRxSoftOwner2 = 0x0010, /*!< Receive software owner*/
+ kEnetRxBdLast = 0x0008, /*!< Last BD in the frame*/
+ kEnetRxBdMiss = 0x0001 /*!< Receive for promiscuous mode*/
+} enet_rx_bd_control_status_t;
+
+/*! @brief Defines the control extended regions of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend
+{
+ kEnetRxBdUnicast = 0x0001, /*!< Unicast frame*/
+ kEnetRxBdCollision = 0x0002, /*!< BD collision*/
+ kEnetRxBdPhyErr = 0x0004, /*!< PHY error*/
+ kEnetRxBdMacErr = 0x0080, /*!< Mac error*/
+ kEnetRxBdIpv4 = 0x0100, /*!< Ipv4 frame*/
+ kEnetRxBdIpv6 = 0x0200, /*!< Ipv6 frame*/
+ kEnetRxBdVlan = 0x0400, /*!< VLAN*/
+ kEnetRxBdProtocolChecksumErr = 0x1000, /*!< Protocol checksum error*/
+ kEnetRxBdIpHeaderChecksumErr = 0x2000, /*!< IP header checksum error*/
+ kEnetRxBdIntrrupt = 0x8000 /*!< BD interrupt*/
+} enet_rx_bd_control_extend_t;
+
+/*! @brief Defines the control status region of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_status
+{
+ kEnetTxBdReady = 0x0080, /*!< Ready bit*/
+ kEnetTxBdTxSoftOwner1 = 0x0040, /*!< Transmit software owner*/
+ kEnetTxBdWrap = 0x0020, /*!< Wrap buffer descriptor*/
+ kEnetTxBdTxSoftOwner2 = 0x0010, /*!< Transmit software owner*/
+ kEnetTxBdLast = 0x0008, /*!< Last BD in the frame*/
+ kEnetTxBdTransmitCrc = 0x0004 /*!< Receive for transmit CRC*/
+} enet_tx_bd_control_status_t;
+
+/*! @brief Defines the control extended region of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend
+{
+ kEnetTxBdTxErr = 0x0080, /*!< Transmit error*/
+ kEnetTxBdTxUnderFlowErr = 0x0020, /*!< Underflow error*/
+ kEnetTxBdExcessCollisionErr = 0x0010, /*!< Excess collision error*/
+ kEnetTxBdTxFrameErr = 0x0008, /*!< Frame error*/
+ kEnetTxBdLatecollisionErr = 0x0004, /*!< Late collision error*/
+ kEnetTxBdOverFlowErr = 0x0002, /*!< Overflow error*/
+ kEnetTxTimestampErr = 0x0001 /*!< Timestamp error*/
+} enet_tx_bd_control_extend_t;
+
+/*! @brief Defines the control extended2 region of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend2
+{
+ kEnetTxBdTxInterrupt = 0x0040, /*!< Transmit interrupt*/
+ kEnetTxBdTimeStamp = 0x0020 /*!< Transmit timestamp flag */
+} enet_tx_bd_control_extend2_t;
+#else
+/*! @brief Defines the control and status region of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_status
+{
+ kEnetRxBdEmpty = 0x8000, /*!< Empty bit*/
+ kEnetRxBdRxSoftOwner1 = 0x4000, /*!< Receive software owner*/
+ kEnetRxBdWrap = 0x2000, /*!< Update buffer descriptor*/
+ kEnetRxBdRxSoftOwner2 = 0x1000, /*!< Receive software owner*/
+ kEnetRxBdLast = 0x0800, /*!< Last BD in the frame*/
+ kEnetRxBdMiss = 0x0100, /*!< Receive for promiscuous mode*/
+ kEnetRxBdBroadCast = 0x0080, /*!< Broadcast */
+ kEnetRxBdMultiCast = 0x0040, /*!< Multicast*/
+ kEnetRxBdLengthViolation = 0x0020, /*!< Receive length violation*/
+ kEnetRxBdNoOctet = 0x0010, /*!< Receive non-octet aligned frame*/
+ kEnetRxBdCrc = 0x0004, /*!< Receive CRC error*/
+ kEnetRxBdOverRun = 0x0002, /*!< Receive FIFO overrun*/
+ kEnetRxBdTrunc = 0x0001 /*!< Frame is truncated */
+} enet_rx_bd_control_status_t;
+
+/*! @brief Defines the control extended region of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend
+{
+ kEnetRxBdIpv4 = 0x0001, /*!< Ipv4 frame*/
+ kEnetRxBdIpv6 = 0x0002, /*!< Ipv6 frame*/
+ kEnetRxBdVlan = 0x0004, /*!< VLAN*/
+ kEnetRxBdProtocolChecksumErr = 0x0010, /*!< Protocol checksum error*/
+ kEnetRxBdIpHeaderChecksumErr = 0x0020, /*!< IP header checksum error*/
+ kEnetRxBdIntrrupt = 0x0080, /*!< BD interrupt*/
+ kEnetRxBdUnicast = 0x0100, /*!< Unicast frame*/
+ kEnetRxBdCollision = 0x0200, /*!< BD collision*/
+ kEnetRxBdPhyErr = 0x0400, /*!< PHY error*/
+ kEnetRxBdMacErr = 0x8000 /*!< Mac error */
+} enet_rx_bd_control_extend_t;
+
+/*! @brief Defines the control status of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_status
+{
+ kEnetTxBdReady = 0x8000, /*!< Ready bit*/
+ kEnetTxBdTxSoftOwner1 = 0x4000, /*!< Transmit software owner*/
+ kEnetTxBdWrap = 0x2000, /*!< Wrap buffer descriptor*/
+ kEnetTxBdTxSoftOwner2 = 0x1000, /*!< Transmit software owner*/
+ kEnetTxBdLast = 0x0800, /*!< Last BD in the frame*/
+ kEnetTxBdTransmitCrc = 0x0400 /*!< Receive for transmit CRC */
+} enet_tx_bd_control_status_t;
+
+/*! @brief Defines the control extended of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend
+{
+ kEnetTxBdTxErr = 0x8000, /*!< Transmit error*/
+ kEnetTxBdTxUnderFlowErr = 0x2000, /*!< Underflow error*/
+ kEnetTxBdExcessCollisionErr = 0x1000, /*!< Excess collision error*/
+ kEnetTxBdTxFrameErr = 0x0800, /*!< Frame error*/
+ kEnetTxBdLatecollisionErr = 0x0400, /*!< Late collision error*/
+ kEnetTxBdOverFlowErr = 0x0200, /*!< Overflow error*/
+ kEnetTxTimestampErr = 0x0100 /*!< Timestamp error*/
+} enet_tx_bd_control_extend_t;
+
+/*! @brief Defines the control extended2 of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend2
+{
+ kEnetTxBdTxInterrupt = 0x4000, /*!< Transmit interrupt*/
+ kEnetTxBdTimeStamp = 0x2000 /*!< Transmit timestamp flag */
+} enet_tx_bd_control_extend2_t;
+#endif
+
+/*! @brief Defines the macro to the different ENET constant value.*/
+typedef enum _enet_constant_parameter
+{
+ kEnetMacAddrLen = 6, /*!< ENET mac address length*/
+ kEnetHashValMask = 0x1f, /*!< ENET hash value mask*/
+ kEnetRxBdCtlJudge1 = 0x0080,/*!< ENET receive buffer descriptor control judge value1*/
+ kEnetRxBdCtlJudge2 = 0x8000 /*!< ENET receive buffer descriptor control judge value2*/
+} enet_constant_parameter_t;
+
+/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/
+typedef enum _enet_config_rmii
+{
+ kEnetCfgMii = 0, /*!< MII mode for data interface*/
+ kEnetCfgRmii = 1 /*!< RMII mode for data interface*/
+} enet_config_rmii_t;
+
+/*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/
+typedef enum _enet_config_speed
+{
+ kEnetCfgSpeed100M = 0, /*!< Speed 100 M mode*/
+ kEnetCfgSpeed10M = 1 /*!< Speed 10 M mode*/
+} enet_config_speed_t;
+
+/*! @brief Defines the half or full duplex mode for the data transfer.*/
+typedef enum _enet_config_duplex
+{
+ kEnetCfgHalfDuplex = 0, /*!< Half duplex mode*/
+ kEnetCfgFullDuplex = 1 /*!< Full duplex mode*/
+} enet_config_duplex_t;
+
+/*! @brief Defines the write/read operation for the MII.*/
+typedef enum _enet_mii_operation
+{
+ kEnetWriteNoCompliant = 0, /*!< Write frame operation, but not MII compliant.*/
+ kEnetWriteValidFrame = 1, /*!< Write frame operation for a valid MII management frame*/
+ kEnetReadValidFrame = 2, /*!< Read frame operation for a valid MII management frame.*/
+ kEnetReadNoCompliant = 3 /*!< Read frame operation, but not MII compliant*/
+}enet_mii_operation_t;
+
+/*! @brief Define holdon time on MDIO output*/
+typedef enum _enet_mdio_holdon_clkcycle
+{
+ kEnetMdioHoldOneClkCycle = 0, /*!< MDIO output hold on one clock cycle*/
+ kEnetMdioHoldTwoClkCycle = 1, /*!< MDIO output hold on two clock cycles*/
+ kEnetMdioHoldThreeClkCycle = 2, /*!< MDIO output hold on three clock cycles*/
+ kEnetMdioHoldFourClkCycle = 3, /*!< MDIO output hold on four clock cycles*/
+ kEnetMdioHoldFiveClkCycle = 4, /*!< MDIO output hold on five clock cycles*/
+ kEnetMdioHoldSixClkCycle = 5, /*!< MDIO output hold on six clock cycles*/
+ kEnetMdioHoldSevenClkCycle = 6, /*!< MDIO output hold seven two clock cycles*/
+ kEnetMdioHoldEightClkCycle = 7, /*!< MDIO output hold on eight clock cycles*/
+}enet_mdio_holdon_clkcycle_t;
+
+/*! @brief Defines the initialization, enables or disables the operation for a special address filter */
+typedef enum _enet_special_address_filter
+{
+ kEnetSpecialAddressInit= 0, /*!< Initializes the special address filter.*/
+ kEnetSpecialAddressEnable = 1, /*!< Enables the special address filter.*/
+ kEnetSpecialAddressDisable = 2 /*!< Disables the special address filter.*/
+} enet_special_address_filter_t;
+
+/*! @brief Defines the capture or compare mode for 1588 timer channels.*/
+typedef enum _enet_timer_channel_mode
+{
+ kEnetChannelDisable = 0, /*!< Disable timer channel*/
+ kEnetChannelRisingCapture = 1, /*!< Input capture on rising edge*/
+ kEnetChannelFallingCapture = 2, /*!< Input capture on falling edge*/
+ kEnetChannelBothCapture = 3, /*!< Input capture on both edges*/
+ kEnetChannelSoftCompare = 4, /*!< Output compare software only*/
+ kEnetChannelToggleCompare = 5, /*!< Toggle output on compare*/
+ kEnetChannelClearCompare = 6, /*!< Clear output on compare*/
+ kEnetChannelSetCompare = 7, /*!< Set output on compare*/
+ kEnetChannelClearCompareSetOverflow = 10, /*!< Clear output on compare, set output on overflow*/
+ kEnetChannelSetCompareClearOverflow = 11, /*!< Set output on compare, clear output on overflow*/
+ kEnetChannelPulseLowonCompare = 14, /*!< Pulse output low on compare for one 1588 clock cycle*/
+ kEnetChannelPulseHighonCompare = 15 /*!< Pulse output high on compare for one 1588 clock cycle*/
+} enet_timer_channel_mode_t;
+
+/*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/
+typedef enum _enet_interrupt_request
+{
+ kEnetBabrInterrupt = 0x40000000, /*!< BABR interrupt source*/
+ kEnetBabtInterrupt = 0x20000000, /*!< BABT interrupt source*/
+ kEnetGraInterrupt = 0x10000000, /*!< GRA interrupt source*/
+ kEnetTxFrameInterrupt = 0x8000000, /*!< TXFRAME interrupt source */
+ kEnetTxByteInterrupt = 0x4000000, /*!< TXBYTE interrupt source*/
+ kEnetRxFrameInterrupt = 0x2000000, /*!< RXFRAME interrupt source */
+ kEnetRxByteInterrupt = 0x1000000, /*!< RXBYTE interrupt source */
+ kEnetMiiInterrupt = 0x0800000, /*!< MII interrupt source*/
+ kEnetEBERInterrupt = 0x0400000, /*!< EBERR interrupt source*/
+ kEnetLcInterrupt = 0x0200000, /*!< LC interrupt source*/
+ kEnetRlInterrupt = 0x0100000, /*!< RL interrupt source*/
+ kEnetUnInterrupt = 0x0080000, /*!< UN interrupt source*/
+ kEnetPlrInterrupt = 0x0040000, /*!< PLR interrupt source*/
+ kEnetWakeupInterrupt = 0x0020000, /*!< WAKEUP interrupt source*/
+ kEnetTsAvailInterrupt = 0x0010000, /*!< TS AVAIL interrupt source*/
+ kEnetTsTimerInterrupt = 0x0008000, /*!< TS WRAP interrupt source*/
+ kEnetAllInterrupt = 0x7FFFFFFF /*!< All interrupt*/
+} enet_interrupt_request_t;
+
+/*! @brief Defines the six-byte Mac address type.*/
+typedef uint8_t enetMacAddr[kEnetMacAddrLen];
+
+#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) && SYSTEM_LITTLE_ENDIAN
+/*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/
+typedef struct ENETBdStruct
+{
+ uint16_t length; /*!< Buffer descriptor data length*/
+ uint16_t control; /*!< Buffer descriptor control*/
+ uint8_t *buffer; /*!< Data buffer pointer*/
+ uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/
+ uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/
+ uint16_t payloadCheckSum; /*!< Internal payload checksum*/
+ uint8_t headerLength; /*!< Header length*/
+ uint8_t protocalTyte; /*!< Protocol type*/
+ uint16_t reserved0;
+ uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/
+ uint32_t timestamp; /*!< Timestamp */
+ uint16_t reserved1;
+ uint16_t reserved2;
+ uint16_t reserved3;
+ uint16_t reserved4;
+} enet_bd_struct_t;
+#define TX_DESC_UPDATED_MASK (0x8000)
+#else
+/*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/
+typedef struct ENETBdStruct
+{
+ uint16_t control; /*!< Buffer descriptor control */
+ uint16_t length; /*!< Buffer descriptor data length*/
+ uint8_t *buffer; /*!< Data buffer pointer*/
+ uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/
+ uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/
+ uint8_t headerLength; /*!< Header length*/
+ uint8_t protocalTyte; /*!< Protocol type*/
+ uint16_t payloadCheckSum; /*!< Internal payload checksum*/
+ uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/
+ uint16_t reserved0;
+ uint32_t timestamp; /*!< Timestamp pointer*/
+ uint16_t reserved1;
+ uint16_t reserved2;
+ uint16_t reserved3;
+ uint16_t reserved4;
+} enet_bd_struct_t;
+#define TX_DESC_UPDATED_MASK (0x0080)
+#endif
+
+/*! @brief Defines the configuration structure for the 1588 PTP timer.*/
+typedef struct ENETConfigPtpTimer
+{
+ bool isSlaveEnabled; /*!< Master or slave PTP timer*/
+ uint32_t clockIncease; /*!< Timer increase value each clock period*/
+ uint32_t period; /*!< Timer period for generate interrupt event */
+} enet_config_ptp_timer_t;
+
+/*! @brief Defines the transmit accelerator configuration.*/
+typedef struct ENETConfigTxAccelerator
+{
+ bool isIpCheckEnabled; /*!< Insert IP header checksum */
+ bool isProtocolCheckEnabled; /*!< Insert protocol checksum*/
+ bool isShift16Enabled; /*!< Tx FIFO shift-16*/
+} enet_config_tx_accelerator_t;
+
+/*! @brief Defines the receive accelerator configuration.*/
+typedef struct ENETConfigRxAccelerator
+{
+ bool isIpcheckEnabled; /*!< Discard with wrong IP header checksum */
+ bool isProtocolCheckEnabled; /*!< Discard with wrong protocol checksum*/
+ bool isMacCheckEnabled; /*!< Discard with Mac layer errors*/
+ bool isPadRemoveEnabled; /*!< Padding removal for short IP frames*/
+ bool isShift16Enabled; /*!< Rx FIFO shift-16*/
+} enet_config_rx_accelerator_t;
+
+/*! @brief Defines the transmit FIFO configuration.*/
+typedef struct ENETConfigTxFifo
+{
+ bool isStoreForwardEnabled; /*!< Transmit FIFO store and forward */
+ uint8_t txFifoWrite; /*!< Transmit FIFO write */
+ uint8_t txEmpty; /*!< Transmit FIFO section empty threshold*/
+ uint8_t txAlmostEmpty; /*!< Transmit FIFO section almost empty threshold*/
+ uint8_t txAlmostFull; /*!< Transmit FIFO section almost full threshold*/
+} enet_config_tx_fifo_t;
+
+/*! @brief Defines the receive FIFO configuration.*/
+typedef struct ENETConfigRxFifo
+{
+ uint8_t rxFull; /*!< Receive FIFO section full threshold*/
+ uint8_t rxAlmostFull; /*!< Receive FIFO section almost full threshold*/
+ uint8_t rxEmpty; /*!< Receive FIFO section empty threshold*/
+ uint8_t rxAlmostEmpty; /*!< Receive FIFO section almost empty threshold*/
+} enet_config_rx_fifo_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Resets the ENET module.
+ *
+ * @param instance The ENET instance number
+ */
+static inline void enet_hal_reset_ethernet(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_ECR_SET(instance, BM_ENET_ECR_RESET);
+}
+
+/*!
+ * @brief Gets the ENET status to check whether the reset has completed.
+ *
+ * @param instance The ENET instance number
+ * @return Current status of the reset operation
+ * - true if ENET reset completed.
+ * - false if ENET reset has not completed.
+ */
+static inline bool enet_hal_is_reset_completed(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return (BR_ENET_ECR_RESET(instance) == 0);
+}
+
+/*!
+ * @brief Enable or disable stop mode.
+ *
+ * Enable stop mode will control device behavior in doze mode.
+ * In doze mode, if this filed is set then all clock of the enet assemably are
+ * disabled, except the RMII/MII clock.
+ *
+ * @param instance The ENET instance number.
+ * @param isEnabled The switch to enable/disable stop mode.
+ * - true to enabale the stop mode.
+ * - false to disable the stop mode.
+ */
+static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_ECR_STOPEN(instance, isEnabled);
+}
+/*!
+ * @brief Enable or disable sleep mode.
+ *
+ * Enable sleep mode will disable normal operating mode. When enable the sleep
+ * mode, the magic packet detection is also enabled so that a remote agent can
+ * wakeup the node.
+ *
+ * @param instance The ENET instance number.
+ * @param isEnabled The switch to enable/disable the sleep mode.
+ * - true to enabale the sleep mode.
+ * - false to disable the sleep mode.
+ */
+ static inline void enet_hal_enable_sleep(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_ECR_SLEEP(instance, isEnabled);
+ BW_ENET_ECR_MAGICEN(instance, isEnabled);
+}
+
+/*!
+ * @brief Sets the Mac address.
+ *
+ * This interface sets the six-byte Mac address of the ENET interface.
+ *
+ * @param instance The ENET instance number
+ * @param hwAddr The mac address pointer store for six bytes Mac address
+ */
+void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr);
+
+/*!
+ * @brief Sets the hardware addressing filtering to a multicast group address.
+ *
+ * This interface is used to add the ENET device to a multicast group address.
+ * After joining the group, Mac receives all frames with the group Mac address.
+ *
+ * @param instance The ENET instance number
+ * @param crcValue The CRC value of the special address
+ * @param mode The operation for init/enable/disable the specified hardware address
+ */
+void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
+
+/*!
+ * @brief Sets the hardware addressing filtering to an individual address.
+ *
+ * This interface is used to add an individual address to the hardware address
+ * filter. Mac receives all frames with the individual address as a destination address.
+ *
+ * @param instance The ENET instance number
+ * @param crcValue The CRC value of the special address
+ * @param mode The operation for init/enable/disable the specified hardware address
+ */
+void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
+
+/*!
+ * @brief Enable/disable payload length check.
+ *
+ * If the length/type is less than 0x600,When enable payload length check
+ * the core checks the fame's payload length. If the length/type is greater
+ * than or equal to 0x600. The MAC interprets the field as a type and no
+ * payload length check is performanced.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable payload length check
+ * - True to enabale payload length check.
+ * - False to disable payload legnth check.
+ */
+static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_NLC(instance, isEnabled);
+}
+
+/*!
+ * @brief Enable/disable append CRC to transmitted frames.
+ *
+ * If transmit CRC forward is enabled, the transmit buffer descriptor controls
+ * whether the frame has a CRC from the application. If transmit CRC forward is disabled,
+ * transmitter does not append any CRC to transmitted frames.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable transmit the receive CRC
+ * - True the transmitter control CRC through transmit buffer descriptor.
+ * - False the transmitter does not append any CRC to transmitted frames.
+ */
+static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_TCR_CRCFWD(instance, !isEnabled);
+}
+
+/*!
+ * @brief Enable/disable forward the CRC filed of the received frame.
+ *
+ * This is used to deceide whether the CRC field of received frame is transmitted
+ * or stripped. Enable this feature to strip CRC field from the frame.
+ * If padding remove is enabled, this feature will be ignored and
+ * the CRC field is checked and always terminated and removed.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable transmit the receive CRC
+ * - True to transmit the received CRC.
+ * - False to strip the received CRC.
+ */
+static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_CRCFWD(instance, !isEnabled);
+}
+/*!
+ * @brief Enable/disable forward PAUSE frames.
+ *
+ * This is used to deceide whether PAUSE frames is forwarded or discarded.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable forward PAUSE frames
+ * - True to forward PAUSE frames.
+ * - False to terminate and discard PAUSE frames.
+ */
+static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_PAUFWD(instance, isEnabled);
+}
+
+/*!
+ * @brief Enable/disable frame padding remove on receive.
+ *
+ * Enable frame padding remove will remove the padding from the received frames.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable remove padding
+ * - True to remove padding from frames.
+ * - False to disable padding remove.
+ */
+static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_PADEN(instance, isEnabled);
+}
+
+/*!
+ * @brief Enable/disable flow control.
+ *
+ * If flow control is enabled, the receive detects PAUSE frames.
+ * Upon PAUSE frame detection, the transmitter stops transmitting
+ * data frames for a given duration.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable flow control
+ * - True to enable the flow control.
+ * - False to disable the flow control.
+ */
+static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_CFEN(instance, isEnabled);
+ BW_ENET_RCR_FCE(instance, isEnabled);
+}
+
+/*!
+ * @brief Enable/disable broadcast frame reject.
+ *
+ * If broadcast frame reject is enabled, frames with destination address
+ * equal to 0xffff_ffff_ffff are rejected unless the promiscuous mode is open.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable reject broadcast frames
+ * - True to reject broadcast frames.
+ * - False to accept broadcast frames.
+ */
+static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_RCR_BC_REJ(instance, isEnabled);
+}
+
+/*!
+ * @brief Sets PAUSE duration for a PAUSE frame.
+ *
+ * This function is used to set the pause duraion used in transmission
+ * of a PAUSE frame. When another node detects a PAUSE frame, that node
+ * pauses transmission for the pause duration.
+ *
+ * @param instance The ENET instance number
+ * @param pauseDuration The PAUSE duration for the transmitted PAUSE frame
+ * the maximum pause duration is 0xFFFF.
+ */
+static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseDuration)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
+ BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
+}
+
+/*!
+ * @brief Gets receive PAUSE frame status.
+ *
+ * This function is used to get the received PAUSE frame status.
+ *
+ * @param instance The ENET instance number
+ * @return The status of the received flow control frames
+ * true if the flow control pause frame is received.
+ * false if there is no flow control frame received or the pause duration is complete.
+ */
+static inline bool enet_hal_get_rxpause_status(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ return BR_ENET_TCR_RFC_PAUSE(instance);
+}
+/*!
+ * @brief Enables transmit frame control PAUSE.
+ *
+ * This function enables pauses frame transmission.
+ * When this is set, with transmission of data frames stopped, the MAC
+ * transmits a MAC control PAUSE frame. NEXT, the MAC clear the
+ * and resumes transmitting data frames.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The switch to enable/disable PAUSE control frame transmission
+ * - True enable PAUSE control frame transmission.
+ * - Flase disable PAUSE control frame transmission.
+ */
+static inline void enet_hal_enable_txpause(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ BW_ENET_TCR_TFC_PAUSE(instance, isEnabled);
+}
+
+/*!
+ * @brief Sets transmit PAUSE frame.
+ *
+ * This function Sets ENET transmit controller with pause duration.
+ * And set the transmit control to do PAUSE frame transmission
+ * This should be called when a PAUSE frame is dynamically wanted.
+ *
+ * @param instance The ENET instance number
+ */
+void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration);
+
+/*!
+ * @brief Sets the transmit inter-packet gap.
+ *
+ * This function indicates the IPG, in bytes, between transmitted frames.
+ * Valid values range from 8 to 27. If value is less than 8, the IPG is 8.
+ * If value is greater than 27, the IPG is 27.
+ *
+ * @param instance The ENET instance number
+ * @param ipgValue The IPG for transmitted frames
+ * The default value is 12, the maximum value set to ipg is 0x1F.
+ *
+ */
+static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(ipgValue <= BM_ENET_TIPG_IPG);
+ BW_ENET_TIPG_IPG(instance, ipgValue);
+}
+
+/*!
+ * @brief Sets the receive frame truncation length.
+ *
+ * This function indicates the value a receive frame is truncated,
+ * if it is greater than this value. The frame truncation length must be greater
+ * than or equal to the receive maximum frame length.
+ *
+ * @param instance The ENET instance number
+ * @param length The truncation length. The maximum value is 0x3FFF
+ * The default truncation length is 2047(0x7FF).
+ *
+ */
+static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(length <= BM_ENET_FTRL_TRUNC_FL);
+ BW_ENET_FTRL_TRUNC_FL(instance, length);
+}
+
+/*!
+ * @brief Sets the maximum receive buffer size and the maximum frame size.
+ *
+ * @param instance The ENET instance number
+ * @param maxBufferSize The maximum receive buffer size, which should not be smaller than 256
+ * It should be evenly divisible by 16 and the maximum receive size should not be larger than 0x3ff0.
+ * @param maxFrameSize The maximum receive frame size, the reset value is 1518 or 1522 if the VLAN tags are
+ * supported. The length is measured starting at DA and including the CRC.
+ */
+static inline void enet_hal_set_rx_max_size(uint32_t instance, uint32_t maxBufferSize, uint32_t maxFrameSize)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ /* max buffer size must larger than 256 to minimize bus usage*/
+ assert(maxBufferSize >= 256);
+ assert(maxFrameSize <= (BM_ENET_RCR_MAX_FL >> BP_ENET_RCR_MAX_FL));
+
+ BW_ENET_RCR_MAX_FL(instance, maxFrameSize);
+ HW_ENET_MRBR_WR(instance, (maxBufferSize & BM_ENET_MRBR_R_BUF_SIZE));
+}
+
+/*!
+ * @brief Configures the ENET transmit FIFO.
+ *
+ * @param instance The ENET instance number
+ * @param thresholdCfg The FIFO threshold configuration
+ */
+void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg);
+
+/*!
+ * @brief Configures the ENET receive FIFO.
+ *
+ * @param instance The ENET instance number
+ * @param thresholdCfg The FIFO threshold configuration
+ */
+void enet_hal_config_rx_fifo(uint32_t instance, enet_config_rx_fifo_t *thresholdCfg);
+
+/*!
+ * @brief Sets the start address for ENET receive buffer descriptors.
+ *
+ * This interface provides the beginning of the receive
+ * and receive buffer descriptor queue in the external memory. The
+ * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
+ *
+ * @param instance The ENET instance number
+ * @param rxBdAddr The start address of receive buffer descriptors
+ */
+static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAddr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_RDSR_WR(instance,rxBdAddr); /* Initialize receive buffer descriptor start address*/
+}
+/*!
+ * @brief Sets the start address for ENET transmit buffer descriptors.
+ *
+ * This interface provides the beginning of the receive
+ * and transmit buffer descriptor queue in the external memory. The
+ * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
+ *
+ * @param instance The ENET instance number
+ * @param txBdAddr The start address of transmit buffer descriptors
+ */
+static inline void enet_hal_set_txbd_address(uint32_t instance, uint32_t txBdAddr)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_TDSR_WR(instance,txBdAddr); /* Initialize transmit buffer descriptor start address*/
+}
+
+/*!
+ * @brief Initializes the receive buffer descriptors.
+ *
+ * To make sure the uDMA will do the right data transfer after you activate
+ * with wrap flag and all the buffer descriptors should be initialized with an empty bit.
+ *
+ * @param rxBds The current receive buffer descriptor
+ * @param buffer The data buffer on buffer descriptor
+ * @param isLastBd The flag to indicate the last receive buffer descriptor
+ */
+void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd);
+
+/*!
+ * @brief Initializes the transmit buffer descriptors.
+ *
+ * To make sure the uDMA will do the right data transfer after you active
+ * with wrap flag.
+ *
+ * @param txBds The current transmit buffer descriptor.
+ * @param isLastBd The last transmit buffer descriptor flag.
+ */
+void enet_hal_init_txbds(void *txBds, bool isLastBd);
+
+/*!
+ * @brief Updates the receive buffer descriptors.
+ *
+ * This interface mainly clears the status region and updates the received
+ * buffer descriptor to ensure that the BD is correctly used.
+ *
+ * @param rxBds The current receive buffer descriptor
+ * @param data The data buffer address
+ * @param isbufferUpdate The data buffer update flag. When you want to update
+ * the data buffer of the buffer descriptor ensure that this flag
+ * is set.
+ */
+void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate);
+
+/*!
+ * @brief Initializes the transmit buffer descriptors.
+ *
+ * Ensures that the uDMA transfer data correctly after the user activates
+ * with the wrap flag.
+ *
+ * @param txBds The current transmit buffer descriptor
+ * @param isLastBd The last transmit buffer descriptor flag
+ */
+void enet_hal_init_txbds(void *txBds, bool isLastBd);
+
+/*!
+ * @brief Updates the transmit buffer descriptors.
+ *
+ * This interface mainly clears the status region and updates the transmit
+ * buffer descriptor to ensure tat this BD is correctly used again.
+ * You should set the isTxtsCfged when the transmit timestamp feature is required.
+ *
+ * @param txBds The current transmit buffer descriptor
+ * @param buffer The data buffer on buffer descriptor
+ * @param length The data length on buffer descriptor
+ * @param isTxtsCfged The timestamp configure flag. The timestamp is
+ * added to the transmit buffer descriptor when this flag is set.
+ */
+void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged);
+
+/*!
+ * @brief Clears the context in the transmit buffer descriptors.
+ *
+ * Clears the data, length, control, and status region of the transmit buffer descriptor.
+ *
+ * @param curBd The current buffer descriptor
+ */
+static inline void enet_hal_clear_txbds(void *curBd)
+{
+ assert(curBd);
+
+ volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
+ bdPtr->length = 0; /* Set data length*/
+ bdPtr->buffer = (uint8_t *)(NULL);/* Set data buffer*/
+ bdPtr->control &= (kEnetTxBdWrap);/* Set control */
+}
+
+/*!
+ * @brief Gets the control and the status region of the receive buffer descriptors.
+ *
+ * This interface can get the whole control and status region of the
+ * receive buffer descriptor. The enet_rx_bd_control_status_t enum type
+ * definition should be used if you want to get each status bit of
+ * the control and status region.
+ *
+ * @param curBd The current receive buffer descriptor
+ * @return The control and status data on buffer descriptors
+ */
+uint16_t enet_hal_get_rxbd_control(void *curBd);
+
+/*!
+ * @brief Gets the control and the status region of the transmit buffer descriptors.
+ *
+ * This interface can get the whole control and status region of the
+ * transmit buffer descriptor. The enet_tx_bd_control_status_t enum type
+ * definition should be used if you want to get each status bit of
+ * the control and status region.
+ *
+ * @param curBd The current transmit buffer descriptor
+ * @return The extended control region of transmit buffer descriptor
+ */
+uint16_t enet_hal_get_txbd_control(void *curBd);
+
+/*!
+ * @brief Gets the extended control region of the receive buffer descriptors.
+ *
+ * This interface can get the whole control and status region of the
+ * receive buffer descriptor. The enet_rx_bd_control_extend_t enum type
+ * definition should be used if you want to get each status bit of
+ * the control and status region.
+ *
+ * @param curBd The current receive buffer descriptor
+ * @param controlRegion The different control region
+ * @return The extended control region data of receive buffer descriptor
+ * - true when the control region is set
+ * - false when the control region is not set
+ */
+bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion);
+/*!
+ * @brief Gets the extended control region of the transmit buffer descriptors.
+ *
+ * This interface can get the whole control and status region of the
+ * transmit buffer descriptor. The enet_tx_bd_control_extend_t enum type
+ * definition should be used if you want to get each status bit of
+ * the control and status region.
+ *
+ * @param curBd The current transmit buffer descriptor
+ * @return The extended control data
+ */
+uint16_t enet_hal_get_txbd_control_extend(void *curBd);
+
+/*!
+ * @brief Gets the data length of the buffer descriptors.
+ *
+ * @param curBd The current buffer descriptor
+ * @return The data length of the buffer descriptor
+ */
+uint16_t enet_hal_get_bd_length(void *curBd);
+
+/*!
+ * @brief Gets the buffer address of the buffer descriptors.
+ *
+ * @param curBd The current buffer descriptor
+ * @return The buffer address of the buffer descriptor
+ */
+uint8_t* enet_hal_get_bd_buffer(void *curBd);
+
+/*!
+ * @brief Gets the timestamp of the buffer descriptors.
+ *
+ * @param curBd The current buffer descriptor
+ * @return The time stamp of the frame in the buffer descriptor.
+ * Notice that the frame timestamp is only set in the last
+ * buffer descriptor of the frame.
+ */
+uint32_t enet_hal_get_bd_timestamp(void *curBd);
+
+/*!
+ * @brief Activates the receive buffer descriptor.
+ *
+ * The buffer descriptor activation
+ * should be done after the ENET module is enabled. Otherwise, the activation fails.
+ *
+ * @param instance The ENET instance number
+ */
+ static inline void enet_hal_active_rxbd(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_RDAR_SET(instance, BM_ENET_RDAR_RDAR);
+}
+
+/*!
+ * @brief Activates the transmit buffer descriptor.
+ *
+ * The buffer descriptor activation should be done after the ENET module is
+ * enabled. Otherwise, the activation fails.
+ *
+ * @param instance The ENET instance number
+ */
+static inline void enet_hal_active_txbd(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_TDAR_SET(instance, BM_ENET_TDAR_TDAR);
+}
+
+/*!
+ * @brief Configures the (R)MII of ENET.
+ *
+ * @param instance The ENET instance number
+ * @param mode The RMII or MII mode
+ * @param speed The speed of RMII
+ * @param duplex The full or half duplex mode
+ * @param isRxOnTxDisabled The Receive on transmit disable flag
+ * @param isLoopEnabled The loop enable flag
+ */
+void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled);
+
+/*!
+ * @brief Configures the MII of ENET.
+ *
+ * Sets the MII interface between Mac and PHY. The miiSpeed is
+ * a value that controls the frequency of the MDC, relative to the internal module clock(InterClockSrc).
+ * A value of zero in this parameter turns the MDC off and leaves it in the low voltage state.
+ * Any non-zero value results in the MDC frequency MDC = InterClockSrc/((miiSpeed + 1)*2).
+ * So miiSpeed = InterClockSrc/(2*MDC) - 1.
+ * The Maximum MDC clock is 2.5MHZ(maximum). We should round up and plus one to simlplify:
+ * miiSpeed = InterClockSrc/(2*2.5MHZ).
+ *
+ * @param instance The ENET instance number
+ * @param miiSpeed The MII speed and it is ranged from 0~0x3F
+ * @param time The holdon clock cycles for MDIO output
+ * @param isPreambleDisabled The preamble disabled flag
+ */
+static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed,
+ enet_mdio_holdon_clkcycle_t clkCycle, bool isPreambleDisabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_MSCR_MII_SPEED(instance, miiSpeed); /* MII speed set*/
+ BW_ENET_MSCR_DIS_PRE(instance, isPreambleDisabled); /* Preamble is disabled*/
+ BW_ENET_MSCR_HOLDTIME(instance, clkCycle); /* hold on clock cycles for MDIO output*/
+
+}
+
+/*!
+ * @brief Gets the MII configuration status.
+ *
+ * This interface is usually called to check the MII interface before
+ * the Mac writes or reads the PHY registers.
+ *
+ * @param instance The ENET instance number
+ * @return The MII configuration status
+ * - true if the MII has been configured.
+ * - false if the MII has not been configured.
+ */
+static inline bool enet_hal_is_mii_enabled(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return (HW_ENET_MSCR_RD(instance) & 0x7E)!= 0;
+}
+
+/*!
+ * @brief Reads data from PHY.
+ *
+ * @param instance The ENET instance number
+ * @return The data read from PHY
+ */
+static inline uint32_t enet_hal_get_mii_data(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return (uint32_t)BR_ENET_MMFR_DATA(instance);
+}
+
+/*!
+ * @brief Sets the MII command.
+ *
+ * @param instance The ENET instance number
+ * @param phyAddr The PHY address
+ * @param phyReg The PHY register
+ * @param operation The read or write operation
+ * @param data The data written to PHY
+ */
+void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data);
+
+/*!
+ * @brief Enables/Disables the ENET module.
+ *
+ * @param instance The ENET instance number
+ * @param isEnhanced The enhanced 1588 feature switch
+ * @param isEnabled The ENET module enable switch
+ */
+void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled);
+
+/*!
+ * @brief Enables/Disables the ENET interrupt.
+ *
+ * @param instance The ENET instance number
+ * @param source The interrupt sources. enet_interrupt_request_t enum types
+ * is recommended as the interrupt source.
+ * @param isEnabled The interrupt enable switch
+ */
+void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled);
+
+/*!
+ * @brief Clears ENET interrupt events.
+ *
+ * @param instance The ENET instance number
+ * @param source The interrupt source to be cleared. enet_interrupt_request_t
+ * enum types is recommended as the interrupt source.
+ */
+static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_EIR_WR(instance,source);
+}
+
+/*!
+ * @brief Gets the ENET interrupt status.
+ *
+ * @param instance The ENET instance number
+ * @param source The interrupt sources. enet_interrupt_request_t
+ * enum types is recommended as the interrupt source.
+ * @return The event status of the interrupt source
+ * - true if the interrupt event happened.
+ * - false if the interrupt event has not happened.
+ */
+static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t source)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return ((HW_ENET_EIR_RD(instance) & source) != 0);
+}
+
+/*
+ * @brief Enables/disables the ENET promiscuous mode.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The enable switch
+ */
+static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_RCR_PROM(instance,isEnabled);
+}
+
+/*!
+ * @brief Enables/disables the clear MIB counter.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The enable switch
+ */
+static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_MIBC_MIB_CLEAR(instance, isEnabled);
+
+}
+
+/*!
+ * @brief Sets the enable/disable of the MIB block.
+ *
+ * @param instance The ENET instance number
+ * @param isEnabled The enable flag
+ * - True to enabale MIB block.
+ * - False to disable MIB block.
+ */
+static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_MIBC_MIB_DIS(instance,!isEnabled);
+
+}
+
+/*!
+ * @brief Gets the MIB idle status.
+ *
+ * @param instance The ENET instance number
+ * @return true if in MIB idle and MIB is not updating else false.
+ */
+static inline bool enet_hal_get_mib_status(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return BR_ENET_MIBC_MIB_IDLE(instance);
+}
+
+/*!
+ * @brief Sets the transmit accelerator.
+ *
+ * @param instance The ENET instance number
+ * @param txCfgPtr The transmit accelerator configuration
+ */
+void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr);
+
+/*!
+ * @brief Sets the receive accelerator.
+ *
+ * @param instance The ENET instance number
+ * @param rxCfgPtr The receive accelerator configuration
+ */
+void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr);
+
+/*!
+ * @brief Initializes the 1588 timer.
+ *
+ * This interface initializes the 1588 context structure.
+ * Initialize 1588 parameters according to the user configuration structure.
+ *
+ * @param instance The ENET instance number
+ * @param ptpCfg The 1588 timer configuration
+ */
+void enet_hal_init_ptp_timer(uint32_t instance, enet_config_ptp_timer_t *ptpCfgPtr);
+
+/*!
+ * @brief Enables or disables the 1588 timer.
+ *
+ * Enable the PTP timer will starts the timer. Disable the timer will stop timer
+ * at the current value.
+ *
+ * @param instance The ENET instance number.
+ * @param isEnabled The 1588 timer Enable switch
+ * - True enbaled the 1588 PTP timer.
+ * - False disable or stop the 1588 PTP timer.
+ */
+static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabled)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_ATCR_EN(instance,isEnabled);
+}
+
+/*!
+ * @brief Restarts the 1588 timer.
+ *
+ * Restarting the PTP timer clears all PTP-timer counters to zero.
+ *
+ * @param instance The ENET instance number
+ */
+static inline void enet_hal_restart_ptp_timer(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ BW_ENET_ATCR_RESTART(instance,1);
+}
+
+/*!
+ * @brief Adjusts the 1588 timer.
+ *
+ * Adjust the 1588 timer according to the increase and correction period of the configured correction.
+ *
+ * @param instance The ENET instance number
+ * @param inceaseCorrection The increase correction for 1588 timer
+ * @param periodCorrection The period correction for 1588 timer
+ */
+static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increaseCorrection, uint32_t periodCorrection)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_ATINC_SET(instance,((increaseCorrection << ENET_ATINC_INC_CORR_SHIFT) & ENET_ATINC_INC_CORR_MASK)); /* set correction for ptp timer increase*/
+ /* set correction for ptp timer period*/
+ HW_ENET_ATCOR_SET(instance, (BM_ENET_ATCOR_COR & periodCorrection));
+}
+
+/*!
+ * @brief Initializes the 1588 timer channel.
+ *
+ * @param instance The ENET instance number
+ * @Param channel The 1588 timer channel number
+ * @param mode Compare or capture mode for the 1588 timer channel
+ */
+static inline void enet_hal_init_timer_channel(uint32_t instance, uint32_t channel, enet_timer_channel_mode_t mode)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(channel < HW_ENET_TCSRn_COUNT);
+ HW_ENET_TCSRn_SET(instance, channel,
+ (BM_ENET_TCSRn_TMODE &(mode << BP_ENET_TCSRn_TMODE)));
+ HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TIE);
+}
+
+/*!
+ * @brief Sets the compare value for the 1588 timer channel.
+ *
+ * @param instance The ENET instance number
+ * @Param channel The 1588 timer channel number
+ * @param compareValue Compare value for 1588 timer channel
+ */
+static inline void enet_hal_set_timer_channel_compare(uint32_t instance, uint32_t channel, uint32_t compareValue)
+{
+ assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(channel < HW_ENET_TCSRn_COUNT);
+ HW_ENET_TCCRn_WR(instance,channel, compareValue);
+}
+
+/*!
+ * @brief Gets the 1588 timer channel status.
+ *
+ * @param instance The ENET instance number
+ * @param channel The 1588 timer channel number
+ * @return Compare or capture operation status
+ * - True if the compare or capture has occurred.
+ * - False if the compare or capture has not occurred.
+ */
+static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t channel)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(channel < HW_ENET_TCSRn_COUNT);
+
+ return BR_ENET_TCSRn_TF(instance,channel);
+}
+
+/*!
+ * @brief Clears the 1588 timer channel flag.
+ *
+ * @param instance The ENET instance number
+ * @param channel The 1588 timer channel number
+ */
+static inline void enet_hal_clear_timer_channel_flag(uint32_t instance, uint32_t channel)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+ assert(channel < HW_ENET_TCSRn_COUNT);
+ HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TF);/* clear interrupt flag*/
+ HW_ENET_TGSR_WR(instance,(1U << channel)); /* clear channel flag*/
+}
+
+/*!
+ * @brief Sets the capture command to the 1588 timer.
+ *
+ * This is used before reading the current time register.
+ * After set timer capture, please wait for about 1us before read
+ * the captured timer.
+ *
+ * @param instance The ENET instance number
+ */
+static inline void enet_hal_set_timer_capture(uint32_t instance)
+{
+ assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_ATCR_SET(instance, BM_ENET_ATCR_CAPTURE);
+}
+
+/*!
+ * @brief Sets the 1588 timer.
+ *
+ * @param instance The ENET instance number
+ * @param nanSecond The nanosecond set to 1588 timer
+ */
+static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSecond)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ HW_ENET_ATVR_WR(instance,nanSecond);
+}
+
+/*!
+ * @brief Gets the time from the 1588 timer.
+ *
+ * @param instance The ENET instance number
+ * @return the current time from 1588 timer
+ */
+static inline uint32_t enet_hal_get_current_time(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return HW_ENET_ATVR_RD(instance);
+}
+
+/*!
+ * @brief Gets the transmit timestamp.
+ *
+ * @param instance The ENET instance number
+ * @return The timestamp of the last transmitted frame
+ */
+static inline uint32_t enet_hal_get_tx_timestamp(uint32_t instance)
+{
+ // assert(instance < HW_ENET_INSTANCE_COUNT);
+
+ return HW_ENET_ATSTMP_RD(instance);
+}
+
+/*!
+ * @brief Gets the transmit buffer descriptor timestamp flag.
+ *
+ * @param curBd The ENET transmit buffer descriptor
+ * @return true if timestamp region is set else false.
+ */
+bool enet_hal_get_txbd_timestamp_flag(void *curBd);
+
+/*!
+ * @brief Gets the buffer descriptor timestamp.
+ *
+ * @param null
+ * @return The the size of the buffer descriptor
+ */
+static inline uint32_t enet_hal_get_bd_size(void)
+{
+ return sizeof(enet_bd_struct_t);
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
+
+/*! @}*/
+#endif /*!< __FSL_ENET_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,156 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_FTM_FEATURES_H__) +#define __FSL_FTM_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (6) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (6) : \ + ((x) == 1 ? (2) : \ + ((x) == 2 ? (2) : (-1)))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : (-1))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : \ + ((x) == 2 ? (2) : (-1)))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : \ + ((x) == 2 ? (2) : \ + ((x) == 3 ? (8) : (-1))))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ + defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \ + defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \ + defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : \ + ((x) == 2 ? (2) : \ + ((x) == 3 ? (8) : (-1))))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : (-1))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) + /* @brief Bus clock is the source clock for the module. */ + #define FSL_FEATURE_FTM_BUS_CLOCK (1) + /* @brief Number of channels. */ + #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) + #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (2) : \ + ((x) == 2 ? (8) : (-1)))) + /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ + #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_FTM_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_ftm_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+void FTM_HAL_Init(uint32_t ftmBaseAddr)
+{
+
+}
+
+void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
+{
+ FTM_HAL_SetDualEdgeCaptureCmd(ftmBaseAddr, channel, false);
+ FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, config->edgeMode ? 1 : 2);
+ switch(config->mode)
+ {
+ case kFtmEdgeAlignedPWM:
+ FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
+ FTM_HAL_SetCpwms(ftmBaseAddr, 0);
+ FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 2);
+ break;
+ case kFtmCenterAlignedPWM:
+ FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
+ FTM_HAL_SetCpwms(ftmBaseAddr, 1);
+ break;
+ case kFtmCombinedPWM:
+ FTM_HAL_SetCpwms(ftmBaseAddr, 0);
+ FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, true);
+ break;
+ default:
+ assert(0);
+ break;
+ }
+}
+
+void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
+{
+
+ FTM_HAL_SetChnCountVal(ftmBaseAddr, channel, 0);
+ FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, 0);
+ FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 0);
+ FTM_HAL_SetCpwms(ftmBaseAddr, 0);
+ FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
+}
+
+void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance)
+{
+ uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance);
+
+ HW_FTM_SC_WR(ftmBaseAddr, 0);
+ HW_FTM_CNT_WR(ftmBaseAddr, 0);
+ HW_FTM_MOD_WR(ftmBaseAddr, 0);
+
+ for(int i = 0; i < chan; i++)
+ {
+ HW_FTM_CnSC_WR(ftmBaseAddr, i, 0);
+ HW_FTM_CnV_WR(ftmBaseAddr, i, 0);
+ }
+ HW_FTM_CNTIN_WR(ftmBaseAddr, 0);
+ HW_FTM_STATUS_WR(ftmBaseAddr, 0);
+ HW_FTM_MODE_WR(ftmBaseAddr, 0x00000004);
+ HW_FTM_SYNC_WR(ftmBaseAddr, 0);
+ HW_FTM_OUTINIT_WR(ftmBaseAddr, 0);
+ HW_FTM_OUTMASK_WR(ftmBaseAddr, 0);
+ HW_FTM_COMBINE_WR(ftmBaseAddr, 0);
+ HW_FTM_DEADTIME_WR(ftmBaseAddr, 0);
+ HW_FTM_EXTTRIG_WR(ftmBaseAddr, 0);
+ HW_FTM_POL_WR(ftmBaseAddr, 0);
+ HW_FTM_FMS_WR(ftmBaseAddr, 0);
+ HW_FTM_FILTER_WR(ftmBaseAddr, 0);
+ HW_FTM_FLTCTRL_WR(ftmBaseAddr, 0);
+ /*HW_FTM_QDCTRL_WR(instance, 0);*/
+ HW_FTM_CONF_WR(ftmBaseAddr, 0);
+ HW_FTM_FLTPOL_WR(ftmBaseAddr, 0);
+ HW_FTM_SYNCONF_WR(ftmBaseAddr, 0);
+ HW_FTM_INVCTRL_WR(ftmBaseAddr, 0);
+ HW_FTM_SWOCTRL_WR(ftmBaseAddr, 0);
+ HW_FTM_PWMLOAD_WR(ftmBaseAddr, 0);
+}
+
+void FTM_HAL_SetHardwareTriggerCmd(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable)
+{
+ switch(trigger_num)
+ {
+ case 0:
+ BW_FTM_SYNC_TRIG0(ftmBaseAddr, enable ? 1 : 0);
+ break;
+ case 1:
+ BW_FTM_SYNC_TRIG1(ftmBaseAddr, enable ? 1 : 0);
+ break;
+ case 2:
+ BW_FTM_SYNC_TRIG2(ftmBaseAddr, enable ? 1 : 0);
+ break;
+ default:
+ assert(0);
+ break;
+ }
+}
+
+void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < HW_CHAN6);
+
+ uint8_t bit = val ? 1 : 0;
+ uint32_t value = (channel > 1U) ? (uint8_t)(bit << (channel - 2U)) : (uint8_t)(bit << (channel + 4U));
+
+ val ? HW_FTM_EXTTRIG_SET(ftmBaseAddr, value) : HW_FTM_EXTTRIG_CLR(ftmBaseAddr, value);
+}
+
+void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val)
+{
+ assert(channel < HW_CHAN4);
+
+ switch(channel)
+ {
+ case HW_CHAN0:
+ BW_FTM_FILTER_CH0FVAL(ftmBaseAddr, val);
+ break;
+ case HW_CHAN1:
+ BW_FTM_FILTER_CH1FVAL(ftmBaseAddr, val);
+ break;
+ case HW_CHAN2:
+ BW_FTM_FILTER_CH2FVAL(ftmBaseAddr, val);
+ break;
+ case HW_CHAN3:
+ BW_FTM_FILTER_CH3FVAL(ftmBaseAddr, val);
+ break;
+ default:
+ assert(0);
+ break;
+ }
+}
+
+uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel)
+{
+ if((channel == HW_CHAN0) || (channel == HW_CHAN1))
+ {
+ return 0;
+ }
+ else if((channel == HW_CHAN2) || (channel == HW_CHAN3))
+ {
+ return 1;
+ }
+ else if((channel == HW_CHAN4) || (channel == HW_CHAN5))
+ {
+ return 2;
+ }
+ else
+ {
+ return 3;
+ }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1433 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_FTM_HAL_H__)
+#define __FSL_FTM_HAL_H__
+
+#include "fsl_device_registers.h"
+#include "fsl_ftm_features.h"
+#include <stdbool.h>
+#include <assert.h>
+
+/*!
+ * @addtogroup ftm_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define HW_CHAN0 (0U) /*!< Channel number for CHAN0.*/
+#define HW_CHAN1 (1U) /*!< Channel number for CHAN1.*/
+#define HW_CHAN2 (2U) /*!< Channel number for CHAN2.*/
+#define HW_CHAN3 (3U) /*!< Channel number for CHAN3.*/
+#define HW_CHAN4 (4U) /*!< Channel number for CHAN4.*/
+#define HW_CHAN5 (5U) /*!< Channel number for CHAN5.*/
+#define HW_CHAN6 (6U) /*!< Channel number for CHAN6.*/
+#define HW_CHAN7 (7U) /*!< Channel number for CHAN7.*/
+
+#define FTM_COMBINE_CHAN_CTRL_WIDTH (8U)
+
+/*! @brief FlexTimer clock source selection*/
+typedef enum _ftm_clock_source
+{
+ kClock_source_FTM_None = 0,
+ kClock_source_FTM_SystemClk,
+ kClock_source_FTM_FixedClk,
+ kClock_source_FTM_ExternalClk
+}ftm_clock_source_t;
+
+/*! @brief FlexTimer counting mode selection */
+typedef enum _ftm_counting_mode
+{
+ kCounting_FTM_UP = 0,
+ kCounting_FTM_UpDown
+}ftm_counting_mode_t;
+
+/*! @brief FlexTimer pre-scaler factor selection for the clock source*/
+typedef enum _ftm_clock_ps
+{
+ kFtmDividedBy1 = 0,
+ kFtmDividedBy2 ,
+ kFtmDividedBy4 ,
+ kFtmDividedBy8,
+ kFtmDividedBy16,
+ kFtmDividedBy32,
+ kFtmDividedBy64,
+ kFtmDividedBy128
+}ftm_clock_ps_t;
+
+/*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/
+typedef enum _ftm_deadtime_ps
+{
+ kFtmDivided1 = 1,
+ kFtmDivided4 = 2,
+ kFtmDivided16 = 3,
+}ftm_deadtime_ps_t;
+
+/*! @brief FlexTimer operation mode, capture, output, dual */
+typedef enum _ftm_config_mode_t
+{
+ kFtmInputCapture,
+ kFtmOutputCompare,
+ kFtmEdgeAlignedPWM,
+ kFtmCenterAlignedPWM,
+ kFtmCombinedPWM,
+ kFtmDualEdgeCapture
+}ftm_config_mode_t;
+
+/*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */
+typedef enum _ftm_input_capture_edge_mode_t
+{
+ kFtmRisingEdge = 0,
+ kFtmFallingEdge,
+ kFtmRisingAndFalling
+}ftm_input_capture_edge_mode_t;
+
+/*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/
+typedef enum _ftm_output_compare_edge_mode_t
+{
+ kFtmToggleOnMatch = 0,
+ kFtmClearOnMatch,
+ kFtmSetOnMatch
+}ftm_output_compare_edge_mode_t;
+
+/*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */
+typedef enum _ftm_pwm_edge_mode_t
+{
+ kFtmHighTrue = 0,
+ kFtmLowTrue
+}ftm_pwm_edge_mode_t;
+
+/*! @brief FlexTimer dual capture edge mode, one shot or continuous */
+typedef enum _ftm_dual_capture_edge_mode_t
+{
+ kFtmOneShout = 0,
+ kFtmContinuous
+}ftm_dual_capture_edge_mode_t;
+
+/*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */
+typedef enum _ftm_quad_decode_mode_t
+{
+ kFtmQuadPhaseEncode = 0,
+ kFtmQuadCountAndDir
+}ftm_quad_decode_mode_t;
+
+/*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */
+typedef enum _ftm_quad_phase_polarity_t
+{
+ kFtmQuadPhaseNormal = 0,
+ kFtmQuadPhaseInvert
+}ftm_quad_phase_polarity_t;
+
+/*! @brief FlexTimer edge mode*/
+typedef union _ftm_edge_mode_t
+{
+ ftm_input_capture_edge_mode_t input_capture_edge_mode;
+ ftm_output_compare_edge_mode_t output_compare_edge_mode;
+ ftm_pwm_edge_mode_t ftm_pwm_edge_mode;
+ ftm_dual_capture_edge_mode_t ftm_dual_capture_edge_mode;
+}ftm_edge_mode_t;
+
+/*!
+ * @brief FlexTimer driver PWM parameter
+ *
+ */
+typedef struct FtmPwmParam
+{
+ ftm_config_mode_t mode; /*!< FlexTimer PWM operation mode */
+ ftm_pwm_edge_mode_t edgeMode; /*!< PWM output mode */
+ uint32_t uFrequencyHZ; /*!< PWM period in Hz */
+ uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
+ 0=inactive signal(0% duty cycle)...
+ 100=active signal (100% duty cycle). */
+ uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
+ Specifies the delay to the first edge in a PWM period.
+ If unsure please leave as 0, should be specified as
+ percentage of the PWM period*/
+}ftm_pwm_param_t;
+
+/*! @brief FlexTimer quadrature decode phase parameters */
+typedef struct FtmPhaseParam
+{
+ bool kFtmPhaseInputFilter; /*!< false: disable phase filter, true: enable phase filter */
+ uint32_t kFtmPhaseFilterVal; /*!< Filter value, used only if phase input filter is enabled */
+ ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert */
+}ftm_phase_params_t;
+
+/*FTM timer control*/
+/*!
+ * @brief Sets the FTM clock source.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param clock The FTM peripheral clock selection\n
+ * bits - 00: No clock 01: system clock 10: fixed clock 11: External clock
+ */
+static inline void FTM_HAL_SetClockSource(uint32_t ftmBaseAddr, ftm_clock_source_t clock)
+{
+ BW_FTM_SC_CLKS(ftmBaseAddr, clock);
+}
+
+/*!
+ * @brief Reads the FTM clock source.
+ *
+ * @param ftmBaseAddr The FTM base address
+ *
+ * @return The FTM clock source selection\n
+ * bits - 00: No clock 01: system clock 10: fixed clock 11:External clock
+ */
+static inline uint8_t FTM_HAL_GetClockSource(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_SC_CLKS(ftmBaseAddr);
+}
+
+/*!
+ * @brief Sets the FTM clock divider.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param ps The FTM peripheral clock pre-scale divider
+ */
+static inline void FTM_HAL_SetClockPs(uint32_t ftmBaseAddr, ftm_clock_ps_t ps)
+{
+ BW_FTM_SC_PS(ftmBaseAddr, ps);
+}
+
+/*!
+ * @brief Reads the FTM clock divider.
+ *
+ * @param ftmBaseAddr The FTM base address
+ *
+ * @return The FTM clock pre-scale divider
+ */
+static inline uint8_t FTM_HAL_GetClockPs(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_SC_PS(ftmBaseAddr);
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer overflow interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ */
+static inline void FTM_HAL_EnableTimerOverflowInt(uint32_t ftmBaseAddr)
+{
+ HW_FTM_SC_SET(ftmBaseAddr, BM_FTM_SC_TOIE);
+}
+
+/*!
+ * @brief Disables the FTM peripheral timer overflow interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ */
+static inline void FTM_HAL_DisableTimerOverflowInt(uint32_t ftmBaseAddr)
+{
+ HW_FTM_SC_CLR(ftmBaseAddr, BM_FTM_SC_TOIE);
+}
+
+/*!
+ * @brief Reads the bit that controls enabling the FTM timer overflow interrupt.
+ *
+ * @param baseAddr FTM module base address.
+ * @retval true if overflow interrupt is enabled, false if not
+ */
+static inline bool FTM_HAL_IsOverflowIntEnabled(uint32_t baseAddr)
+{
+ return (bool)(BR_FTM_SC_TOIE(baseAddr));
+}
+
+/*!
+ * @brief Clears the timer overflow interrupt flag.
+ *
+ * @param ftmBaseAddr The FTM base address
+ */
+static inline void FTM_HAL_ClearTimerOverflow(uint32_t ftmBaseAddr)
+{
+ BW_FTM_SC_TOF(ftmBaseAddr, 0);
+}
+
+/*!
+ * @brief Returns the FTM peripheral timer overflow interrupt flag.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval true if overflow, false if not
+ */
+static inline bool FTM_HAL_HasTimerOverflowed(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_SC_TOF(ftmBaseAddr);
+}
+
+/*!
+ * @brief Sets the FTM center-aligned PWM select.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param mode 1:upcounting mode 0:up_down counting mode
+ */
+static inline void FTM_HAL_SetCpwms(uint32_t ftmBaseAddr, uint8_t mode)
+{
+ assert(mode < 2);
+ BW_FTM_SC_CPWMS(ftmBaseAddr, mode);
+}
+
+/*!
+ * @brief Sets the FTM peripheral current counter value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val FTM timer counter value to be set
+ */
+static inline void FTM_HAL_SetCounter(uint32_t ftmBaseAddr,uint16_t val)
+{
+ BW_FTM_CNT_COUNT(ftmBaseAddr, val);
+}
+
+/*!
+ * @brief Returns the FTM peripheral current counter value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval current FTM timer counter value
+ */
+static inline uint16_t FTM_HAL_GetCounter(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_CNT_COUNT(ftmBaseAddr);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer modulo value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val The value to be set to the timer modulo
+ */
+static inline void FTM_HAL_SetMod(uint32_t ftmBaseAddr, uint16_t val)
+{
+ BW_FTM_MOD_MOD(ftmBaseAddr, val);
+}
+
+/*!
+ * @brief Returns the FTM peripheral counter modulo value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval FTM timer modulo value
+ */
+static inline uint16_t FTM_HAL_GetMod(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_MOD_MOD(ftmBaseAddr);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer counter initial value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val initial value to be set
+ */
+static inline void FTM_HAL_SetCounterInitVal(uint32_t ftmBaseAddr, uint16_t val)
+{
+ BW_FTM_CNTIN_INIT(ftmBaseAddr, val & BM_FTM_CNTIN_INIT);
+}
+
+/*!
+ * @brief Returns the FTM peripheral counter initial value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval FTM timer counter initial value
+ */
+static inline uint16_t FTM_HAL_GetCounterInitVal(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_CNTIN_INIT(ftmBaseAddr);
+}
+
+/*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */
+/*!
+ * @brief Sets the FTM peripheral timer channel mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11
+ */
+static inline void FTM_HAL_SetChnMSnBAMode(uint32_t ftmBaseAddr, uint8_t channel, uint8_t selection)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ BW_FTM_CnSC_MSA(ftmBaseAddr, channel, selection & 1);
+ BW_FTM_CnSC_MSB(ftmBaseAddr, channel, selection & 2 ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel edge level.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11
+ */
+static inline void FTM_HAL_SetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel, uint8_t level)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ BW_FTM_CnSC_ELSA(ftmBaseAddr, channel, level & 1 ? 1 : 0);
+ BW_FTM_CnSC_ELSB(ftmBaseAddr, channel, level & 2 ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval The MSnB:MSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t FTM_HAL_GetChnMode(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return (BR_FTM_CnSC_MSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_MSB(ftmBaseAddr, channel) << 1));
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel edge level.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval The ELSnB:ELSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t FTM_HAL_GetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return (BR_FTM_CnSC_ELSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_ELSB(ftmBaseAddr, channel) << 1));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel DMA.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param val enable or disable
+ */
+static inline void FTM_HAL_SetChnDmaCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ BW_FTM_CnSC_DMA(ftmBaseAddr, channel,(val? 1 : 0));
+}
+
+/*!
+ * @brief Returns whether the FTM peripheral timer channel DMA is enabled.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval true if enabled, false if disabled
+ */
+static inline bool FTM_HAL_IsChnDma(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return (BR_FTM_CnSC_DMA(ftmBaseAddr, channel) ? true : false);
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer channel(n) interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ */
+static inline void FTM_HAL_EnableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 1);
+}
+/*!
+ * @brief Disables the FTM peripheral timer channel(n) interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ */
+static inline void FTM_HAL_DisableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 0);
+}
+
+/*!
+ * @brief Returns whether any event for the FTM peripheral timer channel has occurred.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval true if event occurred, false otherwise.
+ */
+static inline bool FTM_HAL_HasChnEventOccurred(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return (BR_FTM_CnSC_CHF(ftmBaseAddr, channel)) ? true : false;
+}
+
+/*FTM channel control*/
+/*!
+ * @brief Sets the FTM peripheral timer channel counter value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param val counter value to be set
+ */
+static inline void FTM_HAL_SetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ HW_FTM_CnV_WR(ftmBaseAddr, channel, val);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel counter value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval val return current channel counter value
+ */
+static inline uint16_t FTM_HAL_GetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return BR_FTM_CnV_VAL(ftmBaseAddr, channel);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel event status.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval val return current channel event status value
+ */
+static inline uint32_t FTM_HAL_GetChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ return (HW_FTM_STATUS_RD(ftmBaseAddr)&(1U << channel)) ? true : false;
+ /*return BR_FTM_STATUS(ftmBaseAddr, channel);*/
+}
+
+/*!
+ * @brief Clears the FTM peripheral timer all channel event status.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @retval val return current channel counter value
+ */
+static inline void FTM_HAL_ClearChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ HW_FTM_STATUS_CLR(ftmBaseAddr, 1U << channel);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output mask.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param mask mask to be set 0 or 1, unmasked or masked
+ */
+static inline void FTM_HAL_SetChnOutputMask(uint32_t ftmBaseAddr, uint8_t channel, bool mask)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ mask? HW_FTM_OUTMASK_SET(ftmBaseAddr, 1U << channel) : HW_FTM_OUTMASK_CLR(ftmBaseAddr, 1U << channel);
+ /* BW_FTM_OUTMASK_CHnOM(ftmBaseAddr, channel,mask); */
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output initial state 0 or 1.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param state counter value to be set 0 or 1
+ */
+static inline void FTM_HAL_SetChnOutputInitState(uint32_t ftmBaseAddr, uint8_t channel, uint8_t state)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ HW_FTM_OUTINIT_CLR(ftmBaseAddr, 1U << channel);
+ HW_FTM_OUTINIT_SET(ftmBaseAddr, (uint8_t)(state << channel));
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output polarity.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param pol polarity to be set 0 or 1
+ */
+static inline void FTM_HAL_SetChnOutputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ HW_FTM_POL_CLR(ftmBaseAddr, 1U << channel);
+ HW_FTM_POL_SET(ftmBaseAddr, (uint8_t)(pol << channel));
+}
+/*!
+ * @brief Sets the FTM peripheral timer channel input polarity.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param pol polarity to be set, 0: active high, 1:active low
+ */
+static inline void FTM_HAL_SetChnFaultInputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ HW_FTM_FLTPOL_CLR(ftmBaseAddr, 1U << channel);
+ HW_FTM_FLTPOL_SET(ftmBaseAddr, (uint8_t)(pol<<channel));
+}
+
+
+/*Feature mode selection HAL*/
+ /*FTM fault control*/
+/*!
+ * @brief Enables the FTM peripheral timer fault interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ */
+static inline void FTM_HAL_EnableFaultInt(uint32_t ftmBaseAddr)
+{
+ BW_FTM_MODE_FAULTIE(ftmBaseAddr, 1);
+}
+
+/*!
+ * @brief Disables the FTM peripheral timer fault interrupt.
+ *
+ * @param ftmBaseAddr The FTM base address
+ */
+static inline void FTM_HAL_DisableFaultInt(uint32_t ftmBaseAddr)
+{
+ BW_FTM_MODE_FAULTIE(ftmBaseAddr, 0);
+}
+
+/*!
+ * @brief Defines the FTM fault control mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param mode, valid options are 1, 2, 3, 4
+ */
+static inline void FTM_HAL_SetFaultControlMode(uint32_t ftmBaseAddr, uint8_t mode)
+{
+ BW_FTM_MODE_FAULTM(ftmBaseAddr, mode);
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer capture test mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true to enable capture test mode, false to disable
+ */
+static inline void FTM_HAL_SetCaptureTestCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_MODE_CAPTEST(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM write protection.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true: Write-protection is enabled, false: Write-protection is disabled
+ */
+static inline void FTM_HAL_SetWriteProtectionCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ enable ? BW_FTM_FMS_WPEN(ftmBaseAddr, 1) : BW_FTM_MODE_WPDIS(ftmBaseAddr, 1);
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer group.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true: all registers including FTM-specific registers are available
+ * false: only the TPM-compatible registers are available
+ */
+static inline void FTM_HAL_Enable(uint32_t ftmBaseAddr, bool enable)
+{
+ assert(BR_FTM_MODE_WPDIS(ftmBaseAddr));
+ BW_FTM_MODE_FTMEN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Initializes the channels output.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true: the channels output is initialized according to the state of OUTINIT reg
+ * false: has no effect
+ */
+static inline void FTM_HAL_SetInitChnOutputCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_MODE_INIT(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer sync mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true: no restriction both software and hardware triggers can be used\n
+ * false: software trigger can only be used for MOD and CnV synch, hardware trigger
+ * only for OUTMASK and FTM counter synch.
+ */
+static inline void FTM_HAL_SetPwmSyncMode(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_MODE_PWMSYNC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*FTM synchronization control*/
+/*!
+ * @brief Enables or disables the FTM peripheral timer software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address.
+ * @param enable true: software trigger is selected, false: software trigger is not selected
+ */
+static inline void FTM_HAL_SetSoftwareTriggerCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNC_SWSYNC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param trigger_num 0, 1, 2 for trigger0, trigger1 and trigger3
+ * @param enable true: enable hardware trigger from field trigger_num for PWM synch
+ * false: disable hardware trigger from field trigger_num for PWM synch
+ */
+void FTM_HAL_SetHardwareTrigger(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable);
+
+/*!
+ * @brief Determines when the OUTMASK register is updated with the value of its buffer.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true if OUTMASK register is updated only by PWM sync\n
+ * false if OUTMASK register is updated in all rising edges of the system clock
+ */
+static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNC_SYNCHOM(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Determines if the FTM counter is re-initialized when the selected trigger for
+ * synchronization is detected.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to update FTM counter when triggered , false to count normally
+ */
+static inline void FTM_HAL_SetCountReinitSyncCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNC_REINIT(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer maximum loading points.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to enable maximum loading point, false to disable
+ */
+static inline void FTM_HAL_SetMaxLoadingCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNC_CNTMAX(ftmBaseAddr, enable ? 1 : 0);
+}
+/*!
+ * @brief Enables or disables the FTM peripheral timer minimum loading points.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to enable minimum loading point, false to disable
+ */
+static inline void FTM_HAL_SetMinLoadingCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNC_CNTMIN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Combines the channel control.
+ *
+ * Returns an index for each channel pair.
+ *
+ * @param channel The FTM peripheral channel number.
+ * @return 0 for channel pair 0 & 1\n
+ * 1 for channel pair 2 & 3\n
+ * 2 for channel pair 4 & 5\n
+ * 3 for channel pair 6 & 7
+ */
+uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel);
+
+/*!
+ * @brief Enables the FTM peripheral timer channel pair fault control.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable fault control, false to disable
+ */
+static inline void FTM_HAL_SetDualChnFaultCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair counter PWM sync.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable PWM synchronization, false to disable
+ */
+static inline void FTM_HAL_SetDualChnPwmSyncCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable deadtime insertion, false to disable
+ */
+static inline void FTM_HAL_SetDualChnDeadtimeCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel dual edge capture decap.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable dual edge capture mode, false to disable
+ */
+static inline void FTM_HAL_SetDualChnDecapCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer dual edge capture mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable dual edge capture, false to disable
+ */
+static inline void FTM_HAL_SetDualEdgeCaptureCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair output complement mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable complementary mode, false to disable
+ */
+static inline void FTM_HAL_SetDualChnCompCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair output combine mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param enable True to enable channel pair to combine, false to disable
+ */
+static inline void FTM_HAL_SetDualChnCombineCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+ HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*FTM dead time insertion control*/
+/*!
+ * @brief Sets the FTM deadtime divider.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param divider The FTM peripheral prescale divider\n
+ * 0x :divided by 1, 10: divided by 4, 11:divided by 16
+ */
+static inline void FTM_HAL_SetDeadtimePrescale(uint32_t ftmBaseAddr, ftm_deadtime_ps_t divider)
+{
+ BW_FTM_DEADTIME_DTPS(ftmBaseAddr, divider);
+}
+
+/*!
+ * @brief Sets the FTM deadtime value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param count The FTM peripheral prescale divider\n
+ * 0: no counts inserted, 1: 1 count is inserted, 2: 2 count is inserted....
+ */
+static inline void FTM_HAL_SetDeadtimeCount(uint32_t ftmBaseAddr, uint8_t count)
+{
+ BW_FTM_DEADTIME_DTVAL(ftmBaseAddr, count);
+}
+
+/*!
+* @brief Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register.
+*
+* @param ftmBaseAddr The FTM base address
+* @param enable True to enable, false to disable
+*/
+static inline void FTM_HAL_SetInitTriggerCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_EXTTRIG_INITTRIGEN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*FTM external trigger */
+/*!
+ * @brief Enables or disables the generation of the FTM peripheral timer channel trigger.
+ *
+ * Enables or disables the when the generation of the FTM peripheral timer channel trigger when the
+ * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel Channel to be enabled, valid value 0, 1, 2, 3, 4, 5
+ * @param val True to enable, false to disable
+ */
+void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val);
+
+/*!
+ * @brief Checks whether any channel trigger event has occurred.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval true if there is a channel trigger event, false if not.
+ */
+static inline bool FTM_HAL_IsChnTriggerGenerated(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_EXTTRIG_TRIGF(ftmBaseAddr);
+}
+
+
+/*Fault mode status*/
+/*!
+ * @brief Gets the FTM detected fault input.
+ *
+ * This function reads the status for all fault inputs
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval Return fault byte
+ */
+static inline uint8_t FTM_HAL_GetDetectedFaultInput(uint32_t ftmBaseAddr)
+{
+ return (HW_FTM_FMS(ftmBaseAddr).U & 0x0f);
+}
+/*!
+ * @brief Checks whether the write protection is enabled.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @retval True if enabled, false if not
+ */
+static inline bool FTM_HAL_IsWriteProtectionEnabled(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_FMS_WPEN(ftmBaseAddr) ? true : false;
+}
+
+/*Quadrature decoder control*/
+
+/*!
+ * @brief Enables the channel quadrature decoder.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to enable, false to disable
+ */
+static inline void FTM_HAL_SetQuadDecoderCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_QDCTRL_QUADEN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the phase A input filter.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true enables the phase input filter, false disables the filter
+ */
+static inline void FTM_HAL_SetQuadPhaseAFilterCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_QDCTRL_PHAFLTREN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the phase B input filter.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true enables the phase input filter, false disables the filter
+ */
+static inline void FTM_HAL_SetQuadPhaseBFilterCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_QDCTRL_PHBFLTREN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Selects polarity for the quadrature decode phase A input.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param mode 0: Normal polarity, 1: Inverted polarity
+ */
+static inline void FTM_HAL_SetQuadPhaseAPolarity(uint32_t ftmBaseAddr,
+ ftm_quad_phase_polarity_t mode)
+{
+ BW_FTM_QDCTRL_PHAPOL(ftmBaseAddr, mode);
+}
+
+/*!
+ * @brief Selects polarity for the quadrature decode phase B input.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param mode 0: Normal polarity, 1: Inverted polarity
+ */
+static inline void FTM_HAL_SetQuadPhaseBPolarity(uint32_t ftmBaseAddr,
+ ftm_quad_phase_polarity_t mode)
+{
+ BW_FTM_QDCTRL_PHBPOL(ftmBaseAddr, mode);
+}
+
+/*!
+ * @brief Sets the encoding mode used in quadrature decoding mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param quadMode 0: Phase A and Phase B encoding mode\n
+ * 1: Count and direction encoding mode
+ */
+static inline void FTM_HAL_SetQuadMode(uint32_t ftmBaseAddr, ftm_quad_decode_mode_t quadMode)
+{
+ BW_FTM_QDCTRL_QUADMODE(ftmBaseAddr, quadMode);
+}
+
+/*!
+ * @brief Gets the FTM counter direction in quadrature mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ *
+ * @retval 1 if counting direction is increasing, 0 if counting direction is decreasing
+ */
+static inline uint8_t FTM_HAL_GetQuadDir(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_QDCTRL_QUADMODE(ftmBaseAddr);
+}
+
+/*!
+ * @brief Gets the Timer overflow direction in quadrature mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ *
+ * @retval 1 if TOF bit was set on the top of counting, o if TOF bit was set on the bottom of counting
+ */
+static inline uint8_t FTM_HAL_GetQuadTimerOverflowDir(uint32_t ftmBaseAddr)
+{
+ return BR_FTM_QDCTRL_TOFDIR(ftmBaseAddr);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel input capture filter value.
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number, only 0,1,2,3, channel 4, 5,6, 7 don't have.
+ * @param val Filter value to be set
+ */
+void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val);
+
+/*!
+ * @brief Sets the fault input filter value.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val fault input filter value
+ */
+static inline void FTM_HAL_SetFaultInputFilterVal(uint32_t ftmBaseAddr, uint32_t val)
+{
+ BW_FTM_FLTCTRL_FFVAL(ftmBaseAddr, val);
+}
+
+/*!
+ * @brief Enables or disables the fault input filter.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
+ * @param val true to enable fault input filter, false to disable fault input filter
+ */
+static inline void FTM_HAL_SetFaultInputFilterCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
+{
+ assert(inputNum < HW_CHAN4);
+ val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << (inputNum + 4))) :
+ HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << (inputNum + 4)));
+}
+
+/*!
+ * @brief Enables or disables the fault input.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
+ * @param val true to enable fault input, false to disable fault input
+ */
+static inline void FTM_HAL_SetFaultInputCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
+{
+ assert(inputNum < HW_CHAN4);
+ val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << inputNum)) :
+ HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << inputNum));
+}
+
+/*!
+ * @brief Enables or disables the channel invert for a channel pair.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel The FTM peripheral channel number
+ * @param val true to enable channel inverting, false to disable channel inverting
+ */
+static inline void FTM_HAL_SetDualChnInvertCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+ val ? HW_FTM_INVCTRL_SET(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel))) :
+ HW_FTM_INVCTRL_CLR(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel)));
+}
+
+/*FTM software output control*/
+/*!
+ * @brief Enables or disables the channel software output control.
+ * @param ftmBaseAddr The FTM base address
+ * @param channel Channel to be enabled or disabled
+ * @param val true to enable, channel output will be affected by software output control\n
+ false to disable, channel output is unaffected
+ */
+static inline void FTM_HAL_SetChnSoftwareCtrlCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << channel)) :
+ HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << channel));
+}
+/*!
+ * @brief Sets the channel software output control value.
+ *
+ * @param ftmBaseAddr The FTM base address.
+ * @param channel Channel to be configured
+ * @param val True to set 1, false to set 0
+ */
+static inline void FTM_HAL_SetChnSoftwareCtrlVal(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << (channel + 8))) :
+ HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << (channel + 8)));
+}
+
+/*FTM PWM load control*/
+/*!
+ * @brief Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true to enable, false to disable
+ */
+static inline void FTM_HAL_SetPwmLoadCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_PWMLOAD_LDOK(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Includes or excludes the channel in the matching process.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param channel Channel to be configured
+ * @param val true means include the channel in the matching process\n
+ * false means do not include channel in the matching process
+ */
+static inline void FTM_HAL_SetPwmLoadChnSelCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
+{
+ assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+ val ? HW_FTM_PWMLOAD_SET(ftmBaseAddr, 1U << channel) : HW_FTM_PWMLOAD_CLR(ftmBaseAddr, 1U << channel);
+}
+
+/*FTM configuration*/
+/*!
+ * @brief Enables or disables the FTM global time base signal generation to other FTM's.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to enable, false to disable
+ */
+static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_CONF_GTBEOUT(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM timer global time base.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable True to enable, false to disable
+ */
+static inline void FTM_HAL_SetGlobalTimeBaseCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_CONF_GTBEEN(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the BDM mode..
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val FTM behaviour in BDM mode, options are 0,1,2,3
+ */
+static inline void FTM_HAL_SetBdmMode(uint32_t ftmBaseAddr, uint8_t val)
+{
+ BW_FTM_CONF_BDMMODE(ftmBaseAddr, val);
+}
+
+/*!
+ * @brief Sets the FTM timer TOF Frequency
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param val Value of the TOF bit set frequency
+ */
+static inline void FTM_HAL_SetTofFreq(uint32_t ftmBaseAddr, uint8_t val)
+{
+ BW_FTM_CONF_NUMTOF(ftmBaseAddr, val);
+}
+
+/*FTM sync configuration*/
+ /*hardware sync*/
+/*!
+ * @brief Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means the hardware trigger activates register sync\n
+ * false means the hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_HWSOC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM INVCTRL register when using a hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means the hardware trigger activates register sync\n
+ * false means the hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_HWINVC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM OUTMASK register when using a hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means hardware trigger activates register sync\n
+ * false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_HWOM(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means hardware trigger activates register sync\n
+ * false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetModCntinCvHardwareSycnModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_HWWRBUF(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM counter register when using a hardware trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means hardware trigger activates register sync\n
+ * false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_HWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM SWOCTRL register when using a software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means software trigger activates register sync\n
+ * false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWSOC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM INVCTRL register when using a software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means software trigger activates register sync\n
+ * false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWINVC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM OUTMASK register when using a software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means software trigger activates register sync\n
+ * false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWOM(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets synch mode for FTM MOD, CNTIN and CV registers when using a software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means software trigger activates register sync\n
+ * false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWWRBUF(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM counter register when using a software trigger.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means software trigger activates register sync\n
+ * false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the PWM synchronization mode to enhanced or legacy.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means use Enhanced PWM synchronization\n
+ * false means to use Legacy mode
+ */
+static inline void FTM_HAL_SetPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SYNCMODE(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the SWOCTRL register PWM synchronization mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means SWOCTRL register is updated by PWM synch\n
+ * false means SWOCTRL register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_SWOC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the INVCTRL register PWM synchronization mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means INVCTRL register is updated by PWM synch\n
+ * false means INVCTRL register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_INVC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the CNTIN register PWM synchronization mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param enable true means CNTIN register is updated by PWM synch\n
+ * false means CNTIN register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetCntinPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
+{
+ BW_FTM_SYNCONF_CNTINC(ftmBaseAddr, enable ? 1 : 0);
+}
+
+
+/*HAL functionality*/
+/*!
+ * @brief Resets the FTM registers
+ *
+ * @param instance The FTM instance number
+ * @param ftmBaseAddr The FTM base address
+ */
+void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance);
+
+/*!
+ * @brief Initializes the FTM.
+ *
+ * @param ftmBaseAddr The FTM base address.
+ */
+void FTM_HAL_Init(uint32_t ftmBaseAddr);
+
+/*Initializes the 5 FTM operating mode, input capture, output compare, PWM output(edge aligned, center-aligned, conbine), dual and quadrature).*/
+
+/*void FTM_HAL_input_capture_mode(uint32_t ftmBaseAddr);*/
+/*void FTM_HAL_output_compare_mode(uint32_t ftmBaseAddr);*/
+
+/*!
+ * @brief Enables the FTM timer when it is PWM output mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param config PWM configuration parameter
+ * @param channel The channel or channel pair number(combined mode).
+ */
+void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
+
+/*!
+ * @brief Disables the PWM output mode.
+ *
+ * @param ftmBaseAddr The FTM base address
+ * @param config PWM configuration parameter
+ * @param channel The channel or channel pair number(combined mode).
+ */
+void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
+
+/*void FTM_HAL_dual_mode(uint32_t ftmBaseAddr);*/
+/*void FTM_HAL_quad_mode(uint32_t ftmBaseAddr);*/
+
+
+/*void FTM_HAL_set_counting_mode(); //up, up down or free running counting mode*/
+/*void FTM_HAL_set_deadtime(uint32_t ftmBaseAddr, uint_32 us);*/
+
+/*! @}*/
+
+#endif /* __FSL_FTM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,188 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_GPIO_FEATURES_H__) +#define __FSL_GPIO_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \ + defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ + defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ + defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (0) : (-1)))))) +#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (0) : (-1)))))) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (0) : (-1)))))) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ + #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) + /* @brief Has port input disable register (PIDR). */ + #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) + /* @brief Has dedicated interrupt vector. */ + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1) + #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_GPIO_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_HAL_SetPinDir
+ * Description : Set individual gpio pin to general input or output.
+ *
+ *END**************************************************************************/
+void GPIO_HAL_SetPinDir(uint32_t baseAddr, uint32_t pin, gpio_pin_direction_t direction)
+{
+ assert(pin < 32);
+
+ if (direction == kGpioDigitalOutput)
+ {
+ HW_GPIO_PDDR_SET(baseAddr, 1U << pin);
+ }
+ else
+ {
+ HW_GPIO_PDDR_CLR(baseAddr, 1U << pin);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_HAL_WritePinOutput
+ * Description : Set output level of individual gpio pin to logic 1 or 0.
+ *
+ *END**************************************************************************/
+void GPIO_HAL_WritePinOutput(uint32_t baseAddr, uint32_t pin, uint32_t output)
+{
+ assert(pin < 32);
+ if (output != 0U)
+ {
+ HW_GPIO_PSOR_WR(baseAddr, 1U << pin); /* Set pin output to high level.*/
+ }
+ else
+ {
+ HW_GPIO_PCOR_WR(baseAddr, 1U << pin); /* Set pin output to low level.*/
+ }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_GPIO_HAL_H__
+#define __FSL_GPIO_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_gpio_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup gpio_hal
+ * @{
+ */
+
+/*!
+ * @file fsl_gpio_hal.h
+ *
+ * @brief GPIO hardware driver configuration. Use these functions to set the GPIO input/output,
+ * set output logic or get input logic. Check the GPIO header file for base address. Each
+ * GPIO instance has 32 pins with numbers from 0 to 31.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief GPIO direction definition*/
+typedef enum _gpio_pin_direction {
+ kGpioDigitalInput = 0, /*!< Set current pin as digital input*/
+ kGpioDigitalOutput = 1 /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Sets the individual GPIO pin to general input or output.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ * @param direction GPIO directions
+ * - kGpioDigitalInput: set to input
+ * - kGpioDigitalOutput: set to output
+ */
+void GPIO_HAL_SetPinDir(uint32_t baseAddr, uint32_t pin,
+ gpio_pin_direction_t direction);
+
+/*!
+ * @brief Sets the GPIO port pins to general input or output.
+ *
+ * This function operates all 32 port pins.
+ *
+ * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param direction GPIO directions
+ * - 0: set to input
+ * - 1: set to output
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline void GPIO_HAL_SetPortDir(uint32_t baseAddr, uint32_t direction)
+{
+ HW_GPIO_PDDR_WR(baseAddr, direction);
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the current direction of the individual GPIO pin.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ * @return GPIO directions
+ * - kGpioDigitalInput: corresponding pin is set to input.
+ * - kGpioDigitalOutput: corresponding pin is set to output.
+ */
+static inline gpio_pin_direction_t GPIO_HAL_GetPinDir(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ return (gpio_pin_direction_t)((HW_GPIO_PDDR_RD(baseAddr) >> pin) & 1U);
+}
+
+/*!
+ * @brief Gets the GPIO port pins direction.
+ *
+ * This function gets all 32-pin directions as a 32-bit integer.
+ *
+ * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @return GPIO directions. Each bit represents one pin. For each bit:
+ * - 0: corresponding pin is set to input
+ * - 1: corresponding pin is set to output
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_GetPortDir(uint32_t baseAddr)
+{
+ return HW_GPIO_PDDR_RD(baseAddr);
+}
+
+/* @} */
+
+/*!
+ * @name Output Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ * @param output pin output logic level
+ */
+void GPIO_HAL_WritePinOutput(uint32_t baseAddr, uint32_t pin, uint32_t output);
+
+/*!
+ * @brief Reads the current pin output.
+ *
+ * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ * @return current pin output status. 0 - Low logic, 1 - High logic
+ */
+static inline uint32_t GPIO_HAL_ReadPinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ return ((HW_GPIO_PDOR_RD(baseAddr) >> pin) & 0x1U);
+}
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to logic 1.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ */
+static inline void GPIO_HAL_SetPinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_GPIO_PSOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Clears the output level of the individual GPIO pin to logic 0.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ */
+static inline void GPIO_HAL_ClearPinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_GPIO_PCOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Reverses the current output logic of the individual GPIO pin.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ */
+static inline void GPIO_HAL_TogglePinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_GPIO_PTOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Sets the output of the GPIO port to a specific logic value.
+ *
+ * This function operates all 32 port pins.
+ *
+ * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit:
+ * - 0: set logic level 0 to pin
+ * - 1: set logic level 1 to pin
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline void GPIO_HAL_WritePortOutput(uint32_t baseAddr, uint32_t portOutput)
+{
+ HW_GPIO_PDOR_WR(baseAddr, portOutput);
+}
+
+/*!
+ * @brief Reads out all pin output status of the current port.
+ *
+ * This function operates all 32 port pins.
+ *
+ * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @return current port output status. Each bit represents one pin. For each bit:
+ * - 0: corresponding pin is outputting logic level 0
+ * - 1: corresponding pin is outputting logic level 1
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_ReadPortOutput(uint32_t baseAddr)
+{
+ return HW_GPIO_PDOR_RD(baseAddr);
+}
+
+/* @} */
+
+/*!
+ * @name Input Operation
+ * @{
+ */
+
+/*!
+ * @brief Reads the current input value of the individual GPIO pin.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @param pin GPIO port pin number
+ * @return GPIO port input value
+ * - 0: Pin logic level is 0, or is not configured for use by digital function.
+ * - 1: Pin logic level is 1
+ */
+static inline uint32_t GPIO_HAL_ReadPinInput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ return (HW_GPIO_PDIR_RD(baseAddr) >> pin) & 1U;
+}
+
+/*!
+ * @brief Reads the current input value of a specific GPIO port.
+ *
+ * This function gets all 32-pin input as a 32-bit integer.
+ *
+ * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.)
+ * @return GPIO port input data. Each bit represents one pin. For each bit:
+ * - 0: Pin logic level is 0, or is not configured for use by digital function.
+ * - 1: Pin logic level is 1.
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_ReadPortInput(uint32_t baseAddr)
+{
+ return HW_GPIO_PDIR_RD(baseAddr);
+}
+
+/* @} */
+
+/*!
+ * @name FGPIO Operation
+ *
+ * @note FGPIO (Fast GPIO) is only available in a few MCUs. FGPIO and GPIO share the same
+ * peripheral but use different registers. FGPIO is closer to the core than the regular GPIO
+ * and it's faster to read and write.
+ * @{
+ */
+
+#if FSL_FEATURE_GPIO_HAS_FAST_GPIO
+
+/*!
+ * @name Output Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of an individual FGPIO pin to logic 1.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.)
+ * @param pin FGPIO port pin number
+ */
+static inline void FGPIO_HAL_SetPinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_FGPIO_PSOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Clears the output level of an individual FGPIO pin to logic 0.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.)
+ * @param pin FGPIO port pin number
+ */
+static inline void FGPIO_HAL_ClearPinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_FGPIO_PCOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Reverses the current output logic of an individual FGPIO pin.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.)
+ * @param pin FGPIO port pin number
+ */
+static inline void FGPIO_HAL_TogglePinOutput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ HW_FGPIO_PTOR_WR(baseAddr, 1U << pin);
+}
+
+/*!
+ * @brief Sets the output of the FGPIO port to a specific logic value.
+ *
+ * This function affects all 32 port pins.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.)
+ * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit:
+ * - 0: set logic level 0 to pin.
+ * - 1: set logic level 1 to pin.
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline void FGPIO_HAL_WritePortOutput(uint32_t baseAddr, uint32_t portOutput)
+{
+ HW_FGPIO_PDOR_WR(baseAddr, portOutput);
+}
+
+/* @} */
+
+/*!
+ * @name Input Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the current input value of an individual FGPIO pin.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.)
+ * @param pin FGPIO port pin number
+ * @return FGPIO port input data
+ * - 0: Pin logic level is 0, or is not configured for use by digital function.
+ * - 1: Pin logic level is 1.
+ */
+static inline uint32_t FGPIO_HAL_ReadPinInput(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32);
+ return (HW_FGPIO_PDIR_RD(baseAddr) >> pin) & 1U;
+}
+
+/*!
+ * @brief Gets the current input value of a specific FGPIO port.
+ *
+ * This function gets all 32-pin input as a 32-bit integer.
+ *
+ * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.).
+ * @return FGPIO port input data. Each bit represents one pin. For each bit:
+ * - 0: Pin logic level is 0, or is not configured for use by digital function.
+ * - 1: Pin logic level is 1.
+ * - LSB: pin 0
+ * - MSB: pin 31
+ */
+static inline uint32_t FGPIO_HAL_ReadPortInput(uint32_t baseAddr)
+{
+ return HW_FGPIO_PDIR_RD(baseAddr);
+}
+
+/* @} */
+
+#endif /* FSL_FEATURE_GPIO_HAS_FAST_GPIO*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_GPIO_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,283 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_I2C_FEATURES_H__) +#define __FSL_I2C_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \ + defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \ + defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ + defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (1) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (0) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#elif defined(CPU_MK24FN256VDC12) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (1) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (0) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (1) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (0) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (0) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (1) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (0) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) + /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ + #define FSL_FEATURE_I2C_HAS_SMBUS (1) + /* @brief Maximum supported baud rate in kilobit per second. */ + #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) + /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ + #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) + /* @brief Has DMA support (register bit C1[DMAEN]). */ + #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) + /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ + #define FSL_FEATURE_I2C_HAS_START_DETECT (0) + /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ + #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) + /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ + #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) + /* @brief Maximum width of the glitch filter in number of bus clocks. */ + #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) + /* @brief Has control of the drive capability of the I2C pins. */ + #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) + /* @brief Has double buffering support (register S2). */ + #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_I2C_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_hal.h"
+#include "fsl_misc_utilities.h" /* For ARRAY_SIZE*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief An entry in the I2C divider table.
+ *
+ * This struct pairs the value of the I2C_F.ICR bitfield with the resulting
+ * clock divider value.
+ */
+typedef struct I2CDividerTableEntry {
+ uint8_t icr; /*!< F register ICR value.*/
+ uint16_t sclDivider; /*!< SCL clock divider.*/
+} i2c_divider_table_entry_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*!
+ * @brief I2C divider values.
+ *
+ * This table is taken from the I2C Divider and Hold values section of the
+ * reference manual. In the original table there are, in some cases, multiple
+ * entries with the same divider but different hold values. This table
+ * includes only one entry for every divider, selecting the lowest hold value.
+ */
+const i2c_divider_table_entry_t kI2CDividerTable[] = {
+ /* ICR Divider*/
+ { 0x00, 20 },
+ { 0x01, 22 },
+ { 0x02, 24 },
+ { 0x03, 26 },
+ { 0x04, 28 },
+ { 0x05, 30 },
+ { 0x09, 32 },
+ { 0x06, 34 },
+ { 0x0a, 36 },
+ { 0x07, 40 },
+ { 0x0c, 44 },
+ { 0x0d, 48 },
+ { 0x0e, 56 },
+ { 0x12, 64 },
+ { 0x0f, 68 },
+ { 0x13, 72 },
+ { 0x14, 80 },
+ { 0x15, 88 },
+ { 0x19, 96 },
+ { 0x16, 104 },
+ { 0x1a, 112 },
+ { 0x17, 128 },
+ { 0x1c, 144 },
+ { 0x1d, 160 },
+ { 0x1e, 192 },
+ { 0x22, 224 },
+ { 0x1f, 240 },
+ { 0x23, 256 },
+ { 0x24, 288 },
+ { 0x25, 320 },
+ { 0x26, 384 },
+ { 0x2a, 448 },
+ { 0x27, 480 },
+ { 0x2b, 512 },
+ { 0x2c, 576 },
+ { 0x2d, 640 },
+ { 0x2e, 768 },
+ { 0x32, 896 },
+ { 0x2f, 960 },
+ { 0x33, 1024 },
+ { 0x34, 1152 },
+ { 0x35, 1280 },
+ { 0x36, 1536 },
+ { 0x3a, 1792 },
+ { 0x37, 1920 },
+ { 0x3b, 2048 },
+ { 0x3c, 2304 },
+ { 0x3d, 2560 },
+ { 0x3e, 3072 },
+ { 0x3f, 3840 }
+ };
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_Init
+ * Description : Initialize I2C peripheral to reset state.
+ *
+ *END**************************************************************************/
+void I2C_HAL_Init(uint32_t baseAddr)
+{
+
+ HW_I2C_A1_WR(baseAddr, 0u);
+ HW_I2C_F_WR(baseAddr, 0u);
+ HW_I2C_C1_WR(baseAddr, 0u);
+ HW_I2C_S_WR(baseAddr, 0u);
+ HW_I2C_D_WR(baseAddr, 0u);
+ HW_I2C_C2_WR(baseAddr, 0u);
+ HW_I2C_FLT_WR(baseAddr, 0u);
+ HW_I2C_RA_WR(baseAddr, 0u);
+
+#if FSL_FEATURE_I2C_HAS_SMBUS
+ HW_I2C_SMB_WR(baseAddr, 0u);
+ HW_I2C_A2_WR(baseAddr, 0xc2u);
+ HW_I2C_SLTH_WR(baseAddr, 0u);
+ HW_I2C_SLTL_WR(baseAddr, 0u);
+#endif /* FSL_FEATURE_I2C_HAS_SMBUS*/
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetBaudRate
+ * Description : Sets the I2C bus frequency for master transactions.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps,
+ uint32_t * absoluteError_Hz)
+{
+ uint32_t mult, i, multiplier;
+ uint32_t hz = kbps * 1000u;
+ uint32_t bestError = 0xffffffffu;
+ uint32_t bestMult = 0u;
+ uint32_t bestIcr = 0u;
+
+ /* Check if the requested frequency is greater than the max supported baud.*/
+ if ((kbps * 1000U) > (sourceClockInHz / (1U * 20U)))
+ {
+ return kStatus_I2C_OutOfRange;
+ }
+
+ /* Search for the settings with the lowest error.
+ * mult is the MULT field of the I2C_F register, and ranges from 0-2. It selects the
+ * multiplier factor for the divider. */
+ for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
+ {
+ multiplier = 1u << mult;
+
+ /* Scan table to find best match.*/
+ for (i = 0u; i < ARRAY_SIZE(kI2CDividerTable); ++i)
+ {
+ uint32_t computedRate = sourceClockInHz / (multiplier * kI2CDividerTable[i].sclDivider);
+ uint32_t absError = hz > computedRate ? hz - computedRate : computedRate - hz;
+
+ if (absError < bestError)
+ {
+ bestMult = mult;
+ bestIcr = kI2CDividerTable[i].icr;
+ bestError = absError;
+
+ /* If the error is 0, then we can stop searching
+ * because we won't find a better match.*/
+ if (absError == 0)
+ {
+ break;
+ }
+ }
+ }
+ }
+
+ /* Set the resulting error.*/
+ if (absoluteError_Hz)
+ {
+ *absoluteError_Hz = bestError;
+ }
+
+ /* Set frequency register based on best settings.*/
+ HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(bestMult) | BF_I2C_F_ICR(bestIcr));
+
+ return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SendStart
+ * Description : Send a START or Repeated START signal on the I2C bus.
+ * This function is used to initiate a new master mode transfer by sending the
+ * START signal. It is also used to send a Repeated START signal when a transfer
+ * is already in progress.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SendStart(uint32_t baseAddr)
+{
+ /* Check if we're in a master mode transfer.*/
+ if (BR_I2C_C1_MST(baseAddr))
+ {
+#if FSL_FEATURE_I2C_HAS_ERRATA_6070
+ /* Errata 6070: Repeat start cannot be generated if the I2Cx_F[MULT] field is set to a
+ * non- zero value.
+ * The workaround is to either always keep MULT set to 0, or to temporarily set it to
+ * 0 while performing the repeated start and then restore it.*/
+ uint32_t savedMult = 0;
+ if (BR_I2C_F_MULT(baseAddr) != 0)
+ {
+ savedMult = BR_I2C_F_MULT(baseAddr);
+ BW_I2C_F_MULT(baseAddr, 0U);
+ }
+#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/
+
+ /* We are already in a transfer, so send a repeated start.*/
+ BW_I2C_C1_RSTA(baseAddr, 1U);
+
+#if FSL_FEATURE_I2C_HAS_ERRATA_6070
+ if (savedMult)
+ {
+ BW_I2C_F_MULT(baseAddr, savedMult);
+ }
+#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/
+ }
+ else
+ {
+ /* Initiate a transfer by sending the start signal.*/
+ HW_I2C_C1_SET(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetAddress7bit
+ * Description : Sets the primary 7-bit slave address.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address)
+{
+ /* Set 7-bit slave address.*/
+ HW_I2C_A1_WR(baseAddr, address << 1U);
+
+ /* Disable the address extension option, selecting 7-bit mode.*/
+ BW_I2C_C2_ADEXT(baseAddr, 0U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetAddress10bit
+ * Description : Sets the primary slave address and enables 10-bit address mode.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address)
+{
+
+ uint8_t temp;
+
+ /* Set bottom 7 bits of slave address.*/
+ temp = address & 0x7FU;
+ HW_I2C_A1_WR(baseAddr, temp << 1U);
+
+ /* Enable 10-bit address extension.*/
+ BW_I2C_C2_ADEXT(baseAddr, 1U);
+
+ /* Set top 3 bits of slave address.*/
+ BW_I2C_C2_AD(baseAddr, (address & 0x0380U) >> 7U);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,702 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_I2C_HAL_H__)
+#define __FSL_I2C_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_i2c_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup i2c_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief I2C status return codes.*/
+typedef enum _i2c_status {
+ kStatus_I2C_Success = 0x0U,
+ kStatus_I2C_OutOfRange = 0x1U,
+ kStatus_I2C_Fail = 0x2U,
+ kStatus_I2C_Busy = 0x3U, /*!< The master is already performing a transfer.*/
+ kStatus_I2C_Timeout = 0x4U, /*!< The transfer timed out.*/
+ kStatus_I2C_ReceivedNak = 0x5U, /*!< The slave device sent a NAK in response to a byte.*/
+ kStatus_I2C_SlaveTxUnderrun = 0x6U, /*!< I2C Slave TX Underrun error.*/
+ kStatus_I2C_SlaveRxOverrun = 0x7U, /*!< I2C Slave RX Overrun error.*/
+ kStatus_I2C_AribtrationLost = 0x8U, /*!< I2C Arbitration Lost error.*/
+} i2c_status_t;
+
+/*! @brief I2C status flags. */
+typedef enum _i2c_status_flag {
+ kI2CTransferComplete = BP_I2C_S_TCF,
+ kI2CAddressAsSlave = BP_I2C_S_IAAS,
+ kI2CBusBusy = BP_I2C_S_BUSY,
+ kI2CArbitrationLost = BP_I2C_S_ARBL,
+ kI2CAddressMatch = BP_I2C_S_RAM,
+ kI2CSlaveTransmit = BP_I2C_S_SRW,
+ kI2CInterruptPending = BP_I2C_S_IICIF,
+ kI2CReceivedNak = BP_I2C_S_RXAK
+} i2c_status_flag_t;
+
+/*! @brief Direction of master and slave transfers.*/
+typedef enum _i2c_direction {
+ kI2CReceive = 0U, /*!< Master and slave receive.*/
+ kI2CSend = 1U /*!< Master and slave transmit.*/
+} i2c_direction_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Module controls
+ * @{
+ */
+
+/*!
+ * @brief Restores the I2C peripheral to reset state.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+void I2C_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Enables the I2C module operation.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_Enable(uint32_t baseAddr)
+{
+ BW_I2C_C1_IICEN(baseAddr, 0x1U);
+}
+
+/*!
+ * @brief Disables the I2C module operation.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_Disable(uint32_t baseAddr)
+{
+ BW_I2C_C1_IICEN(baseAddr, 0x0U);
+}
+
+/*@}*/
+
+/*!
+ * @name DMA
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the DMA support.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable Pass true to enable DMA transfer signalling
+ */
+static inline void I2C_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C1_DMAEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether I2C DMA support is enabled.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @retval true I2C DMA is enabled.
+ * @retval false I2C DMA is disabled.
+ */
+static inline bool I2C_HAL_GetDmaCmd(uint32_t baseAddr)
+{
+ return BR_I2C_C1_DMAEN(baseAddr);
+}
+
+/*@}*/
+
+/*!
+ * @name Pin functions
+ * @{
+ */
+
+/*!
+ * @brief Controls the drive capability of the I2C pads.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal
+ * drive mode.
+ */
+static inline void I2C_HAL_SetHighDriveCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C2_HDRS(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Controls the width of the programmable glitch filter.
+ *
+ * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb.
+ * The filter does not allow any glitch whose size is less than or equal to this width setting,
+ * to pass.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered.
+ * Pass zero to disable the glitch filter.
+ */
+static inline void I2C_HAL_SetGlitchWidth(uint32_t baseAddr, uint8_t glitchWidth)
+{
+ BW_I2C_FLT_FLT(baseAddr, glitchWidth);
+}
+
+/*@}*/
+
+/*!
+ * @name Low power
+ * @{
+ */
+
+/*!
+ * @brief Controls the I2C wakeup enable.
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus running when
+ * slave address matching occurs.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @param enable true - Enables the wakeup function in low power mode.<br>
+ * false - Normal operation. No interrupt is generated when address matching in
+ * low power mode.
+ */
+static inline void I2C_HAL_SetWakeupCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C1_WUEN(baseAddr, (uint8_t)enable);
+}
+
+#if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+/*!
+ * @brief Controls the stop mode hold off.
+ *
+ * This function lets you enable the hold off entry to low power stop mode when any data transmission
+ * or reception is occurring.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.<br>
+ * true - Stop hold off is enabled.
+ */
+
+static inline void I2C_HAL_SetStopHoldoffCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_FLT_SHEN(baseAddr, (uint8_t)enable);
+}
+#endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/
+
+/*@}*/
+
+/*!
+ * @name Baud rate
+ * @{
+ */
+
+/*!
+ * @brief Sets the I2C bus frequency for master transactions.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param sourceClockInHz I2C source input clock in Hertz
+ * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400.
+ * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the
+ * difference in Hertz between the requested bus frequency and the closest frequency
+ * possible given available divider values.
+ *
+ * @retval kStatus_Success The baud rate was changed successfully. However, there is no
+ * guarantee on the minimum error. If you want to ensure that the baud was set to within
+ * a certain error, then use the @a absoluteError_Hz parameter.
+ * @retval kStatus_OutOfRange The requested baud rate was not within the range of rates
+ * supported by the peripheral.
+ */
+i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps,
+ uint32_t * absoluteError_Hz);
+
+/*!
+ * @brief Sets the I2C baud rate multiplier and table entry.
+ *
+ * Use this function to set the I2C bus frequency register values directly, if they are
+ * known in advance.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param mult Value of the MULT bitfield, ranging from 0-2.
+ * @param icr The ICR bitfield value, which is the index into an internal table in the I2C
+ * hardware that selects the baud rate divisor and SCL hold time.
+ */
+static inline void I2C_HAL_SetFreqDiv(uint32_t baseAddr, uint8_t mult, uint8_t icr)
+{
+ HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(mult) | BF_I2C_F_ICR(icr));
+}
+
+/*!
+ * @brief Slave baud rate control
+ *
+ * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching
+ * on the SCL in very fast I2C modes.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable true - Slave baud rate is independent of the master baud rate;<br>
+ * false - The slave baud rate follows the master baud rate and clock stretching may occur.
+ */
+static inline void I2C_HAL_SetSlaveBaudCtrlCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C2_SBRC(baseAddr, (uint8_t)enable);
+}
+
+/*@}*/
+
+/*!
+ * @name Bus operations
+ * @{
+ */
+
+/*!
+ * @brief Sends a START or a Repeated START signal on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal. It
+ * is also used to send a Repeated START signal when a transfer is already in progress.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+void I2C_HAL_SendStart(uint32_t baseAddr);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * This function changes the direction to receive.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_SendStop(uint32_t baseAddr)
+{
+ assert(BR_I2C_C1_MST(baseAddr) == 1);
+ HW_I2C_C1_CLR(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX);
+}
+
+/*!
+ * @brief Causes an ACK to be sent on the bus.
+ *
+ * This function specifies that an ACK signal is sent in response to the next received byte.
+ *
+ * Note that the behavior of this function is changed when the I2C peripheral is placed in
+ * Fast ACK mode. In this case, this function causes an ACK signal to be sent in
+ * response to the current byte, rather than the next received byte.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_SendAck(uint32_t baseAddr)
+{
+ BW_I2C_C1_TXAK(baseAddr, 0x0U);
+}
+
+/*!
+ * @brief Causes a NAK to be sent on the bus.
+ *
+ * This function specifies that a NAK signal is sent in response to the next received byte.
+ *
+ * Note that the behavior of this function is changed when the I2C peripheral is placed in the
+ * Fast ACK mode. In this case, this function causes an NAK signal to be sent in
+ * response to the current byte, rather than the next received byte.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_SendNak(uint32_t baseAddr)
+{
+ BW_I2C_C1_TXAK(baseAddr, 0x1U);
+}
+
+/*!
+ * @brief Selects either transmit or receive mode.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @param direction Specifies either transmit mode or receive mode. The valid values are:
+ * - #kI2CTransmit
+ * - #kI2CReceive
+ */
+static inline void I2C_HAL_SetDirMode(uint32_t baseAddr, i2c_direction_t direction)
+{
+ BW_I2C_C1_TX(baseAddr, (uint8_t)direction);
+}
+
+/*!
+ * @brief Returns the currently selected transmit or receive mode.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @retval #kI2CTransmit I2C is configured for master or slave transmit mode.
+ * @retval #kI2CReceive I2C is configured for master or slave receive mode.
+ */
+static inline i2c_direction_t I2C_HAL_GetDirMode(uint32_t baseAddr)
+{
+ return (i2c_direction_t)BR_I2C_C1_TX(baseAddr);
+}
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Returns the last byte of data read from the bus and initiate another read.
+ *
+ * In a master receive mode, calling this function initiates receiving the next byte of data.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @return This function returns the last byte received while the I2C module is configured in master
+ * receive or slave receive mode.
+ */
+static inline uint8_t I2C_HAL_ReadByte(uint32_t baseAddr)
+{
+ return HW_I2C_D_RD(baseAddr);
+}
+
+/*!
+ * @brief Writes one byte of data to the I2C bus.
+ *
+ * When this function is called in the master transmit mode, a data transfer is initiated. In slave
+ * mode, the same function is available after an address match occurs.
+ *
+ * In a master transmit mode, the first byte of data written following the start bit or repeated
+ * start bit is used for the address transfer and must consist of the slave address (in bits 7-1)
+ * concatenated with the required R/\#W bit (in position bit 0).
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @param byte The byte of data to transmit.
+ */
+static inline void I2C_HAL_WriteByte(uint32_t baseAddr, uint8_t byte)
+{
+ HW_I2C_D_WR(baseAddr, byte);
+}
+
+/*@}*/
+
+/*!
+ * @name Slave address
+ * @{
+ */
+
+/*!
+ * @brief Sets the primary 7-bit slave address.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0.
+ */
+void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address);
+
+/*!
+ * @brief Sets the primary slave address and enables 10-bit address mode.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0.
+ */
+void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address);
+
+/*!
+ * @brief Enables or disables the extension address (10-bit).
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable true: 10-bit address is enabled.
+ * false: 10-bit address is not enabled.
+ */
+static inline void I2C_HAL_SetExtensionAddrCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C2_ADEXT(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the extension address is enabled or not.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @return true: 10-bit address is enabled.
+ * false: 10-bit address is not enabled.
+ */
+static inline bool I2C_HAL_GetExtensionAddrCmd(uint32_t baseAddr)
+{
+ return BR_I2C_C2_ADEXT(baseAddr);
+}
+
+/*!
+ * @brief Controls whether the general call address is recognized.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable Whether to enable the general call address.
+ */
+static inline void I2C_HAL_SetGeneralCallCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C2_GCAEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Enables or disables the slave address range matching.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @param enable Pass true to enable range address matching. You must also call
+ * I2C_HAL_SetUpperAddress7bit() to set the upper address.
+ */
+static inline void I2C_HAL_SetRangeMatchCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C2_RMEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Sets the upper slave address.
+ *
+ * This slave address is used as a secondary slave address. If range address
+ * matching is enabled, this slave address acts as the upper bound on the slave address
+ * range.
+ *
+ * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling
+ * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used
+ * with the address set with this function to form a 10-bit address.
+ *
+ * Passing 0 for the @a address parameter disables matching the upper slave address.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0.
+ * In addition, this address must be greater than the primary slave address that is set by
+ * calling I2C_HAL_SetAddress7bit().
+ */
+static inline void I2C_HAL_SetUpperAddress7bit(uint32_t baseAddr, uint8_t address)
+{
+ assert((address & 1) == 0);
+ assert((address == 0) || (address > HW_I2C_A1_RD(baseAddr)));
+ HW_I2C_RA_WR(baseAddr, address);
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the I2C status flag state.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @param statusFlag The status flag, defined in type i2c_status_flag_t.
+ * @return State of the status flag: asserted (true) or not-asserted (false).
+ * - true: related status flag is being set.
+ * - false: related status flag is not set.
+ */
+static inline bool I2C_HAL_GetStatusFlag(uint32_t baseAddr, i2c_status_flag_t statusFlag)
+{
+ return (bool)((HW_I2C_S_RD(baseAddr) >> statusFlag) & 0x1U);
+}
+
+/*!
+ * @brief Returns whether the I2C module is in master mode.
+ *
+ * @param baseAddr The I2C peripheral base address.
+ * @retval true The module is in master mode, which implies it is also performing a transfer.
+ * @retval false The module is in slave mode.
+ */
+static inline bool I2C_HAL_IsMaster(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_C1_MST(baseAddr);
+}
+
+/*!
+ * @brief Clears the arbitration lost flag.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_ClearArbitrationLost(uint32_t baseAddr)
+{
+ BW_I2C_S_ARBL(baseAddr, 0x1U);
+}
+
+/*@}*/
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables I2C interrupt requests.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable Pass true to enable interrupt, flase to disable.
+ */
+static inline void I2C_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_C1_IICIE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the I2C interrupts are enabled.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @retval true I2C interrupts are enabled.
+ * @retval false I2C interrupts are disabled.
+ */
+static inline bool I2C_HAL_GetIntCmd(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_C1_IICIE(baseAddr);
+}
+
+/*!
+ * @brief Returns the current I2C interrupt flag.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @retval true An interrupt is pending.
+ * @retval false No interrupt is pending.
+ */
+static inline bool I2C_HAL_IsIntPending(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_S_IICIF(baseAddr);
+}
+
+/*!
+ * @brief Clears the I2C interrupt if set.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_ClearInt(uint32_t baseAddr)
+{
+ BW_I2C_S_IICIF(baseAddr, 0x1U);
+}
+
+/*@}*/
+
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+
+/*!
+ * @name Bus stop detection status
+ * @{
+ */
+
+/*!
+ * @brief Gets the flag indicating a STOP signal was detected on the I2C bus.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @retval true STOP signal detected on bus.
+ * @retval false No STOP signal was detected on the bus.
+ */
+static inline bool I2C_HAL_GetStopFlag(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_FLT_STOPF(baseAddr);
+}
+
+/*!
+ * @brief Clears the bus STOP signal detected flag.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_ClearStopFlag(uint32_t baseAddr)
+{
+ BW_I2C_FLT_STOPF(baseAddr, 0x1U);
+}
+
+/*@}*/
+
+#if FSL_FEATURE_I2C_HAS_START_DETECT
+
+/*!
+ * @name Bus stop detection interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables the I2C bus stop detection interrupt.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @param enable Pass true to enable interrupt, flase to disable.
+ */
+static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_FLT_SSIE(baseAddr, enable);
+}
+
+/*!
+ * @brief Returns whether the I2C bus stop detection interrupts are enabled.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @retval true Stop detect interrupts are enabled.
+ * @retval false Stop detect interrupts are disabled.
+ */
+static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_FLT_SSIE(baseAddr);
+}
+
+#else
+
+/*! @name Bus stop detection interrupt*/
+/*@{*/
+
+/*!
+ * @brief Enables the I2C bus stop detection interrupt.
+ *
+ * @param baseAddr The I2C peripheral base address
+ */
+static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_I2C_FLT_STOPIE(baseAddr, enable);
+}
+
+/*!
+ * @brief Returns whether the I2C bus stop detection interrupts are enabled.
+ *
+ * @param baseAddr The I2C peripheral base address
+ * @retval true Stop detect interrupts are enabled.
+ * @retval false Stop detect interrupts are disabled.
+ */
+static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
+{
+ return (bool)BR_I2C_FLT_STOPIE(baseAddr);
+}
+
+#endif /* FSL_FEATURE_I2C_HAS_START_DETECT*/
+
+/*@}*/
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_I2C_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,153 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_LLWU_FEATURES_H__) +#define __FSL_LLWU_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ + defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ + defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ + defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ + defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \ + defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (0) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (1) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_LLWU_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_llwu_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetExternalInputPinMode
+ * Description : Set external input pin source mode
+ * This function will set the external input pin source mode that will be used
+ * as wake up source.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_SetExternalInputPinMode(uint32_t baseAddr,
+ llwu_external_pin_modes_t pinMode,
+ uint32_t pinNumber)
+{
+ /* check pin number */
+ assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ switch (pinNumber)
+ {
+ case 0:
+ BW_LLWU_PE1_WUPE0(baseAddr, pinMode);
+ break;
+ case 1:
+ BW_LLWU_PE1_WUPE1(baseAddr, pinMode);
+ break;
+ case 2:
+ BW_LLWU_PE1_WUPE2(baseAddr, pinMode);
+ break;
+ case 3:
+ BW_LLWU_PE1_WUPE3(baseAddr, pinMode);
+ break;
+ case 4:
+ BW_LLWU_PE2_WUPE4(baseAddr, pinMode);
+ break;
+ case 5:
+ BW_LLWU_PE2_WUPE5(baseAddr, pinMode);
+ break;
+ case 6:
+ BW_LLWU_PE2_WUPE6(baseAddr, pinMode);
+ break;
+ case 7:
+ BW_LLWU_PE2_WUPE7(baseAddr, pinMode);
+ break;
+ case 8:
+ BW_LLWU_PE3_WUPE8(baseAddr, pinMode);
+ break;
+ case 9:
+ BW_LLWU_PE3_WUPE9(baseAddr, pinMode);
+ break;
+ case 10:
+ BW_LLWU_PE3_WUPE10(baseAddr, pinMode);
+ break;
+ case 11:
+ BW_LLWU_PE3_WUPE11(baseAddr, pinMode);
+ break;
+ case 12:
+ BW_LLWU_PE4_WUPE12(baseAddr, pinMode);
+ break;
+ case 13:
+ BW_LLWU_PE4_WUPE13(baseAddr, pinMode);
+ break;
+ case 14:
+ BW_LLWU_PE4_WUPE14(baseAddr, pinMode);
+ break;
+ case 15:
+ BW_LLWU_PE4_WUPE15(baseAddr, pinMode);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetExternalInputPinMode
+ * Description : Get external input pin source mode
+ * This function will get the external input pin source mode that will be used
+ * as wake up source.
+ *
+ *END**************************************************************************/
+llwu_external_pin_modes_t LLWU_HAL_GetExternalInputPinMode(uint32_t baseAddr,
+ uint32_t pinNumber)
+{
+ llwu_external_pin_modes_t retValue = (llwu_external_pin_modes_t)0;
+
+ /* check pin number */
+ assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ switch (pinNumber)
+ {
+ case 0:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE0(baseAddr);
+ break;
+ case 1:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE1(baseAddr);
+ break;
+ case 2:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE2(baseAddr);
+ break;
+ case 3:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE3(baseAddr);
+ break;
+ case 4:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE4(baseAddr);
+ break;
+ case 5:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE5(baseAddr);
+ break;
+ case 6:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE6(baseAddr);
+ break;
+ case 7:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE7(baseAddr);
+ break;
+ case 8:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE8(baseAddr);
+ break;
+ case 9:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE9(baseAddr);
+ break;
+ case 10:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE10(baseAddr);
+ break;
+ case 11:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE11(baseAddr);
+ break;
+ case 12:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE12(baseAddr);
+ break;
+ case 13:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE13(baseAddr);
+ break;
+ case 14:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE14(baseAddr);
+ break;
+ case 15:
+ retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE15(baseAddr);
+ break;
+ default:
+ retValue = (llwu_external_pin_modes_t)0;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetInternalModuleCmd
+ * Description : Enable/disable internal module source
+ * This function will enable/disable the internal module source mode that will
+ * be used as wake up source.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_SetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber, bool enable)
+{
+ /* check module number */
+ assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE);
+
+ switch (moduleNumber)
+ {
+ case 0:
+ BW_LLWU_ME_WUME0(baseAddr, enable);
+ break;
+ case 1:
+ BW_LLWU_ME_WUME1(baseAddr, enable);
+ break;
+ case 2:
+ BW_LLWU_ME_WUME2(baseAddr, enable);
+ break;
+ case 3:
+ BW_LLWU_ME_WUME3(baseAddr, enable);
+ break;
+ case 4:
+ BW_LLWU_ME_WUME4(baseAddr, enable);
+ break;
+ case 5:
+ BW_LLWU_ME_WUME5(baseAddr, enable);
+ break;
+ case 6:
+ BW_LLWU_ME_WUME6(baseAddr, enable);
+ break;
+ case 7:
+ BW_LLWU_ME_WUME7(baseAddr, enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetInternalModuleCmd
+ * Description : Get internal module source enable setting
+ * This function will enable/disable the internal module source mode that will
+ * be used as wake up source.
+ *
+ *END**************************************************************************/
+bool LLWU_HAL_GetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber)
+{
+ bool retValue = false;
+
+ /* check module number */
+ assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE);
+
+ switch (moduleNumber)
+ {
+ case 0:
+ retValue = (bool)BR_LLWU_ME_WUME0(baseAddr);
+ break;
+ case 1:
+ retValue = (bool)BR_LLWU_ME_WUME1(baseAddr);
+ break;
+ case 2:
+ retValue = (bool)BR_LLWU_ME_WUME2(baseAddr);
+ break;
+ case 3:
+ retValue = (bool)BR_LLWU_ME_WUME3(baseAddr);
+ break;
+ case 4:
+ retValue = (bool)BR_LLWU_ME_WUME4(baseAddr);
+ break;
+ case 5:
+ retValue = (bool)BR_LLWU_ME_WUME5(baseAddr);
+ break;
+ case 6:
+ retValue = (bool)BR_LLWU_ME_WUME6(baseAddr);
+ break;
+ case 7:
+ retValue = (bool)BR_LLWU_ME_WUME7(baseAddr);
+ break;
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetExternalPinWakeupFlag
+ * Description : Get external wakeup source flag
+ * This function will get the external wakeup source flag for specific pin.
+ *
+ *END**************************************************************************/
+bool LLWU_HAL_GetExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber)
+{
+ bool retValue = false;
+
+ /* check pin number */
+ assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ switch (pinNumber)
+ {
+ case 0:
+ retValue = (bool)BR_LLWU_F1_WUF0(baseAddr);
+ break;
+ case 1:
+ retValue = (bool)BR_LLWU_F1_WUF1(baseAddr);
+ break;
+ case 2:
+ retValue = (bool)BR_LLWU_F1_WUF2(baseAddr);
+ break;
+ case 3:
+ retValue = (bool)BR_LLWU_F1_WUF3(baseAddr);
+ break;
+ case 4:
+ retValue = (bool)BR_LLWU_F1_WUF4(baseAddr);
+ break;
+ case 5:
+ retValue = (bool)BR_LLWU_F1_WUF5(baseAddr);
+ break;
+ case 6:
+ retValue = (bool)BR_LLWU_F1_WUF6(baseAddr);
+ break;
+ case 7:
+ retValue = (bool)BR_LLWU_F1_WUF7(baseAddr);
+ break;
+ case 8:
+ retValue = (bool)BR_LLWU_F2_WUF8(baseAddr);
+ break;
+ case 9:
+ retValue = (bool)BR_LLWU_F2_WUF9(baseAddr);
+ break;
+ case 10:
+ retValue = (bool)BR_LLWU_F2_WUF10(baseAddr);
+ break;
+ case 11:
+ retValue = (bool)BR_LLWU_F2_WUF11(baseAddr);
+ break;
+ case 12:
+ retValue = (bool)BR_LLWU_F2_WUF12(baseAddr);
+ break;
+ case 13:
+ retValue = (bool)BR_LLWU_F2_WUF13(baseAddr);
+ break;
+ case 14:
+ retValue = (bool)BR_LLWU_F2_WUF14(baseAddr);
+ break;
+ case 15:
+ retValue = (bool)BR_LLWU_F2_WUF15(baseAddr);
+ break;
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_ClearExternalPinWakeupFlag
+ * Description : Clear external wakeup source flag
+ * This function will clear the external wakeup source flag for specific pin.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_ClearExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber)
+{
+ /* check pin number */
+ assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ switch (pinNumber)
+ {
+ case 0:
+ BW_LLWU_F1_WUF0(baseAddr, 1);
+ break;
+ case 1:
+ BW_LLWU_F1_WUF1(baseAddr, 1);
+ break;
+ case 2:
+ BW_LLWU_F1_WUF2(baseAddr, 1);
+ break;
+ case 3:
+ BW_LLWU_F1_WUF3(baseAddr, 1);
+ break;
+ case 4:
+ BW_LLWU_F1_WUF4(baseAddr, 1);
+ break;
+ case 5:
+ BW_LLWU_F1_WUF5(baseAddr, 1);
+ break;
+ case 6:
+ BW_LLWU_F1_WUF6(baseAddr, 1);
+ break;
+ case 7:
+ BW_LLWU_F1_WUF7(baseAddr, 1);
+ break;
+ case 8:
+ BW_LLWU_F2_WUF8(baseAddr, 1);
+ break;
+ case 9:
+ BW_LLWU_F2_WUF9(baseAddr, 1);
+ break;
+ case 10:
+ BW_LLWU_F2_WUF10(baseAddr, 1);
+ break;
+ case 11:
+ BW_LLWU_F2_WUF11(baseAddr, 1);
+ break;
+ case 12:
+ BW_LLWU_F2_WUF12(baseAddr, 1);
+ break;
+ case 13:
+ BW_LLWU_F2_WUF13(baseAddr, 1);
+ break;
+ case 14:
+ BW_LLWU_F2_WUF14(baseAddr, 1);
+ break;
+ case 15:
+ BW_LLWU_F2_WUF15(baseAddr, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetInternalModuleWakeupFlag
+ * Description : Get internal module wakeup source flag
+ * This function will get the internal module wakeup source flag for specific
+ * module
+ *
+ *END**************************************************************************/
+bool LLWU_HAL_GetInternalModuleWakeupFlag(uint32_t baseAddr, uint32_t moduleNumber)
+{
+ bool retValue = false;
+
+ /* check module number */
+ assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE);
+
+ switch (moduleNumber)
+ {
+ case 0:
+ retValue = (bool)BR_LLWU_F3_MWUF0(baseAddr);
+ break;
+ case 1:
+ retValue = (bool)BR_LLWU_F3_MWUF1(baseAddr);
+ break;
+ case 2:
+ retValue = (bool)BR_LLWU_F3_MWUF2(baseAddr);
+ break;
+ case 3:
+ retValue = (bool)BR_LLWU_F3_MWUF3(baseAddr);
+ break;
+ case 4:
+ retValue = (bool)BR_LLWU_F3_MWUF4(baseAddr);
+ break;
+ case 5:
+ retValue = (bool)BR_LLWU_F3_MWUF5(baseAddr);
+ break;
+ case 6:
+ retValue = (bool)BR_LLWU_F3_MWUF6(baseAddr);
+ break;
+ case 7:
+ retValue = (bool)BR_LLWU_F3_MWUF7(baseAddr);
+ break;
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetPinFilterMode
+ * Description : Set pin filter configuration
+ * This function will set the pin filter configuration.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_SetPinFilterMode(uint32_t baseAddr,
+ uint32_t filterNumber,
+ llwu_external_pin_filter_mode_t pinFilterMode)
+{
+ /* check filter and pin number */
+ assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+ assert(pinFilterMode.pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ /* branch to filter number */
+ switch(filterNumber)
+ {
+ case 0:
+ BW_LLWU_FILT1_FILTSEL(baseAddr, pinFilterMode.pinNumber);
+ BW_LLWU_FILT1_FILTE(baseAddr, pinFilterMode.filterMode);
+ break;
+ case 1:
+ BW_LLWU_FILT2_FILTSEL(baseAddr, pinFilterMode.pinNumber);
+ BW_LLWU_FILT2_FILTE(baseAddr, pinFilterMode.filterMode);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetPinFilterMode
+ * Description : Get pin filter configuration.
+ * This function will get the pin filter configuration.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_GetPinFilterMode(uint32_t baseAddr,
+ uint32_t filterNumber,
+ llwu_external_pin_filter_mode_t *pinFilterMode)
+{
+ /* check filter and pin number */
+ assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+ assert(pinFilterMode->pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+
+ /* branch to filter number */
+ switch(filterNumber)
+ {
+ case 0:
+ pinFilterMode->pinNumber = BR_LLWU_FILT1_FILTSEL(baseAddr);
+ pinFilterMode->filterMode = (llwu_filter_modes_t)BR_LLWU_FILT1_FILTE(baseAddr);
+ break;
+ case 1:
+ pinFilterMode->pinNumber = BR_LLWU_FILT2_FILTSEL(baseAddr);
+ pinFilterMode->filterMode = (llwu_filter_modes_t)BR_LLWU_FILT2_FILTE(baseAddr);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetFilterDetectFlag
+ * Description : Get filter detect flag
+ * This function will get the filter detect flag.
+ *
+ *END**************************************************************************/
+bool LLWU_HAL_GetFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber)
+{
+ bool retValue = false;
+
+ /* check filter and pin number */
+ assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+
+ /* branch to filter number */
+ switch(filterNumber)
+ {
+ case 0:
+ retValue = (bool)BR_LLWU_FILT1_FILTF(baseAddr);
+ break;
+ case 1:
+ retValue = (bool)BR_LLWU_FILT2_FILTF(baseAddr);
+ break;
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_ClearFilterDetectFlag
+ * Description : Clear filter detect flag
+ * This function will clear the filter detect flag.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_ClearFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber)
+{
+ /* check filter and pin number */
+ assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+
+ /* branch to filter number */
+ switch(filterNumber)
+ {
+ case 0:
+ BW_LLWU_FILT1_FILTF(baseAddr, 1);
+ break;
+ case 1:
+ BW_LLWU_FILT2_FILTF(baseAddr, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetResetEnableMode
+ * Description : Set reset enable mode
+ * This function will set the reset enable mode.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_SetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t resetEnableMode)
+{
+ BW_LLWU_RST_RSTFILT(baseAddr, resetEnableMode.digitalFilterMode);
+ BW_LLWU_RST_LLRSTE(baseAddr, resetEnableMode.lowLeakageMode);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetResetEnableMode
+ * Description : Get reset enable mode
+ * This function will get the reset enable mode.
+ *
+ *END**************************************************************************/
+void LLWU_HAL_GetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t *resetEnableMode)
+{
+ resetEnableMode->digitalFilterMode = (bool)BR_LLWU_RST_RSTFILT(baseAddr);
+ resetEnableMode->lowLeakageMode = (bool)BR_LLWU_RST_LLRSTE(baseAddr);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_LLWU_HAL_H__)
+#define __FSL_LLWU_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_llwu_features.h"
+
+/*! @addtogroup llwu_hal*/
+/*! @{*/
+
+/*! @file fsl_llwu_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief External input pin control modes */
+typedef enum _llwu_external_pin_modes {
+ kLlwuExternalPinDisabled, /* pin disabled as wakeup input */
+ kLlwuExternalPinRisingEdge, /* pin enabled with rising edge detection */
+ kLlwuExternalPinFallingEdge, /* pin enabled with falling edge detection */
+ kLlwuExternalPinChangeDetect /* pin enabled with any change detection */
+} llwu_external_pin_modes_t;
+
+/*! @brief Digital filter control modes */
+typedef enum _llwu_filter_modes {
+ kLlwuFilterDisabled, /* filter disabled */
+ kLlwuFilterPosEdgeDetect, /* filter positive edge detection */
+ kLlwuFilterNegEdgeDetect, /* filter negative edge detection */
+ kLlwuFilterAnyEdgeDetect /* filter any edge detection */
+} llwu_filter_modes_t;
+
+/*! @brief External input pin filter control structure */
+typedef struct _llwu_external_pin_filter_mode {
+ llwu_filter_modes_t filterMode; /* filter mode */
+ uint32_t pinNumber; /* pin number */
+} llwu_external_pin_filter_mode_t;
+
+/*! @brief Reset enable control structure */
+typedef struct _llwu_reset_enable_mode {
+ bool lowLeakageMode; /* reset for Low-leakage mode */
+ bool digitalFilterMode; /* reset for digital filter mode */
+} llwu_reset_enable_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief Sets the external input pin source mode.
+ *
+ * This function sets the external input pin source mode that is used
+ * as a wake up source.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t
+ * @param pinNumber pin number specified
+ */
+void LLWU_HAL_SetExternalInputPinMode(uint32_t baseAddr,
+ llwu_external_pin_modes_t pinMode,
+ uint32_t pinNumber);
+
+/*!
+ * @brief Gets the external input pin source mode.
+ *
+ * This function gets the external input pin source mode that is used
+ * as wake up source.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param pinNumber pin number specified
+ * @return pinMode pin mode defined in llwu_external_pin_modes_t
+ */
+llwu_external_pin_modes_t LLWU_HAL_GetExternalInputPinMode(uint32_t baseAddr,
+ uint32_t pinNumber);
+
+/*!
+ * @brief Enables/disables the internal module source.
+ *
+ * This function enables/disables the internal module source mode that is used
+ * as a wake up source.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param moduleNumber module number specified
+ * @param enable enable or disable setting
+ */
+void LLWU_HAL_SetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber, bool enable);
+
+/*!
+ * @brief Gets the internal module source enable setting.
+ *
+ * This function gets the internal module source enable setting that is used
+ * as a wake up source.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param moduleNumber module number specified
+ * @return enable enable or disable setting
+ */
+bool LLWU_HAL_GetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber);
+
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function gets the external wakeup source flag for a specific pin.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param pinNumber pin number specified
+ * @return flag true if wakeup source flag set
+ */
+bool LLWU_HAL_GetExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber);
+
+/*!
+ * @brief Clears the external wakeup source flag.
+ *
+ * This function clears the external wakeup source flag for a specific pin.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param pinNumber pin number specified
+ */
+void LLWU_HAL_ClearExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber);
+
+/*!
+ * @brief Gets the internal module wakeup source flag.
+ *
+ * This function gets the internal module wakeup source flag for a specific module.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param moduleNumber module number specified
+ * @return flag true if wakeup flag set
+ */
+bool LLWU_HAL_GetInternalModuleWakeupFlag(uint32_t baseAddr, uint32_t moduleNumber);
+
+/*!
+ * @brief Sets the pin filter configuration.
+ *
+ * This function sets the pin filter configuration.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param filterNumber filter number specified
+ * @param pinFilterMode filter mode configuration
+ */
+void LLWU_HAL_SetPinFilterMode(uint32_t baseAddr, uint32_t filterNumber,
+ llwu_external_pin_filter_mode_t pinFilterMode);
+/*!
+ * @brief Gets the pin filter configuration.
+ *
+ * This function gets the pin filter configuration.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param filterNumber filter number specified
+ * @param pinFilterMode filter mode configuration
+ */
+void LLWU_HAL_GetPinFilterMode(uint32_t baseAddr, uint32_t filterNumber,
+ llwu_external_pin_filter_mode_t *pinFilterMode);
+
+/*!
+ * @brief Gets the filter detect flag.
+ *
+ * This function will get the filter detect flag.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param filterNumber filter number specified
+ * @return flag true if the filter was a wakeup source
+ */
+bool LLWU_HAL_GetFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber);
+
+/*!
+ * @brief Clears the filter detect flag.
+ *
+ * This function will clear the filter detect flag.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param filterNumber filter number specified
+ */
+void LLWU_HAL_ClearFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber);
+
+#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE
+/*!
+ * @brief Sets the reset enable mode.
+ *
+ * This function will set the reset enable mode.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param resetEnableMode reset enable mode defined in llwu_reset_enable_mode_t
+ */
+void LLWU_HAL_SetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t resetEnableMode);
+
+/*!
+ * @brief Gets the reset enable mode.
+ *
+ * This function gets the reset enable mode.
+ *
+ * @param baseAddr Register base address of LLWU
+ * @param resetEnableMode reset enable mode defined in llwu_reset_enable_mode_t
+ */
+void LLWU_HAL_GetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t *resetEnableMode);
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Low-Leakage Wakeup Unit Control APIs*/
+/*@{*/
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_LLWU_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,86 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_LPTMR_FEATURES_H__) +#define __FSL_LPTMR_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL03Z32CAF4) || \ + defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || \ + defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || \ + defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ + defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || \ + defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || \ + defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ + defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || \ + defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ + defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ + defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ + defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ + defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \ + defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || \ + defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) || defined(CPU_MKL25Z128VLK4) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_LPTMR_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lptmr_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_HAL_Init
+ * Description : Initialize LPTMR module to reset state.
+ *
+ *END**************************************************************************/
+void LPTMR_HAL_Init(uint32_t baseAddr)
+{
+ LPTMR_HAL_Disable(baseAddr);
+ LPTMR_HAL_ClearIntFlag(baseAddr);
+ LPTMR_HAL_SetIntCmd(baseAddr, false);
+ LPTMR_HAL_SetPinSelectMode(baseAddr, kLptmrPinSelectCmpOut);
+ LPTMR_HAL_SetPinPolarityMode(baseAddr, kLptmrPinPolarityActiveHigh);
+ LPTMR_HAL_SetFreeRunningCmd(baseAddr, false);
+ LPTMR_HAL_SetTimerModeMode(baseAddr, kLptmrTimerModeTimeCounter);
+ LPTMR_HAL_SetPrescalerCmd(baseAddr, false);
+ LPTMR_HAL_SetPrescalerValueMode(baseAddr, kLptmrPrescalerDivide2);
+ LPTMR_HAL_SetPrescalerClockSourceMode(baseAddr, kLptmrPrescalerClockSourceMcgIrcClk);
+ LPTMR_HAL_SetCompareValue(baseAddr, 0x0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_LPTMR_HAL_H__
+#define __FSL_LPTMR_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_lptmr_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup lptmr_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief LPTMR pin selection.*/
+typedef enum _lptmr_pin_select{
+ kLptmrPinSelectCmpOut = 0x0U, /*!< Lptmr Pin is CMP0 output pin.*/
+ kLptmrPinSelectLptmrAlt1 = 0x1U, /*!< Lptmr Pin is LPTMR_ALT1 pin.*/
+ kLptmrPinSelectLptmrAlt2 = 0x2U, /*!< Lptmr Pin is LPTMR_ALT2 pin.*/
+ kLptmrPinSelectLptmrAlt3 = 0x3U /*!< Lptmr Pin is LPTMR_ALT3 pin.*/
+} lptmr_pin_select_t;
+
+/*! @brief LPTMR pin polarity, used while in pluse counter mode.*/
+typedef enum _lptmr_pin_polarity{
+ kLptmrPinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high.*/
+ kLptmrPinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low.*/
+} lptmr_pin_polarity_t;
+
+/*! @brief LPTMR timer mode selection.*/
+typedef enum _lptmr_timer_mode{
+ kLptmrTimerModeTimeCounter = 0x0U, /*!< Time Counter mode.*/
+ kLptmrTimerModePluseCounter = 0x1U /*!< Pulse Counter mode.*/
+} lptmr_timer_mode_t;
+
+/*! @brief LPTMR proscaler value.*/
+typedef enum _lptmr_prescaler_value{
+ kLptmrPrescalerDivide2 = 0x0U, /*!< Prescaler divide 2, glitch filter invalid.*/
+ kLptmrPrescalerDivide4GlichFiltch2 = 0x1U, /*!< Prescaler divide 4, glitch filter 2.*/
+ kLptmrPrescalerDivide8GlichFiltch4 = 0x2U, /*!< Prescaler divide 8, glitch filter 4.*/
+ kLptmrPrescalerDivide16GlichFiltch8 = 0x3U, /*!< Prescaler divide 16, glitch filter 8.*/
+ kLptmrPrescalerDivide32GlichFiltch16 = 0x4U, /*!< Prescaler divide 32, glitch filter 16.*/
+ kLptmrPrescalerDivide64GlichFiltch32 = 0x5U, /*!< Prescaler divide 64, glitch filter 32.*/
+ kLptmrPrescalerDivide128GlichFiltch64 = 0x6U, /*!< Prescaler divide 128, glitch filter 64.*/
+ kLptmrPrescalerDivide256GlichFiltch128 = 0x7U, /*!< Prescaler divide 256, glitch filter 128.*/
+ kLptmrPrescalerDivide512GlichFiltch256 = 0x8U, /*!< Prescaler divide 512, glitch filter 256.*/
+ kLptmrPrescalerDivide1024GlichFiltch512 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512.*/
+ kLptmrPrescalerDivide2048lichFiltch1024 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024.*/
+ kLptmrPrescalerDivide4096GlichFiltch2048 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048.*/
+ kLptmrPrescalerDivide8192GlichFiltch4096 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096.*/
+ kLptmrPrescalerDivide16384GlichFiltch8192 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192.*/
+ kLptmrPrescalerDivide32768GlichFiltch16384 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384.*/
+ kLptmrPrescalerDivide65535GlichFiltch32768 = 0xFU /*!< Prescaler divide 65535, glitch filter 32768.*/
+} lptmr_prescaler_value_t;
+
+/*! @brief LPTMR clock source selection.*/
+typedef enum _lptmr_prescaler_clock_source{
+ kLptmrPrescalerClockSourceMcgIrcClk = 0x0U, /*!< Clock source is MCGIRCLK.*/
+ kLptmrPrescalerClockSourceLpo = 0x1U, /*!< Clock source is LPO.*/
+ kLptmrPrescalerClockSourceErClk32K = 0x2U, /*!< Clock source is ERCLK32K.*/
+ kLptmrPrescalerClockSourceOscErClk = 0x3U /*!< Clock source is OSCERCLK.*/
+} lptmr_prescaler_clock_source_t;
+
+/*! @brief LPTMR status return codes.*/
+typedef enum _lptmr_status {
+ kStatus_LPTMR_Success = 0x0U, /*!< Succeed. */
+ kStatus_LPTMR_NotInitlialized = 0x1U, /*!< LPTMR is not initialized yet. */
+ kStatus_LPTMR_NullArgument = 0x2U, /*!< Argument is NULL.*/
+ kStatus_LPTMR_InvalidPrescalerValue = 0x3U, /*!< Value 0 is not valid in pulse counter mode. */
+ kStatus_LPTMR_InvalidInTimeCounterMode = 0x4U, /*!< Function can not called in time counter mode. */
+ kStatus_LPTMR_InvalidInPluseCounterMode = 0x5U, /*!< Function can not called in pulse counter mode. */
+ kStatus_LPTMR_InvalidPlusePeriodCount = 0x6U, /*!< Pulse period count must be integer multiples of the glitch filter divider. */
+ kStatus_LPTMR_TcfNotSet = 0x7U, /*!< If LPTMR is enabled, compare register can only altered when TCF is set. */
+ kStatus_LPTMR_TimerPeriodUsTooSmall = 0x8U, /*!< Timer period time is too small for current clock source. */
+ kStatus_LPTMR_TimerPeriodUsTooLarge = 0x9U /*!< Timer period time is too large for current clock source. */
+ } lptmr_status_t;
+
+/*******************************************************************************
+ ** Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPTMR HAL.
+ * @{
+ */
+
+/*!
+ * @brief Enables the LPTMR module operation.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_Enable(uint32_t baseAddr)
+{
+ BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)true);
+}
+
+/*!
+ * @brief Disables the LPTMR module operation.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_Disable(uint32_t baseAddr)
+{
+ BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)false);
+}
+
+/*!
+ * @brief Checks whether the LPTMR module is enabled.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @retval true LPTMR module is enabled.
+ * @retval false LPTMR module is disabled.
+ */
+static inline bool LPTMR_HAL_IsEnabled(uint32_t baseAddr)
+{
+ return (bool)BR_LPTMR_CSR_TEN(baseAddr);
+}
+
+/*!
+ * @brief Clears the LPTMR interrupt flag if set.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_ClearIntFlag(uint32_t baseAddr)
+{
+ BW_LPTMR_CSR_TCF(baseAddr, 1);
+}
+
+/*!
+ * @brief Returns the current LPTMR interrupt flag.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ * @retval true An interrupt is pending.
+ * @retval false No interrupt is pending.
+ */
+static inline bool LPTMR_HAL_IsIntPending(uint32_t baseAddr)
+{
+ return ((bool)BR_LPTMR_CSR_TCF(baseAddr));
+}
+
+/*!
+ * @brief Enables or disables the LPTMR interrupt.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ * @param enable Pass true to enable LPTMR interrupt
+ */
+static inline void LPTMR_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPTMR_CSR_TIE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the LPTMR interrupt is enabled.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @retval true LPTMR interrupt is enabled.
+ * @retval false LPTMR interrupt is disabled.
+ */
+static inline bool LPTMR_HAL_GetIntCmd(uint32_t baseAddr)
+{
+ return ((bool)BR_LPTMR_CSR_TIE(baseAddr));
+}
+
+/*!
+ * @brief Selects the LPTMR pulse input pin select.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param pinSelect Specifies LPTMR pulse input pin select, see #lptmr_pin_select_t
+ */
+static inline void LPTMR_HAL_SetPinSelectMode(uint32_t baseAddr, lptmr_pin_select_t pinSelect)
+{
+ BW_LPTMR_CSR_TPS(baseAddr, (uint8_t)pinSelect);
+}
+
+/*!
+ * @brief Returns the LPTMR pulse input pin select.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return LPTMR pulse input pin select, see #lptmr_pin_select_t
+ */
+static inline lptmr_pin_select_t LPTMR_HAL_GetPinSelectMode(uint32_t baseAddr)
+{
+ return (lptmr_pin_select_t)BR_LPTMR_CSR_TPS(baseAddr);
+}
+
+/*!
+ * @brief Selects the LPTMR pulse input pin polarity.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param pinPolarity Specifies LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t
+ */
+static inline void LPTMR_HAL_SetPinPolarityMode(uint32_t baseAddr, lptmr_pin_polarity_t pinPolarity)
+{
+ BW_LPTMR_CSR_TPP(baseAddr, (uint8_t)pinPolarity);
+}
+
+/*!
+ * @brief Returns the LPTMR pulse input pin polarity.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t
+ */
+static inline lptmr_pin_polarity_t LPTMR_HAL_GetPinPolarityMode(uint32_t baseAddr)
+{
+ return (lptmr_pin_polarity_t)BR_LPTMR_CSR_TPP(baseAddr);
+}
+
+/*!
+ * @brief Enables or disables the LPTMR free running.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ * @param enable Pass true to enable LPTMR free running
+ */
+static inline void LPTMR_HAL_SetFreeRunningCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPTMR_CSR_TFC(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the LPTMR free running is enabled.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @retval true LPTMR free running is enabled.
+ * @retval false LPTMR free running is disabled.
+ */
+static inline bool LPTMR_HAL_GetFreeRunningCmd(uint32_t baseAddr)
+{
+ return ((bool)BR_LPTMR_CSR_TFC(baseAddr));
+}
+
+/*!
+ * @brief Selects the LPTMR working mode.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param timerMode Specifies LPTMR working mode, see #lptmr_timer_mode_t
+ */
+static inline void LPTMR_HAL_SetTimerModeMode(uint32_t baseAddr, lptmr_timer_mode_t timerMode)
+{
+ BW_LPTMR_CSR_TMS(baseAddr, (uint8_t)timerMode);
+}
+
+/*!
+ * @brief Returns the LPTMR working mode.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return LPTMR working mode, see #lptmr_timer_mode_t
+ */
+static inline lptmr_timer_mode_t LPTMR_HAL_GetTimerModeMode(uint32_t baseAddr)
+{
+ return (lptmr_timer_mode_t)BR_LPTMR_CSR_TMS(baseAddr);
+}
+
+/*!
+ * @brief Selects the LPTMR prescaler value.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param prescaleValue Specifies LPTMR prescaler value, see #lptmr_prescaler_value_t
+ */
+static inline void LPTMR_HAL_SetPrescalerValueMode(uint32_t baseAddr, lptmr_prescaler_value_t prescaleValue)
+{
+ BW_LPTMR_PSR_PRESCALE(baseAddr, (uint8_t)prescaleValue);
+}
+
+/*!
+ * @brief Returns the LPTMR prescaler value.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return LPTMR prescaler value, see #lptmr_prescaler_value_t
+ */
+static inline lptmr_prescaler_value_t LPTMR_HAL_GetPrescalerValueMode(uint32_t baseAddr)
+{
+ return (lptmr_prescaler_value_t)BR_LPTMR_PSR_PRESCALE(baseAddr);
+}
+
+/*!
+ * @brief Enables or disables the LPTMR prescaler.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ * @param enable Pass true to enable LPTMR free running
+ */
+static inline void LPTMR_HAL_SetPrescalerCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPTMR_PSR_PBYP(baseAddr, (uint8_t)(enable == false)); /* 1 means disable prelsaler , 0 means enalbe prescaler */
+}
+
+/*!
+ * @brief Returns whether the LPTMR prescaler is enabled.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @retval true LPTMR prescaler is enabled.
+ * @retval false LPTMR prescaler is disabled.
+ */
+static inline bool LPTMR_HAL_GetPrescalerCmd(uint32_t baseAddr)
+{
+ return (bool)(0 == BR_LPTMR_PSR_PBYP(baseAddr)); /* 1 means prelsaler is disabled, 0 means prescaler is enalbed*/
+}
+
+/*!
+ * @brief Selects the LPTMR clock source.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param prescalerClockSource Specifies LPTMR clock source, see #lptmr_prescaler_clock_source_t
+ */
+static inline void LPTMR_HAL_SetPrescalerClockSourceMode(uint32_t baseAddr, lptmr_prescaler_clock_source_t prescalerClockSource)
+{
+ BW_LPTMR_PSR_PCS(baseAddr, (uint8_t)prescalerClockSource);
+}
+
+/*!
+ * @brief Gets the LPTMR clock source.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return LPTMR clock source, see #lptmr_prescaler_clock_source_t
+ */
+static inline lptmr_prescaler_clock_source_t LPTMR_HAL_GetPrescalerClockSourceMode(uint32_t baseAddr)
+{
+ return (lptmr_prescaler_clock_source_t)BR_LPTMR_PSR_PCS(baseAddr);
+}
+
+/*!
+ * @brief Sets the LPTMR compare value.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @param compareValue Specifies LPTMR compare value, less than 0xFFFFU
+ */
+static inline void LPTMR_HAL_SetCompareValue(uint32_t baseAddr, uint32_t compareValue)
+{
+ BW_LPTMR_CMR_COMPARE(baseAddr, compareValue & 0xFFFFU);
+}
+
+/*!
+ * @brief Gets the LPTMR compare value.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return Current LPTMR compare value
+ */
+static inline uint32_t LPTMR_HAL_GetCompareValue(uint32_t baseAddr)
+{
+ return (uint32_t)(BR_LPTMR_CMR_COMPARE(baseAddr) & 0xFFFFU);
+}
+
+/*!
+ * @brief Gets the LPTMR counter value.
+ *
+ * @param baseAddr The LPTMR peripheral base address.
+ * @return Current LPTMR counter value
+ */
+static inline uint32_t LPTMR_HAL_GetCounterValue(uint32_t baseAddr)
+{
+ BW_LPTMR_CNR_COUNTER(baseAddr, 0); /* Must first write to the CNR with any value */
+ return (uint32_t)(BR_LPTMR_CNR_COUNTER(baseAddr) & 0xFFFFU);
+}
+
+/*!
+ * @brief Restores the LPTMR module to reset state.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ */
+void LPTMR_HAL_Init(uint32_t baseAddr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPTMR_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,220 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_LPUART_FEATURES_H__) +#define __FSL_LPUART_FEATURES_H__ + +#if defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_HAS_FIFO (0) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) + /* @brief Peripheral type. */ + #define FSL_FEATURE_LPUART_IS_SCI (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_FIFO_SIZE (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_HAS_FIFO (0) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) + /* @brief Peripheral type. */ + #define FSL_FEATURE_LPUART_IS_SCI (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_FIFO_SIZE (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_HAS_FIFO (0) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) + /* @brief Peripheral type. */ + #define FSL_FEATURE_LPUART_IS_SCI (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_LPUART_FIFO_SIZE (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +#else + #define MBED_NO_LPUART +#endif + +#endif /* __FSL_LPUART_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,782 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_lpuart_hal.h"
+
+#ifndef MBED_NO_LPUART
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Init
+ * Description : Initializes the LPUART controller to known state.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Init(uint32_t baseAddr)
+{
+ HW_LPUART_BAUD_WR(baseAddr, 0x0F000004);
+ HW_LPUART_STAT_WR(baseAddr, 0xC01FC000);
+ HW_LPUART_CTRL_WR(baseAddr, 0x00000000);
+ HW_LPUART_MATCH_WR(baseAddr, 0x00000000);
+ HW_LPUART_MODIR_WR(baseAddr, 0x00000000);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetBaudRate
+ * Description : Configures the LPUART baud rate.
+ * In some LPUART instances the user must disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz,
+ uint32_t desiredBaudRate)
+{
+ uint16_t sbr, sbrTemp, i;
+ uint32_t osr, tempDiff, calculatedBaud, baudDiff;
+
+ /* This lpuart instantiation uses a slightly different baud rate calculation */
+ /* The idea is to use the best OSR (over-sampling rate) possible */
+ /* Note, osr is typically hard-set to 16 in other lpuart instantiations */
+ /* First calculate the baud rate using the minimum OSR possible (4) */
+ osr = 4;
+ sbr = (sourceClockInHz/(desiredBaudRate * osr));
+ calculatedBaud = (sourceClockInHz / (osr * sbr));
+
+ if (calculatedBaud > desiredBaudRate)
+ {
+ baudDiff = calculatedBaud - desiredBaudRate;
+ }
+ else
+ {
+ baudDiff = desiredBaudRate - calculatedBaud;
+ }
+
+ /* loop to find the best osr value possible, one that generates minimum baudDiff */
+ /* iterate through the rest of the supported values of osr */
+ for (i = 5; i <= 32; i++)
+ {
+ /* calculate the temporary sbr value */
+ sbrTemp = (sourceClockInHz/(desiredBaudRate * i));
+ /* calculate the baud rate based on the temporary osr and sbr values */
+ calculatedBaud = (sourceClockInHz / (i * sbrTemp));
+
+ if (calculatedBaud > desiredBaudRate)
+ {
+ tempDiff = calculatedBaud - desiredBaudRate;
+ }
+ else
+ {
+ tempDiff = desiredBaudRate - calculatedBaud;
+ }
+
+ if (tempDiff <= baudDiff)
+ {
+ baudDiff = tempDiff;
+ osr = i; /* update and store the best osr value calculated */
+ sbr = sbrTemp; /* update store the best sbr value calculated */
+ }
+ }
+
+ /* next, check to see if actual baud rate is within 3% of desired baud rate */
+ /* based on the best calculate osr value */
+ if (baudDiff < ((desiredBaudRate / 100) * 3))
+ {
+ /* Acceptable baud rate */
+ /* Check if osr is between 4x and 7x oversampling */
+ /* If so, then "BOTHEDGE" sampling must be turned on */
+ if ((osr > 3) && (osr < 8))
+ {
+ BW_LPUART_BAUD_BOTHEDGE(baseAddr, 1);
+ }
+
+ /* program the osr value (bit value is one less than actual value) */
+ BW_LPUART_BAUD_OSR(baseAddr, (osr-1));
+
+ /* write the sbr value to the BAUD registers */
+ BW_LPUART_BAUD_SBR(baseAddr, sbr);
+ }
+ else
+ {
+ /* Unacceptable baud rate difference of more than 3% */
+ return kStatus_LPUART_BaudRatePercentDiffExceeded;
+ }
+
+ return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetBitCountPerChar
+ * Description : Configures the number of bits per character in the LPUART controller.
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetBitCountPerChar(uint32_t baseAddr, lpuart_bit_count_per_char_t bitCountPerChar)
+{
+ if(bitCountPerChar == kLpuart10BitsPerChar)
+ {
+ BW_LPUART_BAUD_M10(baseAddr, 1); /* set M10 for 10-bit mode, M bit in C1 is don't care */
+ }
+ else
+ {
+ BW_LPUART_CTRL_M(baseAddr, bitCountPerChar); /* config 8- (M=0) or 9-bits (M=1) */
+ BW_LPUART_BAUD_M10(baseAddr, 0); /* clear M10 to make sure not 10-bit mode */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetParityMode
+ * Description : Configures parity mode in the LPUART controller.
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetParityMode(uint32_t baseAddr, lpuart_parity_mode_t parityModeType)
+{
+ /* configure the parity enable/type */
+
+ if ((parityModeType) == kLpuartParityDisabled)
+ {
+ /* parity disabled, hence parity type is don't care */
+ BW_LPUART_CTRL_PE(baseAddr, 0);
+ }
+ else
+ {
+ /* parity enabled */
+ BW_LPUART_CTRL_PE(baseAddr, 1);
+ /* parity odd/even depending on parity mode setting */
+ BW_LPUART_CTRL_PT(baseAddr, (parityModeType) & 0x1);
+ }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetTxRxInversionCmd
+ * Description : Configures the transmit and receive inversion control in the LPUART controller.
+ * This function should only be called when the LPUART is between transmit and receive packets.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, uint32_t rxInvert, uint32_t txInvert)
+{
+ /* 0 - receive data not inverted, 1 - receive data inverted */
+ BW_LPUART_STAT_RXINV(baseAddr, rxInvert);
+ /* 0 - transmit data not inverted, 1 - transmit data inverted */
+ BW_LPUART_CTRL_TXINV(baseAddr, txInvert);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_EnableTransmitter
+ * Description : Enables the LPUART transmitter.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_EnableTransmitter(uint32_t baseAddr)
+{
+ /* enable the transmitter based on the lpuart baseAddr */
+
+ /* for this lpuart baseAddr, there is a two step process to clear the transmit complete */
+ /* status flag: */
+ /* 1. Read the status register with the status bit set */
+ /* 2. enable the transmitter (change TE from 0 to 1) */
+ /* first read the status register */
+
+ /* no need to store the read value, it's assumed the status bit is set */
+ HW_LPUART_STAT_RD(baseAddr);
+ /* second, enable the transmitter */
+ BW_LPUART_CTRL_TE(baseAddr, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetIntMode
+ * Description : Configures the LPUART module interrupts to enable/disable various interrupt sources.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt, bool enable)
+{
+ uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
+ uint32_t temp = 1U << (uint32_t)interrupt;
+
+ switch ( reg )
+ {
+ case LPUART_BAUD_REG_ID:
+ enable ? HW_LPUART_BAUD_SET(baseAddr, temp) : HW_LPUART_BAUD_CLR(baseAddr, temp);
+ break;
+ case LPUART_STAT_REG_ID:
+ enable ? HW_LPUART_STAT_SET(baseAddr, temp) : HW_LPUART_STAT_CLR(baseAddr, temp);
+ break;
+ case LPUART_CTRL_REG_ID:
+ enable ? HW_LPUART_CTRL_SET(baseAddr, temp) : HW_LPUART_CTRL_CLR(baseAddr, temp);
+ break;
+ case LPUART_DATA_REG_ID:
+ enable ? HW_LPUART_DATA_SET(baseAddr, temp) : HW_LPUART_DATA_CLR(baseAddr, temp);
+ break;
+ case LPUART_MATCH_REG_ID:
+ enable ? HW_LPUART_MATCH_SET(baseAddr, temp) : HW_LPUART_MATCH_CLR(baseAddr, temp);
+ break;
+ case LPUART_MODIR_REG_ID:
+ enable ? HW_LPUART_MODIR_SET(baseAddr, temp) : HW_LPUART_MODIR_CLR(baseAddr, temp);
+ break;
+ default :
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetIntMode
+ * Description : Returns whether the LPUART module interrupts is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool LPUART_HAL_GetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt)
+{
+ uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
+ bool retVal = false;
+
+ switch ( reg )
+ {
+ case LPUART_BAUD_REG_ID:
+ retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ case LPUART_STAT_REG_ID:
+ retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ case LPUART_CTRL_REG_ID:
+ retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ case LPUART_DATA_REG_ID:
+ retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ case LPUART_MATCH_REG_ID:
+ retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ case LPUART_MODIR_REG_ID:
+ retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
+ break;
+ default :
+ break;
+ }
+
+ return retVal;
+}
+
+#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ConfigureDma
+ * Description : LPUART configures DMA requests for Transmitter and Receiver.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig)
+{
+ /* TDMAE configures the transmit data register empty flag, S1[TDRE], */
+ /* to generate a DMA request. */
+ BW_LPUART_BAUD_TDMAE(baseAddr, txDmaConfig) ;/* set TDMAE to enable, clear to disable */
+ /* RDMAE configures the receive data register fell flag, S1[RDRF], */
+ /* to generate a DMA request. */
+ BW_LPUART_BAUD_RDMAE(baseAddr, rxDmaConfig); /* set RDMAE to enable, clear to disable */
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetWaitModeOperationConfig
+ * Description : LPUART configures DMA requests for Transmitter and Receiver.
+ *
+ *END**************************************************************************/
+lpuart_operation_config_t LPUART_HAL_GetWaitModeOperationConfig(uint32_t baseAddr)
+{
+ /* get configuration lpuart operation in wait mode */
+ /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */
+ if (BR_LPUART_CTRL_DOZEEN(baseAddr) == 0)
+ {
+ return kLpuartOperates;
+ }
+ else
+ {
+ return kLpuartStops;
+ }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SedLoopbackCmd
+ * Description : Configures the LPUART loopback operation (enable/disable loopback operation)
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SedLoopbackCmd(uint32_t baseAddr, bool enable)
+{
+ /* configure lpuart to enable/disable operation in loopback mode */
+
+ /* configure LOOPS bit to enable(1)/disable(0) loopback mode, but also need to clear RSRC */
+ BW_LPUART_CTRL_LOOPS(baseAddr, enable);
+
+ /* clear RSRC for loopback mode, and if loopback disabled, */
+ /* this bit has no meaning but clear anyway */
+ /* to set it back to default value */
+ BW_LPUART_CTRL_RSRC(baseAddr, 0);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetSingleWireCmd
+ * Description : Configures the LPUART single-wire operation (enable/disable single-wire mode)
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetSingleWireCmd(uint32_t baseAddr, bool enable)
+{
+ /* configure lpuart to enable/disable operation in single mode */
+
+ /* to enable single-wire mode, need both LOOPS and RSRC set, to disable, clear both */
+ BW_LPUART_CTRL_LOOPS(baseAddr, enable);
+ BW_LPUART_CTRL_RSRC(baseAddr, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_PutReceiverInStandbyMode
+ * Description : Places the LPUART receiver in standby mode.
+ * In some LPUART instances,
+ * before placing LPUART in standby mode, first determine whether the receiver is set to
+ * wake on idle or whether it is already in idle state.
+ * NOTE that the RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If it is set to wake up an IDLE event and the channel is
+ * already idle, it is possible that the LPUART will discard data since data must be received
+ * (or a LIN break detect) after an IDLE is detected and before IDLE is allowed to reasserted.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr)
+{
+ /* In some lpuart instances, there is a condition that must be met before placing */
+ /* rx in standby mode. */
+ /* Before placing lpuart in standby, need to first determine if receiver is set to */
+ /* wake on idle and if receiver is already in idle state. Per ref manual: */
+ /* NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is */
+ /* currently not idle. */
+ /* This can be determined by the STAT[RAF] flag. If set to wake up an IDLE event and */
+ /* the channel is already idle, it is possible that the LPUART will discard data since data */
+ /* must be received (or a LIN break detect) after an IDLE is detected before IDLE is */
+ /* allowed to reasserted. */
+ lpuart_wakeup_method_t rxWakeMethod;
+ bool lpuart_current_rx_state;
+
+ /* see if wake is set for idle or */
+ rxWakeMethod = LPUART_HAL_GetReceiverWakeupMethod(baseAddr);
+ lpuart_current_rx_state = LPUART_HAL_GetStatusFlag(baseAddr, kLpuartRxActive);
+
+ /* if both rxWakeMethod is set for idle and current rx state is idle, don't put in standy */
+ if ((rxWakeMethod == kLpuartIdleLineWake) && (lpuart_current_rx_state == 0))
+ {
+ return kStatus_LPUART_RxStandbyModeError;
+ }
+ else
+ {
+ /* set the RWU bit to place receiver into standby mode */
+ BW_LPUART_CTRL_RWU(baseAddr, 1);
+ return kStatus_LPUART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetReceiverWakeupMethod
+ * Description : Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode.
+ *
+ *END**************************************************************************/
+lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr)
+{
+ /* get configuration of the WAKE bit for idle line wake or address mark wake */
+ if(HW_LPUART_CTRL(baseAddr).B.WAKE == 1)
+ {
+ return kLpuartAddrMarkWake;
+ }
+ else
+ {
+ return kLpuartIdleLineWake;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ConfigureIdleLineDetect
+ * Description : LPUART idle-line detect operation configuration (idle line bit-count start and wake
+ * up affect on IDLE status bit).
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_ConfigureIdleLineDetect(uint32_t baseAddr,
+ const lpuart_idle_line_config_t *config)
+{
+ /* Configure the idle line detection configuration as follows: */
+ /* configure the ILT to bit count after start bit or stop bit */
+ /* configure RWUID to set or not set IDLE status bit upon detection of */
+ /* an idle character when recevier in standby */
+ BW_LPUART_CTRL_ILT(baseAddr, config->idleLineType);
+ BW_LPUART_STAT_RWUID(baseAddr, config->rxWakeIdleDetect);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetMatchAddressOperation
+ * Description : LPUART configures match address mode control (Note: Feature available on
+ * select LPUART instances)
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_SetMatchAddressOperation( uint32_t baseAddr,
+ bool matchAddrMode1, bool matchAddrMode2,
+ uint8_t matchAddrValue1, uint8_t matchAddrValue2, lpuart_match_config_t config)
+{
+ BW_LPUART_BAUD_MAEN1(baseAddr, matchAddrMode1); /* Match Address Mode Enable 1 */
+ BW_LPUART_BAUD_MAEN2(baseAddr, matchAddrMode2); /* Match Address Mode Enable 2 */
+ BW_LPUART_MATCH_MA1(baseAddr, matchAddrValue1); /* match address register 1 */
+ BW_LPUART_MATCH_MA2(baseAddr, matchAddrValue2); /* match address register 2 */
+ BW_LPUART_BAUD_MATCFG(baseAddr, config); /* Match Configuration */
+
+ return kStatus_LPUART_Success;
+}
+
+#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetInfraredOperation
+ * Description : Configures the LPUART infrared operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable,
+ lpuart_ir_tx_pulsewidth_t pulseWidth)
+{
+ /* enable or disable infrared */
+ BW_LPUART_MODIR_IREN(baseAddr, enable);
+
+ /* configure the narrow pulse width of the IR pulse */
+ BW_LPUART_MODIR_TNP(baseAddr, pulseWidth);
+}
+#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetStatusFlag
+ * Description : LPUART get status flag by passing flag enum.
+ *
+ *END**************************************************************************/
+bool LPUART_HAL_GetStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag)
+{
+ uint32_t reg = (uint32_t)(statusFlag) >> LPUART_SHIFT;
+ bool retVal = false;
+
+ switch ( reg )
+ {
+ case LPUART_BAUD_REG_ID:
+ retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ case LPUART_STAT_REG_ID:
+ retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ case LPUART_CTRL_REG_ID:
+ retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ case LPUART_DATA_REG_ID:
+ retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ case LPUART_MATCH_REG_ID:
+ retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ case LPUART_MODIR_REG_ID:
+ retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
+ break;
+ default:
+ break;
+ }
+
+ return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ClearStatusFlag
+ * Description : LPUART clears an individual status flag
+ * (see lpuart_status_flag_t for list of status bits).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_ClearStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag)
+{
+ lpuart_status_t returnCode = kStatus_LPUART_Success;
+
+ /* clear the desired, individual status flag as passed in through statusFlag */
+ switch(statusFlag)
+ {
+ case kLpuartTxDataRegEmpty:
+ /* This flag is cleared automatically by other lpuart operations */
+ /* and cannot be manually cleared, return error code */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+
+ case kLpuartTxComplete:
+ /* This flag is cleared automatically by other lpuart operations */
+ /* and cannot be manually cleared, return error code */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+
+ case kLpuartRxDataRegFull:
+ /* This flag is cleared automatically by other lpuart operations and */
+ /* cannot be manually cleared, return error code */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+
+ case kLpuartIdleLineDetect:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_IDLE(baseAddr, 1);
+ break;
+
+ case kLpuartRxOverrun:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_OR(baseAddr, 1);
+ break;
+
+ case kLpuartNoiseDetect:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_NF(baseAddr, 1);
+ break;
+
+ case kLpuartFrameErr:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_FE(baseAddr, 1);
+ break;
+
+ case kLpuartParityErr:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_PF(baseAddr, 1);
+ break;
+
+ case kLpuartLineBreakDetect:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_LBKDIF(baseAddr, 1);
+ break;
+
+ case kLpuartRxActiveEdgeDetect:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_RXEDGIF(baseAddr, (1U));
+ break;
+
+ case kLpuartRxActive:
+ /* This flag is cleared automatically by other lpuart operations and */
+ /* cannot be manually cleared, return error code */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+
+#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ case kLpuartNoiseInCurrentWord:
+ /* This flag is not clearable, it simply reflects the status in the */
+ /* current data word and changes with each new data word */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+
+ case kLpuartParityErrInCurrentWord:
+ /* This flag is not clearable, it simply reflects the status in the */
+ /* current data word and changes with each new data word */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+#endif
+
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+ case kLpuartMatchAddrOne:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_MA1F(baseAddr, 1);
+ break;
+ case kLpuartMatchAddrTwo:
+ /* write one to clear status flag */
+ BW_LPUART_STAT_MA2F(baseAddr, 1);
+ break;
+#endif
+
+ default: /* catch inputs that are not recognized */
+ returnCode = kStatus_LPUART_ClearStatusFlagError;
+ break;
+ }
+
+ return (returnCode);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ClearAllNonAutoclearStatusFlags
+ * Description : LPUART clears ALL status flags.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr)
+{
+ /* clear the status flags that can be manually cleared */
+ /* note, some flags are automatically cleared and cannot be cleared automatically */
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartIdleLineDetect);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxOverrun);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartNoiseDetect);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartFrameErr);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartParityErr);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartLineBreakDetect);
+ LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxActiveEdgeDetect);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Putchar9
+ * Description : Sends the LPUART 9-bit character.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Putchar9(uint32_t baseAddr, uint16_t data)
+{
+ uint8_t ninthDataBit;
+
+ ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */
+
+ /* put 9-bit data to transmit */
+
+ /* first, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, T8=9th bit) */
+ BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit);
+
+ /* write to the data register last since this will trigger transmit complete status flag */
+ /* also typecast to uint8_t to match register type */
+ HW_LPUART_DATA_WR(baseAddr, (uint8_t)data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Putchar10
+ * Description : Sends the LPUART 10-bit character.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_Putchar10(uint32_t baseAddr, uint16_t data)
+{
+ uint8_t ninthDataBit;
+ uint8_t tenthDataBit;
+
+ /* put 10-bit data to transmit */
+ ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */
+ tenthDataBit = (data >> 9U) & 0x1U; /* isolate the tenth data bit */
+
+ /* first, write to the tenth data bit (bit position T9, where T[0:7]=8-bits, */
+ /* T9=10th bit, T8=9th bit) */
+ BW_LPUART_CTRL_R8T9(baseAddr, tenthDataBit);
+
+ /* next, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, */
+ /* T9=10th bit, T8=9th bit) */
+ BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit);
+
+ /* write to the data register last since this will trigger transmit complete status flag */
+ /* also typecast to uint8_t to match register type */
+ HW_LPUART_DATA_WR(baseAddr, (uint8_t)data);
+
+ return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Getchar
+ * Description : Gets the LPUART 8-bit character.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData)
+{
+ /* get 8-bit data from the lpuart data register */
+ *readData = (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Getchar9
+ * Description : Gets the LPUART 9-bit character.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData)
+{
+ uint16_t temp;
+
+ /* get 9-bit data from the lpuart data register */
+ /* read ninth data bit and left shift to bit position R8 before reading */
+ /* the 8 other data bits R[7:0] */
+ temp = HW_LPUART_CTRL(baseAddr).B.R8T9; /* need this two step process to work around mishra rule */
+ *readData = temp << 8;
+
+ /* do last: get 8-bit data from the lpuart data register, will clear certain */
+ /* receive status bits once completed */
+ /* need to OR these 8-bits with the ninth bit value above */
+ *readData |= (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Getchar10
+ * Description : Gets the LPUART 10-bit character.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_Getchar10(uint32_t baseAddr, uint16_t *readData)
+{
+ /* get 10-bit data from the lpuart data register, available only on supported lpuarts */
+
+ /* read tenth data bit and left shift to bit position R9 before reading the 9 other */
+ /* data bits: R8 and R[7:0] */
+ *readData = (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R9T8) << 9U);
+
+ /* read ninth data bit and left shift to bit position R8 before reading the 8 other */
+ /* data bits R[7:0] */
+ *readData |= (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R8T9) << 8U);
+
+ /* do last: get 8-bit data from the lpuart data register, will clear certain receive */
+ /* status bits once completed */
+ /* need to OR these 8-bits with the ninth bit value above */
+ *readData |= HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
+
+ return kStatus_LPUART_Success;
+}
+
+#endif /* MBED_NO_LPUART */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1134 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPUART_HAL_H__
+#define __FSL_LPUART_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_lpuart_features.h"
+#include "fsl_device_registers.h"
+
+#ifndef MBED_NO_LPUART
+
+/*!
+ * @addtogroup lpuart_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define LPUART_SHIFT (16U)
+#define LPUART_BAUD_REG_ID (0U)
+#define LPUART_STAT_REG_ID (1U)
+#define LPUART_CTRL_REG_ID (2U)
+#define LPUART_DATA_REG_ID (3U)
+#define LPUART_MATCH_REG_ID (4U)
+#define LPUART_MODIR_REG_ID (5U)
+
+/*! @brief Error codes for the LPUART driver.*/
+typedef enum _lpuart_status
+{
+ kStatus_LPUART_Success,
+ kStatus_LPUART_BaudRateCalculationError , /*!< LPUART Baud Rate calculation error out of range. */
+ kStatus_LPUART_BaudRatePercentDiffExceeded, /*!< LPUART Baud Rate exceeds percentage difference*/
+ kStatus_LPUART_BitCountNotSupported, /*!< LPUART bit count configuration not supported.*/
+ kStatus_LPUART_StopBitCountNotSupported, /*!< LPUART stop bit count configuration not supported.*/
+ kStatus_LPUART_RxStandbyModeError, /*!< LPUART unable to place receiver in standby mode.*/
+ kStatus_LPUART_ClearStatusFlagError, /*!< LPUART clear status flag error.*/
+ kStatus_LPUART_MSBFirstNotSupported, /*!< LPUART MSB first feature not supported.*/
+ kStatus_LPUART_Resync_NotSupported, /*!< LPUART resync disable operation not supported.*/
+ kStatus_LPUART_TxNotDisabled, /*!< LPUART Transmitter not disabled before enabling feature*/
+ kStatus_LPUART_RxNotDisabled, /*!< LPUART Receiver not disabled before enabling feature*/
+ kStatus_LPUART_TxOrRxNotDisabled, /*!< LPUART Transmitter or Receiver not disabled*/
+ kStatus_LPUART_TxBusy, /*!< LPUART transmit still in progress.*/
+ kStatus_LPUART_RxBusy, /*!< LPUART receive still in progress.*/
+ kStatus_LPUART_NoTransmitInProgress, /*!< LPUART no transmit in progress.*/
+ kStatus_LPUART_NoReceiveInProgress, /*!< LPUART no receive in progress.*/
+ kStatus_LPUART_InvalidInstanceNumber, /*!< Invalid LPUART base address */
+ kStatus_LPUART_InvalidBitSetting, /*!< Invalid setting for desired LPUART register bit field */
+ kStatus_LPUART_OverSamplingNotSupported, /*!< LPUART oversampling not supported.*/
+ kStatus_LPUART_BothEdgeNotSupported, /*!< LPUART both edge sampling not supported. */
+ kStatus_LPUART_Timeout, /*!< LPUART transfer timed out.*/
+ kStatus_LPUART_Initialized,
+} lpuart_status_t;
+
+/*! @brief LPUART number of stop bits*/
+typedef enum _lpuart_stop_bit_count {
+ kLpuartOneStopBit = 0, /*!< one stop bit*/
+ kLpuartTwoStopBit = 1, /*!< two stop bits*/
+} lpuart_stop_bit_count_t;
+
+/*! @brief LPUART parity mode*/
+typedef enum _lpuart_parity_mode {
+ kLpuartParityDisabled = 0x0, /*!< parity disabled*/
+ kLpuartParityEven = 0x2, /*!< parity enabled, type even, bit setting: PE|PT = 10*/
+ kLpuartParityOdd = 0x3, /*!< parity enabled, type odd, bit setting: PE|PT = 11*/
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART number of bits in a character*/
+typedef enum _lpuart_bit_count_per_char {
+ kLpuart8BitsPerChar = 0, /*!< 8-bit data characters*/
+ kLpuart9BitsPerChar = 1, /*!< 9-bit data characters*/
+ kLpuart10BitsPerChar = 2, /*!< 10-bit data characters*/
+} lpuart_bit_count_per_char_t;
+
+/*! @brief LPUART operation configuration constants*/
+typedef enum _lpuart_operation_config {
+ kLpuartOperates = 0,/*!< LPUART continues to operate normally.*/
+ kLpuartStops = 1, /*!< LPUART stops operation. */
+} lpuart_operation_config_t;
+
+/*! @brief LPUART wakeup from standby method constants*/
+typedef enum _lpuart_wakeup_method {
+ kLpuartIdleLineWake = 0, /*!< Idle-line wakes the LPUART receiver from standby. */
+ kLpuartAddrMarkWake = 1, /*!< Addr-mark wakes LPUART receiver from standby.*/
+} lpuart_wakeup_method_t;
+
+/*! @brief LPUART idle line detect selection types*/
+typedef enum _lpuart_idle_line_select {
+ kLpuartIdleLineAfterStartBit = 0, /*!< LPUART idle character bit count start after start bit */
+ kLpuartIdleLineAfterStopBit = 1, /*!< LPUART idle character bit count start after stop bit */
+} lpuart_idle_line_select_t;
+
+/*!
+ * @brief LPUART break character length settings for transmit/detect.
+ *
+ * The actual maximum bit times may vary depending on the LPUART instance.
+ */
+typedef enum _lpuart_break_char_length {
+ kLpuartBreakChar10BitMinimum = 0, /*!< LPUART break char length 10 bit times (if M = 0, SBNS = 0)
+ or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+ SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1 .*/
+ kLpuartBreakChar13BitMinimum = 1, /*!< LPUART break char length 13 bit times (if M = 0, SBNS = 0)
+ or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
+ SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1)*/
+} lpuart_break_char_length_t;
+
+/*! @brief LPUART single-wire mode TX direction*/
+typedef enum _lpuart_singlewire_txdir {
+ kLpuartSinglewireTxdirIn = 0, /*!< LPUART Single Wire mode TXDIR input*/
+ kLpuartSinglewireTxdirOut = 1, /*!< LPUART Single Wire mode TXDIR output*/
+} lpuart_singlewire_txdir_t;
+
+/*! @brief LPUART Configures the match addressing mode used.*/
+typedef enum _lpuart_match_config {
+ kLpuartAddressMatchWakeup = 0, /*!< LPUART Address Match Wakeup*/
+ kLpuartIdleMatchWakeup = 1, /*!< LPUART Idle Match Wakeup*/
+ kLpuartMatchOnAndMatchOff = 2, /*!< LPUART Match On and Match Off*/
+ kLpuartEnablesRwuOnDataMatch = 3, /*!< LPUART Enables RWU on Data Match and Match On/Off for transmitter CTS input*/
+} lpuart_match_config_t;
+
+/*! @brief LPUART infra-red transmitter pulse width options*/
+typedef enum _lpuart_ir_tx_pulsewidth {
+ kLpuartIrThreeSixteenthsWidth = 0, /*!< 3/16 pulse*/
+ kLpuartIrOneSixteenthWidth = 1, /*!< 1/16 pulse*/
+ kLpuartIrOneThirtysecondsWidth = 2, /*!< 1/32 pulse*/
+ kLpuartIrOneFourthWidth = 3, /*!< 1/4 pulse*/
+} lpuart_ir_tx_pulsewidth_t;
+
+/*! @brief LPUART Configures the number of idle characters that must be received before the IDLE flag is set. */
+typedef enum _lpuart_idle_config {
+ kLpuart_1_IdleChar = 0, /*!< 1 idle character*/
+ kLpuart_2_IdleChar = 1, /*!< 2 idle character*/
+ kLpuart_4_IdleChar = 2, /*!< 4 idle character*/
+ kLpuart_8_IdleChar = 3, /*!< 8 idle character*/
+ kLpuart_16_IdleChar = 4, /*!< 16 idle character*/
+ kLpuart_32_IdleChar = 5, /*!< 32 idle character*/
+ kLpuart_64_IdleChar = 6, /*!< 64 idle character*/
+ kLpuart_128_IdleChar = 7, /*!< 128 idle character*/
+} lpuart_idle_config_t;
+
+/*! @brief LPUART Transmits the CTS Configuration. Configures the source of the CTS input.*/
+typedef enum _lpuart_cts_source {
+ kLpuartCtsSourcePin = 0, /*!< LPUART CTS input is the LPUART_CTS pin.*/
+ kLpuartCtsSourceInvertedReceiverMatch = 1, /*!< LPUART CTS input is the inverted Receiver Match result.*/
+} lpuart_cts_source_t;
+
+/*! @brief LPUART Transmits CTS Source.Configures if the CTS state is checked at the start of each character or only when the transmitter is idle.*/
+typedef enum _lpuart_cts_config {
+ kLpuartCtsSampledOnEachCharacter = 0, /*!< LPUART CTS input is sampled at the start of each character.*/
+ kLpuartCtsSampledOnIdle = 1, /*!< LPUART CTS input is sampled when the transmitter is idle.*/
+} lpuart_cts_config_t;
+
+/*! @brief Structure for idle line configuration settings*/
+typedef struct LpuartIdleLineConfig {
+ unsigned idleLineType : 1; /*!< ILT, Idle bit count start: 0 - after start bit (default),*/
+ /*! 1 - after stop bit */
+ unsigned rxWakeIdleDetect : 1; /*!< RWUID, Receiver Wake Up Idle Detect. IDLE status bit */
+ /*! operation during receive standbyControls whether idle */
+ /*! character that wakes up receiver will also set */
+ /*! IDLE status bit 0 - IDLE status bit doesn't */
+ /*! get set (default), 1 - IDLE status bit gets set*/
+} lpuart_idle_line_config_t;
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the UART functions.
+ */
+typedef enum _lpuart_status_flag {
+ kLpuartTxDataRegEmpty = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_TDRE, /*!< Tx data register empty flag, sets when Tx buffer is empty */
+ kLpuartTxComplete = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_TC, /*!< Transmission complete flag, sets when transmission activity complete */
+ kLpuartRxDataRegFull = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RDRF, /*!< Rx data register full flag, sets when the receive data buffer is full */
+ kLpuartIdleLineDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_IDLE, /*!< Idle line detect flag, sets when idle line detected */
+ kLpuartRxOverrun = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_OR, /*!< Rxr Overrun, sets when new data is received before data is read from receive register */
+ kLpuartNoiseDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_NF, /*!< Rxr takes 3 samples of each received bit. If any of these samples differ, noise flag sets */
+ kLpuartFrameErr = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_FE, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+ kLpuartParityErr = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_PF, /*!< If parity enabled, sets upon parity error detection */
+ kLpuartLineBreakDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_LBKDE, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+ kLpuartRxActiveEdgeDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RXEDGIF, /*!< Rx pin active edge interrupt flag, sets when active edge detected */
+ kLpuartRxActive = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RAF, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ kLpuartNoiseInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | BP_LPUART_DATA_NOISY, /*!< NOISY bit, sets if noise detected in current data word */
+ kLpuartParityErrInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | BP_LPUART_DATA_PARITYE, /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+ kLpuartMatchAddrOne = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_MA1F, /*!< Address one match flag */
+ kLpuartMatchAddrTwo = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_MA2F, /*!< Address two match flag */
+#endif
+} lpuart_status_flag_t;
+
+/*! @brief LPUART interrupt configuration structure, default settings are 0 (disabled)*/
+typedef enum _lpuart_interrupt {
+ kLpuartIntLinBreakDetect = LPUART_BAUD_REG_ID << LPUART_SHIFT | BP_LPUART_BAUD_LBKDIE, /*!< LIN break detect. */
+ kLpuartIntRxActiveEdge = LPUART_BAUD_REG_ID << LPUART_SHIFT | BP_LPUART_BAUD_RXEDGIE, /*!< RX Active Edge. */
+ kLpuartIntTxDataRegEmpty = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_TIE, /*!< Transmit data register empty. */
+ kLpuartIntTxComplete = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_TCIE, /*!< Transmission complete. */
+ kLpuartIntRxDataRegFull = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_RIE, /*!< Receiver data register full. */
+ kLpuartIntIdleLine = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_ILIE, /*!< Idle line. */
+ kLpuartIntRxOverrun = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_ORIE, /*!< Receiver Overrun. */
+ kLpuartIntNoiseErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_NEIE, /*!< Noise error flag. */
+ kLpuartIntFrameErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_FEIE, /*!< Framing error flag. */
+ kLpuartIntParityErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_PEIE, /*!< Parity error flag. */
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+ kLpuartIntMatchAddrOne = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_MA1IE, /*!< Match address one flag. */
+ kLpuartIntMatchAddrTwo = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_MA2IE, /*!< Match address two flag. */
+#endif
+} lpuart_interrupt_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART Common Configurations
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART controller to known state.
+ *
+ * @param baseAddr LPUART base address.
+ */
+void LPUART_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Enables the LPUART transmitter.
+ *
+ * @param baseAddr LPUART base address.
+ */
+void LPUART_HAL_EnableTransmitter(uint32_t baseAddr);
+
+/*!
+ * @brief Disables the LPUART transmitter.
+ *
+ * @param baseAddr LPUART base address
+ */
+static inline void LPUART_HAL_DisableTransmitter(uint32_t baseAddr)
+{
+ BW_LPUART_CTRL_TE(baseAddr, 0);
+}
+
+/*!
+ * @brief Gets the LPUART transmitter enabled/disabled configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @return State of LPUART transmitter enable(1)/disable(0)
+ */
+static inline bool LPUART_HAL_IsTransmitterEnabled(uint32_t baseAddr)
+{
+ return BR_LPUART_CTRL_TE(baseAddr);
+}
+
+/*!
+ * @brief Enables the LPUART receiver.
+ *
+ * @param baseAddr LPUART base address
+ */
+static inline void LPUART_HAL_EnableReceiver(uint32_t baseAddr)
+{
+ BW_LPUART_CTRL_RE(baseAddr, 1);
+}
+
+/*!
+ * @brief Disables the LPUART receiver.
+ *
+ * @param baseAddr LPUART base address
+ */
+static inline void LPUART_HAL_DisableReceiver(uint32_t baseAddr)
+{
+ BW_LPUART_CTRL_RE(baseAddr, 0);
+}
+
+/*!
+ * @brief Gets the LPUART receiver enabled/disabled configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @return State of LPUART receiver enable(1)/disable(0)
+ */
+static inline bool LPUART_HAL_IsReceiverEnabled(uint32_t baseAddr)
+{
+ return BR_LPUART_CTRL_RE(baseAddr);
+}
+
+/*!
+ * @brief Configures the LPUART baud rate.
+ *
+ * In some LPUART instances the user must disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address.
+ * @param sourceClockInHz LPUART source input clock in Hz.
+ * @param desiredBaudRate LPUART desired baud rate.
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz,
+ uint32_t desiredBaudRate);
+
+/*!
+ * @brief Sets the LPUART baud rate modulo divisor.
+ *
+ * @param baseAddr LPUART base address.
+ * @param baudRateDivisor The baud rate modulo division "SBR"
+ */
+static inline void LPUART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint32_t baudRateDivisor)
+{
+ assert ((baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1));
+ BW_LPUART_BAUD_SBR(baseAddr, baudRateDivisor);
+}
+
+#if FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT
+/*!
+ * @brief Sets the LPUART baud rate oversampling ratio (Note: Feature available on select
+ * LPUART instances used together with baud rate programming)
+ * The oversampling ratio should be set between 4x (00011) and 32x (11111). Writing
+ * an invalid oversampling ratio results in an error and is set to a default
+ * 16x (01111) oversampling ratio.
+ * IDisable the transmitter/receiver before calling
+ * this function.
+ *
+ * @param baseAddr LPUART base address.
+ * @param overSamplingRatio The oversampling ratio "OSR"
+ */
+static inline void LPUART_HAL_SetOversamplingRatio(uint32_t baseAddr, uint32_t overSamplingRatio)
+{
+ assert(overSamplingRatio < 0x1F);
+ BW_LPUART_BAUD_OSR(baseAddr, overSamplingRatio);
+}
+#endif
+
+#if FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT
+/*!
+ * @brief Configures the LPUART baud rate both edge sampling (Note: Feature available on select
+ * LPUART instances used with baud rate programming)
+ * When enabled, the received data is sampled on both edges of the baud rate clock.
+ * This must be set when the oversampling ratio is between 4x and 7x.
+ * This function should only be called when the receiver is disabled.
+ *
+ * @param baseAddr LPUART base address.
+ * @param enableBothEdgeSampling Enable (1) or Disable (0) Both Edge Sampling
+ * @return An error code or kStatus_Success
+ */
+static inline void LPUART_HAL_SetBothEdgeSamplingCmd(uint32_t baseAddr, bool enableBothEdgeSampling)
+{
+ BW_LPUART_BAUD_BOTHEDGE(baseAddr, enableBothEdgeSampling);
+}
+#endif
+
+/*!
+ * @brief Configures the number of bits per character in the LPUART controller.
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address.
+ * @param bitCountPerChar Number of bits per char (8, 9, or
+ * 10, depending on the LPUART instance)
+ */
+void LPUART_HAL_SetBitCountPerChar(uint32_t baseAddr, lpuart_bit_count_per_char_t bitCountPerChar);
+
+
+/*!
+ * @brief Configures parity mode in the LPUART controller.
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address.
+ * @param parityModeType Parity mode (enabled, disable, odd, even - see parity_mode_t struct)
+ */
+void LPUART_HAL_SetParityMode(uint32_t baseAddr, lpuart_parity_mode_t parityModeType);
+
+/*!
+ * @brief Configures the number of stop bits in the LPUART controller.
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address.
+ * @param stopBitCount Number of stop bits (1 or 2 - see lpuart_stop_bit_count_t struct)
+ * @return An error code (an unsupported setting in some LPUARTs) or kStatus_Success
+ */
+static inline void LPUART_HAL_SetStopBitCount(uint32_t baseAddr, lpuart_stop_bit_count_t stopBitCount)
+{
+ /* configure the number of stop bits */
+ BW_LPUART_BAUD_SBNS(baseAddr, stopBitCount);
+}
+
+/*!
+ * @brief Configures the transmit and receive inversion control in the LPUART controller.
+ *
+ * This function should only be called when the LPUART is between transmit and receive packets.
+ *
+ * @param baseAddr LPUART base address.
+ * @param rxInvert Enable (1) or disable (0) receive inversion
+ * @param txInvert Enable (1) or disable (0) transmit inversion
+ */
+void LPUART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, uint32_t rxInvert, uint32_t txInvert);
+
+/*@}*/
+
+/*!
+ * @name LPUART Interrupts and DMA
+ * @{
+ */
+
+/*!
+ * @brief Configures the LPUART module interrupts to enable/disable various interrupt sources.
+ *
+ * @param baseAddr LPUART module base address.
+ * @param interrupt LPUART interrupt configuration data.
+ * @param enable true: enable, false: disable.
+ */
+void LPUART_HAL_SetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the LPUART module interrupts is enabled/disabled.
+ *
+ * @param baseAddr LPUART module base address.
+ * @param interrupt LPUART interrupt configuration data.
+ * @return true: enable, false: disable.
+ */
+bool LPUART_HAL_GetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt);
+
+/*!
+ * @brief Enable/Disable the transmission_complete_interrupt.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable true: enable, false: disable.
+ */
+static inline void LPUART_HAL_SetTxDataRegEmptyIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_CTRL_TIE(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the configuration of the transmission_data_register_empty_interrupt enable setting.
+ *
+ * @param baseAddr LPUART base address
+ * @return Bit setting of the interrupt enable bit
+ */
+static inline bool LPUART_HAL_GetTxDataRegEmptyIntCmd(uint32_t baseAddr)
+{
+ return BR_LPUART_CTRL_TIE(baseAddr);
+}
+
+/*!
+ * @brief Enables the rx_data_register_full_interrupt.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable true: enable, false: disable.
+ */
+static inline void LPUART_HAL_SetRxDataRegFullIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_CTRL_RIE(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the configuration of the rx_data_register_full_interrupt enable.
+ *
+ * @param baseAddr LPUART base address
+ * @return Bit setting of the interrupt enable bit
+ */
+static inline bool LPUART_HAL_GetRxDataRegFullIntCmd(uint32_t baseAddr)
+{
+ return BR_LPUART_CTRL_RIE(baseAddr);
+}
+
+#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @brief LPUART configures DMA requests for Transmitter and Receiver.
+ *
+ * @param baseAddr LPUART base address
+ * @param txDmaConfig Transmit DMA request configuration (enable:1 /disable: 0)
+ * @param rxDmaConfig Receive DMA request configuration (enable: 1/disable: 0)
+ */
+void LPUART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig);
+
+/*!
+ * @brief Gets the LPUART Transmit DMA request configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @return Transmit DMA request configuration (enable: 1/disable: 0)
+ */
+static inline bool LPUART_HAL_IsTxDmaEnabled(uint32_t baseAddr)
+{
+ /* TDMAE configures the transmit data register empty flag, S1[TDRE], to */
+ /* generate a DMA request. */
+ return BR_LPUART_BAUD_TDMAE(baseAddr);
+}
+
+/*!
+ * @brief Gets the LPUART receive DMA request configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @return Receives the DMA request configuration (enable: 1/disable: 0).
+ */
+static inline bool LPUART_HAL_IsRxDmaEnabled(uint32_t baseAddr)
+{
+ /* RDMAE configures the receive data register fell flag, S1[RDRF], to */
+ /* generate a DMA request. */
+ return BR_LPUART_BAUD_RDMAE(baseAddr);
+}
+
+#endif
+
+/*@}*/
+
+/*!
+ * @name LPUART Transfer Functions
+ * @{
+ */
+
+/*!
+ * @brief Sends the LPUART 8-bit character.
+ *
+ * @param baseAddr LPUART Instance
+ * @param data data to send (8-bit)
+ */
+static inline void LPUART_HAL_Putchar(uint32_t baseAddr, uint8_t data)
+{
+ /* put 8-bit data into the lpuart data register */
+ HW_LPUART_DATA_WR(baseAddr, data);
+}
+
+/*!
+ * @brief Sends the LPUART 9-bit character.
+ *
+ * @param baseAddr LPUART Instance
+ * @param data data to send (9-bit)
+ */
+void LPUART_HAL_Putchar9(uint32_t baseAddr, uint16_t data);
+
+/*!
+ * @brief Sends the LPUART 10-bit character (Note: Feature available on select LPUART instances).
+ *
+ * @param baseAddr LPUART Instance
+ * @param data data to send (10-bit)
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_Putchar10(uint32_t baseAddr, uint16_t data);
+
+/*!
+ * @brief Gets the LPUART 8-bit character.
+ *
+ * @param baseAddr LPUART base address
+ * @param readData data read from receive (8-bit)
+ */
+void LPUART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData);
+
+/*!
+ * @brief Gets the LPUART 9-bit character.
+ *
+ * @param baseAddr LPUART base address
+ * @param readData data read from receive (9-bit)
+ */
+void LPUART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData);
+
+/*!
+ * @brief Gets the LPUART 10-bit character.
+ *
+ * @param baseAddr LPUART base address
+ * @param readData data read from receive (10-bit)
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_Getchar10(uint32_t baseAddr, uint16_t *readData);
+
+/*!
+ * @brief Configures the number of idle characters that must be received before the IDLE flag is set.
+ *
+ * @param baseAddr LPUART base address
+ * @param idle_config idle characters configuration
+ */
+static inline void LPUART_HAL_IdleConfig(uint32_t baseAddr, lpuart_idle_config_t idleConfig)
+{
+ BW_LPUART_CTRL_IDLECFG(baseAddr, idleConfig);
+}
+
+/*!
+ * @brief Gets the configuration of the number of idle characters that must be received before the IDLE flag is set.
+ *
+ * @param baseAddr LPUART base address
+ * @return idle characters configuration
+ */
+static inline lpuart_idle_config_t LPUART_HAL_GetIdleconfig(uint32_t baseAddr)
+{
+ /* get the receiver idle character config based on the LPUART baseAddr */
+ return (lpuart_idle_config_t)BR_LPUART_CTRL_IDLECFG(baseAddr);
+}
+
+#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+/*!
+ * @brief Configures bit10 (if enabled) or bit9 (if disabled) as the parity bit in the serial
+ * transmission.
+ * This sets LPUARTx_C4[M10] - it is also required to set LPUARTx_C1[M] and LPUARTx_C1[PE]
+ *
+ * @param baseAddr LPUART base address
+ * @param enable Enable (1) to configure bit10 as the parity bit, disable (0) to
+ * configure bit 9 as the parity bit in the serial transmission
+ */
+static inline void LPUART_HAL_ConfigureBit10AsParityBitOperation(uint32_t baseAddr, bool enable)
+{
+ /* to enable the parity bit as the tenth data bit, along with enabling LPUARTx_C4[M10] */
+ /* need to also enable parity and set LPUARTx_CTRL[M] bit */
+ /* assumed that the user has already set the appropriate bits */
+ BW_LPUART_BAUD_M10(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the configuration of bit10 (if enabled) or bit9 (if disabled) as the
+ * parity bit in the serial transmission.
+ *
+ * @param baseAddr LPUART base address
+ * @return Configuration of bit10 (enabled (1)), or bit 9 (disabled (0)) as the
+ * parity bit in the serial transmission
+ */
+static inline bool LPUART_HAL_IsBit10SetAsParityBit(uint32_t baseAddr)
+{
+ /* to see if the parity bit is set as the tenth data bit, */
+ /* return value of LPUARTx_BAUD[M10] */
+ return BR_LPUART_BAUD_M10(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the current data word was received with noise.
+ *
+ * @param baseAddr LPUART base address.
+ * @return The status of the NOISY bit in the LPUART extended data register
+ */
+static inline bool LPUART_HAL_IsCurrentDatawordReceivedWithNoise(uint32_t baseAddr)
+{
+ /* to see if the current dataword was received with noise, */
+ /* return value of LPUARTx_DATA[NOISY] */
+ return BR_LPUART_DATA_NOISY(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the receive buffer is empty.
+ *
+ * @param baseAddr LPUART base address
+ * @return TRUE if the receive-buffer is empty.
+ */
+static inline bool LPUART_HAL_IsReceiveBufferEmpty(uint32_t baseAddr)
+{
+ /* to see if the current state of data buffer is empty, */
+ /* return value of LPUARTx_DATA[RXEMPT] */
+ return BR_LPUART_DATA_RXEMPT(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the previous BUS state was idle before this byte is received.
+ *
+ * @param baseAddr LPUART base address
+ * @return TRUE if the previous BUS state was IDLE.
+ */
+static inline bool LPUART_HAL_ItWasPreviousBusStateIdle(uint32_t baseAddr)
+{
+ /* to see if the current dataword was received with parity error, */
+ /* return value of LPUARTx_DATA[PARITYE] */
+ return BR_LPUART_DATA_IDLINE(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the current data word was received with parity error.
+ *
+ * @param baseAddr LPUART base address
+ * @return The status of the PARITYE bit in the LPUART extended data register
+ */
+static inline bool LPUART_HAL_IsCurrentDatawordReceivedWithParityError(uint32_t baseAddr)
+{
+ /* to see if the current dataword was received with parity error, */
+ /* return value of LPUARTx_DATA[PARITYE] */
+ return BR_LPUART_DATA_PARITYE(baseAddr);
+}
+#endif /* FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS */
+
+/*@}*/
+
+/*!
+ * @name LPUART Special Feature Configurations
+ * @{
+ */
+
+/*!
+ * @brief Configures the LPUART operation in wait mode (operates or stops operations in wait mode).
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param mode LPUART wait mode operation - operates or stops to operate in wait mode.
+ */
+static inline void LPUART_HAL_SetWaitModeOperation(uint32_t baseAddr, lpuart_operation_config_t mode)
+{
+ /* configure lpuart operation in wait mode */
+ /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */
+ BW_LPUART_CTRL_DOZEEN(baseAddr, mode);
+}
+
+/*!
+ * @brief Gets the LPUART operation in wait mode (operates or stops operations in wait mode).
+ *
+ * @param baseAddr LPUART base address
+ * @return LPUART wait mode operation configuration - kLpuartOperates or KLpuartStops in wait mode
+ */
+lpuart_operation_config_t LPUART_HAL_GetWaitModeOperationConfig(uint32_t baseAddr);
+
+/*!
+ * @brief Configures the LPUART loopback operation (enable/disable loopback operation)
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable LPUART loopback mode - disabled (0) or enabled (1)
+ */
+void LPUART_HAL_SedLoopbackCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Configures the LPUART single-wire operation (enable/disable single-wire mode)
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable LPUART loopback mode - disabled (0) or enabled (1)
+ */
+void LPUART_HAL_SetSingleWireCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Configures the LPUART transmit direction while in single-wire mode.
+ *
+ * @param baseAddr LPUART base address
+ * @param direction LPUART single-wire transmit direction - input or output
+ */
+static inline void LPUART_HAL_ConfigureTxdirInSinglewireMode(uint32_t baseAddr,
+ lpuart_singlewire_txdir_t direction)
+{
+ /* configure LPUART transmit direction (input or output) when in single-wire mode */
+ /* it is assumed LPUART is in single-wire mode */
+ BW_LPUART_CTRL_TXDIR(baseAddr, direction);
+}
+
+/*!
+ * @brief Places the LPUART receiver in standby mode.
+ *
+ * In some LPUART instances,
+ * before placing LPUART in standby mode, first determine whether the receiver is set to
+ * wake on idle or whether it is already in idle state.
+ * NOTE that the RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If it is set to wake up an IDLE event and the channel is
+ * already idle, it is possible that the LPUART will discard data since data must be received
+ * (or a LIN break detect) after an IDLE is detected and before IDLE is allowed to reasserted.
+ *
+ * @param baseAddr LPUART base address
+ * @return Error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr);
+
+/*!
+ * @brief Places the LPUART receiver in a normal mode (disable standby mode operation).
+ *
+ * @param baseAddr LPUART base address
+ */
+static inline void LPUART_HAL_PutReceiverInNormalMode(uint32_t baseAddr)
+{
+ /* clear the RWU bit to place receiver into normal mode (disable standby mode) */
+ BW_LPUART_CTRL_RWU(baseAddr, 0);
+}
+
+/*!
+ * @brief Checks whether the LPUART receiver is in a standby mode.
+ *
+ * @param baseAddr LPUART base address
+ * @return LPUART in normal more (0) or standby (1)
+ */
+static inline bool LPUART_HAL_IsReceiverInStandby(uint32_t baseAddr)
+{
+ /* return the RWU bit setting (0 - normal more, 1 - standby) */
+ return BR_LPUART_CTRL_RWU(baseAddr);
+}
+
+/*!
+ * @brief LPUART receiver wakeup method (idle line or addr-mark) from standby mode
+ *
+ * @param baseAddr LPUART base address
+ * @param method LPUART wakeup method: 0 - Idle-line wake (default), 1 - addr-mark wake
+ */
+static inline void LPUART_HAL_SelectReceiverWakeupMethod(uint32_t baseAddr, lpuart_wakeup_method_t method)
+{
+ /* configure the WAKE bit for idle line wake or address mark wake */
+ BW_LPUART_CTRL_WAKE(baseAddr, method);
+}
+
+/*!
+ * @brief Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode.
+ *
+ * @param baseAddr LPUART base address
+ * @return LPUART wakeup method: kLpuartIdleLineWake: 0 - Idle-line wake (default),
+ * kLpuartAddrMarkWake: 1 - addr-mark wake
+ */
+lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr);
+
+/*!
+ * @brief LPUART idle-line detect operation configuration (idle line bit-count start and wake
+ * up affect on IDLE status bit).
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param config LPUART configuration data for idle line detect operation
+ */
+void LPUART_HAL_ConfigureIdleLineDetect(uint32_t baseAddr,
+ const lpuart_idle_line_config_t *config);
+
+/*!
+ * @brief LPUART break character transmit length configuration
+ * In some LPUART instances, the user should disable the transmitter before calling
+ * this function. Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param length LPUART break character length setting: 0 - minimum 10-bit times (default),
+ * 1 - minimum 13-bit times
+ */
+static inline void LPUART_HAL_SetBreakCharTransmitLength(uint32_t baseAddr,
+ lpuart_break_char_length_t length)
+{
+ /* Configure BRK13 - Break Character transmit length configuration */
+ /* LPUART break character length setting: */
+ /* 0 - minimum 10-bit times (default), */
+ /* 1 - minimum 13-bit times */
+ BW_LPUART_STAT_BRK13(baseAddr, length);
+}
+
+/*!
+ * @brief LPUART break character detect length configuration
+ *
+ * @param baseAddr LPUART base address
+ * @param length LPUART break character length setting: 0 - minimum 10-bit times (default),
+ * 1 - minimum 13-bit times
+ */
+static inline void LPUART_HAL_SetBreakCharDetectLength(uint32_t baseAddr,
+ lpuart_break_char_length_t length)
+{
+ /* Configure LBKDE - Break Character detect length configuration */
+ /* LPUART break character length setting: */
+ /* 0 - minimum 10-bit times (default), */
+ /* 1 - minimum 13-bit times */
+ BW_LPUART_STAT_LBKDE(baseAddr, length);
+}
+
+/*!
+ * @brief LPUART transmit sends break character configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable LPUART normal/queue break char - disabled (normal mode, default: 0) or
+ * enabled (queue break char: 1)
+ */
+static inline void LPUART_HAL_QueueBreakCharToSend(uint32_t baseAddr, bool enable)
+{
+ /* Configure SBK - Send Break */
+ /* LPUART send break character setting: */
+ /* 0 - normal transmitter operation, */
+ /* 1 - Queue break character(s) to be sent */
+
+ BW_LPUART_CTRL_SBK(baseAddr, enable);
+}
+
+/*!
+ * @brief LPUART configures match address mode control (Note: Feature available on
+ * select LPUART instances)
+ *
+ * @param baseAddr LPUART base address
+ * @param matchAddrMode1 MAEN1: match address mode1 enable (1)/disable (0)
+ * @param matchAddrMode2 MAEN2: match address mode2 enable (1)/disable (0)
+ * @param matchAddrValue1 MA: match address value to program into match address register 1
+ * @param matchAddrValue2 MA: match address value to program into match address register 2
+ * @param config MATCFG: Configures the match addressing mode used.
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_SetMatchAddressOperation(uint32_t baseAddr,
+ bool matchAddrMode1, bool matchAddrMode2,
+ uint8_t matchAddrValue1, uint8_t matchAddrValue2,
+ lpuart_match_config_t config);
+
+/*!
+ * @brief LPUART sends the MSB first configuration (Note: Feature available on select LPUART instances)
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable MSB first mode configuration, MSBF: 0 - LSB (default, feature disabled),
+ * 1 - MSB (feature enabled)
+ */
+static inline void LPUART_HAL_ConfigureSendMsbFirstOperation(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_STAT_MSBF(baseAddr, enable);
+}
+
+/*!
+ * @brief LPUART disables re-sync of received data configuration (Note: Feature available on
+ * select LPUART instances).
+ *
+ * @param baseAddr LPUART base address
+ * @param enable disable re-sync of received data word configuration, RESYNCDIS:
+ * 0 - re-sync of received data word (default, feature disabled),
+ * 1 - disable the re-sync (feature enabled)
+ */
+static inline void LPUART_HAL_ConfigureReceiveResyncDisableOperation(uint32_t baseAddr, bool enable)
+{
+ /* When set, disables the resynchronization of the received data word when a data */
+ /* one followed by data zero transition is detected. This bit should only be changed */
+ /* when the receiver is disabled. */
+ BW_LPUART_BAUD_RESYNCDIS(baseAddr, enable);
+}
+
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+/*!
+ * @brief Transmits the CTS source configuration.
+ *
+ * @param baseAddr LPUART base address
+ * @param source LPUART CTS source
+ */
+static inline void LPUART_HAL_SelectSourceCts(uint32_t baseAddr, lpuart_cts_source_t source)
+{
+ /* Set TXCTSSRC */
+ BW_LPUART_MODIR_TXCTSSRC(baseAddr, source);
+}
+
+/*!
+ * @brief Transmits the CTS configuration.
+ * Note: configures if the CTS state is checked at the start of each character or only when the transmitter is idle.
+ *
+ * @param baseAddr LPUART base address
+ * @param config LPUART CTS configuration
+ */
+static inline void LPUART_HAL_ConfigureCts(uint32_t baseAddr, lpuart_cts_config_t config)
+{
+ /* Set TXCTSC */
+ BW_LPUART_MODIR_TXCTSC(baseAddr, config);
+}
+
+/*!
+ * @brief Enables the receiver request-to-send.
+ * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE).
+ *
+ * @param baseAddr LPUART base address
+ * @param enable disable(0)/enable(1) receiver RTS.
+ */
+
+static inline void LPUART_HAL_SetReceiverRts(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_MODIR_RXRTSE(baseAddr, enable);
+}
+
+/*!
+ * @brief Enables the transmitter request-to-send.
+ * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE).
+ *
+ * @param baseAddr LPUART base address
+ * @param enable disable(0)/enable(1) transmitter RTS.
+ */
+static inline void LPUART_HAL_SetTransmitterRtsCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_MODIR_TXRTSE(baseAddr, enable);
+}
+
+/*!
+ * @brief Configures the transmitter RTS polarity: 0=active low, 1=active high.
+ *
+ * @param baseAddr LPUART base address
+ * @param polarity Settings to choose RTS polarity.
+ */
+static inline void LPUART_HAL_SetTransmitterRtsPolarityMode(uint32_t baseAddr, bool polarity)
+{
+ /* Configure the transmitter rts polarity: 0=active low, 1=active high */
+ BW_LPUART_MODIR_TXRTSPOL(baseAddr, polarity);
+}
+
+/*!
+ * @brief Enables the transmitter clear-to-send.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable disable(0)/enable(1) transmitter CTS.
+ */
+static inline void LPUART_HAL_SetTransmitterCtsCmd(uint32_t baseAddr, bool enable)
+{
+ BW_LPUART_MODIR_TXCTSE(baseAddr, enable);
+}
+
+#endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */
+
+#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT
+/*!
+ * @brief Configures the LPUART infrared operation.
+ *
+ * @param baseAddr LPUART base address
+ * @param enable Enable (1) or disable (0) the infrared operation
+ * @param pulseWidth The transmit narrow pulse width of type lpuart_ir_tx_pulsewidth_t
+ */
+void LPUART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable,
+ lpuart_ir_tx_pulsewidth_t pulseWidth);
+#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */
+
+/*@}*/
+
+/*!
+ * @name LPUART Status Flags
+ * @{
+ */
+
+/*!
+ * @brief LPUART get status flag
+ *
+ * @param baseAddr LPUART base address
+ * @param statusFlag The status flag to query
+ */
+bool LPUART_HAL_GetStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag);
+
+/*!
+ * @brief Gets the LPUART Transmit data register empty flag.
+ *
+ * This function returns the state of the LPUART Transmit data register empty flag.
+ *
+ * @param baseAddr LPUART module base address.
+ * @return The status of Transmit data register empty flag, which is set when transmit buffer
+ * is empty.
+ */
+static inline bool LPUART_HAL_IsTxDataRegEmpty(uint32_t baseAddr)
+{
+ /* return status condition of TDRE flag */
+ return BR_LPUART_STAT_TDRE(baseAddr);
+}
+
+/*!
+ * @brief Gets the LPUART receive data register full flag.
+ *
+ * @param baseAddr LPUART base address
+ * @return Status of the receive data register full flag, sets when the receive data buffer is full.
+ */
+static inline bool LPUART_HAL_IsRxDataRegFull(uint32_t baseAddr)
+{
+ /* return status condition of RDRF flag */
+ return BR_LPUART_STAT_RDRF(baseAddr);
+}
+
+/*!
+ * @brief Gets the LPUART transmission complete flag.
+ *
+ * @param baseAddr LPUART base address
+ * @return Status of Transmission complete flag, sets when transmitter is idle
+ * (transmission activity complete)
+ */
+static inline bool LPUART_HAL_IsTxComplete(uint32_t baseAddr)
+{
+ /* return status condition of TC flag */
+ return BR_LPUART_STAT_TC(baseAddr);
+}
+
+/*!
+ * @brief LPUART clears an individual status flag (see lpuart_status_flag_t for list of status bits).
+ *
+ * @param baseAddr LPUART base address
+ * @param statusFlag Desired LPUART status flag to clear
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_ClearStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag);
+
+/*!
+ * @brief LPUART clears ALL status flags.
+ *
+ * @param baseAddr LPUART base address
+ */
+void LPUART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* MBED_NO_LPUART */
+
+#endif /* __FSL_LPUART_HAL_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,705 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_MCG_FEATURES_H__) +#define __FSL_MCG_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (1) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (0) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (1) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (1) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (1) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (0) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (1) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (1) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (1) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (1) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (1) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (1) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (1) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (1) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (0) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (0) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (0) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (0) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (0) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (0) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (0) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) +#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (1) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (1) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ + #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) + /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ + #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ + #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) + /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ + #define FSL_FEATURE_MCG_HAS_RTC_32K (0) + /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_PLL1 (0) + /* @brief Has 48MHz internal oscillator. */ + #define FSL_FEATURE_MCG_HAS_IRC_48M (0) + /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ + #define FSL_FEATURE_MCG_HAS_OSC1 (0) + /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ + #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) + /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ + #define FSL_FEATURE_MCG_HAS_LOLRE (1) + /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ + #define FSL_FEATURE_MCG_USE_OSCSEL (0) + /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ + #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) + /* @brief TBD */ + #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) + /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL (1) + /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ + #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) + /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ + #define FSL_FEATURE_MCG_HAS_FLL (1) + /* @brief Has PLL external to MCG (register C9). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) + /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ + #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) + /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) + /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ + #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) + /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ + #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) + /* @brief Has external clock monitor (register bit C6[CME]). */ + #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) + /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ + #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) + /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ + #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_MCG_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcg_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetFllRefclk
+ * Description : Internal function to find the fll reference clock
+ * This is an internal function to get the fll reference clock. The returned
+ * value will be used for other APIs to calculate teh fll and other clock value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetFllRefClk(uint32_t baseAddr)
+{
+ uint32_t mcgffclk;
+ uint8_t divider;
+
+ if (CLOCK_HAL_GetInternalRefSelMode(baseAddr) == kMcgInternalRefClkSrcExternal)
+ {
+ /* External reference clock is selected */
+#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for ffclk */
+
+ int32_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr);
+ if (oscsel == kMcgOscselOsc)
+ {
+#if FSL_FEATURE_MCG_HAS_OSC1
+ /* System oscillator 0 drives MCG clock */
+ mcgffclk = CPU_XTAL0_CLK_HZ;
+#else
+ /* System oscillator 0 drives MCG clock */
+ mcgffclk = CPU_XTAL_CLK_HZ;
+#endif
+ }
+ else if (oscsel == kMcgOscselRtc)
+ {
+ /* RTC 32 kHz oscillator drives MCG clock */
+ mcgffclk = CPU_XTAL32k_CLK_HZ;
+ }
+#if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: if IRC 48M exists*/
+ else if (oscsel == kMcgOscselIrc)
+ {
+ /* IRC 48Mhz oscillator drives MCG clock */
+ mcgffclk = CPU_INT_IRC_CLK_HZ;
+ }
+#endif
+ else
+ {
+ mcgffclk = 0;
+ }
+
+#else /* case 2: use default osc0*/
+
+ /* System oscillator 0 drives MCG clock */
+ mcgffclk = CPU_XTAL_CLK_HZ;
+
+#endif
+
+ divider = (uint8_t)(1u << CLOCK_HAL_GetFllExternalRefDivider(baseAddr));
+
+ /* Calculate the divided FLL reference clock*/
+ mcgffclk = (mcgffclk / divider);
+
+ if ((CLOCK_HAL_GetRange0Mode(baseAddr) != kMcgFreqRangeSelLow)
+#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for ffclk */
+ && (CLOCK_HAL_GetOscselMode(baseAddr) != kMcgOscselRtc))
+#else
+ )
+#endif
+ {
+ /* If high range is enabled, additional 32 divider is active*/
+ mcgffclk = (mcgffclk >> kMcgConstant5);
+ }
+ }
+ else
+ {
+ /* The slow internal reference clock is selected */
+ mcgffclk = CPU_INT_SLOW_CLK_HZ;
+ }
+ return mcgffclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetFllclk
+ * Description : Get the current mcg fll clock
+ * This function will return the mcgfllclk value in frequency(hz) based on
+ * current mcg configurations and settings. Fll should be properly configured
+ * in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetFllClk(uint32_t baseAddr)
+{
+ uint32_t mcgfllclk;
+ mcg_dmx32_select_t dmx32;
+ mcg_digital_controlled_osc_range_select_t drstDrs;
+
+ mcgfllclk = CLOCK_HAL_GetFllRefClk(baseAddr);
+
+ /* Select correct multiplier to calculate the MCG output clock */
+ dmx32 = CLOCK_HAL_GetDmx32(baseAddr);
+ drstDrs = CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr);
+
+ switch (drstDrs)
+ {
+ case kMcgDigitalControlledOscRangeSelLow: /* Low frequency range */
+ switch (dmx32)
+ {
+ case kMcgDmx32Default: /* DCO has a default range of 25% */
+ mcgfllclk *= kMcgConstant640;
+ break;
+ case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
+ mcgfllclk *= kMcgConstant732;
+ break;
+ default:
+ break;
+ }
+ break;
+ case kMcgDigitalControlledOscRangeSelMid: /* Mid frequency range*/
+ switch (dmx32)
+ {
+ case kMcgDmx32Default: /* DCO has a default range of 25% */
+ mcgfllclk *= kMcgConstant1280;
+ break;
+ case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
+ mcgfllclk *= kMcgConstant1464;
+ break;
+ default:
+ break;
+ }
+ break;
+ case kMcgDigitalControlledOscRangeSelMidHigh: /* Mid-High frequency range */
+ switch (dmx32)
+ {
+ case kMcgDmx32Default: /* DCO has a default range of 25% */
+ mcgfllclk *= kMcgConstant1920;
+ break;
+ case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
+ mcgfllclk *= kMcgConstant2197;
+ break;
+ default:
+ break;
+ }
+ break;
+ case kMcgDigitalControlledOscRangeSelHigh: /* High frequency range */
+ switch (dmx32)
+ {
+ case kMcgDmx32Default: /* DCO has a default range of 25% */
+ mcgfllclk *= kMcgConstant2560;
+ break;
+ case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
+ mcgfllclk *= kMcgConstant2929;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return mcgfllclk;
+}
+#if FSL_FEATURE_MCG_HAS_PLL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll0clk
+ * Description : Get the current mcg pll/pll0 clock
+ * This function will return the mcgpllclk/mcgpll0 value in frequency(hz) based
+ * on current mcg configurations and settings. PLL/PLL0 should be properly
+ * configured in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll0Clk(uint32_t baseAddr)
+{
+ uint32_t mcgpll0clk;
+ uint8_t divider;
+
+ /* PLL(0) output is selected*/
+#if FSL_FEATURE_MCG_USE_PLLREFSEL /* case 1 use pllrefsel to select pll*/
+
+ if (CLOCK_HAL_GetPllRefSel0Mode(baseAddr) != kMcgPllExternalRefClkSelOsc0)
+ {
+ /* OSC1 clock source used as an external reference clock */
+ mcgpll0clk = CPU_XTAL1_CLK_HZ;
+ }
+ else
+ {
+ /* OSC0 clock source used as an external reference clock*/
+ mcgpll0clk = CPU_XTAL0_CLK_HZ;
+ }
+#else
+#if FSL_FEATURE_MCG_USE_OSCSEL /* case 2: use oscsel for pll */
+ mcg_oscsel_select_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr);
+ if (oscsel == kMcgOscselOsc) /* case 2.1: OSC0 */
+ {
+ /* System oscillator drives MCG clock*/
+ mcgpll0clk = CPU_XTAL_CLK_HZ;
+ }
+ else if (oscsel == kMcgOscselRtc) /* case 2.2: RTC */
+ {
+ /* RTC 32 kHz oscillator drives MCG clock*/
+ mcgpll0clk = CPU_XTAL32k_CLK_HZ;
+ }
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+ else if (oscsel == kMcgOscselIrc) /* case 2.3: IRC 48M */
+ {
+ /* IRC 48Mhz oscillator drives MCG clock*/
+ mcgpll0clk = CPU_INT_IRC_CLK_HZ;
+ }
+ else
+ {
+ mcgpll0clk = 0;
+ }
+#endif
+#else /* case 3: use default osc0*/
+ /* System oscillator drives MCG clock*/
+ mcgpll0clk = CPU_XTAL_CLK_HZ;
+#endif
+#endif
+
+ divider = (kMcgConstant1 + CLOCK_HAL_GetPllExternalRefDivider0(baseAddr));
+
+ /* Calculate the PLL reference clock*/
+ mcgpll0clk /= divider;
+ divider = (CLOCK_HAL_GetVoltCtrlOscDivider0(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+
+ /* Calculate the MCG output clock*/
+ mcgpll0clk = (mcgpll0clk * divider);
+
+ return mcgpll0clk;
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll1Clk
+ * Description : Get the current mcg pll1 clock
+ * This function will return the mcgpll1clk value in frequency(hz) based
+ * on current mcg configurations and settings. PLL1 should be properly configured
+ * in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll1Clk(uint32_t baseAddr)
+{
+ uint32_t mcgpll1clk;
+ uint8_t divider;
+
+ if (CLOCK_HAL_GetPllRefSel1Mode(baseAddr) != kMcgPllExternalRefClkSelOsc0)
+ {
+ /* OSC1 clock source used as an external reference clock*/
+ mcgpll1clk = CPU_XTAL1_CLK_HZ;
+ }
+ else
+ {
+ /* OSC0 clock source used as an external reference clock*/
+ mcgpll1clk = CPU_XTAL0_CLK_HZ;
+ }
+
+ divider = (kMcgConstant1 + CLOCK_HAL_GetPllExternalRefDivider1(baseAddr));
+
+ /* Calculate the PLL reference clock*/
+ mcgpll1clk /= divider;
+ divider = (CLOCK_HAL_GetVoltCtrlOscDivider1(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+
+ /* Calculate the MCG output clock*/
+ mcgpll1clk = ((mcgpll1clk * divider) >> kMcgConstant1); /* divided by 2*/
+ return mcgpll1clk;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetIrclk
+ * Description : Get the current mcg ir clock
+ * This function will return the mcgirclk value in frequency(hz) based
+ * on current mcg configurations and settings. It will not check if the
+ * mcgirclk is enabled or not, just calculate and return the value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetInternalRefClk(uint32_t baseAddr)
+{
+ int32_t mcgirclk;
+ if (CLOCK_HAL_GetInternalRefClkSelMode(baseAddr) == kMcgInternalRefClkSelSlow)
+ {
+ /* Slow internal reference clock selected*/
+ mcgirclk = CPU_INT_SLOW_CLK_HZ;
+ }
+ else
+ {
+ mcgirclk = CPU_INT_FAST_CLK_HZ / (1 << CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr));
+ }
+ return mcgirclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutclk
+ * Description : Get the current mcg out clock
+ * This function will return the mcgoutclk value in frequency(hz) based on
+ * current mcg configurations and settings. The configuration should be
+ * properly done in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetOutClk(uint32_t baseAddr)
+{
+ /* Variable to store output clock frequency of the MCG module*/
+ uint32_t mcgoutclk = 0;
+
+ if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelOut)
+ {
+#if FSL_FEATURE_MCG_HAS_PLL
+ /* Output of FLL or PLL is selected*/
+ if (CLOCK_HAL_GetPllSelMode(baseAddr) == kMcgPllSelFll)
+ {
+ /* FLL is selected*/
+ mcgoutclk = CLOCK_HAL_GetFllClk(baseAddr);
+ }
+ else
+ {
+ /* PLL is selected*/
+#if FSL_FEATURE_MCG_HAS_PLL1
+ if (CLOCK_HAL_GetPllClkSelMode(baseAddr) != kMcgPllClkSelPll0)
+ {
+ /* PLL1 output is selected*/
+ mcgoutclk = CLOCK_HAL_GetPll1Clk(baseAddr);
+ }
+ else
+ {
+ mcgoutclk = CLOCK_HAL_GetPll0Clk(baseAddr);
+ }
+#else
+ mcgoutclk = CLOCK_HAL_GetPll0Clk(baseAddr);
+#endif // FSL_FEATURE_MCG_HAS_PLL1
+ }
+#else
+ mcgoutclk = CLOCK_HAL_GetFllClk(baseAddr);
+#endif // FSL_FEATURE_MCG_HAS_PLL
+ }
+ else if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelInternal)
+ {
+ /* Internal reference clock is selected*/
+ mcgoutclk = CLOCK_HAL_GetInternalRefClk(baseAddr);
+ }
+ else if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelExternal)
+ {
+ /* External reference clock is selected*/
+
+#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for outclock */
+
+ uint32_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr);
+ if (oscsel == kMcgOscselOsc)
+ {
+#if FSL_FEATURE_MCG_HAS_OSC1
+ /* System oscillator drives MCG clock*/
+ mcgoutclk = CPU_XTAL0_CLK_HZ;
+#else
+ /* System oscillator drives MCG clock*/
+ mcgoutclk = CPU_XTAL_CLK_HZ;
+#endif
+ }
+ else if (oscsel == kMcgOscselRtc)
+ {
+ /* RTC 32 kHz oscillator drives MCG clock*/
+ mcgoutclk = CPU_XTAL32k_CLK_HZ;
+ }
+#if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: IRC 48M exists*/
+ else if (oscsel == kMcgOscselIrc)
+ {
+ /* IRC 48Mhz oscillator drives MCG clock*/
+ mcgoutclk = CPU_INT_IRC_CLK_HZ;
+ }
+ else
+ {
+ mcgoutclk = 0;
+ }
+#endif
+
+#else /* case 2: use default osc0*/
+ /* System oscillator drives MCG clock*/
+ mcgoutclk = CPU_XTAL_CLK_HZ;
+#endif
+ }
+ else
+ {
+ /* Reserved value*/
+ return mcgoutclk;
+ }
+ return mcgoutclk;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,2184 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_MCG_HAL_H__)
+#define __FSL_MCG_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_features.h"
+
+/*! @addtogroup mcg_hal*/
+/*! @{*/
+
+/*! @file fsl_mcg_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief MCG constant definitions*/
+enum _mcg_constant
+{
+ kMcgConstant0 = (0u),
+ kMcgConstant1 = (1u),
+ kMcgConstant2 = (2u),
+ kMcgConstant3 = (3u),
+ kMcgConstant4 = (4u),
+ kMcgConstant5 = (5u),
+ kMcgConstant32 = (32u),
+
+ kMcgConstant640 = (640u),
+ kMcgConstant1280 = (1280u),
+ kMcgConstant1920 = (1920u),
+ kMcgConstant2560 = (2560u),
+ kMcgConstant732 = (732u),
+ kMcgConstant1464 = (1464u),
+ kMcgConstant2197 = (2197u),
+ kMcgConstant2929 = (2929u),
+
+ kMcgConstantHex20 = (0x20u),
+ kMcgConstantHex40 = (0x40u),
+ kMcgConstantHex60 = (0x60u),
+ kMcgConstantHex80 = (0x80u),
+ kMcgConstantHexA0 = (0xA0u),
+ kMcgConstantHexC0 = (0xC0u),
+ kMcgConstantHexE0 = (0xE0u),
+
+ kMcgConstant2000 = (2000u),
+ kMcgConstant3000 = (3000u),
+ kMcgConstant4000 = (4000u),
+
+ kMcgConstant10000 = (10000u),
+ kMcgConstant30000 = (30000u),
+ kMcgConstant31250 = (31250u),
+ kMcgConstant39063 = (39063u),
+ kMcgConstant40000 = (40000u),
+
+ kMcgConstant1250000 = (1250000u),
+ kMcgConstant2500000 = (2500000u),
+ kMcgConstant3000000 = (3000000u),
+ kMcgConstant5000000 = (5000000u),
+ kMcgConstant8000000 = (8000000u),
+
+ kMcgConstant10000000 = (10000000u),
+ kMcgConstant20000000 = (20000000u),
+ kMcgConstant25000000 = (25000000u),
+ kMcgConstant32000000 = (32000000u),
+ kMcgConstant40000000 = (40000000u),
+ kMcgConstant50000000 = (50000000u),
+ kMcgConstant60000000 = (60000000u),
+ kMcgConstant75000000 = (75000000u),
+ kMcgConstant80000000 = (80000000u),
+
+ kMcgConstant100000000 = (100000000u),
+ kMcgConstant180000000 = (180000000u),
+ kMcgConstant360000000 = (360000000u)
+};
+
+/*! @brief MCG clock source select */
+typedef enum _mcg_clock_select
+{
+ kMcgClkSelOut, /* Output of FLL or PLLCS is selected(depends on PLLS bit) */
+ kMcgClkSelInternal, /* Internal reference clock is selected */
+ kMcgClkSelExternal, /* External reference clock is selected */
+ kMcgClkSelReserved
+} mcg_clock_select_t;
+
+/*! @brief MCG internal reference clock source select */
+typedef enum _mcg_internal_ref_clock_source
+{
+ kMcgInternalRefClkSrcExternal, /* External reference clock is selected */
+ kMcgInternalRefClkSrcSlow /* The slow internal reference clock is selected */
+} mcg_internal_ref_clock_source_t;
+
+/*! @brief MCG frequency range select */
+typedef enum _mcg_freq_range_select
+{
+ kMcgFreqRangeSelLow, /* Low frequency range selected for the crystal OSC */
+ kMcgFreqRangeSelHigh, /* High frequency range selected for the crystal OSC */
+ kMcgFreqRangeSelVeryHigh, /* Very High frequency range selected for the crystal OSC */
+ kMcgFreqRangeSelVeryHigh1 /* Very High frequency range selected for the crystal OSC */
+} mcg_freq_range_select_t;
+
+/*! @brief MCG high gain oscillator select */
+typedef enum _mcg_high_gain_osc_select
+{
+ kMcgHighGainOscSelLow, /* Configure crystal oscillator for low-power operation */
+ kMcgHighGainOscSelHigh /* Configure crystal oscillator for high-gain operation */
+} mcg_high_gain_osc_select_t;
+
+/*! @brief MCG high gain oscillator select */
+typedef enum _mcg_external_ref_clock_select
+{
+ kMcgExternalRefClkSelExternal, /* External reference clock requested */
+ kMcgExternalRefClkSelOsc /* Oscillator requested */
+} mcg_external_ref_clock_select_t;
+
+/*! @brief MCG low power select */
+typedef enum _mcg_low_power_select
+{
+ kMcgLowPowerSelNormal, /* FLL (or PLL) is not disabled in bypass modes */
+ kMcgLowPowerSelLowPower /* FLL (or PLL) is disabled in bypass modes (lower power) */
+} mcg_low_power_select_t;
+
+/*! @brief MCG internal reference clock select */
+typedef enum _mcg_internal_ref_clock_select
+{
+ kMcgInternalRefClkSelSlow, /* Slow internal reference clock selected */
+ kMcgInternalRefClkSelFast /* Fast internal reference clock selected */
+} mcg_internal_ref_clock_select_t;
+
+/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
+typedef enum _mcg_dmx32_select
+{
+ kMcgDmx32Default, /* DCO has a default range of 25% */
+ kMcgDmx32Fine /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
+} mcg_dmx32_select_t;
+
+/*! @brief MCG DCO range select */
+typedef enum _mcg_digital_controlled_osc_range_select
+{
+ kMcgDigitalControlledOscRangeSelLow, /* Low frequency range */
+ kMcgDigitalControlledOscRangeSelMid, /* Mid frequency range*/
+ kMcgDigitalControlledOscRangeSelMidHigh, /* Mid-High frequency range */
+ kMcgDigitalControlledOscRangeSelHigh /* High frequency range */
+} mcg_digital_controlled_osc_range_select_t;
+
+/*! @brief MCG PLL external reference clock select */
+typedef enum _mcg_pll_external_ref_clk_select
+{
+ kMcgPllExternalRefClkSelOsc0, /* Selects OSC0 clock source as its external reference clock */
+ kMcgPllExternalRefClkSelOsc1 /* Selects OSC1 clock source as its external reference clock */
+} mcg_pll_external_ref_clk_select_t;
+
+/*! @brief MCG PLL select */
+typedef enum _mcg_pll_select
+{
+ kMcgPllSelFll, /* FLL is selected */
+ kMcgPllSelPllClkSel /* PLLCS output clock is selected */
+} mcg_pll_select_t;
+
+/*! @brief MCG loss of lock status */
+typedef enum _mcg_loss_of_lock_status
+{
+ kMcgLossOfLockNotLost, /* PLL has not lost lock since LOLS 0 was last cleared */
+ kMcgLossOfLockLost /* PLL has lost lock since LOLS 0 was last cleared */
+} mcg_loss_of_lock_status_t;
+
+/*! @brief MCG lock status */
+typedef enum _mcg_lock_status
+{
+ kMcgLockUnlocked, /* PLL is currently unlocked */
+ kMcgLockLocked /* PLL is currently locked */
+} mcg_lock_status_t;
+
+/*! @brief MCG clock status */
+typedef enum _mcg_pll_stat_status
+{
+ kMcgPllStatFll, /* Source of PLLS clock is FLL clock */
+ kMcgPllStatPllClkSel /* Source of PLLS clock is PLLCS output clock */
+} mcg_pll_stat_status_t;
+
+/*! @brief MCG iref status */
+typedef enum _mcg_internal_ref_status
+{
+ kMcgInternalRefStatExternal, /* FLL reference clock is the external reference clock */
+ kMcgInternalRefStatInternal /* FLL reference clock is the internal reference clock */
+} mcg_internal_ref_status_t;
+
+/*! @brief MCG clock mode status */
+typedef enum _mcg_clk_stat_status
+{
+ kMcgClkStatFll, /* Output of the FLL is selected (reset default) */
+ kMcgClkStatInternalRef, /* Internal reference clock is selected */
+ kMcgClkStatExternalRef, /* External reference clock is selected */
+ kMcgClkStatPll /* Output of the PLL is selected */
+} mcg_clk_stat_status_t;
+
+/*! @brief MCG ircst status */
+typedef enum _mcg_internal_ref_clk_status
+{
+ kMcgInternalRefClkStatSlow, /* internal reference clock is the slow clock (32 kHz IRC) */
+ kMcgInternalRefClkStatFast /* internal reference clock is the fast clock (2 MHz IRC) */
+} mcg_internal_ref_clk_status_t;
+
+/*! @brief MCG auto trim fail status */
+typedef enum _mcg_auto_trim_machine_fail_status
+{
+ kMcgAutoTrimMachineNormal, /* Automatic Trim Machine completed normally */
+ kMcgAutoTrimMachineFail /* Automatic Trim Machine failed */
+} mcg_auto_trim_machine_fail_status_t;
+
+/*! @brief MCG loss of clock status */
+typedef enum _mcg_locs0_status
+{
+ kMcgLocs0NotOccured, /* Loss of OSC0 has not occurred */
+ kMcgLocs0Occured /* Loss of OSC0 has occurred */
+} mcg_locs0_status_t;
+
+/*! @brief MCG Automatic Trim Machine Select */
+typedef enum _mcg_auto_trim_machine_select
+{
+ kMcgAutoTrimMachineSel32k, /* 32 kHz Internal Reference Clock selected */
+ kMcgAutoTrimMachineSel4m /* 4 MHz Internal Reference Clock selected */
+} mcg_auto_trim_machine_select_t;
+
+/*! @brief MCG OSC Clock Select */
+typedef enum _mcg_oscsel_select
+{
+ kMcgOscselOsc, /* Selects System Oscillator (OSCCLK) */
+ kMcgOscselRtc, /* Selects 32 kHz RTC Oscillator */
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+ kMcgOscselIrc /* Selects 48 MHz IRC Oscillator */
+#endif
+} mcg_oscsel_select_t;
+
+/*! @brief MCG loss of clock status */
+typedef enum _mcg_loss_of_clk1_status
+{
+ kMcgLossOfClk1NotOccured, /* Loss of RTC has not occurred */
+ kMcgLossOfClk1Occured /* Loss of RTC has occurred */
+} mcg_loss_of_clk1_status_t;
+
+/*! @brief MCG PLLCS select */
+typedef enum _mcg_pll_clk_select
+{
+ kMcgPllClkSelPll0, /* PLL0 output clock is selected */
+ kMcgPllClkSelPll1, /* PLL1 output clock is selected */
+} mcg_pll_clk_select_t;
+
+/*! @brief MCG loss of clock status */
+typedef enum _mcg_locs2_status
+{
+ kMcgLocs2NotOccured, /* Loss of OSC1 has not occurred */
+ kMcgLocs2Occured /* Loss of OSC1 has occurred */
+} mcg_locs2_status_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name MCG out clock access API*/
+/*@{*/
+
+/*!
+ * @brief Gets the current MCG FLL clock.
+ *
+ * This function returns the mcgfllclk value in frequency(Hertz) based on the
+ * current MCG configurations and settings. FLL should be properly configured
+ * in order to get the valid value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of the mcgpllclk.
+ */
+uint32_t CLOCK_HAL_GetFllRefClk(uint32_t baseAddr);
+
+/*!
+ * @brief Gets the current MCG FLL clock.
+ *
+ * This function returns the mcgfllclk value in frequency(Hertz) based on the
+ * current MCG configurations and settings. FLL should be properly configured
+ * in order to get the valid value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of the mcgpllclk.
+ */
+uint32_t CLOCK_HAL_GetFllClk(uint32_t baseAddr);
+
+/*!
+ * @brief Gets the current MCG PLL/PLL0 clock.
+ *
+ * This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based
+ * on the current MCG configurations and settings. PLL/PLL0 should be properly
+ * configured in order to get the valid value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.
+ */
+uint32_t CLOCK_HAL_GetPll0Clk(uint32_t baseAddr);
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*!
+ * @brief Gets the current MCG PLL1 clock.
+ *
+ * This function returns the mcgpll1clk value in frequency (Hertz) based
+ * on the current MCG configurations and settings. PLL1 should be properly configured
+ * in order to get the valid value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of mcgpll1clk.
+ */
+uint32_t CLOCK_HAL_GetPll1Clk(uint32_t baseAddr);
+#endif
+
+/*!
+ * @brief Gets the current MCG IR clock.
+ *
+ * This function returns the mcgirclk value in frequency (Hertz) based
+ * on the current MCG configurations and settings. It does not check if the
+ * mcgirclk is enabled or not, just calculate and return the value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of the mcgirclk.
+ */
+uint32_t CLOCK_HAL_GetInternalRefClk(uint32_t baseAddr);
+
+/*!
+ * @brief Gets the current MCG out clock.
+ *
+ * This function returns the mcgoutclk value in frequency (Hertz) based on the
+ * current MCG configurations and settings. The configuration should be
+ * properly done in order to get the valid value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return value Frequency value in Hertz of mcgoutclk.
+ */
+uint32_t CLOCK_HAL_GetOutClk(uint32_t baseAddr);
+
+/*@}*/
+
+/*! @name MCG control register access API*/
+/*@{*/
+
+/*!
+ * @brief Sets the Clock Source Select
+ *
+ * This function selects the clock source for the MCGOUTCLK.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param select Clock source selection
+ * - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
+ * - 01: Internal reference clock is selected.
+ * - 10: External reference clock is selected.
+ * - 11: Reserved.
+ */
+static inline void CLOCK_HAL_SetClkSrcMode(uint32_t baseAddr, mcg_clock_select_t select)
+{
+ BW_MCG_C1_CLKS(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Clock Source Select.
+ *
+ * This function gets the select of the clock source for the MCGOUTCLK.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select Clock source selection
+ */
+static inline mcg_clock_select_t CLOCK_HAL_GetClkSrcMode(uint32_t baseAddr)
+{
+ return (mcg_clock_select_t)BR_MCG_C1_CLKS(baseAddr);
+}
+
+/*!
+ * @brief Sets the FLL External Reference Divider.
+ *
+ * This function sets the FLL External Reference Divider.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param setting Divider setting
+ */
+static inline void CLOCK_HAL_SetFllExternalRefDivider(uint32_t baseAddr,
+ uint8_t setting)
+{
+ BW_MCG_C1_FRDIV(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the FLL External Reference Divider.
+ *
+ * This function gets the FLL External Reference Divider.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Divider setting
+ */
+static inline uint8_t CLOCK_HAL_GetFllExternalRefDivider(uint32_t baseAddr)
+{
+ return BR_MCG_C1_FRDIV(baseAddr);
+}
+
+/*!
+ * @brief Sets the Internal Reference Select.
+ *
+ * This function selects the reference clock source for the FLL.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param select Clock source select
+ * - 0: External reference clock is selected
+ * - 1: The slow internal reference clock is selected
+ */
+static inline void CLOCK_HAL_SetInternalRefSelMode(uint32_t baseAddr,
+ mcg_internal_ref_clock_source_t select)
+{
+ BW_MCG_C1_IREFS(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Internal Reference Select
+ *
+ * This function gets the reference clock source for the FLL.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select Clock source select
+ */
+static inline mcg_internal_ref_clock_source_t CLOCK_HAL_GetInternalRefSelMode(uint32_t baseAddr)
+{
+ return (mcg_internal_ref_clock_source_t)BR_MCG_C1_IREFS(baseAddr);
+}
+
+/*!
+ * @brief Sets the CLKS, FRDIV and IREFS at the same time.
+ *
+ * This function sets the CLKS, FRDIV, and IREFS settings at the same time
+ * in order keep the integrity of the clock switching.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param clks Clock source select
+ * @param frdiv FLL external reference divider select
+ * @param irefs Internal reference select
+ */
+static inline void CLOCK_HAL_SetClksFrdivInternalRefSelect(uint32_t baseAddr,
+ mcg_clock_select_t clks,
+ uint8_t frdiv,
+ mcg_internal_ref_clock_source_t irefs)
+{
+ /* Set the required CLKS , FRDIV and IREFS values */
+ HW_MCG_C1_WR(baseAddr, (HW_MCG_C1_RD(baseAddr) & ~(BM_MCG_C1_CLKS | BM_MCG_C1_FRDIV | BM_MCG_C1_IREFS))
+ | (BF_MCG_C1_CLKS(clks) | BF_MCG_C1_FRDIV(frdiv) | BF_MCG_C1_IREFS(irefs)));
+}
+
+/*!
+ * @brief Sets the Enable Internal Reference Clock setting.
+ *
+ * This function enables/disables the internal reference clock to use as the MCGIRCLK.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Enable or disable internal reference clock.
+ * - true: MCGIRCLK active
+ * - false: MCGIRCLK inactive
+ */
+static inline void CLOCK_HAL_SetInternalClkCmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C1_IRCLKEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the enable Internal Reference Clock setting.
+ *
+ * This function gets the reference clock enable setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if the internal reference clock is enabled.
+ */
+static inline bool CLOCK_HAL_GetInternalClkCmd(uint32_t baseAddr)
+{
+ return BR_MCG_C1_IRCLKEN(baseAddr);
+}
+
+/*!
+ * @brief Sets the Internal Reference Clock Stop Enable setting.
+ *
+ * This function controls whether or not the internal reference clock remains
+ * enabled when the MCG enters Stop mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Enable or disable the internal reference clock stop setting.
+ * - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set
+ * or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ * - false: Internal reference clock is disabled in Stop mode
+ */
+static inline void CLOCK_HAL_SetInternalRefStopCmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C1_IREFSTEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Enable Internal Reference Clock setting.
+ *
+ * This function gets the Internal Reference Clock Stop Enable setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if internal reference clock stop is enabled.
+ */
+static inline bool CLOCK_HAL_GetInternalRefStopCmd(uint32_t baseAddr)
+{
+ return BR_MCG_C1_IREFSTEN(baseAddr);
+}
+
+/*!
+ * @brief Sets the Loss of Clock Reset Enable setting.
+ *
+ * This function determines whether an interrupt or a reset request is made following a loss
+ * of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Loss of Clock Reset Enable setting
+ * - true: Generate a reset request on a loss of OSC0 external reference clock
+ * - false: Interrupt request is generated on a loss of OSC0 external reference clock
+ */
+static inline void CLOCK_HAL_SetLossOfClkReset0Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C2_LOCRE0(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Loss of Clock Reset Enable setting.
+ *
+ * This function gets the Loss of Clock Reset Enable setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Loss of Clock Reset is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossOfClkReset0Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C2_LOCRE0(baseAddr);
+}
+
+#if FSL_FEATURE_MCG_HAS_FCFTRIM
+/*!
+ * @brief Sets the Fast Internal Reference Clock Fine Trim setting.
+ *
+ * This function sets the Fast Internal Reference Clock Fine Trim setting. FCFTRIM
+ * controls the smallest adjustment of the fast internal reference clock frequency.
+ * Setting the FCFTRIM increases the period and clearing FCFTRIM decreases the period
+ * by the smallest amount possible. If an FCFTRIM value is stored and non-volatile
+ * memory is to be used, it is the user's responsibility to copy that value from the
+ * non-volatile memory location to this bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Fast Internal Reference Clock Fine Trim setting
+ */
+static inline void CLOCK_HAL_SetFastInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C2_FCFTRIM(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Fast Internal Reference Clock Fine Trim setting.
+ *
+ * This function gets the Fast Internal Reference Clock Fine Trim setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Fast Internal Reference Clock Fine Trim setting
+ */
+static inline uint8_t CLOCK_HAL_GetFastInternalRefClkFineTrim(uint32_t baseAddr)
+{
+ return BR_MCG_C2_FCFTRIM(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_HAS_FCFTRIM */
+
+/*!
+ * @brief Sets the Frequency Range Select.
+ *
+ * This function selects the frequency range for the crystal oscillator or an external
+ * clock source. See the Oscillator (OSC) chapter for more details and the device
+ * data sheet for the frequency ranges used.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params select Frequency Range Select
+ * - 00: Low frequency range selected for the crystal oscillator
+ * - 01: High frequency range selected for the crystal oscillator
+ * - 1X: Very high frequency range selected for the crystal oscillator
+ */
+static inline void CLOCK_HAL_SetRange0Mode(uint32_t baseAddr, mcg_freq_range_select_t select)
+{
+ BW_MCG_C2_RANGE(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Frequency Range Select.
+ *
+ * This function gets the Frequency Range Select.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select Frequency Range Select
+ */
+static inline mcg_freq_range_select_t CLOCK_HAL_GetRange0Mode(uint32_t baseAddr)
+{
+ return (mcg_freq_range_select_t)BR_MCG_C2_RANGE(baseAddr);
+}
+
+/*!
+ * @brief Sets the High Gain Oscillator Select.
+ *
+ * This function controls the crystal oscillator mode of operation. See the
+ * Oscillator (OSC) chapter for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params select High Gain Oscillator Select.
+ * - 0: Configure crystal oscillator for low-power operation
+ * - 1: Configure crystal oscillator for high-gain operation
+ */
+static inline void CLOCK_HAL_SetHighGainOsc0Mode(uint32_t baseAddr, mcg_high_gain_osc_select_t select)
+{
+ BW_MCG_C2_HGO(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the High Gain Oscillator Select.
+ *
+ * This function gets the High Gain Oscillator Select.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select High Gain Oscillator Select
+ */
+static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc0Mode(uint32_t baseAddr)
+{
+ return (mcg_high_gain_osc_select_t)BR_MCG_C2_HGO(baseAddr);
+}
+
+/*!
+ * @brief Sets the External Reference Select.
+ *
+ * This function selects the source for the external reference clock.
+ * See the Oscillator (OSC) chapter for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params select External Reference Select
+ * - 0: External reference clock requested
+ * - 1: Oscillator requested
+ */
+static inline void CLOCK_HAL_SetExternalRefSel0Mode(uint32_t baseAddr, mcg_external_ref_clock_select_t select)
+{
+ BW_MCG_C2_EREFS(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the External Reference Select.
+ *
+ * This function gets the External Reference Select.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select External Reference Select
+ */
+static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel0Mode(uint32_t baseAddr)
+{
+ return (mcg_external_ref_clock_select_t)BR_MCG_C2_EREFS(baseAddr);
+}
+
+/*!
+ * @brief Sets the Low Power Select.
+ *
+ * This function controls whether the FLL (or PLL) is disabled in the BLPI and the
+ * BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG
+ * into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into
+ * the BLPI mode. In any other MCG mode, the LP bit has no affect..
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params select Low Power Select
+ * - 0: FLL (or PLL) is not disabled in bypass modes
+ * - 1: FLL (or PLL) is disabled in bypass modes (lower power)
+ */
+static inline void CLOCK_HAL_SetLowPowerMode(uint32_t baseAddr, mcg_low_power_select_t select)
+{
+ BW_MCG_C2_LP(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Low Power Select.
+ *
+ * This function gets the Low Power Select.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select Low Power Select
+ */
+static inline mcg_low_power_select_t CLOCK_HAL_GetLowPowerMode(uint32_t baseAddr)
+{
+ return (mcg_low_power_select_t)BR_MCG_C2_LP(baseAddr);
+}
+
+/*!
+ * @brief Sets the Internal Reference Clock Select.
+ *
+ * This function selects between the fast or slow internal reference clock source.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params select Low Power Select
+ * - 0: Slow internal reference clock selected.
+ * - 1: Fast internal reference clock selected.
+ */
+static inline void CLOCK_HAL_SetInternalRefClkSelMode(uint32_t baseAddr,
+ mcg_internal_ref_clock_select_t select)
+{
+ BW_MCG_C2_IRCS(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Internal Reference Clock Select.
+ *
+ * This function gets the Internal Reference Clock Select.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return select Internal Reference Clock Select
+ */
+static inline mcg_internal_ref_clock_select_t CLOCK_HAL_GetInternalRefClkSelMode(uint32_t baseAddr)
+{
+ return (mcg_internal_ref_clock_select_t)BR_MCG_C2_IRCS(baseAddr);
+}
+
+/*!
+ * @brief Sets the Slow Internal Reference Clock Trim Setting.
+ *
+ * This function controls the slow internal reference clock frequency by
+ * controlling the slow internal reference clock period. The SCTRIM bits are
+ * binary weighted (that is, bit 1 adjusts twice as much as bit 0).
+ * Increasing the binary value increases the period, and decreasing the value
+ * decreases the period.
+ * An additional fine trim bit is available in the C4 register as the SCFTRIM bit.
+ * Upon reset, this value is loaded with a factory trim value.
+ * If an SCTRIM value stored in non-volatile memory is to be used, it is the user's
+ * responsibility to copy that value from the non-volatile memory location to
+ * this register.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Slow Internal Reference Clock Trim Setting
+ */
+static inline void CLOCK_HAL_SetSlowInternalRefClkTrim(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C3_SCTRIM(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Slow Internal Reference Clock Trim Setting.
+ *
+ * This function gets the Slow Internal Reference Clock Trim Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Slow Internal Reference Clock Trim Setting
+ */
+static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkTrim(uint32_t baseAddr)
+{
+ return BR_MCG_C3_SCTRIM(baseAddr);
+}
+
+/*!
+ * @brief Sets the DCO Maximum Frequency with 32.768 kHz Reference.
+ *
+ * This function controls whether or not the DCO frequency range
+ * is narrowed to its maximum frequency with a 32.768 kHz reference.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting DCO Maximum Frequency with 32.768 kHz Reference Setting
+ * - 0: DCO has a default range of 25%.
+ * - 1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+static inline void CLOCK_HAL_SetDmx32(uint32_t baseAddr, mcg_dmx32_select_t setting)
+{
+ BW_MCG_C4_DMX32(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting.
+ *
+ * This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting DCO Maximum Frequency with 32.768 kHz Reference Setting
+ */
+static inline mcg_dmx32_select_t CLOCK_HAL_GetDmx32(uint32_t baseAddr)
+{
+ return (mcg_dmx32_select_t)BR_MCG_C4_DMX32(baseAddr);
+}
+
+/*!
+ * @brief Sets the DCO Range Select.
+ *
+ * This function selects the frequency range for the FLL output, DCOOUT.
+ * When the LP bit is set, the writes to the DRS bits are ignored. The DRST read
+ * field indicates the current frequency range for the DCOOUT. The DRST field does
+ * not update immediately after a write to the DRS field due to internal
+ * synchronization between the clock domains. See the DCO Frequency Range table
+ * for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting DCO Range Select Setting
+ * - 00: Low range (reset default).
+ * - 01: Mid range.
+ * - 10: Mid-high range.
+ * - 11: High range.
+ */
+static inline void CLOCK_HAL_SetDigitalControlledOscRangeMode(uint32_t baseAddr,
+ mcg_digital_controlled_osc_range_select_t setting)
+{
+ BW_MCG_C4_DRST_DRS(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the DCO Range Select Setting.
+ *
+ * This function gets the DCO Range Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting DCO Range Select Setting
+ */
+static inline mcg_digital_controlled_osc_range_select_t CLOCK_HAL_GetDigitalControlledOscRangeMode(uint32_t baseAddr)
+{
+ return (mcg_digital_controlled_osc_range_select_t)BR_MCG_C4_DRST_DRS(baseAddr);
+}
+
+/*!
+ * @brief Sets the Fast Internal Reference Clock Trim Setting.
+ *
+ * This function controls the fast internal reference clock frequency
+ * by controlling the fast internal reference clock period. The FCTRIM
+ * bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
+ * Increasing the binary value increases the period, and decreasing the
+ * value decreases the period.
+ * If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is
+ * the user's responsibility to copy that value from the non-volatile memory location
+ * to this register.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Fast Internal Reference Clock Trim Setting.
+ */
+static inline void CLOCK_HAL_SetFastInternalRefClkTrim(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C4_FCTRIM(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Fast Internal Reference Clock Trim Setting.
+ *
+ * This function gets the Fast Internal Reference Clock Trim Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Fast Internal Reference Clock Trim Setting
+ */
+static inline uint8_t CLOCK_HAL_GetFastInternalRefClkTrim(uint32_t baseAddr)
+{
+ return BR_MCG_C4_FCTRIM(baseAddr);
+}
+
+/*!
+ * @brief Sets the Slow Internal Reference Clock Fine Trim Setting.
+ *
+ * This function controls the smallest adjustment of the slow internal
+ * reference clock frequency. Setting the SCFTRIM increases the period and
+ * clearing the SCFTRIM decreases the period by the smallest amount possible.
+ * If an SCFTRIM value, stored in non-volatile memory, is to be used, it is
+ * the user's responsibility to copy that value from the non-volatile memory
+ * location to this bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Slow Internal Reference Clock Fine Trim Setting
+ */
+static inline void CLOCK_HAL_SetSlowInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C4_SCFTRIM(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Slow Internal Reference Clock Fine Trim Setting.
+ *
+ * This function gets the Slow Internal Reference Clock Fine Trim Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Slow Internal Reference Clock Fine Trim Setting
+ */
+static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkFineTrim(uint32_t baseAddr)
+{
+ return BR_MCG_C4_SCFTRIM(baseAddr);
+}
+
+#if FSL_FEATURE_MCG_USE_PLLREFSEL
+/*!
+ * @brief Sets the PLL0 External Reference Select Setting.
+ *
+ * This function selects the PLL0 external reference clock source.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL0 External Reference Select Setting
+ * - 0: Selects OSC0 clock source as its external reference clock
+ * - 1: Selects OSC1 clock source as its external reference clock
+ */
+static inline void CLOCK_HAL_SetPllRefSel0Mode(uint32_t baseAddr,
+ mcg_pll_external_ref_clk_select_t setting)
+{
+ BW_MCG_C5_PLLREFSEL0(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL0 External Reference Select Setting.
+ *
+ * This function gets the PLL0 External Reference Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL0 External Reference Select Setting
+ */
+static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel0Mode(uint32_t baseAddr)
+{
+ return (mcg_pll_external_ref_clk_select_t)BR_MCG_C5_PLLREFSEL0(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR
+
+/*!
+ * @brief Sets the Clock Monitor Enable Setting.
+ *
+ * This function enables/disables the loss of clock monitoring circuit for
+ * the OSC0 external reference mux select. The LOCRE0 bit determines whether an
+ * interrupt or a reset request is generated following a loss of the OSC0 indication.
+ * The CME0 bit should only be set to a logic 1 when the MCG is in an operational
+ * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the
+ * CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register
+ * should not be changed. CME0 bit should be set to a logic 0 before the MCG
+ * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode.
+ * CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes
+ * if the MCG is in BLPE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Clock Monitor Enable Setting
+ * - true: External clock monitor is enabled for OSC0.
+ * - false: External clock monitor is disabled for OSC0.
+ */
+static inline void CLOCK_HAL_SetClkMonitor0Cmd(uint32_t baseAddr, bool enable)
+{
+#if FSL_FEATURE_MCG_HAS_PLL
+ BW_MCG_C6_CME0(baseAddr, enable ? 1 : 0);
+#else
+ BW_MCG_C6_CME(baseAddr, enable ? 1 : 0);
+#endif
+}
+
+/*!
+ * @brief Gets the Clock Monitor Enable Setting.
+ *
+ * This function gets the Clock Monitor Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Clock Monitor is enabled
+ */
+static inline bool CLOCK_HAL_GetClkMonitor0Cmd(uint32_t baseAddr)
+{
+#if FSL_FEATURE_MCG_HAS_PLL
+ return BR_MCG_C6_CME0(baseAddr);
+#else
+ return BR_MCG_C6_CME(baseAddr);
+#endif
+}
+
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL
+/*!
+ * @brief Sets the PLL Clock Enable Setting.
+ *
+ * This function enables/disables the PLL0 independent of the PLLS and enables the PLL0
+ * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to
+ * the correct divider to generate a PLL1 reference clock in a valid reference range
+ * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external
+ * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being
+ * enabled with the PLLCLKEN0 bit, and the external oscillator is being used
+ * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL Clock Enable Setting
+ * - true: MCGPLL0CLK and MCGPLL0CLK2X are active
+ * - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive
+ */
+static inline void CLOCK_HAL_SetPllClk0Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C5_PLLCLKEN0(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL Clock Enable Setting.
+ *
+ * This function gets the PLL Clock Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if PLL0 PLL Clock is enabled.
+ */
+static inline bool CLOCK_HAL_GetPllClk0Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C5_PLLCLKEN0(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL0 Stop Enable Setting.
+ *
+ * This function enables/disables the PLL0 Clock during a Normal Stop (In Low
+ * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other
+ * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock
+ * to run if it is written to 1.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL0 Stop Enable Setting
+ * - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in
+ * Normal Stop mode.
+ * - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the
+ * Stop modes.
+ */
+static inline void CLOCK_HAL_SetPllStat0Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C5_PLLSTEN0(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL0 Stop Enable Setting.
+ *
+ * This function gets the PLL0 Stop Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if the PLL0 Stop is enabled.
+ */
+static inline bool CLOCK_HAL_GetPllStat0Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C5_PLLSTEN0(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL0 External Reference Divider Setting.
+ *
+ * This function selects the amount to divide down the external reference
+ * clock for the PLL0. The resulting frequency must be in a valid reference
+ * range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the
+ * PRDIV0 value must not be changed when LOCK0 is zero.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL0 External Reference Divider Setting
+ */
+static inline void CLOCK_HAL_SetPllExternalRefDivider0(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C5_PRDIV0(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL0 External Reference Divider Setting.
+ *
+ * This function gets the PLL0 External Reference Divider Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL0 External Reference Divider Setting
+ */
+static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider0(uint32_t baseAddr)
+{
+ return BR_MCG_C5_PRDIV0(baseAddr);
+}
+
+/*!
+ * @brief Sets the Loss of Lock Interrupt Enable Setting.
+ *
+ * This function determine whether an interrupt request is made following a loss
+ * of lock indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Loss of Lock Interrupt Enable Setting
+ * - true: Generate an interrupt request on loss of lock.
+ * - false: No interrupt request is generated on loss of lock.
+ */
+static inline void CLOCK_HAL_SetLossOfClkInt0Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C6_LOLIE0(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Loss of the Lock Interrupt Enable Setting.
+ *
+ * This function gets the Loss of the Lock Interrupt Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if the Loss of Lock Interrupt is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossOfClkInt0Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C6_LOLIE0(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL Select Setting.
+ *
+ * This function controls whether the PLLCS or FLL output is selected as the
+ * MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and
+ * PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the
+ * PLLS is set, the FLL is disabled in all modes.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL Select Setting
+ * - 0: FLL is selected.
+ * - 1: PLLCS output clock is selected (PRDIV0 bits of PLL in
+ * control need to be programmed to the correct divider to
+ * generate a PLL reference clock in the range of 1 - 32 MHz
+ * prior to setting the PLLS bit).
+ */
+static inline void CLOCK_HAL_SetPllSelMode(uint32_t baseAddr, mcg_pll_select_t setting)
+{
+ BW_MCG_C6_PLLS(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL Select Setting.
+ *
+ * This function gets the PLL Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL Select Setting
+ */
+static inline mcg_pll_select_t CLOCK_HAL_GetPllSelMode(uint32_t baseAddr)
+{
+ return (mcg_pll_select_t)BR_MCG_C6_PLLS(baseAddr);
+}
+
+/*!
+ * @brief Sets the VCO0 Divider Setting.
+ *
+ * This function selects the amount to divide the VCO output of the PLL0.
+ * The VDIV0 bits establish the multiplication factor (M) applied to the
+ * reference clock frequency. After the PLL0 is enabled (by setting either
+ * PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting VCO0 Divider Setting
+ */
+static inline void CLOCK_HAL_SetVoltCtrlOscDivider0(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C6_VDIV0(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the VCO0 Divider Setting.
+ *
+ * This function gets the VCO0 Divider Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting VCO0 Divider Setting
+ */
+static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider0(uint32_t baseAddr)
+{
+ return BR_MCG_C6_VDIV0(baseAddr);
+}
+
+/*!
+ * @brief Gets the Loss of the Lock Status.
+ *
+ * This function gets the Loss of Lock Status. This bit is a sticky bit indicating
+ * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL
+ * output frequency has fallen outside the lock exit frequency tolerance, D unl .
+ * LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set.
+ * This bit is cleared by reset or by writing a logic 1 to it when set. Writing a
+ * logic 0 to this bit has no effect.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Loss of Lock Status
+ * - 0: PLL has not lost lock since LOLS 0 was last cleared
+ * - 1: PLL has lost lock since LOLS 0 was last cleared
+ */
+static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock0Mode(uint32_t baseAddr)
+{
+ return (mcg_loss_of_lock_status_t)BR_MCG_S_LOLS0(baseAddr);
+}
+
+/*!
+ * @brief Gets the Lock Status.
+ *
+ * This function gets the Lock Status. This bit indicates whether the PLL0 has
+ * acquired the lock. Lock detection is disabled when not operating in either the PBE or the
+ * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode.
+ * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and
+ * MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock
+ * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register
+ * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear
+ * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference
+ * clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS,
+ * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear
+ * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock.
+ * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and
+ * MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Lock Status
+ * - 0: PLL is currently unlocked
+ * - 1: PLL is currently locked
+ */
+static inline mcg_lock_status_t CLOCK_HAL_GetLock0Mode(uint32_t baseAddr)
+{
+ return (mcg_lock_status_t)BR_MCG_S_LOCK0(baseAddr);
+}
+
+/*!
+ * @brief Gets the PLL Select Status.
+ *
+ * This function gets the PLL Select Status. This bit indicates the clock source
+ * selected by PLLS . The PLLST bit does not update immediately after a write to
+ * the PLLS bit due to the internal synchronization between the clock domains.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status PLL Select Status
+ * - 0: Source of PLLS clock is FLL clock.
+ * - 1: Source of PLLS clock is PLLCS output clock.
+ */
+static inline mcg_pll_stat_status_t CLOCK_HAL_GetPllStatMode(uint32_t baseAddr)
+{
+ return (mcg_pll_stat_status_t)BR_MCG_S_PLLST(baseAddr);
+}
+#endif
+
+/*!
+ * @brief Gets the Internal Reference Status.
+ *
+ * This function gets the Internal Reference Status. This bit indicates the current
+ * source for the FLL reference clock. The IREFST bit does not update immediately
+ * after a write to the IREFS bit due to internal synchronization between the clock
+ * domains.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Internal Reference Status
+ * - 0: Source of FLL reference clock is the external reference clock.
+ * - 1: Source of FLL reference clock is the internal reference clock.
+ */
+static inline mcg_internal_ref_status_t CLOCK_HAL_GetInternalRefStatMode(uint32_t baseAddr)
+{
+ return (mcg_internal_ref_status_t)BR_MCG_S_IREFST(baseAddr);
+}
+
+/*!
+ * @brief Gets the Clock Mode Status.
+ *
+ * This function gets the Clock Mode Status. These bits indicate the current clock mode.
+ * The CLKST bits do not update immediately after a write to the CLKS bits due to
+ * internal synchronization between clock domains.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Clock Mode Status
+ * - 00: Output of the FLL is selected (reset default).
+ * - 01: Internal reference clock is selected.
+ * - 10: External reference clock is selected.
+ * - 11: Output of the PLL is selected.
+ */
+static inline mcg_clk_stat_status_t CLOCK_HAL_GetClkStatMode(uint32_t baseAddr)
+{
+ return (mcg_clk_stat_status_t)BR_MCG_S_CLKST(baseAddr);
+}
+
+/*!
+ * @brief Gets the OSC Initialization Status.
+ *
+ * This function gets the OSC Initialization Status. This bit, which resets to 0, is set
+ * to 1 after the initialization cycles of the crystal oscillator clock have completed.
+ * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the
+ * OSC module's detailed description for more information.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status OSC Initialization Status
+ */
+static inline uint8_t CLOCK_HAL_GetOscInit0(uint32_t baseAddr)
+{
+ return BR_MCG_S_OSCINIT0(baseAddr);
+}
+
+/*!
+ * @brief Gets the Internal Reference Clock Status.
+ *
+ * This function gets the Internal Reference Clock Status. The IRCST bit indicates the
+ * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit
+ * does not update immediately after a write to the IRCS bit due to the internal
+ * synchronization between clock domains. The IRCST bit is only updated if the
+ * internal reference clock is enabled, either by the MCG being in a mode that uses the
+ * IRC or by setting the C1[IRCLKEN] bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Internal Reference Clock Status
+ * - 0: Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 1: Source of internal reference clock is the fast clock (2 MHz IRC).
+ */
+static inline mcg_internal_ref_clk_status_t CLOCK_HAL_GetInternalRefClkStatMode(uint32_t baseAddr)
+{
+ return (mcg_internal_ref_clk_status_t)BR_MCG_S_IRCST(baseAddr);
+}
+
+/*!
+ * @brief Gets the Automatic Trim machine Fail Flag.
+ *
+ * This function gets the Automatic Trim machine Fail Flag. This Fail flag for the
+ * Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is
+ * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG
+ * enters into any Stop mode. A write to ATMF clears the flag.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return flag Automatic Trim machine Fail Flag
+ * - 0: Automatic Trim Machine completed normally.
+ * - 1: Automatic Trim Machine failed.
+ */
+static inline mcg_auto_trim_machine_fail_status_t CLOCK_HAL_GetAutoTrimMachineFailMode(uint32_t baseAddr)
+{
+ return (mcg_auto_trim_machine_fail_status_t)BR_MCG_SC_ATMF(baseAddr);
+}
+
+/*!
+ * @brief Sets the Automatic Trim machine Fail Flag.
+ *
+ * This function clears the ATMF flag.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_SetAutoTrimMachineFail(uint32_t baseAddr)
+{
+ BW_MCG_SC_ATMF(baseAddr, 1);
+}
+
+/*!
+ * @brief Gets the OSC0 Loss of Clock Status.
+ *
+ * This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of
+ * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set.
+ * This bit is cleared by writing a logic 1 to it when set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status OSC0 Loss of Clock Status
+ * - 0: Loss of OSC0 has not occurred.
+ * - 1: Loss of OSC0 has occurred.
+ */
+static inline mcg_locs0_status_t CLOCK_HAL_GetLocs0Mode(uint32_t baseAddr)
+{
+ return (mcg_locs0_status_t)BR_MCG_SC_LOCS0(baseAddr);
+}
+
+/*!
+ * @brief Sets the Automatic Trim Machine Enable Setting.
+ *
+ * This function enables/disables the Auto Trim Machine to start automatically
+ * trimming the selected Internal Reference Clock.
+ * ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits
+ * of the IRCS clock selected by the ATMS bit.
+ * Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto
+ * trim operation and clears this bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Automatic Trim Machine Enable Setting
+ * - true: Auto Trim Machine enabled
+ * - false: Auto Trim Machine disabled
+ */
+static inline void CLOCK_HAL_SetAutoTrimMachineCmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_SC_ATME(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Automatic Trim Machine Enable Setting.
+ *
+ * This function gets the Automatic Trim Machine Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Automatic Trim Machine is enabled
+ */
+static inline bool CLOCK_HAL_GetAutoTrimMachineCmd(uint32_t baseAddr)
+{
+ return BR_MCG_SC_ATME(baseAddr);
+}
+
+/*!
+ * @brief Sets the Automatic Trim Machine Select Setting.
+ *
+ * This function selects the IRCS clock for Auto Trim Test.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Automatic Trim Machine Select Setting
+ * - 0: 32 kHz Internal Reference Clock selected
+ * - 1: 4 MHz Internal Reference Clock selected
+ */
+static inline void CLOCK_HAL_SetAutoTrimMachineSelMode(uint32_t baseAddr,
+ mcg_auto_trim_machine_select_t setting)
+{
+ BW_MCG_SC_ATMS(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Automatic Trim Machine Select Setting.
+ *
+ * This function gets the Automatic Trim Machine Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Automatic Trim Machine Select Setting
+ */
+static inline mcg_auto_trim_machine_select_t CLOCK_HAL_GetAutoTrimMachineSelMode(uint32_t baseAddr)
+{
+ return (mcg_auto_trim_machine_select_t)BR_MCG_SC_ATMS(baseAddr);
+}
+
+/*!
+ * @brief Sets the FLL Filter Preserve Enable Setting.
+ *
+ * This function sets the FLL Filter Preserve Enable. This bit prevents the
+ * FLL filter values from resetting allowing the FLL output frequency to remain the
+ * same during the clock mode changes where the FLL/DCO output is still valid.
+ * (Note: This requires that the FLL reference frequency remain the same as
+ * the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency
+ * values change.)
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable FLL Filter Preserve Enable Setting
+ * - true: FLL filter and FLL frequency retain their previous values
+ * during new clock mode change
+ * - false: FLL filter and FLL frequency will reset on changes to correct
+ * clock mode
+ */
+static inline void CLOCK_HAL_SetFllFilterPreserveCmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_SC_FLTPRSRV(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the FLL Filter Preserve Enable Setting.
+ *
+ * This function gets the FLL Filter Preserve Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if FLL Filter Preserve is enabled.
+ */
+static inline bool CLOCK_HAL_GetFllFilterPreserveCmd(uint32_t baseAddr)
+{
+ return BR_MCG_SC_FLTPRSRV(baseAddr);
+}
+
+/*!
+ * @brief Sets the Fast Clock Internal Reference Divider Setting.
+ *
+ * This function selects the amount to divide down the fast internal reference
+ * clock. The resulting frequency is in the range 31.25 kHz to 4 MHz.
+ * (Note: Changing the divider when the Fast IRC is enabled is not supported).
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Fast Clock Internal Reference Divider Setting
+ */
+static inline void CLOCK_HAL_SetFastClkInternalRefDivider(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_SC_FCRDIV(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Fast Clock Internal Reference Divider Setting.
+ *
+ * This function gets the Fast Clock Internal Reference Divider Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Fast Clock Internal Reference Divider Setting
+ */
+static inline uint8_t CLOCK_HAL_GetFastClkInternalRefDivider(uint32_t baseAddr)
+{
+ return BR_MCG_SC_FCRDIV(baseAddr);
+}
+
+/*!
+ * @brief Sets the ATM Compare Value High Setting.
+ *
+ * This function sets the ATM compare value high setting. The values are used by the
+ * Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM
+ * SAR conversion.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting ATM Compare Value High Setting
+ */
+static inline void CLOCK_HAL_SetAutoTrimMachineCompValHigh(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_ATCVH_ATCVH(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the ATM Compare Value High Setting.
+ *
+ * This function gets the ATM Compare Value High Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting ATM Compare Value High Setting
+ */
+static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValHigh(uint32_t baseAddr)
+{
+ return BR_MCG_ATCVH_ATCVH(baseAddr);
+}
+
+/*!
+ * @brief Sets the ATM Compare Value Low Setting.
+ *
+ * This function sets the ATM compare value low setting. The values are used by the
+ * Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM
+ * SAR conversion.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting ATM Compare Value Low Setting
+ */
+static inline void CLOCK_HAL_SetAutoTrimMachineCompValLow(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_ATCVL_ATCVL(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the ATM Compare Value Low Setting.
+ *
+ * This function gets the ATM Compare Value Low Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting ATM Compare Value Low Setting
+ */
+static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValLow(uint32_t baseAddr)
+{
+ return BR_MCG_ATCVL_ATCVL(baseAddr);
+}
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+/*!
+ * @brief Sets the MCG OSC Clock Select Setting.
+ *
+ * This function selects the MCG FLL external reference clock.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting MCG OSC Clock Select Setting
+ * - 0: Selects System Oscillator (OSCCLK).
+ * - 1: Selects 32 kHz RTC Oscillator.
+ */
+static inline void CLOCK_HAL_SetOscselMode(uint32_t baseAddr, mcg_oscsel_select_t setting)
+{
+ BW_MCG_C7_OSCSEL(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the MCG OSC Clock Select Setting.
+ *
+ * This function gets the MCG OSC Clock Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting MCG OSC Clock Select Setting
+ */
+static inline mcg_oscsel_select_t CLOCK_HAL_GetOscselMode(uint32_t baseAddr)
+{
+ return (mcg_oscsel_select_t)BR_MCG_C7_OSCSEL(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_USE_OSCSEL */
+
+#if FSL_FEATURE_MCG_HAS_LOLRE
+/*!
+ * @brief Sets the PLL Loss of Lock Reset Enable Setting.
+ *
+ * This function determines whether an interrupt or a reset request is made
+ * following a PLL loss of lock.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL Loss of Lock Reset Enable Setting
+ * - true: Generate a reset request on a PLL loss of lock indication.
+ * - false: Interrupt request is generated on a PLL loss of lock
+ * indication. The PLL loss of lock interrupt enable bit
+ * must also be set to generate the interrupt request.
+ */
+static inline void CLOCK_HAL_SetLossOfClkResetCmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C8_LOLRE(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL Loss of Lock Reset Enable Setting.
+ *
+ * This function gets the PLL Loss of Lock Reset Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if the PLL Loss of Lock Reset is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossOfClkResetCmd(uint32_t baseAddr)
+{
+ return BR_MCG_C8_LOLRE(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_HAS_LOLRE */
+
+
+#if FSL_FEATURE_MCG_HAS_RTC_32K
+/*!
+ * @brief Sets the Loss of Clock Reset Enable Setting.
+ *
+ * This function determines whether an interrupt or a reset request is made following
+ * a loss of the RTC external reference clock. The LOCRE1 only has an affect when CME1
+ * is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Loss of Clock Reset Enable Setting
+ * - true: Generate a reset request on a loss of RTC external reference clock.
+ * - false: Interrupt request is generated on a loss of RTC external
+ * reference clock.
+ */
+static inline void CLOCK_HAL_SetLossClkReset1Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C8_LOCRE1(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Loss of Clock Reset Enable Setting.
+ *
+ * This function gets the Loss of Clock Reset Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Loss of Clock Reset is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossClkReset1Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C8_LOCRE1(baseAddr);
+}
+
+/*!
+ * @brief Sets the Clock Monitor Enable1 Setting.
+ *
+ * This function enables/disables the loss of the clock monitoring circuit for the
+ * output of the RTC external reference clock. The LOCRE1 bit determines whether an
+ * interrupt or a reset request is generated following a loss of the RTC clock indication.
+ * The CME1 bit should only be set to a logic 1 when the MCG is in an operational mode
+ * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). CME1 bit must be set to
+ * a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur
+ * while in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or
+ * VLPW power modes if the MCG is in BLPE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Clock Monitor Enable1 Setting
+ * - true: External clock monitor is enabled for RTC clock.
+ * - false: External clock monitor is disabled for RTC clock.
+ */
+static inline void CLOCK_HAL_SetClkMonitor1Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C8_CME1(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Clock Monitor Enable1 Setting.
+ *
+ * This function gets the Clock Monitor Enable1 Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Clock Monitor Enable1 is enabled
+ */
+static inline bool CLOCK_HAL_GetClkMonitor1Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C8_CME1(baseAddr);
+}
+
+/*!
+ * @brief Gets the RTC Loss of Clock Status.
+ *
+ * This function gets the RTC Loss of Clock Status. This bit indicates when a loss
+ * of clock has occurred. This bit is cleared by writing a logic 1 to it when set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status RTC Loss of Clock Status
+ * - 0: Loss of RTC has not occurred
+ * - 1: Loss of RTC has occurred
+ */
+static inline mcg_loss_of_clk1_status_t CLOCK_HAL_GetLossOfClk1Mode(uint32_t baseAddr)
+{
+ return (mcg_loss_of_clk1_status_t)BR_MCG_C8_LOCS1(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_HAS_RTC_32K */
+
+#if FSL_FEATURE_MCG_USE_PLLREFSEL
+/*!
+ * @brief Sets the OSC1 Loss of Clock Reset Enable Setting.
+ *
+ * This function determines whether an interrupt or reset request is made following
+ * a loss of OSC1 external reference clock. The LOCRE2 only has an affect when
+ * LOCS2 is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable OSC1 Loss of Clock Reset Enable Setting
+ * - true: Reset request is generated on a loss of OSC1 external
+ * reference clock..
+ * - false: Interrupt request is generated on a loss of OSC1 external
+ * reference clock.
+ */
+static inline void CLOCK_HAL_SetLossClkReset2Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C10_LOCRE2(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the OSC1 Loss of the Clock Reset Enable Setting.
+ *
+ * This function gets the OSC1 Loss of Clock Reset Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if OSC1 Loss of Clock Reset is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossClkReset2Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C10_LOCRE2(baseAddr);
+}
+
+/*!
+ * @brief Sets the Frequency Range1 Select Setting.
+ *
+ * This function selects the frequency range for the OSC1 crystal oscillator
+ * or an external clock source. See the Oscillator chapter for more details and
+ * the device data sheet for the frequency ranges used.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting Frequency Range1 Select Setting
+ * - 00: Low frequency range selected for the crystal oscillator.
+ * - 01: High frequency range selected for the crystal oscillator.
+ * - 1X: Very high frequency range selected for the crystal oscillator.
+ */
+static inline void CLOCK_HAL_SetRange1Mode(uint32_t baseAddr, mcg_freq_range_select_t setting)
+{
+ BW_MCG_C10_RANGE1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Frequency Range1 Select Setting.
+ *
+ * This function gets the Frequency Range1 Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting Frequency Range1 Select Setting
+ */
+static inline mcg_freq_range_select_t CLOCK_HAL_GetRange1Mode(uint32_t baseAddr)
+{
+ return (mcg_freq_range_select_t)BR_MCG_C10_RANGE1(baseAddr);
+}
+
+/*!
+ * @brief Sets the High Gain Oscillator1 Select Setting.
+ *
+ * This function controls the OSC1 crystal oscillator mode of operation.
+ * See the Oscillator chapter for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting High Gain Oscillator1 Select Setting
+ * - 0: Configure crystal oscillator for low-power operation.
+ * - 1: Configure crystal oscillator for high-gain operation.
+ */
+static inline void CLOCK_HAL_SetHighGainOsc1Mode(uint32_t baseAddr,
+ mcg_high_gain_osc_select_t setting)
+{
+ BW_MCG_C10_HGO1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the High Gain Oscillator1 Select Setting.
+ *
+ * This function gets the High Gain Oscillator1 Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting High Gain Oscillator1 Select Setting
+ */
+static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc1Mode(uint32_t baseAddr)
+{
+ return (mcg_high_gain_osc_select_t)BR_MCG_C10_HGO1(baseAddr);
+}
+
+/*!
+ * @brief Sets the External Reference Select Setting.
+ *
+ * This function selects the source for the OSC1 external reference clock.
+ * See the Oscillator chapter for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting External Reference Select Setting
+ * - 0: External reference clock requested.
+ * - 1: Oscillator requested.
+ */
+static inline void CLOCK_HAL_SetExternalRefSel1Mode(uint32_t baseAddr,
+ mcg_external_ref_clock_select_t setting)
+{
+ BW_MCG_C10_EREFS1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the External Reference Select Setting.
+ *
+ * This function gets the External Reference Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting External Reference Select Setting
+ */
+static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel1Mode(uint32_t baseAddr)
+{
+ return (mcg_external_ref_clock_select_t)BR_MCG_C10_EREFS1(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL1 External Reference Select Setting.
+ *
+ * This function selects the PLL1 external reference clock source.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL1 External Reference Select Setting
+ * - 0: Selects OSC0 clock source as its external reference clock.
+ * - 1: Selects OSC1 clock source as its external reference clock.
+ */
+static inline void CLOCK_HAL_SetPllRefSel1Mode(uint32_t baseAddr,
+ mcg_pll_external_ref_clk_select_t setting)
+{
+ BW_MCG_C11_PLLREFSEL1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL1 External Reference Select Setting.
+ *
+ * This function gets the PLL1 External Reference Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL1 External Reference Select Setting
+ */
+static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel1Mode(uint32_t baseAddr)
+{
+ return (mcg_pll_external_ref_clk_select_t)BR_MCG_C11_PLLREFSEL1(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL1 Clock Enable Setting.
+ *
+ * This function enables/disables the PLL1 independent of PLLS and enables the
+ * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs
+ * to be programmed to the correct divider to generate a PLL1 reference clock in a
+ * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1
+ * enables the PLL1 selected external oscillator if not already enabled.
+ * Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the
+ * external oscillator is used as the reference clock, the OSCINIT1 bit should
+ * be checked to make sure it is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL1 Clock Enable Setting
+ * - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless
+ * MCG is in a bypass mode with LP=1 (BLPI or BLPE).
+ * - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive.
+ */
+static inline void CLOCK_HAL_SetPllClk1Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C11_PLLCLKEN1(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL1 Clock Enable Setting.
+ *
+ * This function gets the PLL1 Clock Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if the PLL1 Clock is enabled.
+ */
+static inline bool CLOCK_HAL_GetPllClk1Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C11_PLLCLKEN1(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL1 Stop Enable Setting.
+ *
+ * This function enables/disables the PLL1 Clock during the Normal Stop (In Low
+ * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other
+ * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to
+ * run if it is written to 1.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL1 Stop Enable Setting
+ * - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and
+ * MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
+ * - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X)
+ * are disabled in any of the Stop modes.
+ */
+static inline void CLOCK_HAL_SetPllStop1Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C11_PLLSTEN1(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL1 Stop Enable Setting.
+ *
+ * This function gets the PLL1 Stop Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if PLL1 Stop is enabled.
+ */
+static inline bool CLOCK_HAL_GetPllStop1Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C11_PLLSTEN1(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL Clock Select Setting.
+ *
+ * This function controls whether the PLL0 or PLL1 output is selected as the
+ * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode
+ * (CLKS[1:0]=00 and IREFS=0 and PLLS=1).
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL Clock Select Setting
+ * - 0: PLL0 output clock is selected.
+ * - 1: PLL1 output clock is selected.
+ */
+static inline void CLOCK_HAL_SetPllClkSelMode(uint32_t baseAddr, mcg_pll_clk_select_t setting)
+{
+ BW_MCG_C11_PLLCS(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL Clock Select Setting.
+ *
+ * This function gets the PLL Clock Select Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL Clock Select Setting
+ */
+static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelMode(uint32_t baseAddr)
+{
+ return (mcg_pll_clk_select_t)BR_MCG_C11_PLLCS(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL1 External Reference Divider Setting.
+ *
+ * This function selects the amount to divide down the external reference
+ * clock selected by REFSEL2 for PLL1. The resulting frequency must be in a valid
+ * reference range. After the PLL1 is enabled (by setting either PLLCLKEN1 or PLLS),
+ * the PRDIV1 value must not be changed when LOCK1 is zero.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting PLL1 External Reference Divider Setting
+ */
+static inline void CLOCK_HAL_SetPllExternalRefDivider1(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C11_PRDIV1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PLL1 External Reference Divider Setting.
+ *
+ * This function gets the PLL1 External Reference Divider Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting PLL1 External Reference Divider Setting
+ */
+static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider1(uint32_t baseAddr)
+{
+ return BR_MCG_C11_PRDIV1(baseAddr);
+}
+
+/*!
+ * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting.
+ *
+ * This function determines whether an interrupt request is made following a
+ * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable PLL1 Loss of Lock Interrupt Enable Setting
+ * - true: Generate an interrupt request on loss of lock on PLL1.
+ * - false: No interrupt request is generated on loss of lock on PLL1.
+ */
+static inline void CLOCK_HAL_SetLossOfLock1Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C12_LOLIE1(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the PLL1 Loss of Lock Interrupt Enable Setting.
+ *
+ * This function gets the PLL1 Loss of Lock Interrupt Enable Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled true if PLL1 Loss of Lock Interrupt is enabled.
+ */
+static inline bool CLOCK_HAL_GetLossOfLock1Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C12_LOLIE1(baseAddr);
+}
+
+/*!
+ * @brief Sets the Clock Monitor Enable2 Setting
+ *
+ * This function enables/disables the loss of the clock monitor for the OSC1 external
+ * reference clock. LOCRE2 determines whether a reset or interrupt request is generated
+ * following a loss of OSC1 external reference clock. The CME2 bit should only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external clock
+ * (PEE or PBE) . Whenever the CME2 bit is set to a logic 1, the value of the RANGE1
+ * bits in the C10 register should not be changed. CME2 bit should be set to a logic 0
+ * before the MCG enters any Stop mode. Otherwise, a reset request may occur while in
+ * Stop mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params enable Clock Monitor Enable2 Setting
+ * - true: Generate a reset request on loss of external clock on OSC1.
+ * - false: External clock monitor for OSC1 is disabled.
+ */
+static inline void CLOCK_HAL_SetClkMonitor2Cmd(uint32_t baseAddr, bool enable)
+{
+ BW_MCG_C12_CME2(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the Clock Monitor Enable2 Setting.
+ *
+ * This function gets the Clock Monitor Enable2 Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return enabled True if Clock Monitor Enable2 is enabled.
+ */
+static inline bool CLOCK_HAL_GetClkMonitor2Cmd(uint32_t baseAddr)
+{
+ return BR_MCG_C12_CME2(baseAddr);
+}
+
+/*!
+ * @brief Sets the VCO1 Divider Setting.
+ *
+ * This function selects the amount to divide the VCO output of the PLL1.
+ * The VDIV1 bits establishes the multiplication factor (M) applied to the reference
+ * clock frequency. After the PLL1 is enabled (by setting either PLLCLKEN1 or
+ * PLLS), the VDIV1 value must not be changed when LOCK1 is zero.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @params setting VCO1 Divider Setting
+ */
+static inline void CLOCK_HAL_SetVoltCtrlOscDivider1(uint32_t baseAddr, uint8_t setting)
+{
+ BW_MCG_C12_VDIV1(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the VCO1 Divider Setting.
+ *
+ * This function gets the VCO1 Divider Setting.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return setting VCO1 Divider Setting
+ */
+static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider1(uint32_t baseAddr)
+{
+ return BR_MCG_C12_VDIV1(baseAddr);
+}
+
+/*!
+ * @brief Gets the Loss of the Lock2 Status.
+ *
+ * This function gets the Loss of the Lock2 Status. This bit is a sticky bit indicating
+ * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1
+ * output frequency has fallen outside the lock exit frequency tolerance, D unl.
+ * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This
+ * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0
+ * to this bit has no effect.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Loss of Lock2 Status
+ * - 0: PLL1 has not lost lock since LOLS1 was last cleared.
+ * - 1: PLL1 has lost lock since LOLS1 was last cleared.
+ */
+static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock1Mode(uint32_t baseAddr)
+{
+ return (mcg_loss_of_lock_status_t)BR_MCG_S2_LOLS1(baseAddr);
+}
+
+/*!
+ * @brief Gets the Lock1 Status.
+ *
+ * This function gets the Lock1 Status. This bit indicates whether PLL1 has
+ * acquired the lock. PLL1 Lock detection is disabled when not operating in either
+ * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the
+ * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK,
+ * MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets
+ * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0]
+ * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the
+ * lock status bit to clear and stay cleared until the PLL1 has reacquired lock.
+ * Loss of PLL1 reference clock will also causes the LOCK1 bit to clear until the PLL1
+ * has reacquired lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also
+ * causes the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit
+ * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off
+ * until the LOCK1 bit is asserted again.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status Lock1 Status
+ * - 0: PLL1 is currently unlocked.
+ * - 1: PLL1 is currently locked.
+ */
+static inline mcg_lock_status_t CLOCK_HAL_GetLock1Mode(uint32_t baseAddr)
+{
+ return (mcg_lock_status_t)BR_MCG_S2_LOCK1(baseAddr);
+}
+
+/*!
+ * @brief Gets the PLL Clock Select Status.
+ *
+ * This function gets the PLL Clock Select Status. The PLLCST indicates the PLL
+ * clock selected by PLLCS. The PLLCST bit is not updated immediately after a
+ * write to the PLLCS bit due internal synchronization between clock domains.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status PLL Clock Select Status
+ * - 0: Source of PLLCS is PLL0 clock.
+ * - 1: Source of PLLCS is PLL1 clock.
+ */
+static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelStatMode(uint32_t baseAddr)
+{
+ return (mcg_pll_clk_select_t)BR_MCG_S2_PLLCST(baseAddr);
+}
+
+/*!
+ * @brief Gets the OSC1 Initialization Status.
+ *
+ * This function gets the OSC1 Initialization Status. This bit is set after the
+ * initialization cycles of the 2nd crystal oscillator clock have completed. See
+ * the Oscillator block guide for more details.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status OSC1 Initialization Status
+ */
+static inline uint8_t CLOCK_HAL_GetOscInit1(uint32_t baseAddr)
+{
+ return BR_MCG_S2_OSCINIT1(baseAddr);
+}
+
+/*!
+ * @brief Gets the OSC1 Loss of Clock Status.
+ *
+ * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss
+ * of the OSC1 external reference clock has occurred. LOCRE2 determines if a reset or
+ * interrupt is generated when LOCS2 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return status OSC1 Loss of Clock Status
+ * - 0: No loss of OSC1 external reference clock has occurred.
+ * - 1: Loss of OSC1 external reference clock has occurred.
+ */
+static inline mcg_locs2_status_t CLOCK_HAL_GetLocs2Mode(uint32_t baseAddr)
+{
+ return (mcg_locs2_status_t)BR_MCG_S2_LOCS2(baseAddr);
+}
+#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_MCG_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,2501 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcg_hal_modes.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*****************************************************************
+ * MCG clock mode transition functions
+ *
+ * FEI -> FEE
+ * FEI -> FBI
+ * FEI -> FBE
+ *
+ * FEE -> FEI
+ * FEE -> FBI
+ * FEE -> FBE
+ *
+ * FBI -> FEI
+ * FBI -> FEE
+ * FBI -> FBE
+ * FBI -> BLPI
+ *
+ * BLPI -> FBI
+ *
+ * FBE -> FEE
+ * FBE -> FEI
+ * FBE -> FBI
+ * FBE -> PBE
+ * FBE -> BLPE
+ *
+ * PBE -> FBE
+ * PBE -> PEE
+ * PBE -> BLPE
+ *
+ * BLPE -> FBE
+ * BLPE -> PBE
+ *
+ * PEE -> PBE
+ *
+ *****************************************************************/
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_GetMcgMode
+ * Description : internal function will check the mcg registers and determine
+ * the current mcg mode
+ *
+ * Return value : mcgMode or error code mcg_modes_t defined in fsl_mcg_hal_modes.h
+ *END***********************************************************************************/
+mcg_modes_t CLOCK_HAL_GetMcgMode(uint32_t baseAddr)
+{
+ /* Check MSG is in FEI mode */
+ if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) /* FLL ref is internal ref clk (IREFST=1) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */
+#else
+ )
+#endif
+ {
+ return kMcgModeFEI; /* return FEI code */
+ }
+ /* Check MCG is in PEE mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll) && /* CLKS mux is PLL output (CLKST=3) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)) /* PLLS mux is PLL or PLLCS (PLLST=1) */
+#else
+ )
+#endif
+ {
+ return kMcgModePEE; /* return PEE code */
+ }
+ /* Check MCG is in PBE mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) && /* PLLS mux is PLL or PLLCS (PLLST=1) */
+#endif
+ (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */
+ {
+ return kMcgModePBE; /* return PBE code */
+ }
+ /* Check MCG is in FBE mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */
+#endif
+ (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */
+ {
+ return kMcgModeFBE; /* return FBE code */
+ }
+ /* Check MCG is in BLPE mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */
+ (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */
+ {
+ return kMcgModeBLPE; /* return BLPE code */
+ }
+ /* Check if in BLPI mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */
+#endif
+ (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */
+ {
+ return kMcgModeBLPI; /* return BLPI code */
+ }
+ /* Check if in FBI mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */
+#endif
+ (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */
+ {
+ return kMcgModeFBI; /* return FBI code */
+ }
+ /* Check MCG is in FEE mode */
+ else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */
+ (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */
+#if FSL_FEATURE_MCG_HAS_PLL
+ && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */
+#else
+ )
+#endif
+ {
+ return kMcgModeFEE; /* return FEE code */
+ }
+ else
+ {
+ return kMcgModeError; /* error unknown mode */
+ }
+} /* CLOCK_HAL_GetMcgMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_GetFllFrequency
+ * Description : internal function to check the fll frequency
+ * This function will calculate and check the fll frequency value based on input value.
+ *
+ * Parameters: fllRef - fll reference clock in Hz.
+ *
+ * Return value : fll output frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_GetFllFrequency(uint32_t baseAddr, int32_t fllRef)
+{
+ int32_t fllFreqHz = 0;
+
+ /* Check that only allowed ranges have been selected */
+ if (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr) > kMcgDigitalControlledOscRangeSelMid)
+ {
+ return kMcgErrFllDrstDrsRange; /* return error code if DRS range 2 or 3 selected */
+ }
+
+ /* if DMX32 set */
+ if (CLOCK_HAL_GetDmx32(baseAddr))
+ {
+ /* determine multiplier based on DRS */
+ switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr))
+ {
+ case 0:
+ fllFreqHz = (fllRef * kMcgConstant732);
+ if (fllFreqHz < kMcgConstant20000000)
+ {
+ return kMcgErrFllRange0Min;
+ }
+ else if (fllFreqHz > kMcgConstant25000000)
+ {
+ return kMcgErrFllRange0Max;
+ }
+ break;
+ case 1:
+ fllFreqHz = (fllRef * kMcgConstant1464);
+ if (fllFreqHz < kMcgConstant40000000)
+ {
+ return kMcgErrFllRange1Min;
+ }
+ else if (fllFreqHz > kMcgConstant50000000)
+ {
+ return kMcgErrFllRange1Max;
+ }
+ break;
+ case 2:
+ fllFreqHz = (fllRef * kMcgConstant2197);
+ if (fllFreqHz < kMcgConstant60000000)
+ {
+ return kMcgErrFllRange2Min;
+ }
+ else if (fllFreqHz > kMcgConstant75000000)
+ {
+ return kMcgErrFllRange2Max;
+ }
+ break;
+ case 3:
+ fllFreqHz = (fllRef * kMcgConstant2929);
+ if (fllFreqHz < kMcgConstant80000000)
+ {
+ return kMcgErrFllRange3Min;
+ }
+ else if (fllFreqHz > kMcgConstant100000000)
+ {
+ return kMcgErrFllRange3Max;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ /* if DMX32 = 0 */
+ else
+ {
+ /* determine multiplier based on DRS */
+ switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr))
+ {
+ case 0:
+ fllFreqHz = (fllRef * kMcgConstant640);
+ if (fllFreqHz < kMcgConstant20000000)
+ {
+ return kMcgErrFllRange0Min;
+ }
+ else if (fllFreqHz > kMcgConstant25000000)
+ {
+ return kMcgErrFllRange0Max;
+ }
+ break;
+ case 1:
+ fllFreqHz = (fllRef * kMcgConstant1280);
+ if (fllFreqHz < kMcgConstant40000000)
+ {
+ return kMcgErrFllRange1Min;
+ }
+ else if (fllFreqHz > kMcgConstant50000000)
+ {
+ return kMcgErrFllRange1Max;
+ }
+ break;
+ case 2:
+ fllFreqHz = (fllRef * kMcgConstant1920);
+ if (fllFreqHz < kMcgConstant60000000)
+ {
+ return kMcgErrFllRange2Min;
+ }
+ else if (fllFreqHz > kMcgConstant75000000)
+ {
+ return kMcgErrFllRange2Max;
+ }
+ break;
+ case 3:
+ fllFreqHz = (fllRef * kMcgConstant2560);
+ if (fllFreqHz < kMcgConstant80000000)
+ {
+ return kMcgErrFllRange3Min;
+ }
+ else if (fllFreqHz > kMcgConstant100000000)
+ {
+ return kMcgErrFllRange3Max;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return fllFreqHz;
+} /* CLOCK_HAL_GetFllFrequency */
+
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeiToFeeMode
+ * Description : Mode transition FEI to FEE mode
+ * This function transitions the MCG from FEI mode to FEE mode.
+ *
+ * Parameters: oscselVal - oscillator selection value
+ * (eunm defined in mcg_oscsel_select_t)
+ * 0: kMcgOscselOsc, Selects System Oscillator (OSCCLK)
+ * 1: kMcgOscselRtc, Selects 32 kHz RTC Oscillator
+ * 2: kMcgOscselIrc, Selects 48 MHz IRC Oscillator (K70)
+ * crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * (enum defined in mcg_high_gain_osc_select_t)
+ * 0: kMcgHgoSelectLow, Configure for low-power operation
+ * 1: kMcgHgoSelectHigh, Configure for high-gain operation
+ * erefsVal - selects external clock or crystal osc
+ * (enum defined in mcg_external_ref_clock_select_t)
+ * 0: kMcgErefClockSelectExt, External reference clock requested
+ * 1: kMcgErefClockSelectOsc, Oscillator requested
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal)
+{
+ uint8_t frDivVal;
+ uint32_t mcgOut, fllRefFreq, i;
+
+ /* check if in FEI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI)
+ {
+ return kMcgErrNotInFeiMode; /* return error code */
+ }
+
+ /* check external frequency is less than the maximum frequency */
+ if (crystalVal > kMcgConstant50000000)
+ {
+ return kMcgErrOscEtalRange; /* - external frequency is bigger than max frequency */
+ }
+
+ /* check crystal frequency is within spec. if crystal osc is being used */
+ if (oscselVal == kMcgOscselOsc)
+ {
+ if (erefsVal)
+ {
+ /* return error if one of the available crystal options is not available */
+ if ((crystalVal < kMcgConstant30000) ||
+ ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) ||
+ (crystalVal > kMcgConstant32000000))
+ {
+ return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */
+ }
+
+ /* config the hgo settings */
+ CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal);
+ }
+
+ /* config the erefs0 settings */
+ CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal);
+ }
+
+ /*
+ * the RANGE value is determined by the external frequency. Since the RANGE parameter
+ * affects the FRDIV divide value it still needs to be set correctly even if the
+ * oscillator is not being used
+ */
+ if (crystalVal <= kMcgConstant40000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow);
+ }
+ else if (crystalVal <= kMcgConstant8000000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh);
+ }
+ else
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh);
+ }
+
+ /* determine FRDIV based on reference clock frequency */
+ /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */
+ if (crystalVal <= kMcgConstant1250000)
+ {
+ frDivVal = kMcgConstant0;
+ }
+ else if (crystalVal <= kMcgConstant2500000)
+ {
+ frDivVal = kMcgConstant1;
+ }
+ else if (crystalVal <= kMcgConstant5000000)
+ {
+ frDivVal = kMcgConstant2;
+ }
+ else if (crystalVal <= kMcgConstant10000000)
+ {
+ frDivVal = kMcgConstant3;
+ }
+ else if (crystalVal <= kMcgConstant20000000)
+ {
+ frDivVal = kMcgConstant4;
+ }
+ else
+ {
+ frDivVal = kMcgConstant5;
+ }
+
+ /* The FLL ref clk divide value depends on FRDIV and the RANGE value */
+ if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow)
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal));
+ }
+ else
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal));
+ }
+
+ /* Check resulting FLL frequency */
+ /* FLL reference frequency calculated from ext ref freq and FRDIV */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ return mcgOut; /* If error code returned, return the code to calling function */
+ }
+
+ /*
+ * Select external oscilator and Reference Divider and clear IREFS to start ext osc
+ * If IRCLK is required it must be enabled outside of this driver, existing state will
+ * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0
+ */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal);
+
+ /* if the external oscillator is used need to wait for OSCINIT to set */
+ if ((oscselVal == kMcgOscselOsc) && (erefsVal))
+ {
+ for (i = 0 ; i < kMcgConstant20000000 ; i++)
+ {
+ if (CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ break; /* jump out early if OSCINIT sets before loop finishes */
+ }
+ }
+
+ if (!CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrOscSetTimeout;
+ }
+ }
+
+ /* Wait for clock status bits to show clock source is FLL */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ break; // jump out early if CLKST shows FLL selected before loop finishes
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll)
+ {
+ return kMcgErrClkst0; // check FLL is really selected and return with error if not
+ }
+
+ /*
+ * Now in FEE
+ * It is recommended that the clock monitor is enabled when using an external clock as the
+ * clock source/reference.
+ * It is enabled here but can be removed if this is not required.
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true);
+
+ return mcgOut; /* MCGOUT frequency equals FLL frequency */
+} /* CLOCK_HAL_SetFeiToFeeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeiToFbiMode
+ * Description : Mode transition FEI to FBI mode
+ * This function transitions the MCG from FEI mode to FBI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value
+ * ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect)
+{
+ uint8_t fcrDivVal;
+ uint16_t i;
+
+ /* Check MCG is in FEI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI)
+ {
+ return kMcgErrNotInFeiMode; /* return error code */
+ }
+
+
+ /* Check that the irc frequency matches the selected IRC */
+ if (!(ircSelect))
+ {
+ if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+ }
+ else
+ {
+ if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000))
+ {
+ return kMcgErrIrcFastRange;
+ } /* Fast IRC freq */
+ }
+
+ /* Select the desired IRC */
+ CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect);
+
+ /* Change the CLKS mux to select the IRC as the MCGOUT */
+ CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelInternal);
+
+ /* Set LP bit to enable the FLL */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+ /* wait until internal reference switches to requested irc. */
+ if (ircSelect == kMcgInternalRefClkSelSlow)
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (!(MCG_S & MCG_S_IRCST_MASK))
+ {
+ break; /* jump out early if IRCST clears before loop finishes */
+ }
+ }
+ if (MCG_S & MCG_S_IRCST_MASK)
+ {
+ /* check bit is really clear and return with error if set */
+ return kMcgErrIrcstClearTimeout;
+ }
+ }
+ else
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (MCG_S & MCG_S_IRCST_MASK)
+ {
+ break; /* jump out early if IRCST sets before loop finishes */
+ }
+ }
+ if (!(MCG_S & MCG_S_IRCST_MASK))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout1;
+ }
+ }
+
+ /* Wait for clock status bits to update */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef)
+ {
+ break; /* jump out early if CLKST shows IRC slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef)
+ {
+ /* check IRC is really selected and return with error if not */
+ return kMcgErrClkst1;
+ }
+
+ /* Now in FBI mode */
+ if (ircSelect == kMcgInternalRefClkSelFast)
+ {
+ fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr);
+
+ /* MCGOUT frequency equals fast IRC frequency divided by 2 */
+ return (ircFreq / fcrDivVal);
+ }
+ else
+ {
+ return ircFreq; /* MCGOUT frequency equals slow IRC frequency */
+ }
+} /* CLOCK_HAL_SetFeiToFbiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeiToFbeMode
+ * Description : Mode transition FEI to FBE mode
+ * This function transitions the MCG from FEI mode to FBE mode.
+ *
+ * Parameters: oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * erefsVal - selects external clock (=0) or crystal osc (=1)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal)
+{
+ uint8_t frDivVal;
+ int16_t i;
+
+ /* check if in FEI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI)
+ {
+ return kMcgErrNotInFeiMode; /* return error code */
+ }
+
+ /* check external frequency is less than the maximum frequency */
+ if (crystalVal > kMcgConstant50000000)
+ {
+ /* - external frequency is bigger than max frequency */
+ return kMcgErrOscEtalRange;
+ }
+
+ /* check crystal frequency is within spec. if crystal osc is being used */
+ if (oscselVal == kMcgOscselOsc)
+ {
+ if (erefsVal)
+ {
+ /* return error if one of the available crystal options is not available */
+ if ((crystalVal < kMcgConstant30000) ||
+ ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) ||
+ (crystalVal > kMcgConstant32000000))
+ {
+ /* - crystal frequency outside allowed range */
+ return kMcgErrOscXtalRange;
+ }
+
+ /* config the hgo settings */
+ CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal);
+ }
+
+ /* config the erefs0 settings */
+ CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal);
+ }
+
+ /*
+ * the RANGE value is determined by the external frequency. Since the RANGE parameter
+ * affects the FRDIV divide value it still needs to be set correctly even if the
+ * oscillator is not being used
+ */
+ if (crystalVal <= kMcgConstant40000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow);
+ }
+ else if (crystalVal <= kMcgConstant8000000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh);
+ }
+ else
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh);
+ }
+
+ /* determine FRDIV based on reference clock frequency */
+ /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */
+ if (crystalVal <= kMcgConstant1250000)
+ {
+ frDivVal = kMcgConstant0;
+ }
+ else if (crystalVal <= kMcgConstant2500000)
+ {
+ frDivVal = kMcgConstant1;
+ }
+ else if (crystalVal <= kMcgConstant5000000)
+ {
+ frDivVal = kMcgConstant2;
+ }
+ else if (crystalVal <= kMcgConstant10000000)
+ {
+ frDivVal = kMcgConstant3;
+ }
+ else if (crystalVal <= kMcgConstant20000000)
+ {
+ frDivVal = kMcgConstant4;
+ }
+ else
+ {
+ frDivVal = kMcgConstant5;
+ }
+
+ /* Set LP bit to enable the FLL */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+ /*
+ * Select external oscilator and Reference Divider and clear IREFS to start ext osc
+ * If IRCLK is required it must be enabled outside of this driver, existing state will
+ * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0
+ */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal);
+
+ /* if the external oscillator is used need to wait for OSCINIT to set */
+ if ((oscselVal == kMcgOscselOsc) && (erefsVal))
+ {
+ for (i = 0 ; i < kMcgConstant10000 ; i++)
+ {
+ if (CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ break; /* jump out early if OSCINIT sets before loop finishes */
+ }
+ }
+
+ if (!CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrOscSetTimeout;
+ }
+ }
+
+ /* wait for Reference clock Status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ break; /* jump out early if IREFST clears before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ /* check bit is really clear and return with error if not set */
+ return kMcgErrIrefstClearTimeOut;
+ }
+
+ /* Wait for clock status bits to show clock source is ext ref clk */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */
+ }
+
+ /*
+ * Now in FBE
+ * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference.
+ * It is enabled here but can be removed if this is not required.
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true);
+
+ return crystalVal; /* MCGOUT frequency equals external clock frequency */
+} /* CLOCK_HAL_SetFeiToFbeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeeToFeiMode
+ * Description : Mode transition FEE to FEI mode
+ * This function transitions the MCG from FEE mode to FEI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value (slow)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeeToFeiMode(uint32_t baseAddr, uint32_t ircFreq)
+{
+ int16_t i;
+ uint32_t mcgOut;
+
+ /* Check MCG is in FEE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE)
+ {
+ return kMcgErrNotInFeeMode; /* return error code */
+ }
+
+ /* Check IRC frequency is within spec. */
+ if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+
+ /* Check resulting FLL frequency */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ /* If error code returned, return the code to calling function */
+ return mcgOut;
+ }
+
+ /* Ensure clock monitor is disabled before switching to FEI otherwise
+ * a loss of clock will trigger
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false);
+
+ /* Change FLL reference clock from external to internal by setting IREFS bit */
+ CLOCK_HAL_SetInternalRefSelMode(baseAddr, kMcgInternalRefClkSrcSlow);
+
+ /* wait for Reference clock to switch to internal reference */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal)
+ {
+ break; /* jump out early if IREFST sets before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout;
+ }
+
+ /* Now in FEI mode */
+ return mcgOut;
+} /* CLOCK_HAL_SetFeeToFeiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeeToFbiMode
+ * Description : Mode transition FEE to FBI mode
+ * This function transitions the MCG from FEE mode to FBI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value
+ * ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect)
+{
+ uint8_t fcrDivVal;
+ int16_t i;
+
+ /* Check MCG is in FEE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE)
+ {
+ return kMcgErrNotInFeeMode; /* return error code */
+ }
+
+ /* Check that the irc frequency matches the selected IRC */
+ if (!(ircSelect))
+ {
+ if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+ }
+ else
+ {
+ if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000))
+ {
+ return kMcgErrIrcFastRange;
+ } /* Fast IRC freq */
+ }
+
+ /* Select the required IRC */
+ CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect);
+
+ /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false);
+
+ /* Select the IRC as the CLKS mux selection */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow);
+
+ /* wait until internal reference switches to requested irc. */
+ if (ircSelect == kMcgInternalRefClkSelSlow)
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow)
+ {
+ break; /* jump out early if IRCST clears before loop finishes */
+ }
+ }
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow)
+ {
+ /* check bit is really clear and return with error if set */
+ return kMcgErrIrcstClearTimeout;
+ }
+ }
+ else
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast)
+ {
+ break; /* jump out early if IRCST sets before loop finishes */
+ }
+ }
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout1;
+ }
+ }
+
+ /* Wait for clock status bits to update */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef)
+ {
+ break; /* jump out early if CLKST shows IRC slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef)
+ {
+ return kMcgErrClkst1; /* check IRC is really selected and return with error if not */
+ }
+
+ /* wait for Reference clock Status bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal)
+ {
+ break; /* jump out early if IREFST sets before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout;
+ }
+
+ /* Now in FBI mode */
+ if (ircSelect == kMcgInternalRefClkSelFast)
+ {
+ fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr);
+
+ return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */
+ }
+ else
+ {
+ return ircFreq; /* MCGOUT frequency equals slow IRC frequency */
+ }
+} /* CLOCK_HAL_SetFeeToFbiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeeToFbeMode
+ * Description : Mode transition FEE to FBE mode
+ * This function transitions the MCG from FEE mode to FBE mode.
+ *
+ * Parameters: crystalVal - external reference clock frequency value
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFeeToFbeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ uint16_t i;
+
+ /* Check MCG is in FEE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE)
+ {
+ return kMcgErrNotInFeeMode; /* return error code */
+ }
+
+ /* Set CLKS field to 2 to switch CLKS mux to select ext ref clock */
+ CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal);
+
+ /* Wait for clock status bits to show clock source is ext ref clk */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef)
+ {
+ break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */
+ }
+
+ /* Now in FBE mode */
+ return crystalVal;
+} /* CLOCK_HAL_SetFeeToFbeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbiToFeiMode
+ * Description : Mode transition FBI to FEI mode
+ * This function transitions the MCG from FBI mode to FEI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value (slow)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbiToFeiMode(uint32_t baseAddr, uint32_t ircFreq)
+{
+ int16_t i;
+ int32_t mcgOut;
+
+ /* check if in FBI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI)
+ {
+ return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */
+ }
+
+ /* Check IRC frequency is within spec. */
+ if ((ircFreq < 31250) || (ircFreq > 39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+
+ /* Check resulting FLL frequency */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ /* If error code returned, return the code to calling function */
+ return mcgOut;
+ }
+
+ /* Change the CLKS mux to select the FLL output as MCGOUT */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow);
+
+ /* wait for Reference clock Status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ break; /* jump out early if IREFST clears before loop finishes */
+ }
+ }
+
+ if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout;
+ }
+
+ /* Wait for clock status bits to show clock source is ext ref clk */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ break; /* jump out early if CLKST shows FLL slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ return kMcgErrClkst0; /* check FLL is really selected and return with error if not */
+ }
+
+ /* Now in FEI mode */
+ return mcgOut;
+} /* CLOCK_HAL_SetFbiToFeiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbiToFeeMode
+ * Description : Mode transition FBI to FEE mode
+ * This function transitions the MCG from FBI mode to FEE mode.
+ *
+ * Parameters: oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * erefsVal - selects external clock (=0) or crystal osc (=1)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal)
+{
+ uint8_t frDivVal;
+ uint32_t i;
+ uint32_t mcgOut, fllRefFreq;
+
+ /* check if in FBI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI)
+ {
+ return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */
+ }
+
+ /* check external frequency is less than the maximum frequency */
+ if (crystalVal > kMcgConstant50000000)
+ {
+ return kMcgErrOscEtalRange;
+ }
+
+ /* check crystal frequency is within spec. if crystal osc is being used */
+ if (oscselVal == kMcgOscselOsc)
+ {
+ if (erefsVal)
+ {
+ /* return error if one of the available crystal options is not available */
+ if ((crystalVal < kMcgConstant30000) ||
+ ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) ||
+ (crystalVal > kMcgConstant32000000))
+ {
+ return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */
+ }
+
+ /* config the hgo settings */
+ CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal);
+ }
+
+ /* config the erefs0 settings */
+ CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal);
+ }
+
+ /*
+ * the RANGE value is determined by the external frequency. Since the RANGE parameter
+ * affects the FRDIV divide value it still needs to be set correctly even if the
+ * oscillator is not being used
+ */
+ if (crystalVal <= kMcgConstant40000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow);
+ }
+ else if (crystalVal <= kMcgConstant8000000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh);
+ }
+ else
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh);
+ }
+
+ /* determine FRDIV based on reference clock frequency */
+ /* since the external frequency has already been checked only the maximum frequency for each FRDIV
+ * value needs to be compared here.
+ */
+ if (crystalVal <= kMcgConstant1250000)
+ {
+ frDivVal = kMcgConstant0;
+ }
+ else if (crystalVal <= kMcgConstant2500000)
+ {
+ frDivVal = kMcgConstant1;
+ }
+ else if (crystalVal <= kMcgConstant5000000)
+ {
+ frDivVal = kMcgConstant2;
+ }
+ else if (crystalVal <= kMcgConstant10000000)
+ {
+ frDivVal = kMcgConstant3;
+ }
+ else if (crystalVal <= kMcgConstant20000000)
+ {
+ frDivVal = kMcgConstant4;
+ }
+ else
+ {
+ frDivVal = kMcgConstant5;
+ }
+
+ /* The FLL ref clk divide value depends on FRDIV and the RANGE value */
+ if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow)
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal));
+ }
+ else
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal));
+ }
+
+ /* Check resulting FLL frequency */
+ /* FLL reference frequency calculated from ext ref freq and FRDIV */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ return mcgOut; /* If error code returned, return the code to calling function */
+ }
+
+ /*
+ * Select external oscilator and Reference Divider and clear IREFS to start ext osc
+ * If IRCLK is required it must be enabled outside of this driver, existing state will
+ * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0
+ */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal);
+
+ /* if the external oscillator is used need to wait for OSCINIT to set */
+ if ((oscselVal == kMcgOscselOsc) && (erefsVal))
+ {
+ for (i = 0 ; i < kMcgConstant20000000 ; i++)
+ {
+ if (CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ break; /* jump out early if OSCINIT sets before loop finishes */
+ }
+ }
+
+ if (!CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrOscSetTimeout;
+ }
+ }
+
+ /* Wait for clock status bits to show clock source is FLL */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ break; // jump out early if CLKST shows FLL selected before loop finishes
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll)
+ {
+ return kMcgErrClkst0; // check FLL is really selected and return with error if not
+ }
+
+ /*
+ * Now in FEE
+ * It is recommended that the clock monitor is enabled when using an external clock as the
+ * clock source/reference.
+ * It is enabled here but can be removed if this is not required.
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true);
+
+ return mcgOut; /* MCGOUT frequency equals FLL frequency */
+} /* CLOCK_HAL_SetFbiToFeeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbiToFbeMode
+ * Description : Mode transition FBI to FBE mode
+ * This function transitions the MCG from FBI mode to FBE mode.
+ *
+ * Parameters: oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * erefsVal - selects external clock (=0) or crystal osc (=1)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal)
+{
+ uint8_t frDivVal;
+ uint16_t i;
+
+ /* check if in FBI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI)
+ {
+ return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */
+ }
+
+ /* check external frequency is less than the maximum frequency */
+ if (crystalVal > kMcgConstant50000000)
+ {
+ return kMcgErrOscEtalRange;
+ }
+
+ /* check crystal frequency is within spec. if crystal osc is being used */
+ if (oscselVal == kMcgOscselOsc)
+ {
+ if (erefsVal)
+ {
+ /* return error if one of the available crystal options is not available */
+ if ((crystalVal < kMcgConstant30000) ||
+ ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) ||
+ (crystalVal > kMcgConstant32000000))
+ {
+ return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */
+ }
+
+ /* config the hgo settings */
+ CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal);
+ }
+
+ /* config the erefs0 settings */
+ CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal);
+ }
+
+ /*
+ * the RANGE value is determined by the external frequency. Since the RANGE parameter
+ * affects the FRDIV divide value it still needs to be set correctly even if the
+ * oscillator is not being used
+ */
+ if (crystalVal <= kMcgConstant40000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow);
+ }
+ else if (crystalVal <= kMcgConstant8000000)
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh);
+ }
+ else
+ {
+ CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh);
+ }
+
+ /* determine FRDIV based on reference clock frequency */
+ /* since the external frequency has already been checked only the maximum frequency for each FRDIV
+ * value needs to be compared here.
+ */
+ if (crystalVal <= kMcgConstant1250000)
+ {
+ frDivVal = kMcgConstant0;
+ }
+ else if (crystalVal <= kMcgConstant2500000)
+ {
+ frDivVal = kMcgConstant1;
+ }
+ else if (crystalVal <= kMcgConstant5000000)
+ {
+ frDivVal = kMcgConstant2;
+ }
+ else if (crystalVal <= kMcgConstant10000000)
+ {
+ frDivVal = kMcgConstant3;
+ }
+ else if (crystalVal <= kMcgConstant20000000)
+ {
+ frDivVal = kMcgConstant4;
+ }
+ else
+ {
+ frDivVal = kMcgConstant5;
+ }
+
+ /* Set LP bit to enable the FLL */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+ /*
+ * Select external oscilator and Reference Divider and clear IREFS to start ext osc
+ * If IRCLK is required it must be enabled outside of this driver, existing state will be maintained
+ * CLKS=2, FRDIV=frdiv_val, IREFS=0
+ */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal);
+
+ /* if the external oscillator is used need to wait for OSCINIT to set */
+ if ((oscselVal == kMcgOscselOsc) && (erefsVal))
+ {
+ for (i = 0 ; i < kMcgConstant10000 ; i++)
+ {
+ if (CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ break; /* jump out early if OSCINIT sets before loop finishes */
+ }
+ }
+
+ if (!CLOCK_HAL_GetOscInit0(baseAddr))
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrOscSetTimeout;
+ }
+ }
+
+ /* wait for Reference clock Status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ break; /* jump out early if IREFST clears before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr))
+ {
+ /* check bit is really clear and return with error if not set */
+ return kMcgErrIrefstClearTimeOut;
+ }
+
+ /* Wait for clock status bits to show clock source is ext ref clk */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */
+ }
+
+ /*
+ * Now in FBE
+ * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference.
+ * It is enabled here but can be removed if this is not required.
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true);
+
+ return crystalVal; /* MCGOUT frequency equals external clock frequency */
+} /* CLOCK_HAL_SetFbiToFbeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbiToBlpiMode
+ * Description : Mode transition FBI to BLPI mode
+ * This function transitions the MCG from FBI mode to BLPI mode.This is
+ * achieved by setting the MCG_C2[LP] bit.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value
+ * ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbiToBlpiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect)
+{
+ uint8_t fcrDivVal;
+
+ /* check if in FBI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI)
+ {
+ return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */
+ }
+
+ /* Set LP bit to disable the FLL and enter BLPI */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower);
+
+ /* Now in BLPI */
+ if (ircSelect == kMcgInternalRefClkSelFast)
+ {
+ fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr);
+ return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */
+ }
+ else
+ {
+ return ircFreq; /* MCGOUT frequency equals slow IRC frequency */
+ }
+} /* CLOCK_HAL_SetFbiToBlpiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetBlpiToFbiMode
+ * Description : Mode transition BLPI to FBI mode
+ * This function transitions the MCG from BLPI mode to FBI mode.This is
+ * achieved by clearing the MCG_C2[LP] bit.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value
+ * ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetBlpiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, uint8_t ircSelect)
+{
+ uint8_t fcrDivVal;
+
+ /* check if in BLPI mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPI)
+ {
+ return kMcgErrNotInBlpiMode; /* MCG not in correct mode return fail code */
+ }
+
+ /* Clear LP bit to enable the FLL and enter FBI mode */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+ /* Now in FBI mode */
+ if (ircSelect)
+ {
+ fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr);
+ return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */
+ }
+ else
+ {
+ return ircFreq; /* MCGOUT frequency equals slow IRC frequency */
+ }
+} /* CLOCK_HAL_SetBlpiToFbiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeToFeeMode
+ * Description : Mode transition FBE to FEE mode
+ * This function transitions the MCG from FBE mode to FEE mode.
+ *
+ * Parameters: crystalVal - external reference clock frequency value
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToFeeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ uint16_t i, fllRefFreq, frDivVal;
+ uint32_t mcgOut;
+
+ /* Check MCG is in FBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE)
+ {
+ return kMcgErrNotInFbeMode; /* return error code */
+ }
+
+ /* get curretn frdiv value */
+ frDivVal = CLOCK_HAL_GetFllExternalRefDivider(baseAddr);
+
+ /* The FLL ref clk divide value depends on FRDIV and the RANGE value */
+ if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow)
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal));
+ }
+ else
+ {
+ fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal));
+ }
+
+ /* Check resulting FLL frequency */
+ /* FLL reference frequency calculated from ext ref freq and FRDIV */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ return mcgOut; /* If error code returned, return the code to calling function */
+ }
+
+ /* Clear CLKS field to switch CLKS mux to select FLL output */
+ CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut);
+
+ /* Wait for clock status bits to show clock source is FLL */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ break; // jump out early if CLKST shows FLL selected before loop finishes
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll)
+ {
+ return kMcgErrClkst0; // check FLL is really selected and return with error if not
+ }
+
+ /* Now in FEE mode */
+ return mcgOut;
+} /* CLOCK_HAL_SetFbeToFeeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeToFeiMode
+ * Description : Mode transition FBE to FEI mode
+ * This function transitions the MCG from FBE mode to FEI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value (slow)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToFeiMode(uint32_t baseAddr, uint32_t ircFreq)
+{
+ uint16_t i;
+ uint32_t mcgOut;
+
+ /* Check MCG is in FBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE)
+ {
+ return kMcgErrNotInFbeMode; /* return error code */
+ }
+
+ /* Check IRC frequency is within spec. */
+ if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+
+ /* Check resulting FLL frequency */
+ mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq);
+ if (mcgOut < kMcgErrMax)
+ {
+ /* If error code returned, return the code to calling function */
+ return mcgOut;
+ }
+
+ /*
+ * Ensure clock monitor is disabled before switching to FEI otherwise
+ * a loss of clock will trigger. This assumes OSC0 is used as the external clock source.
+ */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false);
+
+ // Move to FEI by setting CLKS to 0 and enabling the slow IRC as the FLL reference clock
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow);
+
+ /* wait for Reference clock to switch to internal reference */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal)
+ {
+ break; /* jump out early if IREFST sets before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout;
+ }
+
+ /* Wait for clock status bits to show clock source is FLL output */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll)
+ {
+ /* jump out early if CLKST shows FLL output slected before loop finishes */
+ break;
+ }
+ }
+
+ /* check FLL output is really selected */
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll)
+ {
+ /* return with error if not */
+ return kMcgErrClkst0;
+ }
+
+ /* Now in FEI mode */
+ return mcgOut;
+} /* CLOCK_HAL_SetFbeToFeiMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeToFbiMode
+ * Description : Mode transition FBE to FBI mode
+ * This function transitions the MCG from FBE mode to FBI mode.
+ *
+ * Parameters: ircFreq - internal reference clock frequency value
+ * ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect)
+{
+ uint8_t fcrDivVal;
+ uint16_t i;
+
+ /* Check MCG is in FBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE)
+ {
+ return kMcgErrNotInFbeMode; /* return error code */
+ }
+
+ /* Check that the irc frequency matches the selected IRC */
+ if (!(ircSelect))
+ {
+ if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063))
+ {
+ return kMcgErrIrcSlowRange;
+ }
+ }
+ else
+ {
+ if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000))
+ {
+ return kMcgErrIrcFastRange;
+ } /* Fast IRC freq */
+ }
+
+ /* Select the required IRC */
+ CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect);
+
+ /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */
+ CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false);
+
+ /* Select the IRC as the CLKS mux selection */
+ CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow);
+
+ /* wait until internal reference switches to requested irc. */
+ if (ircSelect == kMcgInternalRefClkSelSlow)
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow)
+ {
+ break; /* jump out early if IRCST clears before loop finishes */
+ }
+ }
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow)
+ {
+ /* check bit is really clear and return with error if set */
+ return kMcgErrIrcstClearTimeout;
+ }
+ }
+ else
+ {
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast)
+ {
+ break; /* jump out early if IRCST sets before loop finishes */
+ }
+ }
+ if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout1;
+ }
+ }
+
+ /* Wait for clock status bits to update */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef)
+ {
+ break; /* jump out early if CLKST shows IRC slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef)
+ {
+ return kMcgErrClkst1; /* check IRC is really selected and return with error if not */
+ }
+
+ /* wait for Reference clock Status bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal)
+ {
+ break; /* jump out early if IREFST sets before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal)
+ {
+ /* check bit is really set and return with error if not set */
+ return kMcgErrIrefstSetTimeout;
+ }
+
+ /* Now in FBI mode */
+ if (ircSelect == kMcgInternalRefClkSelFast)
+ {
+ fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr);
+
+ return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */
+ }
+ else
+ {
+ return ircFreq; /* MCGOUT frequency equals slow IRC frequency */
+ }
+} /* CLOCK_HAL_SetFbeToFbiMode */
+
+#if FSL_FEATURE_MCG_HAS_PLL
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeToPbeMode
+ * Description : Mode transition FBE to PBE mode
+ * This function transitions the MCG from FBE mode to PBE mode.
+ * The function requires the desired OSC and PLL be passed in to it for compatibility
+ * with the future support of OSC/PLL selection
+ * (This function presently only supports OSC0 as PLL source)
+ * Parameters: crystalVal - external clock frequency in Hz
+ * pllcsSelect - 0 to select PLL0, non-zero to select PLL1.
+ * prdivVal - value to divide the external clock source by to create
+ * the desired PLL reference clock frequency
+ * vdivVal - value to multiply the PLL reference clock frequency by
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect,
+ uint8_t prdivVal, uint8_t vdivVal)
+{
+ uint16_t i;
+ uint32_t pllFreq;
+
+ /* Check MCG is in FBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE)
+ {
+ return kMcgErrNotInFbeMode; /* return error code */
+ }
+
+ /*
+ * As the external frequency (osc0) has already been checked when FBE mode was enterred
+ * it is not checked here.
+ */
+
+ /* Check PLL divider settings are within spec.*/
+ if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX))
+ {
+ return kMcgErrPllPrdidRange;
+ }
+
+ if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31)))
+ {
+ return kMcgErrPllVdivRange;
+ }
+
+ /* Check PLL reference clock frequency is within spec. */
+ if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000))
+ {
+ return kMcgErrPllRefClkRange;
+ }
+
+ /* Check PLL output frequency is within spec. */
+ pllFreq = (crystalVal / prdivVal) * vdivVal;
+ if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000))
+ {
+ return kMcgErrPllOutClkRange;
+ }
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+ /* set pllcsSelect */
+ CLOCK_HAL_SetPllcs(pllcsSelect);
+
+ if (pllcsSelect == kMcgPllcsSelectPll0)
+#endif
+ {
+ /*
+ * Configure MCG_C5
+ * If the PLL is to run in STOP mode then the PLLSTEN bit needs
+ * to be OR'ed in here or in user code.
+ */
+
+ CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1);
+
+ /*
+ * Configure MCG_C6
+ * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk
+ * The clock monitor is not enabled here as it has likely been enabled previously and
+ * so the value of CME is not altered here.
+ * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6
+ */
+
+ CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel);
+
+ // wait for PLLST status bit to set
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel))
+ {
+ /* return with error if not set */
+ return kMcgErrPllstSetTimeout;
+ }
+
+ /* Wait for LOCK bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+#if FSL_FEATURE_MCG_USE_PLLREFSEL
+ /* wait for PLLCST status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0)
+ {
+ /* return with error if not set */
+ return kMcgErrPllcst;
+ }
+#endif
+ }
+#if FSL_FEATURE_MCG_HAS_PLL1
+ else
+ {
+ /*
+ * Configure MCG_C11
+ * If the PLL is to run in STOP mode
+ * then the PLLSTEN bit needs to be OR'ed in here or in user code.
+ */
+ CLOCK_HAL_SetPrdiv1(prdivVal - 1);
+
+ /*
+ * Configure MCG_C12
+ * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk
+ * The clock monitor is not enabled here as it has likely been enabled previously
+ * and so the value of CME is not altered here.
+ * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit
+ * in MCG_C12
+ */
+
+ CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel);
+
+ // wait for PLLST status bit to set
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel))
+ {
+ /* return with error if not set */
+ return kMcgErrPllstSetTimeout;
+ }
+
+ /* Wait for LOCK bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+ /* wait for PLLCST status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1)
+ {
+ /* return with error if not set */
+ return kMcgErrPllcst;
+ }
+ }
+#endif /* PLL1 is selected */
+
+ /* now in PBE */
+
+ /* MCGOUT frequency equals external clock frequency */
+ return crystalVal;
+} /* CLOCK_HAL_SetFbeToPbeMode */
+#endif
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeToBlpeMode
+ * Description : Mode transition FBE to BLPE mode
+ * This function transitions the MCG from FBE mode to BLPE mode.
+ *
+ * Parameters: crystalVal - external clock frequency in Hz
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ /* Check MCG is in FBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE)
+ {
+ return kMcgErrNotInFbeMode; /* return error code */
+ }
+
+ /* To move from FBE to BLPE the LP bit must be set */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower);
+
+ /* now in FBE mode */
+
+ /* MCGOUT frequency equals external clock frequency */
+ return crystalVal;
+} /* CLOCK_HAL_SetFbeToBlpeMode */
+
+#if FSL_FEATURE_MCG_HAS_PLL
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPbeToFbeMode
+ * Description : Mode transition PBE to FBE mode
+ * This function transitions the MCG from PBE mode to FBE mode.
+ *
+ * Parameters: crystalVal - external clock frequency in Hz
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetPbeToFbeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ int16_t i;
+
+ /* Check MCG is in PBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE)
+ {
+ return kMcgErrNotInPbeMode; /* return error code */
+ }
+
+ /*
+ * As we are running from the ext clock, by default the external clock settings are valid
+ * To move to FBE from PBE simply requires the switching of the PLLS mux to disable the PLL
+ */
+
+ CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll);
+
+ /* wait for PLLST status bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)
+ {
+ /* jump out early if PLLST clears before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really clear */
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll)
+ {
+ /* return with error if not clear */
+ return kMcgErrPllstClearTimeout;
+ }
+
+ /* Now in FBE mode */
+
+ /* MCGOUT frequency equals external clock frequency */
+ return crystalVal;
+} /* CLOCK_HAL_SetPbeToFbeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPbeToPeeMode
+ * Description : Mode transition PBE to PEE mode
+ * This function transitions the MCG from PBE mode to PEE mode.
+ *
+ * Parameters: crystalVal - external clock frequency in Hz
+ * pllcsSelect - PLLCS select setting
+ * mcg_pll_clk_select_t is defined in fsl_mcg_hal.h
+ * 0: kMcgPllcsSelectPll0 PLL0 output clock is selected
+ * 1: kMcgPllcsSelectPll1 PLL1 output clock is selected
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetPbeToPeeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect)
+{
+ uint8_t prDiv, vDiv;
+ uint16_t i;
+ uint32_t mcgOut;
+
+ /* Check MCG is in PBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE)
+ {
+ return kMcgErrNotInPbeMode; /* return error code */
+ }
+
+ /* As the PLL settings have already been checked when PBE mode was enterred they are not checked here */
+
+ /* Check the PLL state before transitioning to PEE mode */
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+ /* Check the selected PLL state before transitioning to PEE mode */
+ if (pllcsSelect == kMcgPllcsSelectPll1)
+ {
+ /* Check LOCK bit is set before transitioning MCG to PLL output */
+ /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+ /* Use actual PLL settings to calculate PLL frequency */
+ prDiv = (CLOCK_HAL_GetPrdiv1(baseAddr) + 1);
+ vDiv = (CLOCK_HAL_GetVdiv1(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ }
+ else
+#endif
+ {
+ /* Check LOCK bit is set before transitioning MCG to PLL output */
+ /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+ /* Use actual PLL settings to calculate PLL frequency */
+ prDiv = (CLOCK_HAL_GetPllExternalRefDivider0(baseAddr) + 1);
+ vDiv = (CLOCK_HAL_GetVoltCtrlOscDivider0(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ }
+
+ /* clear CLKS to switch CLKS mux to select PLL as MCG_OUT */
+ CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut);
+
+ /* Wait for clock status bits to update */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll)
+ {
+ break; /* jump out early if CLKST = 3 before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatPll)
+ {
+ return kMcgErrClkst3; /* check CLKST is set correctly and return with error if not */
+ }
+
+ /* Now in PEE */
+
+ /* MCGOUT equals PLL output frequency with any special divider */
+ mcgOut = (crystalVal / prDiv) * vDiv;
+
+ return mcgOut;
+} /* CLOCK_HAL_SetPbeToPeeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPbeToBlpeMode
+ * Description : Mode transition PBE to BLPE mode
+ * This function transitions the MCG from PBE mode to BLPE mode.
+ *
+ * Parameters: crystalVal - external clock frequency in Hz
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetPbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ /* Check MCG is in PBE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE)
+ {
+ return kMcgErrNotInPbeMode; /* return error code */
+ }
+
+ /* To enter BLPE mode the LP bit must be set, disabling the PLL */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower);
+
+ /* Now in BLPE mode */
+ return crystalVal;
+} /* CLOCK_HAL_SetPbeToBlpeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPeeToPbeMode
+ * Description : Mode transition PEE to PBE mode
+ * This function transitions the MCG from PEE mode to PBE mode.
+ *
+ * Parameters: crystalVal - external clock frequency in Hz
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetPeeToPbeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+ uint16_t i;
+
+ /* Check MCG is in PEE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePEE)
+ {
+ return kMcgErrNotInPeeMode; /* return error code */
+ }
+
+ /*
+ * As we are running from the PLL by default the PLL and external clock settings are valid
+ * To move to PBE from PEE simply requires the switching of the CLKS mux to select the ext clock
+ */
+ /* As CLKS is already 0 the CLKS value can simply be OR'ed into the register */
+ CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal);
+
+ /* Wait for clock status bits to update */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef)
+ {
+ break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */
+ }
+ }
+
+ if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef)
+ {
+ return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */
+ }
+
+ /* Now in PBE mode */
+ return crystalVal; /* MCGOUT frequency equals external clock frequency */
+} /* CLOCK_HAL_SetPeeToPbeMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetBlpeToPbeMode
+ * Description : Mode transition BLPE to PBE mode
+ * This function transitions the MCG from BLPE mode to PBE mode.
+ * The function requires the desired OSC and PLL be passed in to it for compatibility
+ * with the future support of OSC/PLL selection
+ * (This function presently only supports OSC0 as PLL source)
+ * Parameters: crystalVal - external clock frequency in Hz
+ * pllcsSelect - 0 to select PLL0, non-zero to select PLL1.
+ * prdivVal - value to divide the external clock source by to create
+ * the desired PLL reference clock frequency
+ * vdivVal - value to multiply the PLL reference clock frequency by
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetBlpeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect, uint8_t prdivVal, uint8_t vdivVal)
+{
+ uint16_t i;
+ uint32_t pllFreq;
+
+ /* Check MCG is in BLPE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE)
+ {
+ return kMcgErrNotInBlpeMode; /* return error code */
+ }
+
+ /*
+ * As the external frequency (osc0) has already been checked when FBE mode was enterred
+ * it is not checked here.
+ */
+
+ /* Check PLL divider settings are within spec.*/
+ if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX))
+ {
+ return kMcgErrPllPrdidRange;
+ }
+
+ if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31)))
+ {
+ return kMcgErrPllVdivRange;
+ }
+
+ /* Check PLL reference clock frequency is within spec. */
+ if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000))
+ {
+ return kMcgErrPllRefClkRange;
+ }
+
+ /* Check PLL output frequency is within spec. */
+ pllFreq = (crystalVal / prdivVal) * vdivVal;
+ if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000))
+ {
+ return kMcgErrPllOutClkRange;
+ }
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+ /* set pllcsSelect */
+ CLOCK_HAL_SetPllcs(pllcsSelect);
+
+ if (pllcsSelect == kMcgPllcsSelectPll0)
+#endif
+ {
+ /*
+ * Configure MCG_C5
+ * If the PLL is to run in STOP mode then the PLLSTEN bit needs
+ * to be OR'ed in here or in user code.
+ */
+
+ CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1);
+
+ /*
+ * Configure MCG_C6
+ * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk
+ * The clock monitor is not enabled here as it has likely been enabled previously and
+ * so the value of CME is not altered here.
+ * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6
+ */
+
+ CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel);
+
+ /* Set LP bit to enable the PLL */
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+ // wait for PLLST status bit to set
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel))
+ {
+ /* return with error if not set */
+ return kMcgErrPllstSetTimeout;
+ }
+
+ /* Wait for LOCK bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+#if FSL_FEATURE_MCG_USE_PLLREFSEL
+ /* wait for PLLCST status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0)
+ {
+ /* return with error if not set */
+ return kMcgErrPllcst;
+ }
+#endif
+ }
+#if FSL_FEATURE_MCG_HAS_PLL1
+ else
+ {
+ /*
+ * Configure MCG_C11
+ * If the PLL is to run in STOP mode
+ * then the PLLSTEN bit needs to be OR'ed in here or in user code.
+ */
+ CLOCK_HAL_SetPrdiv1(prdivVal - 1);
+
+ /*
+ * Configure MCG_C12
+ * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk
+ * The clock monitor is not enabled here as it has likely been enabled previously
+ * and so the value of CME is not altered here.
+ * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit
+ * in MCG_C12
+ */
+
+ CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE);
+ CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel);
+
+ /* Set LP bit to enable the PLL */
+ CLOCK_HAL_SetLowPowerMode(kMcgLowPowerSelNormal);
+
+ // wait for PLLST status bit to set
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel))
+ {
+ /* return with error if not set */
+ return kMcgErrPllstSetTimeout;
+ }
+
+ /* Wait for LOCK bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked)
+ {
+ /* jump out early if LOCK sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked))
+ {
+ /* return with error if not set */
+ return kMcgErrPllLockBit;
+ }
+
+ /* wait for PLLCST status bit to clear */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1)
+ {
+ /* jump out early if PLLST sets before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really set */
+ if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1)
+ {
+ /* return with error if not set */
+ return kMcgErrPllcst;
+ }
+ }
+#endif /* PLL1 is selected */
+
+ /* now in PBE */
+
+ /* MCGOUT frequency equals external clock frequency */
+ return crystalVal;
+} /* CLOCK_HAL_SetBlpeToPbeMode */
+#endif
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetBlpeToFbeMode
+ * Description : Mode transition BLPE to FBE mode
+ * This function transitions the MCG from BLPE mode to FBE mode.
+ *
+ * Parameters: crystalVal - external reference clock frequency value
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetBlpeToFbeMode(uint32_t baseAddr, uint32_t crystalVal)
+{
+#if FSL_FEATURE_MCG_HAS_PLL
+ uint16_t i;
+#endif
+
+ /* Check MCG is in BLPE mode */
+ if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE)
+ {
+ return kMcgErrNotInBlpeMode; /* return error code */
+ }
+
+ /* To move from BLPE to FBE the PLLS mux be set to select the FLL output*/
+ /* and the LP bit must be cleared */
+#if FSL_FEATURE_MCG_HAS_PLL
+ CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll);
+#endif
+ CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal);
+
+#if FSL_FEATURE_MCG_HAS_PLL
+ /* wait for PLLST status bit to set */
+ for (i = 0 ; i < kMcgConstant2000 ; i++)
+ {
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)
+ {
+ /* jump out early if PLLST clears before loop finishes */
+ break;
+ }
+ }
+
+ /* check bit is really clear */
+ if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll)
+ {
+ /* return with error if not clear */
+ return kMcgErrPllstClearTimeout;
+ }
+#endif
+ /* now in FBE mode */
+
+ /* MCGOUT frequency equals external clock frequency */
+ return crystalVal;
+} /* CLOCK_HAL_SetBlpeToFbeMode */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_MCG_HAL_MODES_H__)
+#define __FSL_MCG_HAL_MODES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mcg_features.h"
+#include "fsl_mcg_hal.h"
+
+//! @addtogroup mcg_hal
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+/*! @brief MCG mode definitions */
+typedef enum _mcg_modes {
+ kMcgModeFEI, /* FEI - FLL Engaged Internal */
+ kMcgModeFEE, /* FEE - FLL Engaged External */
+ kMcgModeFBI, /* FBI - FLL Bypassed Internal */
+ kMcgModeFBE, /* FBE - FLL Bypassed External */
+ kMcgModePEE, /* PEE - PLL Engaged External */
+ kMcgModePBE, /* PBE - PLL Bypassed Enternal */
+ kMcgModeBLPI, /* BLPI - Bypassed Low Power Internal */
+ kMcgModeBLPE, /* BLPE - Bypassed Low Power External */
+ kMcgModeSTOP, /* STOP - Stop */
+ kMcgModeError /* Unknown mode */
+} mcg_modes_t;
+
+/*! @brief MCG mode transition API error code definitions */
+typedef enum McgModeErrorCode {
+
+ /* MCG mode error codes */
+
+ kMcgErrNotInFeiMode = 0x01, /* - Not in FEI mode */
+ kMcgErrNotInFeeMode = 0x02, /* - Not in FEE mode */
+ kMcgErrNotInFbiMode = 0x03, /* - Not in FBI mode */
+ kMcgErrNotInFbeMode = 0x04, /* - Not in FBE mode */
+ kMcgErrNotInBlpiMode = 0x05, /* - Not in BLPI mode */
+ kMcgErrNotInBlpeMode = 0x06, /* - Not in BLPE mode */
+ kMcgErrNotInPbeMode = 0x07, /* - Not in PBE mode */
+ kMcgErrNotInPeeMode = 0x08, /* - Not in PEE mode */
+
+ /* CLock MUX switching error codes */
+
+ kMcgErrIrefstClearTimeOut = 0x11, /* - IREFST did not clear within allowed time, FLL
+ reference did not switch over from internal to
+ external clock */
+ kMcgErrIrefstSetTimeout = 0x12, /* - IREFST did not set within allowed time, the FLL
+ reference did not switch over from external to
+ internal clock(NEED TO CHECK IN MOVES TO FBI MODE) */
+ kMcgErrIrcstClearTimeout = 0x13, /* - IRCST did not clear within allowed time,
+ slow IRC is not selected */
+ kMcgErrIrefstSetTimeout1 = 0x14, /* - IREFST did not set within allowed time,
+ fast IRC is not selected */
+ kMcgErrPllstClearTimeout = 0x15, /* - PLLST did not clear, PLLST did not switch to
+ FLL output, FLL is not running */
+ kMcgErrPllstSetTimeout = 0x16, /* - PLLST did not set, PLLST did not switch to PLL
+ ouptut, PLL is not running */
+ kMcgErrPllcst = 0x17, /* - PLLCST did not switch to the correct state,
+ the correct PLL is not selected as PLLS clock source */
+ kMcgErrClkst0 = 0x18, /* - CLKST != 0, MCG did not switch to FLL output */
+ kMcgErrClkst1 = 0x19, /* - CLKST != 1, MCG did not switch to internal reference
+ clock source */
+ kMcgErrClkst2 = 0x1A, /* - CLKST != 2, MCG did not switch to external clock */
+ kMcgErrClkst3 = 0x1B, /* - CLKST != 3, MCG did not switch to PLL */
+
+ /* Oscillator error codes */
+
+ kMcgErrOscEtalRange = 0x21, /* - external frequency is bigger than max frequency */
+ kMcgErrOscXtalRange = 0x22, /* - crystal frequency outside allowed range */
+ kMcgErrOscSetTimeout = 0x23, /* - OSCINIT/OSCINIT2 did not set within allowed time */
+
+ /* IRC and FLL error codes */
+
+ kMcgErrIrcSlowRange = 0x31, /* - slow IRC is outside allowed range */
+ kMcgErrIrcFastRange = 0x32, /* - fast IRC is outside allowed range */
+ kMcgErrFllRange0Min = 0x33, /* - FLL frequency is below minimum value for range 0 */
+ kMcgErrFllRange0Max = 0x34, /* - FLL frequency is above maximum value for range 0 */
+ kMcgErrFllRange1Min = 0x35, /* - FLL frequency is below minimum value for range 1 */
+ kMcgErrFllRange1Max = 0x36, /* - FLL frequency is above maximum value for range 1 */
+ kMcgErrFllRange2Min = 0x37, /* - FLL frequency is below minimum value for range 2 */
+ kMcgErrFllRange2Max = 0x38, /* - FLL frequency is above maximum value for range 2 */
+ kMcgErrFllRange3Min = 0x39, /* - FLL frequency is below minimum value for range 3 */
+ kMcgErrFllRange3Max = 0x3A, /* - FLL frequency is above maximum value for range 3 */
+ kMcgErrFllDrstDrsRange = 0x3B, /* - DRS is out of range */
+
+ kMcgErrFllFreqency = 0x3C,
+
+ /* PLL error codes */
+
+ kMcgErrPllPrdidRange = 0x41, /* - PRDIV outside allowed range */
+ kMcgErrPllVdivRange = 0x42, /* - VDIV outside allowed range */
+ kMcgErrPllRefClkRange = 0x43, /* - PLL reference clock frequency, out of allowed range */
+ kMcgErrPllLockBit = 0x44, /* - LOCK or LOCK2 bit did not set */
+ kMcgErrPllOutClkRange = 0x45, /* - PLL output frequency is outside allowed range (NEED
+ TO ADD THIS CHECK TO fbe_pbe and blpe_pbe) only in
+ fei-pee at this time */
+ kMcgErrMax = 0x1000
+} mcg_mode_error_code_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+/*!
+ * @brief Gets the current MCG mode.
+ *
+ * This is an internal function that checks the MCG registers and determine
+ * the current MCG mode
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @return mcgMode Current MCG mode or error code mcg_modes_t
+ */
+mcg_modes_t CLOCK_HAL_GetMcgMode(uint32_t baseAddr);
+
+/*!
+ * @brief Checks the FLL frequency integrity.
+ *
+ * This function calculates and checks the FLL frequency value based on input value.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param fllRef - FLL reference clock in Hz.
+ *
+ * @return value FLL output frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_GetFllFrequency(uint32_t baseAddr, int32_t fllRef);
+
+/*!
+ * @brief Mode transition FEI to FEE mode
+ *
+ * This function transitions the MCG from FEI mode to FEE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * @param crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * @param hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * @param erefsVal - selects external clock (=0) or crystal OSC (=1)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal,
+ uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal,
+ mcg_external_ref_clock_select_t erefsVal);
+
+/*!
+ * @brief Mode transition FEI to FBI mode
+ *
+ * This function transitions the MCG from FEI mode to FBI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value
+ * @param ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeiToFbiMode(uint32_t baseAddr, uint32_t ircFreq,
+ mcg_internal_ref_clock_select_t ircSelect);
+
+/*!
+ * @brief Mode transition FEI to FBE mode
+ *
+ * This function transitions the MCG from FEI mode to FBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * @param crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * @param hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * @param erefsVal - selects external clock (=0) or crystal OSC (=1)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal,
+ uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal,
+ mcg_external_ref_clock_select_t erefsVal);
+
+/*!
+ * @brief Mode transition FEE to FEI mode
+ *
+ * This function transitions the MCG from FEE mode to FEI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value (slow)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeeToFeiMode(uint32_t baseAddr, uint32_t ircFreq);
+
+/*!
+ * @brief Mode transition FEE to FBI mode
+ *
+ * This function transitions the MCG from FEE mode to FBI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value
+ * @param ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeeToFbiMode(uint32_t baseAddr, uint32_t ircFreq,
+ mcg_internal_ref_clock_select_t ircSelect);
+
+/*!
+ * @brief Mode transition FEE to FBE mode
+ *
+ * This function transitions the MCG from FEE mode to FBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external reference clock frequency value
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFeeToFbeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition FBI to FEI mode
+ *
+ * This function transitions the MCG from FBI mode to FEI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value (slow)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbiToFeiMode(uint32_t baseAddr, uint32_t ircFreq);
+
+/*!
+ * @brief Mode transition FBI to FEE mode
+ *
+ * This function transitions the MCG from FBI mode to FEE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * @param crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * @param hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * @param erefsVal - selects external clock (=0) or crystal OSC (=1)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal,
+ uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal,
+ mcg_external_ref_clock_select_t erefsVal);
+
+/*!
+ * @brief Mode transition FBI to FBE mode
+ *
+ * This function transitions the MCG from FBI mode to FBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param oscselVal - oscillator selection value
+ * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M
+ * @param crystalVal - external clock frequency in Hz
+ * oscselVal - 0
+ * erefsVal - 0: osc0 external clock frequency
+ * erefsVal - 1: osc0 crystal clock frequency
+ * oscselVal - 1: RTC 32Khz clock source frequency
+ * oscselVal - 2: IRC 48Mhz clock source frequency
+ * @param hgoVal - selects whether low power or high gain mode is selected
+ * for the crystal oscillator. This value is only valid when
+ * oscselVal is 0 and erefsVal is 1.
+ * @param erefsVal - selects external clock (=0) or crystal OSC (=1)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal,
+ uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal,
+ mcg_external_ref_clock_select_t erefsVal);
+
+/*!
+ * @brief Mode transition FBI to BLPI mode
+ *
+ * This function transitions the MCG from FBI mode to BLPI mode.This is
+ * achieved by setting the MCG_C2[LP] bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value
+ * @param ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbiToBlpiMode(uint32_t baseAddr, uint32_t ircFreq,
+ mcg_internal_ref_clock_select_t ircSelect);
+
+/*!
+ * @brief Mode transition BLPI to FBI mode
+ *
+ * This function transitions the MCG from BLPI mode to FBI mode.This is
+ * achieved by clearing the MCG_C2[LP] bit.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value
+ * @param ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetBlpiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, uint8_t ircSelect);
+
+/*!
+ * @brief Mode transition FBE to FEE mode
+ *
+ * This function transitions the MCG from FBE mode to FEE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external reference clock frequency value
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbeToFeeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition FBE to FEI mode
+ *
+ * This function transitions the MCG from FBE mode to FEI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value (slow)
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToFeiMode(uint32_t baseAddr, uint32_t ircFreq);
+
+/*!
+ * @brief Mode transition FBE to FBI mode
+ *
+ * This function transitions the MCG from FBE mode to FBI mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param ircFreq - internal reference clock frequency value
+ * @param ircSelect - slow or fast clock selection
+ * 0: slow, 1: fast
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+uint32_t CLOCK_HAL_SetFbeToFbiMode(uint32_t baseAddr, uint32_t ircFreq,
+ mcg_internal_ref_clock_select_t ircSelect);
+
+/*!
+ * @brief Mode transition FBE to PBE mode
+ *
+ * This function transitions the MCG from FBE mode to PBE mode.
+ * The function requires the desired OSC and PLL be passed in to it for compatibility
+ * with the future support of OSC/PLL selection
+ * (This function presently only supports OSC0 as PLL source)
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ * @param pllcsSelect - 0 to select PLL0, non-zero to select PLL1.
+ * @param prdivVal - value to divide the external clock source by to create
+ * the desired PLL reference clock frequency
+ * @param vdivVal - value to multiply the PLL reference clock frequency by
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbeToPbeMode(uint32_t baseAddr, uint32_t crystalVal,
+ mcg_pll_clk_select_t pllcsSelect,
+ uint8_t prdivVal, uint8_t vdivVal);
+
+/*!
+ * @brief Mode transition FBE to BLPE mode
+ *
+ * This function transitions the MCG from FBE mode to BLPE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetFbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition PBE to FBE mode
+ *
+ * This function transitions the MCG from PBE mode to FBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetPbeToFbeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition PBE to PEE mode
+ *
+ * This function transitions the MCG from PBE mode to PEE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ * @param pllcsSelect - PLLCS select setting
+ * mcg_pll_clk_select_t is defined in fsl_mcg_hal.h
+ * 0: kMcgPllcsSelectPll0 PLL0 output clock is selected
+ * 1: kMcgPllcsSelectPll1 PLL1 output clock is selected
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetPbeToPeeMode(uint32_t baseAddr, uint32_t crystalVal,
+ mcg_pll_clk_select_t pllcsSelect);
+
+/*!
+ * @brief Mode transition PBE to BLPE mode
+ *
+ * This function transitions the MCG from PBE mode to BLPE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetPbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition PEE to PBE mode
+ *
+ * This function transitions the MCG from PEE mode to PBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetPeeToPbeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+/*!
+ * @brief Mode transition BLPE to PBE mode
+ *
+ * This function transitions the MCG from BLPE mode to PBE mode.
+ * The function requires the desired OSC and PLL be passed in to it for compatibility
+ * with the future support of OSC/PLL selection
+ * (This function presently only supports OSC0 as PLL source)
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external clock frequency in Hz
+ * @param pllcsSelect - 0 to select PLL0, non-zero to select PLL1.
+ * @param prdivVal - value to divide the external clock source by to create
+ * the desired PLL reference clock frequency
+ * @param vdivVal - value to multiply the PLL reference clock frequency by
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetBlpeToPbeMode(uint32_t baseAddr, uint32_t crystalVal,
+ mcg_pll_clk_select_t pllcsSelect,
+ uint8_t prdivVal, uint8_t vdivVal);
+
+/*!
+ * @brief Mode transition BLPE to FBE mode
+ *
+ * This function transitions the MCG from BLPE mode to FBE mode.
+ *
+ * @param baseAddr Base address for current MCG instance.
+ * @param crystalVal - external reference clock frequency value
+ *
+ * @return value MCGCLKOUT frequency (Hz) or error code
+ */
+uint32_t CLOCK_HAL_SetBlpeToFbeMode(uint32_t baseAddr, uint32_t crystalVal);
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+//! @}
+
+#endif // __FSL_MCG_HAL_MODES_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,146 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_MPU_FEATURES_H__) +#define __FSL_MPU_FEATURES_H__ + +#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) + /* @brief Specifies number of descriptors available. */ + #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) + /* @brief Has process identifier support. */ + #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) + /* @brief Has master 0. */ + #define FSL_FEATURE_MPU_HAS_MASTER0 (1) + /* @brief Has master 1. */ + #define FSL_FEATURE_MPU_HAS_MASTER1 (1) + /* @brief Has master 2. */ + #define FSL_FEATURE_MPU_HAS_MASTER2 (1) + /* @brief Has master 3. */ + #define FSL_FEATURE_MPU_HAS_MASTER3 (0) + /* @brief Has master 4. */ + #define FSL_FEATURE_MPU_HAS_MASTER4 (1) + /* @brief Has master 5. */ + #define FSL_FEATURE_MPU_HAS_MASTER5 (1) + /* @brief Has master 6. */ + #define FSL_FEATURE_MPU_HAS_MASTER6 (0) + /* @brief Has master 7. */ + #define FSL_FEATURE_MPU_HAS_MASTER7 (0) +#elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Specifies number of descriptors available. */ + #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) + /* @brief Has process identifier support. */ + #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) + /* @brief Has master 0. */ + #define FSL_FEATURE_MPU_HAS_MASTER0 (1) + /* @brief Has master 1. */ + #define FSL_FEATURE_MPU_HAS_MASTER1 (1) + /* @brief Has master 2. */ + #define FSL_FEATURE_MPU_HAS_MASTER2 (1) + /* @brief Has master 3. */ + #define FSL_FEATURE_MPU_HAS_MASTER3 (1) + /* @brief Has master 4. */ + #define FSL_FEATURE_MPU_HAS_MASTER4 (1) + /* @brief Has master 5. */ + #define FSL_FEATURE_MPU_HAS_MASTER5 (1) + /* @brief Has master 6. */ + #define FSL_FEATURE_MPU_HAS_MASTER6 (0) + /* @brief Has master 7. */ + #define FSL_FEATURE_MPU_HAS_MASTER7 (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Specifies number of descriptors available. */ + #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) + /* @brief Has process identifier support. */ + #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) + /* @brief Has master 0. */ + #define FSL_FEATURE_MPU_HAS_MASTER0 (1) + /* @brief Has master 1. */ + #define FSL_FEATURE_MPU_HAS_MASTER1 (1) + /* @brief Has master 2. */ + #define FSL_FEATURE_MPU_HAS_MASTER2 (1) + /* @brief Has master 3. */ + #define FSL_FEATURE_MPU_HAS_MASTER3 (1) + /* @brief Has master 4. */ + #define FSL_FEATURE_MPU_HAS_MASTER4 (1) + /* @brief Has master 5. */ + #define FSL_FEATURE_MPU_HAS_MASTER5 (1) + /* @brief Has master 6. */ + #define FSL_FEATURE_MPU_HAS_MASTER6 (1) + /* @brief Has master 7. */ + #define FSL_FEATURE_MPU_HAS_MASTER7 (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Specifies number of descriptors available. */ + #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (16) + /* @brief Has process identifier support. */ + #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) + /* @brief Has master 0. */ + #define FSL_FEATURE_MPU_HAS_MASTER0 (1) + /* @brief Has master 1. */ + #define FSL_FEATURE_MPU_HAS_MASTER1 (1) + /* @brief Has master 2. */ + #define FSL_FEATURE_MPU_HAS_MASTER2 (1) + /* @brief Has master 3. */ + #define FSL_FEATURE_MPU_HAS_MASTER3 (1) + /* @brief Has master 4. */ + #define FSL_FEATURE_MPU_HAS_MASTER4 (1) + /* @brief Has master 5. */ + #define FSL_FEATURE_MPU_HAS_MASTER5 (1) + /* @brief Has master 6. */ + #define FSL_FEATURE_MPU_HAS_MASTER6 (0) + /* @brief Has master 7. */ + #define FSL_FEATURE_MPU_HAS_MASTER7 (0) +#else + #define MBED_NO_MPU +#endif + +#endif /* __FSL_MPU_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mpu_hal.h"
+
+#ifndef MBED_NO_MPU
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_Init
+ * Description : Initialize MPU module and all regoins will be invalid after cleared access permission.
+ *
+ *END**************************************************************************/
+void MPU_HAL_Init(uint32_t baseAddr)
+{
+ uint32_t i;
+
+ MPU_HAL_Disable(baseAddr);
+
+ for(i = 1; i < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; i++)
+ {
+ MPU_HAL_SetRegionStartAddr(baseAddr, (mpu_region_num)i, (uint32_t)0);
+
+ MPU_HAL_SetRegionEndAddr(baseAddr, (mpu_region_num)i, (uint32_t)0);
+ }
+}
+
+#endif /* MBED_NO_MPU */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1545 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_MPU_HAL_H__
+#define __FSL_MPU_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_mpu_features.h"
+#include "fsl_device_registers.h"
+
+#ifndef MBED_NO_MPU
+
+#define MPU_REGION_NUMBER 12
+
+/*!
+ * @addtogroup mpu_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief MPU region number region0~region11. */
+typedef enum _mpu_region_num{
+ kMPURegionNum00 = 0U, /*!< MPU region number 0*/
+ kMPURegionNum01 = 1U, /*!< MPU region number 1*/
+ kMPURegionNum02 = 2U, /*!< MPU region number 2*/
+ kMPURegionNum03 = 3U, /*!< MPU region number 3*/
+ kMPURegionNum04 = 4U, /*!< MPU region number 4*/
+ kMPURegionNum05 = 5U, /*!< MPU region number 5*/
+ kMPURegionNum06 = 6U, /*!< MPU region number 6*/
+ kMPURegionNum07 = 7U, /*!< MPU region number 7*/
+ kMPURegionNum08 = 8U, /*!< MPU region number 8*/
+ kMPURegionNum09 = 9U, /*!< MPU region number 9*/
+ kMPURegionNum10 = 10U, /*!< MPU region number 10*/
+ kMPURegionNum11 = 11U, /*!< MPU region number 11*/
+#if defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
+ defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
+ kMPURegionNum11 = 12U, /*!< MPU region number 12*/
+ kMPURegionNum11 = 13U, /*!< MPU region number 13*/
+ kMPURegionNum11 = 14U, /*!< MPU region number 14*/
+ kMPURegionNum11 = 15U, /*!< MPU region number 15*/
+#endif
+}mpu_region_num;
+
+/*! @brief MPU error address register0~4. */
+typedef enum _mpu_error_addr_reg{
+ kMPUErrorAddrReg00 = 0U, /*!< MPU error address register 0*/
+ kMPUErrorAddrReg01 = 1U, /*!< MPU error address register 1*/
+ kMPUErrorAddrReg02 = 2U, /*!< MPU error address register 2*/
+ kMPUErrorAddrReg03 = 3U, /*!< MPU error address register 3*/
+ kMPUErrorAddrReg04 = 4U /*!< MPU error address register 4*/
+}mpu_error_addr_reg;
+
+/*! @brief MPU error detail register0~4. */
+typedef enum _mpu_error_detail_reg{
+ kMPUErrorDetailReg00 = 0U, /*!< MPU error detail register 0*/
+ kMPUErrorDetailReg01 = 1U, /*!< MPU error detail register 1*/
+ kMPUErrorDetailReg02 = 2U, /*!< MPU error detail register 2*/
+ kMPUErrorDetailReg03 = 3U, /*!< MPU error detail register 3*/
+ kMPUErrorDetailReg04 = 4U /*!< MPU error detail register 4*/
+}mpu_error_detail_reg;
+
+/*! @brief MPU access error. */
+typedef enum _mpu_error_access_type{
+ kMPUReadErrorType = 0U, /*!< MPU error type---read*/
+ kMPUWriteErrorType = 1U /*!< MPU error type---write*/
+}mpu_error_access_type;
+
+/*! @brief MPU access error attributes.*/
+typedef enum _mpu_error_attributes{
+ kMPUUserModeInstructionAccess = 0U, /*!< access instruction error in user mode*/
+ kMPUUserModeDataAccess = 1U, /*!< access data error in user mode*/
+ kMPUSupervisorModeInstructionAccess = 2U, /*!< access instruction error in supervisor mode*/
+ kMPUSupervisorModeDataAccess = 3U /*!< access data error in supervisor mode*/
+}mpu_error_attributes;
+
+/*! @brief access MPU in which mode. */
+typedef enum _mpu_access_mode{
+ kMPUAccessInUserMode = 0U, /*!< access data or instruction in user mode*/
+ kMPUAccessInSupervisorMode = 1U /*!< access data or instruction in supervisor mode*/
+}mpu_access_mode;
+
+/*! @brief MPU master number. */
+typedef enum _mpu_master_num{
+ kMPUMaster00 = 0U, /*!< Core.*/
+ kMPUMaster01 = 1U, /*!< Debugger.*/
+ kMPUMaster02 = 2U, /*!< DMA.*/
+ kMPUMaster03 = 3U, /*!< ENET.*/
+ kMPUMaster04 = 4U, /*!< USB.*/
+ kMPUMaster05 = 5U, /*!< SDHC.*/
+ kMPUMaster06 = 6U, /*!< undefined.*/
+ kMPUMaster07 = 7U /*!< undefined.*/
+}mpu_master_num;
+
+/*! @brief MPU error access control detail. */
+typedef enum _mpu_error_access_control{
+ kMPUNoRegionHitError = 0U, /*!< no region hit error*/
+ kMPUNoneOverlappRegionError = 1U, /*!< access single region error*/
+ kMPUOverlappRegionError = 2U /*!< access overlapping region error*/
+}mpu_error_access_control;
+
+/*! @brief MPU access rights in supervisor mode for master0~master3. */
+typedef enum _mpu_supervisor_access_rights{
+ kMPUSupervisorReadWriteExecute = 0U, /*!< R W E allowed in supervisor mode*/
+ kMPUSupervisorReadExecute = 1U, /*!< R E allowed in supervisor mode*/
+ kMPUSupervisorReadWrite = 2U, /*!< R W allowed in supervisor mode*/
+ kMPUSupervisorEqualToUsermode = 3U /*!< access permission equal to user mode*/
+}mpu_supervisor_access_rights;
+
+/*! @brief MPU access rights in user mode for master0~master3. */
+typedef enum _mpu_user_access_rights{
+ kMPUUserNoAccessRights = 0U, /*!< no access allowed in user mode*/
+ kMPUUserExecute = 1U, /*!< E allowed in user mode*/
+ kMPUUserWrite = 2U, /*!< W allowed in user mode*/
+ kMPUUserWriteExecute = 3U, /*!< W E allowed in user mode*/
+ kMPUUserRead = 4U, /*!< R allowed in user mode*/
+ kMPUUserReadExecute = 5U, /*!< R E allowed in user mode*/
+ kMPUUserReadWrite = 6U, /*!< R W allowed in user mode*/
+ kMPUUserReadWriteExecute = 7U /*!< R W E allowed in user mode*/
+}mpu_user_access_rights;
+
+/*! @brief MPU process identifier. */
+typedef enum _mpu_process_identifier_value{
+ kMPUIdentifierDisable = 0U, /*!< processor identifier disable*/
+ kMPUIdentifierEnable = 1U /*!< processor identifier enable*/
+}mpu_process_identifier_value;
+
+/*! @brief MPU access control for master4~master7. */
+typedef enum _mpu_access_control{
+ kMPUAccessDisable = 0U, /*!< Read or Write not allowed*/
+ kMPUAccessEnable = 1U /*!< Read or Write allowed*/
+}mpu_access_control;
+
+/*! @brief MPU access type for master4~master7. */
+typedef enum _mpu_access_type{
+ kMPUAccessRead = 0U, /*!< Access type is read*/
+ kMPUAccessWrite = 1U /*!< Access type is write*/
+}mpu_access_type;
+
+/*! @brief MPU access region valid. */
+typedef enum _mpu_region_valid{
+ kMPURegionInvalid = 0U, /*!< region invalid*/
+ kMPURegionValid = 1U /*!< region valid*/
+}mpu_region_valid;
+
+/*! @brief MPU status return codes.*/
+typedef enum _MPU_status {
+ kStatus_MPU_Success = 0x0U, /*!< Succeed. */
+ kStatus_MPU_NotInitlialized = 0x1U, /*!< MPU is not initialized yet. */
+ kStatus_MPU_NullArgument = 0x2U, /*!< Argument is NULL.*/
+ } mpu_status_t;
+
+/*******************************************************************************
+ ** Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name MPU HAL.
+ * @{
+ */
+
+/*!
+ * @brief Enables the MPU module operation
+ *
+ * @param baseAddr The MPU peripheral base address
+ */
+static inline void MPU_HAL_Enable(uint32_t baseAddr)
+{
+ BW_MPU_CESR_VLD(baseAddr, (uint8_t)true);
+}
+
+/*!
+ * @brief Disables the MPU module operation
+ *
+ * @param baseAddr The MPU peripheral base address
+ */
+static inline void MPU_HAL_Disable(uint32_t baseAddr)
+{
+ BW_MPU_CESR_VLD(baseAddr, (uint8_t)false);
+}
+
+/*!
+ * @brief Checks whether the MPU module is enabled
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @retval true MPU module is enabled
+ * @retval false MPU module is disabled
+ */
+static inline bool MPU_HAL_IsEnabled(uint32_t baseAddr)
+{
+ return BR_MPU_CESR_VLD(baseAddr);
+}
+
+/*!
+ * @brief Returns the total region number
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @retval the number of regions
+ */
+static inline uint32_t MPU_HAL_GetNumberOfRegions(uint32_t baseAddr)
+{
+ return (BR_MPU_CESR_NRGD(baseAddr));
+}
+
+/*!
+ * @brief Returns MPU slave sports
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @retval the number of slaves
+ */
+static inline uint32_t MPU_HAL_GetNumberOfSlaves(uint32_t baseAddr)
+{
+ return (BR_MPU_CESR_NSP(baseAddr));
+}
+
+/*!
+ * @brief Returns hardware level info
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @retval hardware revision level
+ */
+static inline uint32_t MPU_HAL_GetHardwareRevisionLevel(uint32_t baseAddr)
+{
+ return (BR_MPU_CESR_HRL(baseAddr));
+}
+
+/*!
+ * @brief Returns hardware level info
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regNum Error address register number
+ * @retval error access address
+ */
+static inline uint32_t MPU_HAL_GetErrorAccessAddr(uint32_t baseAddr, mpu_error_addr_reg regNum)
+{
+ assert(regNum < HW_MPU_EARn_COUNT);
+ return (BR_MPU_EARn_EADDR(baseAddr, regNum));
+}
+
+/*!
+ * @brief Returns error access slaves sports
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @retval error slave sports
+*/
+static inline uint8_t MPU_HAL_GetErrorSlaveSports(uint32_t baseAddr)
+{
+ return (BR_MPU_CESR_SPERR(baseAddr));
+}
+
+/*!
+ * @brief Returns error access address
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param errorDetailRegNum Error detail register number
+ * @retval error access type
+*/
+static inline mpu_error_access_type MPU_HAL_GetErrorAccessType(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
+{
+ assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
+ return (mpu_error_access_type)(BR_MPU_EDRn_ERW(baseAddr, errorDetailRegNum));
+}
+
+/*!
+ * @brief Returns error access attributes
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param errorDetailRegNum Detail error register number
+ * @retval error access attributes
+ */
+static inline mpu_error_attributes MPU_HAL_GetErrorAttributes(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
+{
+ assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
+ return (mpu_error_attributes)(BR_MPU_EDRn_EATTR(baseAddr, errorDetailRegNum));
+}
+
+/*!
+ * @brief Returns error access master number
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param errorDetailRegNum Error register number
+ * @retval error master number
+ */
+static inline mpu_master_num MPU_HAL_GetErrorMasterNum(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
+{
+ assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
+ return (mpu_master_num)(BR_MPU_EDRn_EMN(baseAddr, errorDetailRegNum));
+}
+
+/*!
+ * @brief Returns error process identifier
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param errorDetailRegNum Error register number
+ * @retval error process identifier
+ */
+static inline uint32_t MPU_HAL_GetErrorProcessIdentifier(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
+{
+ assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
+ return(BR_MPU_EDRn_EPID(baseAddr, errorDetailRegNum));
+}
+
+/*!
+ * @brief Returns error access control
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param errorDetailRegNum Error register number
+ * @retval error access control
+ */
+static inline mpu_error_access_control MPU_HAL_GetErrorAccessControl(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
+{
+ assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
+
+ uint32_t i = BR_MPU_EDRn_EACD(baseAddr, errorDetailRegNum);
+
+ if(0 == i)
+ {
+ return (kMPUNoRegionHitError);
+ }
+ else if(!(i&(i-1)))
+ {
+ return (kMPUNoneOverlappRegionError);
+ }
+ else
+ {
+ return (kMPUOverlappRegionError);
+ }
+}
+
+/*!
+ * @brief Returns the region start address
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval region start address
+ */
+static inline uint32_t MPU_HAL_GetRegionStartAddr(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD0_COUNT);
+ return (BR_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum)<<BP_MPU_RGDn_WORD0_SRTADDR);
+}
+
+/*!
+ * @brief Sets region start address
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param startAddr Region start address
+ */
+static inline void MPU_HAL_SetRegionStartAddr(uint32_t baseAddr, mpu_region_num regionNum, uint32_t startAddr)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD0_COUNT);
+ startAddr >>= BP_MPU_RGDn_WORD0_SRTADDR;
+ BW_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum, startAddr);
+}
+
+/*!
+ * @brief Returns region end address
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval region end address
+ */
+static inline uint32_t MPU_HAL_GetRegionEndAddr(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD1_COUNT);
+ return (BR_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum)<<BP_MPU_RGDn_WORD0_SRTADDR);
+}
+
+/*!
+ * @brief Sets region end address
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param endAddr Region end address
+ */
+static inline void MPU_HAL_SetRegionEndAddr(uint32_t baseAddr, mpu_region_num regionNum, uint32_t endAddr)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD1_COUNT);
+ endAddr >>= BP_MPU_RGDn_WORD0_SRTADDR;
+ BW_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum, endAddr);
+}
+
+/*!
+ * @brief Returns all masters access permission for a specific region
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval all masters access permission
+ */
+static inline uint32_t MPU_HAL_GetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (HW_MPU_RGDn_WORD2_RD(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets all masters access permission for a specific region
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights All masters access rights
+ */
+static inline void MPU_HAL_SetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ HW_MPU_RGDn_WORD2_WR(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Gets M0 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master0 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M0 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master0 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M0 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master0 access permission
+ */
+static inline void MPU_HAL_SetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M0 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master0 access permission
+ */
+static inline void MPU_HAL_SetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M0 process identifier is enabled in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m0 process identifier is enabled
+ * @retval false m0 process identifier is disabled
+ */
+
+static inline bool MPU_HAL_IsM0ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue Process identifier value
+ */
+static inline void MPU_HAL_SetM0ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M1 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master1 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M1 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master1 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M1 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master1 access permission
+ */
+static inline void MPU_HAL_SetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M1 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master1 access permission
+ */
+static inline void MPU_HAL_SetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether M1 process identifier enabled in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m1 process identifier is enabled
+ * @retval false m1 process identifier is disabled
+ */
+static inline bool MPU_HAL_IsM1ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue Process identifier value
+ */
+static inline void MPU_HAL_SetM1ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M2 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master2 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M2 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master2 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M2 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master2 access permission
+ */
+static inline void MPU_HAL_SetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M2 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master2 access permission
+ */
+static inline void MPU_HAL_SetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M2 process identifier enabled in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m2 process identifier is enabled
+ * @retval false m2 process identifier is disabled
+ */
+
+static inline bool MPU_HAL_IsM2ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param identifierValue Process identifier value.
+ */
+static inline void MPU_HAL_SetM2ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M3 access permission in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master3 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M3 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master3 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M3 access permission in supervisor mode.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessRights Master3 access permission.
+ */
+static inline void MPU_HAL_SetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M3 access permission in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master3 access permission
+ */
+static inline void MPU_HAL_SetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M3 process identifier enabled in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m3 process identifier is enabled
+ * @retval false m3 process identifier is disabled
+ */
+
+static inline bool MPU_HAL_IsM3ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue Process identifier value
+ */
+static inline void MPU_HAL_SetM3ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets the M4 access permission.
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @retval read or write permission
+ */
+static inline mpu_access_control MPU_HAL_GetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets the M4 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @param accessControl Access permission
+ */
+static inline void MPU_HAL_SetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets the M5 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @retval read or write permission
+ */
+static inline mpu_access_control MPU_HAL_GetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets the M5 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @param accessControl Access permission
+ */
+static inline void MPU_HAL_SetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets the M6 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType access type Read/Write
+ * @retval read or write permission
+ */
+static inline mpu_access_control MPU_HAL_GetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets the M6 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @param accessControl Access permission
+ */
+static inline void MPU_HAL_SetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets the M7 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @retval read or write permission
+ */
+static inline mpu_access_control MPU_HAL_GetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets the M7 access permission
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessType Access type Read/Write
+ * @param accessControl Access permission
+ */
+static inline void MPU_HAL_SetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Checks whether region is valid
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true region is valid
+ * @retval false region is invalid
+ */
+static inline bool MPU_HAL_IsRegionValid(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ return (1 == BR_MPU_RGDn_WORD3_VLD(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the region valid value
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param validValue Region valid value
+ */
+static inline void MPU_HAL_SetRegionValidValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_region_valid validValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ BW_MPU_RGDn_WORD3_VLD(baseAddr, regionNum, validValue);
+}
+
+/*!
+ * @brief Gets the process identifier mask
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval region process identifier mask
+ */
+static inline uint8_t MPU_HAL_GetProcessIdentifierMask(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ return (BR_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the process identifier mask
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param processIdentifierMask Process identifier mask value
+ */
+static inline void MPU_HAL_SetPIDMASK(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifierMask)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ BW_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum, processIdentifierMask);
+}
+
+/*!
+ * @brief Gets the process identifier
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval process identifier
+ */
+static inline uint8_t MPU_HAL_GetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ return (BR_MPU_RGDn_WORD3_PID(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the process identifier
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param processIdentifier Process identifier
+ */
+static inline void MPU_HAL_SetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifier)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
+ BW_MPU_RGDn_WORD3_PID(baseAddr, regionNum, processIdentifier);
+}
+
+/*!
+ * @brief Gets all masters access permission from alternative register
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval all masters access permission
+ */
+static inline uint32_t MPU_HAL_GetAllMastersAlternateAcessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (HW_MPU_RGDAACn_RD(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets all masters access permission through alternative register
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights All masters access permission
+ */
+static inline void MPU_HAL_SetAllMastersAlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ HW_MPU_RGDAACn_WR(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Gets the M0 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master0 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M0SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets the M0 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master0 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDAACn_M0UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets the M0 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master0 access permission
+ */
+static inline void MPU_HAL_SetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M0SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets the M0 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master0 access permission
+ */
+static inline void MPU_HAL_SetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M0UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M0 process identifier works in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m0 process identifier is enabled
+ * @retval false m0 process identifier is disabled
+ */
+static inline bool MPU_HAL_IsM0AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDAACn_M0PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue Process identifier value
+ */
+static inline void MPU_HAL_SetM0AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDAACn_M0PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M1 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master1 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M1SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M1 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval Master1 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDAACn_M1UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M1 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master1 access permission
+ */
+static inline void MPU_HAL_SetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M1SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M1 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master1 access permission
+ */
+static inline void MPU_HAL_SetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M1UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M1 process identifier works in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m1 process identifier is enabled
+ * @retval false m1 process identifier is disabled
+ */
+static inline bool MPU_HAL_IsM1AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDAACn_M1PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief @brief Sets M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue process identifier value
+ */
+static inline void MPU_HAL_SetM1AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDAACn_M1PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M2 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval M2 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M2SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets the M2 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval M2 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDAACn_M2UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M2 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights M2 access permission
+ */
+static inline void MPU_HAL_SetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M2SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M2 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights M2 access permission
+ */
+static inline void MPU_HAL_SetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M2UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M2 process identifier works in region hit evaluation
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval true m2 process identifier is enabled
+ * @retval false m2 process identifier is disabled
+ */
+static inline bool MPU_HAL_IsM2AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDAACn_M2PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param identifierValue process identifier value
+ */
+static inline void MPU_HAL_SetM2AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDAACn_M2PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M3 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval M3 access permission
+ */
+static inline mpu_supervisor_access_rights MPU_HAL_GetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M3SM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Gets M3 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @retval M3 access permission
+ */
+static inline mpu_user_access_rights MPU_HAL_GetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ return (mpu_user_access_rights)(BR_MPU_RGDAACn_M3UM(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M3 access rights in supervisor mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master3 access permission
+ */
+static inline void MPU_HAL_SetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M3SM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Sets M3 access rights in user mode
+ *
+ * @param baseAddr The MPU peripheral base address
+ * @param regionNum MPU region number
+ * @param accessRights Master3 access permission
+ */
+static inline void MPU_HAL_SetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ BW_MPU_RGDAACn_M3UM(baseAddr, regionNum, accessRights);
+}
+
+/*!
+ * @brief Checks whether the M3 process identifier works in region hit evaluation.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @retval true m3 process identifier is enabled.
+ * @retval false m3 process identifier is disabled.
+ */
+static inline bool MPU_HAL_IsM3AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ return (1 == BR_MPU_RGDAACn_M3PE(baseAddr, regionNum));
+}
+
+/*!
+ * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param identifierValue process identifier value.
+ */
+static inline void MPU_HAL_SetM3AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
+{
+ assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
+ BW_MPU_RGDAACn_M3PE(baseAddr, regionNum, identifierValue);
+}
+
+/*!
+ * @brief Gets M4 access permission from alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @retval read or write permission.
+ */
+static inline mpu_access_control MPU_HAL_GetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M4RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M4WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets M4 access permission through alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @param accessControl Access permission.
+ */
+static inline void MPU_HAL_SetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDAACn_M4RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDAACn_M4WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets M5 access permission from alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @retval read or write permission.
+ */
+static inline mpu_access_control MPU_HAL_GetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M5RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M5WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets M5 access permission through alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @param accessControl Master5 Access permission.
+ */
+static inline void MPU_HAL_SetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDAACn_M5RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDAACn_M5WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets M6 access permission from alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @retval read or write permission.
+ */
+static inline mpu_access_control MPU_HAL_GetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M6RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M6WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets M6 access permission through alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @param accessControl Master6 access permission.
+ */
+static inline void MPU_HAL_SetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDAACn_M6RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDAACn_M6WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Gets M7 access permission from alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @retval read or write permission.
+ */
+static inline mpu_access_control MPU_HAL_GetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M7RE(baseAddr, regionNum));
+ }
+ else
+ {
+ return (mpu_access_control)(BR_MPU_RGDAACn_M7WE(baseAddr, regionNum));
+ }
+}
+
+/*!
+ * @brief Sets M7 access permission through alternate register.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param accessType Access type Read/Write.
+ * @param accessControl Master7 access permission.
+ */
+static inline void MPU_HAL_SetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
+{
+ assert(regionNum < HW_MPU_RGDAACn_COUNT);
+ if(kMPUAccessRead == accessType)
+ {
+ BW_MPU_RGDAACn_M7RE(baseAddr, regionNum, accessControl);
+ }
+ else
+ {
+ BW_MPU_RGDAACn_M7WE(baseAddr, regionNum, accessControl);
+ }
+}
+
+/*!
+ * @brief Initializes the MPU module.
+ *
+ * @param baseAddr The MPU peripheral base address.
+ */
+void MPU_HAL_Init(uint32_t baseAddr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* MBED_NO_MPU */
+
+#endif /* __FSL_MPU_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/osc/fsl_osc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,166 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_OSC_FEATURES_H__) +#define __FSL_OSC_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (0) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (0) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (1) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (1) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \ + defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ + defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \ + defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ + defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || \ + defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || \ + defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ + defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || \ + defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || \ + defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ + defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \ + defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \ + defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \ + defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ + defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ + defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ + defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ + defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (0) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (1) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (0) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (1) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ + defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (0) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (0) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (1) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (1) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (1) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (1) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (0) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (2) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (0) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (0) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (0) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (0) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has OSC1 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC1 (0) + /* @brief Has OSC0 external oscillator. */ + #define FSL_FEATURE_OSC_HAS_OSC0 (0) + /* @brief Has OSC external oscillator (without index). */ + #define FSL_FEATURE_OSC_HAS_OSC (0) + /* @brief Number of OSC external oscillators. */ + #define FSL_FEATURE_OSC_OSC_COUNT (0) + /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ + #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_OSC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_osc_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_SetExternalRefClkCmd
+ * Description : Enable/disable the external reference clock
+ * This function will enable/disable the external reference clock output
+ * for oscillator - that is the OSCERCLK. This clock will be used by many
+ * peripherals. It should be enabled at early system init stage to ensure the
+ * peripherals could select it and use it.
+ *
+ *END**************************************************************************/
+void OSC_HAL_SetExternalRefClkCmd(uint32_t baseAddr, bool enable)
+{
+ BW_OSC_CR_ERCLKEN(baseAddr, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_GetExternalRefClkCmd
+ * Description : Get the external reference clock enable setting for osc
+ * This function will get the external reference clock output enable setting
+ * for oscillator - that is the OSCERCLK. This clock will be used by many
+ * peripherals. It should be enabled at early system init stage to ensure the
+ * peripherals could select it and use it.
+ *
+ *END**************************************************************************/
+bool OSC_HAL_GetExternalRefClkCmd(uint32_t baseAddr)
+{
+ return (bool)BR_OSC_CR_ERCLKEN(baseAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_SetExternalRefClkInStopModeCmd
+ * Description : Enable/disable the external ref clock in stop mode
+ * This function will enable/disable the external reference clock (OSCERCLK)
+ * when MCU enters Stop mode.
+ *
+ *END**************************************************************************/
+void OSC_HAL_SetExternalRefClkInStopModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_OSC_CR_EREFSTEN(baseAddr, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_GetExternalRefClkInStopModeCmd
+ * Description : Get the external ref clock enable setting for osc in stop mode
+ * This function will get the external reference clock (OSCERCLK) setting when
+ * MCU enters Stop mode.
+ *
+ *END**************************************************************************/
+bool OSC_HAL_GetExternalRefClkInStopModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_OSC_CR_EREFSTEN(baseAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_SetCapacitorCmd
+ * Description : Enable/disable the capacitor configuration for oscillator
+ * This function will enable/disable the specified capacitors configuration for
+ * oscillator. This should be done in early system level init function call
+ * based on system configuration.
+ *
+ *END**************************************************************************/
+void OSC_HAL_SetCapacitorCmd(uint32_t baseAddr,
+ osc_capacitor_config_t capacitorConfig,
+ bool enable)
+{
+ if (capacitorConfig == kOscCapacitor2p)
+ {
+ BW_OSC_CR_SC2P(baseAddr, enable);
+ }
+ else if (capacitorConfig == kOscCapacitor4p)
+ {
+ BW_OSC_CR_SC4P(baseAddr, enable);
+ }
+ else if (capacitorConfig == kOscCapacitor8p)
+ {
+ BW_OSC_CR_SC8P(baseAddr, enable);
+ }
+ else if (capacitorConfig == kOscCapacitor16p)
+ {
+ BW_OSC_CR_SC16P(baseAddr, enable);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_GetCapacitorCmd
+ * Description : Get the capacitor configuration for specific oscillator
+ * This function will get the specified capacitors configuration for the
+ * oscillator.
+ *
+ *END**************************************************************************/
+bool OSC_HAL_GetCapacitorCmd(uint32_t baseAddr,
+ osc_capacitor_config_t capacitorConfig)
+{
+ if (capacitorConfig == kOscCapacitor2p)
+ {
+ return (bool)BR_OSC_CR_SC2P(baseAddr);
+ }
+ else if (capacitorConfig == kOscCapacitor4p)
+ {
+ return (bool)BR_OSC_CR_SC4P(baseAddr);
+ }
+ else if (capacitorConfig == kOscCapacitor8p)
+ {
+ return (bool)BR_OSC_CR_SC8P(baseAddr);
+ }
+ else if (capacitorConfig == kOscCapacitor16p)
+ {
+ return (bool)BR_OSC_CR_SC16P(baseAddr);
+ }
+
+ return 0;
+}
+
+#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_SetExternalRefClkDivCmd
+ * Description : Set the external reference clock divider setting for osc
+ * This function will get the external reference clock divider setting
+ * for oscillator - that is the OSCERCLK. This clock will be used by many
+ * peripherals.
+ *
+ *END**************************************************************************/
+void OSC_HAL_SetExternalRefClkDivCmd(uint32_t baseAddr, uint32_t divider)
+{
+ BW_OSC_DIV_ERPS(baseAddr, divider);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_GetExternalRefClkDivCmd
+ * Description : Get the external reference clock divider setting for osc
+ * This function will get the external reference clock divider setting
+ * for oscillator - that is the OSCERCLK. This clock will be used by many
+ * peripherals.
+ *
+ *END**************************************************************************/
+uint32_t OSC_HAL_GetExternalRefClkDivCmd(uint32_t baseAddr)
+{
+ return BR_OSC_DIV_ERPS(baseAddr);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OSC_HAL_H__)
+#define __FSL_OSC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_osc_features.h"
+
+/*! @addtogroup osc_hal*/
+/*! @{*/
+
+/*! @file fsl_osc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Oscillator capacitor load configurations.*/
+typedef enum _osc_capacitor_config {
+ kOscCapacitor2p = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
+ kOscCapacitor4p = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
+ kOscCapacitor8p = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
+ kOscCapacitor16p = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
+} osc_capacitor_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name oscillator control APIs*/
+/*@{*/
+
+
+/*!
+ * @brief Enables the external reference clock for the oscillator.
+ *
+ * This function enables the external reference clock output
+ * for the oscillator, OSCERCLK. This clock is used
+ * by many peripherals. It should be enabled at an early system initialization
+ * stage to ensure the peripherals can select and use it.
+ *
+ * @param baseAddr Oscillator register base address
+ * @param enable enable/disable the clock
+ */
+void OSC_HAL_SetExternalRefClkCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Gets the external reference clock enable setting for the oscillator.
+ *
+ * This function gets the external reference clock output enable setting
+ * for the oscillator , OSCERCLK. This clock is used
+ * by many peripherals. It should be enabled at an early system initialization
+ * stage to ensure the peripherals could select and use it.
+ *
+ * @param baseAddr Oscillator register base address
+ * @return enable clock enable/disable setting
+ */
+bool OSC_HAL_GetExternalRefClkCmd(uint32_t baseAddr);
+
+/*!
+ * @brief Enables/disables the external reference clock in stop mode.
+ *
+ * This function enables/disables the external reference clock (OSCERCLK) when an
+ * MCU enters the stop mode.
+ *
+ * @param baseAddr Oscillator register base address
+ * @param enable enable/disable setting
+ */
+void OSC_HAL_SetExternalRefClkInStopModeCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Gets the external reference clock enable setting in stop mode.
+ *
+ * This function gets the external reference clock (OSCERCLK) enable setting when an
+ * MCU enters stop mode.
+ *
+ * @param baseAddr Oscillator register base address
+ */
+bool OSC_HAL_GetExternalRefClkInStopModeCmd(uint32_t baseAddr);
+
+/*!
+ * @brief Enables the capacitor configuration for the oscillator.
+ *
+ * This function enables the specified capacitors configuration for the
+ * oscillator. This should be done in the early system level initialization function call
+ * based on the system configuration.
+ *
+ * @param baseAddr Oscillator register base address
+ * @param capacitorConfig Capacitor configuration. (2p, 4p, 8p, 16p)
+ * @param enable enable/disable the Capacitor configuration
+ */
+void OSC_HAL_SetCapacitorCmd(uint32_t baseAddr,
+ osc_capacitor_config_t capacitorConfig,
+ bool enable);
+
+/*!
+ * @brief Gets the capacitor configuration for a specific oscillator.
+ *
+ * This function gets the specified capacitors configuration for an
+ * oscillator.
+ *
+ * @param baseAddr Oscillator register base address
+ * @param capacitorConfig Capacitor configuration.
+ * @return enable enable/disable setting
+ */
+bool OSC_HAL_GetCapacitorCmd(uint32_t baseAddr,
+ osc_capacitor_config_t capacitorConfig);
+
+#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
+/*!
+ * @brief Sets the external reference clock divider.
+ *
+ * This function sets the divider for the external reference clock.
+ *
+ * @param baseAddr Oscillator register base address
+ * @param divider divider settings
+ */
+void OSC_HAL_SetExternalRefClkDivCmd(uint32_t baseAddr, uint32_t divider);
+
+/*!
+ * @brief Gets the external reference clock divider.
+ *
+ * This function gets the divider for the external reference clock.
+ *
+ * @param baseAddr Oscillator register base address
+ * @return divider divider settings
+ */
+uint32_t OSC_HAL_GetExternalRefClkDivCmd(uint32_t baseAddr);
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_OSC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,87 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_PDB_FEATURES_H__) +#define __FSL_PDB_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ + defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ + defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ + defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ + defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Define the count of supporting ADC pre-trigger for each channel. */ + #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_PDB_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pdb_hal.h"
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_Init
+ * Description : Reset PDB's registers to a known state. This state is
+ * defined in Reference Manual, which is power on reset value.
+ *
+ *END*************************************************************************/
+void PDB_HAL_Init(uint32_t baseAddr)
+{
+ uint32_t chn, preChn;
+ HW_PDB_SC_WR(baseAddr, 0U);
+ HW_PDB_MOD_WR(baseAddr, 0xFFFFU);
+ HW_PDB_IDLY_WR(baseAddr, 0xFFFFU);
+ /* For ADC trigger. */
+ for (chn = 0U; chn < HW_PDB_CHnC1_COUNT; chn++)
+ {
+ HW_PDB_CHnC1_WR(baseAddr, chn, 0U);
+ HW_PDB_CHnS_WR(baseAddr, chn,0xFU);
+ for (preChn = 0U; preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT; preChn++)
+ {
+ PDB_HAL_SetPreTriggerDelayCount(baseAddr, chn, preChn, 0U);
+ }
+ }
+ /* For DAC trigger. */
+ for (chn = 0U; chn < HW_PDB_DACINTCn_COUNT; chn++)
+ {
+ HW_PDB_DACINTCn_WR(baseAddr, chn, 0U);
+ HW_PDB_DACINTn_WR(baseAddr ,chn, 0U);
+ }
+ /* For Pulse out trigger. */
+ HW_PDB_POEN_WR(baseAddr, 0U);
+ for (chn = 0U; chn < HW_PDB_POnDLY_COUNT; chn++)
+ {
+ HW_PDB_POnDLY_WR(baseAddr, chn, 0U);
+ }
+ /* Load the setting value. */
+ PDB_HAL_Enable(baseAddr);
+ PDB_HAL_SetLoadRegsCmd(baseAddr);
+ PDB_HAL_Disable(baseAddr);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetPreTriggerBackToBackCmd
+ * Description : Switch to enable pre-trigger's back to back mode.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetPreTriggerBackToBackCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable)
+{
+ assert(chn < HW_PDB_CHnC1_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+
+ uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn);
+ if (enable)
+ {
+ tmp32 |= (1U << (preChn + BP_PDB_CHnC1_BB));
+ }
+ else
+ {
+ tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_BB));
+ }
+ HW_PDB_CHnC1_WR(baseAddr, chn, tmp32);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetPreTriggerOutputCmd
+ * Description : Switch to enable pre-trigger's output.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetPreTriggerOutputCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable)
+{
+ assert(chn < HW_PDB_CHnC1_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+
+ uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn);
+ if (enable)
+ {
+ tmp32 |= (1U << (preChn + BP_PDB_CHnC1_TOS));
+ }
+ else
+ {
+ tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_TOS));
+ }
+ HW_PDB_CHnC1_WR(baseAddr, chn, tmp32);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetPreTriggerCmd
+ * Description : Switch to enable pre-trigger's.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetPreTriggerCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable)
+{
+ assert(chn < HW_PDB_CHnC1_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+ uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn);
+
+ if (enable)
+ {
+ tmp32 |= (1U << (preChn + BP_PDB_CHnC1_EN));
+ }
+ else
+ {
+ tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_EN));
+ }
+ HW_PDB_CHnC1_WR(baseAddr, chn, tmp32);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_ClearPreTriggerFlag
+ * Description : Clear the flag that the PDB counter reaches to the
+ * pre-trigger's delay value.
+ *
+ *END*************************************************************************/
+void PDB_HAL_ClearPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn)
+{
+ assert(chn < HW_PDB_CHnS_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+
+ /* Write 0 to clear. */
+ uint32_t tmp32 = HW_PDB_CHnS_RD(baseAddr, chn); /* Get current value. */
+ tmp32 &= ~(1U << (preChn + BP_PDB_CHnS_CF)); /* Update the change. */
+ tmp32 &= BM_PDB_CHnS_CF; /* Limit the change range. */
+
+ HW_PDB_CHnS_WR(baseAddr, chn, tmp32);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_ClearPreTriggerSeqErrFlag
+ * Description : Clear the flag that sequence error is detected.
+ *
+ *END*************************************************************************/
+void PDB_HAL_ClearPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn)
+{
+ assert(chn < HW_PDB_CHnS_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+
+ /* Write 1 to clear. */
+ uint32_t tmp32 = HW_PDB_CHnS_RD(baseAddr, chn); /* Get current value. */
+ tmp32 &= ~BM_PDB_CHnS_ERR;/* Clear the operate controller. */
+ tmp32 |= ( 1U << (preChn + BP_PDB_CHnS_ERR) );/* Add indicated clear operator. */
+
+ HW_PDB_CHnS_WR(baseAddr, chn, tmp32);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetPreTriggerDelayCount
+ * Description : Set the delay value for pre-trigger.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetPreTriggerDelayCount(uint32_t baseAddr, uint32_t chn, uint32_t preChn, uint32_t value)
+{
+ assert(chn < HW_PDB_CHnDLY0_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+ switch (preChn)
+ {
+ case 0U:
+ BW_PDB_CHnDLY0_DLY(baseAddr, chn, value);
+ break;
+#if (FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT > 1U)
+ case 1U:
+ BW_PDB_CHnDLY1_DLY(baseAddr, chn, value);
+ break;
+#endif /* FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT */
+ default:
+ break;
+ }
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetPulseOutCmd
+ * Description : Switch to enable the pulse-out trigger.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetPulseOutCmd(uint32_t baseAddr, uint32_t pulseChn, bool enable)
+{
+ assert(pulseChn < HW_PDB_POnDLY_COUNT);
+
+ uint32_t tmp32 = HW_PDB_POEN_RD(baseAddr);
+
+ if (enable)
+ {
+ tmp32 |= (1U << (pulseChn+BP_PDB_POEN_POEN));
+ }
+ else
+ {
+ tmp32 &= ~(1U << (pulseChn+BP_PDB_POEN_POEN));
+ }
+ HW_PDB_POEN_WR(baseAddr, tmp32);
+}
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PDB_HAL_H__
+#define __FSL_PDB_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_pdb_features.h"
+
+/*!
+ * @addtogroup pdb_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*!
+ * @brief PDB status return codes.
+ */
+typedef enum _pdb_status
+{
+ kStatus_PDB_Success = 0U, /*!< Success. */
+ kStatus_PDB_InvalidArgument = 1U, /*!< Invalid argument existed. */
+ kStatus_PDB_Failed = 2U /*!< Execution failed. */
+} pdb_status_t;
+
+/*!
+ * @brief Defines the type of value load mode for the PDB module.
+ *
+ * Some timing related registers, such as the MOD, IDLY, CHnDLYm, INTx and POyDLY,
+ * buffer the setting values. Only the load operation is triggered.
+ * The setting value is loaded from a buffer and takes effect. There are
+ * four loading modes to fit different applications.
+ */
+typedef enum _pdb_load_mode
+{
+ kPdbLoadImmediately = 0U,
+ /*!< Loaded immediately after load operation. */
+ kPdbLoadAtModuloCounter = 1U,
+ /*!< Loaded when counter hits the modulo after load operation. */
+ kPdbLoadAtNextTrigger = 2U,
+ /*!< Loaded when detecting an input trigger after load operation. */
+ kPdbLoadAtModuloCounterOrNextTrigger = 3U
+ /*!< Loaded when counter hits the modulo or detecting an input trigger after load operation. */
+} pdb_load_mode_t;
+
+/*!
+ * @brief Defines the type of prescaler divider for the PDB counter clock.
+ */
+typedef enum _pdb_clk_prescaler_div_mode
+{
+ kPdbClkPreDivBy1 = 0U, /*!< Counting divided by multiplication factor selected by MULT. */
+ kPdbClkPreDivBy2 = 1U, /*!< Counting divided by multiplication factor selected by 2 times ofMULT. */
+ kPdbClkPreDivBy4 = 2U, /*!< Counting divided by multiplication factor selected by 4 times ofMULT. */
+ kPdbClkPreDivBy8 = 3U, /*!< Counting divided by multiplication factor selected by 8 times ofMULT. */
+ kPdbClkPreDivBy16 = 4U, /*!< Counting divided by multiplication factor selected by 16 times ofMULT. */
+ kPdbClkPreDivBy32 = 5U, /*!< Counting divided by multiplication factor selected by 32 times ofMULT. */
+ kPdbClkPreDivBy64 = 6U, /*!< Counting divided by multiplication factor selected by 64 times ofMULT. */
+ kPdbClkPreDivBy128 = 7U, /*!< Counting divided by multiplication factor selected by 128 times ofMULT. */
+} pdb_clk_prescaler_div_mode_t;
+
+/*!
+ * @brief Defines the type of trigger source mode for the PDB.
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can
+ * be internal or external (EXTRG pin), or the software trigger.
+ */
+typedef enum _pdb_trigger_src_mode
+{
+ kPdbTrigger0 = 0U, /*!< Select trigger-In 0. */
+ kPdbTrigger1 = 1U, /*!< Select trigger-In 1. */
+ kPdbTrigger2 = 2U, /*!< Select trigger-In 2. */
+ kPdbTrigger3 = 3U, /*!< Select trigger-In 3. */
+ kPdbTrigger4 = 4U, /*!< Select trigger-In 4. */
+ kPdbTrigger5 = 5U, /*!< Select trigger-In 5. */
+ kPdbTrigger6 = 6U, /*!< Select trigger-In 6. */
+ kPdbTrigger7 = 7U, /*!< Select trigger-In 7. */
+ kPdbTrigger8 = 8U, /*!< Select trigger-In 8. */
+ kPdbTrigger9 = 9U, /*!< Select trigger-In 8. */
+ kPdbTrigger10 = 10U, /*!< Select trigger-In 10. */
+ kPdbTrigger11 = 11U, /*!< Select trigger-In 11. */
+ kPdbTrigger12 = 12U, /*!< Select trigger-In 12. */
+ kPdbTrigger13 = 13U, /*!< Select trigger-In 13. */
+ kPdbTrigger14 = 14U, /*!< Select trigger-In 14. */
+ kPdbSoftTrigger = 15U, /*!< Select software trigger. */
+} pdb_trigger_src_mode_t;
+
+/*!
+ * @brief Defines the type of the multiplication source mode for PDB.
+ *
+ * Selects the multiplication factor of the prescaler divider for the PDB counter clock.
+ */
+typedef enum _pdb_mult_factor_mode
+{
+ kPdbMultFactorAs1 = 0U, /*!< Multiplication factor is 1. */
+ kPdbMultFactorAs10 = 1U, /*!< Multiplication factor is 10. */
+ kPdbMultFactorAs20 = 2U, /*!< Multiplication factor is 20. */
+ kPdbMultFactorAs40 = 3U /*!< Multiplication factor is 40. */
+} pdb_mult_factor_mode_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Resets the PDB registers to a known state.
+ *
+ * This function resets the PDB registers to a known state. This state is
+ * defined in a reference manual and is power on reset value.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+void PDB_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Sets the load mode for timing registers.
+ *
+ * This function sets the load mode for some timing registers including
+ * MOD, IDLY, CHnDLYm, INTx and POyDLY.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode, see to "pdb_load_mode_t".
+ */
+static inline void PDB_HAL_SetLoadMode(uint32_t baseAddr, pdb_load_mode_t mode)
+{
+ BW_PDB_SC_LDMOD(baseAddr, (uint32_t)mode);
+}
+
+/*!
+ * @brief Switches to enable the PDB sequence error interrupt.
+ *
+ * This function switches to enable the PDB sequence error interrupt.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable The switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetSeqErrIntCmd(uint32_t baseAddr, bool enabled)
+{
+ BW_PDB_SC_PDBEIE(baseAddr, (enabled ? 1U : 0U) );
+}
+
+/*!
+ * @brief Triggers the DAC by software if enabled.
+ *
+ * If enabled, this function triggers the DAC by using software.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline void PDB_HAL_SetSoftTriggerCmd(uint32_t baseAddr)
+{
+ BW_PDB_SC_SWTRIG(baseAddr, 1U);
+}
+
+/*!
+ * @brief Switches to enable the PDB DMA support.
+ *
+ * This function switches to enable the PDB DMA support.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable The switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PDB_SC_DMAEN(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Sets the prescaler divider from the peripheral bus clock for the PDB.
+ *
+ * This function sets the prescaler divider from the peripheral bus clock for the PDB.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode, see to "pdb_clk_prescaler_div_mode_t".
+ */
+static inline void PDB_HAL_SetPreDivMode(uint32_t baseAddr, pdb_clk_prescaler_div_mode_t mode)
+{
+ BW_PDB_SC_PRESCALER(baseAddr, (uint32_t)mode);
+}
+
+/*!
+ * @brief Sets the trigger source mode for the PDB module.
+ *
+ * This function sets the trigger source mode for the PDB module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode, see to "pdb_trigger_src_mode_t".
+ */
+static inline void PDB_HAL_SetTriggerSrcMode(uint32_t baseAddr, pdb_trigger_src_mode_t mode)
+{
+ BW_PDB_SC_TRGSEL(baseAddr, (uint32_t)mode);
+}
+
+/*!
+ * @brief Switches on to enable the PDB module.
+ *
+ * This function switches on to enable the PDB module.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline void PDB_HAL_Enable(uint32_t baseAddr)
+{
+ BW_PDB_SC_PDBEN(baseAddr, 1U);
+}
+
+/*!
+ * @brief Switches off to enable the PDB module.
+ *
+ * This function switches off to enable the PDB module.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline void PDB_HAL_Disable(uint32_t baseAddr)
+{
+ BW_PDB_SC_PDBEN(baseAddr, 0U);
+}
+
+/*!
+ * @brief Gets the PDB delay interrupt flag.
+ *
+ * This function gets the PDB delay interrupt flag.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return Flat status, true if the flag is set.
+ */
+static inline bool PDB_HAL_GetIntFlag(uint32_t baseAddr)
+{
+ return (1U == BR_PDB_SC_PDBIF(baseAddr));
+}
+
+/*!
+ * @brief Clears the PDB delay interrupt flag.
+ *
+ * This function clears PDB delay interrupt flag.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return Flat status, true if the flag is set.
+ */
+static inline void PDB_HAL_ClearIntFlag(uint32_t baseAddr)
+{
+ BW_PDB_SC_PDBIF(baseAddr, 0U);
+}
+
+/*!
+ * @brief Switches to enable the PDB interrupt.
+ *
+ * This function switches to enable the PDB interrupt.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable The switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PDB_SC_PDBIE(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Sets the PDB prescaler multiplication factor.
+ *
+ * This function sets the PDB prescaler multiplication factor.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param mode Selection of mode, see to "pdb_mult_factor_mode_t".
+ */
+static inline void PDB_HAL_SetPreMultFactorMode(uint32_t baseAddr,
+ pdb_mult_factor_mode_t mode)
+{
+ BW_PDB_SC_MULT(baseAddr, (uint32_t)mode);
+}
+
+/*!
+ * @brief Switches to enable the PDB continuous mode.
+ *
+ * This function switches to enable the PDB continuous mode.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param enable The switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetContinuousModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PDB_SC_CONT(baseAddr, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Loads the delay registers value for the PDB module.
+ *
+ * This function sets the LDOK bit and loads the delay registers value.
+ * Writing one to this bit updates the internal registers MOD, IDLY, CHnDLYm,
+ * DACINTx, and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY take effect according to the load mode settings.
+ *
+ * After one is written to the LDOK bit, the values in the buffers of above mentioned registers
+ * are not effective and cannot be written until the values in the
+ * buffers are loaded into their internal registers.
+ * The LDOK can be written only when the the PDB is enabled or as alone with it. It is
+ * automatically cleared either when the values in the buffers are loaded into the
+ * internal registers or when the PDB is disabled.
+ *
+ * @param baseAddr Register base address for the module.
+ */
+static inline void PDB_HAL_SetLoadRegsCmd(uint32_t baseAddr)
+{
+ BW_PDB_SC_LDOK(baseAddr, 1U);
+}
+
+/*!
+ * @brief Sets the modulus value for the PDB module.
+ *
+ * This function sets the modulus value for the PDB module.
+ * When the counter reaches the setting value, it is automatically reset to zero.
+ * When in continuous mode, the counter begins to increase
+ * again.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value The setting value of upper limit for PDB counter.
+ */
+static inline void PDB_HAL_SetModulusValue(uint32_t baseAddr, uint32_t value)
+{
+ BW_PDB_MOD_MOD(baseAddr, value);
+}
+
+/*!
+ * @brief Gets the modulus value for the PDB module.
+ *
+ * This function gets the modulus value for the PDB module.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return The current value of upper limit for counter.
+ */
+static inline uint32_t PDB_HAL_GetModulusValue(uint32_t baseAddr)
+{
+ return BR_PDB_MOD_MOD(baseAddr);
+}
+
+/*!
+ * @brief Gets the PDB counter value.
+ *
+ * This function gets the PDB counter value.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return The current counter value.
+ */
+static inline uint32_t PDB_HAL_GetCounterValue(uint32_t baseAddr)
+{
+ return BR_PDB_CNT_CNT(baseAddr);
+}
+
+/*!
+ * @brief Sets the interrupt delay milestone of the PDB counter.
+ *
+ * This function sets the interrupt delay milestone of the PDB counter.
+ * If enabled, a PDB interrupt is generated when the counter is equal to the
+ * setting value.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param value The setting value for interrupt delay milestone of PDB counter.
+ */
+static inline void PDB_HAL_SetIntDelayValue(uint32_t baseAddr, uint32_t value)
+{
+ BW_PDB_IDLY_IDLY(baseAddr, value);
+}
+
+/*!
+ * @brief Gets the current interrupt delay milestone of the PDB counter.
+ *
+ * This function gets the current interrupt delay milestone of the PDB counter.
+ *
+ * @param baseAddr Register base address for the module.
+ * @return The current setting value for interrupt delay milestone of PDB counter.
+ */
+static inline uint32_t PDB_HAL_GetIntDelayValue(uint32_t baseAddr)
+{
+ return BR_PDB_IDLY_IDLY(baseAddr);
+}
+
+/*!
+ * @brief Switches to enable the pre-trigger back-to-back mode.
+ *
+ * This function switches to enable the pre-trigger back-to-back mode.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetPreTriggerBackToBackCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable);
+
+/*!
+ * @brief Switches to enable the pre-trigger output.
+ *
+ * This function switches to enable pre-trigger output.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetPreTriggerOutputCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable);
+
+/*!
+ * @brief Switches to enable the pre-trigger.
+ *
+ * This function switches to enable the pre-trigger.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetPreTriggerCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable);
+
+/*!
+ * @brief Gets the flag which indicates whether the PDB counter has reached the pre-trigger delay value.
+ *
+ * This function gets the flag which indicates the PDB counter has reached the
+ * pre-trigger delay value.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @return Flag status. True if the event is asserted.
+ */
+static inline bool PDB_HAL_GetPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn)
+{
+ assert(chn < HW_PDB_CHnC1_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+ return ( ((1U<< preChn) & BR_PDB_CHnS_CF(baseAddr, chn))? true: false);
+}
+
+/*!
+ * @brief Clears the flag which indicates that the PDB counter has reached the pre-trigger delay value.
+ *
+ * This function clears the flag which indicates that the PDB counter has reached the
+ * pre-trigger delay value.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ */
+void PDB_HAL_ClearPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn);
+
+/*!
+ * @brief Gets the flag which indicates whether a sequence error is detected.
+ *
+ * This function gets the flag which indicates whether a sequence error is detected.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @return Flag status. True if the event is asserted.
+ */
+static inline bool PDB_HAL_GetPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn)
+{
+ assert(chn < HW_PDB_CHnC1_COUNT);
+ assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+ return ( ((1U<< preChn) & BR_PDB_CHnS_ERR(baseAddr, chn))? true: false);
+}
+
+/*!
+ * @brief Clears the flag which indicates that a sequence error has been detected.
+ *
+ * This function clears the flag which indicates that the sequence error has been detected.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ */
+void PDB_HAL_ClearPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn);
+
+/*!
+ * @brief Sets the pre-trigger delay value.
+ *
+ * This function sets the pre-trigger delay value.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @param value Setting value for pre-trigger's delay value.
+ */
+void PDB_HAL_SetPreTriggerDelayCount(uint32_t baseAddr, uint32_t chn, uint32_t preChn, uint32_t value);
+
+/*!
+ * @brief Switches to enable the DAC external trigger input.
+ *
+ * This function switches to enable the DAC external trigger input.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param value Setting value for pre-trigger's delay value.
+ */
+static inline void PDB_HAL_SetDacExtTriggerInputCmd(uint32_t baseAddr, uint32_t dacChn, bool enable)
+{
+ assert(dacChn < HW_PDB_DACINTCn_COUNT);
+ BW_PDB_DACINTCn_EXT(baseAddr, dacChn, (enable ? 1U: 0U) );
+}
+
+/*!
+ * @brief Switches to enable the DAC external trigger input.
+ *
+ * This function switches to enable the DAC external trigger input.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetDacIntervalTriggerCmd(uint32_t baseAddr, uint32_t dacChn, bool enable)
+{
+ assert(dacChn < HW_PDB_DACINTCn_COUNT);
+ BW_PDB_DACINTCn_TOE(baseAddr, dacChn, (enable ? 1U: 0U) );
+}
+
+/*!
+ * @brief Sets the interval value for the DAC trigger.
+ *
+ * This function sets the interval value for the DAC trigger.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param value Setting value for DAC trigger interval.
+ */
+static inline void PDB_HAL_SetDacIntervalValue(uint32_t baseAddr, uint32_t dacChn, uint32_t value)
+{
+ assert(dacChn < HW_PDB_DACINTn_COUNT);
+ BW_PDB_DACINTn_INT(baseAddr, dacChn, value);
+}
+
+/*!
+ * @brief Gets the interval value for the DAC trigger.
+ *
+ * This function gets the interval value for the DAC trigger.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @return The current setting value for DAC trigger interval.
+ */
+static inline uint32_t PDB_HAL_GetDacIntervalValue(uint32_t baseAddr, uint32_t dacChn)
+{
+ assert(dacChn < HW_PDB_DACINTn_COUNT);
+ return BR_PDB_DACINTn_INT(baseAddr, dacChn);
+}
+
+/*!
+ * @brief Switches to enable the pulse-out trigger.
+ *
+ * This function switches to enable the pulse-out trigger.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param pulseChn Pulse-out channle index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetPulseOutCmd(uint32_t baseAddr, uint32_t pulseChn, bool enable);
+
+/*!
+ * @brief Sets the counter delay value for the pulse-out goes high.
+ *
+ * This function sets the counter delay value for the pulse-out goes high.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param pulseChn Pulse-out channel index for trigger.
+ * @param value Setting value for PDB delay .
+ */
+static inline void PDB_HAL_SetPulseOutDelayForHigh(uint32_t baseAddr, uint32_t pulseChn, uint32_t value)
+{
+ assert(pulseChn < HW_PDB_POnDLY_COUNT);
+ BW_PDB_POnDLY_DLY1(baseAddr, pulseChn, value);
+}
+
+/*!
+ * @brief Sets the counter delay value for the pulse-out goes low.
+ *
+ * This function sets the counter delay value for the pulse-out goes low.
+ *
+ * @param baseAddr Register base address for the module.
+ * @param pulseChn Pulse-out channel index for trigger.
+ * @param value Setting value for PDB delay .
+ */
+static inline void PDB_HAL_SetPulseOutDelayForLow(uint32_t baseAddr, uint32_t pulseChn, uint32_t value)
+{
+ assert(pulseChn < HW_PDB_POnDLY_COUNT);
+ BW_PDB_POnDLY_DLY2(baseAddr, pulseChn, value);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_PDB_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/pit/fsl_pit_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,127 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_PIT_FEATURES_H__) +#define __FSL_PIT_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MKV30F128VFM10) || \ + defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || \ + defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ + defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || \ + defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || \ + defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ + defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || \ + defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ + defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ + #define FSL_FEATURE_PIT_TIMER_COUNT (4) + /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ + #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) + /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ + #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ + #define FSL_FEATURE_PIT_TIMER_COUNT (4) + /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ + #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) + /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ + #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ + #define FSL_FEATURE_PIT_TIMER_COUNT (4) + /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ + #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) + /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ + #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ + #define FSL_FEATURE_PIT_TIMER_COUNT (2) + /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ + #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) + /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ + #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_PIT_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pit_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_HAL_ReadLifetimeTimerCount
+ * Description : Read current lifefime counter value.
+ * Lifetime timer is 64-bit timer which chains timer 0 and timer 1 together.
+ * So, timer 0 and 1 should by chained by calling PIT_HAL_SetTimerChainCmd
+ * before using this timer. The period of lifetime timer equals to "period of
+ * timer 0 * period of timer 1". For the 64-bit value, higher 32-bit will have
+ * the value of timer 1, and lower 32-bit have the value of timer 0.
+*
+ *END**************************************************************************/
+uint64_t PIT_HAL_ReadLifetimeTimerCount(uint32_t baseAddr)
+{
+ uint32_t valueH = 0U, valueL = 0U;
+
+ /* LTMR64H should be read before LTMR64L */
+ valueH = HW_PIT_LTMR64H_RD(baseAddr);
+ valueL = HW_PIT_LTMR64L_RD(baseAddr);
+ return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PIT_HAL_H__
+#define __FSL_PIT_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_pit_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup pit_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Enables the PIT module.
+ *
+ * This function enables the PIT timer clock (Note: this function does not un-gate
+ * the system clock gating control). It should be called before any other timer
+ * related setup.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ */
+static inline void PIT_HAL_Enable(uint32_t baseAddr)
+{
+ BW_PIT_MCR_MDIS(baseAddr, 0U);
+}
+
+/*!
+ * @brief Disables the PIT module.
+ *
+ * This function disables all PIT timer clocks(Note: it does not affect the
+ * SIM clock gating control).
+ *
+ * @param baseAddr Base address for current PIT instance.
+ */
+static inline void PIT_HAL_Disable(uint32_t baseAddr)
+{
+ BW_PIT_MCR_MDIS(baseAddr, 1U);
+}
+
+/*!
+ * @brief Configures the timers to continue running or to stop in debug mode.
+ *
+ * In debug mode, the timers may or may not be frozen, based on the configuration of
+ * this function. This is intended to aid software development, allowing the developer
+ * to halt the processor, investigate the current state of the system (for example,
+ * the timer values), and continue the operation.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param timerRun Timers run or stop in debug mode.
+ * - true: Timers continue to run in debug mode.
+ * - false: Timers stop in debug mode.
+ */
+static inline void PIT_HAL_SetTimerRunInDebugCmd(uint32_t baseAddr, bool timerRun)
+{
+ BW_PIT_MCR_FRZ(baseAddr, !timerRun);
+}
+
+#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
+/*!
+ * @brief Enables or disables the timer chain with the previous timer.
+ *
+ * When a timer has a chain mode enabled, it only counts after the previous
+ * timer has expired. If the timer n-1 has counted down to 0, counter n
+ * decrements the value by one. This allows the developers to chain timers together
+ * and form a longer timer. The first timer (timer 0) cannot be chained to any
+ * other timer.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number which is chained with the previous timer.
+ * @param enable Enable or disable chain.
+ * - true: Current timer is chained with the previous timer.
+ * - false: Timer doesn't chain with other timers.
+ */
+static inline void PIT_HAL_SetTimerChainCmd(uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ BW_PIT_TCTRLn_CHN(baseAddr, channel, enable);
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE*/
+
+/* @} */
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load the start value as specified by the function
+ * PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count), count down to
+ * 0, and load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the time-out interrupt flag.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_StartTimer(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ BW_PIT_TCTRLn_TEN(baseAddr, channel, 1U);
+}
+
+/*!
+ * @brief Stops the timer from counting.
+ *
+ * This function stops every timer from counting. Timers reload their periods
+ * respectively after they call the PIT_HAL_StartTimer the next time.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_StopTimer(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ BW_PIT_TCTRLn_TEN(baseAddr, channel, 0U);
+}
+
+/*!
+ * @brief Checks to see whether the current timer is started or not.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current timer running status
+ * -true: Current timer is running.
+ * -false: Current timer has stopped.
+ */
+static inline bool PIT_HAL_IsTimerRunning(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ return BR_PIT_TCTRLn_TEN(baseAddr, channel);
+}
+
+/* @} */
+
+/*!
+ * @name Timer Period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function.
+ * The counter period of a running timer can be modified by first stopping
+ * the timer, setting a new load value, and starting the timer again. If
+ * timers are not restarted, the new value is loaded after the next trigger
+ * event.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @param count Timer period in units of count
+ */
+static inline void PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ HW_PIT_LDVALn_WR(baseAddr, channel, count);
+}
+
+/*!
+ * @brief Returns the current timer period in units of count.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Timer period in units of count
+ */
+static inline uint32_t PIT_HAL_GetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ return HW_PIT_LDVALn_RD(baseAddr, channel);
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current timer counting value
+ */
+static inline uint32_t PIT_HAL_ReadTimerCount(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ return HW_PIT_CVALn_RD(baseAddr, channel);
+}
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*!
+ * @brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_HAL_SetTimerChainCmd
+ * before using this timer. The period of lifetime timer is equal to the "period of
+ * timer 0 * period of timer 1". For the 64-bit value, the higher 32-bit has
+ * the value of timer 1, and the lower 32-bit has the value of timer 0.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @return Current lifetime timer value
+ */
+uint64_t PIT_HAL_ReadLifetimeTimerCount(uint32_t baseAddr);
+#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the timer interrupt.
+ *
+ * If enabled, an interrupt happens when a timeout event occurs
+ * (Note: NVIC should be called to enable pit interrupt in system level).
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @param enable Enable or disable interrupt.
+ * - true: Generate interrupt when timer counts to 0.
+ * - false: No interrupt is generated.
+ */
+static inline void PIT_HAL_SetIntCmd(uint32_t baseAddr, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ BW_PIT_TCTRLn_TIE(baseAddr, channel, enable);
+}
+
+/*!
+ * @brief Checks whether the timer interrupt is enabled or not.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Status of enabled or disabled interrupt
+ * - true: Interrupt is enabled.
+ * - false: Interrupt is disabled.
+ */
+static inline bool PIT_HAL_GetIntCmd(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ return BR_PIT_TCTRLn_TIE(baseAddr, channel);
+}
+
+/*!
+ * @brief Clears the timer interrupt flag.
+ *
+ * This function clears the timer interrupt flag after a timeout event
+ * occurs.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_ClearIntFlag(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ /* Write 1 will clear the flag. */
+ HW_PIT_TFLGn_WR(baseAddr, channel, 1U);
+}
+
+/*!
+ * @brief Reads the current timer timeout flag.
+ *
+ * Every time the timer counts to 0, this flag is set.
+ *
+ * @param baseAddr Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current status of the timeout flag
+ * - true: Timeout has occurred.
+ * - false: Timeout has not yet occurred.
+ */
+static inline bool PIT_HAL_IsIntPending(uint32_t baseAddr, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+ return HW_PIT_TFLGn_RD(baseAddr, channel);
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PIT_HAL_H__*/
+/*******************************************************************************
+* EOF
+*******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,109 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_PMC_FEATURES_H__) +#define __FSL_PMC_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL03Z32CAF4) || \ + defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || \ + defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \ + defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ + defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \ + defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ + defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || \ + defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || \ + defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ + defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || \ + defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || \ + defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ + defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \ + defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \ + defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \ + defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ + defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ + defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ + defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ + defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ + defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || \ + defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ + defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || \ + defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ + defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ + defined(CPU_MKV46F256VLL15) + /* @brief Has Bandgap Enable In VLPx Operation support. */ + #define FSL_FEATURE_PMC_HAS_BGEN (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has Bandgap Enable In VLPx Operation support. */ + #define FSL_FEATURE_PMC_HAS_BGEN (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_PMC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pmc_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PMC_HAL_SetLowVoltIntCmd
+ * Description : Enable/Disable low voltage related interrupts
+ * This function enables the interrupt for the low voltage detection, warning,
+ * etc. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a hardware
+ * interrupt occurs.
+ *
+ *END**************************************************************************/
+void PMC_HAL_SetLowVoltIntCmd(uint32_t baseAddr, pmc_int_select_t intSelect, bool enable)
+{
+ switch (intSelect)
+ {
+ case kPmcIntLowVoltDetect: /* Low Voltage Detect */
+ BW_PMC_LVDSC1_LVDIE(baseAddr, enable);
+ break;
+ case kPmcIntLowVoltWarn: /* Low Voltage Warning */
+ BW_PMC_LVDSC2_LVWIE(baseAddr, enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_PMC_HAL_H__)
+#define __FSL_PMC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_pmc_features.h"
+
+/*! @addtogroup pmc_hal*/
+/*! @{*/
+
+/*! @file fsl_pmc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Low-Voltage Warning Voltage Select*/
+typedef enum _pmc_low_volt_warn_volt_select {
+ kPmcLowVoltWarnVoltLowTrip, /*!< Low trip point selected (VLVW = VLVW1)*/
+ kPmcLowVoltWarnVoltMid1Trip, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
+ kPmcLowVoltWarnVoltMid2Trip, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
+ kPmcLowVoltWarnVoltHighTrip /*!< High trip point selected (VLVW = VLVW4)*/
+} pmc_low_volt_warn_volt_select_t;
+
+/*! @brief Low-Voltage Detect Voltage Select*/
+typedef enum _pmc_low_volt_detect_volt_select {
+ kPmcLowVoltDetectVoltLowTrip, /*!< Low trip point selected (V LVD = V LVDL )*/
+ kPmcLowVoltDetectVoltHighTrip, /*!< High trip point selected (V LVD = V LVDH )*/
+} pmc_low_volt_detect_volt_select_t;
+
+/*! @brief interrupt control*/
+typedef enum _pmc_int_select {
+ kPmcIntLowVoltDetect, /*!< Low Voltage Detect Interrupt */
+ kPmcIntLowVoltWarn, /*!< Low Voltage Warning Interrupt */
+} pmc_int_select_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Power Management Controller Control APIs*/
+/*@{*/
+
+
+/*!
+ * @brief Enables/Disables low voltage-related interrupts.
+ *
+ * This function enables the interrupt for the low voltage detection, warning,
+ * etc. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a hardware
+ * interrupt occurs.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param intSelect interrut select
+ * @param enable enable/disable the interrupt
+ */
+void PMC_HAL_SetLowVoltIntCmd(uint32_t baseAddr, pmc_int_select_t intSelect, bool enable);
+
+/*!
+ * @brief Low-Voltage Detect Hardware Reset Enable/Disable (write once)
+ *
+ * This function enables/disables the hardware reset for the low voltage
+ * detection. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a
+ * hardware reset occurs. This setting is a write-once-only. Any additional writes
+ * are ignored.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param enable enable/disable the LVD hardware reset
+ */
+static inline void PMC_HAL_SetLowVoltDetectResetCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PMC_LVDSC1_LVDRE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Low-Voltage Detect Acknowledge
+ *
+ * This function acknowledges the low voltage detection errors (write 1 to
+ * clear LVDF).
+ *
+ * @param baseAddr Base address for current PMC instance.
+ */
+static inline void PMC_HAL_SetLowVoltDetectAck(uint32_t baseAddr)
+{
+ BW_PMC_LVDSC1_LVDACK(baseAddr, 1);
+}
+
+/*!
+ * @brief Low-Voltage Detect Flag Read
+ *
+ * This function reads the current LVDF status. If it returns 1, a low
+ * voltage event is detected.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return status Current low voltage detect flag
+ * - true: Low-Voltage detected
+ * - false: Low-Voltage not detected
+ */
+static inline bool PMC_HAL_GetLowVoltDetectFlag(uint32_t baseAddr)
+{
+ return BR_PMC_LVDSC1_LVDF(baseAddr);
+}
+
+/*!
+ * @brief Sets the Low-Voltage Detect Voltage Mode
+ *
+ * This function sets the low voltage detect voltage select. It sets
+ * the low voltage detect trip point voltage (Vlvd). An application can select
+ * either a low-trip or a high-trip point. See a chip reference manual for details.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param select Voltage select setting defined in pmc_lvdv_select_t
+ */
+static inline void PMC_HAL_SetLowVoltDetectVoltMode(uint32_t baseAddr, pmc_low_volt_detect_volt_select_t select)
+{
+ BW_PMC_LVDSC1_LVDV(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Low-Voltage Detect Voltage Mode
+ *
+ * This function gets the low voltage detect voltage select. It gets
+ * the low voltage detect trip point voltage (Vlvd). An application can select
+ * either a low-trip or a high-trip point. See a chip reference manual for details.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return select Current voltage select setting
+ */
+static inline pmc_low_volt_detect_volt_select_t PMC_HAL_GetLowVoltDetectVoltMode(uint32_t baseAddr)
+{
+ return (pmc_low_volt_detect_volt_select_t)BR_PMC_LVDSC1_LVDV(baseAddr);
+}
+
+/*!
+ * @brief Low-Voltage Warning Acknowledge
+ *
+ * This function acknowledges the low voltage warning errors (write 1 to
+ * clear LVWF).
+ *
+ * @param baseAddr Base address for current PMC instance.
+ */
+static inline void PMC_HAL_SetLowVoltWarnAck(uint32_t baseAddr)
+{
+ BW_PMC_LVDSC2_LVWACK(baseAddr, 1);
+}
+
+/*!
+ * @brief Low-Voltage Warning Flag Read
+ *
+ * This function polls the current LVWF status. When 1 is returned, it
+ * indicates a low-voltage warning event. LVWF is set when V Supply transitions
+ * below the trip point or after reset and V Supply is already below the V LVW.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return status Current LVWF status
+ * - true: Low-Voltage Warning Flag is set.
+ * - false: the Low-Voltage Warning does not happen.
+ */
+static inline bool PMC_HAL_GetLowVoltWarnFlag(uint32_t baseAddr)
+{
+ return BR_PMC_LVDSC2_LVWF(baseAddr);
+}
+
+/*!
+ * @brief Sets the Low-Voltage Warning Voltage Mode.
+ *
+ * This function sets the low voltage warning voltage select. It sets
+ * the low voltage warning trip point voltage (Vlvw). An application can select
+ * either a low, mid1, mid2 and a high-trip point. See a chip reference manual for
+ * details and the pmc_lvwv_select_t for supported settings.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param select Low voltage warning select setting
+ */
+static inline void PMC_HAL_SetLowVoltWarnVoltMode(uint32_t baseAddr, pmc_low_volt_warn_volt_select_t select)
+{
+ BW_PMC_LVDSC2_LVWV(baseAddr, select);
+}
+
+/*!
+ * @brief Gets the Low-Voltage Warning Voltage Mode.
+ *
+ * This function gets the low voltage warning voltage select. It gets
+ * the low voltage warning trip point voltage (Vlvw). See the pmc_lvwv_select_t
+ * for supported settings.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return select Current low voltage warning select setting
+ */
+static inline pmc_low_volt_warn_volt_select_t PMC_HAL_GetLowVoltWarnVoltMode(uint32_t baseAddr)
+{
+ return (pmc_low_volt_warn_volt_select_t)BR_PMC_LVDSC2_LVWV(baseAddr);
+}
+
+#if FSL_FEATURE_PMC_HAS_BGEN
+/*!
+ * @brief Enables the Bandgap in the VLPx Operation.
+ *
+ * This function enables/disables the bandgap in lower power modes
+ * (VLPx, * LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes, set the BGEN to continue to enable
+ * the bandgap operation.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param enable enable/disable the Bangap.
+ */
+static inline void PMC_HAL_SetBandgapInLowPowerModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PMC_REGSC_BGEN(baseAddr, enable);
+}
+#endif
+
+/*!
+ * @brief Enables/Disables the Bandgap Buffer.
+ *
+ * This function enables/disables the Bandgap buffer.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @param enable enable/disable the Bangap Buffer.
+ */
+static inline void PMC_HAL_SetBandgapBufferCmd(uint32_t baseAddr, bool enable)
+{
+ BW_PMC_REGSC_BGBE(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the acknowledge isolation value.
+ *
+ * This function reads the Acknowledge Isolation setting that indicates
+ * whether certain peripherals and the I/O pads are in a latched state as
+ * a result of having been in the VLLS mode.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return value ACK isolation
+ * 0 - Peripherals and I/O pads are in a normal run state.
+ * 1 - Certain peripherals and I/O pads are in an isolated and
+ * latched state.
+ */
+static inline uint8_t PMC_HAL_GetAckIsolation(uint32_t baseAddr)
+{
+ return BR_PMC_REGSC_ACKISO(baseAddr);
+}
+
+/*!
+ * @brief Clears an acknowledge isolation.
+ *
+ * This function clears the ACK Isolation flag. Writing one to this setting
+ * when it is set releases the I/O pads and certain peripherals to their normal
+ * run mode state.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ */
+static inline void PMC_HAL_SetClearAckIsolation(uint32_t baseAddr)
+{
+ BW_PMC_REGSC_ACKISO(baseAddr, 1);
+}
+
+/*!
+ * @brief Gets the Regulator regulation status.
+ *
+ * This function returns the regulator to a run regulation status. It provides
+ * the current status of the internal voltage regulator.
+ *
+ * @param baseAddr Base address for current PMC instance.
+ * @return value Regulation status
+ * 0 - Regulator is in a stop regulation or in transition to/from it.
+ * 1 - Regulator is in a run regulation.
+ *
+ */
+static inline uint8_t PMC_HAL_GetRegulatorStatus(uint32_t baseAddr)
+{
+ return BR_PMC_REGSC_REGONS(baseAddr);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_PMC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,333 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_PORT_FEATURES_H__) +#define __FSL_PORT_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ + defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ + defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has control lock (register bit PCR[LK]). */ + #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) + /* @brief Has open drain control (register bit PCR[ODE]). */ + #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) + /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) + #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has DMA request (register bit field PCR[IRQC] values). */ + #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) + /* @brief Has pull resistor selection (register bit PCR[PS]). */ + #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) + /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ + #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) + /* @brief Has slew rate control (register bit PCR[SRE]). */ + #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) + /* @brief Has passive filter (register bit field PCR[PFE]). */ + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) + #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has drive strength control (register bit PCR[DSE]). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) + /* @brief Has separate drive strength register (HDRVE). */ + #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) + /* @brief Has glitch filter (register IOFLT). */ + #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_PORT_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_port_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PORT_HAL_SetLowGlobalPinCtrl
+ * Description : Configure low half of pin control register for the same settings,
+ * this function operates pin 0 -15 of one specific port.
+ *
+ *END**************************************************************************/
+void PORT_HAL_SetLowGlobalPinCtrl(uint32_t baseAddr, uint16_t lowPinSelect, uint16_t config)
+{
+ uint32_t combine = lowPinSelect;
+ combine = (combine << 16) + config;
+ HW_PORT_GPCLR_WR(baseAddr, combine);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PORT_HAL_SetHighGlobalPinCtrl
+ * Description : Configure high half of pin control register for the same
+ * settings, this function operates pin 16 -31 of one specific port.
+ *
+ *END**************************************************************************/
+void PORT_HAL_SetHighGlobalPinCtrl(uint32_t baseAddr, uint16_t highPinSelect, uint16_t config)
+{
+ uint32_t combine = highPinSelect;
+ combine = (combine << 16) + config;
+ HW_PORT_GPCHR_WR(baseAddr, combine);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,450 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PORT_HAL_H__
+#define __FSL_PORT_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_port_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup port_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Internal resistor pull feature selection*/
+typedef enum _port_pull {
+ kPortPullDown = 0U, /*!< internal pull-down resistor is enabled.*/
+ kPortPullUp = 1U /*!< internal pull-up resistor is enabled.*/
+} port_pull_t;
+
+/*! @brief Slew rate selection*/
+typedef enum _port_slew_rate {
+ kPortFastSlewRate = 0U, /*!< fast slew rate is configured.*/
+ kPortSlowSlewRate = 1U /*!< slow slew rate is configured.*/
+} port_slew_rate_t;
+
+/*! @brief Configures the drive strength.*/
+typedef enum _port_drive_strength {
+ kPortLowDriveStrength = 0U, /*!< low drive strength is configured.*/
+ kPortHighDriveStrength = 1U /*!< high drive strength is configured.*/
+} port_drive_strength_t;
+
+/*! @brief Pin mux selection*/
+typedef enum _port_mux {
+ kPortPinDisabled = 0U, /*!< corresponding pin is disabled as analog.*/
+ kPortMuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO.*/
+ kPortMuxAlt2 = 2U, /*!< chip-specific*/
+ kPortMuxAlt3 = 3U, /*!< chip-specific*/
+ kPortMuxAlt4 = 4U, /*!< chip-specific*/
+ kPortMuxAlt5 = 5U, /*!< chip-specific*/
+ kPortMuxAlt6 = 6U, /*!< chip-specific*/
+ kPortMuxAlt7 = 7U /*!< chip-specific*/
+} port_mux_t;
+
+/*! @brief Digital filter clock source selection*/
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+typedef enum _port_digital_filter_clock_source {
+ kPortBusClock = 0U, /*!< Digital filters are clocked by the bus clock.*/
+ kPortLPOClock = 1U /*!< Digital filters are clocked by the 1 kHz LPO clock.*/
+} port_digital_filter_clock_source_t;
+#endif
+
+/*! @brief Configures the interrupt generation condition.*/
+typedef enum _port_interrupt_config {
+ kPortIntDisabled = 0x0U, /*!< Interrupt/DMA request is disabled.*/
+ kPortDmaRisingEdge = 0x1U, /*!< DMA request on rising edge.*/
+ kPortDmaFallingEdge = 0x2U, /*!< DMA request on falling edge.*/
+ kPortDmaEitherEdge = 0x3U, /*!< DMA request on either edge.*/
+ kPortIntLogicZero = 0x8U, /*!< Interrupt when logic zero. */
+ kPortIntRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
+ kPortIntFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+ kPortIntEitherEdge = 0xBU, /*!< Interrupt on either edge. */
+ kPortIntLogicOne = 0xCU /*!< Interrupt when logic one. */
+} port_interrupt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Selects the internal resistor as pull-down or pull-up.
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * @param baseAddr port base address.
+ * @param pin port pin number
+ * @param pullSelect internal resistor pull feature selection
+ * - kPortPullDown: internal pull-down resistor is enabled.
+ * - kPortPullUp : internal pull-up resistor is enabled.
+ */
+static inline void PORT_HAL_SetPullMode(uint32_t baseAddr,
+ uint32_t pin,
+ port_pull_t pullSelect)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_PS(baseAddr, pin, pullSelect);
+}
+
+/*!
+ * @brief Enables or disables the internal pull resistor.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param isPullEnabled internal pull resistor enable or disable
+ * - true : internal pull resistor is enabled.
+ * - false: internal pull resistor is disabled.
+ */
+static inline void PORT_HAL_SetPullCmd(uint32_t baseAddr, uint32_t pin, bool isPullEnabled)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_PE(baseAddr, pin, isPullEnabled);
+}
+
+/*!
+ * @brief Configures the fast/slow slew rate if the pin is used as a digital output.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param rateSelect slew rate selection
+ * - kPortFastSlewRate: fast slew rate is configured.
+ * - kPortSlowSlewRate: slow slew rate is configured.
+ */
+static inline void PORT_HAL_SetSlewRateMode(uint32_t baseAddr,
+ uint32_t pin,
+ port_slew_rate_t rateSelect)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_SRE(baseAddr, pin, rateSelect);
+}
+
+/*!
+ * @brief Configures the passive filter if the pin is used as a digital input.
+ *
+ * If enabled, a low pass filter (10 MHz to 30 MHz bandwidth) is enabled
+ * on the digital input path. Disable the Passive Input Filter when supporting
+ * high speed interfaces (> 2 MHz) on the pin.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param isPassiveFilterEnabled passive filter configuration
+ * - false: passive filter is disabled.
+ * - true : passive filter is enabled.
+ */
+static inline void PORT_HAL_SetPassiveFilterCmd(uint32_t baseAddr,
+ uint32_t pin,
+ bool isPassiveFilterEnabled)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_PFE(baseAddr, pin, isPassiveFilterEnabled);
+}
+
+#if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*!
+ * @brief Enables or disables the open drain.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param isOpenDrainEnabled enable open drain or not
+ * - false: Open Drain output is disabled on the corresponding pin.
+ * - true : Open Drain output is disabled on the corresponding pin.
+ */
+static inline void PORT_HAL_SetOpenDrainCmd(uint32_t baseAddr,
+ uint32_t pin,
+ bool isOpenDrainEnabled)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_ODE(baseAddr, pin, isOpenDrainEnabled);
+}
+#endif /*FSL_FEATURE_PORT_HAS_OPEN_DRAIN*/
+
+/*!
+ * @brief Configures the drive strength if the pin is used as a digital output.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param driveSelect drive strength selection
+ * - kLowDriveStrength : low drive strength is configured.
+ * - kHighDriveStrength: high drive strength is configured.
+ */
+static inline void PORT_HAL_SetDriveStrengthMode(uint32_t baseAddr,
+ uint32_t pin,
+ port_drive_strength_t driveSelect)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_DSE(baseAddr, pin, driveSelect);
+}
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param mux pin muxing slot selection
+ * - kPinDisabled: Pin disabled.
+ * - kMuxAsGpio : Set as GPIO.
+ * - others : chip-specific.
+ */
+static inline void PORT_HAL_SetMuxMode(uint32_t baseAddr, uint32_t pin, port_mux_t mux)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_MUX(baseAddr, pin, mux);
+}
+
+#if FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*!
+ * @brief Locks or unlocks the pin control register bits[15:0].
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param isPinLockEnabled lock pin control register or not
+ * - false: pin control register bit[15:0] are not locked.
+ * - true : pin control register bit[15:0] are locked, cannot be updated till system reset.
+ */
+static inline void PORT_HAL_SetPinCtrlLockCmd(uint32_t baseAddr,
+ uint32_t pin,
+ bool isPinLockEnabled)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_LK(baseAddr, pin, isPinLockEnabled);
+}
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK*/
+
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*!
+ * @brief Enables or disables the digital filter in one single port.
+ * Each bit of the 32-bit register represents one pin.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @param isDigitalFilterEnabled digital filter enable/disable
+ * - false: digital filter is disabled on the corresponding pin.
+ * - true : digital filter is enabled on the corresponding pin.
+ */
+static inline void PORT_HAL_SetDigitalFilterCmd(uint32_t baseAddr,
+ uint32_t pin,
+ bool isDigitalFilterEnabled)
+{
+ assert(pin < 32U);
+ HW_PORT_DFER_SET(baseAddr, (uint32_t)isDigitalFilterEnabled << pin);
+}
+
+/*!
+ * @brief Configures the clock source for the digital input filters. Changing the filter clock source should
+ * only be done after disabling all enabled filters. Every pin in one port uses the same
+ * clock source.
+ *
+ * @param baseAddr port base address
+ * @param clockSource chose which clock source to use for current port
+ * - kBusClock: digital filters are clocked by the bus clock.
+ * - kLPOClock: digital filters are clocked by the 1 kHz LPO clock.
+ */
+static inline void PORT_HAL_SetDigitalFilterClock(uint32_t baseAddr,
+ port_digital_filter_clock_source_t clockSource)
+{
+ HW_PORT_DFCR_WR(baseAddr, clockSource);
+}
+
+/*!
+ * @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs
+ * for enabled digital filters. Glitches that are longer than this register setting
+ * (in clock cycles) pass through the digital filter, while glitches that are equal
+ * to or less than this register setting (in clock cycles) are filtered. Changing the
+ * filter length should only be done after disabling all enabled filters.
+ *
+ * @param baseAddr port base address
+ * @param width configure digital filter width (should be less than 5 bits).
+ */
+static inline void PORT_HAL_SetDigitalFilterWidth(uint32_t baseAddr, uint8_t width)
+{
+ HW_PORT_DFWR_WR(baseAddr, width);
+}
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER*/
+
+/*!
+ * @brief Configures the low half of the pin control register for the same settings.
+ * This function operates pin 0 -15 of one specific port.
+ *
+ * @param baseAddr port base address
+ * @param lowPinSelect update corresponding pin control register or not. For a specific bit:
+ * - 0: corresponding low half of pin control register won't be updated according to configuration.
+ * - 1: corresponding low half of pin control register will be updated according to configuration.
+ * @param config value is written to a low half port control register bits[15:0].
+ */
+void PORT_HAL_SetLowGlobalPinCtrl(uint32_t baseAddr, uint16_t lowPinSelect, uint16_t config);
+
+/*!
+ * @brief Configures the high half of pin control register for the same settings.
+ * This function operates pin 16 -31 of one specific port.
+ *
+ * @param baseAddr port base address
+ * @param highPinSelect update corresponding pin control register or not. For a specific bit:
+ * - 0: corresponding high half of pin control register won't be updated according to configuration.
+ * - 1: corresponding high half of pin control register will be updated according to configuration.
+ * @param config value is written to a high half port control register bits[15:0].
+ */
+void PORT_HAL_SetHighGlobalPinCtrl(uint32_t baseAddr, uint16_t highPinSelect, uint16_t config);
+
+/*@}*/
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param baseAddr port base address.
+ * @param pin port pin number
+ * @param intConfig interrupt configuration
+ * - kIntDisabled : Interrupt/DMA request disabled.
+ * - kDmaRisingEdge : DMA request on rising edge.
+ * - kDmaFallingEdge: DMA request on falling edge.
+ * - kDmaEitherEdge : DMA request on either edge.
+ * - KIntLogicZero : Interrupt when logic zero.
+ * - KIntRisingEdge : Interrupt on rising edge.
+ * - KIntFallingEdge: Interrupt on falling edge.
+ * - KIntEitherEdge : Interrupt on either edge.
+ * - KIntLogicOne : Interrupt when logic one.
+ */
+static inline void PORT_HAL_SetPinIntMode(uint32_t baseAddr,
+ uint32_t pin,
+ port_interrupt_config_t intConfig)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_IRQC(baseAddr, pin, intConfig);
+}
+
+/*!
+ * @brief Gets the current port pin interrupt/DMA request configuration.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @return interrupt configuration
+ * - kIntDisabled : Interrupt/DMA request disabled.
+ * - kDmaRisingEdge : DMA request on rising edge.
+ * - kDmaFallingEdge: DMA request on falling edge.
+ * - kDmaEitherEdge : DMA request on either edge.
+ * - KIntLogicZero : Interrupt when logic zero.
+ * - KIntRisingEdge : Interrupt on rising edge.
+ * - KIntFallingEdge: Interrupt on falling edge.
+ * - KIntEitherEdge : Interrupt on either edge.
+ * - KIntLogicOne : Interrupt when logic one.
+ */
+static inline port_interrupt_config_t PORT_HAL_GetPinIntMode(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32U);
+ return (port_interrupt_config_t)BR_PORT_PCRn_IRQC(baseAddr, pin);
+}
+
+/*!
+ * @brief Reads the individual pin-interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ * @return current pin interrupt status flag
+ * - 0: interrupt is not detected.
+ * - 1: interrupt is detected.
+ */
+static inline bool PORT_HAL_IsPinIntPending(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32U);
+ return BR_PORT_PCRn_ISF(baseAddr, pin);
+}
+
+/*!
+ * @brief Clears the individual pin-interrupt status flag.
+ *
+ * @param baseAddr port base address
+ * @param pin port pin number
+ */
+static inline void PORT_HAL_ClearPinIntFlag(uint32_t baseAddr, uint32_t pin)
+{
+ assert(pin < 32U);
+ BW_PORT_PCRn_ISF(baseAddr, pin, 1U);
+}
+
+/*!
+ * @brief Reads the entire port interrupt status flag.
+ *
+ * @param baseAddr port base address
+ * @return all 32 pin interrupt status flags. For specific bit:
+ * - 0: interrupt is not detected.
+ * - 1: interrupt is detected.
+ */
+static inline uint32_t PORT_HAL_GetPortIntFlag(uint32_t baseAddr)
+{
+ return HW_PORT_ISFR_RD(baseAddr);
+}
+
+/*!
+ * @brief Clears the entire port interrupt status flag.
+ *
+ * @param baseAddr port base address
+ */
+static inline void PORT_HAL_ClearPortIntFlag(uint32_t baseAddr)
+{
+ HW_PORT_ISFR_WR(baseAddr, ~0U);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PORT_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,109 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140516 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_RCM_FEATURES_H__) +#define __FSL_RCM_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ + defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || \ + defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ + defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ + defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || \ + defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || \ + defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ + defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) + /* @brief Has Loss-of-Lock Reset support. */ + #define FSL_FEATURE_RCM_HAS_LOL (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ + defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ + defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ + defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ + defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ + defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ + defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || \ + defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ + defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || \ + defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ + defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ + defined(CPU_MKV46F256VLL15) + /* @brief Has Loss-of-Lock Reset support. */ + #define FSL_FEATURE_RCM_HAS_LOL (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_RCM_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rcm_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RCM_HAL_GetSrcStatusCmd
+ * Description : Get the reset source status
+ *
+ * This function will get the current reset source status for specified source
+ *
+ *END**************************************************************************/
+bool RCM_HAL_GetSrcStatusCmd(uint32_t baseAddr, rcm_source_names_t srcName)
+{
+ bool retValue = false;
+
+ assert(srcName < kRcmSrcNameMax);
+
+ switch (srcName)
+ {
+ case kRcmWakeup: /* low-leakage wakeup reset */
+ retValue = (bool)BR_RCM_SRS0_WAKEUP(baseAddr);
+ break;
+ case kRcmLowVoltDetect: /* low voltage detect reset */
+ retValue = (bool)BR_RCM_SRS0_LVD(baseAddr);
+ break;
+ case kRcmLossOfClk: /* loss of clock reset */
+ retValue = (bool)BR_RCM_SRS0_LOC(baseAddr);
+ break;
+#if FSL_FEATURE_RCM_HAS_LOL
+ case kRcmLossOfLock: /* loss of lock reset */
+ retValue = (bool)BR_RCM_SRS0_LOL(baseAddr);
+ break;
+#endif
+ case kRcmWatchDog: /* watch dog reset */
+ retValue = (bool)BR_RCM_SRS0_WDOG(baseAddr);
+ break;
+ case kRcmExternalPin: /* external pin reset */
+ retValue = (bool)BR_RCM_SRS0_PIN(baseAddr);
+ break;
+ case kRcmPowerOn: /* power on reset */
+ retValue = (bool)BR_RCM_SRS0_POR(baseAddr);
+ break;
+ case kRcmJtag: /* JTAG generated reset */
+ retValue = (bool)BR_RCM_SRS1_JTAG(baseAddr);
+ break;
+ case kRcmCoreLockup: /* core lockup reset */
+ retValue = (bool)BR_RCM_SRS1_LOCKUP(baseAddr);
+ break;
+ case kRcmSoftware: /* software reset */
+ retValue = (bool)BR_RCM_SRS1_SW(baseAddr);
+ break;
+ case kRcmSystem: /* system reset request bit set reset */
+ retValue = (bool)BR_RCM_SRS1_MDM_AP(baseAddr);
+ break;
+ case kRcmEzport: /* EzPort reset */
+ retValue = (bool)BR_RCM_SRS1_EZPT(baseAddr);
+ break;
+ case kRcmStopModeAckErr: /* stop mode ack error reset */
+ retValue = (bool)BR_RCM_SRS1_SACKERR(baseAddr);
+ break;
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_RCM_HAL_H__)
+#define __FSL_RCM_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_rcm_features.h"
+
+/*! @addtogroup rcm_hal*/
+/*! @{*/
+
+/*! @file fsl_rcm_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief System Reset Source Name definitions */
+typedef enum _rcm_source_names {
+ kRcmWakeup, /* low-leakage wakeup reset */
+ kRcmLowVoltDetect, /* low voltage detect reset */
+ kRcmLossOfClk, /* loss of clock reset */
+ kRcmLossOfLock, /* loss of lock reset */
+ kRcmWatchDog, /* watch dog reset */
+ kRcmExternalPin, /* external pin reset */
+ kRcmPowerOn, /* power on reset */
+ kRcmJtag, /* JTAG generated reset */
+ kRcmCoreLockup, /* core lockup reset */
+ kRcmSoftware, /* software reset */
+ kRcmSystem, /* system reset request bit set reset */
+ kRcmEzport, /* EzPort reset */
+ kRcmStopModeAckErr, /* stop mode ack error reset */
+ kRcmSrcNameMax
+} rcm_source_names_t;
+
+/*! @brief Reset pin filter select in Run and Wait modes */
+typedef enum _rcm_filter_run_wait_modes {
+ kRcmFilterDisabled, /* all filtering disabled */
+ kRcmFilterBusClk, /* Bus clock filter enabled */
+ kRcmFilterLpoClk, /* LPO clock filter enabled */
+ kRcmFilterReserverd /* reserved setting */
+} rcm_filter_run_wait_modes_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the reset source status.
+ *
+ * This function gets the current reset source status for a specified source.
+ *
+ * @param baseAddr Register base address of RCM
+ * @param srcName reset source name
+ * @return status true or false for specified reset source
+ */
+bool RCM_HAL_GetSrcStatusCmd(uint32_t baseAddr, rcm_source_names_t srcName);
+
+/*!
+ * @brief Sets the reset pin filter in stop mode.
+ *
+ * This function sets the reset pin filter enable setting in stop mode.
+ *
+ * @param baseAddr Register base address of RCM
+ * @param enable enable or disable the filter in stop mode
+ */
+static inline void RCM_HAL_SetFilterStopModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_RCM_RPFC_RSTFLTSS(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the reset pin filter in stop mode.
+ *
+ * This function gets the reset pin filter enable setting in stop mode.
+ *
+ * @param baseAddr Register base address of RCM
+ * @return enable true/false to enable or disable the filter in stop mode
+ */
+static inline bool RCM_HAL_GetFilterStopModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_RCM_RPFC_RSTFLTSS(baseAddr);
+}
+
+/*!
+ * @brief Sets the reset pin filter in run and wait mode.
+ *
+ * This function sets the reset pin filter enable setting in run/wait mode.
+ *
+ * @param baseAddr Register base address of RCM
+ * @param mode to be set for reset filter in run/wait mode
+ */
+static inline void RCM_HAL_SetFilterRunWaitMode(uint32_t baseAddr, rcm_filter_run_wait_modes_t mode)
+{
+ BW_RCM_RPFC_RSTFLTSRW(baseAddr, mode);
+}
+
+/*!
+ * @brief Gets the reset pin filter for stop mode.
+ *
+ * This function gets the reset pin filter enable setting for stop mode.
+ *
+ * @param baseAddr Register base address of RCM
+ * @return mode for reset filter in run/wait mode
+ */
+static inline rcm_filter_run_wait_modes_t RCM_HAL_GetFilterRunWaitMode(uint32_t baseAddr)
+{
+ return (rcm_filter_run_wait_modes_t)BR_RCM_RPFC_RSTFLTSRW(baseAddr);
+}
+
+/*!
+ * @brief Sets the reset pin filter width.
+ *
+ * This function sets the reset pin filter width.
+ *
+ * @param baseAddr Register base address of RCM
+ * @param width to be set for reset filter width
+ */
+static inline void RCM_HAL_SetFilterWidth(uint32_t baseAddr, uint32_t width)
+{
+ BW_RCM_RPFW_RSTFLTSEL(baseAddr, width);
+}
+
+/*!
+ * @brief Gets the reset pin filter for stop mode.
+ *
+ * This function gets the reset pin filter width.
+ *
+ * @param baseAddr Register base address of RCM
+ * @return width reset filter width
+ */
+static inline uint32_t RCM_HAL_GetFilterWidth(uint32_t baseAddr)
+{
+ return (uint32_t)BR_RCM_RPFW_RSTFLTSEL(baseAddr);
+}
+
+/*!
+ * @brief Gets the EZP_MS_B pin assert status.
+ *
+ * This function gets the easy port mode status (EZP_MS_B) pin assert status.
+ *
+ * @param baseAddr Register base address of RCM
+ * @return status true - asserted, false - reasserted
+ */
+static inline bool RCM_HAL_GetEasyPortModeStatusCmd(uint32_t baseAddr)
+{
+ return (bool)BR_RCM_MR_EZP_MS(baseAddr);
+}
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Reset Control Module APIs*/
+/*@{*/
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_RCM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,144 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_RTC_FEATURES_H__) +#define __FSL_RTC_FEATURES_H__ + +#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (1) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (1) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (1) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \ + defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ + defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ + defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || \ + defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ + defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || \ + defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || \ + defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ + defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || \ + defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \ + defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ + defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \ + defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ + defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || \ + defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || \ + defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || \ + defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has wakeup pin (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_RTC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc_hal.h"
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MIN (60U)
+#define MINS_IN_A_HOUR (60U)
+#define HOURS_IN_A_DAY (24U)
+#define DAYS_IN_A_YEAR (365U)
+#define DAYS_IN_A_LEAP_YEAR (366U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of month length (in days) for the Un-leap-year*/
+static const uint8_t ULY[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U,
+ 31U,30U,31U};
+
+/* Table of month length (in days) for the Leap-year*/
+static const uint8_t LY[] = {0U, 31U, 29U, 31U, 30U, 31U, 30U, 31U, 31U, 30U,
+ 31U,30U,31U};
+
+/* Number of days from begin of the non Leap-year*/
+static const uint16_t MONTH_DAYS[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U,
+ 212U, 243U, 273U, 304U, 334U};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_ConvertSecsToDatetime
+ * Description : converts time data from seconds to a datetime structure.
+ * This function will convert time data from seconds to a datetime structure.
+ *
+ *END**************************************************************************/
+void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime)
+{
+ uint32_t x;
+ uint32_t Seconds, Days, Days_in_year;
+ const uint8_t *Days_in_month;
+
+ /* Start from 1970-01-01*/
+ Seconds = *seconds;
+ /* days*/
+ Days = Seconds / SECONDS_IN_A_DAY;
+ /* seconds left*/
+ Seconds = Seconds % SECONDS_IN_A_DAY;
+ /* hours*/
+ datetime->hour = Seconds / SECONDS_IN_A_HOUR;
+ /* seconds left*/
+ Seconds = Seconds % SECONDS_IN_A_HOUR;
+ /* minutes*/
+ datetime->minute = Seconds / SECONDS_IN_A_MIN;
+ /* seconds*/
+ datetime->second = Seconds % SECONDS_IN_A_MIN;
+ /* year*/
+ datetime->year = YEAR_RANGE_START;
+ Days_in_year = DAYS_IN_A_YEAR;
+
+ while (Days > Days_in_year)
+ {
+ Days -= Days_in_year;
+ datetime->year++;
+ if (datetime->year & 3U)
+ {
+ Days_in_year = DAYS_IN_A_YEAR;
+ }
+ else
+ {
+ Days_in_year = DAYS_IN_A_LEAP_YEAR;
+ }
+ }
+
+ if (datetime->year & 3U)
+ {
+ Days_in_month = ULY;
+ }
+ else
+ {
+ Days_in_month = LY;
+ }
+
+ for (x=1U; x <= 12U; x++)
+ {
+ if (Days <= (*(Days_in_month + x)))
+ {
+ datetime->month = x;
+ break;
+ }
+ else
+ {
+ Days -= (*(Days_in_month + x));
+ }
+ }
+
+ datetime->day = Days;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_IsDatetimeCorrectFormat
+ * Description : checks if the datetime is in correct format.
+ * This function will check if the given datetime is in the correct format.
+ *
+ *END**************************************************************************/
+bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime)
+{
+ bool result = false;
+
+ /* Test correctness of given parameters*/
+ if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) ||
+ (datetime->month > 12U) || (datetime->month < 1U) ||
+ (datetime->day > 31U) || (datetime->day < 1U) ||
+ (datetime->hour >= HOURS_IN_A_DAY) || (datetime->minute >= MINS_IN_A_HOUR) ||
+ (datetime->second >= SECONDS_IN_A_MIN))
+ {
+ /* If not correct then error*/
+ result = false;
+ }
+ else
+ {
+ result = true;
+ }
+
+ /* Is given year un-leap-one?*/
+ /* Leap year calculation only looks for years divisible by 4 as acceptable years is limited */
+ if ( result && (datetime->year & 3U))
+ {
+ /* Does the obtained number of days exceed number of days in the appropriate month & year?*/
+ if (ULY[datetime->month] < datetime->day)
+ {
+ /* If yes (incorrect datetime inserted) then error*/
+ result = false;
+ }
+ }
+ else /* Is given year leap-one?*/
+ {
+ /* Does the obtained number of days exceed number of days in the appropriate month & year?*/
+ if (result && (LY[datetime->month] < datetime->day))
+ {
+ /* if yes (incorrect date inserted) then error*/
+ result = false;
+ }
+ }
+
+ return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_ConvertDatetimeToSecs
+ * Description : converts time data from datetime to seconds.
+ * This function will convert time data from datetime to seconds.
+ *
+ *END**************************************************************************/
+void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds)
+{
+ /* Compute number of days from 1970 till given year*/
+ *seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+ /* Add leap year days */
+ *seconds += ((datetime->year / 4) - (1970U / 4));
+ /* Add number of days till given month*/
+ *seconds += MONTH_DAYS[datetime->month];
+ /* Add days in given month*/
+ *seconds += datetime->day;
+ /* For leap year if month less than or equal to Febraury, decrement day counter*/
+ if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+ {
+ (*seconds)--;
+ }
+
+ *seconds = ((*seconds) * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+ (datetime->minute * SECONDS_IN_A_MIN) + datetime->second;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_Enable
+ * Description : initializes the RTC module.
+ * This function will initiate a soft-reset of the RTC module to reset
+ * all the RTC registers. It also enables the RTC oscillator.
+ *
+ *END**************************************************************************/
+void RTC_HAL_Enable(uint32_t rtcBaseAddr)
+{
+ /* Enable RTC oscillator since it is required to start the counter*/
+ RTC_HAL_SetOscillatorCmd(rtcBaseAddr, true);
+}
+
+void RTC_HAL_Disable(uint32_t rtcBaseAddr)
+{
+ /* Disable counter*/
+ RTC_HAL_EnableCounter(rtcBaseAddr, false);
+
+ /* Disable RTC oscillator */
+ RTC_HAL_SetOscillatorCmd(rtcBaseAddr, false);
+}
+
+void RTC_HAL_Init(uint32_t rtcBaseAddr)
+{
+ uint32_t seconds = 0x1;
+
+ /* Resets the RTC registers except for the SWR bit */
+ RTC_HAL_SoftwareReset(rtcBaseAddr);
+ RTC_HAL_SoftwareResetFlagClear(rtcBaseAddr);
+
+ /* Set TSR register to 0x1 to avoid the TIF bit being set in the SR register */
+ RTC_HAL_SetSecsReg(rtcBaseAddr, seconds);
+
+ /* Clear the interrupt enable register */
+ RTC_HAL_SetSecsIntCmd(rtcBaseAddr, false);
+ RTC_HAL_SetAlarmIntCmd(rtcBaseAddr, false);
+ RTC_HAL_SetTimeOverflowIntCmd(rtcBaseAddr, false);
+ RTC_HAL_SetTimeInvalidIntCmd(rtcBaseAddr, false);
+}
+
+void RTC_HAL_SetDatetime(uint32_t rtcBaseAddr, const rtc_datetime_t * datetime)
+{
+ uint32_t seconds;
+
+ /* Protect against null pointers*/
+ assert(datetime);
+
+ RTC_HAL_ConvertDatetimeToSecs(datetime, &seconds);
+ /* Set time in seconds */
+ RTC_HAL_SetDatetimeInsecs(rtcBaseAddr, seconds);
+}
+
+void RTC_HAL_SetDatetimeInsecs(uint32_t rtcBaseAddr, const uint32_t seconds)
+{
+ /* Disable counter*/
+ RTC_HAL_EnableCounter(rtcBaseAddr, false);
+ /* Set seconds counter*/
+ RTC_HAL_SetSecsReg(rtcBaseAddr, seconds);
+ /* Enable the counter*/
+ RTC_HAL_EnableCounter(rtcBaseAddr, true);
+}
+
+void RTC_HAL_GetDatetime(uint32_t rtcBaseAddr, rtc_datetime_t * datetime)
+{
+ uint32_t seconds = 0;
+
+ /* Protect against null pointers*/
+ assert(datetime);
+
+ RTC_HAL_GetDatetimeInSecs(rtcBaseAddr, &seconds);
+
+ RTC_HAL_ConvertSecsToDatetime(&seconds, datetime);
+}
+
+void RTC_HAL_GetDatetimeInSecs(uint32_t rtcBaseAddr, uint32_t * seconds)
+{
+ /* Protect against null pointers*/
+ assert(seconds);
+ *seconds = RTC_HAL_GetSecsReg(rtcBaseAddr);
+}
+
+bool RTC_HAL_SetAlarm(uint32_t rtcBaseAddr, const rtc_datetime_t * date)
+{
+ uint32_t alrm_seconds, curr_seconds;
+
+ /* Protect against null pointers*/
+ assert(date);
+
+ RTC_HAL_ConvertDatetimeToSecs(date, &alrm_seconds);
+
+ /* Get the current time */
+ curr_seconds = RTC_HAL_GetSecsReg(rtcBaseAddr);
+
+ /* Make sure the alarm is for a future time */
+ if (alrm_seconds <= curr_seconds)
+ {
+ return false;
+ }
+
+ /* set alarm in seconds*/
+ RTC_HAL_SetAlarmReg(rtcBaseAddr, alrm_seconds);
+
+ return true;
+}
+
+void RTC_HAL_GetAlarm(uint32_t rtcBaseAddr, rtc_datetime_t * date)
+{
+ uint32_t seconds = 0;
+
+ /* Protect against null pointers*/
+ assert(date);
+
+ /* Get alarm in seconds */
+ seconds = RTC_HAL_GetAlarmReg(rtcBaseAddr);
+
+ RTC_HAL_ConvertSecsToDatetime(&seconds, date);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+void RTC_HAL_GetMonotonicCounter(uint32_t rtcBaseAddr, uint64_t * counter)
+{
+ uint32_t tmpCountHigh = 0;
+ uint32_t tmpCountLow = 0;
+
+ tmpCountHigh = RTC_HAL_GetMonotonicCounterHigh(rtcBaseAddr);
+ tmpCountLow = RTC_HAL_GetMonotonicCounterLow(rtcBaseAddr);
+
+ *counter = (((uint64_t)(tmpCountHigh) << 32) | ((uint64_t)tmpCountLow));
+}
+
+void RTC_HAL_SetMonotonicCounter(uint32_t rtcBaseAddr, const uint64_t * counter)
+{
+ uint32_t tmpCountHigh = 0;
+ uint32_t tmpCountLow = 0;
+
+ tmpCountHigh = (uint32_t)((*counter) >> 32);
+ RTC_HAL_SetMonotonicCounterHigh(rtcBaseAddr, tmpCountHigh);
+ tmpCountLow = (uint32_t)(*counter);
+ RTC_HAL_SetMonotonicCounterLow(rtcBaseAddr, tmpCountLow);
+}
+
+bool RTC_HAL_IncrementMonotonicCounter(uint32_t rtcBaseAddr)
+{
+ bool result = false;
+
+ if((!(RTC_HAL_IsMonotonicCounterOverflow(rtcBaseAddr))) && (!(RTC_HAL_IsTimeInvalid(rtcBaseAddr))))
+ {
+ /* prepare for incrementing after write*/
+ RTC_HAL_SetMonotonicEnableCmd(rtcBaseAddr, true);
+
+ /* write anything so the counter increments*/
+ BW_RTC_MCLR_MCL(rtcBaseAddr, 1U);
+
+ result = true;
+ }
+
+ return result;
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1976 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_RTC_HAL_H__)
+#define __FSL_RTC_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_rtc_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup rtc_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure is used to hold the time in a simple "date" format.
+ */
+typedef struct RtcDatetime
+{
+ uint16_t year; /*!< Range from 1970 to 2099.*/
+ uint16_t month; /*!< Range from 1 to 12.*/
+ uint16_t day; /*!< Range from 1 to 31 (depending on month).*/
+ uint16_t hour; /*!< Range from 0 to 23.*/
+ uint16_t minute; /*!< Range from 0 to 59.*/
+ uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name RTC HAL API Functions
+ * @{
+ */
+
+/*!
+ * @brief Initializes the RTC module.
+ *
+ * This function enables the RTC oscillator.
+ *
+ * @param rtcBaseAddr The RTC base address.
+ */
+void RTC_HAL_Enable(uint32_t rtcBaseAddr);
+
+/*!
+ * @brief Disables the RTC module.
+ *
+ * This function disablesS the RTC counter and oscillator.
+ *
+ * @param rtcBaseAddr The RTC base address.
+ */
+void RTC_HAL_Disable(uint32_t rtcBaseAddr);
+
+/*!
+ * @brief Resets the RTC module.
+ *
+ * This function initiates a soft-reset of the RTC module to reset
+ * the RTC registers.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ */
+void RTC_HAL_Init(uint32_t rtcBaseAddr);
+
+/*!
+ * @brief Converts seconds to date time format data structure.
+ *
+ * @param seconds holds the date and time information in seconds
+ * @param datetime holds the converted information from seconds in date and time format
+ */
+void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime);
+
+/*!
+ * @brief Checks whether the date time structure elements have the information that is within the range.
+ *
+ * @param datetime holds the date and time information that needs to be converted to seconds
+ */
+bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime);
+
+/*!
+ * @brief Converts the date time format data structure to seconds.
+ *
+ * @param datetime holds the date and time information that needs to be converted to seconds
+ * @param seconds holds the converted date and time in seconds
+ */
+void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds);
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The function converts the data from the time structure to seconds and writes the seconds
+ * value to the RTC register. The RTC counter is started after setting the time.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param datetime [in] Pointer to structure where the date and time
+ * details to set are stored.
+ */
+void RTC_HAL_SetDatetime(uint32_t rtcBaseAddr, const rtc_datetime_t * datetime);
+
+/*!
+ * @brief Sets the RTC date and time according to the given time provided in seconds.
+ *
+ * The RTC counter is started after setting the time.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param seconds [in] Time in seconds
+ */
+void RTC_HAL_SetDatetimeInsecs(uint32_t rtcBaseAddr, const uint32_t seconds);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * The function reads the value in seconds from the RTC register. It then converts to the
+ * time structure which provides the time in date, hour, minutes and seconds.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param datetime [out] pointer to a structure where the date and time details are
+ * stored.
+ */
+void RTC_HAL_GetDatetime(uint32_t rtcBaseAddr, rtc_datetime_t * datetime);
+
+/*!
+ * @brief Gets the RTC time and returns it in seconds.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param datetime [out] pointer to variable where the RTC time is stored in seconds
+ */
+void RTC_HAL_GetDatetimeInSecs(uint32_t rtcBaseAddr, uint32_t * seconds);
+
+/*!
+ * @brief Reads the value of the time alarm.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param date [out] pointer to a variable where the alarm date and time
+ * details are stored.
+ */
+void RTC_HAL_GetAlarm(uint32_t rtcBaseAddr, rtc_datetime_t * date);
+
+/*!
+ * @brief Sets the RTC alarm time and enables the alarm interrupt.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param date [in] pointer to structure where the alarm date and time
+ * details will be stored at.
+ * @return true: success in setting the RTC alarm\n
+ * false: error in setting the RTC alarm.
+ */
+bool RTC_HAL_SetAlarm(uint32_t rtcBaseAddr, const rtc_datetime_t * date);
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Monotonic Counter*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ * them as a single value.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param counter [out] pointer to variable where the value is stored.
+ */
+void RTC_HAL_GetMonotonicCounter(uint32_t rtcBaseAddr, uint64_t * counter);
+
+/*!
+ * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ * the given single value.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param counter [in] pointer to variable where the value is stored.
+ */
+void RTC_HAL_SetMonotonicCounter(uint32_t rtcBaseAddr, const uint64_t * counter);
+
+/*!
+ * @brief Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: success\n
+ * false: error occurred, either time invalid or monotonic overflow flag was found
+ */
+bool RTC_HAL_IncrementMonotonicCounter(uint32_t rtcBaseAddr);
+#endif
+/*! @}*/
+
+/*!
+ * @name RTC register access functions
+ * @{
+ */
+
+/*!
+ * @brief Reads the value of the time seconds counter.
+ *
+ * The time counter reads as zero if either the SR[TOF] or the SR[TIF] is set.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return contents of the seconds register.
+ */
+static inline uint32_t RTC_HAL_GetSecsReg(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TSR_TSR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes to the time seconds counter.
+ *
+ * When the time counter is enabled, the TSR is read only and increments
+ * once every second provided the SR[TOF] or SR[TIF] is not set. When the time counter
+ * is disabled, the TSR can be read or written. Writing to the TSR when the
+ * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing
+ * to the TSR register with zero is supported, but not recommended, since the TSR
+ * reads as zero when either the SR[TIF] or the SR[TOF] is set (indicating the time is
+ * invalid).
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param seconds [in] seconds value.
+ *
+ */
+static inline void RTC_HAL_SetSecsReg(uint32_t rtcBaseAddr, const uint32_t seconds)
+{
+ HW_RTC_TPR_WR(rtcBaseAddr, (uint32_t)0x00000000U);
+ BW_RTC_TSR_TSR(rtcBaseAddr, seconds);
+}
+
+/*!
+ * @brief Sets the time alarm and clears the time alarm flag.
+ *
+ * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
+ * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR
+ * clears the SR[TAF].
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param seconds [in] alarm value in seconds.
+ */
+static inline void RTC_HAL_SetAlarmReg(uint32_t rtcBaseAddr, const uint32_t seconds)
+{
+ BW_RTC_TAR_TAR(rtcBaseAddr, seconds);
+}
+
+/*!
+ * @brief Gets the time alarm register contents.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return contents of the alarm register.
+ */
+static inline uint32_t RTC_HAL_GetAlarmReg(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TAR_TAR(rtcBaseAddr);
+}
+
+
+/*!
+ * @brief Reads the value of the time prescaler.
+ *
+ * The time counter reads as zero when either the SR[TOF] or the SR[TIF] is set.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return contents of the time prescaler register.
+ */
+static inline uint16_t RTC_HAL_GetPrescaler(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TPR_TPR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Sets the time prescaler.
+ *
+ * When the time counter is enabled, the TPR is read only and increments
+ * every 32.768 kHz clock cycle. When the time counter is disabled, the TPR
+ * can be read or written. The TSR[TSR] increments when bit 14 of the TPR
+ * transitions from a logic one to a logic zero.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param prescale Prescaler value
+ */
+static inline void RTC_HAL_SetPrescaler(uint32_t rtcBaseAddr, const uint16_t prescale)
+{
+ BW_RTC_TPR_TPR(rtcBaseAddr, prescale);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Time Compensation*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Reads the time compensation register contents.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return time compensation register contents.
+ */
+static inline uint32_t RTC_HAL_GetCompensationReg(uint32_t rtcBaseAddr)
+{
+ return HW_RTC_TCR_RD(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes the value to the RTC TCR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param compValue value to be written to the compensation register.
+ */
+static inline void RTC_HAL_SetCompensationReg(uint32_t rtcBaseAddr, const uint32_t compValue)
+{
+ HW_RTC_TCR_WR(rtcBaseAddr, compValue);
+}
+
+/*!
+ * @brief Reads the current value of the compensation interval counter, which is the field CIC in the RTC TCR register.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return compensation interval value.
+ */
+static inline uint8_t RTC_HAL_GetCompensationIntervalCounter(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TCR_CIC(rtcBaseAddr);
+}
+
+/*!
+ * @brief Reads the current value used by the compensation logic for the present second interval.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return time compensation value
+ */
+static inline uint8_t RTC_HAL_GetTimeCompensationValue(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TCR_TCV(rtcBaseAddr);
+}
+
+/*!
+ * @brief Reads the compensation interval register.
+
+ * The value is the configured compensation interval in seconds from 1 to 256 to control
+ * how frequently the time compensation register should adjust the
+ * number of 32.768 kHz cycles in each second. The value is one
+ * less than the number of seconds (for example, zero means a
+ * configuration for a compensation interval of one second).
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return compensation interval in seconds.
+ */
+static inline uint8_t RTC_HAL_GetCompensationIntervalRegister(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TCR_CIR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes the compensation interval.
+ *
+ * This configures the compensation interval in seconds from 1 to 256 to control
+ * how frequently the TCR should adjust the number of 32.768 kHz
+ * cycles in each second. The value written should be one less than
+ * the number of seconds (for example, write zero to configure for
+ * a compensation interval of one second). This register is double
+ * buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param value the compensation interval value.
+ */
+static inline void RTC_HAL_SetCompensationIntervalRegister(uint32_t rtcBaseAddr, const uint8_t value)
+{
+ BW_RTC_TCR_CIR(rtcBaseAddr, value);
+}
+
+/*!
+ * @brief Reads the time compensation value which is the configured number
+ * of 32.768 kHz clock cycles in each second.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return time compensation value.
+ */
+static inline uint8_t RTC_HAL_GetTimeCompensationRegister(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_TCR_TCR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes to the field Time Compensation Register (TCR) of the RTC Time Compensation Register (RTC_TCR).
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This register is double
+ * buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ * 80h Time prescaler register overflows every 32896 clock cycles.
+ * .. ...\n
+ * FFh Time prescaler register overflows every 32769 clock cycles.\n
+ * 00h Time prescaler register overflows every 32768 clock cycles.\n
+ * 01h Time prescaler register overflows every 32767 clock cycles.\n
+ * ... ...\n
+ * 7Fh Time prescaler register overflows every 32641 clock cycles.\n
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param comp_value value of the time compensation.
+ */
+static inline void RTC_HAL_SetTimeCompensationRegister(uint32_t rtcBaseAddr, const uint8_t compValue)
+{
+ BW_RTC_TCR_TCR(rtcBaseAddr, compValue);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Control*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Enables/disables the oscillator configuration for the 2pF load.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables load\n
+ * false: disables load.
+ */
+static inline void RTC_HAL_SetOsc2pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_SC2P(rtcBaseAddr, enable);
+}
+
+/*!
+ * @brief Reads the oscillator 2pF load configure bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 2pF additional load enabled.\n
+ * false: 2pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc2pfLoad(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SC2P(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the oscillator configuration for the 4pF load.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables load.\n
+ * false: disables load
+ */
+static inline void RTC_HAL_SetOsc4pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_SC4P(rtcBaseAddr, enable);
+}
+
+/*!
+ * @brief Reads the oscillator 4pF load configure bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 4pF additional load enabled.\n
+ * false: 4pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc4pfLoad(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SC4P(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the oscillator configuration for the 8pF load.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables load.\n
+ * false: disables load.
+ */
+static inline void RTC_HAL_SetOsc8pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_SC8P(rtcBaseAddr, enable);
+}
+
+/*!
+ * @brief Reads the oscillator 8pF load configure bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 8pF additional load enabled.\n
+ * false: 8pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc8pfLoad(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SC8P(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the oscillator configuration for the 16pF load.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables load.\n
+ * false: disables load.
+ */
+static inline void RTC_HAL_SetOsc16pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_SC16P(rtcBaseAddr, enable);
+}
+
+/*!
+ * @brief Reads the oscillator 16pF load configure bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 16pF additional load enabled.\n
+ * false: 16pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc16pfLoad(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SC16P(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the 32 kHz clock output to other peripherals.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables clock out.\n
+ * false: disables clock out.
+ */
+static inline void RTC_HAL_SetClockOutCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_CLKO(rtcBaseAddr, !enable);
+}
+
+/*!
+ * @brief Reads the RTC_CR CLKO bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 32 kHz clock is not output to other peripherals.\n
+ * false: 32 kHz clock is output to other peripherals.
+ */
+static inline bool RTC_HAL_GetClockOutCmd(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_CLKO(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the oscillator.
+ *
+ * After enabling, waits for the oscillator startup time before enabling the
+ * time counter to allow the 32.768 kHz clock time to stabilize.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables oscillator.\n
+ * false: disables oscillator.
+ */
+static inline void RTC_HAL_SetOscillatorCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_CR_OSCE(rtcBaseAddr, enable);
+/* TODO: Wait for oscillator startup period if enabling the oscillator
+ if (enable)
+*/
+
+}
+
+/*!
+ * @brief Reads the RTC_CR OSCE bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: 32.768 kHz oscillator is enabled
+ * false: 32.768 kHz oscillator is disabled.
+ */
+static inline bool RTC_HAL_IsOscillatorEnabled(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_OSCE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the update mode.
+ *
+ * This mode allows the time counter enable bit in the SR to be written
+ * even when the status register is locked.
+ * When set, the time counter enable, can always be written if the
+ * TIF (Time Invalid Flag) or TOF (Time Overflow Flag) are set or
+ * if the time counter enable is clear. For devices with the
+ * monotonic counter it allows the monotonic enable to be written
+ * when it is locked. When set, the monotonic enable can always be
+ * written if the TIF (Time Invalid Flag) or TOF (Time Overflow Flag)
+ * are set or if the montonic counter enable is clear.
+ * For devices with tamper detect it allows the it to be written
+ * when it is locked. When set, the tamper detect can always be
+ * written if the TIF (Time Invalid Flag) is clear.
+ * Note: Tamper and Monotonic features are not available in all MCUs.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param lock can be true or false\n
+ * true: registers can be written when locked under limited conditions\n
+ * false: registers cannot be written when locked
+ */
+static inline void RTC_HAL_SetUpdateModeCmd(uint32_t rtcBaseAddr, bool lock)
+{
+ BW_RTC_CR_UM(rtcBaseAddr, lock);
+}
+
+/*!
+ * @brief Reads the RTC_CR update mode bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Registers can be written when locked under limited conditions.
+ * false: Registers cannot be written when locked.
+ */
+static inline bool RTC_HAL_GetUpdateMode(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_UM(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the supervisor access.
+ *
+ * This configures non-supervisor mode write access to all RTC registers and
+ * non-supervisor mode read access to RTC tamper/monotonic registers.
+ * Note: Tamper and Monotonic features are NOT available in all MCUs.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param enableRegWrite can be true or false\n
+ * true: non-supervisor mode write accesses are supported.\n
+ * false: non-supervisor mode write accesses are not supported and generate a bus error.
+ */
+static inline void RTC_HAL_SetSupervisorAccessCmd(uint32_t rtcBaseAddr, bool enableRegWrite)
+{
+ BW_RTC_CR_SUP(rtcBaseAddr, enableRegWrite);
+}
+
+/*!
+ * @brief Reads the RTC_CR SUP bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Non-supervisor mode write accesses are supported
+ * false: Non-supervisor mode write accesses are not supported.
+ */
+static inline bool RTC_HAL_GetSupervisorAccess(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SUP(rtcBaseAddr);
+}
+
+#if FSL_FEATURE_RTC_HAS_WAKEUP_PIN
+/*!
+ * @brief Enables/disables the wakeup pin.
+ *
+ * Note: The wakeup pin is optional and not available on all devices.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable_wp can be true or false\n
+ * true: enables wakeup-pin, wakeup pin asserts if the
+ * RTC interrupt asserts and the chip is powered down.\n
+ * false: disables wakeup-pin.
+ */
+static inline void RTC_HAL_SetWakeupPinCmd(uint32_t rtcBaseAddr, bool enableWp)
+{
+ BW_RTC_CR_WPE(rtcBaseAddr, enableWp);
+}
+
+/*!
+ * @brief Reads the RTC_CR WPE bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Wakeup pin is enabled.
+ * false: Wakeup pin is disabled.
+ */
+static inline bool RTC_HAL_GetWakeupPin(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_WPE(rtcBaseAddr);
+}
+#endif
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
+ * registers. The SWR bit is cleared after VBAT POR and by software
+ * explicitly clearing it.
+ * Note: access control features (RTC_WAR and RTC_RAR registers)
+ * are not available in all MCUs.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_SoftwareReset(uint32_t rtcBaseAddr)
+{
+ BW_RTC_CR_SWR(rtcBaseAddr, 1u);
+}
+
+/*!
+ * @brief Clears the software reset flag.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_SoftwareResetFlagClear(uint32_t rtcBaseAddr)
+{
+ BW_RTC_CR_SWR(rtcBaseAddr, 0u);
+}
+
+/*!
+ * @brief Reads the RTC_CR SWR bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: SWR is set.
+ * false: SWR is cleared.
+ */
+static inline bool RTC_HAL_ReadSoftwareResetStatus(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_CR_SWR(rtcBaseAddr);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Status*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Reads the time counter status (enabled/disabled).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: time counter is enabled, time seconds register and time
+ * prescaler register are not writeable, but increment.\n
+ * false: time counter is disabled, time seconds register and
+ * time prescaler register are writeable, but do not increment.
+ */
+static inline bool RTC_HAL_IsCounterEnabled(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_SR_TCE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the time counter status.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: enables the time counter\n
+ * false: disables the time counter.
+ */
+static inline void RTC_HAL_EnableCounter(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_SR_TCE(rtcBaseAddr, enable);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*!
+ * @brief Reads the value of the Monotonic Overflow Flag (MOF).
+ *
+ * This flag is set when the monotonic counter is enabled and the monotonic
+ * counter high overflows. The monotonic counter does not increment and
+ * reads as zero when this bit is set. This bit is cleared by writing the monotonic
+ * counter high register when the monotonic counter is disabled.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return true: monotonic counter overflow has occurred and monotonic
+ * counter is read as zero.\n
+ * false: No monotonic counter overflow has occurred.
+ */
+static inline bool RTC_HAL_IsMonotonicCounterOverflow(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_SR_MOF(rtcBaseAddr);
+}
+#endif
+
+/*!
+ * @brief Checks whether the configured time alarm has occurred.
+ *
+ * Reads time alarm flag (TAF). This flag is set when the time
+ * alarm register (TAR) equals the time seconds register (TSR) and
+ * the TSR increments. This flag is cleared by writing the TAR register.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return true: time alarm has occurred.\n
+ * false: no time alarm occurred.
+ */
+static inline bool RTC_HAL_HasAlarmOccured(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_SR_TAF(rtcBaseAddr);
+}
+
+/*!
+ * @brief Checks whether a counter overflow has occurred.
+ *
+ * Reads the value of RTC Status Register (RTC_SR), field Time
+ * Overflow Flag (TOF). This flag is set when the time counter is
+ * enabled and overflows. The TSR and TPR do not increment and read
+ * as zero when this bit is set. This flag is cleared by writing the
+ * TSR register when the time counter is disabled.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return true: time overflow occurred and time counter is zero.\n
+ * false: no time overflow occurred.
+ */
+static inline bool RTC_HAL_HasCounterOverflowed(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_SR_TOF(rtcBaseAddr);
+}
+
+/*!
+ * @brief Checks whether the time has been marked as invalid.
+ *
+ * Reads the value of RTC Status Register (RTC_SR), field Time
+ * Invalid Flag (TIF). This flag is set on VBAT POR or software
+ * reset. The TSR and TPR do not increment and read as zero when
+ * this bit is set. This flag is cleared by writing the TSR
+ * register when the time counter is disabled.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return true: time is INVALID and time counter is zero.\n
+ * false: time is valid.
+ */
+static inline bool RTC_HAL_IsTimeInvalid(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_SR_TIF(rtcBaseAddr);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Lock*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Configures the register lock to other module fields.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ * @param bitfields [in] configuration flags:\n
+ * Valid bitfields:\n
+ * LRL: Lock Register Lock \n
+ * SRL: Status Register Lock \n
+ * CRL: Control Register Lock \n
+ * TCL: Time Compensation Lock \n
+ *
+ * For MCUs that have the Tamper Detect only: \n
+ * TIL: Tamper Interrupt Lock \n
+ * TTL: Tamper Trim Lock \n
+ * TDL: Tamper Detect Lock \n
+ * TEL: Tamper Enable Lock \n
+ * TTSL: Tamper Time Seconds Lock \n
+ *
+ * For MCUs that have the Monotonic Counter only: \n
+ * MCHL: Monotonic Counter High Lock \n
+ * MCLL: Monotonic Counter Low Lock \n
+ * MEL: Monotonic Enable Lock \n
+ */
+static inline void RTC_HAL_SetLockRegistersCmd(uint32_t rtcBaseAddr, hw_rtc_lr_t bitfields)
+{
+ uint32_t valid_flags = 0;
+
+ valid_flags |= (BM_RTC_LR_LRL | BM_RTC_LR_SRL | BM_RTC_LR_CRL |
+ BM_RTC_LR_TCL);
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+ valid_flags |= (BM_RTC_LR_MCHL | BM_RTC_LR_MCLL | BM_RTC_LR_MEL);
+#endif
+ HW_RTC_LR_WR(rtcBaseAddr, (bitfields.U) & valid_flags);
+}
+
+/*!
+ * @brief Obtains the lock status of the lock register.
+ *
+ * Reads the value of the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: lock register is not locked and writes complete as normal.\n
+ * false: lock register is locked and writes are ignored.
+ */
+static inline bool RTC_HAL_GetLockRegLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_LRL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the lock status of the lock register.
+ *
+ * Writes to the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR).
+ * Once cleared, this can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param lock can be true or false\n
+ * true: Lock register is not locked and writes complete as normal.\n
+ * false: Lock register is locked and writes are ignored.
+ */
+static inline void RTC_HAL_SetLockRegLock(uint32_t rtcBaseAddr, bool lock)
+{
+ BW_RTC_LR_LRL(rtcBaseAddr, (uint32_t) lock);
+}
+
+/*!
+ * @brief Obtains the state of the status register lock.
+ *
+ * Reads the value of field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR), which is the field Status Register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Status register is not locked and writes complete as
+ * normal.\n
+ * false: Status register is locked and writes are ignored.
+ */
+static inline bool RTC_HAL_GetStatusRegLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_SRL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the state of the status register lock.
+ *
+ * Writes to the field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR).
+ * Once cleared, this can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param lock can be true or false\n
+ * true: Status register is not locked and writes complete as
+ * normal.\n
+ * false: Status register is locked and writes are ignored.
+ */
+static inline void RTC_HAL_SetStatusRegLock(uint32_t rtcBaseAddr, bool lock)
+{
+ BW_RTC_LR_SRL(rtcBaseAddr, (uint32_t) lock);
+}
+
+/*!
+ * @brief Obtains the state of the control register lock.
+ *
+ * Reads the field Control Register Lock (CRL)value of the RTC Lock Register (RTC_LR).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Control register is not locked and writes complete as
+ * normal.\n
+ * false: Control register is locked and writes are ignored.
+ */
+static inline bool RTC_HAL_GetControlRegLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_CRL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the state of the control register lock.
+ *
+ * Writes to the field Control Register Lock (CRL) of the RTC Lock Register (RTC_LR).
+ * Once cleared, this can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param lock can be true or false\n
+ * true: Control register is not locked and writes complete
+ * as normal.\n
+ * false: Control register is locked and writes are ignored.
+ */
+static inline void RTC_HAL_SetControlRegLock(uint32_t rtcBaseAddr, bool lock)
+{
+ BW_RTC_LR_CRL(rtcBaseAddr, (uint32_t) lock);
+}
+
+/*!
+ * @brief Obtains the state of the time compensation lock.
+ *
+ * Reads the field Time Compensation Lock (TCL) value of the RTC Lock Register (RTC_LR).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Time compensation register is not locked and writes
+ * complete as normal.\n
+ * false: Time compensation register is locked and writes are
+ * ignored.
+ */
+static inline bool RTC_HAL_GetTimeCompLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_TCL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the state of the time compensation lock.
+ *
+ * Writes to the field Time Compensation Lock (TCL) of the RTC Lock Register (RTC_LR).
+ * Once cleared, this can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param lock can be true or false\n
+ * true: Time compensation register is not locked and writes
+ * complete as normal.\n
+ * false: Time compensation register is locked and writes are
+ * ignored.
+ */
+static inline void RTC_HAL_SetTimeCompLock(uint32_t rtcBaseAddr, bool lock)
+{
+ BW_RTC_LR_TCL(rtcBaseAddr, (uint32_t) lock);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*!
+ * @brief Reads the value of the Monotonic Counter High Lock.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Monotonic counter high register is not locked and writes
+ * complete as normal.\n
+ * false: Monotonic counter high register is locked and writes are
+ * ignored.
+ */
+static inline bool RTC_HAL_ReadMonotonicHcounterLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_MCHL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter High Lock (MCHL) of the RTC Lock Register (RTC_LR).
+ *
+ * Once done, this flag can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicHcounterLock(uint32_t rtcBaseAddr)
+{
+ BW_RTC_LR_MCHL(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the value of the Monotonic Counter Low Lock.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Monotonic counter low register is not locked and writes
+ * complete as normal.\n
+ * false: Monotonic counter low register is locked and writes are
+ * ignored.
+ */
+static inline bool RTC_HAL_ReadMonotonicLcounterLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_MCLL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter Low Lock (MCLL) of the RTC Lock Register (RTC_LR).
+ *
+ * Once done, this flag can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicLcounterLock(uint32_t rtcBaseAddr)
+{
+ BW_RTC_LR_MCLL(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the value of the Monotonic Enable Lock.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Monotonic enable register is not locked and writes
+ * complete as normal.\n
+ * false: Monotonic enable register is locked and writes are
+ * ignored.
+ */
+static inline bool RTC_HAL_ReadMonotonicEnableLock(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_LR_MEL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the Monotonic Enable Lock field of the RTC Lock Register (RTC_LR).
+ *
+ * Once done, this flag can only be set by VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicEnableLock(uint32_t rtcBaseAddr)
+{
+ BW_RTC_LR_MEL(rtcBaseAddr, 0U);
+}
+#endif
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Interrupt Enable*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Checks whether the Time Seconds Interrupt is enabled/disabled.
+ *
+ * Reads the value of field Time Seconds Interrupt Enable (TSIE)of the RTC Interrupt Enable Register (RTC_IER).
+ * The seconds interrupt is an edge-sensitive
+ * interrupt with a dedicated interrupt vector. It is generated once a second
+ * and requires no software overhead (there is no corresponding status flag to
+ * clear).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Seconds interrupt is enabled.\n
+ * false: Seconds interrupt is disabled.
+ */
+static inline bool RTC_HAL_IsSecsIntEnabled(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_IER_TSIE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the Time Seconds Interrupt.
+ *
+ * Writes to the field Time Seconds
+ * Interrupt Enable (TSIE) of the RTC Interrupt Enable Register (RTC_IER).
+ * Note: The seconds interrupt is an edge-sensitive interrupt with a
+ * dedicated interrupt vector. It is generated once a second and
+ * requires no software overhead (there is no corresponding status
+ * flag to clear).
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: Seconds interrupt is enabled.\n
+ * false: Seconds interrupt is disabled.
+ */
+static inline void RTC_HAL_SetSecsIntCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_IER_TSIE(rtcBaseAddr, (uint32_t) enable);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*!
+ * @brief Checks whether the Monotonic Overflow Interrupt is enabled/disabled.
+ *
+ * Reads the value of the RTC Interrupt Enable Register (RTC_IER), field
+ * Monotonic Overflow Interrupt Enable (MOIE).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Monotonic overflow flag does generate an interrupt.\n
+ * false: Monotonic overflow flag does not generate an interrupt.
+ */
+static inline bool RTC_HAL_ReadMonotonicOverflowInt(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_IER_MOIE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the Monotonic Overflow Interrupt Enable.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: Monotonic overflow flag does generate an interrupt.\n
+ * false: Monotonic overflow flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetMonotonicOverflowIntCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_IER_MOIE(rtcBaseAddr, (uint32_t)enable);
+}
+
+#endif
+
+/*!
+ * @brief Checks whether the Time Alarm Interrupt is enabled/disabled.
+ *
+ * Reads the field Time Alarm Interrupt Enable (TAIE) value of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Time alarm flag does generate an interrupt.\n
+ * false: Time alarm flag does not generate an interrupt.
+ */
+static inline bool RTC_HAL_ReadAlarmInt(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_IER_TAIE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the Time Alarm Interrupt.
+ *
+ * Writes to the field Time Alarm
+ * Interrupt Enable (TAIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: Time alarm flag does generate an interrupt.\n
+ * false: Time alarm flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetAlarmIntCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_IER_TAIE(rtcBaseAddr, (uint32_t) enable);
+}
+
+/*!
+ * @brief Checks whether the Time Overflow Interrupt is enabled/disabled.
+ *
+ * Reads the field
+ * Time Overflow Interrupt Enable (TOIE) of the value of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address..
+ *
+ * @return true: Time overflow flag does generate an interrupt.\n
+ * false: Time overflow flag does not generate an interrupt.
+ */
+static inline bool RTC_HAL_ReadTimeOverflowInt(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_IER_TOIE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the Time Overflow Interrupt.
+ *
+ * Writes to the field Time Overflow Interrupt Enable (TOIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: Time overflow flag does generate an interrupt.\n
+ * false: Time overflow flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetTimeOverflowIntCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_IER_TOIE(rtcBaseAddr, (uint32_t) enable);
+}
+
+/*!
+ * @brief Checks whether the Time Invalid Interrupt is enabled/disabled.
+ *
+ * Reads the value of the field Time
+ * Invalid Interrupt Enable (TIIE)of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Time invalid flag does generate an interrupt.\n
+ * false: Time invalid flag does not generate an interrupt.
+ */
+static inline bool RTC_HAL_ReadTimeInvalidInt(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_IER_TIIE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Enables/disables the Time Invalid Interrupt.
+ *
+ * Writes to the field Time Invalid
+ * Interrupt Enable (TIIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable can be true or false\n
+ * true: Time invalid flag does generate an interrupt.\n
+ * false: Time invalid flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetTimeInvalidIntCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ BW_RTC_IER_TIIE(rtcBaseAddr, (uint32_t) enable);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Monotonic Enable*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief Reads the Monotonic Counter Enable bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: This means writing to the monotonic counter increments the counter by one and
+ * the value written is ignored.\n
+ * false: This means writing to the monotonic counter loads the counter with the
+ * value written.
+ */
+static inline bool RTC_HAL_ReadMonotonicEnable(uint32_t rtcBaseAddr)
+{
+ /* Reads value of the RTC_MER register, field Monotonic Counter Enable (MCE). */
+ return (bool)BR_RTC_MER_MCE(rtcBaseAddr);
+}
+
+/*!
+ * @brief Changes the state of Monotonic Counter Enable bit.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param enable value to be written to the MER[MCE] bit\n
+ * true: Set the bit to 1 which means writing to the monotonic counter will increment
+ * the counter by one and the value written will be ignored.\n
+ * false: Set the bit to 0 which means writing to the monotonic counter loads the counter
+ * with the value written.
+ */
+static inline void RTC_HAL_SetMonotonicEnableCmd(uint32_t rtcBaseAddr, bool enable)
+{
+ /* Writes to the RTC_MER registers Monotonic Counter Enable (MCE) bit.*/
+ BW_RTC_MER_MCE(rtcBaseAddr, (uint32_t) enable);
+}
+
+/*!
+ * @brief Reads the values of the Monotonic Counter Low register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return Monotonic Counter Low value.
+ */
+static inline uint32_t RTC_HAL_GetMonotonicCounterLow(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_MCLR_MCL(rtcBaseAddr);
+}
+
+/*!
+ * @brief Reads the values of the Monotonic Counter High register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return Monotonic Counter High value.
+ */
+static inline uint32_t RTC_HAL_GetMonotonicCounterHigh(uint32_t rtcBaseAddr)
+{
+ return BR_RTC_MCHR_MCH(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes values of the Monotonic Counter Low register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param counter [in] Monotonic Counter Low value to be stored.
+ */
+static inline void RTC_HAL_SetMonotonicCounterLow(uint32_t rtcBaseAddr, const uint32_t counter)
+{
+ /* enable writing to the counter*/
+ BW_RTC_MER_MCE(rtcBaseAddr, 0U);
+ BW_RTC_MCLR_MCL(rtcBaseAddr, counter);
+}
+
+/*!
+ * @brief Writes values of the Monotonic Counter High register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ * @param counter [in] Monotonic Counter High value to be stored.
+ */
+static inline void RTC_HAL_SetMonotonicCounterHigh(uint32_t rtcBaseAddr, const uint32_t counter)
+{
+ /* enable writing to the counter*/
+ BW_RTC_MER_MCE(rtcBaseAddr, 0U);
+ BW_RTC_MCHR_MCH(rtcBaseAddr, counter);
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+#if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*!
+ * @brief Reads the field Monotonic Counter High Write (MCHW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the monotonic counter high register will complete as normal.\n
+ * false: Writes to the monotonic counter high register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicHcountWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_MCHW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter High Write (MCHW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicHcountWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_MCHW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Monotonic Counter Low Write (MCLW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the monotonic counter low register will complete as normal.\n
+ * false: Writes to the monotonic counter low register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicLcountWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_MCLW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter High Write (MCLW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by the system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address..
+ */
+static inline void RTC_HAL_ClearMonotonicLcountWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_MCLW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Monotonic Enable Register Write (MERW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the monotonic enable register will complete as normal.\n
+ * false: Writes to the monotonic enable register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicEnableWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_MERW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter High Write (MERW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicEnableWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_MERW(rtcBaseAddr, 0U);
+}
+#endif
+
+/*!
+ * @brief Reads the field Interrupt Enable Register Write (IERW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the interrupt enable register will complete as normal.\n
+ * false: Writes to the interrupt enable register are ignored.
+ */
+static inline bool RTC_HAL_GetIntEnableWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_IERW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Interrupt Enable Register Write (IERW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearIntEnableWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_IERW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Lock Register Write (LRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the lock register will complete as normal.\n
+ * false: Writes to the lock register are ignored.
+ */
+static inline bool RTC_HAL_GetLockWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_LRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Lock Register Write (LRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearLockWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_LRW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Status Register Write (SRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the status register completes as normal.\n
+ * false: Writes to the status register are ignored.
+ */
+static inline bool RTC_HAL_GetStatusWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_SRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Status Register Write (SRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearStatusWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_SRW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Control Register Write (CRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the control register will complete as normal.\n
+ * false: Writes to the control register are ignored.
+ */
+static inline bool RTC_HAL_GetControlWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_CRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Control Register Write (CRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearControlWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_CRW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Compensation Register Write (TCRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the time compensation register will complete as normal.\n
+ * false: Writes to the time compensation register are ignored.
+ */
+static inline bool RTC_HAL_GetCompensationWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_TCRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Compensation Register Write (TCRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearCompensationWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_TCRW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Alarm Register Write (TARW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the time alarm register will complete as normal.\n
+ * false: Writes to the time alarm register are ignored.
+ */
+static inline bool RTC_HAL_GetAlarmWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_TARW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Alarm Register Write (TARW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearAlarmWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_TARW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Prescaler Register Write (TPRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the time prescaler register will complete as normal.\n
+ * false: Writes to the time prescaler register are ignored.
+ */
+static inline bool RTC_HAL_GetPrescalerWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_TPRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Prescaler Register Write (TPRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearPrescalerWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_TPRW(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Seconds Register Write (TSRW) value of the register RTC_WAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Writes to the time seconds register will complete as normal.\n
+ * false: Writes to the time seconds register are ignored.
+ */
+static inline bool RTC_HAL_GetSecsWreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_WAR_TSRW(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Seconds Register Write (TSRW) of the RTC_WAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearSecsWreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_WAR_TSRW(rtcBaseAddr, 0U);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*!
+ * @brief Reads the field Monotonic Counter High Read (MCHR) value of the register RTC_RAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the monotonic counter high register completes as normal.\n
+ * false: Reads to the monotonic counter high register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicHcountRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_MCHR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter High Read (MCHR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicHcountRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_MCHR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Monotonic Counter Low Read (MCLR) value of the register RTC_RAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the monotonic counter low register will complete as normal.\n
+ * false: Reads to the monotonic counter low register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicLcountRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_MCLR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Counter Low Read (MCLR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicLcountRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_MCLR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Monotonic Enable Register Read (MERR) value of the register RTC_RAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the monotonic enable register completes as normal.\n
+ * false: Reads to the monotonic enable register are ignored.
+ */
+static inline bool RTC_HAL_GetMonotonicEnableRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_MERR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Monotonic Enable Register Read (MERR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearMonotonicEnableRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_MERR(rtcBaseAddr, 0U);
+}
+
+#endif
+
+/*!
+ * @brief Reads the field Interrupt Enable Register Read (IERR) value of the register RTC_RAR.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the interrupt enable register completes as normal.\n
+ * false: Reads to the interrupt enable register are ignored.
+ */
+static inline bool RTC_HAL_GetIntEnableRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_IERR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Interrupt Enable Register Read (IERR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearIntEnableRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_IERR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Lock Register Read (LRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the lock register will complete as normal.\n
+ * false: Reads to the lock register are ignored.
+ */
+static inline bool RTC_HAL_GetLockRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_LRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Lock Register Read (LRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearLockRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_LRR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Status Register Read (SRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the status register completes as normal.\n
+ * false: Reads to the status register are ignored.
+ */
+static inline bool RTC_HAL_GetStatusRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_SRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Status Register Read (SRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearStatusRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_SRR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Control Register Read (CRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the control register completes as normal.\n
+ * false: Reads to the control register are ignored.
+ */
+static inline bool RTC_HAL_GetControlRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_CRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Control Register Read (CRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearControlRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_CRR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Compensation Register Read (TCRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the time compensation register completes as normal.\n
+ * false: Reads to the time compensation register are ignored.
+ */
+static inline bool RTC_HAL_GetCompensationRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_TCRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Compensation Register Read (TCRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearCompensationRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_TCRR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Alarm Register Read (TARR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the time alarm register completes as normal.\n
+ * false: Reads to the time alarm register are ignored.
+ */
+static inline bool RTC_HAL_GetAlarmRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_TARR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Alarm Register Read (TARR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearAlarmRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_TARR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Prescaler Register Read (TPRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the time prescaler register completes as normal.\n
+ * false: Reads to the time prescaler register are ignored.
+ */
+static inline bool RTC_HAL_GetPrescalerRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_TPRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Prescaler Register Read (TPRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearPrescalerRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_TPRR(rtcBaseAddr, 0U);
+}
+
+/*!
+ * @brief Reads the field Time Seconds Register Read (TSRR) value of the RTC_RAR register.
+ *
+ * @param rtcBaseAddr The RTC base address
+ *
+ * @return true: Reads to the time seconds register completes as normal.\n
+ * false: Reads to the time seconds register are ignored.
+ */
+static inline bool RTC_HAL_GetSecsRreg(uint32_t rtcBaseAddr)
+{
+ return (bool)BR_RTC_RAR_TSRR(rtcBaseAddr);
+}
+
+/*!
+ * @brief Writes 0 to the field Time Seconds Register Read (TSRR) of the RTC_RAR register.
+ *
+ * Once cleared, this bit is only set by system reset. It is not affected by
+ * VBAT POR or software reset.
+ *
+ * @param rtcBaseAddr The RTC base address
+ */
+static inline void RTC_HAL_ClearSecsRreg(uint32_t rtcBaseAddr)
+{
+ BW_RTC_RAR_TSRR(rtcBaseAddr, 0U);
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_ACCESS_CONTROL */
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/*! @}*/
+
+#endif /* __FSL_RTC_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,168 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_SAI_FEATURES_H__) +#define __FSL_SAI_FEATURES_H__ + +#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ + defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ + defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ + defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \ + defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ + #define FSL_FEATURE_SAI_FIFO_COUNT (8) + /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ + #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) + /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ + #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) + /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) + /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) + /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) + /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ + #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) + /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ + #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) + /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ + #define FSL_FEATURE_SAI_FIFO_COUNT (8) + /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ + #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) + /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ + #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) + /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) + /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) + /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) + /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ + #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) + /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ + #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ + #define FSL_FEATURE_SAI_FIFO_COUNT (8) + /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ + #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) + /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ + #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) + /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) + /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) + /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) + /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ + #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) + /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ + #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ + #define FSL_FEATURE_SAI_FIFO_COUNT (4) + /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ + #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) + /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ + #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) + /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) + /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) + /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) + /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ + #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) + /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ + #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (1) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ + #define FSL_FEATURE_SAI_FIFO_COUNT (1) + /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ + #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) + /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ + #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) + /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) + /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) + /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ + #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) + /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ + #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) + /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ + #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_SAI_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,835 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sai_hal.h"
+
+/******************************************************************************
+*Code
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxInit
+ * Description : Initialize the sai Tx register, just set the register vaule to zero.
+ *This function just clear the register value of sai.
+ *END**************************************************************************/
+void SAI_HAL_TxInit(uint32_t saiBaseAddr)
+{
+ /* Software reset and FIFO reset */
+ BW_I2S_TCSR_SR(saiBaseAddr, 1);
+ BW_I2S_TCSR_FR(saiBaseAddr, 1);
+ /* Clear all registers */
+ HW_I2S_TCSR_WR(saiBaseAddr, 0);
+ HW_I2S_TCR1_WR(saiBaseAddr, 0);
+ HW_I2S_TCR2_WR(saiBaseAddr, 0);
+ HW_I2S_TCR3_WR(saiBaseAddr, 0);
+ HW_I2S_TCR4_WR(saiBaseAddr, 0);
+ HW_I2S_TCR5_WR(saiBaseAddr, 0);
+ HW_I2S_TMR_WR(saiBaseAddr,0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxInit
+ * Description : Initialize the sai Rx register, just set the register vaule to zero.
+ *This function just clear the register value of sai.
+ *END**************************************************************************/
+void SAI_HAL_RxInit(uint32_t saiBaseAddr)
+{
+ /* Software reset and FIFO reset */
+ BW_I2S_RCSR_SR(saiBaseAddr, 1);
+ BW_I2S_RCSR_FR(saiBaseAddr, 1);
+ /* Clear all registers */
+ HW_I2S_RCSR_WR(saiBaseAddr, 0);
+ HW_I2S_RCR1_WR(saiBaseAddr, 0);
+ HW_I2S_RCR2_WR(saiBaseAddr, 0);
+ HW_I2S_RCR3_WR(saiBaseAddr, 0);
+ HW_I2S_RCR4_WR(saiBaseAddr, 0);
+ HW_I2S_RCR5_WR(saiBaseAddr, 0);
+ HW_I2S_RMR_WR(saiBaseAddr,0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetProtocol
+ * Description : According to the protocol type to set the registers for tx.
+ *The protocol can be I2S left, I2S right, I2S and so on.
+ *END**************************************************************************/
+void SAI_HAL_TxSetProtocol(uint32_t saiBaseAddr,sai_protocol_t protocol)
+{
+ switch (protocol)
+ {
+ case kSaiBusI2SLeft:
+ BW_I2S_TCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */
+ BW_I2S_TCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */
+ BW_I2S_TCR4_FSE(saiBaseAddr,0);/*Frame sync not early */
+ BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left channel is high */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusI2SRight:
+ BW_I2S_TCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */
+ BW_I2S_TCR4_MF(saiBaseAddr,1);/* MSB transmitted firsrt */
+ BW_I2S_TCR4_FSE(saiBaseAddr,0);/*Frame sync not early */
+ BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusI2SType:
+ BW_I2S_TCR2_BCP(saiBaseAddr,1);/*Bit clock polarity */
+ BW_I2S_TCR4_MF(saiBaseAddr,1);/*MSB transmitted firsrt */
+ BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_TCR4_FSP(saiBaseAddr,1);/* Frame sync polarity, left channel is low */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusPCMA:
+ BW_I2S_TCR2_BCP(saiBaseAddr,0); /* Bit clock active low */
+ BW_I2S_TCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */
+ BW_I2S_TCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */
+ BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusPCMB:
+ BW_I2S_TCR2_BCP(saiBaseAddr,0); /* Bit clock active high */
+ BW_I2S_TCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */
+ BW_I2S_TCR4_FSE(saiBaseAddr,0);/* Frame sync not early */
+ BW_I2S_TCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */
+ BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusAC97:
+ BW_I2S_TCR2_BCP(saiBaseAddr,1); /* Bit clock active high */
+ BW_I2S_TCR4_MF(saiBaseAddr,1); /* MSB transmitted first */
+ BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,12); /* There are 13 words in a frame in AC'97 */
+ BW_I2S_TCR4_SYWD(saiBaseAddr,15); /* Length of frame sync, 16 bit transmitted in first word */
+ BW_I2S_TCR5_W0W(saiBaseAddr,15); /* The first word have 16 bits */
+ BW_I2S_TCR5_WNW(saiBaseAddr,19); /* Other word is 20 bits */
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetProtocol
+ * Description : According to the protocol type to set the registers for rx.
+ *The protocol can be I2S left, I2S right, I2S and so on.
+ *END**************************************************************************/
+void SAI_HAL_RxSetProtocol(uint32_t saiBaseAddr,sai_protocol_t protocol)
+{
+ switch (protocol)
+ {
+ case kSaiBusI2SLeft:
+ BW_I2S_RCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */
+ BW_I2S_RCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */
+ BW_I2S_RCR4_FSE(saiBaseAddr,0);/*Frame sync one bit early */
+ BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left channel is high */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusI2SRight:
+ BW_I2S_RCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */
+ BW_I2S_RCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */
+ BW_I2S_RCR4_FSE(saiBaseAddr,0);/*Frame sync one bit early */
+ BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusI2SType:
+ BW_I2S_RCR2_BCP(saiBaseAddr,1);/*Bit clock polarity */
+ BW_I2S_RCR4_MF(saiBaseAddr,1);/*MSB transmitted fisrt */
+ BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_RCR4_FSP(saiBaseAddr,1);/* Frame sync polarity, left channel is low */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusPCMA:
+ BW_I2S_RCR2_BCP(saiBaseAddr,0); /* Bit clock active high */
+ BW_I2S_RCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */
+ BW_I2S_RCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */
+ BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusPCMB:
+ BW_I2S_RCR2_BCP(saiBaseAddr,0); /* Bit clock active high */
+ BW_I2S_RCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */
+ BW_I2S_RCR4_FSE(saiBaseAddr,0);/* Frame sync not early */
+ BW_I2S_RCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */
+ BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */
+ break;
+
+ case kSaiBusAC97:
+ BW_I2S_RCR2_BCP(saiBaseAddr,1); /* Bit clock active high */
+ BW_I2S_RCR4_MF(saiBaseAddr,1); /* MSB transmitted first */
+ BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,12); /* There are 13 words in a frame in AC'97 */
+ BW_I2S_RCR4_SYWD(saiBaseAddr,15); /* Length of frame sync, 16 bit transmitted in first word */
+ BW_I2S_RCR5_W0W(saiBaseAddr,15); /* The first word have 16 bits */
+ BW_I2S_RCR5_WNW(saiBaseAddr,19); /* Other word is 20 bits */
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_SetMclkDiv
+ * Description : Set the divider from the clock source to get the master clock.
+ *The function would compute the divider number and set the number to the registers.
+ *END**************************************************************************/
+void SAI_HAL_SetMclkDiv(uint32_t saiBaseAddr, uint32_t mclk, uint32_t src_clk)
+{
+ uint32_t freq = src_clk;
+ uint16_t fract, divide;
+ uint32_t remaind = 0;
+ uint32_t current_remainder = 0xffffffff;
+ uint16_t current_fract = 0;
+ uint16_t current_divide = 0;
+ uint32_t mul_freq = 0;
+ uint32_t max_fract = SAI_FRACT_MAX;
+ /*In order to prevent overflow */
+ freq /= 10;
+ mclk/= 10;
+ max_fract = mclk * SAI_DIV_MAX/freq;
+ if(max_fract > SAI_FRACT_MAX)
+ {
+ max_fract = SAI_FRACT_MAX;
+ }
+ /* Looking for the closet frequency */
+ for (fract = 1; fract < max_fract; fract ++)
+ {
+ mul_freq = freq * fract;
+ remaind = mul_freq % mclk;
+ divide = mul_freq/mclk;
+ /* Find the exactly frequency */
+ if (remaind == 0)
+ {
+ current_fract = fract;
+ current_divide = mul_freq/mclk;
+ break;
+ }
+ /* closer to next one */
+ if (remaind > mclk/2)
+ {
+ remaind = mclk - remaind;
+ divide += 1;
+ }
+ /* Update the closest div and fract */
+ if (remaind < current_remainder)
+ {
+ current_fract = fract;
+ current_divide = divide;
+ current_remainder = remaind;
+ }
+ }
+ BW_I2S_MDR_DIVIDE(saiBaseAddr, current_divide -1);
+ /* Waiting for the divider updated */
+ while(BR_I2S_MCR_DUF(saiBaseAddr))
+ {}
+ BW_I2S_MDR_FRACT(saiBaseAddr, current_fract - 1);
+ /* Waiting for the divider updated */
+ while(BR_I2S_MCR_DUF(saiBaseAddr))
+ {}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetMasterSlave
+ * Description : Set the tx master or slave mode.
+ *The slave or master mode only would affect the clock direction relevant registers.
+ *END**************************************************************************/
+void SAI_HAL_TxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode)
+{
+ if (master_slave_mode == kSaiMaster)
+ {
+ BW_I2S_TCR2_BCD(saiBaseAddr,1);/* Bit clock generated internal */
+ BW_I2S_TCR4_FSD(saiBaseAddr,1);/* Frame sync generated internal */
+ BW_I2S_MCR_MOE(saiBaseAddr,1);/* Master clock generated internal */
+ }
+ else
+ {
+ BW_I2S_TCR2_BCD(saiBaseAddr,0);/* Bit clock generated external */
+ BW_I2S_TCR4_FSD(saiBaseAddr,0);/* Frame sync generated external */
+ BW_I2S_MCR_MOE(saiBaseAddr,0);/* Master clock generated external */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetMasterSlave
+ * Description : Set the rx master or slave mode.
+ *The slave or master mode only would affect the clock direction relevant registers.
+ *END**************************************************************************/
+void SAI_HAL_RxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode)
+{
+ if (master_slave_mode == kSaiMaster)
+ {
+ BW_I2S_RCR2_BCD(saiBaseAddr,1);/* Bit clock generated internal */
+ BW_I2S_RCR4_FSD(saiBaseAddr,1);/* Frame sync generated internal */
+ BW_I2S_MCR_MOE(saiBaseAddr,1);/* Master clock generated internal */
+ }
+ else
+ {
+ BW_I2S_RCR2_BCD(saiBaseAddr,0);/* Bit clock generated external */
+ BW_I2S_RCR4_FSD(saiBaseAddr,0);/* Frame sync generated external */
+ BW_I2S_MCR_MOE(saiBaseAddr,0);/* Master clock generated external */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetSyncMode
+ * Description : Set the tx sync mode.
+ *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx.
+ *END**************************************************************************/
+void SAI_HAL_TxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode)
+{
+ switch (sync_mode)
+ {
+ case kSaiModeAsync:
+ BW_I2S_TCR2_SYNC(saiBaseAddr,0);
+ break;
+ case kSaiModeSync:
+ BW_I2S_TCR2_SYNC(saiBaseAddr,1);
+ BW_I2S_RCR2_SYNC(saiBaseAddr,0);/* Receiver must be async mode */
+ break;
+ case kSaiModeSyncWithOtherTx:
+ BW_I2S_TCR2_SYNC(saiBaseAddr,2);
+ break;
+ case kSaiModeSyncWithOtherRx:
+ BW_I2S_TCR2_SYNC(saiBaseAddr,3);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetSyncMode
+ * Description : Set the rx sync mode.
+ *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx.
+ *END**************************************************************************/
+void SAI_HAL_RxSetSyncMode(uint32_t saiBaseAddr,sai_sync_mode_t sync_mode)
+{
+ switch (sync_mode)
+ {
+ case kSaiModeAsync:
+ BW_I2S_RCR2_SYNC(saiBaseAddr,0);
+ break;
+ case kSaiModeSync:
+ BW_I2S_RCR2_SYNC(saiBaseAddr,1);
+ BW_I2S_TCR2_SYNC(saiBaseAddr,0);/* Receiver must be async mode */
+ break;
+ case kSaiModeSyncWithOtherTx:
+ BW_I2S_RCR2_SYNC(saiBaseAddr,3);
+ break;
+ case kSaiModeSyncWithOtherRx:
+ BW_I2S_RCR2_SYNC(saiBaseAddr,2);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetIntCmd
+ * Description : Enable the interrupt request source for tx.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_TxSetIntCmd(uint32_t saiBaseAddr, sai_interrupt_request_t source, bool enable)
+{
+ switch (source)
+ {
+ case kSaiIntrequestWordStart:
+ BW_I2S_TCSR_WSIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestSyncError:
+ BW_I2S_TCSR_SEIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFOWarning:
+ BW_I2S_TCSR_FWIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFOError:
+ BW_I2S_TCSR_FEIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFORequest:
+ BW_I2S_TCSR_FRIE(saiBaseAddr, enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetIntCmd
+ * Description : Enable the interrupt request source for rx.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_RxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source,bool enable)
+{
+ switch(source)
+ {
+ case kSaiIntrequestWordStart:
+ BW_I2S_RCSR_WSIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestSyncError:
+ BW_I2S_RCSR_SEIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFOWarning:
+ BW_I2S_RCSR_FWIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFOError:
+ BW_I2S_RCSR_FEIE(saiBaseAddr, enable);
+ break;
+ case kSaiIntrequestFIFORequest:
+ BW_I2S_RCSR_FRIE(saiBaseAddr, enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxGetIntCmd
+ * Description : Gets state of tx interrupt source.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+bool SAI_HAL_TxGetIntCmd(uint32_t saiBaseAddr, sai_interrupt_request_t source)
+{
+ bool ret = false;
+ switch (source)
+ {
+ case kSaiIntrequestWordStart:
+ ret = BR_I2S_TCSR_WSIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestSyncError:
+ ret = BR_I2S_TCSR_SEIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFOWarning:
+ ret = BR_I2S_TCSR_FWIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFOError:
+ ret = BR_I2S_TCSR_FEIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFORequest:
+ ret = BR_I2S_TCSR_FRIE(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxGetIntCmd
+ * Description : Gets state of rx interrupt source.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+bool SAI_HAL_RxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source)
+{
+ bool ret = false;
+ switch(source)
+ {
+ case kSaiIntrequestWordStart:
+ ret = BR_I2S_RCSR_WSIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestSyncError:
+ ret = BR_I2S_RCSR_SEIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFOWarning:
+ ret = BR_I2S_RCSR_FWIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFOError:
+ ret = BR_I2S_RCSR_FEIE(saiBaseAddr);
+ break;
+ case kSaiIntrequestFIFORequest:
+ ret= BR_I2S_RCSR_FRIE(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetDmaCmd
+ * Description : Enable the dma request source for tx.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_TxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable)
+{
+ switch (source)
+ {
+ case kSaiDmaReqFIFOWarning:
+ BW_I2S_TCSR_FWDE(saiBaseAddr, enable);
+ break;
+ case kSaiDmaReqFIFORequest:
+ BW_I2S_TCSR_FRDE(saiBaseAddr, enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetDmaCmd
+ * Description : Enable the dma request source for rx.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_RxSetDmaCmd(uint32_t saiBaseAddr,sai_dma_request_t source,bool enable)
+{
+ switch (source)
+ {
+ case kSaiDmaReqFIFOWarning:
+ BW_I2S_RCSR_FWDE(saiBaseAddr,enable);
+ break;
+ case kSaiDmaReqFIFORequest:
+ BW_I2S_RCSR_FRDE(saiBaseAddr,enable);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxGetDmaCmd
+ * Description : Gets state of tx dma request source.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+bool SAI_HAL_TxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source)
+{
+ bool ret = false;
+ switch (source)
+ {
+ case kSaiDmaReqFIFOWarning:
+ ret = BR_I2S_TCSR_FWDE(saiBaseAddr);
+ break;
+ case kSaiDmaReqFIFORequest:
+ ret = BR_I2S_TCSR_FRDE(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxGetDmaCmd
+ * Description : Gets state of rx dma request source.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+bool SAI_HAL_RxGetDmaCmd(uint32_t saiBaseAddr,sai_dma_request_t source)
+{
+ bool ret = false;
+ switch (source)
+ {
+ case kSaiDmaReqFIFOWarning:
+ ret = BR_I2S_RCSR_FWDE(saiBaseAddr);
+ break;
+ case kSaiDmaReqFIFORequest:
+ ret = BR_I2S_RCSR_FRDE(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxClearStateFlag
+ * Description : Clear the state flag of tx registers.
+ *The state flag incudes word start flag, sync error flag and fifo error flag.
+ *END**************************************************************************/
+void SAI_HAL_TxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag)
+{
+ switch (flag)
+ {
+ case kSaiStateFlagWordStart:
+ BW_I2S_TCSR_WSF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagSyncError:
+ BW_I2S_TCSR_SEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagFIFOError:
+ BW_I2S_TCSR_FEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagSoftReset:
+ BW_I2S_TCSR_SR(saiBaseAddr, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxClearStateFlag
+ * Description : Clear the state flag of rx registers.
+ *The state flag incudes word start flag, sync error flag and fifo error flag.
+ *END**************************************************************************/
+void SAI_HAL_RxClearStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag)
+{
+ switch (flag)
+ {
+ case kSaiStateFlagWordStart:
+ BW_I2S_RCSR_WSF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagSyncError:
+ BW_I2S_RCSR_SEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagFIFOError:
+ BW_I2S_RCSR_FEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */
+ break;
+ case kSaiStateFlagSoftReset:
+ BW_I2S_RCSR_SR(saiBaseAddr, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetReset
+ * Description : Reset tx according to reset mode.
+ *The reset mode can be software reset and FIFO reset.
+ *END**************************************************************************/
+void SAI_HAL_TxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type)
+{
+ switch (type)
+ {
+ case kSaiResetTypeSoftware:
+ BW_I2S_TCSR_SR(saiBaseAddr,1);
+ break;
+ case kSaiResetTypeFIFO:
+ BW_I2S_TCSR_FR(saiBaseAddr, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetReset
+ * Description : Reset rx according to reset mode.
+ *The reset mode can be software reset and FIFO reset.
+ *END**************************************************************************/
+void SAI_HAL_RxSetReset(uint32_t saiBaseAddr,sai_reset_type_t type)
+{
+ switch (type)
+ {
+ case kSaiResetTypeSoftware:
+ BW_I2S_RCSR_SR(saiBaseAddr,1);
+ break;
+ case kSaiResetTypeFIFO:
+ BW_I2S_RCSR_FR(saiBaseAddr, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetRunModeCmd
+ * Description : Set the work mode for tx.
+ *The work mode have stop mode, debug mode and normal mode.
+ *END**************************************************************************/
+void SAI_HAL_TxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable)
+{
+ switch (run_mode)
+ {
+ case kSaiRunModeStop:
+ BW_I2S_TCSR_STOPE(saiBaseAddr, enable);/* Stop mode */
+ break;
+ case kSaiRunModeDebug:
+ BW_I2S_TCSR_DBGE(saiBaseAddr, enable);/* Debug mode */
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetRunModeCmd
+ * Description : Set the work mode for rx.
+ *The work mode have stop mode, debug mode and normal mode.
+ *END**************************************************************************/
+void SAI_HAL_RxSetRunModeCmd(uint32_t saiBaseAddr,sai_run_mode_t run_mode,bool enable)
+{
+ switch (run_mode)
+ {
+ case kSaiRunModeStop:
+ BW_I2S_RCSR_STOPE(saiBaseAddr, enable);/* Stop mode */
+ break;
+ case kSaiRunModeDebug:
+ BW_I2S_RCSR_DBGE(saiBaseAddr, enable);/* Debug mode */
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxGetFlagState
+ * Description : Get the state flag value of tx.
+ *The state flag includes fifo error, fifo warning, fifo request, software reset,
+ * sync error and word start.
+ *END**************************************************************************/
+bool SAI_HAL_TxGetStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag)
+{
+ bool ret = false;
+ switch(flag)
+ {
+ case kSaiStateFlagFIFOError:
+ ret = BR_I2S_TCSR_FEF(saiBaseAddr);
+ break;
+ case kSaiStateFlagFIFORequest:
+ ret = BR_I2S_TCSR_FRF(saiBaseAddr);
+ break;
+ case kSaiStateFlagFIFOWarning:
+ ret = BR_I2S_TCSR_FWF(saiBaseAddr);
+ break;
+ case kSaiStateFlagSoftReset:
+ ret = BR_I2S_TCSR_SR(saiBaseAddr);
+ break;
+ case kSaiStateFlagSyncError:
+ ret = BR_I2S_TCSR_SEF(saiBaseAddr);
+ break;
+ case kSaiStateFlagWordStart:
+ ret = BR_I2S_TCSR_WSF(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxGetFlagState
+ * Description : Get the state flag value of rx.
+ *The state flag includes fifo error, fifo warning, fifo request, software reset,
+ * sync error and word start.
+ *END**************************************************************************/
+bool SAI_HAL_RxGetStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag)
+{
+ bool ret = false;
+ switch(flag)
+ {
+ case kSaiStateFlagFIFOError:
+ ret = BR_I2S_RCSR_FEF(saiBaseAddr);
+ break;
+ case kSaiStateFlagFIFORequest:
+ ret = BR_I2S_RCSR_FRF(saiBaseAddr);
+ break;
+ case kSaiStateFlagFIFOWarning:
+ ret = BR_I2S_RCSR_FWF(saiBaseAddr);
+ break;
+ case kSaiStateFlagSoftReset:
+ ret = BR_I2S_RCSR_SR(saiBaseAddr);
+ break;
+ case kSaiStateFlagSyncError:
+ ret = BR_I2S_RCSR_SEF(saiBaseAddr);
+ break;
+ case kSaiStateFlagWordStart:
+ ret = BR_I2S_RCSR_WSF(saiBaseAddr);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_ReceiveDataBlocking
+ * Description : Receive data in blocking way.
+ *The sending would wait until there is vaild data in FIFO for reading.
+ *END**************************************************************************/
+uint32_t SAI_HAL_ReceiveDataBlocking(uint32_t saiBaseAddr,uint32_t rx_channel)
+{
+ assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+ /* Wait while fifo is empty */
+ uint8_t w_ptr = BR_I2S_RFRn_WFP(saiBaseAddr,rx_channel);
+ uint8_t r_ptr = BR_I2S_RFRn_RFP(saiBaseAddr,rx_channel);
+ while(w_ptr == r_ptr)
+ {
+ w_ptr = BR_I2S_RFRn_WFP(saiBaseAddr,rx_channel);
+ r_ptr = BR_I2S_RFRn_RFP(saiBaseAddr,rx_channel);
+ }
+ return BR_I2S_RDRn_RDR(saiBaseAddr,rx_channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_SendDataBlocking
+ * Description : Send data in blocking way.
+ *The sending would wait until there is space for writing.
+ *END**************************************************************************/
+void SAI_HAL_SendDataBlocking(uint32_t saiBaseAddr,uint32_t tx_channel,uint32_t data)
+{
+ assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+ /* Wait while fifo is full */
+ uint8_t w_ptr = BR_I2S_TFRn_WFP(saiBaseAddr,tx_channel);
+ uint8_t r_ptr = BR_I2S_TFRn_RFP(saiBaseAddr,tx_channel);
+ while((w_ptr ^ r_ptr) == 0x8)
+ {
+ w_ptr = BR_I2S_TFRn_WFP(saiBaseAddr,tx_channel);
+ r_ptr = BR_I2S_TFRn_RFP(saiBaseAddr,tx_channel);
+ }
+ BW_I2S_TDRn_TDR(saiBaseAddr, tx_channel, data);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1423 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SAI_HAL_H__
+#define __FSL_SAI_HAL_H__
+
+
+#include <string.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sai_features.h"
+
+
+/*!
+ * @addtogroup sai_hal
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Define the bit limits of in a word*/
+#define SAI_BIT_MIN 8
+#define SAI_BIT_MAX 32
+
+/* Define the max div and fract value for master clock divider. */
+#define SAI_FRACT_MAX 256
+#define SAI_DIV_MAX 4096
+
+/*! @brief Define the bus type of sai */
+typedef enum _sai_protocol
+{
+ kSaiBusI2SLeft = 0x0,
+ kSaiBusI2SRight = 0x1,
+ kSaiBusI2SType = 0x2,
+ kSaiBusPCMA = 0x3,
+ kSaiBusPCMB = 0x4,
+ kSaiBusAC97 = 0x5
+ } sai_protocol_t;
+
+/*! @brief Master or slave mode */
+typedef enum _sai_master_slave
+{
+ kSaiMaster = 0x0,/*!< Master mode */
+ kSaiSlave = 0x1/*!< Slave mode */
+} sai_master_slave_t;
+
+/*! @brief Polarity of SAI clock. */
+typedef enum _sai_clk_polarity
+{
+ kSaiClkPolarityHigh = 0x0, /*!< Clock active high */
+ kSaiClkPolarityLow = 0x1 /*!< Clock active low */
+} sai_clk_polarity_t;
+
+/*! @brief Clock generate direction. */
+typedef enum _sai_clk_direction
+{
+ kSaiClkInternal = 0x0, /*!< Clock generated internal. */
+ kSaiClkExternal = 0x1 /*!< Clock generated external. */
+} sai_clk_direction_t;
+
+/*! @brief Data transfer polarity, means MSB first of LSB first.*/
+typedef enum _sai_data_order
+{
+ kSaiLSBFirst = 0x0, /*!< Least significant bit transferred first. */
+ kSaiMSBFirst = 0x1 /*!< Most significant bit transferred first. */
+} sai_data_order_t;
+
+/*! @brief Synchronous or asynchronous mode */
+typedef enum _sai_sync_mode
+{
+ kSaiModeAsync = 0x0,/*!< Asynchronous mode */
+ kSaiModeSync = 0x1,/*!< Synchronous mode (with receiver or transmit) */
+ kSaiModeSyncWithOtherTx = 0x2,/*!< Synchronous with another SAI transmit */
+ kSaiModeSyncWithOtherRx = 0x3/*!< Synchronous with another SAI receiver */
+} sai_sync_mode_t;
+
+/*! @brief Mater clock source */
+typedef enum _sai_mclk_source
+{
+ kSaiMclkSourceSysclk = 0x0,/*!< Master clock from the system clock */
+ kSaiMclkSourceSelect1 = 0x1,/*!< Master clock from source 1 */
+ kSaiMclkSourceSelect2 = 0x2,/*!< Master clock from source 2 */
+ kSaiMclkSourceSelect3 = 0x3/*!< Master clock from source 3 */
+} sai_mclk_source_t;
+
+/*! @brief Bit clock source */
+typedef enum _sai_bclk_source
+{
+ kSaiBclkSourceBusclk = 0x0,/*!< Bit clock using bus clock */
+ kSaiBclkSourceMclkDiv = 0x1,/*!< Bit clock using master clock divider */
+ kSaiBclkSourceOtherSai0 = 0x2,/*!< Bit clock from other SAI device */
+ kSaiBclkSourceOtherSai1 = 0x3/*!< Bit clock from other SAI device */
+} sai_bclk_source_t;
+
+/*! @brief The SAI state flag. */
+typedef enum _sai_interrupt_request
+{
+ kSaiIntrequestWordStart = 0x0,/*!< Word start flag, means the first word in a frame detected */
+ kSaiIntrequestSyncError = 0x1,/*!< Sync error flag, means the sync error is detected */
+ kSaiIntrequestFIFOWarning = 0x2,/*!< FIFO warning flag, means the FIFO is empty */
+ kSaiIntrequestFIFOError = 0x3,/*!< FIFO error flag */
+ kSaiIntrequestFIFORequest = 0x4/*!< FIFO request, means reached watermark */
+} sai_interrupt_request_t;
+
+
+/*! @brief The DMA request sources */
+typedef enum _sai_dma_request
+{
+ kSaiDmaReqFIFOWarning = 0x0,/*!< FIFO warning caused by the DMA request */
+ kSaiDmaReqFIFORequest = 0x1/*!< FIFO request caused by the DMA request */
+} sai_dma_request_t;
+
+/*! @brief The SAI state flag */
+typedef enum _sai_state_flag
+{
+ kSaiStateFlagWordStart = 0x0,/*!< Word start flag, means the first word in a frame detected. */
+ kSaiStateFlagSyncError = 0x1,/*!< Sync error flag, means the sync error is detected */
+ kSaiStateFlagFIFOError = 0x2,/*!< FIFO error flag */
+ kSaiStateFlagFIFORequest = 0x3,
+ kSaiStateFlagFIFOWarning = 0x4,
+ kSaiStateFlagSoftReset = 0x5 /*!< Software reset flag */
+} sai_state_flag_t;
+
+/*! @brief The reset type */
+typedef enum _sai_reset_type
+{
+ kSaiResetTypeSoftware = 0x0,/*!< Software reset, reset the logic state */
+ kSaiResetTypeFIFO = 0x1/*!< FIFO reset, reset the FIFO read and write pointer */
+} sai_reset_type_t;
+
+/*
+ * @brief The SAI running mode
+ * The mode includes normal mode, debug mode, and stop mode.
+ */
+typedef enum _sai_running_mode
+{
+ kSaiRunModeDebug = 0x0,/*!< In debug mode */
+ kSaiRunModeStop = 0x1/*!< In stop mode */
+} sai_run_mode_t;
+
+#if FSL_FEATURE_SAI_HAS_FIFO_PACKING
+
+/*
+ * @brief The SAI packing mode
+ * The mode includes 8 bit and 16 bit packing.
+ */
+typedef enum _sai_fifo_packing
+{
+ kSaiFifoPackingDisabled = 0x0, /*!< Packing disabled. */
+ kSaiFifoPacking8bit = 0x2,/*!< 8 bit packing enabled. */
+ kSaiFifoPacking16bit = 0x3 /*!< 16bit packing enabled. */
+} sai_fifo_packing_t;
+
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+* @name Module control
+* @{
+*/
+
+/*!
+ * @brief Initializes the SAI Tx.
+ *
+ * The initialization resets the SAI module by setting the SR bit of TCSR register.
+ * Note that the function writes 0 to every control registers.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+void SAI_HAL_TxInit(uint32_t saiBaseAddr);
+
+/*!
+ * @brief Initializes the SAI Rx.
+ *
+ * The initialization resets the SAI module by setting the SR bit of RCSR register.
+ * Note that the function writes 0 to every control registers.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+void SAI_HAL_RxInit(uint32_t saiBaseAddr);
+
+/*!
+ * @brief Sets Tx protocol relevant settings.
+ *
+ * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol
+ * has a different configuration on bit clock and frame sync.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc.
+ */
+void SAI_HAL_TxSetProtocol(uint32_t saiBaseAddr, sai_protocol_t protocol);
+
+/*!
+ * @brief Sets Rx protocol relevant settings.
+ *
+ * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol
+ * has a different configuration on bit clock and frame sync.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc.
+ */
+void SAI_HAL_RxSetProtocol(uint32_t saiBaseAddr, sai_protocol_t protocol);
+
+/*!
+ * @brief Sets master or slave mode.
+ *
+ * The function determines master or slave mode. Master mode provides its
+ * own clock and slave mode uses an external clock.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param master_slave_mode Mater or slave mode.
+ */
+void SAI_HAL_TxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode);
+
+/*!
+ * @brief Sets master or slave mode.
+ *
+ * The function determines master or slave mode. Master mode provides its
+ * own clock and slave mode uses external clock.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param master_slave_mode Mater or slave mode.
+ */
+void SAI_HAL_RxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode);
+
+/*! @}*/
+
+/*!
+* @name Master clock configuration
+* @{
+*/
+
+/*!
+ * @brief Sets the master clock source.
+ *
+ * The source of the clock is different from socs.
+ * This function sets the clock source for SAI master clock source.
+ * Master clock is used to produce the bit clock for the data transfer.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source Mater clock source
+ */
+static inline void SAI_HAL_SetMclkSrc(uint32_t saiBaseAddr, sai_mclk_source_t source)
+{
+ BW_I2S_MCR_MICS(saiBaseAddr,source);
+}
+
+/*!
+ * @brief Gets the master clock source.
+ *
+ * The source of the clock is different from socs.
+ * This function gets the clock source for SAI master clock source.
+ * Master clock is used to produce the bit clock for the data transfer.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @return Mater clock source
+ */
+static inline uint32_t SAI_HAL_GetMclkSrc(uint32_t saiBaseAddr)
+{
+ return BR_I2S_MCR_MICS(saiBaseAddr);
+}
+
+/*!
+ * @brief Sets the direction of the SAI master clock.
+ *
+ * This function would decides the direction of bit clock generated.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_SetMclkDividerCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_MCR_MOE(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Sets the divider of the master clock.
+ *
+ * Using the divider to get the master clock frequency wanted from the source.
+ * mclk = clk_source * fract/divide. The input is the master clock frequency needed and the source clock frequency.
+ * The master clock is decided by the sample rate and the multi-clock number.
+ * Notice that mclk should less than src_clk, or it would do hang as the HW refuses to write in this situation.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param mclk Master clock frequency needed.
+ * @param src_clk The source clock frequency.
+ */
+void SAI_HAL_SetMclkDiv(uint32_t saiBaseAddr, uint32_t mclk, uint32_t src_clk);
+
+/*!
+ * @brief Flag to see if the master clock divider is re-divided.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @return True if the divider updated otherwise false.
+ */
+static inline bool SAI_HAL_GetMclkDivUpdatingCmd(uint32_t saiBaseAddr)
+{
+ return BR_I2S_MCR_DUF(saiBaseAddr);
+}
+
+/*! @}*/
+
+/*!
+* @name Bit clock configuration
+* @{
+*/
+
+/*!
+ * @brief Sets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function sets the source of the bit clock. The bit clock can be produced by the master
+ * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit
+ * clock either from Tx or Rx.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source Bit clock source.
+ */
+static inline void SAI_HAL_TxSetBclkSrc(uint32_t saiBaseAddr, sai_bclk_source_t source)
+{
+ BW_I2S_TCR2_MSEL(saiBaseAddr,source);
+}
+
+/*!
+ * @brief Sets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function sets the source of the bit clock. The bit clock can be produced by the master
+ * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit
+ * clock either from Tx or Rx.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source Bit clock source.
+ */
+static inline void SAI_HAL_RxSetBclkSrc(uint32_t saiBaseAddr, sai_bclk_source_t source)
+{
+ BW_I2S_RCR2_MSEL(saiBaseAddr,source);
+}
+
+/*!
+ * @brief Gets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function gets the source of the bit clock. The bit clock can be produced by the master
+ * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit
+ * clock either from Tx or Rx.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @return Bit clock source.
+ */
+static inline uint32_t SAI_HAL_TxGetBclkSrc(uint32_t saiBaseAddr)
+{
+ return BR_I2S_TCR2_MSEL(saiBaseAddr);
+}
+
+/*!
+ * @brief Gets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function gets the source of the bit clock. The bit clock can be produced by the master
+ * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit
+ * clock either from Tx or Rx.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @return Bit clock source.
+ */
+static inline uint32_t SAI_HAL_RxGetBclkSrc(uint32_t saiBaseAddr)
+{
+ return BR_I2S_RCR2_MSEL(saiBaseAddr);
+}
+
+/*!
+ * @brief Sets the Tx bit clock divider value.
+ *
+ * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means
+ * how much time is needed to transfer one bit.
+ * Notice: The function is called while the bit clock source is the master clock.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param divider The divide number of bit clock.
+ */
+static inline void SAI_HAL_TxSetBclkDiv(uint32_t saiBaseAddr, uint32_t divider)
+{
+ BW_I2S_TCR2_DIV(saiBaseAddr,divider/2 -1);
+}
+
+/*!
+ * @brief Sets the Rx bit clock divider value.
+ *
+ * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means
+ * how much time is needed to transfer one bit.
+ * Notice: The function is called while the bit clock source is the master clock.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param divider The divide number of bit clock.
+ */
+static inline void SAI_HAL_RxSetBclkDiv(uint32_t saiBaseAddr, uint32_t divider)
+{
+ BW_I2S_RCR2_DIV(saiBaseAddr,divider/2 -1);
+}
+
+/*!
+ * @brief Enables or disables the Tx bit clock.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetBclkCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCSR_BCE(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Enables or disables the Rx bit clock.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetBclkCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCSR_BCE(saiBaseAddr, enable);
+}
+
+/*!
+ * @brief Enables or disables the Tx bit clock input bit.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetBclkInputCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCR2_BCI(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Enables or disables the Rx bit clock input bit.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetBclkInputCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCR2_BCI(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Sets the Tx bit clock swap.
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter is configured in
+ * asynchronous mode and this bit is set, the transmitter is clocked by the receiver bit clock.
+ * This allows the transmitter and receiver to share the same bit clock, but the transmitter
+ * continues to use the transmit frame sync (SAI_TX_SYNC).
+ * When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver
+ * BCS field must be set to the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means swap bit closk, false means no swap.
+ */
+static inline void SAI_HAL_TxSetSwapBclkCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCR2_BCS(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Sets the Rx bit clock swap.
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is configured in
+ * asynchronous mode and this bit is set, the receiver is clocked by the transmitter bit clock
+ * (SAI_TX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the
+ * receiver continues to use the receiver frame sync (SAI_RX_SYNC).
+ * When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS
+ * field must be set to the same value. When both are set, the transmitter and receiver are both
+ * clocked by the receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC).
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means swap bit closk, false means no swap.
+ */
+static inline void SAI_HAL_RxSetSwapBclkCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCR2_BCS(saiBaseAddr, enable);
+}
+
+/*!
+ * @brief Sets the direction of the Tx SAI bit clock.
+ *
+ * This function sets the direction of the bit clock generated.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param direction Bit clock generated internal or external.
+ */
+static inline void SAI_HAL_TxSetBclkDir(uint32_t saiBaseAddr, sai_clk_direction_t direction)
+{
+ BW_I2S_TCR2_BCD(saiBaseAddr,direction);
+}
+
+/*!
+ * @brief Sets the direction of the Rx SAI bit clock.
+ *
+ * This function sets the direction of the bit clock generated.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param direction Bit clock generated internal or external.
+ */
+static inline void SAI_HAL_RxSetBclkDir(uint32_t saiBaseAddr, sai_clk_direction_t direction)
+{
+ BW_I2S_RCR2_BCD(saiBaseAddr,direction);
+}
+
+/*!
+ * @brief Sets the polarity of the Tx SAI bit clock.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param pol Polarity of the SAI bit clock, which can be configured to active high or low.
+ */
+static inline void SAI_HAL_TxSetBclkPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol)
+{
+ BW_I2S_TCR2_BCP(saiBaseAddr, pol);
+}
+
+/*!
+ * @brief Sets the polarity of the Rx SAI bit clock.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param pol Polarity of SAI bit clock, which can be configured to active high or low.
+ */
+static inline void SAI_HAL_RxSetBclkPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol)
+{
+ BW_I2S_RCR2_BCP(saiBaseAddr, pol);
+}
+/*! @} */
+
+/*!
+* @name Frame sync configuration
+* @{
+*/
+
+/*!
+ * @brief Sets the Tx frame size.
+ *
+ * The frame size means how many words are in a frame. For example 2-channel
+ * audio data, the frame size is 2, which means 2 words in a frame.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param size Words number in a frame.
+ */
+static inline void SAI_HAL_TxSetFrameSize(uint32_t saiBaseAddr, uint32_t size)
+{
+ BW_I2S_TCR4_FRSZ(saiBaseAddr,size -1);
+}
+
+/*!
+ * @brief Sets the Rx frame size.
+ *
+ * The frame size means how many words are in a frame. For example 2-channel
+ * audio data, the frame size is 2, which means 2 words in a frame.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param size Words number in a frame.
+ */
+static inline void SAI_HAL_RxSetFrameSize(uint32_t saiBaseAddr, uint32_t size)
+{
+ BW_I2S_RCR4_FRSZ(saiBaseAddr,size - 1);
+}
+
+/*!
+ * @brief Gets the Tx frame size.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline uint32_t SAI_HAL_TxGetFrameSize(uint32_t saiBaseAddr)
+{
+ return BR_I2S_TCR4_FRSZ(saiBaseAddr);
+}
+
+/*!
+ * @brief Gets the Tx frame size.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline uint32_t SAI_HAL_RxGetFrameSize(uint32_t saiBaseAddr)
+{
+ return BR_I2S_RCR4_FRSZ(saiBaseAddr);
+}
+
+/*!
+ * @brief Sets the Tx sync width.
+ *
+ * A sync is the number of bit clocks of a frame. The sync width cannot be longer than the
+ * length of the first word of the frame.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param width How many bit clock in a sync.
+ */
+static inline void SAI_HAL_TxSetFrameSyncWidth(uint32_t saiBaseAddr, uint32_t width)
+{
+ BW_I2S_TCR4_SYWD(saiBaseAddr, width -1);
+}
+
+/*!
+ * @brief Sets the Rx sync width.
+ *
+ * A sync is the number of bit clocks of a frame. The sync width cannot be longer than the
+ * length of the first word of the frame.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param width How many bit clock in a sync.
+ */
+static inline void SAI_HAL_RxSetFrameSyncWidth(uint32_t saiBaseAddr, uint32_t width)
+{
+ BW_I2S_RCR4_SYWD(saiBaseAddr, width -1);
+}
+
+/*!
+ * @brief Sets the polarity of the Tx frame sync.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param pol Polarity of sai frame sync, can be configured to active high or low.
+ */
+static inline void SAI_HAL_TxSetFrameSyncPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol)
+{
+ BW_I2S_TCR4_FSP(saiBaseAddr,pol);
+}
+
+/*!
+ * @brief Sets the polarity of the Rx frame sync.
+ *
+ * @param saiBaseAddr Register base address of SAI module..
+ * @param pol Polarity of SAI frame sync, can be configured to active high or low.
+ */
+static inline void SAI_HAL_RxSetFrameSyncPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol)
+{
+ BW_I2S_RCR4_FSP(saiBaseAddr,pol);
+}
+
+/*!
+ * @brief Sets the direction of the SAI Tx frame sync.
+ *
+ * This function sets the direction of frame sync.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param direction Frame sync generated internal or external.
+ */
+static inline void SAI_HAL_TxSetFrameSyncDir(uint32_t saiBaseAddr,sai_clk_direction_t direction)
+{
+ BW_I2S_TCR4_FSD(saiBaseAddr,direction);
+}
+
+/*!
+ * @brief Sets the direction of the SAI Rx frame sync.
+ *
+ * This function sets the direction of frame sync.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param direction Frame sync generated internal or external.
+ */
+static inline void SAI_HAL_RxSetFrameSyncDir(uint32_t saiBaseAddr,sai_clk_direction_t direction)
+{
+ BW_I2S_RCR4_FSD(saiBaseAddr,direction);
+}
+
+/*!
+ * @brief Sets the Tx data transfer order.
+ *
+ * This function sets the data transfer order. It can be set to MSB first or LSB first.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param order MSB transmit first or LSB transmit first.
+ */
+static inline void SAI_HAL_TxSetBitOrder(uint32_t saiBaseAddr, sai_data_order_t order)
+{
+ BW_I2S_TCR4_MF(saiBaseAddr,order);
+}
+
+/*!
+ * @brief Sets the Rx data transfer order.
+ *
+ * This function sets the data transfer order. It can be set to MSB first or LSB first.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param order MSB transmit first or LSB transmit first.
+ */
+static inline void SAI_HAL_RxSetBitOrder(uint32_t saiBaseAddr, sai_data_order_t order)
+{
+ BW_I2S_RCR4_MF(saiBaseAddr,order);
+}
+
+/*!
+ * @brief Tx Frame sync one bit early.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means the frame sync one bit early and false means no early.
+ */
+static inline void SAI_HAL_TxSetFrameSyncEarlyCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCR4_FSE(saiBaseAddr,enable);
+}
+
+/*!
+ * @brief Rx Frame sync one bit early.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means the frame sync one bit early and false means no early.
+ */
+static inline void SAI_HAL_RxSetFrameSyncEarlyCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCR4_FSE(saiBaseAddr,enable);
+}
+
+/*! @} */
+
+/*!
+* @name Word configurations
+* @{
+*/
+
+/*!
+ * @brief Sets the word size for Tx.
+ *
+ * The word size means the quantization level of audio file.
+ * SAI supports the 8 bit, 16 bit, 24 bit, and 32 bit formats.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param bits How many bits in a word.
+*/
+static inline void SAI_HAL_TxSetWordSize(uint32_t saiBaseAddr,uint32_t bits)
+{
+ BW_I2S_TCR5_WNW(saiBaseAddr,bits-1);
+}
+
+/*!
+ * @brief Sets the word size for Rx.
+ *
+ * The word size means the quantization level of audio file.
+ * SAI supports 8 bit, 16 bit, 24 bit, and 32 bit formats.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param bits How many bits in a word.
+*/
+static inline void SAI_HAL_RxSetWordSize(uint32_t saiBaseAddr,uint32_t bits)
+{
+ BW_I2S_RCR5_WNW(saiBaseAddr,bits-1);
+}
+
+/*!
+ * @brief Gets the Tx word size.
+ * @param saiBaseAddr Register base address of SAI module.
+*/
+static inline uint32_t SAI_HAL_TxGetWordSize(uint32_t saiBaseAddr)
+{
+ return BR_I2S_TCR5_WNW(saiBaseAddr);
+}
+
+/*!
+ * @brief Gets the Rx word size.
+ * @param saiBaseAddr Register base address of SAI module.
+*/
+static inline uint32_t SAI_HAL_RxGetWordSize(uint32_t saiBaseAddr)
+{
+ return BR_I2S_RCR5_WNW(saiBaseAddr);
+}
+
+/*!
+ * @brief Sets the size of the first word of the Tx frame .
+ *
+ * In I2S protocol, the size of the first word is the same as the size of other words. In some protocols,
+ * for example, AC'97, the first word is not the same size as others. This function
+ * sets the length of the first word which is, in most situations, the same as others.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param size The length of frame head word.
+ */
+static inline void SAI_HAL_TxSetFirstWordSize(uint32_t saiBaseAddr, uint8_t size)
+{
+ BW_I2S_TCR5_W0W(saiBaseAddr, size-1);
+}
+
+/*!
+ * @brief Sets the size of the first word of Rx frame .
+ *
+ * In I2S protocol, the size of the first word is the same as the size of other words. In some protocols,
+ * for example, AC'97, the first word is not the same size as others. This function
+ * sets the length of the first word which is, in most situations, the same as others.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param size The length of frame head word.
+ */
+static inline void SAI_HAL_RxSetFirstWordSize(uint32_t saiBaseAddr, uint8_t size)
+{
+ BW_I2S_RCR5_W0W(saiBaseAddr, size-1);
+}
+
+/*!
+ * @brief Sets the FIFO index for the first bit data.
+ *
+ * The FIFO is 32-bit in SAI. However, not all audio data is 32-bit, but is mostly 16-bit.
+ * In this situation, the codec needs to know which bit of the FIFO marks the valid audio data.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param index First bit shifted in FIFO.
+ */
+static inline void SAI_HAL_TxSetFirstBitShifted(uint32_t saiBaseAddr, uint32_t index)
+{
+ BW_I2S_TCR5_FBT(saiBaseAddr, index-1);
+}
+
+/*!
+ * @brief Sets the index in FIFO for the first bit data.
+ *
+ * The FIFO is 32-bit in SAI. However, not all audio data is 32-bit, but is mostly 16-bit.
+ * In this situation, the codec needs to know which bit of the FIFO marks the valid audio data.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param index First bit shifted in FIFO.
+ */
+static inline void SAI_HAL_RxSetFirstBitShifted(uint32_t saiBaseAddr, uint32_t index)
+{
+ BW_I2S_RCR5_FBT(saiBaseAddr, index-1);
+}
+
+/*!@}*/
+
+/*!
+* @name watermark settings
+* @{
+*/
+
+/*!
+ * @brief Sets the Tx watermark value.
+ *
+ * While the value in the FIFO is less or equal to the watermark , it generates an interrupt
+ * request or a DMA request. The watermark value cannot be greater than the depth of FIFO.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param watermark Watermark value of a FIFO.
+ */
+static inline void SAI_HAL_TxSetWatermark(uint32_t saiBaseAddr, uint32_t watermark)
+{
+ BW_I2S_TCR1_TFW(saiBaseAddr, watermark);
+}
+
+/*!
+ * @brief Sets the Tx watermark value.
+ *
+ * While the value in the FIFO is more or equal to the watermark , it generates an interrupt
+ * request or a DMA request. The watermark value cannot be greater than the depth of FIFO.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param watermark Watermark value of a FIFO.
+ */
+static inline void SAI_HAL_RxSetWatermark(uint32_t saiBaseAddr, uint32_t watermark)
+{
+ BW_I2S_RCR1_RFW(saiBaseAddr, watermark);
+}
+
+/*!
+ * @brief Gets the Tx watermark value.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline uint32_t SAI_HAL_TxGetWatermark(uint32_t saiBaseAddr)
+{
+ return BR_I2S_TCR1_TFW(saiBaseAddr);
+}
+
+/*!
+ * @brief Gets the Rx watermark value.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline uint32_t SAI_HAL_RxGetWatermark(uint32_t saiBaseAddr)
+{
+ return BR_I2S_RCR1_RFW(saiBaseAddr);
+}
+
+/*! @}*/
+
+/*!
+ * @brief SAI Tx sync mode setting.
+ *
+ * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device.
+ * When configured for a synchronous mode of operation, the receiver must be configured for the
+ * asynchronous operation.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param sync_mode Synchronous mode or Asynchronous mode.
+ */
+void SAI_HAL_TxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode);
+
+/*!
+ * @brief SAI Rx sync mode setting.
+ *
+ * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device.
+ * When configured for a synchronous mode of operation, the receiver must be configured for the
+ * asynchronous operation.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param sync_mode Synchronous mode or Asynchronous mode.
+ */
+void SAI_HAL_RxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode);
+
+/*!
+ * @brief Gets the Tx FIFO read pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return FIFO read pointer value.
+ */
+static inline uint8_t SAI_HAL_TxGetFifoReadPointer(uint32_t saiBaseAddr, uint32_t fifo_channel)
+{
+ return BR_I2S_TFRn_RFP(saiBaseAddr,fifo_channel);
+}
+
+/*!
+ * @brief Gets the Rx FIFO read pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return FIFO read pointer value.
+ */
+static inline uint8_t SAI_HAL_RxGetFifoReadPointer(uint32_t saiBaseAddr, uint32_t fifo_channel)
+{
+ return BR_I2S_RFRn_RFP(saiBaseAddr,fifo_channel);
+}
+
+/*!
+ * @brief Gets the Tx FIFO write pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return FIFO read pointer value.
+ */
+static inline uint8_t SAI_HAL_TxGetFifoWritePointer(uint32_t saiBaseAddr,uint32_t fifo_channel)
+{
+ return BR_I2S_TFRn_WFP(saiBaseAddr,fifo_channel);
+}
+
+/*!
+ * @brief Gets the Rx FIFO write pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return FIFO read pointer value.
+ */
+static inline uint8_t SAI_HAL_RxGetFifoWritePointer(uint32_t saiBaseAddr,uint32_t fifo_channel)
+{
+ return BR_I2S_RFRn_WFP(saiBaseAddr,fifo_channel);
+}
+
+/*!
+ * @brief Gets the TDR register address.
+ *
+ * This function determines the dest/src address of the DMA transfer.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return TDR register or RDR register address
+ */
+static inline uint32_t* SAI_HAL_TxGetFifoAddr(uint32_t saiBaseAddr, uint32_t fifo_channel)
+{
+ return (uint32_t *)HW_I2S_TDRn_ADDR(saiBaseAddr, fifo_channel);
+}
+
+/*!
+ * @brief Gets the RDR register address.
+ *
+ * This function determines the dest/src address of the DMA transfer.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return TDR register or RDR register address
+ */
+static inline uint32_t* SAI_HAL_RxGetFifoAddr(uint32_t saiBaseAddr, uint32_t fifo_channel)
+{
+ return (uint32_t *)HW_I2S_RDRn_ADDR(saiBaseAddr, fifo_channel);
+}
+
+/*!
+ * @brief Enables the SAI Tx module.
+ *
+ * Enables the Tx. This function enables both the bit clock and the transfer channel.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline void SAI_HAL_TxEnable(uint32_t saiBaseAddr)
+{
+ BW_I2S_TCSR_BCE(saiBaseAddr,true);
+ BW_I2S_TCSR_TE(saiBaseAddr,true);
+}
+
+/*!
+ * @brief Enables the SAI Rx module.
+ *
+ * Enables the Rx. This function enables both the bit clock and the receive channel.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline void SAI_HAL_RxEnable(uint32_t saiBaseAddr)
+{
+ BW_I2S_RCSR_BCE(saiBaseAddr,true);
+ BW_I2S_RCSR_RE(saiBaseAddr,true);
+}
+
+/*!
+ * @brief Disables the Tx module.
+ *
+ * Disables the Tx. This function disables both the bit clock and the transfer channel.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline void SAI_HAL_TxDisable(uint32_t saiBaseAddr)
+{
+ BW_I2S_TCSR_TE(saiBaseAddr,false);
+ BW_I2S_TCSR_BCE(saiBaseAddr,false);
+}
+
+/*!
+ * @brief Disables the Rx module.
+ *
+ * Disables the Rx. This function disables both the bit clock and the receive channel.
+ * @param saiBaseAddr Register base address of SAI module.
+ */
+static inline void SAI_HAL_RxDisable(uint32_t saiBaseAddr)
+{
+ BW_I2S_RCSR_RE(saiBaseAddr,false);
+ BW_I2S_RCSR_BCE(saiBaseAddr,false);
+}
+
+/*!
+ * @brief Enables the Tx interrupt from different interrupt sources.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_TxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source, bool enable);
+
+/*!
+ * @brief Enables the Rx interrupt from different interrupt sources.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_RxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source, bool enable);
+
+/*!
+ * @brief Gets the status as to whether the Tx interrupt source is enabled.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @return Enabled or disabled.
+ */
+bool SAI_HAL_TxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source);
+
+/*!
+ * @brief Gets the status as to whether the Rx interrupt source is enabled.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @return Enabled or disabled.
+ */
+bool SAI_HAL_RxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source);
+
+/*!
+ * @brief Enables the Tx DMA request from different sources.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_TxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable);
+
+/*!
+ * @brief Enables the Rx DMA request from different sources.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_RxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable);
+
+/*!
+ * @brief Gets the status whether the Tx DMA source is enabled.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @param Enable or disable.
+ */
+bool SAI_HAL_TxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source);
+
+/*!
+ * @brief Gets the status whether the Rx DMA source is enabled.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @return Enable or disable.
+ */
+bool SAI_HAL_RxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source);
+
+/*!
+ * @brief Clears the Tx state flags.
+ *
+ * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error,
+ * FIFO request flag.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning.
+ */
+void SAI_HAL_TxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag);
+
+/*!
+ * @brief Clears the Rx state flags.
+ *
+ * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error,
+ * FIFO request flag.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning.
+ */
+void SAI_HAL_RxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag);
+
+/*!
+ * @brief Resets the Tx module.
+ *
+ * There are two kinds of resets: Software reset and FIFO reset.
+ * Software reset: resets all transmitter internal logic, including the bit clock generation,
+ * status flags and FIFO pointers. It does not reset the configuration registers.
+ * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer.
+ * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set,
+ * and before the FIFO is re-initialized and the Error Flag is cleared.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param type SAI reset type.
+ */
+void SAI_HAL_TxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type);
+
+/*!
+ * @brief Resets the Rx module.
+ *
+ * There are two kinds of resets: Software reset and FIFO reset.
+ * Software reset: resets all transmitter internal logic, including the bit clock generation,
+ * status flags and FIFO pointers. It does not reset the configuration registers.
+ * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer.
+ * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set,
+ * and before the FIFO is re-initialized and the Error Flag is cleared.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param type SAI reset type.
+ */
+void SAI_HAL_RxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type);
+
+/*!
+ * @brief Sets the Tx mask word of the frame.
+ *
+ * Each bit number represent the mask word index. For example, 0 represents mask the 0th word, 3
+ * represents mask 0th and 1st word. The TMR register can be different from frame to frame. If the
+ * user wants a mono audio, set the mask to 0/1.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param mask Which bits need to be masked in a frame.
+ */
+static inline void SAI_HAL_TxSetWordMask(uint32_t saiBaseAddr, uint32_t mask)
+{
+ BW_I2S_TMR_TWM(saiBaseAddr, mask);
+}
+
+/*!
+ * @brief Sets the Rx mask word of the frame.
+ *
+ * Each bit number represent the mask word index. For example, 0 represents mask the 0th word, 3
+ * represents mask 0th and 1st word. The TMR register can be different from frame to frame. If the
+ * user wants a mono audio, set the mask to 0/1.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param mask Which bits need to be masked in a frame.
+ */
+static inline void SAI_HAL_RxSetWordMask(uint32_t saiBaseAddr, uint32_t mask)
+{
+ BW_I2S_RMR_RWM(saiBaseAddr, mask);
+}
+
+/*!
+ * @brief Sets the Tx FIFO channel.
+ *
+ * A SAI saiBaseAddr includes a Tx and an Rx. Each has several channels according to
+ * different platforms. A channel means a path for the audio data input/output.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel number.
+ */
+static inline void SAI_HAL_TxSetDataChn(uint32_t saiBaseAddr, uint8_t fifo_channel)
+{
+ BW_I2S_TCR3_TCE(saiBaseAddr, 1u << fifo_channel);
+}
+
+/*!
+ * @brief Sets the Rx FIFO channel.
+ *
+ * A SAI saiBaseAddr includes a Tx and a Rx. Each has several channels according to
+ * different platforms. A channel means a path for the audio data input/output.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param fifo_channel FIFO channel number.
+ */
+static inline void SAI_HAL_RxSetDataChn(uint32_t saiBaseAddr, uint8_t fifo_channel)
+{
+ BW_I2S_RCR3_RCE(saiBaseAddr, 1u << fifo_channel);
+}
+
+/*!
+ * @brief Sets the running mode of the Tx. There is a debug mode, stop mode, and a normal mode.
+ *
+ * This function can set the working mode of the SAI saiBaseAddr. Stop mode is always
+ * used in low power cases, and the debug mode disables the SAI after the current
+ * transmit/receive is completed.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param run_mode SAI running mode.
+ * @param enable Enable or disable a mode.
+ */
+void SAI_HAL_TxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable);
+
+/*!
+ * @brief Sets the running mode of the Rx. There is a debug mode, stop mode, and a normal mode.
+ *
+ * This function can set the working mode of the SAI saiBaseAddr. Stop mode is always
+ * used in low power cases, and the debug mode disables the SAI after the current
+ * transmit/receive is completed.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param run_mode SAI running mode.
+ * @param enable Enable or disable a mode.
+ */
+void SAI_HAL_RxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable);
+
+/*!
+ * @brief Configures at which word the start of word flag is set in the Tx.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param index Which word triggers word start flag.
+ */
+static inline void SAI_HAL_TxSetWordStartIndex(uint32_t saiBaseAddr,uint32_t index)
+{
+ assert(index <= FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME);
+ BW_I2S_TCR3_WDFL(saiBaseAddr, index -1);
+}
+
+/*!
+ * @brief Configures at which word the start of word flag is set in the Tx.
+ *
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param index Which word triggers word start flag.
+ */
+static inline void SAI_HAL_RxSetWordStartIndex(uint32_t saiBaseAddr,uint32_t index)
+{
+ assert(index <= FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME);
+ BW_I2S_RCR3_WDFL(saiBaseAddr, index -1);
+}
+
+/*!
+ * @brief Gets the state of the flags in the TCSR.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param flag State flag type, it can be FIFO error, FIFO warning and so on.
+ * @return True if detect word start otherwise false.
+ */
+bool SAI_HAL_TxGetStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag);
+
+/*!
+ * @brief Gets the state of the flags in the RCSR.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param flag State flag type, it can be FIFO error, FIFO warning and so on.
+ * @return True if detect word start otherwise false.
+ */
+bool SAI_HAL_RxGetStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag);
+
+/*!
+ * @brief Receives the data from the FIFO.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param rx_channel Rx FIFO channel.
+ * @param data Pointer to the address to be written in.
+ */
+static inline uint32_t SAI_HAL_ReceiveData(uint32_t saiBaseAddr, uint32_t rx_channel)
+{
+ assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+ return HW_I2S_RDRn_RD(saiBaseAddr, rx_channel);
+}
+
+/*!
+ * @brief Transmits data to the FIFO.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param tx_channel Tx FIFO channel.
+ * @param data Data value which needs to be written into FIFO.
+ */
+static inline void SAI_HAL_SendData(uint32_t saiBaseAddr, uint32_t tx_channel, uint32_t data)
+{
+ assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+ HW_I2S_TDRn_WR(saiBaseAddr,tx_channel,data);
+}
+
+/*!
+* @brief Uses blocking to receive data.
+* @param saiBaseAddr The SAI saiBaseAddr.
+* @param rx_channel Rx FIFO channel.
+* @return Received data.
+*/
+uint32_t SAI_HAL_ReceiveDataBlocking(uint32_t saiBaseAddr, uint32_t rx_channel);
+
+/*!
+* @brief Uses blocking to send data.
+* @param saiBaseAddr The SAI saiBaseAddr.
+* @param tx_channel Tx FIFO channel.
+* @param data Data value which needs to be written into FIFO.
+*/
+void SAI_HAL_SendDataBlocking(uint32_t saiBaseAddr, uint32_t tx_channel, uint32_t data);
+
+#if FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+/*!
+ * @brief Tx on-demand mode setting.
+ *
+ * When set, the frame sync is generated internally. A frame sync is only generated when the
+ * FIFO warning flag is clear.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetOndemandCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCR4_ONDEM(saiBaseAddr, enable);
+}
+
+/*!
+ * @brief Rx on-demand mode setting.
+ *
+ * When set, the frame sync is generated internally. A frame sync is only generated when the
+ * FIFO warning flag is clear.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetOndemandCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCR4_ONDEM(saiBaseAddr, enable);
+}
+#endif
+
+#if FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+/*!
+ * @brief Tx FIFO continues on error.
+ *
+ * Configures when the SAI continues transmitting after a FIFO error has been detected.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetFIFOErrorContinueCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_TCR4_FCONT(saiBaseAddr, enable);
+}
+
+/*!
+ * @brief Rx FIFO continues on error.
+ *
+ * Configures when the SAI continues transmitting after a FIFO error has been detected.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetFIFOErrorContinueCmd(uint32_t saiBaseAddr, bool enable)
+{
+ BW_I2S_RCR4_FCONT(saiBaseAddr, enable);
+}
+#endif
+
+#if FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * @brief Tx FIFO packing mode setting.
+ *
+ * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is
+ * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO.
+ * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted
+ * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write
+ * pointer only increments when the full 32-bit FIFO word has been written by software.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param mode FIFO packing mode.
+ */
+static inline void SAI_HAL_TxSetFIFOPackingMode(uint32_t saiBaseAddr, sai_fifo_packing_t mode)
+{
+ BW_I2S_TCR4_FPACK(saiBaseAddr,mode);
+}
+
+/*!
+ * @brief Rx FIFO packing mode setting.
+ *
+ * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is
+ * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO.
+ * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted
+ * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write
+ * pointer only increments when the full 32-bit FIFO word has been written by software.
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param mode FIFO packing mode.
+ */
+static inline void SAI_HAL_RxSetFIFOPackingMode(uint32_t saiBaseAddr, sai_fifo_packing_t mode)
+{
+ BW_I2S_RCR4_FPACK(saiBaseAddr,mode);
+}
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_SAI_HAL_H__ */
+/*******************************************************************************
+* EOF
+*******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,84 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140519 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_SDHC_FEATURES_H__) +#define __FSL_SDHC_FEATURES_H__ + +#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) + /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ + #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) + /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ + #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) + /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ + #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ + #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) + /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ + #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) + /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ + #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ + #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) + /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ + #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (1) + /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ + #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (1) +#else + #define MBED_NO_SDHC +#endif + +#endif /* __FSL_SDHC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_sdhc_hal.h"
+
+#ifndef MBED_NO_SDHC
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_Init
+ * Description: Initialize sdhc hal
+ *
+ *END*********************************************************************/
+void SDHC_HAL_Init(uint32_t baseAddr)
+{
+ SDHC_HAL_SetSdClock(baseAddr, false);
+ SDHC_HAL_SetExternalDmaRequest(baseAddr, false);
+ SDHC_HAL_SetIntState(baseAddr, false, (uint32_t)-1);
+ SDHC_HAL_SetIntSignal(baseAddr, false, (uint32_t)-1);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_SetIntSignal
+ * Description: Enable specified interrupts
+ *
+ *END*********************************************************************/
+void SDHC_HAL_SetIntSignal(uint32_t baseAddr, bool enable, uint32_t mask)
+{
+ if (enable)
+ {
+ HW_SDHC_IRQSIGEN_SET(baseAddr, mask);
+ }
+ else
+ {
+ HW_SDHC_IRQSIGEN_CLR(baseAddr, mask);
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_SetIntState
+ * Description: Enable specified interrupts' state
+ *
+ *END*********************************************************************/
+void SDHC_HAL_SetIntState(uint32_t baseAddr, bool enable, uint32_t mask)
+{
+ if (enable)
+ {
+ HW_SDHC_IRQSTATEN_SET(baseAddr, mask);
+ }
+ else
+ {
+ HW_SDHC_IRQSTATEN_CLR(baseAddr, mask);
+ }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetResponse
+ * Description: get command response
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_GetResponse(uint32_t baseAddr, uint32_t index)
+{
+ uint32_t ret = 0;
+
+ assert(index < 4);
+
+ switch(index)
+ {
+ case 0:
+ ret = BR_SDHC_CMDRSP0_CMDRSP0(baseAddr);
+ break;
+ case 1:
+ ret = BR_SDHC_CMDRSP1_CMDRSP1(baseAddr);
+ break;
+ case 2:
+ ret = BR_SDHC_CMDRSP2_CMDRSP2(baseAddr);
+ break;
+ case 3:
+ ret = BR_SDHC_CMDRSP3_CMDRSP3(baseAddr);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_InitCard
+ * Description: Initialize card by sending 80 clocks to card
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_InitCard(uint32_t baseAddr, uint32_t timeout)
+{
+ assert(timeout);
+ BW_SDHC_SYSCTL_INITA(baseAddr, 1);
+ while((!BR_SDHC_SYSCTL_INITA(baseAddr)))
+ {
+ if (!timeout)
+ {
+ break;
+ }
+ timeout--;
+ }
+ return (!timeout);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_Reset
+ * Description: Perform different kinds of reset
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout)
+{
+ uint32_t mask;
+ assert(timeout);
+ mask = type & (BM_SDHC_SYSCTL_RSTA
+ | BM_SDHC_SYSCTL_RSTC
+ | BM_SDHC_SYSCTL_RSTD);
+ HW_SDHC_SYSCTL_SET(baseAddr, mask);
+ while (!(HW_SDHC_SYSCTL_RD(baseAddr) & mask))
+ {
+ if (!timeout)
+ {
+ break;
+ }
+ timeout--;
+ }
+ return (!timeout);
+}
+
+#endif /* MBED_NO_SDHC */
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1236 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_SDHC_HAL_H__
+#define __FSL_SDHC_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sdhc_features.h"
+
+#ifndef MBED_NO_SDHC
+
+/*! @addtogroup sdhc_hal */
+/*! @{ */
+
+/* PRSSTA */
+#define SDHC_HAL_DAT0_LEVEL (BM_SDHC_PRSSTAT_DLSL & (1 << 24))
+
+/* XFERTYP */
+#define SDHC_HAL_MAX_BLOCK_COUNT ((1 << BS_SDHC_BLKATTR_BLKCNT) - 1)
+#define SDHC_HAL_ENABLE_DMA BM_SDHC_XFERTYP_DMAEN
+
+#define SDHC_HAL_CMD_TYPE_SUSPEND (BF_SDHC_XFERTYP_CMDTYP(1))
+#define SDHC_HAL_CMD_TYPE_RESUME (BF_SDHC_XFERTYP_CMDTYP(2))
+#define SDHC_HAL_CMD_TYPE_ABORT (BF_SDHC_XFERTYP_CMDTYP(3))
+
+#define SDHC_HAL_ENABLE_BLOCK_COUNT BM_SDHC_XFERTYP_BCEN
+#define SDHC_HAL_ENABLE_AUTO_CMD12 BM_SDHC_XFERTYP_AC12EN
+#define SDHC_HAL_ENABLE_DATA_READ BM_SDHC_XFERTYP_DTDSEL
+#define SDHC_HAL_MULTIPLE_BLOCK BM_SDHC_XFERTYP_MSBSEL
+
+#define SDHC_HAL_RESP_LEN_136 ((0x1 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
+#define SDHC_HAL_RESP_LEN_48 ((0x2 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
+#define SDHC_HAL_RESP_LEN_48_BC ((0x3 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
+
+#define SDHC_HAL_ENABLE_CRC_CHECK BM_SDHC_XFERTYP_CCCEN
+#define SDHC_HAL_ENABLE_INDEX_CHECK BM_SDHC_XFERTYP_CICEN
+#define SDHC_HAL_DATA_PRESENT BM_SDHC_XFERTYP_DPSEL
+
+/* SYSCTL */
+#define SDHC_HAL_MAX_DVS (16U)
+#define SDHC_HAL_INITIAL_DVS (1U) /* initial value of divisor to calculate clock rate */
+#define SDHC_HAL_INITIAL_CLKFS (2U) /* initial value of clock selector to calculate clock rate */
+#define SDHC_HAL_NEXT_DVS(x) do { ((x) += 1); } while(0)
+#define SDHC_HAL_PREV_DVS(x) do { ((x) -= 1); } while(0)
+#define SDHC_HAL_MAX_CLKFS (256U)
+#define SDHC_HAL_NEXT_CLKFS(x) do { ((x) <<= 1); } while(0)
+#define SDHC_HAL_PREV_CLKFS(x) do { ((x) >>= 1); } while(0)
+
+/* IRQSTAT */
+#define SDHC_HAL_CMD_COMPLETE_INT BM_SDHC_IRQSTAT_CC
+#define SDHC_HAL_DATA_COMPLETE_INT BM_SDHC_IRQSTAT_TC
+#define SDHC_HAL_BLOCK_GAP_EVENT_INT BM_SDHC_IRQSTAT_BGE
+#define SDHC_HAL_DMA_INT BM_SDHC_IRQSTAT_DINT
+#define SDHC_HAL_DMA_ERR_INT BM_SDHC_IRQSTAT_DMAE
+#define SDHC_HAL_BUF_WRITE_READY_INT BM_SDHC_IRQSTAT_BWR
+#define SDHC_HAL_BUF_READ_READY_INT BM_SDHC_IRQSTAT_BRR
+#define SDHC_HAL_CARD_INSERTION_INT BM_SDHC_IRQSTAT_CINS
+#define SDHC_HAL_CARD_REMOVAL_INT BM_SDHC_IRQSTAT_CRM
+#define SDHC_HAL_CARD_INT BM_SDHC_IRQSTAT_CINT
+#define SDHC_HAL_CMD_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_CTOE
+#define SDHC_HAL_CMD_CRC_ERR_INT BM_SDHC_IRQSTAT_CCE
+#define SDHC_HAL_CMD_END_BIT_ERR_INT BM_SDHC_IRQSTAT_CEBE
+#define SDHC_HAL_CMD_INDEX_ERR_INT BM_SDHC_IRQSTAT_CIE
+#define SDHC_HAL_DATA_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_DTOE
+#define SDHC_HAL_DATA_CRC_ERR_INT BM_SDHC_IRQSTAT_DCE
+#define SDHC_HAL_DATA_END_BIT_ERR_INT BM_SDHC_IRQSTAT_DEBE
+#define SDHC_HAL_AUTO_CMD12_ERR_INT BM_SDHC_IRQSTAT_AC12E
+
+#define SDHC_HAL_CMD_ERR_INT ((uint32_t)(SDHC_HAL_CMD_TIMEOUT_ERR_INT | \
+ SDHC_HAL_CMD_CRC_ERR_INT | \
+ SDHC_HAL_CMD_END_BIT_ERR_INT | \
+ SDHC_HAL_CMD_INDEX_ERR_INT))
+#define SDHC_HAL_DATA_ERR_INT ((uint32_t)(SDHC_HAL_DATA_TIMEOUT_ERR_INT | \
+ SDHC_HAL_DATA_CRC_ERR_INT | \
+ SDHC_HAL_DATA_END_BIT_ERR_INT))
+#define SDHC_HAL_DATA_ALL_INT ((uint32_t)(SDHC_HAL_DATA_ERR_INT | \
+ SDHC_HAL_DATA_COMPLETE_INT | \
+ SDHC_HAL_BUF_READ_READY_INT | \
+ SDHC_HAL_BUF_WRITE_READY_INT | \
+ SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT))
+#define SDHC_HAL_CMD_ALL_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
+ SDHC_HAL_CMD_COMPLETE_INT | \
+ SDHC_HAL_AUTO_CMD12_ERR_INT))
+#define SDHC_HAL_CD_ALL_INT ((uint32_t)(SDHC_HAL_CARD_INSERTION_INT | \
+ SDHC_HAL_CARD_REMOVAL_INT))
+#define SDHC_HAL_ALL_ERR_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
+ SDHC_HAL_DATA_ERR_INT | \
+ SDHC_HAL_AUTO_CMD12_ERR_INT | \
+ SDHC_HAL_DMA_ERR_INT))
+
+/* AC12ERR */
+#define SDHC_HAL_ACMD12_NOT_EXEC_ERR BM_SDHC_AC12ERR_AC12NE
+#define SDHC_HAL_ACMD12_TIMEOUT_ERR BM_SDHC_AC12ERR_AC12TOE
+#define SDHC_HAL_ACMD12_END_BIT_ERR BM_SDHC_AC12ERR_AC12EBE
+#define SDHC_HAL_ACMD12_CRC_ERR BM_SDHC_AC12ERR_AC12CE
+#define SDHC_HAL_ACMD12_INDEX_ERR BM_SDHC_AC12ERR_AC12IE
+#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR BM_SDHC_AC12ERR_CNIBAC12E
+
+/* HTCAPBLT */
+#define SDHC_HAL_SUPPORT_ADMA BM_SDHC_HTCAPBLT_ADMAS
+#define SDHC_HAL_SUPPORT_HIGHSPEED BM_SDHC_HTCAPBLT_HSS
+#define SDHC_HAL_SUPPORT_DMA BM_SDHC_HTCAPBLT_DMAS
+#define SDHC_HAL_SUPPORT_SUSPEND_RESUME BM_SDHC_HTCAPBLT_SRS
+#define SDHC_HAL_SUPPORT_3_3_V BM_SDHC_HTCAPBLT_VS33
+#define SDHC_HAL_SUPPORT_3_0_V BM_SDHC_HTCAPBLT_VS30
+#define SDHC_HAL_SUPPORT_1_8_V BM_SDHC_HTCAPBLT_VS18
+
+/* FEVT */
+#define SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT BM_SDHC_FEVT_AC12NE
+#define SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_AC12TOE
+#define SDHC_HAL_ACMD12_CRC_ERR_EVENT BM_SDHC_FEVT_AC12CE
+#define SDHC_HAL_ACMD12_END_BIT_ERR_EVENT BM_SDHC_FEVT_AC12EBE
+#define SDHC_HAL_ACMD12_INDEX_ERR_EVENT BM_SDHC_FEVT_AC12IE
+#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT BM_SDHC_FEVT_CNIBAC12E
+#define SDHC_HAL_CMD_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_CTOE
+#define SDHC_HAL_CMD_CRC_ERR_EVENT BM_SDHC_FEVT_CCE
+#define SDHC_HAL_CMD_END_BIT_ERR_EVENT BM_SDHC_FEVT_CEBE
+#define SDHC_HAL_CMD_INDEX_ERR_EVENT BM_SDHC_FEVT_CIE
+#define SDHC_HAL_DATA_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_DTOE
+#define SDHC_HAL_DATA_CRC_ERR_EVENT BM_SDHC_FEVT_DCE
+#define SDHC_HAL_DATA_END_BIT_ERR_EVENT BM_SDHC_FEVT_DEBE
+#define SDHC_HAL_ACMD12_ERR_EVENT BM_SDHC_FEVT_AC12E
+#define SDHC_HAL_CARD_INT_EVENT BM_SDHC_FEVT_CINT
+#define SDHC_HAL_DMA_ERROR_EVENT BM_SDHC_FEVT_DMAE
+
+/* MMCBOOT */
+typedef enum _sdhc_hal_mmcboot {
+ kSdhcHalMmcbootNormal = 0,
+ kSdhcHalMmcbootAlter = 1,
+} sdhc_hal_mmcboot_t;
+
+/* PROCTL */
+typedef enum _sdhc_hal_led {
+ kSdhcHalLedOff = 0,
+ kSdhcHalLedOn = 1,
+} sdhc_hal_led_t;
+
+typedef enum _sdhc_hal_dtw {
+ kSdhcHalDtw1Bit = 0,
+ kSdhcHalDtw4Bit = 1,
+ kSdhcHalDtw8Bit = 2,
+} sdhc_hal_dtw_t;
+
+typedef enum _sdhc_hal_endian {
+ kSdhcHalEndianBig = 0,
+ kSdhcHalEndianHalfWordBig = 1,
+ kSdhcHalEndianLittle = 2,
+} sdhc_hal_endian_t;
+
+typedef enum _sdhc_hal_dma_mode {
+ kSdhcHalDmaSimple = 0,
+ kSdhcHalDmaAdma1 = 1,
+ kSdhcHalDmaAdma2 = 2,
+} sdhc_hal_dma_mode_t;
+
+#define SDHC_HAL_ADMA1_ADDR_ALIGN (4096)
+#define SDHC_HAL_ADMA1_LEN_ALIGN (4096)
+#define SDHC_HAL_ADMA2_ADDR_ALIGN (4)
+#define SDHC_HAL_ADMA2_LEN_ALIGN (4)
+
+/*
+ * ADMA1 descriptor table
+ * |------------------------|---------|--------------------------|
+ * | Address/page Field |reserved | Attribute |
+ * |------------------------|---------|--------------------------|
+ * |31 12|11 6|05 |04 |03|02 |01 |00 |
+ * |------------------------|---------|----|----|--|---|---|-----|
+ * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
+ * |------------------------|---------|----|----|--|---|---|-----|
+ *
+ *
+ * |------|------|-----------------|-------|-------------|
+ * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
+ * |------|------|-----------------|---------------------|
+ * | 0 | 0 | No op | Don't care |
+ * |------|------|-----------------|-------|-------------|
+ * | 0 | 1 | Set data length | 0000 | Data Length |
+ * |------|------|-----------------|-------|-------------|
+ * | 1 | 0 | Transfer data | Data address |
+ * |------|------|-----------------|---------------------|
+ * | 1 | 1 | Link descriptor | Descriptor address |
+ * |------|------|-----------------|---------------------|
+ *
+ */
+typedef uint32_t sdhc_hal_adma1_descriptor_t;
+#define SDHC_HAL_ADMA1_DESC_VALID_MASK (1 << 0)
+#define SDHC_HAL_ADMA1_DESC_END_MASK (1 << 1)
+#define SDHC_HAL_ADMA1_DESC_INT_MASK (1 << 2)
+#define SDHC_HAL_ADMA1_DESC_ACT1_MASK (1 << 4)
+#define SDHC_HAL_ADMA1_DESC_ACT2_MASK (1 << 5)
+#define SDHC_HAL_ADMA1_DESC_TYPE_NOP (SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_TRAN (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_LINK (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_SET (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT (12)
+#define SDHC_HAL_ADMA1_DESC_ADDRESS_MASK (0xFFFFFU)
+#define SDHC_HAL_ADMA1_DESC_LEN_SHIFT (12)
+#define SDHC_HAL_ADMA1_DESC_LEN_MASK (0xFFFFU)
+#define SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1)
+
+/*
+ * ADMA2 descriptor table
+ * |----------------|---------------|-------------|--------------------------|
+ * | Address Field | length | reserved | Attribute |
+ * |----------------|---------------|-------------|--------------------------|
+ * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
+ * |----------------|---------------|-------------|----|----|--|---|---|-----|
+ * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
+ * |----------------|---------------|-------------|----|----|--|---|---|-----|
+ *
+ *
+ * | Act2 | Act1 | Comment | Operation |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * | 0 | 0 | No op | Don't care |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * | 0 | 1 | Reserved | Read this line and go to next one |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * | 1 | 1 | Link descriptor | Link to another descriptor |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ *
+ */
+typedef struct SdhcHalAdma2Descriptor {
+ uint32_t attribute;
+ uint32_t *address;
+} sdhc_hal_adma2_descriptor_t;
+
+#define SDHC_HAL_ADMA2_DESC_VALID_MASK (1 << 0)
+#define SDHC_HAL_ADMA2_DESC_END_MASK (1 << 1)
+#define SDHC_HAL_ADMA2_DESC_INT_MASK (1 << 2)
+#define SDHC_HAL_ADMA2_DESC_ACT1_MASK (1 << 4)
+#define SDHC_HAL_ADMA2_DESC_ACT2_MASK (1 << 5)
+#define SDHC_HAL_ADMA2_DESC_TYPE_NOP (SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_RCV (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_TRAN (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_LINK (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_LEN_SHIFT (16)
+#define SDHC_HAL_ADMA2_DESC_LEN_MASK (0xFFFFU)
+#define SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA2_DESC_LEN_MASK + 1)
+
+#define SDHC_HAL_RST_TYPE_ALL BM_SDHC_SYSCTL_RSTA
+#define SDHC_HAL_RST_TYPE_CMD BM_SDHC_SYSCTL_RSTC
+#define SDHC_HAL_RST_TYPE_DATA BM_SDHC_SYSCTL_RSTD
+
+#define SDHC_HAL_MAX_BLKLEN_512B (0U)
+#define SDHC_HAL_MAX_BLKLEN_1024B (1U)
+#define SDHC_HAL_MAX_BLKLEN_2048B (2U)
+#define SDHC_HAL_MAX_BLKLEN_4096B (3U)
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name SDHC HAL FUNCTION */
+/*@{ */
+
+/*!
+ * @brief Configures the DMA address.
+ *
+ * @param baseAddr SDHC base address
+ * @param address the DMA address
+ */
+static inline void SDHC_HAL_SetDmaAddress(uint32_t baseAddr, uint32_t address)
+{
+ HW_SDHC_DSADDR_WR(baseAddr, BF_SDHC_DSADDR_DSADDR(address));
+}
+
+/*!
+ * @brief Gets the DMA address.
+ *
+ * @param baseAddr SDHC base address
+ * @return the DMA address
+ */
+static inline uint32_t SDHC_HAL_GetDmaAddress(uint32_t baseAddr)
+{
+ return HW_SDHC_DSADDR_RD(baseAddr);
+}
+
+/*!
+ * @brief Gets the block size configured.
+ *
+ * @param baseAddr SDHC base address
+ * @return the block size already configured
+ */
+static inline uint32_t SDHC_HAL_GetBlockSize(uint32_t baseAddr)
+{
+ return BR_SDHC_BLKATTR_BLKSIZE(baseAddr);
+}
+
+/*!
+ * @brief Sets the block size.
+ *
+ * @param baseAddr SDHC base address
+ * @param blockSize the block size
+ */
+static inline void SDHC_HAL_SetBlockSize(uint32_t baseAddr, uint32_t blockSize)
+{
+ BW_SDHC_BLKATTR_BLKSIZE(baseAddr, blockSize);
+}
+
+/*!
+ * @brief Sets the block count.
+ *
+ * @param baseAddr SDHC base address
+ * @param blockCount the block count
+ */
+static inline void SDHC_HAL_SetBlockCount(uint32_t baseAddr, uint32_t blockCount)
+{
+ BW_SDHC_BLKATTR_BLKCNT(baseAddr, blockCount);
+}
+
+/*!
+ * @brief Gets the block count configured.
+ *
+ * @param baseAddr SDHC base address
+ * @return the block count already configured
+ */
+static inline uint32_t SDHC_HAL_GetBlockCount(uint32_t baseAddr)
+{
+ return BR_SDHC_BLKATTR_BLKCNT(baseAddr);
+}
+
+/*!
+ * @brief Configures the command argument.
+ *
+ * @param baseAddr SDHC base address
+ * @param arg the command argument
+ */
+static inline void SDHC_HAL_SetCmdArgument(uint32_t baseAddr, uint32_t arg)
+{
+ BW_SDHC_CMDARG_CMDARG(baseAddr, arg);
+}
+
+/*!
+ * @brief Sends a command.
+ *
+ * @param baseAddr SDHC base address
+ * @param index command index
+ * @param flags transfer type flags
+ */
+static inline void SDHC_HAL_SendCmd(uint32_t baseAddr, uint32_t index, uint32_t flags)
+{
+ HW_SDHC_XFERTYP_WR(baseAddr, ((index << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX)
+ | (flags & ( BM_SDHC_XFERTYP_DMAEN | BM_SDHC_XFERTYP_MSBSEL | BM_SDHC_XFERTYP_DPSEL
+ | BM_SDHC_XFERTYP_CMDTYP | BM_SDHC_XFERTYP_BCEN | BM_SDHC_XFERTYP_CICEN
+ | BM_SDHC_XFERTYP_CCCEN | BM_SDHC_XFERTYP_RSPTYP | BM_SDHC_XFERTYP_DTDSEL
+ | BM_SDHC_XFERTYP_AC12EN)));
+}
+
+/*!
+ * @brief Fills the the data port.
+ *
+ * @param baseAddr SDHC base address
+ * @param data the data about to be sent
+ */
+static inline void SDHC_HAL_SetData(uint32_t baseAddr, uint32_t data)
+{
+ HW_SDHC_DATPORT_WR(baseAddr, data);
+}
+
+/*!
+ * @brief Retrieves the data from the data port.
+ *
+ * @param baseAddr SDHC base address
+ * @return data the data read
+ */
+static inline uint32_t SDHC_HAL_GetData(uint32_t baseAddr)
+{
+ return BR_SDHC_DATPORT_DATCONT(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the command inhibit bit is set or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if command inhibit, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsCmdInhibit(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_CIHB(baseAddr);
+}
+
+/*!
+ * @brief Checks whether data inhibit bit is set or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if data inhibit, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsDataInhibit(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_CDIHB(baseAddr);
+}
+
+/*!
+ * @brief Checks whether data line is active.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's active, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsDataLineActive(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_DLA(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the SD clock is stable or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's stable, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsSdClockStable(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_SDSTB(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the IPG clock is off or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's off, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsIpgClockOff(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_IPGOFF(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the system clock is off or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's off, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsSysClockOff(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_HCKOFF(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the peripheral clock is off or not.
+ *
+ * @param baseAddr SDHC base address.
+ * @return 1 if it's off, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsPeripheralClockOff(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_PEROFF(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the SD clock is off or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's off, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsSdClkOff(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_SDOFF(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the write transfer is active or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's active, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsWriteTransferActive(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_WTA(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the read transfer is active or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's off, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsReadTransferActive(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_RTA(baseAddr);
+}
+
+/*!
+ * @brief Check whether the buffer write is enabled or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's isEnabledd, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsBuffWriteEnabled(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_BWEN(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the buffer read is enabled or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's isEnabledd, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsBuffReadEnabled(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_BREN(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the card is inserted or not.
+ *
+ * @param baseAddr SDHC base address.
+ * @return 1 if it's inserted, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsCardInserted(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_CINS(baseAddr);
+}
+
+/*!
+ * @brief Checks whether the command line signal is high or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return 1 if it's high, 0 if not.
+ */
+static inline uint32_t SDHC_HAL_IsCmdLineLevelHigh(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_CLSL(baseAddr);
+}
+
+/*!
+ * @brief Gets the data line signal level or not.
+ *
+ * @param baseAddr SDHC base address
+ * @return [7:0] data line signal level
+ */
+static inline uint32_t SDHC_HAL_GetDataLineLevel(uint32_t baseAddr)
+{
+ return BR_SDHC_PRSSTAT_DLSL(baseAddr);
+}
+
+/*!
+ * @brief Sets the LED state.
+ *
+ * @param baseAddr SDHC base address
+ * @param state the LED state
+ */
+static inline void SDHC_HAL_SetLedState(uint32_t baseAddr, sdhc_hal_led_t state)
+{
+ BW_SDHC_PROCTL_LCTL(baseAddr, state);
+}
+
+/*!
+ * @brief Sets the data transfer width.
+ *
+ * @param baseAddr SDHC base address
+ * @param dtw data transfer width
+ */
+static inline void SDHC_HAL_SetDataTransferWidth(uint32_t baseAddr, sdhc_hal_dtw_t dtw)
+{
+ BW_SDHC_PROCTL_DTW(baseAddr, dtw);
+}
+
+/*!
+ * @brief Checks whether the DAT3 is taken as card detect pin.
+ *
+ * @param baseAddr SDHC base address
+ * @return if DAT3 as card detect pin is enabled
+ */
+static inline bool SDHC_HAL_IsD3cdEnabled(uint32_t baseAddr)
+{
+ return BR_SDHC_PROCTL_D3CD(baseAddr);
+}
+
+/*!
+ * @brief Enables the DAT3 as a card detect pin.
+ *
+ * @param baseAddr SDHC base address
+ * @param enable to enable DAT3 as card detect pin
+ */
+static inline void SDHC_HAL_SetD3cd(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_D3CD(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Configures the endian mode.
+ *
+ * @param baseAddr SDHC base address
+ * @param endianMode endian mode
+ */
+static inline void SDHC_HAL_SetEndian(uint32_t baseAddr, sdhc_hal_endian_t endianMode)
+{
+ BW_SDHC_PROCTL_EMODE(baseAddr, endianMode);
+}
+
+/*!
+* @brief Gets the card detect test level.
+*
+* @param baseAddr SDHC base address
+* @return card detect test level
+*/
+static inline uint32_t SDHC_HAL_GetCdTestLevel(uint32_t baseAddr)
+{
+ return BR_SDHC_PROCTL_CDTL(baseAddr);
+}
+
+/*!
+* @brief Enables the card detect test.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable card detect signal for test purpose
+*/
+static inline void SDHC_HAL_SetCdTest(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_CDSS(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Sets the DMA mode.
+*
+* @param baseAddr SDHC base address
+* @param dmaMode the DMA mode
+*/
+static inline void SDHC_HAL_SetDmaMode(uint32_t baseAddr, sdhc_hal_dma_mode_t dmaMode)
+{
+ BW_SDHC_PROCTL_DMAS(baseAddr, dmaMode);
+}
+
+/*!
+* @brief Enables stop at the block gap.
+*
+* @param baseAddr SDHC base address
+* @param enable to stop at block gap request
+*/
+static inline void SDHC_HAL_SetStopAtBlockGap(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_SABGREQ(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Restarts a transaction which has stopped at the block gap.
+*
+* @param baseAddr SDHC base address
+*/
+static inline void SDHC_HAL_SetContinueRequest(uint32_t baseAddr)
+{
+ BW_SDHC_PROCTL_CREQ(baseAddr, 1);
+}
+
+/*!
+* @brief Enables the read wait control for the SDIO cards.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable read wait control
+*/
+static inline void SDHC_HAL_SetReadWaitCtrl(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_RWCTL(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables stop at the block gap requests.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable interrupt at block gap
+*/
+static inline void SDHC_HAL_SetIntStopAtBlockGap(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_IABG(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables wakeup event on the card interrupt.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable wakeup event on card interrupt
+*/
+static inline void SDHC_HAL_SetWakeupOnCardInt(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_WECINT(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables wakeup event on the card insertion.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable wakeup event on card insertion
+*/
+static inline void SDHC_HAL_SetWakeupOnCardInsertion(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_WECINS(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables wakeup event on card removal.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable wakeup event on card removal
+*/
+static inline void SDHC_HAL_SetWakeupOnCardRemoval(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_PROCTL_WECRM(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the IPG clock and no automatic clock gating off.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable IPG clock
+*/
+static inline void SDHC_HAL_SetIpgClock(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_SYSCTL_IPGEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the system clock and no automatic clock gating off.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable SYS clock
+*/
+static inline void SDHC_HAL_SetSysClock(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_SYSCTL_HCKEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the peripheral clock and no automatic clock gating off.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable Peripheral clock
+*/
+static inline void SDHC_HAL_SetPeripheralClock(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_SYSCTL_PEREN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the SD clock. It should be disabled before changing the SD clock
+* frequency.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable SD clock or not
+*/
+static inline void SDHC_HAL_SetSdClock(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_SYSCTL_SDCLKEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Sets the SD clock frequency divisor.
+*
+* @param baseAddr SDHC base address
+* @param divisor the divisor
+*/
+static inline void SDHC_HAL_SetClockDivisor(uint32_t baseAddr, uint32_t divisor)
+{
+ BW_SDHC_SYSCTL_DVS(baseAddr, divisor);
+}
+
+/*!
+* @brief Sets the SD clock frequency select.
+*
+* @param baseAddr SDHC base address
+* @param frequency the frequency selector
+*/
+static inline void SDHC_HAL_SetClockFrequency(uint32_t baseAddr, uint32_t frequency)
+{
+ BW_SDHC_SYSCTL_SDCLKFS(baseAddr, frequency);
+}
+
+/*!
+* @brief Sets the data timeout counter value.
+*
+* @param baseAddr SDHC base address
+* @param timeout Data timeout counter value
+*/
+static inline void SDHC_HAL_SetDataTimeout(uint32_t baseAddr, uint32_t timeout)
+{
+ BW_SDHC_SYSCTL_DTOCV(baseAddr, timeout);
+}
+
+/*!
+* @brief Gets the current interrupt status.
+*
+* @param baseAddr SDHC base address
+* @return current interrupt flags
+*/
+static inline uint32_t SDHC_HAL_GetIntFlags(uint32_t baseAddr)
+{
+ return HW_SDHC_IRQSTAT_RD(baseAddr);
+}
+
+/*!
+* @brief Clears a specified interrupt status.
+*
+* @param baseAddr SDHC base address
+* @param mask to specify interrupts' flags to be cleared
+*/
+static inline void SDHC_HAL_ClearIntFlags(uint32_t baseAddr, uint32_t mask)
+{
+ HW_SDHC_IRQSTAT_WR(baseAddr, mask);
+}
+
+/*!
+* @brief Gets the currently enabled interrupt signal.
+*
+* @param baseAddr SDHC base address
+* @return currently enabled interrupt signal
+*/
+static inline uint32_t SDHC_HAL_GetIntSignal(uint32_t baseAddr)
+{
+ return HW_SDHC_IRQSIGEN_RD(baseAddr);
+}
+
+/*!
+* @brief Gets the currently enabled interrupt state.
+*
+* @param baseAddr SDHC base address
+* @return currently enabled interrupts' state
+*/
+static inline uint32_t SDHC_HAL_GetIntState(uint32_t baseAddr)
+{
+ return HW_SDHC_IRQSTATEN_RD(baseAddr);
+}
+
+/*!
+* @brief Gets the auto cmd12 error.
+*
+* @param baseAddr SDHC base address
+* @return auto cmd12 error status
+*/
+static inline uint32_t SDHC_HAL_GetAc12Error(uint32_t baseAddr)
+{
+ return HW_SDHC_AC12ERR_RD(baseAddr);
+}
+
+/*!
+* @brief Gets the maximum block length supported.
+*
+* @param baseAddr SDHC base address
+* @return the maximum block length support
+*/
+static inline uint32_t SDHC_HAL_GetMaxBlockLength(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_MBL(baseAddr);
+}
+
+/*!
+* @brief Checks whether the ADMA is supported.
+*
+* @param baseAddr SDHC base address
+* @return if ADMA is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportAdma(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_ADMAS(baseAddr);
+}
+
+/*!
+* @brief Checks whether the high speed is supported.
+*
+* @param baseAddr SDHC base address
+* @return if high speed is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportHighspeed(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_HSS(baseAddr);
+}
+
+/*!
+* @brief Checks whether the DMA is supported.
+*
+* @param baseAddr SDHC base address
+* @return if high speed is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportDma(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_DMAS(baseAddr);
+}
+
+/*!
+* @brief Checks whether the suspend/resume is supported.
+*
+* @param baseAddr SDHC base address
+* @return if suspend and resume is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportSuspendResume(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_SRS(baseAddr);
+}
+
+/*!
+* @brief Checks whether the voltage 3.3 is supported.
+*
+* @param baseAddr SDHC base address
+* @return if voltage 3.3 is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportV330(uint32_t baseAddr)
+{
+ return BR_SDHC_HTCAPBLT_VS33(baseAddr);
+}
+
+/*!
+* @brief Checks whether the voltage 3.0 is supported.
+*
+* @param baseAddr SDHC base address
+* @return if voltage 3.0 is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportV300(uint32_t baseAddr)
+{
+#if defined(FSL_FEATURE_SDHC_HAS_V300_SUPPORT) && FSL_FEATURE_SDHC_HAS_V300_SUPPORT
+ return BR_SDHC_HTCAPBLT_VS30(baseAddr);
+#else
+ return 0;
+#endif
+}
+
+/*!
+* @brief Checks whether the voltage 1.8 is supported.
+*
+* @param baseAddr SDHC base address
+* @return if voltage 1.8 is supported
+*/
+static inline uint32_t SDHC_HAL_DoesHostSupportV180(uint32_t baseAddr)
+{
+#if defined(FSL_FEATURE_SDHC_HAS_V180_SUPPORT) && FSL_FEATURE_SDHC_HAS_V180_SUPPORT
+ return BR_SDHC_HTCAPBLT_VS18(baseAddr);
+#else
+ return 0;
+#endif
+}
+
+/*!
+* @brief Sets the watermark for writing.
+*
+* @param baseAddr SDHC base address
+* @param watermark for writing
+*/
+static inline void SDHC_HAL_SetWriteWatermarkLevel(uint32_t baseAddr, uint32_t watermark)
+{
+ BW_SDHC_WML_WRWML(baseAddr, watermark);
+}
+
+/*!
+* @brief Sets the watermark for reading.
+*
+* @param baseAddr SDHC base address
+* @param watermark for reading
+*/
+static inline void SDHC_HAL_SetReadWatermarkLevel(uint32_t baseAddr, uint32_t watermark)
+{
+ BW_SDHC_WML_RDWML(baseAddr, watermark);
+}
+
+/*!
+* @brief Sets the force events according to the given mask.
+*
+* @param baseAddr SDHC base address
+* @param mask to specify the force events' flags to be set
+*/
+static inline void SDHC_HAL_SetForceEventFlags(uint32_t baseAddr, uint32_t mask)
+{
+ HW_SDHC_FEVT_WR(baseAddr, mask);
+}
+
+/*!
+* @brief Checks whether the ADMA error is length mismatch.
+*
+* @param baseAddr SDHC base address
+* @return if ADMA error is length mismatch
+*/
+static inline uint32_t SDHC_HAL_IsAdmaLengthMismatchError(uint32_t baseAddr)
+{
+ return BR_SDHC_ADMAES_ADMALME(baseAddr);
+}
+
+/*!
+* @brief Checks the SD clock.
+*
+* Checks whether the clock to the SD is enabled.
+*
+* @param baseAddr SDHC base address
+* @return true if enabled
+*/
+static inline bool SDHC_HAL_IsSdClockOff(uint32_t baseAddr)
+{
+ return BR_SDHC_SYSCTL_SDCLKEN(baseAddr);
+}
+
+/*!
+* @brief Returns the state of the ADMA error.
+*
+* @param baseAddr SDHC base address
+* @return error state
+*/
+static inline uint32_t SDHC_HAL_GetAdmaErrorState(uint32_t baseAddr)
+{
+ return BR_SDHC_ADMAES_ADMAES(baseAddr);
+}
+
+/*!
+* @brief Checks whether the ADMA error is a descriptor error.
+*
+* @param baseAddr SDHC base address
+* @return if ADMA error is descriptor error
+*/
+static inline uint32_t SDHC_HAL_IsAdmaDescriptionError(uint32_t baseAddr)
+{
+ return BR_SDHC_ADMAES_ADMADCE(baseAddr);
+}
+
+/*!
+* @brief Sets the ADMA address.
+*
+* @param baseAddr SDHC base address
+* @param address for ADMA transfer
+*/
+static inline void SDHC_HAL_SetAdmaAddress(uint32_t baseAddr, uint32_t address)
+{
+ HW_SDHC_ADSADDR_WR(baseAddr, address);
+}
+
+/*!
+* @brief Enables the external DMA request.
+*
+* @param baseAddr SDHC base address
+* @param enable to external DMA
+*/
+static inline void SDHC_HAL_SetExternalDmaRequest(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_VENDOR_EXTDMAEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the exact block number for the SDIO CMD53.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable exact block number block read for SDIO CMD53
+*/
+static inline void SDHC_HAL_SetExactBlockNumber(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_VENDOR_EXBLKNU(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Sets the timeout value for the boot ACK.
+*
+* @param baseAddr SDHC base address
+* @param timeout boot ack time out counter value
+*/
+static inline void SDHC_HAL_SetBootAckTimeout(uint32_t baseAddr, uint32_t timeout)
+{
+ BW_SDHC_MMCBOOT_DTOCVACK(baseAddr, timeout);
+}
+
+/*!
+* @brief Enables the boot ACK.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable boot ack mode
+*/
+static inline void SDHC_HAL_SetBootAck(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_MMCBOOT_BOOTACK(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Configures the boot mode.
+*
+* @param baseAddr SDHC base address
+* @param mode the boot mode
+*/
+static inline void SDHC_HAL_SetBootMode(uint32_t baseAddr, sdhc_hal_mmcboot_t mode)
+{
+ BW_SDHC_MMCBOOT_BOOTMODE(baseAddr, mode);
+}
+
+/*!
+* @brief Enables the fast boot.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable fast boot
+*/
+static inline void SDHC_HAL_SetFastboot(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_MMCBOOT_BOOTEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Enables the automatic stop at the block gap.
+*
+* @param baseAddr SDHC base address
+* @param enable to enable auto stop at block gap function, when boot.
+*/
+static inline void SDHC_HAL_SetAutoStopAtBlockGap(uint32_t baseAddr, bool enable)
+{
+ BW_SDHC_MMCBOOT_AUTOSABGEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+* @brief Configures the the block count for the boot.
+*
+* @param baseAddr SDHC base address
+* @param blockCount the block count for boot
+*/
+static inline void SDHC_HAL_SetBootBlockCount(uint32_t baseAddr, uint32_t blockCount)
+{
+ BW_SDHC_MMCBOOT_BOOTBLKCNT(baseAddr, blockCount);
+}
+
+/*!
+* @brief Gets a specification version.
+*
+* @param baseAddr SDHC base address
+* @return specification version
+*/
+static inline uint32_t SDHC_HAL_GetSpecificationVersion(uint32_t baseAddr)
+{
+ return BR_SDHC_HOSTVER_SVN(baseAddr);
+}
+
+/*!
+* @brief Gets the vendor version.
+*
+* @param baseAddr SDHC base address
+* @return vendor version
+*/
+static inline uint32_t SDHC_HAL_GetVendorVersion(uint32_t baseAddr)
+{
+ return BR_SDHC_HOSTVER_VVN(baseAddr);
+}
+
+/*!
+ * @brief Gets the command response.
+ *
+ * @param baseAddr SDHC base address
+ * @param index of response register, range from 0 to 3
+ */
+uint32_t SDHC_HAL_GetResponse(uint32_t baseAddr, uint32_t index);
+
+/*!
+* @brief Enables the specified interrupts.
+*
+* @param baseAddr SDHC base address
+* @param enable enable or disable
+* @param mask to specify interrupts to be isEnabledd
+*/
+void SDHC_HAL_SetIntSignal(uint32_t baseAddr, bool enable, uint32_t mask);
+
+/*!
+* @brief Enables the specified interrupt state.
+*
+* @param baseAddr SDHC base address
+* @param enable enable or disable
+* @param mask to specify interrupts' state to be enabled
+*/
+void SDHC_HAL_SetIntState(uint32_t baseAddr, bool enable, uint32_t mask);
+
+/*!
+* @brief Performs an SDHC reset.
+*
+* @param baseAddr SDHC base address
+* @param type the type of reset
+* @param timeout timeout for reset
+* @return 0 on success, else on error
+*/
+uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout);
+
+/*!
+* @brief Sends 80 clocks to the card to initialize the card.
+*
+* @param baseAddr SDHC base address
+* @param timeout timeout for initialize card
+* @return 0 on success, else on error
+*/
+uint32_t SDHC_HAL_InitCard(uint32_t baseAddr, uint32_t timeout);
+
+/*!
+* @brief Gets the IRQ ID for a given host controller.
+*
+* @param baseAddr SDHC base address
+* @return IRQ number for specific SDHC instance
+*/
+IRQn_Type SDHC_HAL_GetIrqId(uint32_t baseAddr);
+
+/*!
+ * @brief Initializes the SDHC HAL.
+ *
+ * @param baseAddr SDHC base address
+ */
+void SDHC_HAL_Init(uint32_t baseAddr);
+
+/*@} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif /* MBED_NO_SDHC */
+
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,4222 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_SIM_FEATURES_H__) +#define __FSL_SIM_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK24FN256VDC12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (1) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (1) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (1) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (1) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (1) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (1) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (1) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (1) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (1) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (4) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (1) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (1) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (1) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (1) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (1) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (1) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (1) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (1) +#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ + defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (2) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ + defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) + /* @brief Has USB FS divider. */ + #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) + /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ + #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) + /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) + /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) + /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) + /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ + #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) + /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) + /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) + /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) + /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) + /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) + /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) + /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) + /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ + #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) + /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ + #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) + /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) + /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) + /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ + #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) + /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) + /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) + /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) + /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) + /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) + /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) + /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) + /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) + /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) + /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) + /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ + #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) + /* @brief Has FTM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) + /* @brief Number of FTM modules. */ + #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) + /* @brief Number of FTM triggers with selectable source. */ + #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) + /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) + /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) + /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) + /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) + /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) + /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) + /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) + /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) + /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) + /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ + #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) + /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) + /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ + #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) + /* @brief Has TPM module(s) configuration. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) + /* @brief The highest TPM module index. */ + #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) + /* @brief Has TPM module with index 0. */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) + /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) + /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) + /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) + /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) + /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) + /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) + /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ + #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) + /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) + /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) + /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) + /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) + /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) + /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) + /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) + /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) + /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) + /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) + /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) + /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) + /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) + /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) + /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) + /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ + #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) + /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ + #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) + /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) + /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) + /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) + /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ + #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) + /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) + /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) + /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) + /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) + /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) + /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) + /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ + #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) + /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) + /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) + /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) + /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) + /* @brief Has device die ID (register bit field SDID[DIEID]). */ + #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) + /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ + #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) + /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) + /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) + /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) + /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) + /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) + /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) + /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) + /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) + /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) + /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) + /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) + /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ + #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) + /* @brief Has miscellanious control register (register MCR). */ + #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) + /* @brief Has COP watchdog (registers COPC and SRVCOP). */ + #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) + /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ + #define FSL_FEATURE_SIM_HAS_COP_STOP (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_SIM_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1468 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetSource
+ * Description : Set clock source setting
+ * This function will set the settings for specified clock source. Each clock
+ * source has its clock selection settings. Refer to reference manual for
+ * details of settings for each clock source. Refer to clock_source_names_t
+ * for clock sources.
+ *
+ *END**************************************************************************/
+sim_hal_status_t CLOCK_HAL_SetSource(uint32_t baseAddr,
+ clock_source_names_t clockSource,
+ uint8_t setting)
+{
+ sim_hal_status_t status = kSimHalSuccess;
+ assert(clockSource < kClockSourceMax);
+
+ switch (clockSource)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC
+ case kClockNfcSrc: /* NFCSRC*/
+ BW_SIM_SOPT2_NFCSRC(baseAddr, setting);
+ break;
+ case kClockNfcSel: /* NFC_CLKSEL*/
+ BW_SIM_SOPT2_NFC_CLKSEL(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC
+ case kClockEsdhcSrc: /* ESDHCSRC*/
+ BW_SIM_SOPT2_ESDHCSRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_SDHCSRC
+ case kClockSdhcSrc: /* SDHCSRC*/
+ BW_SIM_SOPT2_SDHCSRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC
+ case kClockLcdcSrc: /* LCDCSRC*/
+ BW_SIM_SOPT2_LCDCSRC(baseAddr, setting);
+ break;
+ case kClockLcdcSel: /* LCDC_CLKSEL*/
+ BW_SIM_SOPT2_LCDC_CLKSEL(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TIMESRC
+ case kClockTimeSrc: /* TIMESRC*/
+ BW_SIM_SOPT2_TIMESRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_RMIISRC
+ case kClockRmiiSrc: /* RMIISRC*/
+ BW_SIM_SOPT2_RMIISRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBSRC
+ case kClockUsbSrc: /* USBSRC*/
+ BW_SIM_SOPT2_USBSRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBFSRC
+ case kClockUsbfSrc: /* USBFSRC*/
+ BW_SIM_SOPT2_USBFSRC(baseAddr, setting);
+ break;
+ case kClockUsbfSel: /* USBF_CLKSEL*/
+ BW_SIM_SOPT2_USBF_CLKSEL(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBHSRC
+ case kClockUsbhSrc: /* USBHSRC*/
+ BW_SIM_SOPT2_USBHSRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_UART0SRC
+ case kClockUart0Src: /* UART0SRC*/
+ BW_SIM_SOPT2_UART0SRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPMSRC
+ case kClockTpmSrc: /* TPMSRC*/
+ BW_SIM_SOPT2_TPMSRC(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC
+ case kClockLpuartSrc: /* LPUARTSRC*/
+ BW_SIM_SOPT2_LPUARTSRC(baseAddr, setting);
+ break;
+#endif
+
+ case kClockOsc32kSel: /* OSC32KSEL*/
+ BW_SIM_SOPT1_OSC32KSEL(baseAddr, setting);
+ break;
+
+ case kClockPllfllSel: /* PLLFLLSEL*/
+ BW_SIM_SOPT2_PLLFLLSEL(baseAddr, setting);
+ break;
+
+#if FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL
+ case kClockTraceSel: /* TRACE_CLKSEL*/
+ BW_SIM_SOPT2_TRACECLKSEL(baseAddr, setting);
+ break;
+#endif
+
+ case kClockClkoutSel: /* CLKOUTSEL*/
+ BW_SIM_SOPT2_CLKOUTSEL(baseAddr, setting);
+ break;
+
+#if FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION
+ case kClockRtcClkoutSel: /* RTCCLKOUTSEL*/
+ BW_SIM_SOPT2_RTCCLKOUTSEL(baseAddr, setting);
+ break;
+#endif
+
+ default:
+ status = kSimHalNoSuchClockSrc;
+ break;
+ }
+
+ return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetSource
+ * Description : Get clock source setting
+ * This function will get the settings for specified clock source. Each clock
+ * source has its clock selection settings. Refer to reference manual for
+ * details of settings for each clock source. Refer to clock_source_names_t
+ * for clock sources.
+ *
+ *END**************************************************************************/
+sim_hal_status_t CLOCK_HAL_GetSource(uint32_t baseAddr,
+ clock_source_names_t clockSource,
+ uint8_t *setting)
+{
+ sim_hal_status_t status = kSimHalSuccess;
+ assert(clockSource < kClockSourceMax);
+
+ switch (clockSource)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC
+ case kClockNfcSrc: /* NFCSRC*/
+ *setting = BR_SIM_SOPT2_NFCSRC(baseAddr);
+ break;
+ case kClockNfcSel: /* NFC_CLKSEL*/
+ *setting = BR_SIM_SOPT2_NFC_CLKSEL(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC
+ case kClockEsdhcSrc: /* ESDHCSRC*/
+ *setting = BR_SIM_SOPT2_ESDHCSRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_SDHCSRC
+ case kClockSdhcSrc: /* SDHCSRC*/
+ *setting = BR_SIM_SOPT2_SDHCSRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC
+ case kClockLcdcSrc: /* LCDCSRC*/
+ *setting = BR_SIM_SOPT2_LCDCSRC(baseAddr);
+ break;
+ case kClockLcdcSel: /* LCDC_CLKSEL*/
+ *setting = BR_SIM_SOPT2_LCDC_CLKSEL(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TIMESRC
+ case kClockTimeSrc: /* TIMESRC*/
+ *setting = BR_SIM_SOPT2_TIMESRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_RMIISRC
+ case kClockRmiiSrc: /* RMIISRC*/
+ *setting = BR_SIM_SOPT2_RMIISRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBSRC
+ case kClockUsbSrc: /* USBSRC*/
+ *setting = BR_SIM_SOPT2_USBSRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBFSRC
+ case kClockUsbfSrc: /* USBFSRC*/
+ *setting = BR_SIM_SOPT2_USBFSRC(baseAddr);
+ break;
+ case kClockUsbfSel: /* USBF_CLKSEL*/
+ *setting = BR_SIM_SOPT2_USBF_CLKSEL(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_USBHSRC
+ case kClockUsbhSrc: /* USBHSRC*/
+ *setting = BR_SIM_SOPT2_USBHSRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_UART0SRC
+ case kClockUart0Src: /* UART0SRC*/
+ *setting = BR_SIM_SOPT2_UART0SRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPMSRC
+ case kClockTpmSrc: /* TPMSRC*/
+ *setting = BR_SIM_SOPT2_TPMSRC(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC
+ case kClockLpuartSrc: /* LPUARTSRC*/
+ *setting = BR_SIM_SOPT2_LPUARTSRC(baseAddr);
+ break;
+#endif
+
+ case kClockOsc32kSel: /* OSC32KSEL*/
+ *setting = BR_SIM_SOPT1_OSC32KSEL(baseAddr);
+ break;
+
+ case kClockPllfllSel: /* PLLFLLSEL*/
+ *setting = BR_SIM_SOPT2_PLLFLLSEL(baseAddr);
+ break;
+
+#if FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL
+ case kClockTraceSel: /* TRACE_CLKSEL*/
+ *setting = BR_SIM_SOPT2_TRACECLKSEL(baseAddr);
+ break;
+#endif
+
+ case kClockClkoutSel: /* CLKOUTSEL */
+ *setting = BR_SIM_SOPT2_CLKOUTSEL(baseAddr);
+ break;
+
+#if FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION
+ case kClockRtcClkoutSel: /* RTCCLKOUTSEL */
+ *setting = BR_SIM_SOPT2_RTCCLKOUTSEL(baseAddr);
+ break;
+#endif
+
+ default:
+ status = kSimHalNoSuchClockSrc;
+ break;
+ }
+
+ return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetDivider
+ * Description : Set clock divider setting
+ * This function will set the setting for specified clock divider. Refer to
+ * reference manual for supported clock divider and value range. Refer to
+ * clock_divider_names_t for dividers.
+ *
+ *END**************************************************************************/
+sim_hal_status_t CLOCK_HAL_SetDivider(uint32_t baseAddr,
+ clock_divider_names_t clockDivider,
+ uint32_t setting)
+{
+ sim_hal_status_t status = kSimHalSuccess;
+ assert(clockDivider < kClockDividerMax);
+
+ switch (clockDivider)
+ {
+ case kClockDividerOutdiv1: /* OUTDIV1*/
+ BW_SIM_CLKDIV1_OUTDIV1(baseAddr, setting);
+ break;
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2
+ case kClockDividerOutdiv2: /* OUTDIV2*/
+ BW_SIM_CLKDIV1_OUTDIV2(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3
+ case kClockDividerOutdiv3: /* OUTDIV3*/
+ BW_SIM_CLKDIV1_OUTDIV3(baseAddr, setting);
+ break;
+#endif
+
+ case kClockDividerOutdiv4: /* OUTDIV4*/
+ BW_SIM_CLKDIV1_OUTDIV4(baseAddr, setting);
+ break;
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV
+ case kClockDividerUsbFrac: /* USBFRAC*/
+ BW_SIM_CLKDIV2_USBFRAC(baseAddr, setting);
+ break;
+ case kClockDividerUsbDiv: /* USBDIV*/
+ BW_SIM_CLKDIV2_USBDIV(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV
+ case kClockDividerUsbfsFrac: /* USBFSFRAC*/
+ BW_SIM_CLKDIV2_USBFSFRAC(baseAddr, setting);
+ break;
+ case kClockDividerUsbfsDiv: /* USBFSDIV*/
+ BW_SIM_CLKDIV2_USBFSDIV(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV
+ case kClockDividerUsbhsFrac: /* USBHSFRAC*/
+ BW_SIM_CLKDIV2_USBHSFRAC(baseAddr, setting);
+ break;
+ case kClockDividerUsbhsDiv: /* USBHSDIV*/
+ BW_SIM_CLKDIV2_USBHSDIV(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC
+ case kClockDividerLcdcFrac: /* LCDCFRAC*/
+ BW_SIM_CLKDIV3_LCDCFRAC(baseAddr, setting);
+ break;
+ case kClockDividerLcdcDiv: /* LCDCDIV*/
+ BW_SIM_CLKDIV3_LCDCDIV(baseAddr, setting);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC
+ case kClockDividerNfcFrac: /* NFCFRAC*/
+ BW_SIM_CLKDIV4_NFCFRAC(baseAddr, setting);
+ break;
+ case kClockDividerNfcDiv: /* NFCDIV*/
+ BW_SIM_CLKDIV4_NFCDIV(baseAddr, setting);
+ break;
+#endif
+
+ case kClockDividerSpecial1: /* special divider 1 */
+ break;
+
+ default:
+ status = kSimHalNoSuchDivider;
+ break;
+ }
+
+ return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDividers
+ * Description : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers. Refer to
+ * reference manual for supported clock divider and value range. Refer to
+ * clock_divider_names_t for dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDividers(uint32_t baseAddr, uint32_t outdiv1, uint32_t outdiv2,
+ uint32_t outdiv3, uint32_t outdiv4)
+{
+ uint32_t clkdiv1 = 0;
+
+ clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV1(outdiv1);
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2
+ clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV2(outdiv2);
+#endif
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3
+ clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV3(outdiv3);
+#endif
+ clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+ HW_SIM_CLKDIV1_WR(baseAddr, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetDivider
+ * Description : Get clock divider setting
+ * This function will get the setting for specified clock divider. Refer to
+ * reference manual for supported clock divider and value range. Refer to
+ * clock_divider_names_t for dividers.
+ *
+ *END**************************************************************************/
+sim_hal_status_t CLOCK_HAL_GetDivider(uint32_t baseAddr,
+ clock_divider_names_t clockDivider,
+ uint32_t *setting)
+{
+ sim_hal_status_t status = kSimHalSuccess;
+ assert(clockDivider < kClockDividerMax);
+
+ *setting = 0;
+
+ switch (clockDivider)
+ {
+ case kClockDividerOutdiv1: /* OUTDIV1*/
+ *setting = BR_SIM_CLKDIV1_OUTDIV1(baseAddr);
+ break;
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2
+ case kClockDividerOutdiv2: /* OUTDIV2*/
+ *setting = BR_SIM_CLKDIV1_OUTDIV2(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3
+ case kClockDividerOutdiv3: /* OUTDIV3*/
+ *setting = BR_SIM_CLKDIV1_OUTDIV3(baseAddr);
+ break;
+#endif
+
+ case kClockDividerOutdiv4: /* OUTDIV4*/
+ *setting = BR_SIM_CLKDIV1_OUTDIV4(baseAddr);
+ break;
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV
+ case kClockDividerUsbFrac: /* USBFRAC*/
+ *setting = BR_SIM_CLKDIV2_USBFRAC(baseAddr);
+ break;
+ case kClockDividerUsbDiv: /* USBDIV*/
+ *setting = BR_SIM_CLKDIV2_USBDIV(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV
+ case kClockDividerUsbfsFrac: /* USBFSFRAC*/
+ *setting = BR_SIM_CLKDIV2_USBFSFRAC(baseAddr);
+ break;
+ case kClockDividerUsbfsDiv: /* USBFSDIV*/
+ *setting = BR_SIM_CLKDIV2_USBFSDIV(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV
+ case kClockDividerUsbhsFrac: /* USBHSFRAC*/
+ *setting = BR_SIM_CLKDIV2_USBHSFRAC(baseAddr);
+ break;
+ case kClockDividerUsbhsDiv: /* USBHSDIV*/
+ *setting = BR_SIM_CLKDIV2_USBHSDIV(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC
+ case kClockDividerLcdcFrac: /* LCDCFRAC*/
+ *setting = BR_SIM_CLKDIV3_LCDCFRAC(baseAddr);
+ break;
+ case kClockDividerLcdcDiv: /* LCDCDIV*/
+ *setting = BR_SIM_CLKDIV3_LCDCDIV(baseAddr);
+ break;
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC
+ case kClockDividerNfcFrac: /* NFCFRAC*/
+ *setting = BR_SIM_CLKDIV4_NFCFRAC(baseAddr);
+ break;
+ case kClockDividerNfcDiv: /* NFCDIV*/
+ *setting = BR_SIM_CLKDIV4_NFCDIV(baseAddr);
+ break;
+#endif
+
+ case kClockDividerSpecial1: /* special divider 1 */
+ *setting = 1;
+ break;
+
+ default:
+ status = kSimHalNoSuchDivider;
+ break;
+ }
+
+ return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance, bool enable)
+{
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT7_ADC0ALTTRGEN(baseAddr, enable ? 1 : 0);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ BW_SIM_SOPT7_ADC1ALTTRGEN(baseAddr, enable ? 1 : 0);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ BW_SIM_SOPT7_ADC2ALTTRGEN(baseAddr, enable ? 1 : 0);
+ break;
+ case 3:
+ BW_SIM_SOPT7_ADC3ALTTRGEN(baseAddr, enable ? 1 : 0);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance)
+{
+ bool retValue = false;
+
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = BR_SIM_SOPT7_ADC0ALTTRGEN(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ retValue = BR_SIM_SOPT7_ADC1ALTTRGEN(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ retValue = BR_SIM_SOPT7_ADC2ALTTRGEN(baseAddr);
+ break;
+ case 3:
+ retValue = BR_SIM_SOPT7_ADC3ALTTRGEN(baseAddr);
+ break;
+#endif
+#endif
+ default:
+ retValue = false;
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance, sim_pretrgsel_t select)
+{
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT7_ADC0PRETRGSEL(baseAddr, select);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ BW_SIM_SOPT7_ADC1PRETRGSEL(baseAddr, select);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ BW_SIM_SOPT7_ADC2PRETRGSEL(baseAddr, select);
+ break;
+ case 3:
+ BW_SIM_SOPT7_ADC3PRETRGSEL(baseAddr, select);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_pretrgsel_t SIM_HAL_GetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_pretrgsel_t retValue = (sim_pretrgsel_t)0;
+
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC0PRETRGSEL(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC1PRETRGSEL(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC2PRETRGSEL(baseAddr);
+ break;
+ case 3:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC3PRETRGSEL(baseAddr);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(uint32_t baseAddr, uint8_t instance, sim_trgsel_t select)
+{
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT7_ADC0TRGSEL(baseAddr, select);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ BW_SIM_SOPT7_ADC1TRGSEL(baseAddr, select);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ BW_SIM_SOPT7_ADC2TRGSEL(baseAddr, select);
+ break;
+ case 3:
+ BW_SIM_SOPT7_ADC3TRGSEL(baseAddr, select);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_pretrgsel_t SIM_HAL_GetAdcTriggerMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_pretrgsel_t retValue =(sim_pretrgsel_t)0;
+
+ assert(instance < HW_ADC_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC0TRGSEL(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 1)
+ case 1:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC1TRGSEL(baseAddr);
+ break;
+#if (HW_ADC_INSTANCE_COUNT > 2)
+ case 2:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC2TRGSEL(baseAddr);
+ break;
+ case 3:
+ retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC3TRGSEL(baseAddr);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_rxsrc_t select)
+{
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT5_UART0RXSRC(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT5_UART1RXSRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_uart_rxsrc_t)BR_SIM_SOPT5_UART0RXSRC(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_uart_rxsrc_t)BR_SIM_SOPT5_UART1RXSRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_txsrc_t select)
+{
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT5_UART0TXSRC(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT5_UART1TXSRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_uart_txsrc_t)BR_SIM_SOPT5_UART0TXSRC(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_uart_txsrc_t)BR_SIM_SOPT5_UART1TXSRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description : Set UARTx Open Drain Enable setting
+ * This function will enable/disable the UARTx Open Drain.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance, bool enable)
+{
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT5_UART0ODE(baseAddr, enable ? 1 : 0);
+ break;
+ case 1:
+ BW_SIM_SOPT5_UART1ODE(baseAddr, enable ? 1 : 0);
+ break;
+ case 2:
+ BW_SIM_SOPT5_UART2ODE(baseAddr, enable ? 1 : 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description : Get UARTx Open Drain Enable setting
+ * This function will get UARTx Open Drain Enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance)
+{
+ bool retValue = false;
+
+ assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = BR_SIM_SOPT5_UART0ODE(baseAddr);
+ break;
+ case 1:
+ retValue = BR_SIM_SOPT5_UART1ODE(baseAddr);
+ break;
+ case 2:
+ retValue = BR_SIM_SOPT5_UART2ODE(baseAddr);
+ break;
+ default:
+ break;
+ }
+
+ return retValue;
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t trigger,
+ sim_ftm_trg_src_t select)
+{
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+ assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+ switch (instance)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER
+ case 0:
+ switch (trigger)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM0TRG0SRC(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT4_FTM0TRG1SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER
+ case 3:
+ switch (trigger)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM3TRG0SRC(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT4_FTM3TRG1SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t trigger)
+{
+ sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+ assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+ switch (instance)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER
+ case 0:
+ switch (trigger)
+ {
+ case 0:
+ retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM0TRG0SRC(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM0TRG1SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER
+ case 3:
+ switch (trigger)
+ {
+ case 0:
+ retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM3TRG0SRC(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM3TRG1SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance, sim_ftm_clk_sel_t select)
+{
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM0CLKSEL(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT4_FTM1CLKSEL(baseAddr, select);
+ break;
+ case 2:
+ BW_SIM_SOPT4_FTM2CLKSEL(baseAddr, select);
+ break;
+#if (HW_FTM_INSTANCE_COUNT > 3)
+ case 3:
+ BW_SIM_SOPT4_FTM3CLKSEL(baseAddr, select);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM0CLKSEL(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM1CLKSEL(baseAddr);
+ break;
+ case 2:
+ retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM2CLKSEL(baseAddr);
+ break;
+#if (HW_FTM_INSTANCE_COUNT > 3)
+ case 3:
+ retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM3CLKSEL(baseAddr);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t channel,
+ sim_ftm_ch_src_t select)
+{
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS
+ case 1:
+ switch (channel)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM1CH0SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS
+ case 2:
+ switch (channel)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM2CH0SRC(baseAddr, select);
+ break;
+#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1
+ case 1:
+ BW_SIM_SOPT4_FTM2CH1SRC(baseAddr, select);
+ break;
+#endif
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS
+ case 3:
+ switch (channel)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM3CH0SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel)
+{
+ sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+#if FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS
+ case 1:
+ switch (channel)
+ {
+ case 0:
+ retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM1CH0SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS
+ case 2:
+ switch (channel)
+ {
+ case 0:
+ retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM2CH0SRC(baseAddr);
+ break;
+#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1
+ case 1:
+ retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM2CH1SRC(baseAddr);
+ break;
+#endif
+ default:
+ break;
+ }
+ break;
+#endif
+#if FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS
+ case 3:
+ switch (channel)
+ {
+ case 0:
+ retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM3CH0SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t fault,
+ sim_ftm_flt_sel_t select)
+{
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ switch (fault)
+ {
+ case 0:
+ BW_SIM_SOPT4_FTM0FLT0(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT4_FTM0FLT1(baseAddr, select);
+ break;
+#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 2)
+ case 2:
+ BW_SIM_SOPT4_FTM0FLT2(baseAddr, select);
+ break;
+#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 3)
+ case 3:
+ BW_SIM_SOPT4_FTM0FLT3(baseAddr, select);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+ break;
+ case 1:
+ BW_SIM_SOPT4_FTM1FLT0(baseAddr, select);
+ break;
+ case 2:
+ BW_SIM_SOPT4_FTM2FLT0(baseAddr, select);
+ break;
+#if (HW_FTM_INSTANCE_COUNT > 3)
+ case 3:
+ BW_SIM_SOPT4_FTM3FLT0(baseAddr, select);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault)
+{
+ sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+ assert (instance < HW_FTM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ switch (fault)
+ {
+ case 0:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT0(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT1(baseAddr);
+ break;
+#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 2)
+ case 2:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT2(baseAddr);
+ break;
+#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 3)
+ case 3:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT3(baseAddr);
+ break;
+#endif
+#endif
+ default:
+ break;
+ }
+ break;
+ case 1:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM1FLT0(baseAddr);
+ break;
+ case 2:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM2FLT0(baseAddr);
+ break;
+#if (HW_FTM_INSTANCE_COUNT > 3)
+ case 3:
+ retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM3FLT0(baseAddr);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return retValue;
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description : Set Timer/PWM x external clock pin select setting
+ * This function will select the source of Timer/PWM x external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(uint32_t baseAddr,
+ uint8_t instance,
+ sim_tpm_clk_sel_t select)
+{
+ assert (instance < HW_TPM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ BW_SIM_SOPT4_TPM0CLKSEL(baseAddr, select);
+ break;
+ case 1:
+ BW_SIM_SOPT4_TPM1CLKSEL(baseAddr, select);
+ break;
+ case 2:
+ BW_SIM_SOPT4_TPM2CLKSEL(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance)
+{
+ sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+ assert (instance < HW_TPM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 0:
+ retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM0CLKSEL(baseAddr);
+ break;
+ case 1:
+ retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM1CLKSEL(baseAddr);
+ break;
+ case 2:
+ retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM2CLKSEL(baseAddr);
+ break;
+ default:
+ break;
+ }
+
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description : Timer/PWM x channel y input capture source select setting
+ * This function will select Timer/PWM x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t channel,
+ sim_tpm_ch_src_t select)
+{
+ assert (instance < HW_TPM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 1:
+ switch (channel)
+ {
+ case 0:
+ BW_SIM_SOPT4_TPM1CH0SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (channel)
+ {
+ case 0:
+ BW_SIM_SOPT4_TPM2CH0SRC(baseAddr, select);
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t channel)
+{
+ sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+ assert (instance < HW_TPM_INSTANCE_COUNT);
+
+ switch (instance)
+ {
+ case 1:
+ switch (channel)
+ {
+ case 0:
+ retValue = (sim_tpm_ch_src_t)BR_SIM_SOPT4_TPM1CH0SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (channel)
+ {
+ case 0:
+ retValue = (sim_tpm_ch_src_t)BR_SIM_SOPT4_TPM2CH0SRC(baseAddr);
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return retValue;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1620 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_H__)
+#define __FSL_SIM_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_features.h"
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+typedef enum _clock_names {
+
+ /* default clocks*/
+ kCoreClock, /**/
+ kSystemClock, /**/
+ kPlatformClock, /**/
+ kBusClock, /**/
+ kFlexBusClock, /**/
+ kFlashClock, /**/
+
+ /* other internal clocks used by peripherals*/
+ /* osc clock*/
+ kOsc32kClock,
+ kOsc0ErClock,
+ kOsc1ErClock,
+
+ /* irc 48Mhz clock */
+ kIrc48mClock,
+
+ /* rtc clock*/
+ kRtc32kClock,
+ kRtc1hzClock,
+
+ /* lpo clcok*/
+ kLpoClock,
+
+ /* mcg clocks*/
+ kMcgFfClock,
+ kMcgFllClock,
+ kMcgPll0Clock,
+ kMcgPll1Clock,
+ kMcgOutClock,
+ kMcgIrClock,
+
+ /* constant clocks (provided in other header files?)*/
+ kSDHC0_CLKIN,
+ kENET_1588_CLKIN,
+ kEXTAL_Clock,
+ kEXTAL1_Clock,
+ kUSB_CLKIN,
+
+ /* reserved value*/
+ kReserved,
+
+ kClockNameCount
+} clock_names_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+ kClockNfcSrc, /* NFCSRC*/
+ kClockEsdhcSrc, /* ESDHCSRC K70*/
+ kClockSdhcSrc, /* SDHCSRC K64*/
+ kClockLcdcSrc, /* LCDCSRC*/
+ kClockTimeSrc, /* TIMESRC*/
+ kClockRmiiSrc, /* RMIISRC*/
+ kClockUsbfSrc, /* USBFSRC K70*/
+ kClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
+ kClockUsbhSrc, /* USBHSRC*/
+ kClockUart0Src, /* UART0SRC*/
+ kClockLpuartSrc, /* LPUARTSRC K22, KV31 */
+ kClockTpmSrc, /* TPMSRC*/
+ kClockOsc32kSel, /* OSC32KSEL*/
+ kClockUsbfSel, /* USBF_CLKSEL*/
+ kClockPllfllSel, /* PLLFLLSEL*/
+ kClockNfcSel, /* NFC_CLKSEL*/
+ kClockLcdcSel, /* LCDC_CLKSEL*/
+ kClockTraceSel, /* TRACE_CLKSEL*/
+ kClockClkoutSel, /* CLKOUTSEL*/
+ kClockRtcClkoutSel, /* RTCCLKOUTSEL */
+ kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+ kClockDividerOutdiv1, /* OUTDIV1*/
+ kClockDividerOutdiv2, /* OUTDIV2*/
+ kClockDividerOutdiv3, /* OUTDIV3*/
+ kClockDividerOutdiv4, /* OUTDIV4*/
+ kClockDividerUsbFrac, /* (USBFRAC + 1) / (USBDIV + 1)*/
+ kClockDividerUsbDiv,
+ kClockDividerUsbfsFrac, /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+ kClockDividerUsbfsDiv,
+ kClockDividerUsbhsFrac, /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+ kClockDividerUsbhsDiv,
+ kClockDividerLcdcFrac, /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+ kClockDividerLcdcDiv,
+ kClockDividerNfcFrac, /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+ kClockDividerNfcDiv,
+ kClockDividerSpecial1, /* special divider 1*/
+ kClockDividerMax
+} clock_divider_names_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+ kSimUsbsstbyNoRegulator, /* regulator not in standby during Stop modes */
+ kSimUsbsstbyWithRegulator /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+ kSimUsbvstbyNoRegulator, /* regulator not in standby during VLPR and VLPW modes */
+ kSimUsbvstbyWithRegulator /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+ kSimCmtuartSinglePad, /* Single-pad drive strength for CMT IRO or UART0_TXD */
+ kSimCmtuartDualPad /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+ kSimPtd7padSinglePad, /* Single-pad drive strength for PTD7 */
+ kSimPtd7padDualPad /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+ kSimFbslLevel0, /* All off-chip accesses (op code and data) via the FlexBus */
+ /* and DDR controller are disallowed */
+ kSimFbslLevel1, /* Undefined */
+ kSimFbslLevel2, /* Off-chip op code accesses are disallowed. Data accesses */
+ /* are allowed */
+ kSimFbslLevel3 /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_pretrgsel
+{
+ kSimAdcPretrgselA, /* Pre-trigger A selected for ADCx */
+ kSimAdcPretrgselB /* Pre-trigger B selected for ADCx */
+} sim_pretrgsel_t;
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_trgsel
+{
+ kSimAdcTrgselExt, /* External trigger */
+ kSimAdcTrgSelHighSpeedComp0, /* High speed comparator 0 asynchronous interrupt */
+ kSimAdcTrgSelHighSpeedComp1, /* High speed comparator 1 asynchronous interrupt */
+ kSimAdcTrgSelHighSpeedComp2, /* High speed comparator 2 asynchronous interrupt */
+ kSimAdcTrgSelPit0, /* PIT trigger 0 */
+ kSimAdcTrgSelPit1, /* PIT trigger 1 */
+ kSimAdcTrgSelPit2, /* PIT trigger 2 */
+ kSimAdcTrgSelPit3, /* PIT trigger 3 */
+ kSimAdcTrgSelFtm0, /* FTM0 trigger */
+ kSimAdcTrgSelFtm1, /* FTM1 trigger */
+ kSimAdcTrgSelFtm2, /* FTM2 trigger */
+ kSimAdcTrgSelFtm3, /* FTM3 trigger */
+ kSimAdcTrgSelRtcAlarm, /* RTC alarm */
+ kSimAdcTrgSelRtcSec, /* RTC seconds */
+ kSimAdcTrgSelLptimer, /* Low-power timer trigger */
+ kSimAdcTrgSelHigSpeedComp3 /* High speed comparator 3 asynchronous interrupt */
+} sim_trgsel_t;
+
+/*! @brief SIM receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+ kSimUartRxsrcPin, /* UARTx_RX Pin */
+ kSimUartRxsrcCmp0, /* CMP0 */
+ kSimUartRxsrcCmp1, /* CMP1 */
+ kSimUartRxsrcReserved /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+ kSimUartTxsrcPin, /* UARTx_TX Pin */
+ kSimUartTxsrcCmp0, /* UARTx_TX pin modulated with FTM1 channel 0 output */
+ kSimUartTxsrcCmp1, /* UARTx_TX pin modulated with FTM2 channel 0 output */
+ kSimUartTxsrcReserved /* Reserved */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+ kSimFtmTrgSrc0, /* FlexTimer x trigger y select 0 */
+ kSimFtmTrgSrc1 /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+ kSimFtmClkSel0, /* FTM CLKIN0 pin. */
+ kSimFtmClkSel1 /* FTM CLKIN1 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+ kSimFtmChSrc0, /* See RM for details of each selection for each channel */
+ kSimFtmChSrc1, /* See RM for details of each selection for each channel */
+ kSimFtmChSrc2, /* See RM for details of each selection for each channel */
+ kSimFtmChSrc3 /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+ kSimFtmFltSel0, /* FlexTimer x fault y select 0 */
+ kSimFtmFltSel1 /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+ kSimTpmClkSel0, /* Timer/PWM TPM_CLKIN0 pin. */
+ kSimTpmClkSel1 /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+ kSimTpmChSrc0, /* TPMx_CH0 signal */
+ kSimTpmChSrc1 /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*! @brief SIM HAL API return status*/
+typedef enum _sim_hal_status {
+ kSimHalSuccess,
+ kSimHalFail,
+ kSimHalNoSuchModule,
+ kSimHalNoSuchClockSrc,
+ kSimHalNoSuchDivider
+} sim_hal_status_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+ bool useOtherRefClock; /*!< if it uses the other ref clock*/
+ clock_names_t otherRefClockName; /*!< other ref clock name*/
+ clock_divider_names_t dividerName; /*!< clock divider name*/
+} clock_name_config_t;
+
+/*! @brief clock name configuration table for specified CPU defined in fsl_clock_module_names_Kxxx.h*/
+extern const clock_name_config_t kClockNameConfigTable[];
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name clock-related feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function sets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the chip reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting Setting value
+ * @return status If the clock source doesn't exist, it returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(uint32_t baseAddr, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting Current setting pointer for the clock source
+ * @return status If the clock source doesn't exist, it returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(uint32_t baseAddr, clock_source_names_t clockSource,
+ uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting Divider setting
+ * @return status If the clock divider doesn't exist, it returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider,
+ uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param outdiv1 Outdivider1 setting
+ * @param outdiv2 Outdivider2 setting
+ * @param outdiv3 Outdivider3 setting
+ * @param outdiv4 Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDividers(uint32_t baseAddr, uint32_t outdiv1, uint32_t outdiv2,
+ uint32_t outdiv3, uint32_t outdiv4);
+
+/*!
+ * @brief Gets the clock divider setting.
+ *
+ * This function gets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting Divider value pointer
+ * @return status If the clock divider doesn't exist, it returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider,
+ uint32_t *setting);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return size RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT1_RAMSIZE(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param enable USB voltage regulator enable setting
+ * - true: USB voltage regulator is enabled.
+ * - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SIM_SOPT1_USBREGEN(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function gets the USB voltage regulator enabled setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT1_USBREGEN(baseAddr);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting USB voltage regulator in standby mode setting
+ * - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ * VLLS modes.
+ * - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ * modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr,
+ sim_usbsstby_stop_t setting)
+{
+ BW_SIM_SOPT1_USBSSTBY(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr)
+{
+ return (sim_usbsstby_stop_t)BR_SIM_SOPT1_USBSSTBY(baseAddr);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting USB voltage regulator in standby mode setting
+ * - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr,
+ sim_usbvstby_stop_t setting)
+{
+ BW_SIM_SOPT1_USBVSTBY(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr)
+{
+ return (sim_usbvstby_stop_t)BR_SIM_SOPT1_USBVSTBY(baseAddr);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function controls whether the USB voltage regulator stop standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param enable USB voltage regulator stop standby write enable setting
+ * - true: SOPT1[USBSSTBY] can be written.
+ * - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SIM_SOPT1CFG_USSWE(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT1CFG_USSWE(baseAddr);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param enable USB voltage regulator VLP standby write enable setting
+ * - true: SOPT1[USBSSTBY] can be written.
+ * - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SIM_SOPT1CFG_UVSWE(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT1CFG_UVSWE(baseAddr);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param enable USB voltage regulator enable write enable setting
+ * - true: SOPT1[USBSSTBY] can be written.
+ * - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(uint32_t baseAddr, bool enable)
+{
+ BW_SIM_SOPT1CFG_URWE(baseAddr, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function gets the USB voltage regulator enable write enable setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT1CFG_URWE(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting CMT/UART pad drive strength setting
+ * - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ * - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(uint32_t baseAddr,
+ sim_cmtuartpad_strengh_t setting)
+{
+ BW_SIM_SOPT2_CMTUARTPAD(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function gets the CMT/UART pad drive strength setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(uint32_t baseAddr)
+{
+ return (sim_cmtuartpad_strengh_t)BR_SIM_SOPT2_CMTUARTPAD(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting PTD7 pad drive strength setting
+ * - 0: Single-pad drive strength for PTD7.
+ * - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(uint32_t baseAddr,
+ sim_ptd7pad_strengh_t setting)
+{
+ BW_SIM_SOPT2_PTD7PAD(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function gets the PTD7 pad drive strength setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(uint32_t baseAddr)
+{
+ return (sim_ptd7pad_strengh_t)BR_SIM_SOPT2_PTD7PAD(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting FlexBus security level setting
+ * - 00: All off-chip accesses (op code and data) via the FlexBus and
+ * DDR controller are disallowed.
+ * - 10: Off-chip op code accesses are disallowed. Data accesses are
+ * allowed.
+ * - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(uint32_t baseAddr,
+ sim_flexbus_security_level_t setting)
+{
+ BW_SIM_SOPT2_FBSL(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function gets the FlexBus security level setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(uint32_t baseAddr)
+{
+ return (sim_flexbus_security_level_t)BR_SIM_SOPT2_FBSL(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(uint32_t baseAddr, uint32_t setting)
+{
+ BW_SIM_SOPT6_PCR(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function gets the PCR setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT6_PCR(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function sets the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(uint32_t baseAddr, uint32_t setting)
+{
+ BW_SIM_SOPT6_MCC(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function gets the MCC setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(uint32_t baseAddr)
+{
+ return BR_SIM_SOPT6_MCC(baseAddr);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ * - true: Select alternative conversion trigger.
+ * - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return enabled True if ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select pre-trigger select setting for ADCx
+ * - 0: Pre-trigger A selected for ADCx.
+ * - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance, sim_pretrgsel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function gets the ADCx pre-trigger select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_pretrgsel_t SIM_HAL_GetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select trigger select setting for ADCx
+ * - 0000: External trigger
+ * - 0001: High speed comparator 0 asynchronous interrupt
+ * - 0010: High speed comparator 1 asynchronous interrupt
+ * - 0011: High speed comparator 2 asynchronous interrupt
+ * - 0100: PIT trigger 0
+ * - 0101: PIT trigger 1
+ * - 0110: PIT trigger 2
+ * - 0111: PIT trigger 3
+ * - 1000: FTM0 trigger
+ * - 1001: FTM1 trigger
+ * - 1010: FTM2 trigger
+ * - 1011: FTM3 trigger
+ * - 1100: RTC alarm
+ * - 1101: RTC seconds
+ * - 1110: Low-power timer trigger
+ * - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(uint32_t baseAddr, uint8_t instance, sim_trgsel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function gets the ADCx trigger select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select ADCx trigger select setting
+ */
+sim_pretrgsel_t SIM_HAL_GetAdcTriggerMode(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function selects the source for the UARTx receive data.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select the source for the UARTx receive data
+ * - 00: UARTx_RX pin.
+ * - 01: CMP0.
+ * - 10: CMP1.
+ * - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function gets the UARTx receive data source select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function selects the source for the UARTx transmit data.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select the source for the UARTx transmit data
+ * - 00: UARTx_TX pin.
+ * - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ * - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ * - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function gets the UARTx transmit data source select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(uint32_t baseAddr, uint8_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function enables/disables the UARTx Open Drain.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ * - True: Enable UARTx Open Drain
+ * - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function gets the UARTx Open Drain Enable setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function selects the source of FTMx hardware trigger y.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param trigger hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ * - 0: Pre-trigger A selected for ADCx.
+ * - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(uint32_t baseAddr,
+ uint8_t instance,
+ uint8_t trigger,
+ sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param trigger hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function selects the source of FTMx external clock pin select.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select FTMx external clock pin select
+ * - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ * - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance, sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function selects the FlexTimer x channel y input capture source.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param channel FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ * See the reference manual for detailed definition for each channel and selection.
+ */
+void SIM_HAL_SetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture source select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param channel FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function sets the FlexTimer x fault y select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param fault fault y
+ * @param select FlexTimer x fault y select setting
+ * - 0: FlexTimer x fault y select 0.
+ * - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function gets the FlexTimer x fault y select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param fault fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param select Timer/PWM x external clock pin select
+ * - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ * - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function selects the Timer/PWM x channel y input capture source.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param channel TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ * - 0: TPMx_CH0 signal
+ * - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param instance device instance.
+ * @param channel Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_FAMILYID(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_SUBFAMID(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_SERIESID(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_FAMID(baseAddr);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_PINID(baseAddr);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_REVID(baseAddr);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_DIEID(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(uint32_t baseAddr)
+{
+ return BR_SIM_SDID_SRAMSIZE(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG1_NVMSIZE(baseAddr);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG1_PFSIZE(baseAddr);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG1_EESIZE(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG1_DEPART(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(uint32_t baseAddr, uint32_t setting)
+{
+ BW_SIM_FCFG1_FLASHDOZE(baseAddr, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG1_FLASHDOZE(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(uint32_t baseAddr, bool disable)
+{
+ BW_SIM_FCFG1_FLASHDIS(baseAddr, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(uint32_t baseAddr)
+{
+ return (bool)BR_SIM_FCFG1_FLASHDIS(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG2_MAXADDR0(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG2_MAXADDR1(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG2_MAXADDR01(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG2_MAXADDR23(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param baseAddr Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(uint32_t baseAddr)
+{
+ return BR_SIM_FCFG2_PFLSH(baseAddr);
+}
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+/*
+ * Include the CPU-specific clock API header files.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+ defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+ #define K02F12810_SERIES
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+ defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+ defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+ defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+ defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+ defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+ defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+ defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+ defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+ defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+ #define K20D5_SERIES
+
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+ defined(CPU_MK22FN128VMP10))
+
+ #define K22F12810_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F12810/fsl_sim_hal_K22F12810.h"
+
+#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \
+ defined(CPU_MK22FN256VMP12))
+
+ #define K22F25612_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F25612/fsl_sim_hal_K22F25612.h"
+
+
+
+#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12))
+
+ #define K22F51212_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK22F51212/fsl_sim_hal_K22F51212.h"
+
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12))
+
+ #define K24F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK24F12/fsl_sim_hal_K24F12.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+ #define K24F25612_SERIES
+
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+ #define K63F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK63F12/fsl_sim_hal_K63F12.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+ defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+ defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+ #define K64F12_SERIES
+
+ /* Clock System Level API header file */
+ #include "MK64F12/fsl_sim_hal_K64F12.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+ defined(CPU_MK65FX1M0VMI18))
+
+ #define K65F18_SERIES
+
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+ defined(CPU_MK66FX1M0VMD18))
+
+ #define K66F18_SERIES
+
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+ defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+ defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+ #define K70F12_SERIES
+
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+ defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+ defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+ #define K70F15_SERIES
+
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+ defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+ defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+ #define KL02Z4_SERIES
+
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+ defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+ defined(CPU_MKL03Z32VFK4))
+
+ #define KL03Z4_SERIES
+
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+ defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+ defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+ defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+ #define KL05Z4_SERIES
+
+
+#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \
+ defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \
+ defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
+ defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4))
+
+ #define KL13Z4_SERIES
+
+
+#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \
+ defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \
+ defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
+ defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4))
+
+ #define KL23Z4_SERIES
+
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+ defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+ defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+ defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+ #define KL25Z4_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKL25Z4/fsl_sim_hal_KL25Z4.h"
+
+#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \
+ defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \
+ defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
+ defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \
+ defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4))
+
+ #define KL26Z4_SERIES
+
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+ defined(CPU_MKL33Z256VMP4))
+
+ #define KL33Z4_SERIES
+
+
+#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \
+ defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4))
+
+ #define KL43Z4_SERIES
+
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+ defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4))
+
+ #define KL46Z4_SERIES
+
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+ defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+ #define KV30F12810_SERIES
+
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+ #define KV31F12810_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F12810/fsl_sim_hal_KV31F12810.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+ #define KV31F25612_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F25612/fsl_sim_hal_KV31F25612.h"
+
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+ #define KV31F51212_SERIES
+
+ /* Clock System Level API header file */
+ #include "MKV31F51212/fsl_sim_hal_KV31F51212.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+ defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+ #define KV40F15_SERIES
+
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+ #define KV43F15_SERIES
+
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+ #define KV44F15_SERIES
+
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+ defined(CPU_MKV45F256VLL15))
+
+ #define KV45F15_SERIES
+
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+ defined(CPU_MKV46F256VLL15))
+
+ #define KV46F15_SERIES
+
+
+#else
+ #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_SIM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,245 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_SMC_FEATURES_H__) +#define __FSL_SMC_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ + defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ + defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (1) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (0) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (0) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ + defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ + defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ + defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ + defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (0) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (0) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (1) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (1) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (0) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (0) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (0) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (0) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (0) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (1) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ + defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (1) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (1) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (0) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ + defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ + defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ + defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ + defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ + defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ + defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ + defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ + defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ + defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ + defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (1) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (0) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (0) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ + #define FSL_FEATURE_SMC_HAS_PSTOPO (1) + /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ + #define FSL_FEATURE_SMC_HAS_LPOPO (1) + /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ + #define FSL_FEATURE_SMC_HAS_PORPO (1) + /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ + #define FSL_FEATURE_SMC_HAS_LPWUI (0) + /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ + #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) + /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) + /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ + #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) + /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ + #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) + /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ + #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) + /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ + #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_SMC_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,671 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_smc_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetMode
+ * Description : Config the power mode
+ * This function will configure the power mode control for any run, stop and
+ * stop submode if needed. It will also configure the power options for specific
+ * power mode. Application should follow the proper procedure to configure and
+ * switch power mode between the different run and stop mode. Refer to reference
+ * manual for the proper procedure and supported power mode that can be configured
+ * and switch between each other. Refert to smc_power_mode_config_t for required
+ * parameters to configure the power mode and the supported options. Other options
+ * may need to configure through the hal driver individaully. Refer to hal driver
+ * header for details.
+ *
+ *END**************************************************************************/
+smc_hal_error_code_t SMC_HAL_SetMode(uint32_t baseAddr, const smc_power_mode_config_t *powerModeConfig)
+{
+ smc_hal_error_code_t retCode = kSmcHalSuccess;
+ uint8_t currentStat;
+ volatile unsigned int dummyread;
+ smc_stop_mode_t stopMode;
+ smc_run_mode_t runMode;
+ power_mode_stat_t modeStat;
+ power_modes_t powerModeName = powerModeConfig->powerModeName;
+
+ /* verify the power mode name*/
+ assert(powerModeName < kPowerModeMax);
+
+#if FSL_FEATURE_SMC_HAS_LPWUI
+ /* check lpwui option*/
+ if (powerModeConfig->lpwuiOption)
+ {
+ /* check current stat*/
+ currentStat = SMC_HAL_GetStat(baseAddr);
+
+ /* if not in VLPR stat, could not set to RUN*/
+ if (currentStat == kStatRun)
+ {
+ SMC_HAL_SetLpwuiMode(baseAddr, powerModeConfig->lpwuiOptionValue);
+ }
+ }
+#endif
+
+ /* branch based on power mode name*/
+ switch (powerModeName)
+ {
+ case kPowerModeRun:
+ case kPowerModeVlpr:
+ if (powerModeName == kPowerModeRun)
+ {
+ /* mode setting for normal RUN*/
+ runMode = kSmcRun;
+ modeStat = kStatVlpr;
+ }
+ else
+ {
+ /* mode setting for VLPR*/
+ runMode = kSmcVlpr;
+ modeStat = kStatRun;
+ }
+
+ /* check current stat*/
+ currentStat = SMC_HAL_GetStat(baseAddr);
+
+ /* if not in VLPR stat, could not set to RUN*/
+ if (currentStat != modeStat)
+ {
+ retCode = kSmcHalFailed;
+ }
+ else
+ {
+ /* set power mode to normal RUN or VLPR*/
+ SMC_HAL_SetRunMode(baseAddr, runMode);
+ }
+ break;
+
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ case kPowerModeHsrun:
+ /* mode setting for HSRUN (high speed run) */
+ runMode = kSmcHsrun;
+ modeStat = kStatRun;
+
+ /* check current stat*/
+ currentStat = SMC_HAL_GetStat(baseAddr);
+
+ if (currentStat != modeStat)
+ {
+ /* if not in the mode, return error*/
+ retCode = kSmcHalFailed;
+ }
+ else
+ {
+ /* set power mode to normal RUN or VLPR mode first*/
+ SMC_HAL_SetRunMode(baseAddr, runMode);
+ }
+
+ break;
+#endif
+
+ case kPowerModeWait:
+ case kPowerModeVlpw:
+ if (powerModeName == kPowerModeWait)
+ {
+ /* mode setting for normal RUN*/
+ runMode = kSmcRun;
+ modeStat = kStatRun;
+ }
+ else
+ {
+ /* mode setting for VLPR*/
+ runMode = kSmcVlpr;
+ modeStat = kStatVlpr;
+ }
+
+ /* check current stat*/
+ currentStat = SMC_HAL_GetStat(baseAddr);
+
+ if (currentStat != modeStat)
+ {
+ /* if not in the mode, return error*/
+ retCode = kSmcHalFailed;
+ }
+ else
+ {
+ /* set power mode to normal RUN or VLPR mode first*/
+ SMC_HAL_SetRunMode(baseAddr, runMode);
+ }
+
+ if (retCode == kSmcHalSuccess)
+ {
+ /* Clear the SLEEPDEEP bit to disable deep sleep mode - enter wait mode*/
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+ }
+ break;
+
+ case kPowerModeStop:
+ case kPowerModeVlps:
+ case kPowerModeLls:
+ if (powerModeName == kPowerModeStop)
+ {
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ /* check current stat*/
+ currentStat = SMC_HAL_GetStat(baseAddr);
+
+ if ((currentStat == kStatHsrun) || (SMC_HAL_GetRunMode(baseAddr) == kSmcHsrun))
+ {
+ retCode = kSmcHalFailed;
+ break;
+ }
+#endif
+ stopMode = kSmcStop;
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+ if (powerModeConfig->pstopOption)
+ {
+ SMC_HAL_SetPstopMode(baseAddr, powerModeConfig->pstopOptionValue);
+ }
+#endif
+ }
+ else if (powerModeName == kPowerModeVlps)
+ {
+ stopMode = kSmcVlps;
+ }
+ else
+ {
+ stopMode = kSmcLls;
+ }
+
+ /* set power mode to specified STOP mode*/
+ SMC_HAL_SetStopMode(baseAddr, stopMode);
+
+#if FSL_FEATURE_SMC_HAS_LLS_SUBMODE
+ if (powerModeName == kPowerModeLls)
+ {
+ /* further set the stop sub mode configuration*/
+ SMC_HAL_SetStopSubMode(baseAddr, powerModeConfig->stopSubMode);
+ }
+#endif
+
+ /* wait for write to complete to SMC before stopping core */
+ dummyread = SMC_HAL_GetStat(baseAddr);
+ dummyread = dummyread + 1;
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP)*/
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+
+ break;
+
+ case kPowerModeVlls:
+ /* set power mode to specified STOP mode*/
+ SMC_HAL_SetStopMode(baseAddr, kSmcVlls);
+
+ /* further set the stop sub mode configuration*/
+ SMC_HAL_SetStopSubMode(baseAddr, powerModeConfig->stopSubMode);
+
+ /* check if Vlls0 option needs configuration*/
+ if (powerModeConfig->stopSubMode == kSmcStopSub0)
+ {
+#if FSL_FEATURE_SMC_HAS_PORPO
+ if (powerModeConfig->porOption)
+ {
+ SMC_HAL_SetPorMode(baseAddr, powerModeConfig->porOptionValue);
+ }
+#endif
+ }
+
+ /* wait for write to complete to SMC before stopping core */
+ dummyread = SMC_HAL_GetStat(baseAddr);
+ dummyread = dummyread + 1;
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP)*/
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+
+ break;
+ default:
+ retCode = kSmcHalNoSuchModeName;
+ break;
+ }
+
+ return retCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetProtection
+ * Description : Config all power mode protection settings
+ * This function will configure the power mode protection settings for
+ * supported power mode on the specified chip family. The availabe power modes
+ * are defined in smc_power_mode_protection_config_t. Application should provide
+ * the protect settings for all supported power mode on the chip and aslo this
+ * should be done at early system level init stage. Refer to reference manual
+ * for details. This register can only write once after power reset. So either
+ * use this function or use the individual set function if you only have single
+ * option to set.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetProtection(uint32_t baseAddr, smc_power_mode_protection_config_t *protectConfig)
+{
+ /* initialize the setting */
+ uint8_t regValue = 0;
+
+ /* check configurations for each mode and combine the seting together */
+ if (protectConfig->vlpProt)
+ {
+ regValue |= BF_SMC_PMPROT_AVLP(1);
+ }
+
+ if (protectConfig->llsProt)
+ {
+ regValue |= BF_SMC_PMPROT_ALLS(1);
+ }
+
+ if (protectConfig->vllsProt)
+ {
+ regValue |= BF_SMC_PMPROT_AVLLS(1);
+ }
+
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ if (protectConfig->hsrunProt)
+ {
+ regValue |= BF_SMC_PMPROT_AHSRUN(1);
+ }
+#endif
+
+ /* write once into pmprot register*/
+ HW_SMC_PMPROT_SET(baseAddr, regValue);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetProtectionMode
+ * Description : Config the individual power mode protection setting
+ * This function will only configure the power mode protection settings for
+ * a specified power mode on the specified chip family. The availabe power modes
+ * are defined in smc_power_mode_protection_config_t. Refer to reference manual
+ * for details. This register can only write once after power reset.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect, bool allow)
+{
+ /* check the setting range */
+ assert(protect < kAllowMax);
+
+ /* branch according to mode and write the setting */
+ switch (protect)
+ {
+ case kAllowVlp:
+ if (allow)
+ {
+ BW_SMC_PMPROT_AVLP(baseAddr, 1);
+ }
+ else
+ {
+ BW_SMC_PMPROT_AVLP(baseAddr, 0);
+ }
+ break;
+ case kAllowLls:
+ if (allow)
+ {
+ BW_SMC_PMPROT_ALLS(baseAddr, 1);
+ }
+ else
+ {
+ BW_SMC_PMPROT_ALLS(baseAddr, 0);
+ }
+ break;
+ case kAllowVlls:
+ if (allow)
+ {
+ BW_SMC_PMPROT_AVLLS(baseAddr, 1);
+ }
+ else
+ {
+ BW_SMC_PMPROT_AVLLS(baseAddr, 0);
+ }
+ break;
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ case kAllowHsrun:
+ if (allow)
+ {
+ BW_SMC_PMPROT_AHSRUN(baseAddr, 1);
+ }
+ else
+ {
+ BW_SMC_PMPROT_AHSRUN(baseAddr, 0);
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetProtectionMode
+ * Description : Get the current power mode protection setting
+ * This function will get the current power mode protection settings for
+ * a specified power mode.
+ *
+ *END**************************************************************************/
+bool SMC_HAL_GetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect)
+{
+ bool retValue = false;
+
+ /* check the mode range */
+ assert(protect < kAllowMax);
+
+ /* branch according to the mode and read the setting */
+ switch (protect)
+ {
+ case kAllowVlp:
+ retValue = BR_SMC_PMPROT_AVLP(baseAddr);
+ break;
+ case kAllowLls:
+ retValue = BR_SMC_PMPROT_ALLS(baseAddr);
+ break;
+ case kAllowVlls:
+ retValue = BR_SMC_PMPROT_AVLLS(baseAddr);
+ break;
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ case kAllowHsrun:
+ retValue = BR_SMC_PMPROT_AHSRUN(baseAddr);
+ break;
+#endif
+ default:
+ break;
+ }
+ return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetRunMode
+ * Description : Config the RUN mode control setting
+ * This function will set the run mode settings. For example, normal run mode,
+ * very lower power run mode, etc. Refer to smc_run_mode_t for supported run
+ * mode on the chip family. Refer to reference manual for details about the
+ * run mode.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetRunMode(uint32_t baseAddr, smc_run_mode_t runMode)
+{
+ BW_SMC_PMCTRL_RUNM(baseAddr, runMode);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetRunMode
+ * Description : Get the current RUN mode config
+ * This function will get the run mode settings. Refer to smc_run_mode_t
+ * for supported run mode on the chip family. Refer to reference manual for
+ * details about the run mode.
+ *
+ *END**************************************************************************/
+smc_run_mode_t SMC_HAL_GetRunMode(uint32_t baseAddr)
+{
+ return (smc_run_mode_t)BR_SMC_PMCTRL_RUNM(baseAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetStopMode
+ * Description : Config the STOP mode control setting
+ * This function will set the stop mode settings. For example, normal stop mode,
+ * very lower power stop mode, etc. Refer to smc_stop_mode_t for supported stop
+ * mode on the chip family. Refer to reference manual for details about the
+ * stop mode.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetStopMode(uint32_t baseAddr, smc_stop_mode_t stopMode)
+{
+ BW_SMC_PMCTRL_STOPM(baseAddr, stopMode);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetStopMode
+ * Description : Get the current STOP mode control setting
+ * This function will get the stop mode settings. For example, normal stop mode,
+ * very lower power stop mode, etc. Refer to smc_stop_mode_t for supported stop
+ * mode on the chip family. Refer to reference manual for details about the
+ * stop mode.
+ *
+ *END**************************************************************************/
+smc_stop_mode_t SMC_HAL_GetStopMode(uint32_t baseAddr)
+{
+ return (smc_stop_mode_t)BR_SMC_PMCTRL_STOPM(baseAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetStopSubMode
+ * Description : Config the stop sub mode control setting
+ * This function will set the stop submode settings. Some of the stop mode will
+ * further have submode supported. Refer to smc_stop_submode_t for supported
+ * stop submode and Refer to reference manual for details about the submode
+ * for specific stop mode.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetStopSubMode(uint32_t baseAddr, smc_stop_submode_t stopSubMode)
+{
+#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG
+ BW_SMC_VLLSCTRL_VLLSM(baseAddr, stopSubMode);
+#else
+#if FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM
+ BW_SMC_STOPCTRL_VLLSM(baseAddr, stopSubMode);
+#else
+ BW_SMC_STOPCTRL_LLSM(baseAddr, stopSubMode);
+#endif
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetStopSubMode
+ * Description : Get the current stop submode config
+ * This function will get the stop submode settings. Some of the stop mode will
+ * further have submode supported. Refer to smc_stop_submode_t for supported
+ * stop submode and Refer to reference manual for details about the submode
+ * for specific stop mode.
+ *
+ *END**************************************************************************/
+smc_stop_submode_t SMC_HAL_GetStopSubMode(uint32_t baseAddr)
+{
+#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG
+ return (smc_stop_submode_t)BR_SMC_VLLSCTRL_VLLSM(baseAddr);
+#else
+#if FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM
+ return (smc_stop_submode_t)BR_SMC_STOPCTRL_VLLSM(baseAddr);
+#else
+ return (smc_stop_submode_t)BR_SMC_STOPCTRL_LLSM(baseAddr);
+#endif
+#endif
+}
+
+#if FSL_FEATURE_SMC_HAS_PORPO
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetPorMode
+ * Description : Config the POR (power-on-reset) option
+ * This function will set the POR power option setting. It controls whether the
+ * POR detect circuit (for brown-out detection) is enabled in certain stop mode.
+ * The setting will be either enable or disable the above feature when POR
+ * happened. Refer to reference manual for details.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetPorMode(uint32_t baseAddr, smc_por_option_t option)
+{
+#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG
+ BW_SMC_VLLSCTRL_PORPO(baseAddr, option);
+#else
+ BW_SMC_STOPCTRL_PORPO(baseAddr, option);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetPorMode
+ * Description : Get the config of POR option
+ * This function will set the POR power option setting. See config function
+ * header for details.
+ *
+ *END**************************************************************************/
+smc_por_option_t SMC_HAL_GetPorMode(uint32_t baseAddr)
+{
+#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG
+ return (smc_por_option_t)BR_SMC_VLLSCTRL_PORPO(baseAddr);
+#else
+ return (smc_por_option_t)BR_SMC_STOPCTRL_PORPO(baseAddr);
+#endif
+}
+#endif
+
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetPorMode
+ * Description : Config the PSTOPO (Partial Stop Option)
+ * This function will set the PSTOPO option. It controls whether a Partial
+ * Stop mode is entered when STOPM=STOP. When entering a Partial Stop mode from
+ * RUN mode, the PMC, MCG and flash remain fully powered, allowing the device
+ * to wakeup almost instantaneously at the expense of higher power consumption.
+ * In PSTOP2, only system clocks are gated allowing peripherals running on bus
+ * clock to remain fully functional. In PSTOP1, both system and bus clocks are
+ * gated. Refer to smc_pstop_option_t for supported options. Refer to reference
+ * manual for details.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetPstopMode(uint32_t baseAddr, smc_pstop_option_t option)
+{
+ BW_SMC_STOPCTRL_PSTOPO(baseAddr, option);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetPorMode
+ * Description : Get the config of PSTOPO option
+ * This function will get the current PSTOPO option setting. Refer to config
+ * function for more details.
+ *
+ *END**************************************************************************/
+smc_pstop_option_t SMC_HAL_GetPstopMode(uint32_t baseAddr)
+{
+ return (smc_pstop_option_t)BR_SMC_STOPCTRL_PSTOPO(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SMC_HAS_LPOPO
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetPorMode
+ * Description : Config the LPO option setting
+ * This function will set the LPO option setting. It controls whether the 1kHZ
+ * LPO clock is enabled in certain lower power stop modes. Refer to
+ * smc_lpo_option_t for supported options and refer to reference manual for
+ * details about this option.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetLpoMode(uint32_t baseAddr, smc_lpo_option_t option)
+{
+ BW_SMC_STOPCTRL_LPOPO(baseAddr, option);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetPorMode
+ * Description : Get the config of LPO option
+ * This function will get the current LPO option setting. Refer to config
+ * function for details.
+ *
+ *END**************************************************************************/
+smc_por_option_t SMC_HAL_GetLpoMode(uint32_t baseAddr)
+{
+ return (smc_por_option_t)BR_SMC_STOPCTRL_LPOPO(baseAddr);
+}
+#endif
+
+#if FSL_FEATURE_SMC_HAS_LPWUI
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetLpwuiMode
+ * Description : Config the LPWUI (Low Power Wake Up on interrup) option
+ * This function will set the LPWUI option. It will cause the system to exit
+ * to normal RUN mode when any active interrupt occurs while in a certain lower
+ * power mode. Refer to smc_lpwui_option_t for supported options and refer to
+ * reference manual for more details about this option.
+ *
+ *END**************************************************************************/
+void SMC_HAL_SetLpwuiMode(uint32_t baseAddr, smc_lpwui_option_t option)
+{
+ BW_SMC_PMCTRL_LPWUI(baseAddr, option);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetLpwuiMode
+ * Description : Get the current LPWUI option
+ * This function will get the LPWUI option. Refer to config function for more
+ * details.
+ *
+ *END**************************************************************************/
+smc_lpwui_option_t SMC_HAL_GetLpwuiMode(uint32_t baseAddr)
+{
+ return (smc_lpwui_option_t)BR_SMC_PMCTRL_LPWUI(baseAddr);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetStat
+ * Description : Get the current power mode stat
+ * This function will return the current power mode stat. Once application is
+ * switching the power mode, it should always check the stat to make sure it
+ * runs into the specified mode or not. Also application will need to check
+ * this mode before switching to certain mode. The system will require that
+ * only certain mode could switch to other specific mode. Refer to the
+ * reference manual for details. Refer to _power_mode_stat for the meaning
+ * of the power stat
+ *
+ *END**************************************************************************/
+uint8_t SMC_HAL_GetStat(uint32_t baseAddr)
+{
+ return BR_SMC_PMSTAT_PMSTAT(baseAddr);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SMC_HAL_H__)
+#define __FSL_SMC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_smc_features.h"
+
+/*! @addtogroup smc_hal*/
+/*! @{*/
+
+/*! @file fsl_smc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Power Modes */
+typedef enum _power_modes {
+ kPowerModeRun,
+ kPowerModeWait,
+ kPowerModeStop,
+ kPowerModeVlpr,
+ kPowerModeVlpw,
+ kPowerModeVlps,
+ kPowerModeLls,
+ kPowerModeVlls,
+ kPowerModeHsrun,
+ kPowerModeMax
+} power_modes_t;
+
+/*!
+ * @brief Error code definition for the system mode controller manager APIs.
+ */
+typedef enum _smc_hal_error_code {
+ kSmcHalSuccess, /*!< Success */
+ kSmcHalNoSuchModeName, /*!< Cannot find the mode name specified*/
+ kSmcHalAlreadyInTheState, /*!< Already in the required state*/
+ kSmcHalFailed /*!< Unknown error, operation failed*/
+} smc_hal_error_code_t;
+
+/*! @brief Power Modes in PMSTAT*/
+typedef enum _power_mode_stat {
+ kStatRun = 0x01, /*!< 0000_0001 - Current power mode is RUN*/
+ kStatStop = 0x02, /*!< 0000_0010 - Current power mode is STOP*/
+ kStatVlpr = 0x04, /*!< 0000_0100 - Current power mode is VLPR*/
+ kStatVlpw = 0x08, /*!< 0000_1000 - Current power mode is VLPW*/
+ kStatVlps = 0x10, /*!< 0001_0000 - Current power mode is VLPS*/
+ kStatLls = 0x20, /*!< 0010_0000 - Current power mode is LLS*/
+ kStatVlls = 0x40, /*!< 0100_0000 - Current power mode is VLLS*/
+ kStatHsrun = 0x80 /*!< 1000_0000 - Current power mode is HSRUN*/
+} power_mode_stat_t;
+
+/*! @brief Power Modes Protection*/
+typedef enum _power_modes_protect {
+ kAllowHsrun, /*!< Allow High Speed Run mode*/
+ kAllowVlp, /*!< Allow Very-Low-Power Modes*/
+ kAllowLls, /*!< Allow Low-Leakage Stop Mode*/
+ kAllowVlls, /*!< Allow Very-Low-Leakage Stop Mode*/
+ kAllowMax
+} power_modes_protect_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode {
+ kSmcRun, /*!< normal RUN mode*/
+ kSmcReservedRun,
+ kSmcVlpr, /*!< Very-Low-Power RUN mode*/
+ kSmcHsrun /*!< High Speed Run mode (HSRUN)*/
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode {
+ kSmcStop, /*!< Normal STOP mode*/
+ kSmcReservedStop1, /*!< Reserved*/
+ kSmcVlps, /*!< Very-Low-Power STOP mode*/
+ kSmcLls, /*!< Low-Leakage Stop mode*/
+ kSmcVlls /*!< Very-Low-Leakage Stop mode*/
+} smc_stop_mode_t;
+
+/*!
+ * @brief VLLS/LLS stop sub mode definition
+ */
+typedef enum _smc_stop_submode {
+ kSmcStopSub0,
+ kSmcStopSub1,
+ kSmcStopSub2,
+ kSmcStopSub3
+} smc_stop_submode_t;
+
+/*! @brief Low Power Wake Up on Interrupt option*/
+typedef enum _smc_lpwui_option {
+ kSmcLpwuiEnabled, /*!< Low Power Wake Up on Interrupt enabled*/
+ kSmcLpwuiDisabled /*!< Low Power Wake Up on Interrupt disabled*/
+} smc_lpwui_option_t;
+
+/*! @brief Partial STOP option*/
+typedef enum _smc_pstop_option {
+ kSmcPstopStop, /*!< STOP - Normal Stop mode*/
+ kSmcPstopStop1, /*!< Partial Stop with both system and bus clocks disabled*/
+ kSmcPstopStop2, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+ kSmcPstopReserved,
+} smc_pstop_option_t;
+
+/*! @brief POR option*/
+typedef enum _smc_por_option {
+ kSmcPorEnabled, /*!< POR detect circuit is enabled in VLLS0*/
+ kSmcPorDisabled /*!< POR detect circuit is disabled in VLLS0*/
+} smc_por_option_t;
+
+/*! @brief LPO power option*/
+typedef enum _smc_lpo_option {
+ kSmcLpoEnabled, /*!< LPO clock is enabled in LLS/VLLSx*/
+ kSmcLpoDisabled /*!< LPO clock is disabled in LLS/VLLSx*/
+} smc_lpo_option_t;
+
+/*! @brief Power mode control options*/
+typedef enum _smc_power_options {
+ kSmcOptionLpwui, /*!< Low Power Wake Up on Interrupt*/
+ kSmcOptionPropo /*!< POR option*/
+} smc_power_options_t;
+
+/*! @brief Power mode protection configuration*/
+typedef struct _smc_power_mode_protection_config {
+ bool vlpProt; /*!< VLP protect*/
+ bool llsProt; /*!< LLS protect */
+ bool vllsProt; /*!< VLLS protect*/
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+ bool hsrunProt; /*!< HSRUN protect */
+#endif
+} smc_power_mode_protection_config_t;
+
+/*! @brief Power mode control configuration used for calling the SMC_SYS_SetPowerMode API. */
+typedef struct _smc_power_mode_config {
+ power_modes_t powerModeName; /*!< Power mode(enum), see power_modes_t */
+ smc_stop_submode_t stopSubMode; /*!< Stop submode(enum), see smc_stop_submode_t */
+#if FSL_FEATURE_SMC_HAS_LPWUI
+ bool lpwuiOption; /*!< If LPWUI option is needed */
+ smc_lpwui_option_t lpwuiOptionValue; /*!< LPWUI option(enum), see smc_lpwui_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_PORPO
+ bool porOption; /*!< If POR option is needed */
+ smc_por_option_t porOptionValue; /*!< POR option(enum), see smc_por_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+ bool pstopOption; /*!< If PSTOPO option is needed */
+ smc_pstop_option_t pstopOptionValue; /*!< PSTOPO option(enum), see smc_por_option_t */
+#endif
+} smc_power_mode_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+/*!
+ * @brief Configures the power mode.
+ *
+ * This function configures the power mode control for both run, stop, and
+ * stop sub mode if needed. Also it configures the power options for a specific
+ * power mode. An application should follow the proper procedure to configure and
+ * switch power modes between different run and stop modes. For proper procedures
+ * and supported power modes, see an appropriate chip reference
+ * manual. See the smc_power_mode_config_t for required
+ * parameters to configure the power mode and the supported options. Other options
+ * may need to be individually configured through the HAL driver. See the HAL driver
+ * header file for details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param powerModeConfig Power mode configuration structure smc_power_mode_config_t
+ * @return errorCode SMC error code
+ */
+smc_hal_error_code_t SMC_HAL_SetMode(uint32_t baseAddr,
+ const smc_power_mode_config_t *powerModeConfig);
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_config_t. An application should provide
+ * the protect settings for all supported power modes on the chip. This
+ * should be done at an early system level initialization stage. See the reference manual
+ * for details. This register can only write once after the power reset. If the user has
+ * only a single option to set,
+ * either use this function or use the individual set function.
+ *
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param protectConfig Configurations for the supported power mode protect settings
+ * - See smc_power_mode_protection_config_t for details.
+ */
+void SMC_HAL_SetProtection(uint32_t baseAddr, smc_power_mode_protection_config_t *protectConfig);
+
+/*!
+ * @brief Configures the individual power mode protection settings.
+ *
+ * This function only configures the power mode protection settings for
+ * a specified power mode on the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_config_t. See the reference manual
+ * for details. This register can only write once after the power reset.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param protect Power mode to set for protection
+ * @param allow Allow or not allow the power mode protection
+ */
+void SMC_HAL_SetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect, bool allow);
+
+/*!
+ * @brief Gets the the current power mode protection setting.
+ *
+ * This function gets the current power mode protection settings for
+ * a specified power mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param protect Power mode to set for protection
+ * @return state Status of the protection setting
+ * - true: Allowed
+ * - false: Not allowed
+*/
+bool SMC_HAL_GetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect);
+
+/*!
+ * @brief Configures the the RUN mode control setting.
+ *
+ * This function sets the run mode settings, for example, normal run mode,
+ * very lower power run mode, etc. See the smc_run_mode_t for supported run
+ * mode on the chip family and the reference manual for details about the
+ * run mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param runMode Run mode setting defined in smc_run_mode_t
+ */
+void SMC_HAL_SetRunMode(uint32_t baseAddr, smc_run_mode_t runMode);
+
+/*!
+ * @brief Gets the current RUN mode configuration setting.
+ *
+ * This function gets the run mode settings. See the smc_run_mode_t
+ * for a supported run mode on the chip family and the reference manual for
+ * details about the run mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return setting Run mode configuration setting
+ */
+smc_run_mode_t SMC_HAL_GetRunMode(uint32_t baseAddr);
+
+/*!
+ * @brief Configures the STOP mode control setting.
+ *
+ * This function sets the stop mode settings, for example, normal stop mode,
+ * very lower power stop mode, etc. See the smc_stop_mode_t for supported stop
+ * mode on the chip family and the reference manual for details about the
+ * stop mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param stopMode Stop mode defined in smc_stop_mode_t
+ */
+void SMC_HAL_SetStopMode(uint32_t baseAddr, smc_stop_mode_t stopMode);
+
+/*!
+ * @brief Gets the current STOP mode control settings.
+ *
+ * This function gets the stop mode settings, for example, normal stop mode,
+ * very lower power stop mode, etc. See the smc_stop_mode_t for supported stop
+ * mode on the chip family and the reference manual for details about the
+ * stop mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return setting Current stop mode configuration setting
+ */
+smc_stop_mode_t SMC_HAL_GetStopMode(uint32_t baseAddr);
+
+/*!
+ * @brief Configures the stop sub mode control setting.
+ *
+ * This function sets the stop submode settings. Some of the stop mode
+ * further supports submodes. See the smc_stop_submode_t for supported
+ * stop submodes and the reference manual for details about the submodes
+ * for a specific stop mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param stopSubMode Stop submode setting defined in smc_stop_submode_t
+ */
+void SMC_HAL_SetStopSubMode(uint32_t baseAddr, smc_stop_submode_t stopSubMode);
+
+/*!
+ * @brief Gets the current stop submode configuration settings.
+ *
+ * This function gets the stop submode settings. Some of the stop mode
+ * further support submodes. See the smc_stop_submode_t for supported
+ * stop submodes and the reference manual for details about the submode
+ * for a specific stop mode.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return setting Current stop submode setting
+*/
+smc_stop_submode_t SMC_HAL_GetStopSubMode(uint32_t baseAddr);
+
+#if FSL_FEATURE_SMC_HAS_PORPO
+/*!
+ * @brief Configures the POR (power-on-reset) option.
+ *
+ * This function sets the POR power option setting. It controls whether the
+ * POR detect circuit (for brown-out detection) is enabled in a certain stop mode.
+ * The setting either enables or disables the above feature when the POR
+ * occurs. See the reference manual for details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param option POR option setting refer to smc_por_option_t
+ */
+void SMC_HAL_SetPorMode(uint32_t baseAddr, smc_por_option_t option);
+
+/*!
+ * @brief Gets the configuration settings for the POR option.
+ *
+ * This function sets the POR power option setting. See the configuration function
+ * header for details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return option Current POR option setting
+*/
+smc_por_option_t SMC_HAL_GetPorMode(uint32_t baseAddr);
+#endif
+
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+/*!
+ * @brief Configures the PSTOPO (Partial Stop Option).
+ *
+ * This function sets the PSTOPO option. It controls whether a Partial
+ * Stop mode is entered when the STOPM=STOP. When entering a Partial Stop mode from the
+ * RUN mode, the PMC, MCG and Flash remain fully powered allowing the device
+ * to wakeup almost instantaneously at the expense of a higher power consumption.
+ * In PSTOP2, only the system clocks are gated, which allows the peripherals running on bus
+ * clock to remain fully functional. In PSTOP1, both system and bus clocks are
+ * gated. Refer to the smc_pstop_option_t for supported options. See the reference
+ * manual for details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param option PSTOPO option setting defined in smc_pstop_option_t
+ */
+void SMC_HAL_SetPstopMode(uint32_t baseAddr, smc_pstop_option_t option);
+
+/*!
+ * @brief Gets the configuration of the PSTOPO option.
+ *
+ * This function gets the current PSTOPO option setting. See the configuration
+ * function for more details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return option Current PSTOPO option setting
+ */
+smc_pstop_option_t SMC_HAL_GetPstopMode(uint32_t baseAddr);
+#endif
+
+#if FSL_FEATURE_SMC_HAS_LPOPO
+/*!
+ * @brief Configures the LPO option setting.
+ *
+ * This function sets the LPO option setting. It controls whether the 1 kHZ
+ * LPO clock is enabled in a certain lower power stop modes. See the
+ * smc_lpo_option_t for supported options and the reference manual for
+ * details about this option.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param option LPO option setting defined in smc_lpo_option_t
+ */
+void SMC_HAL_SetLpoMode(uint32_t baseAddr, smc_lpo_option_t option);
+
+/*!
+ * @brief Gets the settings of the LPO option.
+ *
+ * This function gets the current LPO option setting. See the configuration
+ * function for details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return option Current LPO option setting
+ */
+smc_por_option_t SMC_HAL_GetLpoMode(uint32_t baseAddr);
+#endif
+
+#if FSL_FEATURE_SMC_HAS_LPWUI
+/*!
+ * @brief Configures the LPWUI (Low Power Wake Up on interrupt) option.
+ *
+ * This function sets the LPWUI option and cause the system to exit
+ * to normal RUN mode when any active interrupt occurs while in a specific lower
+ * power mode. See the smc_lpwui_option_t for supported options and the
+ * reference manual for more details about this option.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @param option LPWUI option setting defined in smc_lpwui_option_t
+ */
+void SMC_HAL_SetLpwuiMode(uint32_t baseAddr, smc_lpwui_option_t option);
+
+/*!
+ * @brief Gets the current LPWUI option.
+ *
+ * This function gets the LPWUI option. See the configuration function for more
+ * details.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return setting Current LPWAUI option setting
+ */
+smc_lpwui_option_t SMC_HAL_GetLpwuiMode(uint32_t baseAddr);
+#endif
+
+/*!
+ * @brief Gets the current power mode stat.
+ *
+ * This function returns the current power mode stat. Once application
+ * switches the power mode, it should always check the stat to check whether it
+ * runs into the specified mode or not. An application should check
+ * this mode before switching to a different mode. The system requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the _power_mode_stat for information about
+ * the power stat.
+ *
+ * @param baseAddr Base address for current SMC instance.
+ * @return stat Current power mode stat
+ */
+uint8_t SMC_HAL_GetStat(uint32_t baseAddr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SMC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,1218 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_UART_FEATURES_H__) +#define __FSL_UART_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ + defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : (-1))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : (-1))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : (-1)))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : \ + ((x) == 2 ? (10) : (-1)))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : (-1))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : (-1))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : (-1)))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : \ + ((x) == 2 ? (10) : (-1)))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ + defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (8) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : \ + ((x) == 3 ? (9) : \ + ((x) == 4 ? (9) : \ + ((x) == 5 ? (9) : (-1))))))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : \ + ((x) == 2 ? (10) : \ + ((x) == 3 ? (10) : \ + ((x) == 4 ? (10) : \ + ((x) == 5 ? (10) : (-1))))))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ + defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (8) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : \ + ((x) == 3 ? (9) : \ + ((x) == 4 ? (9) : (-1)))))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : \ + ((x) == 2 ? (10) : \ + ((x) == 3 ? (10) : \ + ((x) == 4 ? (10) : (-1)))))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : (-1)))))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : (-1)))))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ + defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (8) : \ + ((x) == 2 ? (8) : \ + ((x) == 3 ? (8) : \ + ((x) == 4 ? (8) : \ + ((x) == 5 ? (8) : (-1))))))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : \ + ((x) == 3 ? (9) : \ + ((x) == 4 ? (9) : \ + ((x) == 5 ? (9) : (-1))))))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : \ + ((x) == 2 ? (10) : \ + ((x) == 3 ? (10) : \ + ((x) == 4 ? (10) : \ + ((x) == 5 ? (10) : (-1))))))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : \ + ((x) == 3 ? (1) : \ + ((x) == 4 ? (1) : \ + ((x) == 5 ? (1) : (-1))))))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : \ + ((x) == 3 ? (0) : \ + ((x) == 4 ? (0) : \ + ((x) == 5 ? (0) : (-1))))))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ + defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ + defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (0) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (0) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (10) : (-1)) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (9) : (-1)) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (0) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ + defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ + defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ + defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ + defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ + defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ + defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ + defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ + defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : (-1)) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : (-1)) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : (-1)) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (1) : (-1)) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : (-1)) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ + defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ + defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \ + defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ + defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (0) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (0) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (9) : \ + ((x) == 2 ? (9) : (-1)))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (8) : \ + ((x) == 2 ? (8) : (-1)))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (1) : \ + ((x) == 2 ? (1) : (-1)))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : \ + ((x) == 2 ? (0) : (-1)))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ + defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ + defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ + defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ + defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZE (8) + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == 0 ? (8) : \ + ((x) == 1 ? (8) : (-1))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ + ((x) == 0 ? (9) : \ + ((x) == 1 ? (9) : (-1))) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ + ((x) == 0 ? (10) : \ + ((x) == 1 ? (10) : (-1))) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ + ((x) == 0 ? (1) : \ + ((x) == 1 ? (1) : (-1))) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ + ((x) == 0 ? (0) : \ + ((x) == 1 ? (0) : (-1))) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_UART_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,961 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_uart_hal.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*******************************************************************************
+ * UART Common Configurations
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Init
+ * Description : This function initializes the module to a known state.
+ *
+ *END**************************************************************************/
+void UART_HAL_Init(uint32_t baseAddr)
+{
+ HW_UART_BDH_WR(baseAddr, 0U);
+ HW_UART_BDL_WR(baseAddr, 4U);
+ HW_UART_C1_WR(baseAddr, 0U);
+ HW_UART_C2_WR(baseAddr, 0U);
+ HW_UART_S2_WR(baseAddr, 0U);
+ HW_UART_C3_WR(baseAddr, 0U);
+ HW_UART_D_WR(baseAddr, 0U);
+#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+ HW_UART_MA1_WR(baseAddr, 0U);
+ HW_UART_MA2_WR(baseAddr, 0U);
+#endif
+ HW_UART_C4_WR(baseAddr, 0U);
+#if FSL_FEATURE_UART_HAS_DMA_ENABLE
+ HW_UART_C5_WR(baseAddr, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+ HW_UART_MODEM_WR(baseAddr, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+ HW_UART_IR_WR(baseAddr, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+ HW_UART_PFIFO_WR(baseAddr, 0U);
+ HW_UART_CFIFO_WR(baseAddr, 0U);
+ HW_UART_SFIFO_WR(baseAddr, 0xC0U);
+ HW_UART_TWFIFO_WR(baseAddr, 0U);
+ HW_UART_RWFIFO_WR(baseAddr, 1U);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetBaudRate
+ * Description : Configure the UART baud rate.
+ * This function programs the UART baud rate to the desired value passed in by the
+ * user. The user must also pass in the module source clock so that the function can
+ * calculate the baud rate divisors to their appropriate values.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t baudRate)
+{
+ /* BaudRate = (SourceClkInHz)/[16 * (SBR + BRFA)]
+ * First, calculate SBR (integer part) then calculate the BRFA (fine adjust fractional field). */
+ uint16_t brfa, sbr;
+
+ /* calculate the baud rate modulo divisor, sbr*/
+ sbr = sourceClockInHz / (baudRate * 16);
+
+ /* check to see if sbr is out of range of register bits */
+ if ( (sbr > 0x1FFF) || (sbr < 1) )
+ {
+ /* unsupported baud rate for given source clock input*/
+ return kStatus_UART_BaudRateCalculationError;
+ }
+
+ /* write the sbr value to the BDH and BDL registers*/
+ BW_UART_BDH_SBR(baseAddr, (uint8_t)(sbr >> 8));
+ BW_UART_BDL_SBR(baseAddr, (uint8_t)sbr);
+
+#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+ /* determine if a fractional divider is needed to fine tune closer to the desired baud
+ * each value of brfa is in 1/32 increments, hence the multiply-by-32. */
+ brfa = (32*sourceClockInHz/(baudRate*16)) - 32*sbr;
+
+ /* write the brfa value to the register*/
+ BW_UART_C4_BRFA(baseAddr, brfa);
+#endif
+
+ return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetBaudRateDivisor
+ * Description : Set the UART baud rate modulo divisor value.
+ * This function allows the user to program the baud rate divisor directly in
+ * situations where the divisor value is known. In this case, the user may not want to
+ * call the UART_HAL_SetBaudRate() function as the divisor is already known to them.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint16_t baudRateDivisor)
+{
+ /* check to see if baudRateDivisor is out of range of register bits */
+ assert( (baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1) );
+
+ /* program the sbr (baudRateDivisor) value to the BDH and BDL registers*/
+ BW_UART_BDH_SBR(baseAddr, (uint8_t)(baudRateDivisor >> 8));
+ BW_UART_BDL_SBR(baseAddr, (uint8_t)baudRateDivisor);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxRxInversionCmd
+ * Description : Configure the transmit and receive inversion control in UART
+ * controller. This function allows the user to invert the transmit and receive
+ * signals, independently. This function should only be called when the UART is
+ * between transmit and receive packets.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, bool rxInvertEnable, bool txInvertEnable)
+{
+ /* 0 - receive data not inverted, 1 - receive data inverted */
+ BW_UART_S2_RXINV(baseAddr, (uint8_t)rxInvertEnable);
+ /* 0 - transmit data not inverted, 1 - transmit data inverted*/
+ BW_UART_C3_TXINV(baseAddr, (uint8_t)txInvertEnable);
+}
+
+/*******************************************************************************
+ * UART Transfer Functions
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Putchar
+ * Description : This function allows the user to send an 8-bit character from the UART
+ * data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Putchar(uint32_t baseAddr, uint8_t data)
+{
+ /* put 8-bit data into the uart data register*/
+ /* in addition to sending a char, this function also clears the transmit status flags
+ * for this uart baseAddr, there is a two step process to clear the
+ * transmit status flags:
+ * 1. Read the status register with the status bit set
+ * 2. write to the data register */
+ HW_UART_S1_RD(baseAddr);
+ HW_UART_D_WR(baseAddr, data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Putchar9
+ * Description : This function allows the user to send a 9-bit character from the UART
+ * data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Putchar9(uint32_t baseAddr, uint16_t data)
+{
+ uint8_t ninthDataBit;
+
+ ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit*/
+
+ /* put 9-bit data to transmit*/
+ /* first, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, T8=9th bit)*/
+ BW_UART_C3_T8(baseAddr, ninthDataBit);
+
+ /* in addition to sending a char, this function also clears the transmit status flags
+ * for this uart baseAddr, there is a two step process to clear the
+ * transmit status flags:
+ * 1. Read the status register with the status bit set
+ * 2. write to the data register */
+ HW_UART_S1_RD(baseAddr);
+ /* write to the data register last since this will trigger transmit complete status flags
+ * also typecast to uint8_t to match register type */
+ HW_UART_D_WR(baseAddr, (uint8_t)data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Getchar
+ * Description : This function gets a received 8-bit character from the UART data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData)
+{
+ /* get 8-bit data from the uart data register*/
+ /* in addition to getting a char, this function also clears the receive status flag RDRF
+ * along with IDLE, OR, NF, FE, and PF (these can also be cleared in separate functions)
+ * for this uart baseAddr, there is a two step process to clear the receive
+ * status flag:
+ * 1. Read the status register with the status bit set
+ * 2. read from the data register */
+ HW_UART_S1_RD(baseAddr);
+ /* second, perform a read from the data register */
+ *readData = HW_UART_D_RD(baseAddr); /* read 8-bit data from data register*/
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Getchar9
+ * Description : This function gets a received 9-bit character from the UART data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData)
+{
+ uint16_t temp;
+
+ /* get 9-bit data from the uart data register*/
+ /* read ninth data bit and left shift to bit position R8 before reading
+ * the 8 other data bits R[7:0]
+ * *readData = (HW_UART_C3(baseAddr).B.R8) << 8; */
+ temp = (HW_UART_C3(baseAddr).B.R8);
+ *readData = temp << 8;
+
+ /* in addition to getting a char, this function also clears the receive status flag RDRF
+ * along with IDLE, OR, NF, FE, and PF (these can also be cleared in separate functions)
+ * for this uart baseAddr, there is a two step process to clear the receive
+ * status flag:
+ * 1. Read the status register with the status bit set
+ * 2. read from the data register */
+ HW_UART_S1_RD(baseAddr);
+ /* do last: get 8-bit data from the uart data register,
+ * will clear certain receive status bits once completed
+ * need to OR these 8-bits with the ninth bit value above. */
+ *readData |= HW_UART_D_RD(baseAddr); /* read 8-bit data from data register*/
+}
+
+/*******************************************************************************
+ * UART Interrupts and DMA
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ConfigureInterrupts
+ * Description : Configure the UART module interrupts to enable/disable various
+ * interrupt sources.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt, bool enable)
+{
+ uint8_t reg = (uint32_t)interrupt >> UART_SHIFT;
+ uint32_t temp = 1U << (uint8_t)interrupt;
+
+ switch ( reg )
+ {
+ case 0 :
+ enable ? HW_UART_BDH_SET(baseAddr, temp) : HW_UART_BDH_CLR(baseAddr, temp);
+ break;
+ case 1 :
+ enable ? HW_UART_C2_SET(baseAddr, temp) : HW_UART_C2_CLR(baseAddr, temp);
+ break;
+ case 2 :
+ enable ? HW_UART_C3_SET(baseAddr, temp) : HW_UART_C3_CLR(baseAddr, temp);
+ break;
+#if FSL_FEATURE_UART_HAS_FIFO
+ case 3 :
+ enable ? HW_UART_CFIFO_SET(baseAddr, temp) : HW_UART_CFIFO_CLR(baseAddr, temp);
+ break;
+#endif
+ default :
+ break;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetIntMode
+ * Description : Return whether the UART module interrupts is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt)
+{
+ uint8_t reg = (uint32_t)interrupt >> UART_SHIFT;
+ uint8_t temp = 0;
+
+ switch ( reg )
+ {
+ case 0 :
+ temp = HW_UART_BDH_RD(baseAddr) >> (uint8_t)(interrupt) & 1U;
+ break;
+ case 1 :
+ temp = HW_UART_C2_RD(baseAddr) >> (uint8_t)(interrupt) & 1U;
+ break;
+ case 2 :
+ temp = HW_UART_C3_RD(baseAddr) >> (uint8_t)(interrupt) & 1U;
+ break;
+#if FSL_FEATURE_UART_HAS_FIFO
+ case 3 :
+ temp = HW_UART_CFIFO_RD(baseAddr) >> (uint8_t)(interrupt) & 1U;
+ break;
+#endif
+ default :
+ break;
+ }
+ return (bool)temp;
+}
+#if FSL_FEATURE_UART_HAS_DMA_SELECT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ConfigureDma
+ * Description : Configure the UART DMA requests for the Transmitter and Receiver.
+ * This function allows the user to configure the transmit data register empty flag to
+ * generate an interrupt request (default) or a DMA request. Similarly, this function
+ * allows the user to conigure the receive data register full flag to generate an interrupt
+ * request (default) or a DMA request.
+ *
+ *END**************************************************************************/
+void UART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig)
+{
+
+ /* TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt
+ * or DMA requests if TIE is set.
+ * NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are
+ * not asserted when the TDRE flag is set, regardless of the state of TDMAS.
+ * If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE] must be cleared, and UART_D
+ * must not be written outside of servicing of a DMA request.
+ * 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted
+ * to request interrupt service.
+ * 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted
+ * to request a DMA transfer.
+ */
+ if (txDmaConfig == 1)
+ {
+ /* enable uart to generate transmit DMA request*/
+ BW_UART_C5_TDMAS(baseAddr, 1U); /* set TDMAS */
+ BW_UART_C2_TCIE(baseAddr, 0U); /* clear TCIE */
+ BW_UART_C2_TIE(baseAddr, 1U); /* set TIE */
+ }
+ else
+ {
+ /* disable uart transmit DMA request*/
+ BW_UART_C2_TIE(baseAddr, 0U); /* clear TIE to disable */
+ BW_UART_C5_TDMAS(baseAddr, 0U); /* clear TDMAS to disable */
+ }
+
+ /* RDMAS configures the receiver data register full flag, RDRF, to generate interrupt or
+ * DMA requests if RIEis set.
+ * NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not
+ * asserted when the RDRF flag is set, regardless of the state of RDMAS.
+ * 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is
+ * asserted to request interrupt service.
+ * 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted
+ * to request a DMA transfer.
+ */
+ if (rxDmaConfig == 1)
+ {
+ /* enable uart to generate receive DMA request*/
+ BW_UART_C5_RDMAS(baseAddr, 1U); /* set RDMAS */
+ BW_UART_C2_RIE(baseAddr, 1U); /* set RIE */
+ }
+ else
+ {
+ /* disable uart receive DMA request*/
+ BW_UART_C2_RIE(baseAddr, 0U); /* clear RIE to disable */
+ BW_UART_C5_RDMAS(baseAddr, 0U); /* clear RDMAS to disable */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_IsTxdmaEnabled
+ * Description : Get the UART Transmit DMA request configuration setting.
+ * This function returns to the user the configuration setting of the Transmit DMA request.
+ *
+ *END**************************************************************************/
+bool UART_HAL_IsTxdmaEnabled(uint32_t baseAddr)
+{
+ /* create variable for this to work around MISRA rule 12.4 since this is a volatile value*/
+ uint32_t tcieBitStatus;
+ tcieBitStatus = HW_UART_C2(baseAddr).B.TCIE;
+
+ /* TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt or
+ * DMA requests if TIE is set.
+ * NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are
+ * not asserted when the TDRE flag is set, regardless of the state of TDMAS.
+ * If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE] must be cleared, and UART_D
+ * must not be written outside of servicing of a DMA request.
+ * 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted
+ * to request interrupt service.
+ * 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to
+ * request a DMA transfer.
+ */
+ if (BR_UART_C5_TDMAS(baseAddr) == 1)
+ {
+ /* in order to enable transmit DMA request, TIE must be set and TCIE must be cleared*/
+ if ((BR_UART_C2_TIE(baseAddr) == 1) && (tcieBitStatus == 0))
+ {
+ /* UART module is configured to generate TxDMA request*/
+ return 1;
+ }
+ else
+ {
+ /* UART module is NOT configured to generate TxDMA request*/
+ return 0;
+ }
+ }
+ else
+ {
+ /* UART module is NOT configured to generate TxDMA request*/
+ return 0;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_IsRxdmaEnabled
+ * Description : Get the UART Receive DMA request configuration setting.
+ * This function returns to the user the configuration setting of the Receive DMA request.
+ *
+ *END**************************************************************************/
+bool UART_HAL_IsRxdmaEnabled(uint32_t baseAddr)
+{
+ /* RDMAS configures the receiver data register full flag, RDRF, to generate interrupt or
+ * DMA requests if RIE is set.
+ * NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not
+ * asserted when the RDRF flag is set, regardless of the state of RDMAS.
+ * 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted
+ * to requestinterrupt service.
+ * 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to
+ * request a DMA transfer.
+ */
+ if (BR_UART_C5_RDMAS(baseAddr) == 1)
+ {
+ /* enable uart to generate receive DMA request*/
+ if (BR_UART_C2_RIE(baseAddr) == 1)
+ {
+ /* UART module is configured to generate RxDMA request*/
+ return 1;
+ }
+ else
+ {
+ /* UART module is NOT configured to generate RxDMA request*/
+ return 0;
+ }
+ }
+ else
+ {
+ /* UART module is NOT configured to generate RxDMA request*/
+ return 0;
+ }
+}
+#endif
+/*******************************************************************************
+ * UART UART Status Flags
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetStatusFlag
+ * Description : Get UART status flag states.
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag)
+{
+ uint8_t reg = (uint32_t)statusFlag >> UART_SHIFT;
+ uint8_t temp = 0;
+
+ switch ( reg )
+ {
+ case 0 :
+ temp = HW_UART_S1_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U;
+ break;
+ case 1 :
+ temp = HW_UART_S2_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U;
+ break;
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ case 2 :
+ temp = HW_UART_ED_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U;
+ break;
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+ case 3 :
+ temp = HW_UART_SFIFO_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U;
+ break;
+#endif
+ default :
+ break;
+ }
+ return (bool)temp;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ClearStatusFlag
+ * Description : Clear an individual and specific UART status flag.
+ * This function allows the user to clear an individual and specific UART status flag. Refer to
+ * structure definition uart_status_flag_t for list of status bits.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_ClearStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag)
+{
+ uart_status_t returnCode; /* return code variable */
+ returnCode = kStatus_UART_Success; /* default return code, unless changed by error condition*/
+
+ /* clear the desired, individual status flag as passed in through statusFlag */
+ switch(statusFlag)
+ {
+ case kUartTxDataRegEmpty:
+ /* This flag is cleared automatically by other uart operations and
+ * cannot be manually cleared, return error code
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartTxComplete:
+ /* This flag is cleared automatically by other uart operations and
+ * cannot be manually cleared, return error code
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartRxDataRegFull:
+ /* This flag is cleared automatically by other uart operations and
+ * cannot be manually cleared, return error code
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartIdleLineDetect:
+ /* to clear the status is a two-step process:
+ * first, read S1 register with the status flag set
+ */
+ HW_UART_S1_RD(baseAddr);
+ /* second, read the data register*/
+ HW_UART_D_RD(baseAddr);
+ break;
+
+ case kUartRxOverrun:
+ /* to clear the status is a two-step process:
+ * first, read S1 register with the status flag set
+ */
+ HW_UART_S1_RD(baseAddr);
+ /* second, read the data register*/
+ HW_UART_D_RD(baseAddr);
+ break;
+
+ case kUartNoiseDetect:
+ /* to clear the status is a two-step process:
+ * first, read S1 register with the status flag set
+ */
+ HW_UART_S1_RD(baseAddr);
+ /* second, read the data register*/
+ HW_UART_D_RD(baseAddr);
+ break;
+
+ case kUartFrameErr:
+ /* to clear the status is a two-step process:
+ * first, read S1 register with the status flag set
+ */
+ HW_UART_S1_RD(baseAddr);
+ /* second, read the data register*/
+ HW_UART_D_RD(baseAddr);
+ break;
+
+ case kUartParityErr:
+ /* to clear the status is a two-step process:
+ * first, read S1 register with the status flag set
+ */
+ HW_UART_S1_RD(baseAddr);
+ /* second, read the data register*/
+ HW_UART_D_RD(baseAddr);
+ break;
+
+ case kUartLineBreakDetect:
+ /* write one to clear status flag */
+ HW_UART_S2_SET(baseAddr, BM_UART_S2_LBKDIF);
+ break;
+
+ case kUartRxActiveEdgeDetect:
+ /* write one to clear status flag */
+ HW_UART_S2_SET(baseAddr, BM_UART_S2_RXEDGIF);
+ break;
+
+ case kUartRxActive:
+ /* This flag is cleared automatically by other uart operations and
+ * cannot be manually cleared, return error code
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ case kUartNoiseInCurrentWord:
+ /* This flag is not clearable, it simply reflects the status in the
+ * current data word and changes with each new data word
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartParityErrInCurrentWord:
+ /* This flag is not clearable, it simply reflects the status in the
+ * current data word and changes with each new data word
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+ case kUartTxBuffEmpty:
+ /* This flag is not clearable, it simply reflects the current
+ * status of the buffer/FIFO
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartRxBuffEmpty:
+ /* This flag is not clearable, it simply reflects the current
+ * status of the buffer/FIFO
+ */
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+
+ case kUartTxBuffOverflow:
+ /* write one to clear status flag */
+ HW_UART_SFIFO_SET(baseAddr, BM_UART_SFIFO_TXOF);
+ break;
+
+ case kUartRxBuffUnderflow:
+ /* write one to clear status flag */
+ HW_UART_SFIFO_SET(baseAddr, BM_UART_SFIFO_RXUF);
+ break;
+#endif
+ default: /* catch inputs that are not recognized*/
+ returnCode = kStatus_UART_ClearStatusFlagError;
+ break;
+ }
+
+ return (returnCode);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ClearAllNonAutoclearStatusFlags
+ * Description : Clear ALL of the UART status flags.
+ * This function tries to clear all of the UART status flags. In some cases, some of the status
+ * flags may not get cleared because of the condition that set the flag may still exist.
+ *
+ *END**************************************************************************/
+void UART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr)
+{
+ /* clear the status flags that can be manually cleared
+ * note, some flags are automatically cleared and cannot be cleared automatically
+ */
+ UART_HAL_ClearStatusFlag(baseAddr, kUartIdleLineDetect);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartRxOverrun);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartNoiseDetect);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartFrameErr);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartParityErr);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartLineBreakDetect);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartRxActiveEdgeDetect);
+#if FSL_FEATURE_UART_HAS_FIFO
+ UART_HAL_ClearStatusFlag(baseAddr, kUartTxBuffOverflow);
+ UART_HAL_ClearStatusFlag(baseAddr, kUartRxBuffUnderflow);
+#endif
+}
+
+/*******************************************************************************
+ * UART FIFO Configurations
+ ******************************************************************************/
+#if FSL_FEATURE_UART_HAS_FIFO
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxFifo
+ * Description : Enable or disable the UART transmit FIFO.
+ * This function allows the user to enable or disable the UART transmit FIFO.
+ * It is required that the transmitter/receiver should be disabled before calling this
+ * function and when the FIFO is empty. Additionally, TXFLUSH and RXFLUSH commands
+ * should be issued after calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetTxFifoCmd(uint32_t baseAddr, bool enable)
+{
+ /* before enabling the tx fifo, UARTx_C2[TE] (transmitter) and
+ * UARTx_C2[RE] (receiver) must be disabled
+ * if not, return an error code */
+ uint8_t txEnable = BR_UART_C2_TE(baseAddr);
+ uint8_t rxEnable = BR_UART_C2_RE(baseAddr);
+
+ if (txEnable || rxEnable)
+ {
+ return kStatus_UART_TxOrRxNotDisabled;
+ }
+ else
+ {
+ BW_UART_PFIFO_TXFE(baseAddr, enable);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetRxFifoCmd
+ * Description : Enable or disable the UART receive FIFO.
+ * This function allows the user to enable or disable the UART receive FIFO.
+ * It is required that the transmitter/receiver should be disabled before calling
+ * this function and when the FIFO is empty. Additionally, TXFLUSH and RXFLUSH
+ * commands should be issued after calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetRxFifoCmd(uint32_t baseAddr, bool enable)
+{
+ /* before enabling the rx fifo, UARTx_C2[TE] (transmitter) and
+ * UARTx_C2[RE] (receiver) must be disabled
+ * if not, return an error code */
+ uint8_t txEnable = BR_UART_C2_TE(baseAddr);
+ uint8_t rxEnable = BR_UART_C2_RE(baseAddr);
+
+ if (txEnable || rxEnable)
+ {
+ return kStatus_UART_TxOrRxNotDisabled;
+ }
+ else
+ {
+ BW_UART_PFIFO_RXFE(baseAddr, enable);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_FlushTxFifo
+ * Description : Flush the UART transmit FIFO.
+ * This function allows you to flush the UART transmit FIFO for a particular modulei
+ * baseAddr. Flushing the FIFO may result in data loss. It is recommended that the
+ * transmitter should be disabled before calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_FlushTxFifo(uint32_t baseAddr)
+{
+ /* in order to flush the tx fifo, UARTx_C2[TE] (transmitter) must be disabled
+ * if not, return an error code */
+ if (BR_UART_C2_TE(baseAddr) != 0)
+ {
+ return kStatus_UART_TxNotDisabled;
+ }
+ else
+ {
+ /* Set the bit to flush fifo*/
+ BW_UART_CFIFO_TXFLUSH(baseAddr, 1U);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_FlushRxFifo
+ * Description : Flush the UART receive FIFO.
+ * This function allows you to flush the UART receive FIFO for a particular module
+ * baseAddr. Flushing the FIFO may result in data loss. It is recommended that the
+ * receiver should be disabled before calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_FlushRxFifo(uint32_t baseAddr)
+{
+ /* in order to flush the rx fifo, UARTx_C2[RE] (receiver) must be disabled
+ * if not, return an error code. */
+ if (BR_UART_C2_RE(baseAddr) != 0)
+ {
+ return kStatus_UART_RxNotDisabled;
+ }
+ else
+ {
+ /* Set the bit to flush fifo*/
+ BW_UART_CFIFO_RXFLUSH(baseAddr, 1U);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxFifoWatermark
+ * Description : Set the UART transmit FIFO watermark value.
+ * Programming the transmit watermark should be done when UART the transmitter is
+ * disabled and the value must be set less than the size obtained from
+ * UART_HAL_GetTxFifoSize.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetTxFifoWatermark(uint32_t baseAddr, uint8_t watermark)
+{
+ /* in order to set the tx watermark, UARTx_C2[TE] (transmitter) must be disabled
+ * if not, return an error code
+ */
+ if (BR_UART_C2_TE(baseAddr) != 0)
+ {
+ return kStatus_UART_TxNotDisabled;
+ }
+ else
+ {
+ /* Programming the transmit watermark should be done when the transmitter is
+ * disabled and the value must be set less than the size given in
+ * PFIFO[TXFIFOSIZE] */
+ HW_UART_TWFIFO_WR(baseAddr, watermark);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetRxFifoWatermark
+ * Description : Set the UART receive FIFO watermark value.
+ * Programming the receive watermark should be done when the receiver is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize
+ * and greater than zero.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetRxFifoWatermark(uint32_t baseAddr, uint8_t watermark)
+{
+ /* in order to set the rx watermark, UARTx_C2[RE] (receiver) must be disabled
+ * if not, return an error code. */
+ if (BR_UART_C2_RE(baseAddr) != 0)
+ {
+ return kStatus_UART_RxNotDisabled;
+ }
+ else
+ {
+ /* Programming the receive watermark should be done when the receiver is
+ * disabled and the value must be set less than the size given in
+ * PFIFO[RXFIFOSIZE] and greater than zero. */
+ HW_UART_RWFIFO_WR(baseAddr, watermark);
+ return kStatus_UART_Success;
+ }
+}
+#endif /* FSL_FEATURE_UART_HAS_FIFO*/
+
+/*******************************************************************************
+ * UART Special Feature Configurations
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_PutReceiverInStandbyMode
+ * Description : Place the UART receiver in standby mode.
+ * This function, when called, will place the UART receiver into standby mode.
+ * In some UART baseAddrs, there is a condition that must be met before placing rx in standby mode.
+ * Before placing UART in standby, you need to first determine if receiver is set to
+ * wake on idle and if receiver is already in idle state. Per ref manual:
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel
+ * is already idle, it is possible that the UART will discard data since data must be received
+ * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to reasserted.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr)
+{
+ /* In some uart baseAddrs, there is a condition that must be met before placing
+ * rx in standby mode.
+ * Before placing uart in standby, need to first determine if receiver is set to
+ * wake on idle and if receiver is already in idle state. Per ref manual:
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is
+ * currently not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up an IDLE event and
+ * the channel is already idle, it is possible that the UART will discard data since data
+ * must be received (or a LIN break detect) after an IDLE is detected before IDLE is
+ * allowed to reasserted.
+ */
+ uart_wakeup_method_t rxWakeMethod;
+ bool uart_current_rx_state;
+
+ /* see if wake is set for idle or */
+ rxWakeMethod = UART_HAL_GetReceiverWakeupMethod(baseAddr);
+ uart_current_rx_state = UART_HAL_GetStatusFlag(baseAddr, kUartRxActive);
+
+ /* if both rxWakeMethod is set for idle and current rx state is idle, don't put in standy*/
+ if ((rxWakeMethod == kUartIdleLineWake) && (uart_current_rx_state == 0))
+ {
+ return kStatus_UART_RxStandbyModeError;
+ }
+ else
+ {
+ /* set the RWU bit to place receiver into standby mode*/
+ HW_UART_C2_SET(baseAddr, BM_UART_C2_RWU);
+ return kStatus_UART_Success;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ConfigIdleLineDetect
+ * Description : Configure the operation options of the UART idle line detect.
+ * This function allows the user to configure the UART idle-line detect operation. There are two
+ * separate operations for the user to configure, the idle line bit-count start and the receive
+ * wake up affect on IDLE status bit. The user will pass in a stucture of type
+ * uart_idle_line_config_t.
+ *
+ *END**************************************************************************/
+void UART_HAL_ConfigIdleLineDetect(uint32_t baseAddr, uint8_t idleLine, uint8_t rxWakeIdleDetect)
+{
+ /* Configure the idle line detection configuration as follows:
+ * configure the ILT to bit count after start bit or stop bit
+ * configure RWUID to set or not set IDLE status bit upon detection of
+ * an idle character when recevier in standby */
+ BW_UART_C1_ILT(baseAddr, idleLine);
+ BW_UART_S2_RWUID(baseAddr, rxWakeIdleDetect);
+}
+#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetMatchAddress
+ * Description : Configure the UART match address mode control operation. (Note: Feature
+ * available on select UART baseAddrs)
+ * The function allows the user to configure the UART match address control operation. The user
+ * has the option to enable the match address mode and to program the match address value. There
+ * are two match address modes, each with it's own enable and programmable match address value.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetMatchAddress( uint32_t baseAddr, bool matchAddrMode1, bool matchAddrMode2,
+ uint8_t matchAddrValue1, uint8_t matchAddrValue2)
+{
+ BW_UART_C4_MAEN1(baseAddr, matchAddrMode1); /* Match Address Mode Enable 1 */
+ BW_UART_C4_MAEN2(baseAddr, matchAddrMode2); /* Match Address Mode Enable 2 */
+ HW_UART_MA1_WR(baseAddr, matchAddrValue1); /* match address register 1 */
+ HW_UART_MA2_WR(baseAddr, matchAddrValue2); /* match address register 2 */
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetInfraredOperation
+ * Description : Configure the UART infrared operation.
+ * The function allows the user to enable or disable the UART infrared (IR) operation
+ * and to configure the IR pulse width.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable,
+ uart_ir_tx_pulsewidth_t pulseWidth)
+{
+ /* enable or disable infrared */
+ BW_UART_IR_IREN(baseAddr, enable);
+ /* configure the narrow pulse width of the IR pulse */
+ BW_UART_IR_TNP(baseAddr, pulseWidth);
+}
+#endif /* FSL_FEATURE_UART_HAS_IR_SUPPORT */
+
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,1333 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_UART_HAL_H__
+#define __FSL_UART_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_uart_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup uart_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define UART_SHIFT (8U)
+
+/*! @brief Error codes for the UART driver. */
+typedef enum _uart_status
+{
+ kStatus_UART_Success = 0x0U,
+ kStatus_UART_BaudRateCalculationError = 0x1U,
+ kStatus_UART_RxStandbyModeError = 0x2U,
+ kStatus_UART_ClearStatusFlagError = 0x3U,
+ kStatus_UART_TxNotDisabled = 0x4U,
+ kStatus_UART_RxNotDisabled = 0x5U,
+ kStatus_UART_TxOrRxNotDisabled = 0x6U,
+ kStatus_UART_TxBusy = 0x7U,
+ kStatus_UART_RxBusy = 0x8U,
+ kStatus_UART_NoTransmitInProgress = 0x9U,
+ kStatus_UART_NoReceiveInProgress = 0xAU,
+ kStatus_UART_Timeout = 0xBU,
+ kStatus_UART_Initialized = 0xCU,
+ kStatus_UART_RxCallBackEnd = 0xDU
+} uart_status_t;
+
+/*!
+ * @brief UART number of stop bits.
+ *
+ * These constants define the number of allowable stop bits to configure in a UART baseAddr.
+ */
+typedef enum _uart_stop_bit_count {
+ kUartOneStopBit = 0U, /*!< one stop bit */
+ kUartTwoStopBit = 1U, /*!< two stop bits */
+} uart_stop_bit_count_t;
+
+/*!
+ * @brief UART parity mode.
+ *
+ * These constants define the UART parity mode options: disabled or enabled of type even or odd.
+ */
+typedef enum _uart_parity_mode {
+ kUartParityDisabled = 0x0U, /*!< parity disabled */
+ kUartParityEven = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 */
+ kUartParityOdd = 0x3U, /*!< parity enabled, type odd, bit setting: PE|PT = 11 */
+} uart_parity_mode_t;
+
+/*!
+ * @brief UART number of bits in a character.
+ *
+ * These constants define the number of allowable data bits per UART character. Note, check the
+ * UART documentation to determine if the desired UART baseAddr supports the desired number
+ * of data bits per UART character.
+ */
+typedef enum _uart_bit_count_per_char {
+ kUart8BitsPerChar = 0U, /*!< 8-bit data characters */
+ kUart9BitsPerChar = 1U, /*!< 9-bit data characters */
+} uart_bit_count_per_char_t;
+
+/*!
+ * @brief UART operation configuration constants.
+ *
+ * This provides constants for UART operational states: "operates normally"
+ * or "stops/ceases operation"
+ */
+typedef enum _uart_operation_config {
+ kUartOperates = 0U, /*!< UART continues to operate normally */
+ kUartStops = 1U, /*!< UART ceases operation */
+} uart_operation_config_t;
+
+/*! @brief UART receiver source select mode. */
+typedef enum _uart_receiver_source {
+ kUartLoopBack = 0U, /*!< Internal loop back mode. */
+ kUartSingleWire = 1U,/*!< Single wire mode. */
+} uart_receiver_source_t ;
+
+/*!
+ * @brief UART wakeup from standby method constants.
+ *
+ * This provides constants for the two UART wakeup methods: idle-line or address-mark.
+ */
+typedef enum _uart_wakeup_method {
+ kUartIdleLineWake = 0U, /*!< The idle-line wakes UART receiver from standby */
+ kUartAddrMarkWake = 1U, /*!< The address-mark wakes UART receiver from standby */
+} uart_wakeup_method_t;
+
+/*!
+ * @brief UART idle-line detect selection types.
+ *
+ * This provides constants for the UART idle character bit-count start: either after start or
+ * stop bit.
+ */
+typedef enum _uart_idle_line_select {
+ kUartIdleLineAfterStartBit = 0U, /*!< UART idle character bit count start after start bit */
+ kUartIdleLineAfterStopBit = 1U, /*!< UART idle character bit count start after stop bit */
+} uart_idle_line_select_t;
+
+/*!
+ * @brief UART break character length settings for transmit/detect.
+ *
+ * This provides constants for the UART break character length for both transmission and detection
+ * purposes. Note that the actual maximum bit times may vary depending on the UART baseAddr.
+ */
+typedef enum _uart_break_char_length {
+ kUartBreakChar10BitMinimum = 0U, /*!< UART break char length 10 bit times (if M = 0, SBNS = 0) or
+ 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+ SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */
+ kUartBreakChar13BitMinimum = 1U, /*!< UART break char length 13 bit times (if M = 0, SBNS = 0) or
+ 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
+ SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */
+} uart_break_char_length_t;
+
+/*!
+ * @brief UART single-wire mode transmit direction.
+ *
+ * This provides constants for the UART transmit direction when configured for single-wire mode.
+ * The transmit line TXDIR is either an input or output.
+ */
+typedef enum _uart_singlewire_txdir {
+ kUartSinglewireTxdirIn = 0U, /*!< UART Single-Wire mode TXDIR input */
+ kUartSinglewireTxdirOut = 1U, /*!< UART Single-Wire mode TXDIR output */
+} uart_singlewire_txdir_t;
+
+/*!
+ * @brief UART infrared transmitter pulse width options.
+ *
+ * This provides constants for the UART infrared (IR) pulse widths. Options include 3/16, 1/16
+ * 1/32, and 1/4 pulse widths.
+ */
+typedef enum _uart_ir_tx_pulsewidth {
+ kUartIrThreeSixteenthsWidth = 0U, /*!< 3/16 pulse */
+ kUartIrOneSixteenthWidth = 1U, /*!< 1/16 pulse */
+ kUartIrOneThirtysecondsWidth = 2U, /*!< 1/32 pulse */
+ kUartIrOneFourthWidth = 3U, /*!< 1/4 pulse */
+} uart_ir_tx_pulsewidth_t;
+
+/*!
+ * @brief UART status flags.
+ *
+ * This provides constants for the UART status flags for use in the UART functions.
+ */
+typedef enum _uart_status_flag {
+ kUartTxDataRegEmpty = 0U << UART_SHIFT | BP_UART_S1_TDRE, /*!< Tx data register empty flag, sets when Tx buffer is empty */
+ kUartTxComplete = 0U << UART_SHIFT | BP_UART_S1_TC, /*!< Transmission complete flag, sets when transmission activity complete */
+ kUartRxDataRegFull = 0U << UART_SHIFT | BP_UART_S1_RDRF, /*!< Rx data register full flag, sets when the receive data buffer is full */
+ kUartIdleLineDetect = 0U << UART_SHIFT | BP_UART_S1_IDLE, /*!< Idle line detect flag, sets when idle line detected */
+ kUartRxOverrun = 0U << UART_SHIFT | BP_UART_S1_OR, /*!< Rxr Overrun, sets when new data is received before data is read from receive register */
+ kUartNoiseDetect = 0U << UART_SHIFT | BP_UART_S1_NF, /*!< Rxr takes 3 samples of each received bit. If any of these samples differ, noise flag sets */
+ kUartFrameErr = 0U << UART_SHIFT | BP_UART_S1_FE, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+ kUartParityErr = 0U << UART_SHIFT | BP_UART_S1_PF, /*!< If parity enabled, sets upon parity error detection */
+ kUartLineBreakDetect = 1U << UART_SHIFT | BP_UART_S2_LBKDIF, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+ kUartRxActiveEdgeDetect = 1U << UART_SHIFT | BP_UART_S2_RXEDGIF, /*!< Rx pin active edge interrupt flag, sets when active edge detected */
+ kUartRxActive = 1U << UART_SHIFT | BP_UART_S2_RAF, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ kUartNoiseInCurrentWord = 2U << UART_SHIFT | BP_UART_ED_NOISY, /*!< NOISY bit, sets if noise detected in current data word */
+ kUartParityErrInCurrentWord = 2U << UART_SHIFT | BP_UART_ED_PARITYE, /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+ kUartTxBuffEmpty = 3U << UART_SHIFT | BP_UART_SFIFO_TXEMPT, /*!< TXEMPT bit, sets if Tx buffer is empty */
+ kUartRxBuffEmpty = 3U << UART_SHIFT | BP_UART_SFIFO_RXEMPT, /*!< RXEMPT bit, sets if Rx buffer is empty */
+ kUartTxBuffOverflow = 3U << UART_SHIFT | BP_UART_SFIFO_TXOF, /*!< TXOF bit, sets if Tx buffer overflow occurred */
+ kUartRxBuffUnderflow = 3U << UART_SHIFT | BP_UART_SFIFO_RXUF, /*!< RXUF bit, sets if receive buffer underflow occurred */
+#endif
+} uart_status_flag_t;
+
+/*!
+ * @brief UART interrupt configuration structure, default settings are 0 (disabled).
+ *
+ * This structure contains the settings for all of the UART interrupt configurations.
+ */
+typedef enum _uart_interrupt {
+ kUartIntLinBreakDetect = 0U << UART_SHIFT | BP_UART_BDH_LBKDIE, /*!< LIN break detect. */
+ kUartIntRxActiveEdge = 0U << UART_SHIFT | BP_UART_BDH_RXEDGIE, /*!< RX Active Edge. */
+ kUartIntTxDataRegEmpty = 1U << UART_SHIFT | BP_UART_C2_TIE, /*!< Transmit data register empty. */
+ kUartIntTxComplete = 1U << UART_SHIFT | BP_UART_C2_TCIE, /*!< Transmission complete. */
+ kUartIntRxDataRegFull = 1U << UART_SHIFT | BP_UART_C2_RIE, /*!< Receiver data register full. */
+ kUartIntIdleLine = 1U << UART_SHIFT | BP_UART_C2_ILIE, /*!< Idle line. */
+ kUartIntRxOverrun = 2U << UART_SHIFT | BP_UART_C3_ORIE, /*!< Receiver Overrun. */
+ kUartIntNoiseErrFlag = 2U << UART_SHIFT | BP_UART_C3_NEIE, /*!< Noise error flag. */
+ kUartIntFrameErrFlag = 2U << UART_SHIFT | BP_UART_C3_FEIE, /*!< Framing error flag. */
+ kUartIntParityErrFlag = 2U << UART_SHIFT | BP_UART_C3_PEIE, /*!< Parity error flag. */
+#if FSL_FEATURE_UART_HAS_FIFO
+ kUartIntTxFifoOverflow = 3U << UART_SHIFT | BP_UART_CFIFO_TXOFE, /*!< TX FIFO Overflow. */
+ kUartIntRxFifoUnderflow = 3U << UART_SHIFT | BP_UART_CFIFO_RXUFE, /*!< RX FIFO Underflow. */
+#endif
+} uart_interrupt_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART Common Configurations
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART controller.
+ *
+ * This function initializes the module to a known state.
+ *
+ * @param baseAddr UART module base address.
+ */
+void UART_HAL_Init(uint32_t baseAddr);
+
+/*!
+ * @brief Enables the UART transmitter.
+ *
+ * This function allows the user to enable the UART transmitter.
+ *
+ * @param baseAddr UART module base address.
+ */
+static inline void UART_HAL_EnableTransmitter(uint32_t baseAddr)
+{
+ BW_UART_C2_TE(baseAddr, 1U);
+}
+
+/*!
+ * @brief Disables the UART transmitter.
+ *
+ * This function allows the user to disable the UART transmitter.
+ *
+ * @param baseAddr UART module base address.
+ */
+static inline void UART_HAL_DisableTransmitter(uint32_t baseAddr)
+{
+ BW_UART_C2_TE(baseAddr, 0U);
+}
+
+/*!
+ * @brief Gets the UART transmitter enabled/disabled configuration setting.
+ *
+ * This function allows the user to get the setting of the UART transmitter.
+ *
+ * @param baseAddr UART module base address.
+ * @return The state of UART transmitter enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_IsTransmitterEnabled(uint32_t baseAddr)
+{
+ return (bool)BR_UART_C2_TE(baseAddr);
+}
+
+/*!
+ * @brief Enables the UART receiver.
+ *
+ * This function allows the user to enable the UART receiver.
+ *
+ * @param baseAddr UART module base address.
+ */
+static inline void UART_HAL_EnableReceiver(uint32_t baseAddr)
+{
+ BW_UART_C2_RE(baseAddr, 1U);
+}
+
+/*!
+ * @brief Disables the UART receiver.
+ *
+ * This function allows the user to disable the UART receiver.
+ *
+ * @param baseAddr UART module base address.
+ */
+static inline void UART_HAL_DisableReceiver(uint32_t baseAddr)
+{
+ BW_UART_C2_RE(baseAddr, 0U);
+}
+
+/*!
+ * @brief Gets the UART receiver enabled/disabled configuration setting.
+ *
+ * This function allows the user to get the setting of the UART receiver.
+ *
+ * @param baseAddr UART module base address.
+ * @return The state of UART receiver enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_IsReceiverEnabled(uint32_t baseAddr)
+{
+ return (bool)BR_UART_C2_RE(baseAddr);
+}
+
+/*!
+ * @brief Configures the UART baud rate.
+ *
+ * This function programs the UART baud rate to the desired value passed in by the user. The user
+ * must also pass in the module source clock so that the function can calculate the baud
+ * rate divisors to their appropriate values.
+ * In some UART baseAddrs it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * Generally this is applied to all UARTs to ensure safe operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param sourceClockInHz UART source input clock in Hz.
+ * @param baudRate UART desired baud rate.
+ * @return An error code or kStatus_UART_Success
+ */
+uart_status_t UART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t baudRate);
+
+/*!
+ * @brief Sets the UART baud rate modulo divisor value.
+ *
+ * This function allows the user to program the baud rate divisor directly in situations
+ * where the divisor value is known. In this case, the user may not want to call the
+ * UART_HAL_SetBaudRate() function, as the divisor is already known.
+ *
+ * @param baseAddr UART module base address.
+ * @param baudRateDivisor The baud rate modulo division "SBR" value.
+ */
+void UART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint16_t baudRateDivisor);
+
+#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+/*!
+ * @brief Sets the UART baud rate fine adjust. (Note: Feature available on select
+ * UART baseAddrs used in conjunction with baud rate programming)
+ *
+ * This function, which programs the baud rate fine adjust, is used together with
+ * programming the baud rate modulo divisor in situations where these divisors value are known.
+ * In this case, the user may not want to call the UART_HAL_SetBaudRate() function, as the
+ * divisors are already known.
+ *
+ * @param baseAddr UART module base address.
+ * @param baudFineAdjust Value of 5-bit field used to add more timing resolution to average
+ * baud rate frequency is 1/32 increments.
+ */
+static inline void UART_HAL_SetBaudRateFineAdjust(uint32_t baseAddr, uint8_t baudFineAdjust)
+{
+ assert(baudFineAdjust < 0x1F);
+ BW_UART_C4_BRFA(baseAddr, baudFineAdjust);
+}
+#endif
+
+/*!
+ * @brief Configures the number of bits per character in the UART controller.
+ *
+ * This function allows the user to configure the number of bits per character according to the
+ * typedef uart_bit_count_per_char_t.
+ *
+ * @param baseAddr UART module base address.
+ * @param bitCountPerChar Number of bits per char (8, 9, or 10, depending on the UART baseAddr).
+ */
+static inline void UART_HAL_SetBitCountPerChar(uint32_t baseAddr,
+ uart_bit_count_per_char_t bitCountPerChar)
+{
+ /* config 8- (M=0) or 9-bits (M=1) */
+ BW_UART_C1_M(baseAddr, bitCountPerChar);
+}
+
+/*!
+ * @brief Configures the parity mode in the UART controller.
+ *
+ * This function allows the user to configure the parity mode of the UART controller to disable
+ * it or enable it for even parity or for odd parity.
+ *
+ * @param baseAddr UART module base address.
+ * @param parityMode Parity mode setting (enabled, disable, odd, even - see
+ * parity_mode_t struct).
+ */
+static inline void UART_HAL_SetParityMode(uint32_t baseAddr, uart_parity_mode_t parityMode)
+{
+ HW_UART_C1_SET(baseAddr, parityMode);
+}
+
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+/*!
+ * @brief Configures the number of stop bits in the UART controller.
+ *
+ * This function allows the user to configure the number of stop bits in the UART controller
+ * to be one or two stop bits.
+ *
+ * @param baseAddr UART module base address.
+ * @param stopBitCount Number of stop bits setting (1 or 2 - see uart_stop_bit_count_t struct).
+ * @return An error code (an unsupported setting in some UARTs) or kStatus_UART_Success.
+ */
+static inline void UART_HAL_SetStopBitCount(uint32_t baseAddr, uart_stop_bit_count_t stopBitCount)
+{
+ BW_UART_BDH_SBNS(baseAddr, stopBitCount);
+}
+#endif
+
+/*!
+ * @brief Configures the transmit and receive inversion control in UART controller.
+ *
+ * This function allows the user to invert the transmit and receive signals, independently.
+ * This function should only be called when the UART is between transmit and receive packets.
+ *
+ * @param baseAddr UART module base address.
+ * @param rxInvert Enable (true) or disable (false) receive inversion.
+ * @param txInvert Enable (true) or disable (false) transmit inversion.
+ */
+void UART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, bool rxInvertEnable, bool txInvertEnable);
+
+/*@}*/
+
+/*!
+ * @name UART Interrupts and DMA
+ * @{
+ */
+
+/*!
+ * @brief Configures the UART module interrupts to enable/disable various interrupt sources.
+ *
+ * @param baseAddr UART module base address.
+ * @param interrupt UART interrupt configuration data.
+ * @param enable true: enable, false: disable.
+ */
+void UART_HAL_SetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the UART module interrupts is enabled/disabled.
+ *
+ * @param baseAddr UART module base address.
+ * @param interrupt UART interrupt configuration data.
+ * @return true: enable, false: disable.
+ */
+bool UART_HAL_GetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt);
+
+/*!
+ * @brief Enables or disables the tx_data_register_empty_interrupt.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable true: enable, false: disable.
+ */
+static inline void UART_HAL_SetTxDataRegEmptyIntCmd(uint32_t baseAddr, bool enable)
+{
+ /* transmit interrupt enable for TDRE (transmit data register empty)*/
+ BW_UART_C2_TIE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Gets the configuration of the tx_data_register_empty_interrupt enable setting.
+ *
+ * @param baseAddr UART module base address.
+ * @return setting of the interrupt enable bit.
+ */
+static inline bool UART_HAL_GetTxDataRegEmptyIntCmd(uint32_t baseAddr)
+{
+ /* return interrupt enable condition of TIE */
+ return (bool)BR_UART_C2_TIE(baseAddr);
+}
+
+/*!
+ * @brief Disables the rx_data_register_full_interrupt.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable true: enable, false: disable.
+ */
+static inline void UART_HAL_SetRxDataRegFullIntCmd(uint32_t baseAddr, bool enable)
+{
+ /* receiver interrupt enable for receiver data register full (RDRF)*/
+ BW_UART_C2_RIE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Gets the configuration of the rx_data_register_full_interrupt enable setting.
+ *
+ * @param baseAddr UART module base address.
+ * @return Bit setting of the interrupt enable bit.
+ */
+static inline bool UART_HAL_GetRxDataRegFullIntCmd(uint32_t baseAddr)
+{
+ /* return interrupt enable condition of RIE */
+ return (bool)BR_UART_C2_RIE(baseAddr);
+}
+
+/*!
+ * @brief Configures the UART DMA requests for the Transmitter and Receiver.
+ *
+ * This function allows the user to configure the transmit data register empty flag to
+ * generate an interrupt request (default) or a DMA request. Similarly, this function
+ * allows the user to configure the receive data register full flag to generate an interrupt
+ * request (default) or a DMA request.
+ *
+ * @param baseAddr UART module base address.
+ * @param txDmaConfig Transmit DMA request configuration setting (enable: true /disable: false).
+ * @param rxDmaConfig Receive DMA request configuration setting (enable: true/disable: false).
+ */
+void UART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig);
+
+/*!
+ * @brief Gets the UART Transmit DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Transmit DMA request.
+ *
+ * @param baseAddr UART module base address.
+ * @return Transmit DMA request configuration setting (enable: true /disable: false).
+ */
+bool UART_HAL_IsTxdmaEnabled(uint32_t baseAddr);
+
+/*!
+ * @brief Gets the UART Receive DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Receive DMA request.
+ *
+ * @param baseAddr UART module base address.
+ * @return Receive DMA request configuration setting (enable: true /disable: false).
+ */
+bool UART_HAL_IsRxdmaEnabled(uint32_t baseAddr);
+
+/*!
+ * @brief Get UART tx/rx data register address.
+ *
+ * This function is used for DMA transfer.
+ *
+ * @return UART tx/rx data register address.
+ */
+static inline uint32_t UART_HAL_GetDataRegAddr(uint32_t baseAddr)
+{
+ return (uint32_t)HW_UART_D_ADDR(baseAddr);
+}
+
+/*@}*/
+
+/*!
+ * @name UART Transfer Functions
+ * @{
+ */
+
+/*!
+ * @brief This function allows the user to send an 8-bit character from the UART data register.
+ *
+ * @param baseAddr UART module base address.
+ * @param data The data to send of size 8-bit.
+ */
+void UART_HAL_Putchar(uint32_t baseAddr, uint8_t data);
+
+/*!
+ * @brief This function allows the user to send a 9-bit character from the UART data register.
+ *
+ * @param baseAddr UART module base address.
+ * @param data The data to send of size 9-bit.
+ */
+void UART_HAL_Putchar9(uint32_t baseAddr, uint16_t data);
+
+/*!
+ * @brief This function gets a received 8-bit character from the UART data register.
+ *
+ * @param baseAddr UART module base address.
+ * @param readData The received data read from data register of size 8-bit.
+ */
+void UART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData);
+
+/*!
+ * @brief This function gets a received 9-bit character from the UART data register.
+ *
+ * @param baseAddr UART module base address.
+ * @param readData The received data read from data register of size 9-bit.
+ */
+void UART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData);
+
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+/*!
+ * @brief Configures the UART bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the
+ * serial transmission.
+ *
+ * This function configures bit 10 or bit 9 to be the parity bit. To configure bit 10 as the parity
+ * bit, the function sets UARTx_C4[M10]; it also sets UARTx_C1[M] and UARTx_C1[PE] as required.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable The setting to enable (true), which configures bit 10 as the parity bit or to
+ * disable (false), which configures bit 9 as the parity bit in the serial
+ * transmission.
+ */
+static inline void UART_HAL_SetBit10AsParitybit(uint32_t baseAddr, bool enable)
+{
+ /* to enable the parity bit as the tenth data bit, along with enabling UARTx_C4[M10]
+ * need to also enable parity and set UARTx_C1[M] bit
+ * assumed that the user has already set the appropriate bits */
+ BW_UART_C4_M10(baseAddr, enable);
+}
+
+/*!
+ * @brief Gets the configuration of the UART bit 10 (if enabled) or bit 9 (if disabled) as the
+ * parity bit in the serial transmission.
+ *
+ * This function returns true if bit 10 is configured as the parity bit, otherwise it returns
+ * false if bit 9 is configured as the parity bit.
+ *
+ * @param baseAddr UART module base address.
+ * @return The configuration setting of bit 10 (true), or bit 9 (false) as the
+ * parity bit in the serial transmission.
+ */
+static inline bool UART_HAL_IsBit10SetAsParitybit(uint32_t baseAddr)
+{
+ /* to see if the parity bit is set as the tenth data bit,
+ * return value of UARTx_C4[M10] */
+ return BR_UART_C4_M10(baseAddr);
+}
+
+/*!
+ * @brief Determines whether the UART received data word was received with noise.
+ *
+ * This function returns true if the received data word was received with noise. Otherwise,
+ * it returns false indicating no noise was detected.
+ *
+ * @param baseAddr UART module base address.
+ * @return The status of the NOISY bit in the UART extended data register.
+ */
+static inline bool UART_HAL_IsCurrentDatawordReceivedWithNoise(uint32_t baseAddr)
+{
+ /* to see if the current dataword was received with noise,
+ * return value of UARTx_ED[NOISY] */
+ return BR_UART_ED_NOISY(baseAddr);
+}
+
+/*!
+ * @brief Determines whether the UART received data word was received with a parity error.
+ *
+ * This function returns true if the received data word was received with a parity error.
+ * Otherwise, it returns false indicating no parity error was detected.
+ *
+ * @param baseAddr UART module base address.
+ * @return The status of the PARITYE (parity error) bit in the UART extended data register.
+ */
+static inline bool UART_HAL_IsCurrentDatawordReceivedWithParityerror(uint32_t baseAddr)
+{
+ /* to see if the current dataword was received with parity error,
+ * return value of UARTx_ED[PARITYE] */
+ return BR_UART_ED_PARITYE(baseAddr);
+}
+
+#endif /* FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS*/
+
+/*@}*/
+
+/*!
+ * @name UART Special Feature Configurations
+ * @{
+ */
+
+/*!
+ * @brief Configures the UART to either operate or cease to operate in WAIT mode.
+ *
+ * The function configures the UART to either operate or cease to operate when WAIT mode is
+ * entered.
+ *
+ * @param baseAddr UART module base address.
+ * @param mode The UART WAIT mode operation - operates or ceases to operate in WAIT mode.
+ */
+static inline void UART_HAL_SetWaitModeOperation(uint32_t baseAddr, uart_operation_config_t mode)
+{
+ /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */
+ BW_UART_C1_UARTSWAI(baseAddr, mode);
+}
+
+/*!
+ * @brief Determines if the UART operates or ceases to operate in WAIT mode.
+ *
+ * This function returns kUartOperates if the UART has been configured to operate in WAIT mode.
+ * Else it returns KUartStops if the UART has been configured to cease-to-operate in WAIT mode.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART WAIT mode operation configuration, returns either kUartOperates or KUartStops.
+ */
+static inline uart_operation_config_t UART_HAL_GetWaitModeOperation(uint32_t baseAddr)
+{
+ /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */
+ return (uart_operation_config_t)BR_UART_C1_UARTSWAI(baseAddr);
+}
+
+/*!
+ * @brief Configures the UART loopback operation.
+ *
+ * This function enables or disables the UART loopback operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable The UART loopback mode configuration, either disabled (false) or enabled (true).
+ */
+static inline void UART_HAL_SetLoopCmd(uint32_t baseAddr, bool enable)
+{
+ BW_UART_C1_LOOPS(baseAddr, enable);
+}
+
+/*!
+ * @brief Configures the UART single-wire operation.
+ *
+ * This function enables or disables the UART single-wire operation.
+ * In some UART baseAddrs it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable The UART single-wire mode configuration, either disabled (false) or enabled (true).
+ */
+static inline void UART_HAL_SetReceiverSource(uint32_t baseAddr, uart_receiver_source_t source)
+{
+ BW_UART_C1_RSRC(baseAddr, source);
+}
+/*!
+ * @brief Configures the UART transmit direction while in single-wire mode.
+ *
+ * This function configures the transmitter direction when the UART is configured for single-wire
+ * operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param direction The UART single-wire mode transmit direction configuration of type
+ * uart_singlewire_txdir_t (either kUartSinglewireTxdirIn or
+ * kUartSinglewireTxdirOut.
+ */
+static inline void UART_HAL_SetTransmitterDir(uint32_t baseAddr, uart_singlewire_txdir_t direction)
+{
+ /* configure UART transmit direction (input or output) when in single-wire mode
+ * it is assumed UART is in single-wire mode
+ */
+ BW_UART_C3_TXDIR(baseAddr, direction);
+}
+
+/*!
+ * @brief Places the UART receiver in standby mode.
+ *
+ * This function, when called, places the UART receiver into standby mode.
+ * In some UART baseAddrs, there are conditions that must be met before placing Rx in standby mode.
+ * Before placing UART in standby, determine if receiver is set to
+ * wake on idle, and if receiver is already in idle state.
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel
+ * is already idle, it is possible that the UART will discard data because data must be received
+ * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted.
+ *
+ * @param baseAddr UART module base address.
+ * @return Error code or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr);
+
+/*!
+ * @brief Places the UART receiver in normal mode (disable standby mode operation).
+ *
+ * This function, when called, places the UART receiver into normal mode and out of
+ * standby mode.
+ *
+ * @param baseAddr UART module base address.
+ */
+static inline void UART_HAL_PutReceiverInNormalMode(uint32_t baseAddr)
+{
+ /* clear the RWU bit to place receiver into normal mode (disable standby mode)*/
+ HW_UART_C2_CLR(baseAddr, BM_UART_C2_RWU);
+}
+
+/*!
+ * @brief Determines if the UART receiver is currently in standby mode.
+ *
+ * This function determines the state of the UART receiver. If it returns true, this means
+ * that the UART receiver is in standby mode; if it returns false, the UART receiver
+ * is in normal mode.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART receiver is in normal mode (false) or standby mode (true).
+ */
+static inline bool UART_HAL_IsReceiverInStandby(uint32_t baseAddr)
+{
+ /* return the RWU bit setting (0 - normal more, 1 - standby)*/
+ return BR_UART_C2_RWU(baseAddr);
+}
+
+/*!
+ * @brief Selects the UART receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function configures the wakeup method of the UART receiver from standby mode. The options
+ * are idle-line wake or address-mark wake.
+ *
+ * @param baseAddr UART module base address.
+ * @param method The UART receiver wakeup method options: kUartIdleLineWake - Idle-line wake or
+ * kUartAddrMarkWake - address-mark wake.
+ */
+static inline void UART_HAL_SetReceiverWakeupMethod(uint32_t baseAddr, uart_wakeup_method_t method)
+{
+ /* configure the WAKE bit for idle line wake or address mark wake */
+ BW_UART_C1_WAKE(baseAddr, method);
+}
+
+/*!
+ * @brief Gets the UART receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function returns how the UART receiver is configured to wake from standby mode. The
+ * wake method options that can be returned are kUartIdleLineWake or kUartAddrMarkWake.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART receiver wakeup from standby method, false: kUartIdleLineWake (idle-line wake)
+ * or true: kUartAddrMarkWake (address-mark wake).
+ */
+static inline uart_wakeup_method_t UART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr)
+{
+ /* get configuration of the WAKE bit for idle line wake or address mark wake */
+ return (uart_wakeup_method_t)BR_UART_C1_WAKE(baseAddr);
+}
+
+/*!
+ * @brief Configures the operation options of the UART idle line detect.
+ *
+ * This function allows the user to configure the UART idle-line detect operation. There are two
+ * separate operations for the user to configure, the idle line bit-count start and the receive
+ * wake up affect on IDLE status bit. The user will pass in a structure of type
+ * uart_idle_line_config_t.
+ *
+ * @param baseAddr UART module base address.
+ * @param idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit
+ * @param rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive
+ * standby. Controls whether idle character that wakes up receiver will also set IDLE status
+ * bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set
+ */
+void UART_HAL_ConfigIdleLineDetect(uint32_t baseAddr, uint8_t idleLine, uint8_t rxWakeIdleDetect);
+
+/*!
+ * @brief Configures the UART break character transmit length.
+ *
+ * This function allows the user to configure the UART break character transmit length. Refer to
+ * the typedef uart_break_char_length_t for setting options.
+ * In some UART baseAddrs it is required that the transmitter be disabled before calling
+ * this function. This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param length The UART break character length setting of type uart_break_char_length_t, either a
+ * minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void UART_HAL_SetBreakCharTransmitLength(uint32_t baseAddr,
+ uart_break_char_length_t length)
+{
+ /* Configure BRK13 - Break Character transmit length configuration
+ * UART break character length setting:
+ * 0 - minimum 10-bit times (default),
+ * 1 - minimum 13-bit times */
+ BW_UART_S2_BRK13(baseAddr, length);
+}
+
+/*!
+ * @brief Configures the UART break character detect length.
+ *
+ * This function allows the user to configure the UART break character detect length. Refer to
+ * the typedef uart_break_char_length_t for setting options.
+ *
+ * @param baseAddr UART module base address.
+ * @param length The UART break character length setting of type uart_break_char_length_t, either a
+ * minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void UART_HAL_SetBreakCharDetectLength(uint32_t baseAddr, uart_break_char_length_t length)
+{
+ /* Configure LBKDE - Break Character detect length configuration
+ * UART break character length setting:
+ * 0 - minimum 10-bit times (default),
+ * 1 - minimum 13-bit times */
+ BW_UART_S2_LBKDE(baseAddr, length);
+}
+
+/*!
+ * @brief Configures the UART transmit send break character operation.
+ *
+ * This function allows the user to queue a UART break character to send. If true is passed into
+ * the function, then a break character is queued for transmission. A break character will
+ * continuously be queued until this function is called again when a false is passed into this
+ * function.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable If false, the UART normal/queue break character setting is disabled, which
+ * configures the UART for normal transmitter operation. If true, a break
+ * character is queued for transmission.
+ */
+static inline void UART_HAL_SetBreakCharCmd(uint32_t baseAddr, bool enable)
+{
+ BW_UART_C2_SBK(baseAddr, enable);
+}
+
+/*!
+ * @brief Configures the UART match address mode control operation. (Note: Feature available on
+ * select UART baseAddrs)
+ *
+ * The function allows the user to configure the UART match address control operation. The user
+ * has the option to enable the match address mode and to program the match address value. There
+ * are two match address modes, each with its own enable and programmable match address value.
+ *
+ * @param baseAddr UART module base address.
+ * @param matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables.
+ * @param matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables.
+ * @param matchAddrValue1 The match address value to program for match address mode 1.
+ * @param matchAddrValue2 The match address value to program for match address mode 2.
+ */
+void UART_HAL_SetMatchAddress(uint32_t baseAddr, bool matchAddrMode1, bool matchAddrMode2,
+ uint8_t matchAddrValue1, uint8_t matchAddrValue2);
+
+#if FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT
+/*!
+ * @brief Configures the UART to send data MSB first
+ * (Note: Feature available on select UART baseAddrs)
+ *
+ * The function allows the user to configure the UART to send data MSB first or LSB first.
+ * In some UART baseAddrs it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable This configures send MSB first mode configuration. If true, the data is sent MSB
+ * first; if false, it is sent LSB first.
+ */
+static inline void UART_HAL_SetSendMsbFirstCmd(uint32_t baseAddr, bool enable)
+{
+ BW_UART_S2_MSBF(baseAddr, enable);
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+/*!
+ * @brief Enables the UART receiver request-to-send functionality.
+ *
+ * This function allows the user to enable the UART receiver request-to-send (RTS) functionality.
+ * By enabling, it allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data
+ * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the
+ * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
+ * Do not set both RXRTSE and TXRTSE.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable or disable receiver rts.
+ */
+static inline void UART_HAL_SetReceiverRtsCmd(uint32_t baseAddr, bool enable)
+{
+ /* Set RXRTSE */
+ BW_UART_MODEM_RXRTSE(baseAddr, enable);
+}
+
+/*!
+ * @brief Enables the UART transmitter request-to-send functionality.
+ *
+ * This function allows the user to enable the UART transmitter request-to-send (RTS) functionality.
+ * When enabled, it allows the UART to control the RTS assertion before and after a transmission
+ * such that when a character is placed into an empty transmitter data buffer, RTS
+ * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all
+ * characters in the transmitter data buffer and shift register are completely sent, including
+ * the last stop bit.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable or disable transmitter RTS.
+ */
+static inline void UART_HAL_SetTransmitterRtsCmd(uint32_t baseAddr, bool enable)
+{
+ /* Set TXRTSE */
+ BW_UART_MODEM_TXRTSE(baseAddr, enable);
+}
+
+/*!
+ * @brief Configures the UART transmitter RTS polarity.
+ *
+ * This function allows the user configure the transmitter RTS polarity to be either active low
+ * or active high.
+ *
+ * @param baseAddr UART module base address.
+ * @param polarity The UART transmitter RTS polarity setting (false - active low,
+ * true - active high).
+ */
+static inline void UART_HAL_SetTransmitterRtsPolarityMode(uint32_t baseAddr, bool polarity)
+{
+ /* Configure the transmitter rts polarity: 0=active low, 1=active high */
+ BW_UART_MODEM_TXRTSPOL(baseAddr, polarity);
+}
+
+/*!
+ * @brief Enables the UART transmitter clear-to-send functionality.
+ *
+ * This function allows the user to enable the UART transmitter clear-to-send (CTS) functionality.
+ * When enabled, the transmitter checks the state of CTS each time it is ready to send a character.
+ * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
+ * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a
+ * character is being sent do not affect its transmission.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable or disable transmitter CTS.
+ */
+static inline void UART_HAL_SetTransmitterCtsCmd(uint32_t baseAddr, bool enable)
+{
+ /* Set TXCTSE */
+ BW_UART_MODEM_TXCTSE(baseAddr, enable);
+}
+
+#endif /* FSL_FEATURE_UART_HAS_MODEM_SUPPORT*/
+
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+/*!
+ * @brief Configures the UART infrared operation.
+ *
+ * The function allows the user to enable or disable the UART infrared (IR) operation
+ * and to configure the IR pulse width.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable (true) or disable (false) the infrared operation.
+ * @param pulseWidth The UART transmit narrow pulse width setting of type uart_ir_tx_pulsewidth_t.
+ */
+void UART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable,
+ uart_ir_tx_pulsewidth_t pulseWidth);
+#endif /* FSL_FEATURE_UART_HAS_IR_SUPPORT*/
+
+/*@}*/
+
+/*!
+ * @name UART Status Flags
+ * @{
+ */
+
+/*!
+ * @brief Gets all UART status flag states.
+ *
+ * @param baseAddr UART module base address.
+ * @param statusFlag Status flag name.
+ */
+bool UART_HAL_GetStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag);
+
+/*!
+ * @brief Gets the UART Transmit data register empty flag.
+ *
+ * This function returns the state of the UART Transmit data register empty flag.
+ *
+ * @param baseAddr UART module base address.
+ * @return The status of Transmit data register empty flag, which is set when transmit buffer
+ * is empty.
+ */
+static inline bool UART_HAL_IsTxDataRegEmpty(uint32_t baseAddr)
+{
+ /* return status condition of TDRE flag */
+ return BR_UART_S1_TDRE(baseAddr);
+}
+
+/*!
+ * @brief Gets the UART Transmission complete flag.
+ *
+ * This function returns the state of the UART Transmission complete flag.
+ *
+ * @param baseAddr UART module base address.
+ * @return The status of Transmission complete flag, which is set when the transmitter is idle
+ * (transmission activity complete).
+ */
+static inline bool UART_HAL_IsTxComplete(uint32_t baseAddr)
+{
+ /* return status condition of TC flag */
+ return BR_UART_S1_TC(baseAddr);
+}
+
+/*!
+ * @brief Gets the UART Receive data register full flag.
+ *
+ * This function returns the state of the UART Receive data register full flag.
+ *
+ * @param baseAddr UART module base address.
+ * @return The status of Receive data register full flag, which is set when the receive data buffer
+ * is full.
+ */
+static inline bool UART_HAL_IsRxDataRegFull(uint32_t baseAddr)
+{
+ /* return status condition of RDRF flag */
+ return BR_UART_S1_RDRF(baseAddr);
+}
+
+/*!
+ * @brief Clears an individual and specific UART status flag.
+ *
+ * This function allows the user to clear an individual and specific UART status flag. Refer to
+ * structure definition uart_status_flag_t for list of status bits.
+ *
+ * @param baseAddr UART module base address.
+ * @param statusFlag The desired UART status flag to clear.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_ClearStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag);
+
+/*!
+ * @brief Clears all UART status flags.
+ *
+ * This function tries to clear all of the UART status flags. In some cases, some of the status
+ * flags may not get cleared because the condition that set the flag may still exist.
+ *
+ * @param baseAddr UART module base address.
+ */
+void UART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr);
+
+/*@}*/
+
+/*!
+ * @name UART FIFO Configurations
+ * @{
+ */
+
+#if FSL_FEATURE_UART_HAS_FIFO
+/*!
+ * @brief Enables or disable the UART transmit FIFO.
+ *
+ * This function allows the user to enable or disable the UART transmit FIFO.
+ * It is required that the transmitter/receiver be disabled before calling this function
+ * when the FIFO is empty.
+ * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable or disable Tx FIFO.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ * kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetTxFifoCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Enables or disable the UART receive FIFO.
+ *
+ * This function allows the user to enable or disable the UART receive FIFO.
+ * It is required that the transmitter/receiver be disabled before calling this function
+ * when the FIFO is empty.
+ * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function.
+ *
+ * @param baseAddr UART module base address.
+ * @param enable Enable or disable Rx FIFO.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ * kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetRxFifoCmd(uint32_t baseAddr, bool enable);
+
+/*!
+ * @brief Gets the size of the UART transmit FIFO.
+ *
+ * This function returns the size (number of entries) supported in the UART transmit FIFO for
+ * a particular module baseAddr.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART transmit FIFO size as follows:
+ * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words
+ * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved
+ */
+static inline uint8_t UART_HAL_GetTxFifoSize(uint32_t baseAddr)
+{
+ return BR_UART_PFIFO_TXFIFOSIZE(baseAddr);
+}
+
+/*!
+ * @brief Gets the size of the UART receive FIFO.
+ *
+ * This function returns the size (number of entries) supported in the UART receive FIFO for
+ * a particular module baseAddr.
+ *
+ * @param baseAddr UART module base address.
+ * @return The receive FIFO size as follows:
+ * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words
+ * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved
+ */
+static inline uint8_t UART_HAL_GetRxFifoSize(uint32_t baseAddr)
+{
+ return BR_UART_PFIFO_RXFIFOSIZE(baseAddr);
+}
+
+/*!
+ * @brief Flushes the UART transmit FIFO.
+ *
+ * This function allows the user to flush the UART transmit FIFO for a particular module baseAddr.
+ * Flushing the FIFO may result in data loss.
+ * It is recommended that the transmitter be disabled before calling this function.
+ *
+ * @param baseAddr UART module base address.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ * kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_FlushTxFifo(uint32_t baseAddr);
+
+/*!
+ * @brief Flushes the UART receive FIFO.
+ *
+ * This function allows the user to flush the UART receive FIFO for a particular module baseAddr.
+ * Flushing the FIFO may result in data loss.
+ * It is recommended that the receiver be disabled before calling this function.
+ *
+ * @param baseAddr UART module base address.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ * kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_FlushRxFifo(uint32_t baseAddr);
+
+/*!
+ * @brief Gets the UART transmit FIFO empty status state.
+ *
+ * The function returns the state of the transmit FIFO empty status state, but does not take into
+ * account data in the shift register.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART transmit FIFO empty status: true=empty; false=not-empty.
+ */
+static inline bool UART_HAL_IsTxFifoEmpty(uint32_t baseAddr)
+{
+ return BR_UART_SFIFO_TXEMPT(baseAddr);
+}
+
+/*!
+ * @brief Gets the UART receive FIFO empty status state.
+ *
+ * The function returns the state of the receive FIFO empty status state, but does not take into
+ * account data in the shift register.
+ *
+ * @param baseAddr UART module base address.
+ * @return The UART receive FIFO empty status: true=empty; false=not-empty.
+ */
+static inline bool UART_HAL_IsRxFifoEmpty(uint32_t baseAddr)
+{
+ return BR_UART_SFIFO_RXEMPT(baseAddr);
+}
+
+/*!
+ * @brief Sets the UART transmit FIFO watermark value.
+ *
+ * Programming the transmit watermark should be done when UART the transmitter is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetTxFifoSize.
+ *
+ * @param baseAddr UART module base address.
+ * @param watermark The UART transmit watermark value to be programmed.
+ * @return Error code if transmitter is enabled or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetTxFifoWatermark(uint32_t baseAddr, uint8_t watermark);
+
+/*!
+ * @brief Gets the UART transmit FIFO watermark value.
+ *
+ * @param baseAddr UART module base address.
+ * @return The value currently programmed for the UART transmit watermark.
+ */
+static inline uint8_t UART_HAL_GetTxFifoWatermark(uint32_t baseAddr)
+{
+ /* get watermark*/
+ return HW_UART_TWFIFO_RD(baseAddr);
+}
+
+/*!
+ * @brief Gets the UART transmit FIFO data word count (number of words in the transmit FIFO).
+ *
+ * The function UART_HAL_GetTxDatawordCountInFifo excludes any data that may
+ * be in the UART transmit shift register
+ *
+ * @param baseAddr UART module base address.
+ * @return The number of data words currently in the UART transmit FIFO.
+ */
+static inline uint8_t UART_HAL_GetTxDatawordCountInFifo(uint32_t baseAddr)
+{
+ /* get the current number of datawords in the FIFO*/
+ return HW_UART_TCFIFO_RD(baseAddr);
+}
+
+/*!
+ * @brief Sets the UART receive FIFO watermark value.
+ *
+ * Programming the receive watermark should be done when the receiver is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize and
+ * greater than zero.
+ *
+ * @param baseAddr UART module base address.
+ * @param watermark The UART receive watermark value to be programmed.
+ * @return Error code if receiver is enabled or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetRxFifoWatermark(uint32_t baseAddr, uint8_t watermark);
+
+/*!
+ * @brief Gets the UART receive FIFO data word count (number of words in the receive FIFO).
+ *
+ * The function UART_HAL_GetRxDatawordCountInFifo excludes any data that may be
+ * in the receive shift register.
+ *
+ * @param baseAddr UART module base address.
+ * @return The number of data words currently in the UART receive FIFO.
+ */
+static inline uint8_t UART_HAL_GetRxDatawordCountInFifo(uint32_t baseAddr)
+{
+ /* get the current number of datawords in the FIFO*/
+ return HW_UART_RCFIFO_RD(baseAddr);
+}
+
+/*!
+ * @brief Gets the UART receive FIFO watermark value.
+ *
+ * @param baseAddr UART module base address.
+ * @return The value currently programmed for the UART receive watermark.
+ */
+static inline uint8_t UART_HAL_GetRxFifoWatermark(uint32_t baseAddr)
+{
+ /* get watermark*/
+ return HW_UART_RWFIFO_RD(baseAddr);
+}
+
+#endif /* FSL_FEATURE_UART_HAS_FIFO*/
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_UART_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_features.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,87 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b140515 +** +** Abstract: +** Chip specific module features. +** +** Copyright: 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_WDOG_FEATURES_H__) +#define __FSL_WDOG_FEATURES_H__ + +#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ + defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ + defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ + defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ + defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ + defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ + defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ + defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ + defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ + defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ + defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ + defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ + defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ + defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ + defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ + defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ + defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ + defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ + defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ + defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ + defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ + defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) + /* @brief Watchdog is available. */ + #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_WDOG_FEATURES_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wdog_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : WDOG_HAL_Init
+ * Description : Initialize WDOG peripheral to reset state.
+ *
+ *END**************************************************************************/
+void WDOG_HAL_Init(uint32_t baseAddr)
+{
+ wdog_common_config wdogCommonConfig;
+ wdogCommonConfig.commonConfig.workInWaitModeEnable = (uint8_t)true;
+ wdogCommonConfig.commonConfig.workInDebugModeEnable = (uint8_t)false;
+ wdogCommonConfig.commonConfig.workInStopModeEnable = (uint8_t)true;
+ wdogCommonConfig.commonConfig.clockSource = (uint8_t)kWdogClockSourceBusClock;
+ wdogCommonConfig.commonConfig.interruptEnable = (uint8_t)false;
+ wdogCommonConfig.commonConfig.windowModeEnable = (uint8_t)false;
+ wdogCommonConfig.commonConfig.updateRegisterEnable = (uint8_t)true;
+ wdogCommonConfig.commonConfig.wdogEnable = (uint8_t)(true);
+
+ WDOG_HAL_Unlock(baseAddr);
+ WDOG_HAL_SetTimeoutValue(baseAddr, 0x004C4B4CU);
+ WDOG_HAL_SetWindowValue(baseAddr, 0);
+ WDOG_HAL_SetClockPrescalerValueMode(baseAddr, kWdogClockPrescalerValueDevide5);
+ WDOG_HAL_ClearIntFlag(baseAddr);
+ WDOG_HAL_SetCommonConfig(baseAddr, wdogCommonConfig);
+
+}
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_WDOG_HAL_H__
+#define __FSL_WDOG_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_wdog_features.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup wdog_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+#define WDOG_UNLOCK_VALUE_HIGH (0xC520U)
+#define WDOG_UNLOCK_VALUE_LOW (0xD928U)
+
+#define WDOG_REFRESH_VALUE_HIGH (0xA602U)
+#define WDOG_REFRESH_VALUE_LOW (0xB480U)
+
+/*! @brief Watchdog clock source selection.*/
+typedef enum _wdog_clock_source {
+ kWdogClockSourceLpoClock = 0x0U, /*!< Clock source is LPO clock */
+ kWdogClockSourceBusClock = 0x1U /*!< Clock source is Bus clock */
+} wdog_clock_source_t;
+
+/*! @brief Define the selection of the clock prescaler*/
+typedef enum _wdog_clock_prescaler_value {
+ kWdogClockPrescalerValueDevide1 = 0x0U, /*!< Divided by 1 */
+ kWdogClockPrescalerValueDevide2 = 0x1U, /*!< Divided by 2 */
+ kWdogClockPrescalerValueDevide3 = 0x2U, /*!< Divided by 3 */
+ kWdogClockPrescalerValueDevide4 = 0x3U, /*!< Divided by 4 */
+ kWdogClockPrescalerValueDevide5 = 0x4U, /*!< Divided by 5 */
+ kWdogClockPrescalerValueDevide6 = 0x5U, /*!< Divided by 6 */
+ kWdogClockPrescalerValueDevide7 = 0x6U, /*!< Divided by 7 */
+ kWdogClockPrescalerValueDevide8 = 0x7U /*!< Divided by 8 */
+} wdog_clock_prescaler_value_t;
+
+/*! @brief Define the common configure */
+typedef union _wdog_common_config {
+ uint32_t U;
+ struct CommonConfig {
+ uint32_t wdogEnable:1; /*!< Enable configure, 1 means enable WDOG */
+ uint32_t clockSource:1; /*!< Clock source */
+ uint32_t interruptEnable:1; /*!< WDOG interrupt configure, 1 means enable interrupt */
+ uint32_t windowModeEnable:1; /*!< Window mode configure, 1 means enable window mode */
+ uint32_t updateRegisterEnable:1; /*!< 1 means WDOG register can reconfigure by unlock */
+ uint32_t workInDebugModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
+ uint32_t workInStopModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
+ uint32_t workInWaitModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
+ uint32_t reserved0:1; /*!< Reserved */
+ uint32_t reserved1:1; /*!< Reserved */
+ uint32_t testWdog:1; /*!< WDOG enable configure */
+ uint32_t testSelect:1; /*!< 0 means quick test, 1 means byte test */
+ uint32_t byteSelect:2; /*!< Test byte select */
+ uint32_t disableTestWdog:1; /*!< 1 means WDOG test mode is disabled */
+ uint32_t reserved2:1; /*!< Reserved */
+ uint32_t reserved3:16; /*!< Reserved */
+ } commonConfig;
+} wdog_common_config;
+
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Watchdog HAL.
+ * @{
+ */
+
+/*!
+ * @brief Sets the WDOG common configure.
+ *
+ * This function is used to set the WDOG common configure.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, the WCT window is still open and
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * The common configuration is controlled by the WDOG_STCTRLH. This is a write-once register and this interface
+ * is used to set all field of the WDOG_STCTRLH registers at the same time.
+ * If only one field needs to be set, the API can be used. These API write to the WDOG_STCTRLH register:
+ * #WDOG_HAL_Enable,#WDOG_HAL_Disable,#WDOG_HAL_SetIntCmd,#WDOG_HAL_SetClockSourceMode,#WDOG_HAL_SetWindowModeCmd,
+ * #WDOG_HAL_SetRegisterUpdateCmd,#WDOG_HAL_SetWorkInDebugModeCmd,#WDOG_HAL_SetWorkInStopModeCmd,
+ * #WDOG_HAL_SetWorkInWaitModeCmd
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param commonConfig The common configure of the WDOG
+ */
+static inline void WDOG_HAL_SetCommonConfig(uint32_t baseAddr, wdog_common_config commonConfig)
+{
+ HW_WDOG_STCTRLH_WR(baseAddr,(uint16_t)commonConfig.U);
+}
+
+/*!
+ * @brief Enables the Watchdog module.
+ *
+ * This function enables the WDOG.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Enable(uint32_t baseAddr)
+{
+ BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)true);
+}
+
+/*!
+ * @brief Disables the Watchdog module.
+ *
+ * This function disables the WDOG.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Disable(uint32_t baseAddr)
+{
+ BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)false);
+}
+
+/*!
+ * @brief Checks whether the WDOG is enabled.
+ *
+ * This function checks whether the WDOG is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means WDOG is disabled, true means WODG is enabled.
+ *
+ */
+static inline bool WDOG_HAL_IsEnabled(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_WDOGEN(baseAddr);
+}
+
+/*!
+ * @brief Enables and disables the Watchdog interrupt.
+ *
+ * This function enables or disables the WDOG interrupt.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means disable watchdog interrupt and true means enable watchdog interrupt.
+ */
+static inline void WDOG_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_IRQRSTEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the WDOG interrupt is enabled.
+ *
+ * This function checks whether the WDOG interrupt is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means interrupt is disabled, true means interrupt is enabled.
+ */
+static inline bool WDOG_HAL_GetIntCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_IRQRSTEN(baseAddr);
+}
+
+/*!
+ * @brief Sets the Watchdog clock Source.
+ *
+ * This function sets the WDOG clock source. There are two clock sources that can be used:
+ * the LPO clock and the bus clock.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param clockSource watchdog clock source, see #wdog_clock_source_t.
+ */
+static inline void WDOG_HAL_SetClockSourceMode(uint32_t baseAddr, wdog_clock_source_t clockSource)
+{
+ BW_WDOG_STCTRLH_CLKSRC(baseAddr, (uint8_t)clockSource);
+}
+
+/*!
+ * @brief Gets the Watchdog clock Source.
+ *
+ * This function gets the WDOG clock source. There are two clock sources that can be used:
+ * the LPO clock and the bus clock.
+ * A Clock Switching Delay time is about 2 clock A cycles plus 2
+ * clock B, where clock A and B are the two input clocks to the clock mux.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return watchdog clock source, see #wdog_clock_source_t.
+ */
+static inline wdog_clock_source_t WDOG_HAL_GetClockSourceMode(uint32_t baseAddr)
+{
+ return (wdog_clock_source_t)BR_WDOG_STCTRLH_CLKSRC(baseAddr);
+}
+
+/*!
+ * @brief Enables and disables the Watchdog window mode.
+ *
+ * This function configures the WDOG window mode.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means disable watchdog window mode. true means enable watchdog window mode.
+ */
+static inline void WDOG_HAL_SetWindowModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_WINEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the window mode is enabled.
+ *
+ * This function checks whether the WDOG window mode is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means window mode is disabled, true means window mode is enabled.
+ */
+static inline bool WDOG_HAL_GetWindowModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_WINEN(baseAddr);
+}
+
+/*!
+ * @brief Enables and disables the Watchdog write-once-only register update.
+ *
+ * This function configures the WDOG register update feature. If disabled, it means that
+ * all WDOG registers is never written again unless Power On Reset.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means disable watchdog write-once-only register update.
+ * true means enable watchdog write-once-only register update.
+ */
+static inline void WDOG_HAL_SetRegisterUpdateCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_ALLOWUPDATE(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the register update is enabled.
+ *
+ * This function checks whether the WDOG register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means register update is disabled, true means register update is enabled.
+ */
+static inline bool WDOG_HAL_GetRegisterUpdateCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_ALLOWUPDATE(baseAddr);
+}
+
+/*!
+ * @brief Sets whether Watchdog is working while the CPU is in debug mode.
+ *
+ * This function configures whether the WDOG is enabled in the CPU debug mode.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means watchdog is disabled in CPU debug mode.
+ * true means watchdog is enabled in CPU debug mode.
+ */
+static inline void WDOG_HAL_SetWorkInDebugModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_DBGEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the WDOG works while in the CPU debug mode.
+ *
+ * This function checks whether the WDOG works in the CPU debug mode.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means not work while in CPU debug mode, true means works while in CPU debug mode.
+ */
+static inline bool WDOG_HAL_GetWorkInDebugModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_DBGEN(baseAddr);
+}
+
+/*!
+ * @brief Sets whether the Watchdog is working while the CPU is in stop mode.
+ *
+ * This function configures whether the WDOG is enabled in the CPU stop mode.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means watchdog is disabled in CPU stop mode.
+ * true means watchdog is enabled in CPU stop mode.
+ */
+static inline void WDOG_HAL_SetWorkInStopModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_STOPEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the WDOG works while in CPU stop mode.
+ *
+ * This function checks whether the WDOG works in the CPU stop mode.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means not work while in CPU stop mode, true means works while in CPU stop mode.
+ */
+static inline bool WDOG_HAL_GetWorkInStopModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_STOPEN(baseAddr);
+}
+
+/*!
+ * @brief Sets whether the Watchdog is working while the CPU is in wait mode.
+ *
+ * This function configures whether the WDOG is enabled in the CPU wait mode.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param enable false means watchdog is disabled in CPU wait mode.
+ * true means watchdog is enabled in CPU wait mode.
+ */
+static inline void WDOG_HAL_SetWorkInWaitModeCmd(uint32_t baseAddr, bool enable)
+{
+ BW_WDOG_STCTRLH_WAITEN(baseAddr, (uint8_t)enable);
+}
+
+/*!
+ * @brief Checks whether the WDOG works while in the CPU wait mode.
+ *
+ * This function checks whether the WDOG works in the CPU wait mode.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return false means not work while in CPU wait mode, true means works while in CPU wait mode.
+ */
+
+static inline bool WDOG_HAL_GetWorkInWaitModeCmd(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLH_WAITEN(baseAddr);
+}
+
+/*!
+ * @brief Gets the Watchdog interrupt status.
+ *
+ * This function gets the WDOG interrupt flag.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return Watchdog interrupt status, false means interrupt not asserted, true means interrupt asserted.
+ */
+static inline bool WDOG_HAL_IsIntPending(uint32_t baseAddr)
+{
+ return (bool)BR_WDOG_STCTRLL_INTFLG(baseAddr);
+}
+
+/*!
+ * @brief Clears the Watchdog interrupt flag.
+ *
+ * This function clears the WDOG interrupt flag.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_ClearIntFlag(uint32_t baseAddr)
+{
+ BW_WDOG_STCTRLL_INTFLG(baseAddr, true);
+}
+
+/*!
+ * @brief Set the Watchdog timeout value.
+ *
+ * This function sets the WDOG_TOVAL value.
+ * It should be ensured that the time-out value for the Watchdog is always greater than
+ * 2xWCT time + 20 bus clock cycles.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
+ * this API has not been called in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param timeoutCount watchdog timeout value, count of watchdog clock tick.
+ */
+static inline void WDOG_HAL_SetTimeoutValue(uint32_t baseAddr, uint32_t timeoutCount)
+{
+ HW_WDOG_TOVALH_WR(baseAddr, (uint16_t)((timeoutCount >> 16U) & 0xFFFFU));
+ HW_WDOG_TOVALL_WR(baseAddr, (uint16_t)((timeoutCount) & 0xFFFFU));
+}
+
+/*!
+ * @brief Gets the Watchdog timeout value.
+ *
+ * This function gets the WDOG_TOVAL value.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return value of register WDOG_TOVAL.
+ */
+static inline uint32_t WDOG_HAL_GetTimeoutValue(uint32_t baseAddr)
+{
+ return (uint32_t)((((uint32_t)(HW_WDOG_TOVALH_RD(baseAddr))) << 16U) | (HW_WDOG_TOVALL_RD(baseAddr)));
+}
+
+/*!
+ * @brief Gets the Watchdog timer output.
+ *
+ * This function gets the WDOG_TMROUT value.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return Current value of watchdog timer counter.
+ */
+static inline uint32_t WDOG_HAL_GetTimerOutputValue(uint32_t baseAddr)
+{
+ return (uint32_t)((((uint32_t)(HW_WDOG_TMROUTH_RD(baseAddr))) << 16U) | (HW_WDOG_TMROUTL_RD(baseAddr)));
+}
+
+/*!
+ * @brief Sets the Watchdog clock prescaler.
+ *
+ * This function sets the WDOG clock prescaler.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
+ * this API has not been called in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param clockPrescaler watchdog clock prescaler, see #wdog_clock_prescaler_value_t.
+ */
+static inline void WDOG_HAL_SetClockPrescalerValueMode(uint32_t baseAddr, wdog_clock_prescaler_value_t clockPrescaler)
+{
+ BW_WDOG_PRESC_PRESCVAL(baseAddr, (uint8_t)clockPrescaler);
+}
+
+/*!
+ * @brief Gets the Watchdog clock prescaler.
+ *
+ * This function gets the WDOG clock prescaler.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return WDOG clock prescaler, see #wdog_clock_prescaler_value_t.
+ */
+static inline wdog_clock_prescaler_value_t WDOG_HAL_GetClockPrescalerValueMode(uint32_t baseAddr)
+{
+ return (wdog_clock_prescaler_value_t)BR_WDOG_PRESC_PRESCVAL(baseAddr);
+}
+
+/*!
+ * @brief Sets the Watchdog window value.
+ *
+ * This function sets the WDOG_WIN value.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
+ * this API has not been called in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @param windowValue watchdog window value.
+ */
+static inline void WDOG_HAL_SetWindowValue(uint32_t baseAddr, uint32_t windowValue)
+{
+ HW_WDOG_WINH_WR(baseAddr, (uint16_t)((windowValue>>16U) & 0xFFFFU));
+ HW_WDOG_WINL_WR(baseAddr, (uint16_t)((windowValue) & 0xFFFFU));
+}
+
+/*!
+ * @brief Gets the Watchdog window value.
+ *
+ * This function gets the WDOG_WIN value.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return watchdog window value.
+ */
+static inline uint32_t WDOG_HAL_GetWindowValue(uint32_t baseAddr)
+{
+ return (uint32_t)((((uint32_t)(HW_WDOG_WINH_RD(baseAddr))) << 16U) | (HW_WDOG_WINL_RD(baseAddr)));
+}
+
+/*!
+ * @brief Unlocks the Watchdog register written.
+ *
+ * This function unlocks the WDOG register written.
+ * This function must be called before any configuration is set because watchdog register
+ * will be locked automatically after a WCT(256 bus cycles).
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Unlock(uint32_t baseAddr)
+{
+ HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_HIGH);
+ HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_LOW);
+}
+
+/*!
+ * @brief Refreshes the Watchdog timer.
+ *
+ * This function feeds the WDOG.
+ * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Refresh(uint32_t baseAddr)
+{
+ HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH);
+ HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_LOW);
+}
+
+/*!
+ * @brief Resets the chip using the Watchdog.
+ *
+ * This function resets the chip using WDOG.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_ResetSystem(uint32_t baseAddr)
+{
+ HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH);
+ HW_WDOG_REFRESH_WR(baseAddr, 0);
+ while(1)
+ {
+ }
+}
+
+/*!
+ * @brief Gets the chip reset count that was reset by Watchdog.
+ *
+ * This function gets the value of the WDOG_RSTCNT.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ * @return Chip reset count that was reset by Watchdog.
+ */
+static inline uint32_t WDOG_HAL_GetResetCount(uint32_t baseAddr)
+{
+ return HW_WDOG_RSTCNT_RD(baseAddr);
+}
+
+/*!
+ * @brief Clears the chip reset count that was reset by Watchdog.
+ *
+ * This function clears the WDOG_RSTCNT.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_ClearResetCount(uint32_t baseAddr)
+{
+ HW_WDOG_RSTCNT_WR(baseAddr, 0xFFFFU);
+}
+
+/*!
+ * @brief Restores the WDOG module to reset value.
+ *
+ * This function restores the WDOG module to reset value.
+ *
+ * @param baseAddr The WDOG peripheral base address
+ */
+void WDOG_HAL_Init(uint32_t baseAddr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_WDOG_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/mbed KSDK readme.txt Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,15 @@ +This document is not complete, please try to add more to it to keep it as much up-to-date as possible. + +*************ADDING NEW TARGET************* +TODO (partially) + +UNAVAILABLE PERIPHERALS: +The original build system of the KSDK simply does not compile files which are not available on a target, mbed tries to compile everything. If your target tries to compile a peripheral which is not available, compilation will fail with a "No valid CPU defined!" error message. In the file which throws the error, replace the error code with: #define MBED_NO_[PERIPHERAL-NAME]. Then in the other .h and .c file in the same folder add #ifndef guards. See for an example: \mbed\targets\hal\TARGET_Freescale\TARGET_KPSDK_MCUS\TARGET_KPSDK_CODE\hal\lpuart. + +SYSTEM_MKXXXXX.C: +The file included in the top cannot be found by the compiler, replace it by cmsis.h + + + +************UPDATING KSDK FILES************ +TODO (Also good luck with it). \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/utilities/fsl_misc_utilities.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_MISC_UTILITIES_H__ +#define __FSL_MISC_UTILITIES_H__ + +#include <stdint.h> + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Min/max macros */ +#if !defined(MIN) + #define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) + #define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +/*! @brief Computes the number of elements in an array.*/ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/*! @brief Byte swap macros */ +#define BSWAP_16(x) (uint16_t)((((x) & 0xFF00) >> 0x8) | (((x) & 0xFF) << 0x8)) +#define BSWAP_32(val) (uint32_t)((BSWAP_16((uint32_t)(val) & (uint32_t)0xFFFF) << 0x10) | \ + (BSWAP_16((uint32_t)((val) >> 0x10)))) + +#endif /* __FSL_MISC_UTILITIES_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,572 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OS_ABSTRACTION_H__)
+#define __FSL_OS_ABSTRACTION_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#if defined __CC_ARM
+#define inline __inline
+#endif
+
+/*!
+ * @addtogroup os_abstraction
+ * @{
+ */
+
+/*! @brief Status values to be returned by functions. */
+typedef enum
+{
+ kSuccess = 0, /*!< Functions work correctly. */
+ kError, /*!< Functions work failed. */
+ kTimeout, /*!< Timeout occurs while waiting for an object. */
+ kIdle /*!< Can not get the object in non-blocking mode.*/
+}fsl_rtos_status;
+
+/*! @brief The event flags are set or not.*/
+typedef enum
+{
+ kFlagNotSet = 0, /*!< The flags checked are set. */
+ kFlagSet /*!< The flags checked are not set. */
+}event_status;
+
+/*! @brief The event flags are cleared automatically or manually.*/
+typedef enum
+{
+ kEventAutoClr = 0, /*!< The flags of the event will be cleared automatically. */
+ kEventManualClr /*!< The flags of the event will be cleared manually. */
+}event_clear_type;
+
+// Temporary "fix", until the proper macros are integrated in the on-line build system
+#define FSL_RTOS_MBED
+
+/* Include required header file based on RTOS selection */
+#if defined (FSL_RTOS_MQX)
+ /*! @brief Macro to set message queue copy messages to internal memory or not. */
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_mqx.h"
+
+#elif defined (FSL_RTOS_FREE_RTOS)
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_free_rtos.h"
+
+#elif defined (FSL_RTOS_UCOSII)
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_ucosii.h"
+
+#elif defined (FSL_RTOS_UCOSIII)
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_ucosiii.h"
+
+#elif defined (FSL_RTOS_CMSIS)
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 0
+ #include "fsl_os_abstraction_cmsis.h"
+
+#elif defined (FSL_RTOS_MBED)
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_mbed.h"
+
+#else
+ #define __FSL_RTOS_MSGQ_COPY_MSG__ 1
+ #include "fsl_os_abstraction_bm.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Synchronization
+ * @{
+ */
+
+/*!
+ * @brief Initialize a synchronization object to a given state.
+ *
+ * @param obj The sync object to initialize.
+ * @param initValue The initial value the object will be set to.
+ *
+ * @retval kSuccess The object was successfully created.
+ * @retval kError Invalid parameter or no more objects can be created.
+ */
+fsl_rtos_status sync_create(sync_object_t *obj, uint8_t initValue);
+
+/*!
+ * @brief Wait for the synchronization object.
+ *
+ * This function checks the sync object's counting value, if it is
+ * positive, decreases it and returns kSuccess, otherwise, timeout will be
+ * used for wait.
+ *
+ * @param obj Pointer to the synchronization object.
+ * @param timeout The maximum number of milliseconds to wait for the object to be signalled.
+ * Pass the #kSyncWaitForever constant to wait indefinitely for someone to signal the object.
+ * A value of 0 should not be passed to this function. Instead, use sync_poll for
+ * a non blocking check.
+ *
+ * @retval kSuccess The object was signalled.
+ * @retval kTimeout A timeout occurred.
+ * @retval kError An incorrect parameter was passed.
+ * @retval kIdle The object has not been signalled.
+ *
+ * @note There could be only one process waiting for the object at the same time.
+ */
+fsl_rtos_status sync_wait(sync_object_t *obj, uint32_t timeout);
+
+/*!
+ * @brief Checks a synchronization object's status.
+ *
+ * This function is used to poll a sync object's status.
+ * If the sync object's counting value is positive, decrease it and return
+ * kSuccess. If the object's counting value is 0, the function will
+ * return kIdle immediately
+ *
+ * @param obj The synchronization object.
+ *
+ * @retval kSuccess The object was signalled.
+ * @retval kIdle The object was not signalled.
+ * @retval kError An incorrect parameter was passed.
+ */
+fsl_rtos_status sync_poll(sync_object_t *obj);
+
+/*!
+ * @brief Signal for someone waiting on the synchronization object to wake up.
+ *
+ * This function should not be called from an ISR.
+ *
+ * @param obj The synchronization object to signal.
+ *
+ * @retval kSuccess The object was successfully signaled.
+ * @retval kError The object can not be signaled or invalid parameter.
+ */
+fsl_rtos_status sync_signal(sync_object_t *obj);
+
+/*!
+ * @brief Signal for someone waiting on the synchronization object to wake up.
+ *
+ * This function should only be called from an ISR.
+ *
+ * @param obj The synchronization object to signal.
+ *
+ * @retval kSuccess The object was successfully signaled.
+ * @retval kError The object can not be signaled or invalid parameter.
+ */
+fsl_rtos_status sync_signal_from_isr(sync_object_t *obj);
+
+/*!
+ * @brief Destroy a previously created synchronization object.
+ *
+ * @param obj The synchronization object to destroy.
+ *
+ * @retval kSuccess The object was successfully destroyed.
+ * @retval kError Object destruction failed.
+ */
+fsl_rtos_status sync_destroy(sync_object_t *obj);
+
+/* @} */
+
+/*!
+ * @name Resource locking
+ * @{
+ */
+
+/*!
+ * @brief Initialize a locking object.
+ *
+ * @param obj The lock object to initialize.
+ *
+ * @retval kSuccess The lock is created successfully.
+ * @retval kError Tke lock creation failed.
+ */
+fsl_rtos_status lock_create(lock_object_t *obj);
+
+/*!
+ * @brief Wait for the object to be unlocked and lock it.
+ *
+ * This function will wait for some time or wait forever if could not get the lock.
+ *
+ * @param obj The locking object.
+ * @param timeout The maximum number of milliseconds to wait for the mutex.
+ * Pass the #kSyncWaitForever constant to wait indefinitely for someone to unlock the object.
+ * A value of 0 should not be passed to this function. Instead, use lock_poll for a non
+ * blocking check.
+ *
+ * @retval kSuccess The lock was obtained.
+ * @retval kTimeout A timeout occurred.
+ * @retval kError An incorrect parameter was passed.
+ */
+fsl_rtos_status lock_wait(lock_object_t *obj, uint32_t timeout);
+
+/*!
+ * @brief Checks if a locking object can be locked and locks it if possible.
+ *
+ * This function returns instantly if could not get the lock.
+ *
+ * @param obj The locking object.
+ *
+ * @retval kSuccess The lock was obtained.
+ * @retval kIdle The lock could not be obtained.
+ * @retval kError An incorrect parameter was passed.
+ *
+ * @note There could be only one process waiting for the object at the same time.
+ * For RTOSes, wait for a lock recursively by one task is not supported.
+ *
+ */
+fsl_rtos_status lock_poll(lock_object_t *obj);
+
+/*!
+ * @brief Unlock a previously locked object.
+ *
+ * @param obj The locking object to unlock.
+ *
+ * @retval kSuccess The object was successfully unlocked.
+ * @retval kError The object can not be unlocked or invalid parameter.
+ */
+fsl_rtos_status lock_release(lock_object_t *obj);
+
+/*!
+ * @brief Destroy a previously created locking object.
+ *
+ * @param obj The locking object to destroy.
+ *
+ * @retval kSuccess The object was successfully destroyed.
+ * @retval kError Object destruction failed.
+ */
+fsl_rtos_status lock_destroy(lock_object_t *obj);
+
+/* @} */
+
+/*!
+ * @name Event signaling
+ * @{
+ */
+
+/*!
+ * @brief Initializes the event object.
+ *
+ * When the object is created, the flags is 0.
+ *
+ * @param obj Pointer to the event object to initialize.
+ * @param clearType The event is auto-clear or manual-clear.
+ *
+ * @retval kSuccess The object was successfully created.
+ * @retval kError Incorrect parameter or no more objects can be created.
+ */
+fsl_rtos_status event_create(event_object_t *obj, event_clear_type clearType);
+
+/*!
+ * @brief Wait for any event flags to be set.
+ *
+ * This function will wait for some time or wait forever if no flags are set. Any flags set
+ * will wake up the function.
+ *
+ * @param obj The event object.
+ * @param timeout The maximum number of milliseconds to wait for the event.
+ * Pass the #kSyncWaitForever constant to wait indefinitely. A value of 0 should not be passed
+ * to this function.
+ * @param setFlags Pointer to receive the flags that were set.
+ *
+ * @retval kSuccess An event was set.
+ * @retval kTimeout A timeout occurred.
+ * @retval kError An incorrect parameter was passed.
+ */
+fsl_rtos_status event_wait(event_object_t *obj, uint32_t timeout, event_group_t *setFlags);
+
+/*!
+ * @brief Set one or more event flags of an event object.
+ *
+ * This function should not be called from an ISR.
+ *
+ * @param obj The event object.
+ * @param flags Event flags to be set.
+ *
+ * @retval kSuccess The flags were successfully set.
+ * @retval kError An incorrect parameter was passed.
+ *
+ * @note There could be only one process waiting for the event.
+ *
+ */
+fsl_rtos_status event_set(event_object_t *obj, event_group_t flags);
+
+/*!
+ * @brief Set one or more event flags of an event object.
+ *
+ * This function should only be called from an ISR.
+ *
+ * @param obj The event object.
+ * @param flags Event flags to be set.
+ *
+ * @retval kSuccess The flags were successfully set.
+ * @retval kError An incorrect parameter was passed.
+ */
+fsl_rtos_status event_set_from_isr(event_object_t *obj, event_group_t flags);
+
+/*!
+ * @brief Clear one or more events of an event object.
+ *
+ * This function should not be called from an ISR.
+ *
+ * @param obj The event object.
+ * @param flags Event flags to be clear.
+ *
+ * @retval kSuccess The flags were successfully cleared.
+ * @retval kError An incorrect parameter was passed.
+ */
+fsl_rtos_status event_clear(event_object_t *obj, event_group_t flags);
+
+/*!
+ * @brief Check the flags are set or not.
+ *
+ * @param obj The event object.
+ * @param flag The flag to check.
+ *
+ * @retval kFlagsSet The flags checked are set.
+ * @retval kFlagsNotSet The flags checked are not set or got an error.
+ */
+event_status event_check_flags(event_object_t *obj, event_group_t flag);
+
+/*!
+ * @brief Destroy a previously created event object.
+ *
+ * @param obj The event object to destroy.
+ *
+ * @retval kSuccess The object was successfully destroyed.
+ * @retval kError Event destruction failed.
+ */
+fsl_rtos_status event_destroy(event_object_t *obj);
+/* @} */
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief Create a task.
+ *
+ * This function is wrapped by the macro task_create. Generally, this function is for
+ * internal use only, applications must use FSL_RTOS_TASK_DEFINE to define resources for
+ * task statically then use task_create to create task. If applications have prepare
+ * the resouces for task dynamically, they can use this function to create the task.
+ *
+ * @param task The task function.
+ * @param name The name of this task.
+ * @param stackSize The stack size in byte.
+ * @param stackMem Pointer to the stack. For bare metal, MQX and FreeRTOS, this could be NULL.
+ * @param priority Initial priority of the task.
+ * @param param Pointer to be passed to the task when it is created.
+ * @param usesFloat This task will use float register or not.
+ * @param handler Pointer to the task handler.
+ *
+ * @retval kSuccess The task was successfully created.
+ * @retval kError The task could not be created.
+ *
+ * @note Different tasks can not use the same task function.
+ */
+fsl_rtos_status __task_create(task_t task, uint8_t *name, uint16_t stackSize,
+ task_stack_t *stackMem, uint16_t priority,
+ void *param, bool usesFloat, task_handler_t *handler);
+
+/*!
+ * @brief Destroy a previously created task.
+ * @note Depending on the RTOS, task resources may or may not be automatically freed,
+ * and this function may not return if the current task is destroyed.
+ *
+ * @param handler The handler of the task to destroy. Returned by the task_create function.
+ *
+ * @retval kSuccess The task was successfully destroyed.
+ * @retval kError Task destruction failed or invalid parameter.
+ */
+fsl_rtos_status task_destroy(task_handler_t handler);
+/* @} */
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief Initialize the message queue.
+ *
+ * This function will initialize the message queue that declared previously.
+ * Here is an example demonstrating how to use:
+ @code
+ msg_queue_handler_t handler;
+ MSG_QUEUE_DECLARE(my_message, msg_num, msg_size);
+ handler = msg_queue_create(&my_message, msg_num, msg_size);
+ @endcode
+ *
+ * @param queue The queue declared through the MSG_QUEUE_DECLARE macro.
+ * @param number The number of elements in the queue.
+ * @param size Size of every elements in words.
+ *
+ * @retval Handler to access the queue for put and get operations. If message queue
+ * created failed, return 0.
+ */
+msg_queue_handler_t msg_queue_create(msg_queue_t *queue, uint16_t number, uint16_t size);
+
+/*!
+ * @brief Introduce an element at the tail of the queue.
+ *
+ * @param handler Queue handler returned by the msg_queue_create function.
+ * @param item Pointer to the element to be introduced in the queue.
+ *
+ * @retval kSuccess Element successfully introduced in the queue.
+ * @retval kError The queue was full or an invalid parameter was passed.
+ */
+fsl_rtos_status msg_queue_put(msg_queue_handler_t handler, msg_queue_item_t item);
+
+/*!
+ * @brief Read and remove an element at the head of the queue.
+ *
+ * @param handler Queue handler returned by the msg_queue_create function.
+ * @param item Pointer to store a pointer to the element of the queue.
+ * @param timeout In case the queue is empty, the number of milliseconds to
+ * wait for an element to be introduced into the queue. Use 0 to return
+ * immediately or #kSyncWaitForever to wait indefinitely.
+ *
+ * @retval kSuccess Element successfully obtained from the queue.
+ * @retval kTimeout If a timeout was specified, the queue remained empty after timeout.
+ * @retval kError The queue was empty or the handler was invalid.
+ * @retval kIdle The queue was empty and the timeout has not expired.
+ *
+ * @note There should be only one process waiting on the queue.
+ */
+fsl_rtos_status msg_queue_get(msg_queue_handler_t handler,
+ msg_queue_item_t *item,
+ uint32_t timeout);
+
+/*!
+ * @brief Discards all elements in the queue and leaves the queue empty.
+ *
+ * @param handler Queue handler returned by the msg_queue_create function.
+ *
+ * @retval kSuccess Queue successfully emptied.
+ * @retval kError Emptying queue failed.
+ */
+fsl_rtos_status msg_queue_flush(msg_queue_handler_t handler);
+
+/*!
+ * @brief Destroy a previously created queue.
+ *
+ * @param handler Queue handler returned by the msg_queue_create function.
+ *
+ * @retval kSuccess The queue was successfully destroyed.
+ * @retval kError Message queue destruction failed.
+ */
+fsl_rtos_status msg_queue_destroy(msg_queue_handler_t handler);
+
+/* @} */
+
+#ifndef FSL_RTOS_MBED
+/*!
+ * @name Memory Management
+ * @{
+ */
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * @param size Amount of bytes to reserve.
+ *
+ * @retval Pointer to the reserved memory. NULL if memory could not be allocated.
+ */
+void * mem_allocate(size_t size);
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param size Amount of bytes to reserve.
+ *
+ * @retval Pointer to the reserved memory. NULL if memory could not be allocated.
+ */
+void * mem_allocate_zero(size_t size);
+
+/*!
+ * @brief Releases the memory previously reserved.
+ *
+ * @param ptr Pointer to the start of the memory block previously reserved.
+ *
+ * @retval kSuccess Memory correctly released.
+ */
+fsl_rtos_status mem_free(void *ptr);
+#endif
+
+/* @} */
+
+/*!
+ * @name Time management
+ * @{
+ */
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param delay The time in milliseconds to wait.
+ */
+void time_delay(uint32_t delay);
+
+/* @} */
+
+/*!
+ * @name Interrupt management
+ * @{
+ */
+
+/*!
+ * @brief Install interrupt handler.
+ *
+ * @param irqNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ *
+ * @retval kSuccess Handler is installed successfully.
+ * @retval kSuccess Handler could not be installed.
+ */
+fsl_rtos_status interrupt_handler_register(int32_t irqNumber, void (*handler)(void));
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_OS_ABSTRACTION_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction_mbed.h Wed Mar 23 21:26:50 2016 +0000 @@ -0,0 +1,38 @@ +/* fsl_os_mbed_abstraction.h */ +/* Copyright (C) 2012 mbed.org, MIT License + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef FSL_OS_ABSTRACTION_MBED_H_ +#define FSL_OS_ABSTRACTION_MBED_H_ + +// This is not really an "abstraction", but rather a set of quick&dirty +// defines to allow the KSDK to compile. Currently, this is relevant only +// in the context of the ENET driver (fsl_enet_driver.c) + +typedef int event_object_t; +typedef int lock_object_t; +typedef void sync_object_t; +typedef unsigned int event_group_t; +typedef int task_t; +typedef void task_stack_t; +typedef int task_handler_t; +typedef int msg_queue_handler_t; +typedef void msg_queue_t; +typedef int msg_queue_item_t; + +#endif // #ifdef FSL_OS_ABSTRACTION_MBED_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/utilities/src/fsl_misc_utilities.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "fsl_misc_utilities.h"
+
+#if (defined(KEIL))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : __aeabi_assert
+ * Description : called by assert in KEIL
+ * This function is called by the assert function in KEIL.
+ *
+ *END**************************************************************************/
+void __aeabi_assert(const char *expr, const char *file, int line)
+{
+ printf("assert failed:%s, file %s:%d\r\n",expr,file,line);
+}
+
+#elif (defined(KDS))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : _isatty
+ * Description : used to enable the overwrite of the _write
+ * This function is used to enable the overwrite of the _write.
+ *
+ *END**************************************************************************/
+int _isatty (int fd)
+{
+ return 1;
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/utilities/src/fsl_os_abstraction_mbed.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,35 @@
+/* fsl_os_mbed_abstraction.h */
+/* Copyright (C) 2012 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fsl_os_abstraction.h"
+#include "wait_api.h"
+
+fsl_rtos_status lock_destroy(lock_object_t *obj) {
+ return kSuccess;
+}
+
+
+fsl_rtos_status event_set(event_object_t *obj, event_group_t flags) {
+ return kSuccess;
+}
+
+void time_delay(uint32_t delay) {
+ wait_ms(delay);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KPSDK_CODE/utilities/sw_timer.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__SW_TIMER_H__)
+#define __SW_TIMER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/*! @addtogroup sw_timer Software Timer
+ * @brief This module is used to interface with Abstract Timer HAL to generate periodical timeouts
+ * required through different modules of the AOA protocol. This block will be based on 1ms
+ * ticks for all the timeout calculations. The HAL Interface block used to communicate with
+ * this must have the same 1ms timeout configured. This module can generate different
+ * software timer channels based on the same 1ms.
+ */
+/*! @{*/
+
+/*! Definition of the possible status of a software channel timer. */
+typedef enum SwTimerChannelStatus
+{
+ kSwTimerChannelExpired = 0x00, /*!< Indicates the timer channel has counted the given ms*/
+ kSwTimerChannelStillCounting = 0x01, /*!< Indicates the timeout of the channel has not expired
+ and the timer is still counting.*/
+ kSwTimerChannelIsDisable = 0x02, /*!< Indicates the timer channel is not reserved. */
+ kSwTimerChannelNotAvailable = 0xFF /*!< Indicates there are not available channels to reserve
+ or the requested channel is not available.*/
+}sw_timer_channel_status_t;
+
+/*! List of status and errors. */
+enum _sw_timer_errors
+{
+ kSwTimerStatusSuccess, /*!< The execution was successful.*/
+ kSwTimerStatusFail, /*!< The execution failed.*/
+ kSwTimerStatusInvalidChannel /*!< The given channel is not valid. Valid channels are 0 to
+ (SW_TIMER_NUMBER_CHANNELS - 1). */
+};
+
+/*!
+ * Data type of the counter of each timer channel. If it is an int8_t the counter will count
+ * up to 127ms, int16_t up to 32767ms and int32_t up to 2147483647ms.
+ */
+typedef int32_t time_counter_t;
+
+/*! Max timeout value according to size of the time counter */
+enum sw_timer_timeouts
+{
+ kSwTimerMaxTimeout = 2147483647
+};
+
+/*!
+ * Data type of the free running counter. This data type should be unsigned and will count up to
+ * 255ms if it is uint8_t, 65535ms for uint16_t and 4294967295ms for uint32_t.
+ */
+typedef uint32_t time_free_counter_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Initializes the software timer module. Prepares variables and HAL layer to provide timer
+ * services. Starts the free running counter which will be available to get its value any
+ * time while the service is running; it is useful whenever a module wants to keep track of
+ * time, but do not wants to reserve a channel.
+ *
+ * @return status_t Returns software timer status after initialization.
+ * @retval kSwTimerStatusSuccess The initialization was successful and the software timer is ready
+ * to provide services.
+ * @retval kSwTimerStatusFail The initialization failed.
+ */
+uint32_t sw_timer_init_service(void);
+
+/*!
+ * @brief Deinitializes the software timer module. Shutdown HAL layer, so no timer service can be
+ * provided after the execution of this function.
+ *
+ * @return void
+ */
+void sw_timer_shutdown_service(void);
+
+/*!
+ * @brief Reserves a free timer channel to be used by any module and returns its identifier.
+ *
+ * @return uint8_t Returns the number of the channel that was reserved.
+ * @retval Any value between 0 and SW_TIMER_NUMBER_CHANNELS is a valid channel. It indicates the
+ * channel was reserved and can be used.
+ * @retval kSwTimerChannelNotAvailable If there is not any available channel, because all
+ * channels are already reserved.
+ */
+uint8_t sw_timer_reserve_channel(void);
+
+/*!
+ * @brief Returns the actual status of the given timer channel. The timer has to be previously
+ * started to return a valid status.
+ *
+ * @param timerChannel [in] Indicates the timer channel which status is going to be returned.
+ *
+ * @return sw_timer_channel_status_t Current status of the given timer channel.
+ * @retval kSwTimerChannelExpired Indicates the timer channel has counted the given ms.
+ * @retval kSwTimerChannelStillCounting Indicates the timeout of the channel has not expired and
+ the timer is still counting.
+ * @retval kSwTimerChannelIsDisable Indicates the timer channel is not reserved.
+ * @retval kSwTimerChannelNotAvailable Indicates the timer channel is invalid.
+ */
+sw_timer_channel_status_t sw_timer_get_channel_status(uint8_t timerChannel);
+
+/*!
+ * @brief Starts the count down of the given timer channel. The timer channel has to be previously
+ * reserved.
+ *
+ * @param timerChannel [in] Indicates the timer channel that is going to be started.
+ * @param timeout [in] Time in ms that the timer channel will count. The timeout should be
+ a multiple of count unit of the timer, otherwise it will be taken
+ the integer part of the division and the exact count will not be
+ achieved
+ *
+ * @return status_t Reports failures in the execution of the function.
+ * @retval kSwTimerStatusSuccess A channel was started successfully.
+ * @retval kSwTimerStatusInvalidChannel The timer channel is invalid, it does not exist.
+ */
+uint32_t sw_timer_start_channel(uint8_t timerChannel, time_counter_t timeout);
+
+/*!
+ * @brief Releases the given timer channel, so it can be used by someone else.
+ *
+ * @param timerChannel [in] Identifier of the timer channel.
+ *
+ * @return status_t Reports failures in the execution of the function.
+ * @retval kSwTimerStatusSuccess A channel was released successfully.
+ * @retval kSwTimerStatusInvalidChannel The timer channel is invalid, it does not exist.
+ */
+uint32_t sw_timer_release_channel(uint8_t timerChannel);
+
+/*!
+ * @brief Gets the current value of the free running counter. Any module can keep track of the time
+ * by reading this counter and calculates time difference. No reservation of timer channel
+ * is needed. Consider for calculations that when the counter overflows it will start from
+ * 0 again.
+ *
+ * @return time_free_counter_t Returns current count of the free running counter.
+ */
+time_free_counter_t sw_timer_get_free_counter(void);
+
+/*!
+ * @brief This function is called every 1ms by the interruption and update count down values of all
+ * timer channels.
+ *
+ * @return void
+ */
+void sw_timer_update_counters(void);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+/*Group sw_timer*/
+
+#endif /* __SW_TIMER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/analogin_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralNames.h"
+#include "fsl_adc_hal.h"
+#include "fsl_clock_manager.h"
+#include "PeripheralPins.h"
+#include "fsl_device_registers.h"
+
+#define MAX_FADC 6000000
+
+void analogin_init(analogin_t *obj, PinName pin) {
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+ uint32_t adc_addrs[] = ADC_BASE_ADDRS;
+
+ CLOCK_SYS_EnableAdcClock(instance);
+
+ uint32_t bus_clock;
+ CLOCK_SYS_GetFreq(kBusClock, &bus_clock);
+ uint32_t clkdiv;
+ for (clkdiv = 0; clkdiv < 4; clkdiv++) {
+ if ((bus_clock >> clkdiv) <= MAX_FADC)
+ break;
+ }
+ if (clkdiv == 4) {
+ clkdiv = 0x3; //Set max div
+ }
+ /* adc is enabled/triggered when reading. */
+ ADC_HAL_Init(adc_addrs[instance]);
+ ADC_HAL_SetClkSrcMode(adc_addrs[instance], kAdcClkSrcOfBusClk);
+ ADC_HAL_SetClkDividerMode(adc_addrs[instance], (adc_clk_divider_mode_t)(clkdiv & 0x3));
+ ADC_HAL_SetRefVoltSrcMode(adc_addrs[instance], kAdcRefVoltSrcOfVref);
+ ADC_HAL_SetResolutionMode(adc_addrs[instance], kAdcResolutionBitOfSingleEndAs16);
+ ADC_HAL_SetContinuousConvCmd(adc_addrs[instance], false);
+ ADC_HAL_SetHwTriggerCmd(adc_addrs[instance], false); /* sw trigger */
+ ADC_HAL_SetHwAverageCmd(adc_addrs[instance], true);
+ ADC_HAL_SetHwAverageMode(adc_addrs[instance], kAdcHwAverageCountOf4);
+ ADC_HAL_SetChnMuxMode(adc_addrs[instance],
+ obj->adc & (1 << ADC_B_CHANNEL_SHIFT) ? kAdcChnMuxOfB : kAdcChnMuxOfA);
+
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+ uint32_t adc_addrs[] = ADC_BASE_ADDRS;
+ /* sw trigger (SC1A) */
+ ADC_HAL_ConfigChn(adc_addrs[instance], 0, false, false, obj->adc & 0xF);
+ while (!ADC_HAL_GetChnConvCompletedCmd(adc_addrs[instance], 0));
+ return ADC_HAL_GetChnConvValueRAW(adc_addrs[instance], 0);
+}
+
+float analogin_read(analogin_t *obj) {
+ uint16_t value = analogin_read_u16(obj);
+ return (float)value * (1.0f / (float)0xFFFF);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/analogout_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "fsl_clock_manager.h"
+
+#define RANGE_12BIT 0xFFF
+
+void analogout_init(dac_t *obj, PinName pin) {
+ obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+ if (obj->dac == (DACName)NC) {
+ error("DAC pin mapping failed");
+ }
+
+ SIM_HAL_EnableDacClock(SIM_BASE, 0);
+
+ DAC0->DAT[obj->dac].DATH = 0;
+ DAC0->DAT[obj->dac].DATL = 0;
+
+ DAC0->C1 = DAC_C1_DACBFMD(2); // One-Time Scan Mode
+
+ DAC0->C0 = DAC_C0_DACEN_MASK // Enable
+ | DAC_C0_DACSWTRG_MASK // Software Trigger
+ | DAC_C0_DACRFS_MASK; // VDDA selected
+
+ analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {}
+
+static inline void dac_write(dac_t *obj, int value) {
+ DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF);
+ DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF);
+}
+
+static inline int dac_read(dac_t *obj) {
+ return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
+}
+
+void analogout_write(dac_t *obj, float value) {
+ if (value < 0.0f) {
+ dac_write(obj, 0);
+ } else if (value > 1.0f) {
+ dac_write(obj, RANGE_12BIT);
+ } else {
+ dac_write(obj, value * (float)RANGE_12BIT);
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+ dac_write(obj, value >> 4); // 12-bit
+}
+
+float analogout_read(dac_t *obj) {
+ uint32_t value = dac_read(obj);
+ return (float)value * (1.0f / (float)RANGE_12BIT);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+ uint32_t value = dac_read(obj); // 12-bit
+ return (value << 4) | ((value >> 8) & 0x003F);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "fsl_port_hal.h"
+#include "fsl_gpio_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+uint32_t gpio_set(PinName pin) {
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t pin_num = pin & 0xFF;
+
+ pin_function(pin, (int)kPortMuxAsGpio);
+ return 1 << pin_num;
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+ obj->pin = pin;
+ if (pin == (PinName)NC)
+ return;
+
+ uint32_t port = pin >> GPIO_PORT_SHIFT;
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ uint32_t pin_num = pin & 0xFF;
+ CLOCK_SYS_EnablePortClock(port);
+ PORT_HAL_SetMuxMode(port_addrs[port], pin_num, kPortMuxAsGpio);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+ uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
+ uint32_t pin_num = obj->pin & 0xFF;
+
+ switch (direction) {
+ case PIN_INPUT:
+ GPIO_HAL_SetPinDir(gpio_addrs[port], pin_num, kGpioDigitalInput);
+ break;
+ case PIN_OUTPUT:
+ GPIO_HAL_SetPinDir(gpio_addrs[port], pin_num, kGpioDigitalOutput);
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio_irq_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,215 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+
+#include "gpio_irq_api.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "fsl_gpio_hal.h"
+#include "fsl_port_hal.h"
+#include "mbed_error.h"
+
+#define CHANNEL_NUM 160
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+#define IRQ_DISABLED (0)
+#define IRQ_RAISING_EDGE (9)
+#define IRQ_FALLING_EDGE (10)
+#define IRQ_EITHER_EDGE (11)
+
+static void handle_interrupt_in(PortName port, int ch_base) {
+ uint32_t i;
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+
+ for (i = 0; i < 32; i++) {
+ if (PORT_HAL_IsPinIntPending(port_addrs[port], i)) {
+ uint32_t id = channel_ids[ch_base + i];
+ if (id == 0) {
+ continue;
+ }
+
+ gpio_irq_event event = IRQ_NONE;
+ uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
+ switch (BR_PORT_PCRn_IRQC(port_addrs[port], i)) {
+ case IRQ_RAISING_EDGE:
+ event = IRQ_RISE;
+ break;
+
+ case IRQ_FALLING_EDGE:
+ event = IRQ_FALL;
+ break;
+
+ case IRQ_EITHER_EDGE:
+ event = (GPIO_HAL_ReadPinInput(gpio_addrs[port], i)) ? (IRQ_RISE) : (IRQ_FALL);
+ break;
+ }
+ if (event != IRQ_NONE) {
+ irq_handler(id, event);
+ }
+ }
+ }
+ PORT_HAL_ClearPortIntFlag(port_addrs[port]);
+}
+
+void gpio_irqA(void) {handle_interrupt_in(PortA, 0);}
+void gpio_irqB(void) {handle_interrupt_in(PortB, 32);}
+void gpio_irqC(void) {handle_interrupt_in(PortC, 64);}
+void gpio_irqD(void) {handle_interrupt_in(PortD, 96);}
+void gpio_irqE(void) {handle_interrupt_in(PortE, 128);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ if (pin == NC) {
+ return -1;
+ }
+
+ irq_handler = handler;
+ obj->port = pin >> GPIO_PORT_SHIFT;
+ obj->pin = pin & 0x7F;
+
+ uint32_t ch_base = 0;
+ uint32_t vector = (uint32_t)gpio_irqA;
+ IRQn_Type irq_n = PORTA_IRQn;
+ switch (obj->port) {
+ case PortA:
+ ch_base = 0;
+ irq_n = PORTA_IRQn;
+ vector = (uint32_t)gpio_irqA;
+ break;
+ case PortB:
+ ch_base = 32;
+ irq_n = PORTB_IRQn;
+ vector = (uint32_t)gpio_irqB;
+ break;
+ case PortC:
+ ch_base = 64;
+ irq_n = PORTC_IRQn;
+ vector = (uint32_t)gpio_irqC;
+ break;
+ case PortD:
+ ch_base = 96;
+ irq_n = PORTD_IRQn;
+ vector = (uint32_t)gpio_irqD;
+ break;
+ case PortE:
+ ch_base = 128;
+ irq_n = PORTE_IRQn;
+ vector = (uint32_t)gpio_irqE;
+ break;
+
+ default:
+ error("gpio_irq only supported on port A-E.");
+ break;
+ }
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ obj->ch = ch_base + obj->pin;
+ channel_ids[obj->ch] = id;
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ port_interrupt_config_t irq_settings = kPortIntDisabled;
+
+ switch (BR_PORT_PCRn_IRQC(port_addrs[obj->port], obj->pin)) {
+ case IRQ_DISABLED:
+ if (enable)
+ irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntFallingEdge);
+ break;
+
+ case IRQ_RAISING_EDGE:
+ if (enable) {
+ irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntEitherEdge);
+ } else {
+ if (event == IRQ_FALL)
+ irq_settings = kPortIntRisingEdge;
+ }
+ break;
+
+ case IRQ_FALLING_EDGE:
+ if (enable) {
+ irq_settings = (event == IRQ_FALL) ? (kPortIntFallingEdge) : (kPortIntEitherEdge);
+ } else {
+ if (event == IRQ_RISE)
+ irq_settings = kPortIntFallingEdge;
+ }
+ break;
+
+ case IRQ_EITHER_EDGE:
+ if (enable) {
+ irq_settings = kPortIntEitherEdge;
+ } else {
+ irq_settings = (event == IRQ_RISE) ? (kPortIntFallingEdge) : (kPortIntRisingEdge);
+ }
+ break;
+ }
+
+ PORT_HAL_SetPinIntMode(port_addrs[obj->port], obj->pin, irq_settings);
+ PORT_HAL_ClearPinIntFlag(port_addrs[obj->port], obj->pin);
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+ switch (obj->port) {
+ case PortA:
+ NVIC_EnableIRQ(PORTA_IRQn);
+ break;
+ case PortB:
+ NVIC_EnableIRQ(PORTB_IRQn);
+ break;
+ case PortC:
+ NVIC_EnableIRQ(PORTC_IRQn);
+ break;
+ case PortD:
+ NVIC_EnableIRQ(PORTD_IRQn);
+ break;
+ case PortE:
+ NVIC_EnableIRQ(PORTE_IRQn);
+ break;
+ }
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+ switch (obj->port) {
+ case PortA:
+ NVIC_DisableIRQ(PORTA_IRQn);
+ break;
+ case PortB:
+ NVIC_DisableIRQ(PORTB_IRQn);
+ break;
+ case PortC:
+ NVIC_DisableIRQ(PORTC_IRQn);
+ break;
+ case PortD:
+ NVIC_DisableIRQ(PORTD_IRQn);
+ break;
+ case PortE:
+ NVIC_DisableIRQ(PORTE_IRQn);
+ break;
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio_object.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "fsl_gpio_hal.h"
+// #include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+ uint32_t pin = obj->pin & 0xFF;
+ uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
+
+ GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+ uint32_t pin = obj->pin & 0xFF;
+ uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
+
+ return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+ return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/i2c_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,328 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_clock_manager.h"
+#include "fsl_i2c_hal.h"
+#include "fsl_port_hal.h"
+#include "fsl_sim_hal.h"
+#include "PeripheralPins.h"
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+ uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->instance = pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)obj->instance != NC);
+
+ CLOCK_SYS_EnableI2cClock(obj->instance);
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_Init(i2c_addrs[obj->instance]);
+ I2C_HAL_Enable(i2c_addrs[obj->instance]);
+ I2C_HAL_SetIntCmd(i2c_addrs[obj->instance], true);
+ i2c_frequency(obj, 100000);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ PORT_HAL_SetOpenDrainCmd(port_addrs[sda >> GPIO_PORT_SHIFT], sda & 0xFF, true);
+ PORT_HAL_SetOpenDrainCmd(port_addrs[scl >> GPIO_PORT_SHIFT], scl & 0xFF, true);
+}
+
+int i2c_start(i2c_t *obj) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_SendStart(i2c_addrs[obj->instance]);
+ return 0;
+}
+
+int i2c_stop(i2c_t *obj) {
+ volatile uint32_t n = 0;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ if (I2C_HAL_IsMaster(i2c_addrs[obj->instance]))
+ I2C_HAL_SendStop(i2c_addrs[obj->instance]);
+
+ // It seems that there are timing problems
+ // when there is no waiting time after a STOP.
+ // This wait is also included on the samples
+ // code provided with the freedom board
+ for (n = 0; n < 200; n++) __NOP();
+ return 0;
+}
+
+static int timeout_status_poll(i2c_t *obj, i2c_status_flag_t flag) {
+ uint32_t i, timeout = 100000;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+
+ for (i = 0; i < timeout; i++) {
+ if (I2C_HAL_GetStatusFlag(i2c_addrs[obj->instance], flag))
+ return 0;
+ }
+ return 1;
+}
+
+// this function waits the end of a tx transfer and return the status of the transaction:
+// 0: OK ack received
+// 1: OK ack not received
+// 2: failure
+static int i2c_wait_end_tx_transfer(i2c_t *obj) {
+ // wait for the interrupt flag
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+
+ if (timeout_status_poll(obj, kI2CInterruptPending)) {
+ return 2;
+ }
+ I2C_HAL_ClearInt(i2c_addrs[obj->instance]);
+
+ // wait transfer complete
+ if (timeout_status_poll(obj, kI2CTransferComplete)) {
+ return 2;
+ }
+
+ // check if we received the ACK or not
+ return I2C_HAL_GetStatusFlag(i2c_addrs[obj->instance], kI2CReceivedNak) ? 1 : 0;
+}
+
+// this function waits the end of a rx transfer and return the status of the transaction:
+// 0: OK
+// 1: failure
+static int i2c_wait_end_rx_transfer(i2c_t *obj) {
+ // wait for the end of the rx transfer
+ if (timeout_status_poll(obj, kI2CInterruptPending)) {
+ return 1;
+ }
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_ClearInt(i2c_addrs[obj->instance]);
+
+ return 0;
+}
+
+static int i2c_do_write(i2c_t *obj, int value) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_WriteByte(i2c_addrs[obj->instance], value);
+
+ // init and wait the end of the transfer
+ return i2c_wait_end_tx_transfer(obj);
+}
+
+static int i2c_do_read(i2c_t *obj, char * data, int last) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ if (last) {
+ I2C_HAL_SendNak(i2c_addrs[obj->instance]);
+ } else {
+ I2C_HAL_SendAck(i2c_addrs[obj->instance]);
+ }
+
+ *data = (I2C_HAL_ReadByte(i2c_addrs[obj->instance]) & 0xFF);
+
+ // start rx transfer and wait the end of the transfer
+ return i2c_wait_end_rx_transfer(obj);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ uint32_t busClock;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ clock_manager_error_code_t error = CLOCK_SYS_GetFreq(kBusClock, &busClock);
+ if (error == kClockManagerSuccess) {
+ I2C_HAL_SetBaudRate(i2c_addrs[obj->instance], busClock, hz / 1000, NULL);
+ }
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count;
+ char dummy_read, *ptr;
+
+ if (i2c_start(obj)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ if (i2c_do_write(obj, (address | 0x01))) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // set rx mode
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive);
+
+ // Read in bytes
+ for (count = 0; count < (length); count++) {
+ ptr = (count == 0) ? &dummy_read : &data[count - 1];
+ uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
+ if (i2c_do_read(obj, ptr, stop_)) {
+ i2c_stop(obj);
+ return count;
+ }
+ }
+
+ // If not repeated start, send stop.
+ if (stop)
+ i2c_stop(obj);
+
+ // last read
+ data[count-1] = I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i;
+
+ if (i2c_start(obj)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ if (i2c_do_write(obj, (address & 0xFE))) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i = 0; i < length; i++) {
+ if(i2c_do_write(obj, data[i])) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ if (stop)
+ i2c_stop(obj);
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ char data;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ // set rx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive);
+
+ // Setup read
+ i2c_do_read(obj, &data, last);
+
+ // set tx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend);
+ return I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ // set tx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend);
+
+ return !i2c_do_write(obj, (data & 0xFF));
+}
+
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ if (enable_slave) {
+ // set slave mode
+ BW_I2C_C1_MST(i2c_addrs[obj->instance], 0);
+ I2C_HAL_SetIntCmd(i2c_addrs[obj->instance], true);
+ } else {
+ // set master mode
+ BW_I2C_C1_MST(i2c_addrs[obj->instance], 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ switch(HW_I2C_S_RD(i2c_addrs[obj->instance])) {
+ // read addressed
+ case 0xE6:
+ return 1;
+ // write addressed
+ case 0xE2:
+ return 3;
+ default:
+ return 0;
+ }
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ uint8_t dummy_read;
+ uint8_t *ptr;
+ int count;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ // set rx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend);
+
+ // first dummy read
+ dummy_read = I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+ if (i2c_wait_end_rx_transfer(obj))
+ return 0;
+
+ // read address
+ dummy_read = I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+ if (i2c_wait_end_rx_transfer(obj))
+ return 0;
+
+ // read (length - 1) bytes
+ for (count = 0; count < (length - 1); count++) {
+ data[count] = I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+ if (i2c_wait_end_rx_transfer(obj))
+ return count;
+ }
+
+ // read last byte
+ ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
+ *ptr = I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+
+ return (length) ? (count + 1) : 0;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int i, count = 0;
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+
+ // set tx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend);
+
+ for (i = 0; i < length; i++) {
+ if (i2c_do_write(obj, data[count++]) == 2)
+ return i;
+ }
+
+ // set rx mode
+ I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive);
+
+ // dummy rx transfer needed
+ // otherwise the master cannot generate a stop bit
+ I2C_HAL_ReadByte(i2c_addrs[obj->instance]);
+ if (i2c_wait_end_rx_transfer(obj) == 2)
+ return count;
+
+ return count;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t i2c_addrs[] = I2C_BASE_ADDRS;
+ I2C_HAL_SetUpperAddress7bit(i2c_addrs[obj->instance], address & 0xfe);
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/objects.h Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm_name;
+};
+
+struct serial_s {
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct i2c_s {
+ uint32_t instance;
+};
+
+struct spi_s {
+ uint32_t instance;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/pinmap.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "fsl_clock_manager.h"
+#include "fsl_port_hal.h"
+
+void pin_function(PinName pin, int function) {
+ MBED_ASSERT(pin != (PinName)NC);
+ CLOCK_SYS_EnablePortClock(pin >> GPIO_PORT_SHIFT);
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ PORT_HAL_SetMuxMode(port_addrs[pin >> GPIO_PORT_SHIFT], pin & 0xFF, (port_mux_t)function);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t instance = pin >> GPIO_PORT_SHIFT;
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ uint32_t pinName = pin & 0xFF;
+
+ switch (mode) {
+ case PullNone:
+ PORT_HAL_SetPullCmd(port_addrs[instance], pinName, false);
+ PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullDown);
+ break;
+ case PullDown:
+ PORT_HAL_SetPullCmd(port_addrs[instance], pinName, true);
+ PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullDown);
+ break;
+ case PullUp:
+ PORT_HAL_SetPullCmd(port_addrs[instance], pinName, true);
+ PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullUp);
+ break;
+ default:
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/port_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+ return (PinName)((port << GPIO_PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+ obj->port = port;
+ obj->mask = mask;
+
+ // The function is set per pin: reuse gpio logic
+ for (uint32_t i = 0; i < 32; i++) {
+ if (obj->mask & (1 << i)) {
+ gpio_set(port_pin(obj->port, i));
+ }
+ }
+
+ port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+
+ // The mode is set per pin: reuse pinmap logic
+ for (uint32_t i = 0; i < 32; i++) {
+ if (obj->mask & (1 << i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ uint32_t direction = GPIO_HAL_GetPortDir(port_addrs[obj->port]);
+ switch (dir) {
+ case PIN_INPUT :
+ direction &= ~obj->mask;
+ GPIO_HAL_SetPortDir(port_addrs[obj->port], direction);
+ break;
+ case PIN_OUTPUT:
+ direction |= obj->mask;
+ GPIO_HAL_SetPortDir(port_addrs[obj->port], direction);
+ break;
+ }
+}
+
+void port_write(port_t *obj, int value) {
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ uint32_t input = GPIO_HAL_ReadPortInput(port_addrs[obj->port]) & ~obj->mask;
+ GPIO_HAL_WritePortOutput(port_addrs[obj->port], input | (uint32_t)(value & obj->mask));
+}
+
+int port_read(port_t *obj) {
+ uint32_t port_addrs[] = PORT_BASE_ADDRS;
+ return (int)(GPIO_HAL_ReadPortInput(port_addrs[obj->port]) & obj->mask);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/pwmout_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_ftm_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+#include "PeripheralPins.h"
+
+static float pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT(pwm != (PWMName)NC);
+
+ obj->pwm_name = pwm;
+
+ uint32_t pwm_base_clock;
+ CLOCK_SYS_GetFreq(kBusClock, &pwm_base_clock);
+ float clkval = (float)pwm_base_clock / 1000000.0f;
+ uint32_t clkdiv = 0;
+ while (clkval > 1) {
+ clkdiv++;
+ clkval /= 2.0f;
+ if (clkdiv == 7) {
+ break;
+ }
+ }
+
+ pwm_clock_mhz = clkval;
+ uint32_t channel = pwm & 0xF;
+ uint32_t instance = pwm >> TPM_SHIFT;
+ uint32_t ftm_addrs[] = FTM_BASE_ADDRS;
+ CLOCK_SYS_EnableFtmClock(instance);
+
+ FTM_HAL_SetTofFreq(ftm_addrs[instance], 3);
+ FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk);
+ FTM_HAL_SetClockPs(ftm_addrs[instance], (ftm_clock_ps_t)clkdiv);
+ FTM_HAL_SetCounter(ftm_addrs[instance], 0);
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_ms(obj, 20);
+ pwmout_write (obj, 0);
+ ftm_pwm_param_t config = {
+ .mode = kFtmEdgeAlignedPWM,
+ .edgeMode = kFtmHighTrue
+ };
+ FTM_HAL_EnablePwmMode(ftm_addrs[instance], &config, channel);
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ uint32_t instance = obj->pwm_name >> TPM_SHIFT;
+ if (value < 0.0f) {
+ value = 0.0f;
+ } else if (value > 1.0f) {
+ value = 1.0f;
+ }
+ uint32_t ftm_addrs[] = FTM_BASE_ADDRS;
+ uint16_t mod = FTM_HAL_GetMod(ftm_addrs[instance]);
+ uint32_t new_count = (uint32_t)((float)(mod) * value);
+ // Stop FTM clock to ensure instant update of MOD register
+ FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_None);
+ FTM_HAL_SetChnCountVal(ftm_addrs[instance], obj->pwm_name & 0xF, new_count);
+ FTM_HAL_SetCounter(ftm_addrs[instance], 0);
+ FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk);
+}
+
+float pwmout_read(pwmout_t* obj) {
+ uint32_t ftm_addrs[] = FTM_BASE_ADDRS;
+ uint16_t count = FTM_HAL_GetChnCountVal(ftm_addrs[obj->pwm_name >> TPM_SHIFT], obj->pwm_name & 0xF, 0);
+ uint16_t mod = FTM_HAL_GetMod(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
+ if (mod == 0)
+ return 0.0;
+ float v = (float)(count) / (float)(mod);
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ uint32_t instance = obj->pwm_name >> TPM_SHIFT;
+ uint32_t ftm_addrs[] = FTM_BASE_ADDRS;
+ float dc = pwmout_read(obj);
+ // Stop FTM clock to ensure instant update of MOD register
+ FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_None);
+ FTM_HAL_SetMod(ftm_addrs[instance], (uint32_t)(pwm_clock_mhz * (float)us) - 1);
+ pwmout_write(obj, dc);
+ FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ uint32_t ftm_addrs[] = FTM_BASE_ADDRS;
+ uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
+ FTM_HAL_SetChnCountVal(ftm_addrs[obj->pwm_name >> TPM_SHIFT], obj->pwm_name & 0xF, value);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/rtc_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "pinmap.h"
+#include "fsl_rtc_hal.h"
+#include "fsl_clock_manager.h"
+#include "PeripheralPins.h"
+
+void rtc_init(void) {
+ SIM_HAL_EnableRtcClock(SIM_BASE, 0U);
+
+ RTC_HAL_Init(RTC_BASE);
+ RTC_HAL_Enable(RTC_BASE);
+
+ RTC_HAL_EnableCounter(RTC_BASE, true);
+}
+
+void rtc_free(void) {
+ // [TODO]
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ * 0 = Disabled, 1 = Enabled
+ */
+int rtc_isenabled(void) {
+ SIM_HAL_EnableRtcClock(SIM_BASE, 0U);
+ return (int)RTC_HAL_IsCounterEnabled(RTC_BASE);
+}
+
+time_t rtc_read(void) {
+ return (time_t)RTC_HAL_GetSecsReg(RTC_BASE);
+}
+
+void rtc_write(time_t t) {
+ if (t == 0) {
+ t = 1;
+ }
+ RTC_HAL_EnableCounter(RTC_BASE, false);
+ RTC_HAL_SetSecsReg(RTC_BASE, t);
+ RTC_HAL_EnableCounter(RTC_BASE, true);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/serial_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,233 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_uart_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_uart_features.h"
+#include "PeripheralPins.h"
+
+/* TODO:
+ putchar/getchar 9 and 10 bits support
+*/
+#ifndef UART3_BASE
+#define UART_NUM 3
+#else
+#define UART_NUM 5
+#endif
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+ uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+ obj->index = pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT((int)obj->index != NC);
+
+ uint32_t uartSourceClock = CLOCK_SYS_GetUartFreq(obj->index);
+
+ CLOCK_SYS_EnableUartClock(obj->index);
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ UART_HAL_Init(uart_addrs[obj->index]);
+ UART_HAL_SetBaudRate(uart_addrs[obj->index], uartSourceClock, 9600);
+ UART_HAL_SetParityMode(uart_addrs[obj->index], kUartParityDisabled);
+ #if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ UART_HAL_SetStopBitCount(uart_addrs[obj->index], kUartOneStopBit);
+ #endif
+ UART_HAL_SetBitCountPerChar(uart_addrs[obj->index], kUart8BitsPerChar);
+ UART_HAL_DisableTransmitter(uart_addrs[obj->index]);
+ UART_HAL_DisableReceiver(uart_addrs[obj->index]);
+
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ if (tx != NC) {
+ UART_HAL_FlushTxFifo(uart_addrs[obj->index]);
+ UART_HAL_EnableTransmitter(uart_addrs[obj->index]);
+
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ UART_HAL_EnableReceiver(uart_addrs[obj->index]);
+ pin_mode(rx, PullUp);
+ }
+
+ if (obj->index == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ UART_HAL_SetBaudRate(uart_addrs[obj->index], CLOCK_SYS_GetUartFreq(obj->index), (uint32_t)baudrate);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ UART_HAL_SetBitCountPerChar(uart_addrs[obj->index], (uart_bit_count_per_char_t)data_bits);
+ UART_HAL_SetParityMode(uart_addrs[obj->index], (uart_parity_mode_t)parity);
+ #if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ UART_HAL_SetStopBitCount(uart_addrs[obj->index], (uart_stop_bit_count_t)--stop_bits);
+ #endif
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+ if (serial_irq_ids[index] != 0) {
+ if (transmit_empty)
+ irq_handler(serial_irq_ids[index], TxIrq);
+
+ if (receive_full)
+ irq_handler(serial_irq_ids[index], RxIrq);
+ }
+}
+
+void uart0_irq() {
+ uart_irq(UART_HAL_IsTxDataRegEmpty(UART0_BASE), UART_HAL_IsRxDataRegFull(UART0_BASE), 0);
+ if (UART_HAL_GetStatusFlag(UART0_BASE, kUartRxOverrun))
+ UART_HAL_ClearStatusFlag(UART0_BASE, kUartRxOverrun);
+}
+void uart1_irq() {
+ uart_irq(UART_HAL_IsTxDataRegEmpty(UART1_BASE), UART_HAL_IsRxDataRegFull(UART1_BASE), 1);
+}
+
+void uart2_irq() {
+ uart_irq(UART_HAL_IsTxDataRegEmpty(UART2_BASE), UART_HAL_IsRxDataRegFull(UART2_BASE), 2);
+}
+
+#if (UART_NUM > 3)
+
+void uart3_irq() {
+ uart_irq(UART_HAL_IsTxDataRegEmpty(UART3_BASE), UART_HAL_IsRxDataRegFull(UART3_BASE), 3);
+}
+
+void uart4_irq() {
+ uart_irq(UART_HAL_IsTxDataRegEmpty(UART4_BASE), UART_HAL_IsRxDataRegFull(UART4_BASE), 4);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ switch (obj->index) {
+ case 0: irq_n=UART0_RX_TX_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case 1: irq_n=UART1_RX_TX_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case 2: irq_n=UART2_RX_TX_IRQn; vector = (uint32_t)&uart2_irq; break;
+#if (UART_NUM > 3)
+ case 3: irq_n=UART3_RX_TX_IRQn; vector = (uint32_t)&uart3_irq; break;
+ case 4: irq_n=UART4_RX_TX_IRQn; vector = (uint32_t)&uart4_irq; break;
+#endif
+ }
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ if (enable) {
+ switch (irq) {
+ case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], true); break;
+ case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], true); break;
+ }
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ switch (irq) {
+ case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], false); break;
+ case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], false); break;
+ }
+ switch (other_irq) {
+ case RxIrq: all_disabled = UART_HAL_GetRxDataRegFullIntCmd(uart_addrs[obj->index]) == 0; break;
+ case TxIrq: all_disabled = UART_HAL_GetTxDataRegEmptyIntCmd(uart_addrs[obj->index]) == 0; break;
+ }
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ uint8_t data;
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ UART_HAL_Getchar(uart_addrs[obj->index], &data);
+
+ return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ uint32_t uart_addrs[] = UART_BASE_ADDRS;
+ UART_HAL_Putchar(uart_addrs[obj->index], (uint8_t)c);
+}
+
+int serial_readable(serial_t *obj) {
+ uint32_t uart_address[] = UART_BASE_ADDRS;
+ if (UART_HAL_GetStatusFlag(uart_address[obj->index], kUartRxOverrun))
+ UART_HAL_ClearStatusFlag(uart_address[obj->index], kUartRxOverrun);
+ return UART_HAL_IsRxDataRegFull(uart_address[obj->index]);
+}
+
+int serial_writable(serial_t *obj) {
+ uint32_t uart_address[] = UART_BASE_ADDRS;
+ if (UART_HAL_GetStatusFlag(uart_address[obj->index], kUartRxOverrun))
+ UART_HAL_ClearStatusFlag(uart_address[obj->index], kUartRxOverrun);
+
+ return UART_HAL_IsTxDataRegEmpty(uart_address[obj->index]);
+}
+
+void serial_clear(serial_t *obj) {
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ uint32_t uart_address[] = UART_BASE_ADDRS;
+ UART_HAL_SetBreakCharCmd(uart_address[obj->index], true);
+}
+
+void serial_break_clear(serial_t *obj) {
+ uint32_t uart_address[] = UART_BASE_ADDRS;
+ UART_HAL_SetBreakCharCmd(uart_address[obj->index], false);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sleep.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_smc_hal.h"
+
+void sleep(void) {
+ smc_power_mode_protection_config_t sleep_config = {true};
+ SMC_HAL_SetProtection(SMC_BASE, &sleep_config);
+
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+}
+
+void deepsleep(void) {
+ mcg_clock_select_t mcg_clock = CLOCK_HAL_GetClkSrcMode(MCG_BASE);
+
+ smc_power_mode_protection_config_t sleep_config = {true};
+ SMC_HAL_SetProtection(SMC_BASE, &sleep_config);
+ SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
+
+ //Deep sleep for ARM core:
+ SCB->SCR = 1 << SCB_SCR_SLEEPDEEP_Pos;
+
+ __WFI();
+
+ //Switch back to PLL as clock source if needed
+ //The interrupt that woke up the device will run at reduced speed
+ if (mcg_clock == kMcgClkSelOut) {
+ if (CLOCK_HAL_GetPllStatMode(MCG_BASE) == kMcgPllStatPllClkSel) {
+ while (CLOCK_HAL_GetLock0Mode(MCG_BASE) == kMcgLockUnlocked);
+ }
+ CLOCK_HAL_SetClkSrcMode(MCG_BASE, kMcgClkSelOut);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/spi_api.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include "mbed_assert.h"
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "fsl_clock_manager.h"
+#include "fsl_dspi_hal.h"
+#include "PeripheralPins.h"
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+ uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+ uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->instance = pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT((int)obj->instance != NC);
+
+ CLOCK_SYS_EnableSpiClock(obj->instance);
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ DSPI_HAL_Init(spi_address[obj->instance]);
+ DSPI_HAL_Disable(spi_address[obj->instance]);
+ DSPI_HAL_SetDelay(spi_address[obj->instance], kDspiCtar0, 0, 0, kDspiPcsToSck);
+
+ DSPI_HAL_Enable(spi_address[obj->instance]);
+ DSPI_HAL_StartTransfer(spi_address[obj->instance]);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {
+ // [TODO]
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ dspi_data_format_config_t config = {0};
+ config.bitsPerFrame = (uint32_t)bits;
+ config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh;
+ config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge;
+ config.direction = kDspiMsbFirst;
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ dspi_status_t result = DSPI_HAL_SetDataFormat(spi_address[obj->instance], kDspiCtar0, &config);
+ if (result != kStatus_DSPI_Success) {
+ error("Failed to configure SPI data format");
+ }
+
+ if (slave) {
+ DSPI_HAL_SetMasterSlaveMode(spi_address[obj->instance], kDspiSlave);
+ } else {
+ DSPI_HAL_SetMasterSlaveMode(spi_address[obj->instance], kDspiMaster);
+ }
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ uint32_t busClock;
+ CLOCK_SYS_GetFreq(kBusClock, &busClock);
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ DSPI_HAL_SetBaudRate(spi_address[obj->instance], kDspiCtar0, (uint32_t)hz, busClock);
+ DSPI_HAL_CalculateDelay(spi_address[obj->instance], kDspiCtar0, kDspiLastSckToPcs, busClock, 500000000 / hz); //Half clock period delay after SPI transfer
+}
+
+static inline int spi_writeable(spi_t * obj) {
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ return DSPI_HAL_GetStatusFlag(spi_address[obj->instance], kDspiTxFifoFillRequest);
+}
+
+static inline int spi_readable(spi_t * obj) {
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ return DSPI_HAL_GetStatusFlag(spi_address[obj->instance], kDspiRxFifoDrainRequest);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+
+ // wait tx buffer empty
+ while(!spi_writeable(obj));
+ dspi_command_config_t command = {0};
+ command.isEndOfQueue = true;
+ command.isChipSelectContinuous = 0;
+ DSPI_HAL_WriteDataMastermode(spi_address[obj->instance], &command, (uint16_t)value);
+ DSPI_HAL_ClearStatusFlag(spi_address[obj->instance], kDspiTxFifoFillRequest);
+
+ // wait rx buffer full
+ while (!spi_readable(obj));
+ DSPI_HAL_ClearStatusFlag(spi_address[obj->instance], kDspiRxFifoDrainRequest);
+ return DSPI_HAL_ReadData(spi_address[obj->instance]) & 0xff;
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return spi_readable(obj);
+}
+
+int spi_slave_read(spi_t *obj) {
+ DSPI_HAL_ClearStatusFlag(obj->instance, kDspiRxFifoDrainRequest);
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ return DSPI_HAL_ReadData(spi_address[obj->instance]);
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (!spi_writeable(obj));
+ uint32_t spi_address[] = SPI_BASE_ADDRS;
+ DSPI_HAL_WriteDataSlavemode(spi_address[obj->instance], (uint32_t)value);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/us_ticker.c Wed Mar 23 21:26:50 2016 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "fsl_pit_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) {
+ return;
+ }
+ us_ticker_inited = 1;
+
+ //Common for ticker/timer
+ uint32_t busClock;
+ CLOCK_SYS_EnablePitClock(0);
+ PIT_HAL_Enable(PIT_BASE);
+ CLOCK_SYS_GetFreq(kBusClock, &busClock);
+
+ //Timer
+ PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 0, busClock / 1000000 - 1);
+ PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 1, 0xFFFFFFFF);
+ PIT_HAL_SetTimerChainCmd(PIT_BASE, 1, true);
+ PIT_HAL_StartTimer(PIT_BASE, 0);
+ PIT_HAL_StartTimer(PIT_BASE, 1);
+
+ //Ticker
+ PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 2, busClock / 1000000 - 1);
+ PIT_HAL_SetTimerChainCmd(PIT_BASE, 3, true);
+ NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(PIT3_IRQn);
+}
+
+
+uint32_t us_ticker_read() {
+ if (!us_ticker_inited) {
+ us_ticker_init();
+ }
+
+ return ~(PIT_HAL_ReadTimerCount(PIT_BASE, 1));
+}
+
+void us_ticker_disable_interrupt(void) {
+ PIT_HAL_SetIntCmd(PIT_BASE, 3, false);
+}
+
+void us_ticker_clear_interrupt(void) {
+ PIT_HAL_ClearIntFlag(PIT_BASE, 3);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+ int delta = (int)(timestamp - us_ticker_read());
+ if (delta <= 0) {
+ // This event was in the past:
+ us_ticker_irq_handler();
+ return;
+ }
+
+ PIT_HAL_StopTimer(PIT_BASE, 3);
+ PIT_HAL_StopTimer(PIT_BASE, 2);
+ PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 3, (uint32_t)delta);
+ PIT_HAL_SetIntCmd(PIT_BASE, 3, true);
+ PIT_HAL_StartTimer(PIT_BASE, 3);
+ PIT_HAL_StartTimer(PIT_BASE, 2);
+}