Microbug / MicroBitDAL_SB2_TEST

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Fork of MicroBitDALImageRewrite by Joe Finney

CortexContextSwitch.s@2:6597fe50dc94, 2015-04-28 (annotated)

Committer:
finneyj
Date:
Tue Apr 28 18:32:34 2015 +0000
Revision:
2:6597fe50dc94
Integrated a Cortex M0 Fiber scheduler.; Updated MessageBus to generated events to decouple event handlers from interrupt context through use of scheduled fibers.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
finneyj 2:6597fe50dc94 1 AREA asm_func, CODE, READONLY
finneyj 2:6597fe50dc94 2
finneyj 2:6597fe50dc94 3 ; Export our context switching subroutine as a C function for use in mBed
finneyj 2:6597fe50dc94 4 EXPORT swap_context
finneyj 2:6597fe50dc94 5 EXPORT save_context
finneyj 2:6597fe50dc94 6
finneyj 2:6597fe50dc94 7 ALIGN
finneyj 2:6597fe50dc94 8
finneyj 2:6597fe50dc94 9 ; R0 Contains a pointer to the TCB of the fibre being scheduled out.
finneyj 2:6597fe50dc94 10 ; R1 Contains a pointer to the TCB of the fibre being scheduled in.
finneyj 2:6597fe50dc94 11 ; R2 Contains a pointer to the base of the stack of the fibre being scheduled out.
finneyj 2:6597fe50dc94 12 ; R3 Contains a pointer to the base of the stack of the fibre being scheduled in.
finneyj 2:6597fe50dc94 13
finneyj 2:6597fe50dc94 14 swap_context
finneyj 2:6597fe50dc94 15
finneyj 2:6597fe50dc94 16 ; Write our core registers into the TCB
finneyj 2:6597fe50dc94 17 ; First, store the general registers
finneyj 2:6597fe50dc94 18
finneyj 2:6597fe50dc94 19 STR R0, [R0,#0]
finneyj 2:6597fe50dc94 20 STR R1, [R0,#4]
finneyj 2:6597fe50dc94 21 STR R2, [R0,#8]
finneyj 2:6597fe50dc94 22 STR R3, [R0,#12]
finneyj 2:6597fe50dc94 23 STR R4, [R0,#16]
finneyj 2:6597fe50dc94 24 STR R5, [R0,#20]
finneyj 2:6597fe50dc94 25 STR R6, [R0,#24]
finneyj 2:6597fe50dc94 26 STR R7, [R0,#28]
finneyj 2:6597fe50dc94 27
finneyj 2:6597fe50dc94 28 ; Now the high general purpose registers
finneyj 2:6597fe50dc94 29 MOV R4, R8
finneyj 2:6597fe50dc94 30 STR R4, [R0,#32]
finneyj 2:6597fe50dc94 31 MOV R4, R9
finneyj 2:6597fe50dc94 32 STR R4, [R0,#36]
finneyj 2:6597fe50dc94 33 MOV R4, R10
finneyj 2:6597fe50dc94 34 STR R4, [R0,#40]
finneyj 2:6597fe50dc94 35 MOV R4, R11
finneyj 2:6597fe50dc94 36 STR R4, [R0,#44]
finneyj 2:6597fe50dc94 37 MOV R4, R12
finneyj 2:6597fe50dc94 38 STR R4, [R0,#48]
finneyj 2:6597fe50dc94 39
finneyj 2:6597fe50dc94 40 ; Now the Stack and Link Register.
finneyj 2:6597fe50dc94 41 ; As this context is only intended for use with a fiber scheduler,
finneyj 2:6597fe50dc94 42 ; we don't need the PC.
finneyj 2:6597fe50dc94 43 MOV R6, SP
finneyj 2:6597fe50dc94 44 STR R6, [R0,#52]
finneyj 2:6597fe50dc94 45 MOV R4, LR
finneyj 2:6597fe50dc94 46 STR R4, [R0,#56]
finneyj 2:6597fe50dc94 47
finneyj 2:6597fe50dc94 48 ; Finally, Copy the stack. We do this to reduce RAM footprint, as stackis usually very small at the point
finneyj 2:6597fe50dc94 49 ; of sceduling, but we need a lot of capacity for interrupt handling and other functions.
finneyj 2:6597fe50dc94 50
finneyj 2:6597fe50dc94 51 MOVS R7, #0x20 ; Load R8 with top of System Stack space.
finneyj 2:6597fe50dc94 52 LSLS R7, #24
finneyj 2:6597fe50dc94 53 MOVS R4, #0x40
finneyj 2:6597fe50dc94 54 LSLS R4, #8
finneyj 2:6597fe50dc94 55 ORRS R7, R4
finneyj 2:6597fe50dc94 56 MOV R4, R7
finneyj 2:6597fe50dc94 57
finneyj 2:6597fe50dc94 58 store_stack
finneyj 2:6597fe50dc94 59 SUBS R4, #4
finneyj 2:6597fe50dc94 60 SUBS R2, #4
finneyj 2:6597fe50dc94 61
finneyj 2:6597fe50dc94 62 LDR R5, [R4]
finneyj 2:6597fe50dc94 63 STR R5, [R2]
finneyj 2:6597fe50dc94 64
finneyj 2:6597fe50dc94 65 CMP R4, R6
finneyj 2:6597fe50dc94 66 BNE store_stack
finneyj 2:6597fe50dc94 67
finneyj 2:6597fe50dc94 68 ;
finneyj 2:6597fe50dc94 69 ; Now page in the new context.
finneyj 2:6597fe50dc94 70 ; Update all registers except the PC. We can also safely ignore the STATUS register, as we're just a fiber scheduler.
finneyj 2:6597fe50dc94 71 ;
finneyj 2:6597fe50dc94 72 LDR R4, [R1, #56]
finneyj 2:6597fe50dc94 73 MOV LR, R4
finneyj 2:6597fe50dc94 74 LDR R6, [R1, #52]
finneyj 2:6597fe50dc94 75 MOV SP, R6
finneyj 2:6597fe50dc94 76
finneyj 2:6597fe50dc94 77 ; Copy the stack in.
finneyj 2:6597fe50dc94 78 ; n.b. we do this after setting the SP to make comparisons easier.
finneyj 2:6597fe50dc94 79
finneyj 2:6597fe50dc94 80 MOV R4, R7 ; Load R4 with top of System Stack space.
finneyj 2:6597fe50dc94 81
finneyj 2:6597fe50dc94 82
finneyj 2:6597fe50dc94 83 restore_stack
finneyj 2:6597fe50dc94 84 SUBS R4, #4
finneyj 2:6597fe50dc94 85 SUBS R3, #4
finneyj 2:6597fe50dc94 86
finneyj 2:6597fe50dc94 87 LDR R5, [R3]
finneyj 2:6597fe50dc94 88 STR R5, [R4]
finneyj 2:6597fe50dc94 89
finneyj 2:6597fe50dc94 90 CMP R4, R6
finneyj 2:6597fe50dc94 91 BNE restore_stack
finneyj 2:6597fe50dc94 92
finneyj 2:6597fe50dc94 93 LDR R4, [R1, #48]
finneyj 2:6597fe50dc94 94 MOV R12, R4
finneyj 2:6597fe50dc94 95 LDR R4, [R1, #44]
finneyj 2:6597fe50dc94 96 MOV R11, R4
finneyj 2:6597fe50dc94 97 LDR R4, [R1, #40]
finneyj 2:6597fe50dc94 98 MOV R10, R4
finneyj 2:6597fe50dc94 99 LDR R4, [R1, #36]
finneyj 2:6597fe50dc94 100 MOV R9, R4
finneyj 2:6597fe50dc94 101 LDR R4, [R1, #32]
finneyj 2:6597fe50dc94 102 MOV R8, R4
finneyj 2:6597fe50dc94 103
finneyj 2:6597fe50dc94 104 LDR R7, [R1, #28]
finneyj 2:6597fe50dc94 105 LDR R6, [R1, #24]
finneyj 2:6597fe50dc94 106 LDR R5, [R1, #20]
finneyj 2:6597fe50dc94 107 LDR R4, [R1, #16]
finneyj 2:6597fe50dc94 108 LDR R3, [R1, #12]
finneyj 2:6597fe50dc94 109 LDR R2, [R1, #8]
finneyj 2:6597fe50dc94 110 LDR R0, [R1, #0]
finneyj 2:6597fe50dc94 111 LDR R1, [R1, #4]
finneyj 2:6597fe50dc94 112
finneyj 2:6597fe50dc94 113 ; Return to caller (scheduler).
finneyj 2:6597fe50dc94 114 BX LR
finneyj 2:6597fe50dc94 115
finneyj 2:6597fe50dc94 116
finneyj 2:6597fe50dc94 117
finneyj 2:6597fe50dc94 118
finneyj 2:6597fe50dc94 119 ; R0 Contains a pointer to the TCB of the fibre to snapshot
finneyj 2:6597fe50dc94 120 ; R1 Contains a pointer to the base of the stack of the fibre being snapshotted
finneyj 2:6597fe50dc94 121
finneyj 2:6597fe50dc94 122 save_context
finneyj 2:6597fe50dc94 123
finneyj 2:6597fe50dc94 124 ; Write our core registers into the TCB
finneyj 2:6597fe50dc94 125 ; First, store the general registers
finneyj 2:6597fe50dc94 126
finneyj 2:6597fe50dc94 127 STR R0, [R0,#0]
finneyj 2:6597fe50dc94 128 STR R1, [R0,#4]
finneyj 2:6597fe50dc94 129 STR R2, [R0,#8]
finneyj 2:6597fe50dc94 130 STR R3, [R0,#12]
finneyj 2:6597fe50dc94 131 STR R4, [R0,#16]
finneyj 2:6597fe50dc94 132 STR R5, [R0,#20]
finneyj 2:6597fe50dc94 133 STR R6, [R0,#24]
finneyj 2:6597fe50dc94 134 STR R7, [R0,#28]
finneyj 2:6597fe50dc94 135
finneyj 2:6597fe50dc94 136 ; Now the high general purpose registers
finneyj 2:6597fe50dc94 137 MOV R4, R8
finneyj 2:6597fe50dc94 138 STR R4, [R0,#32]
finneyj 2:6597fe50dc94 139 MOV R4, R9
finneyj 2:6597fe50dc94 140 STR R4, [R0,#36]
finneyj 2:6597fe50dc94 141 MOV R4, R10
finneyj 2:6597fe50dc94 142 STR R4, [R0,#40]
finneyj 2:6597fe50dc94 143 MOV R4, R11
finneyj 2:6597fe50dc94 144 STR R4, [R0,#44]
finneyj 2:6597fe50dc94 145 MOV R4, R12
finneyj 2:6597fe50dc94 146 STR R4, [R0,#48]
finneyj 2:6597fe50dc94 147
finneyj 2:6597fe50dc94 148 ; Now the Stack and Link Register.
finneyj 2:6597fe50dc94 149 ; As this context is only intended for use with a fiber scheduler,
finneyj 2:6597fe50dc94 150 ; we don't need the PC.
finneyj 2:6597fe50dc94 151 MOV R6, SP
finneyj 2:6597fe50dc94 152 STR R6, [R0,#52]
finneyj 2:6597fe50dc94 153 MOV R4, LR
finneyj 2:6597fe50dc94 154 STR R4, [R0,#56]
finneyj 2:6597fe50dc94 155
finneyj 2:6597fe50dc94 156 ; Finally, Copy the stack. We do this to reduce RAM footprint, as stackis usually very small at the point
finneyj 2:6597fe50dc94 157 ; of sceduling, but we need a lot of capacity for interrupt handling and other functions.
finneyj 2:6597fe50dc94 158
finneyj 2:6597fe50dc94 159 MOVS R5, #0x20 ; Load R8 with top of System Stack space.
finneyj 2:6597fe50dc94 160 LSLS R5, #24
finneyj 2:6597fe50dc94 161 MOVS R4, #0x40
finneyj 2:6597fe50dc94 162 LSLS R4, #8
finneyj 2:6597fe50dc94 163 ORRS R5, R4
finneyj 2:6597fe50dc94 164 MOV R4, R5
finneyj 2:6597fe50dc94 165
finneyj 2:6597fe50dc94 166 store_stack1
finneyj 2:6597fe50dc94 167 SUBS R4, #4
finneyj 2:6597fe50dc94 168 SUBS R1, #4
finneyj 2:6597fe50dc94 169
finneyj 2:6597fe50dc94 170 LDR R5, [R4]
finneyj 2:6597fe50dc94 171 STR R5, [R1]
finneyj 2:6597fe50dc94 172
finneyj 2:6597fe50dc94 173 CMP R4, R6
finneyj 2:6597fe50dc94 174 BNE store_stack1
finneyj 2:6597fe50dc94 175
finneyj 2:6597fe50dc94 176 ; Restore scratch registers.
finneyj 2:6597fe50dc94 177
finneyj 2:6597fe50dc94 178 LDR R7, [R0, #28]
finneyj 2:6597fe50dc94 179 LDR R6, [R0, #24]
finneyj 2:6597fe50dc94 180 LDR R5, [R0, #20]
finneyj 2:6597fe50dc94 181 LDR R4, [R0, #16]
finneyj 2:6597fe50dc94 182
finneyj 2:6597fe50dc94 183 ; Return to caller (scheduler).
finneyj 2:6597fe50dc94 184 BX LR
finneyj 2:6597fe50dc94 185
finneyj 2:6597fe50dc94 186 ALIGN
finneyj 2:6597fe50dc94 187 END