Maxim Integrated / max3134x

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Fork of max3134x by Mahir Ozturk

RtcBase.cpp@0:1efa49a69ff8, 2019-04-10 (annotated)

Committer:
Mahir Ozturk
Date:
Wed Apr 10 17:28:15 2019 +0300
Revision:
0:1efa49a69ff8
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Mahir Ozturk 0:1efa49a69ff8 1 /*******************************************************************************
Mahir Ozturk 0:1efa49a69ff8 2 * Copyright (C) 2018 Maxim Integrated Products, Inc., All Rights Reserved.
Mahir Ozturk 0:1efa49a69ff8 3 *
Mahir Ozturk 0:1efa49a69ff8 4 * Permission is hereby granted, free of charge, to any person obtaining a
Mahir Ozturk 0:1efa49a69ff8 5 * copy of this software and associated documentation files (the "Software"),
Mahir Ozturk 0:1efa49a69ff8 6 * to deal in the Software without restriction, including without limitation
Mahir Ozturk 0:1efa49a69ff8 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Mahir Ozturk 0:1efa49a69ff8 8 * and/or sell copies of the Software, and to permit persons to whom the
Mahir Ozturk 0:1efa49a69ff8 9 * Software is furnished to do so, subject to the following conditions:
Mahir Ozturk 0:1efa49a69ff8 10 *
Mahir Ozturk 0:1efa49a69ff8 11 * The above copyright notice and this permission notice shall be included
Mahir Ozturk 0:1efa49a69ff8 12 * in all copies or substantial portions of the Software.
Mahir Ozturk 0:1efa49a69ff8 13 *
Mahir Ozturk 0:1efa49a69ff8 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Mahir Ozturk 0:1efa49a69ff8 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Mahir Ozturk 0:1efa49a69ff8 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Mahir Ozturk 0:1efa49a69ff8 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Mahir Ozturk 0:1efa49a69ff8 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Mahir Ozturk 0:1efa49a69ff8 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Mahir Ozturk 0:1efa49a69ff8 20 * OTHER DEALINGS IN THE SOFTWARE.
Mahir Ozturk 0:1efa49a69ff8 21 *
Mahir Ozturk 0:1efa49a69ff8 22 * Except as contained in this notice, the name of Maxim Integrated
Mahir Ozturk 0:1efa49a69ff8 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Mahir Ozturk 0:1efa49a69ff8 24 * Products, Inc. Branding Policy.
Mahir Ozturk 0:1efa49a69ff8 25 *
Mahir Ozturk 0:1efa49a69ff8 26 * The mere transfer of this software does not imply any licenses
Mahir Ozturk 0:1efa49a69ff8 27 * of trade secrets, proprietary technology, copyrights, patents,
Mahir Ozturk 0:1efa49a69ff8 28 * trademarks, maskwork rights, or any other form of intellectual
Mahir Ozturk 0:1efa49a69ff8 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Mahir Ozturk 0:1efa49a69ff8 30 * ownership rights.
Mahir Ozturk 0:1efa49a69ff8 31 *******************************************************************************
Mahir Ozturk 0:1efa49a69ff8 32 */
Mahir Ozturk 0:1efa49a69ff8 33
Mahir Ozturk 0:1efa49a69ff8 34 #include "RtcBase.h"
Mahir Ozturk 0:1efa49a69ff8 35
Mahir Ozturk 0:1efa49a69ff8 36 #define pr_err(fmt, ...) if(1) printf(fmt " (%s:%d)\r\n", ## __VA_ARGS__, __func__, __LINE__)
Mahir Ozturk 0:1efa49a69ff8 37 #define pr_debug(fmt, ...) if(0) printf(fmt " (%s:%d)\r\n", ## __VA_ARGS__, __func__, __LINE__)
Mahir Ozturk 0:1efa49a69ff8 38
Mahir Ozturk 0:1efa49a69ff8 39 #define BCD2BIN(val) (((val) & 15) + ((val) >> 4) * 10)
Mahir Ozturk 0:1efa49a69ff8 40 #define BIN2BCD(val) ((((val) / 10) << 4) + (val) % 10)
Mahir Ozturk 0:1efa49a69ff8 41
Mahir Ozturk 0:1efa49a69ff8 42 #define POST_INTR_WORK_SIGNAL_ID 0x1
Mahir Ozturk 0:1efa49a69ff8 43
Mahir Ozturk 0:1efa49a69ff8 44 RtcBase::RtcBase(const regmap_t *regmap, I2C *i2c, PinName inta_pin = NC, PinName intb_pin = NC)
Mahir Ozturk 0:1efa49a69ff8 45 {
Mahir Ozturk 0:1efa49a69ff8 46 if (i2c == NULL) {
Mahir Ozturk 0:1efa49a69ff8 47 pr_err("i2c object is invalid!");
Mahir Ozturk 0:1efa49a69ff8 48 while (1);
Mahir Ozturk 0:1efa49a69ff8 49 }
Mahir Ozturk 0:1efa49a69ff8 50 i2c_handler = i2c;
Mahir Ozturk 0:1efa49a69ff8 51
Mahir Ozturk 0:1efa49a69ff8 52 this->regmap = regmap;
Mahir Ozturk 0:1efa49a69ff8 53
Mahir Ozturk 0:1efa49a69ff8 54 sw_reset_release();
Mahir Ozturk 0:1efa49a69ff8 55
Mahir Ozturk 0:1efa49a69ff8 56 rtc_start();
Mahir Ozturk 0:1efa49a69ff8 57
Mahir Ozturk 0:1efa49a69ff8 58 irq_disable_all();
Mahir Ozturk 0:1efa49a69ff8 59
Mahir Ozturk 0:1efa49a69ff8 60 post_intr_work_thread = new Thread();
Mahir Ozturk 0:1efa49a69ff8 61
Mahir Ozturk 0:1efa49a69ff8 62 post_intr_work_thread->start(Callback<void()>(this, &RtcBase::post_interrupt_work));
Mahir Ozturk 0:1efa49a69ff8 63
Mahir Ozturk 0:1efa49a69ff8 64 if (inta_pin != NC) {
Mahir Ozturk 0:1efa49a69ff8 65 this->inta_pin = new InterruptIn(inta_pin);
Mahir Ozturk 0:1efa49a69ff8 66
Mahir Ozturk 0:1efa49a69ff8 67 this->inta_pin->fall(Callback<void()>(this, &RtcBase::interrupt_handler));
Mahir Ozturk 0:1efa49a69ff8 68
Mahir Ozturk 0:1efa49a69ff8 69 this->inta_pin->enable_irq();
Mahir Ozturk 0:1efa49a69ff8 70 } else {
Mahir Ozturk 0:1efa49a69ff8 71 this->inta_pin = NULL;
Mahir Ozturk 0:1efa49a69ff8 72 }
Mahir Ozturk 0:1efa49a69ff8 73
Mahir Ozturk 0:1efa49a69ff8 74 if (intb_pin != NC) {
Mahir Ozturk 0:1efa49a69ff8 75 this->intb_pin = new InterruptIn(intb_pin);
Mahir Ozturk 0:1efa49a69ff8 76
Mahir Ozturk 0:1efa49a69ff8 77 this->intb_pin->fall(Callback<void()>(this, &RtcBase::interrupt_handler));
Mahir Ozturk 0:1efa49a69ff8 78
Mahir Ozturk 0:1efa49a69ff8 79 this->intb_pin->enable_irq();
Mahir Ozturk 0:1efa49a69ff8 80 } else {
Mahir Ozturk 0:1efa49a69ff8 81 this->intb_pin = NULL;
Mahir Ozturk 0:1efa49a69ff8 82 }
Mahir Ozturk 0:1efa49a69ff8 83 }
Mahir Ozturk 0:1efa49a69ff8 84
Mahir Ozturk 0:1efa49a69ff8 85 RtcBase::~RtcBase()
Mahir Ozturk 0:1efa49a69ff8 86 {
Mahir Ozturk 0:1efa49a69ff8 87 if (post_intr_work_thread) {
Mahir Ozturk 0:1efa49a69ff8 88 delete post_intr_work_thread;
Mahir Ozturk 0:1efa49a69ff8 89 }
Mahir Ozturk 0:1efa49a69ff8 90
Mahir Ozturk 0:1efa49a69ff8 91 if (inta_pin) {
Mahir Ozturk 0:1efa49a69ff8 92 delete inta_pin;
Mahir Ozturk 0:1efa49a69ff8 93 }
Mahir Ozturk 0:1efa49a69ff8 94
Mahir Ozturk 0:1efa49a69ff8 95 if (intb_pin) {
Mahir Ozturk 0:1efa49a69ff8 96 delete intb_pin;
Mahir Ozturk 0:1efa49a69ff8 97 }
Mahir Ozturk 0:1efa49a69ff8 98 }
Mahir Ozturk 0:1efa49a69ff8 99
Mahir Ozturk 0:1efa49a69ff8 100 int RtcBase::read_register(uint8_t reg, uint8_t *value, uint8_t len)
Mahir Ozturk 0:1efa49a69ff8 101 {
Mahir Ozturk 0:1efa49a69ff8 102 int ret;
Mahir Ozturk 0:1efa49a69ff8 103
Mahir Ozturk 0:1efa49a69ff8 104 if (value == NULL) {
Mahir Ozturk 0:1efa49a69ff8 105 pr_err("value is invalid!");
Mahir Ozturk 0:1efa49a69ff8 106 return -1;
Mahir Ozturk 0:1efa49a69ff8 107 }
Mahir Ozturk 0:1efa49a69ff8 108
Mahir Ozturk 0:1efa49a69ff8 109 ret = i2c_handler->write(MAX3134X_I2C_W, (const char *) &reg, 1, true);
Mahir Ozturk 0:1efa49a69ff8 110 if (ret != 0) {
Mahir Ozturk 0:1efa49a69ff8 111 pr_err("i2c write failed with %d!", ret);
Mahir Ozturk 0:1efa49a69ff8 112 return -1;
Mahir Ozturk 0:1efa49a69ff8 113 }
Mahir Ozturk 0:1efa49a69ff8 114
Mahir Ozturk 0:1efa49a69ff8 115 ret = i2c_handler->read(MAX3134X_I2C_R, (char *) value, len, false);
Mahir Ozturk 0:1efa49a69ff8 116 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 117 pr_err("i2c read failed with %d!", ret);
Mahir Ozturk 0:1efa49a69ff8 118 return -1;
Mahir Ozturk 0:1efa49a69ff8 119 }
Mahir Ozturk 0:1efa49a69ff8 120
Mahir Ozturk 0:1efa49a69ff8 121 return 0;
Mahir Ozturk 0:1efa49a69ff8 122 }
Mahir Ozturk 0:1efa49a69ff8 123
Mahir Ozturk 0:1efa49a69ff8 124 int RtcBase::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
Mahir Ozturk 0:1efa49a69ff8 125 {
Mahir Ozturk 0:1efa49a69ff8 126 int ret;
Mahir Ozturk 0:1efa49a69ff8 127 uint8_t *buffer;
Mahir Ozturk 0:1efa49a69ff8 128
Mahir Ozturk 0:1efa49a69ff8 129 if (value == NULL) {
Mahir Ozturk 0:1efa49a69ff8 130 pr_err("value is invalid!");
Mahir Ozturk 0:1efa49a69ff8 131 return -1;
Mahir Ozturk 0:1efa49a69ff8 132 }
Mahir Ozturk 0:1efa49a69ff8 133
Mahir Ozturk 0:1efa49a69ff8 134 buffer = new uint8_t[1 + len];
Mahir Ozturk 0:1efa49a69ff8 135 buffer[0] = reg;
Mahir Ozturk 0:1efa49a69ff8 136
Mahir Ozturk 0:1efa49a69ff8 137 memcpy(&buffer[1], value, len);
Mahir Ozturk 0:1efa49a69ff8 138
Mahir Ozturk 0:1efa49a69ff8 139 ret = i2c_handler->write(MAX3134X_I2C_W, (const char *)buffer, 1 + len);
Mahir Ozturk 0:1efa49a69ff8 140 if (ret != 0) {
Mahir Ozturk 0:1efa49a69ff8 141 pr_err("i2c write failed with %d!", ret);
Mahir Ozturk 0:1efa49a69ff8 142 }
Mahir Ozturk 0:1efa49a69ff8 143
Mahir Ozturk 0:1efa49a69ff8 144 delete[] buffer;
Mahir Ozturk 0:1efa49a69ff8 145
Mahir Ozturk 0:1efa49a69ff8 146 return ret;
Mahir Ozturk 0:1efa49a69ff8 147 }
Mahir Ozturk 0:1efa49a69ff8 148
Mahir Ozturk 0:1efa49a69ff8 149 int RtcBase::rtc_regs_to_time(struct tm *time, const rtc_time_regs_t *regs)
Mahir Ozturk 0:1efa49a69ff8 150 {
Mahir Ozturk 0:1efa49a69ff8 151 /* tm_sec seconds [0,61] */
Mahir Ozturk 0:1efa49a69ff8 152 time->tm_sec = BCD2BIN(regs->seconds.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 153
Mahir Ozturk 0:1efa49a69ff8 154 /* tm_min minutes [0,59] */
Mahir Ozturk 0:1efa49a69ff8 155 time->tm_min = BCD2BIN(regs->minutes.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 156
Mahir Ozturk 0:1efa49a69ff8 157 /* tm_hour hour [0,23] */
Mahir Ozturk 0:1efa49a69ff8 158 time->tm_hour = BCD2BIN(regs->hours.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 159
Mahir Ozturk 0:1efa49a69ff8 160 /* tm_wday day of week [0,6] (Sunday = 0) */
Mahir Ozturk 0:1efa49a69ff8 161 time->tm_wday = BCD2BIN(regs->day.bcd.value) - 1;
Mahir Ozturk 0:1efa49a69ff8 162
Mahir Ozturk 0:1efa49a69ff8 163 /* tm_mday day of month [1,31] */
Mahir Ozturk 0:1efa49a69ff8 164 time->tm_mday = BCD2BIN(regs->date.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 165
Mahir Ozturk 0:1efa49a69ff8 166 /* tm_mon month of year [0,11] */
Mahir Ozturk 0:1efa49a69ff8 167 time->tm_mon = BCD2BIN(regs->month.bcd.value) - 1;
Mahir Ozturk 0:1efa49a69ff8 168
Mahir Ozturk 0:1efa49a69ff8 169 /* tm_year years since 2000 */
Mahir Ozturk 0:1efa49a69ff8 170 if (regs->month.bits.century) {
Mahir Ozturk 0:1efa49a69ff8 171 time->tm_year = BCD2BIN(regs->year.bcd.value) + 200;
Mahir Ozturk 0:1efa49a69ff8 172 } else {
Mahir Ozturk 0:1efa49a69ff8 173 time->tm_year = BCD2BIN(regs->year.bcd.value) + 100;
Mahir Ozturk 0:1efa49a69ff8 174 }
Mahir Ozturk 0:1efa49a69ff8 175
Mahir Ozturk 0:1efa49a69ff8 176 /* tm_yday day of year [0,365] */
Mahir Ozturk 0:1efa49a69ff8 177 time->tm_yday = 0; /* TODO */
Mahir Ozturk 0:1efa49a69ff8 178
Mahir Ozturk 0:1efa49a69ff8 179 /* tm_isdst daylight savings flag */
Mahir Ozturk 0:1efa49a69ff8 180 time->tm_isdst = 0; /* TODO */
Mahir Ozturk 0:1efa49a69ff8 181
Mahir Ozturk 0:1efa49a69ff8 182 return 0;
Mahir Ozturk 0:1efa49a69ff8 183 }
Mahir Ozturk 0:1efa49a69ff8 184
Mahir Ozturk 0:1efa49a69ff8 185 int RtcBase::time_to_rtc_regs(rtc_time_regs_t *regs, const struct tm *time)
Mahir Ozturk 0:1efa49a69ff8 186 {
Mahir Ozturk 0:1efa49a69ff8 187 /*********************************************************
Mahir Ozturk 0:1efa49a69ff8 188 * +----------+------+---------------------------+-------+
Mahir Ozturk 0:1efa49a69ff8 189 * | Member | Type | Meaning | Range |
Mahir Ozturk 0:1efa49a69ff8 190 * +----------+------+---------------------------+-------+
Mahir Ozturk 0:1efa49a69ff8 191 * | tm_sec | int | seconds after the minute | 0-61* |
Mahir Ozturk 0:1efa49a69ff8 192 * | tm_min | int | minutes after the hour | 0-59 |
Mahir Ozturk 0:1efa49a69ff8 193 * | tm_hour | int | hours since midnight | 0-23 |
Mahir Ozturk 0:1efa49a69ff8 194 * | tm_mday | int | day of the month | 1-31 |
Mahir Ozturk 0:1efa49a69ff8 195 * | tm_mon | int | months since January | 0-11 |
Mahir Ozturk 0:1efa49a69ff8 196 * | tm_year | int | years since 1900 | |
Mahir Ozturk 0:1efa49a69ff8 197 * | tm_wday | int | days since Sunday | 0-6 |
Mahir Ozturk 0:1efa49a69ff8 198 * | tm_yday | int | days since January 1 | 0-365 |
Mahir Ozturk 0:1efa49a69ff8 199 * | tm_isdst | int | Daylight Saving Time flag | |
Mahir Ozturk 0:1efa49a69ff8 200 * +----------+------+---------------------------+-------+
Mahir Ozturk 0:1efa49a69ff8 201 * * tm_sec is generally 0-59. The extra range is to accommodate for leap
Mahir Ozturk 0:1efa49a69ff8 202 * seconds in certain systems.
Mahir Ozturk 0:1efa49a69ff8 203 *********************************************************/
Mahir Ozturk 0:1efa49a69ff8 204 regs->seconds.bcd.value = BIN2BCD(time->tm_sec);
Mahir Ozturk 0:1efa49a69ff8 205
Mahir Ozturk 0:1efa49a69ff8 206 regs->minutes.bcd.value = BIN2BCD(time->tm_min);
Mahir Ozturk 0:1efa49a69ff8 207
Mahir Ozturk 0:1efa49a69ff8 208 regs->hours.bcd.value= BIN2BCD(time->tm_hour);
Mahir Ozturk 0:1efa49a69ff8 209
Mahir Ozturk 0:1efa49a69ff8 210 regs->day.bcd.value = BIN2BCD(time->tm_wday + 1);
Mahir Ozturk 0:1efa49a69ff8 211
Mahir Ozturk 0:1efa49a69ff8 212 regs->date.bcd.value = BIN2BCD(time->tm_mday);
Mahir Ozturk 0:1efa49a69ff8 213
Mahir Ozturk 0:1efa49a69ff8 214 regs->month.bcd.value = BIN2BCD(time->tm_mon + 1);
Mahir Ozturk 0:1efa49a69ff8 215
Mahir Ozturk 0:1efa49a69ff8 216 if (time->tm_year >= 200) {
Mahir Ozturk 0:1efa49a69ff8 217 regs->month.bits.century = 1;
Mahir Ozturk 0:1efa49a69ff8 218 regs->year.bcd.value = BIN2BCD(time->tm_year - 200);
Mahir Ozturk 0:1efa49a69ff8 219 } else if (time->tm_year >= 100) {
Mahir Ozturk 0:1efa49a69ff8 220 regs->month.bits.century = 0;
Mahir Ozturk 0:1efa49a69ff8 221 regs->year.bcd.value = BIN2BCD(time->tm_year - 100);
Mahir Ozturk 0:1efa49a69ff8 222 } else {
Mahir Ozturk 0:1efa49a69ff8 223 pr_err("Invalid set date!");
Mahir Ozturk 0:1efa49a69ff8 224 return -1;
Mahir Ozturk 0:1efa49a69ff8 225 }
Mahir Ozturk 0:1efa49a69ff8 226
Mahir Ozturk 0:1efa49a69ff8 227 return 0;
Mahir Ozturk 0:1efa49a69ff8 228 }
Mahir Ozturk 0:1efa49a69ff8 229
Mahir Ozturk 0:1efa49a69ff8 230 int RtcBase::get_time(struct tm *time)
Mahir Ozturk 0:1efa49a69ff8 231 {
Mahir Ozturk 0:1efa49a69ff8 232 rtc_time_regs_t time_regs;
Mahir Ozturk 0:1efa49a69ff8 233
Mahir Ozturk 0:1efa49a69ff8 234 if (time == NULL) {
Mahir Ozturk 0:1efa49a69ff8 235 pr_err("rtc_ctime is invalid!");
Mahir Ozturk 0:1efa49a69ff8 236 return -1;
Mahir Ozturk 0:1efa49a69ff8 237 }
Mahir Ozturk 0:1efa49a69ff8 238
Mahir Ozturk 0:1efa49a69ff8 239 if (read_register(regmap->seconds, (uint8_t *) &time_regs,
Mahir Ozturk 0:1efa49a69ff8 240 sizeof(time_regs)) < 0) {
Mahir Ozturk 0:1efa49a69ff8 241 pr_err("read time registers failed!");
Mahir Ozturk 0:1efa49a69ff8 242 return -1;
Mahir Ozturk 0:1efa49a69ff8 243 }
Mahir Ozturk 0:1efa49a69ff8 244
Mahir Ozturk 0:1efa49a69ff8 245 return rtc_regs_to_time(time, &time_regs);
Mahir Ozturk 0:1efa49a69ff8 246 }
Mahir Ozturk 0:1efa49a69ff8 247
Mahir Ozturk 0:1efa49a69ff8 248 int RtcBase::set_rtc_time()
Mahir Ozturk 0:1efa49a69ff8 249 {
Mahir Ozturk 0:1efa49a69ff8 250 config_reg2_t reg;
Mahir Ozturk 0:1efa49a69ff8 251
Mahir Ozturk 0:1efa49a69ff8 252 /* Toggle Set_RTC bit to set RTC date */
Mahir Ozturk 0:1efa49a69ff8 253
Mahir Ozturk 0:1efa49a69ff8 254 if (read_register(regmap->config_reg2, (uint8_t *)&reg, 1) < 0) {
Mahir Ozturk 0:1efa49a69ff8 255 pr_err("read time registers failed!");
Mahir Ozturk 0:1efa49a69ff8 256 return -1;
Mahir Ozturk 0:1efa49a69ff8 257 }
Mahir Ozturk 0:1efa49a69ff8 258
Mahir Ozturk 0:1efa49a69ff8 259 reg.bits.set_rtc = CONFIG_REG2_SET_RTC_RTCPRGM;
Mahir Ozturk 0:1efa49a69ff8 260 if (write_register(regmap->config_reg2, (uint8_t *)&reg, 1) < 0) {
Mahir Ozturk 0:1efa49a69ff8 261 pr_err("write config2 register failed!");
Mahir Ozturk 0:1efa49a69ff8 262 return -1;
Mahir Ozturk 0:1efa49a69ff8 263 }
Mahir Ozturk 0:1efa49a69ff8 264
Mahir Ozturk 0:1efa49a69ff8 265 /* SET_RTC bit should be kept high at least 10ms */
Mahir Ozturk 0:1efa49a69ff8 266 ThisThread::sleep_for(10);
Mahir Ozturk 0:1efa49a69ff8 267
Mahir Ozturk 0:1efa49a69ff8 268 reg.bits.set_rtc = CONFIG_REG2_SET_RTC_RTCRUN;
Mahir Ozturk 0:1efa49a69ff8 269 if (write_register(regmap->config_reg2, (uint8_t *)&reg, 1) < 0) {
Mahir Ozturk 0:1efa49a69ff8 270 pr_err("write config2 register failed!");
Mahir Ozturk 0:1efa49a69ff8 271 return -1;
Mahir Ozturk 0:1efa49a69ff8 272 }
Mahir Ozturk 0:1efa49a69ff8 273
Mahir Ozturk 0:1efa49a69ff8 274 return 0;
Mahir Ozturk 0:1efa49a69ff8 275 }
Mahir Ozturk 0:1efa49a69ff8 276
Mahir Ozturk 0:1efa49a69ff8 277 int RtcBase::set_time(const struct tm *time)
Mahir Ozturk 0:1efa49a69ff8 278 {
Mahir Ozturk 0:1efa49a69ff8 279 rtc_time_regs_t time_regs;
Mahir Ozturk 0:1efa49a69ff8 280
Mahir Ozturk 0:1efa49a69ff8 281 if (time == NULL) {
Mahir Ozturk 0:1efa49a69ff8 282 pr_err("rtc_ctime is invalid!");
Mahir Ozturk 0:1efa49a69ff8 283 return -1;
Mahir Ozturk 0:1efa49a69ff8 284 }
Mahir Ozturk 0:1efa49a69ff8 285
Mahir Ozturk 0:1efa49a69ff8 286 time_to_rtc_regs(&time_regs, time);
Mahir Ozturk 0:1efa49a69ff8 287
Mahir Ozturk 0:1efa49a69ff8 288 if (write_register(regmap->seconds, (const uint8_t *) &time_regs,
Mahir Ozturk 0:1efa49a69ff8 289 sizeof(time_regs)) < 0) {
Mahir Ozturk 0:1efa49a69ff8 290 pr_err("read time registers failed!");
Mahir Ozturk 0:1efa49a69ff8 291 return -1;
Mahir Ozturk 0:1efa49a69ff8 292 }
Mahir Ozturk 0:1efa49a69ff8 293
Mahir Ozturk 0:1efa49a69ff8 294 return set_rtc_time();
Mahir Ozturk 0:1efa49a69ff8 295 }
Mahir Ozturk 0:1efa49a69ff8 296
Mahir Ozturk 0:1efa49a69ff8 297 int RtcBase::nvram_write(const uint8_t *buffer, int offset, int length)
Mahir Ozturk 0:1efa49a69ff8 298 {
Mahir Ozturk 0:1efa49a69ff8 299 int totlen;
Mahir Ozturk 0:1efa49a69ff8 300
Mahir Ozturk 0:1efa49a69ff8 301 if (regmap->ram_start == REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 302 pr_err("Device does not have NVRAM!");
Mahir Ozturk 0:1efa49a69ff8 303 return -1;
Mahir Ozturk 0:1efa49a69ff8 304 }
Mahir Ozturk 0:1efa49a69ff8 305
Mahir Ozturk 0:1efa49a69ff8 306 totlen = regmap->ram_end - regmap->ram_start + 1;
Mahir Ozturk 0:1efa49a69ff8 307
Mahir Ozturk 0:1efa49a69ff8 308 if ((offset + length) > totlen) {
Mahir Ozturk 0:1efa49a69ff8 309 return -1;
Mahir Ozturk 0:1efa49a69ff8 310 }
Mahir Ozturk 0:1efa49a69ff8 311
Mahir Ozturk 0:1efa49a69ff8 312 if (length == 0) {
Mahir Ozturk 0:1efa49a69ff8 313 return 0;
Mahir Ozturk 0:1efa49a69ff8 314 }
Mahir Ozturk 0:1efa49a69ff8 315
Mahir Ozturk 0:1efa49a69ff8 316 if (write_register(regmap->ram_start + offset, buffer, length) < 0) {
Mahir Ozturk 0:1efa49a69ff8 317 return -1;
Mahir Ozturk 0:1efa49a69ff8 318 }
Mahir Ozturk 0:1efa49a69ff8 319
Mahir Ozturk 0:1efa49a69ff8 320 return 0;
Mahir Ozturk 0:1efa49a69ff8 321 }
Mahir Ozturk 0:1efa49a69ff8 322
Mahir Ozturk 0:1efa49a69ff8 323 int RtcBase::nvram_read(uint8_t *buffer, int offset, int length)
Mahir Ozturk 0:1efa49a69ff8 324 {
Mahir Ozturk 0:1efa49a69ff8 325 int totlen;
Mahir Ozturk 0:1efa49a69ff8 326
Mahir Ozturk 0:1efa49a69ff8 327 if (regmap->ram_start == REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 328 pr_err("Device does not have NVRAM!");
Mahir Ozturk 0:1efa49a69ff8 329 return -1;
Mahir Ozturk 0:1efa49a69ff8 330 }
Mahir Ozturk 0:1efa49a69ff8 331
Mahir Ozturk 0:1efa49a69ff8 332 totlen = regmap->ram_end - regmap->ram_start + 1;
Mahir Ozturk 0:1efa49a69ff8 333
Mahir Ozturk 0:1efa49a69ff8 334 if ((offset + length) > totlen) {
Mahir Ozturk 0:1efa49a69ff8 335 return -1;
Mahir Ozturk 0:1efa49a69ff8 336 }
Mahir Ozturk 0:1efa49a69ff8 337
Mahir Ozturk 0:1efa49a69ff8 338 if (length == 0) {
Mahir Ozturk 0:1efa49a69ff8 339 return -1;
Mahir Ozturk 0:1efa49a69ff8 340 }
Mahir Ozturk 0:1efa49a69ff8 341
Mahir Ozturk 0:1efa49a69ff8 342 if (read_register(regmap->ram_start + offset, buffer, length) < 0) {
Mahir Ozturk 0:1efa49a69ff8 343 return -1;
Mahir Ozturk 0:1efa49a69ff8 344 }
Mahir Ozturk 0:1efa49a69ff8 345
Mahir Ozturk 0:1efa49a69ff8 346 return 0;
Mahir Ozturk 0:1efa49a69ff8 347 }
Mahir Ozturk 0:1efa49a69ff8 348
Mahir Ozturk 0:1efa49a69ff8 349 int RtcBase::nvram_size()
Mahir Ozturk 0:1efa49a69ff8 350 {
Mahir Ozturk 0:1efa49a69ff8 351 if ((regmap->ram_start == REG_NOT_AVAILABLE) ||
Mahir Ozturk 0:1efa49a69ff8 352 (regmap->ram_end == REG_NOT_AVAILABLE)) {
Mahir Ozturk 0:1efa49a69ff8 353 return 0;
Mahir Ozturk 0:1efa49a69ff8 354 }
Mahir Ozturk 0:1efa49a69ff8 355
Mahir Ozturk 0:1efa49a69ff8 356 return regmap->ram_end - regmap->ram_start + 1;
Mahir Ozturk 0:1efa49a69ff8 357 }
Mahir Ozturk 0:1efa49a69ff8 358
Mahir Ozturk 0:1efa49a69ff8 359 int RtcBase::time_to_alarm_regs(alarm_regs_t &regs, const struct tm *alarm_time)
Mahir Ozturk 0:1efa49a69ff8 360 {
Mahir Ozturk 0:1efa49a69ff8 361 regs.sec.bcd.value = BIN2BCD(alarm_time->tm_sec);
Mahir Ozturk 0:1efa49a69ff8 362 regs.min.bcd.value = BIN2BCD(alarm_time->tm_min);
Mahir Ozturk 0:1efa49a69ff8 363 regs.hrs.bcd.value = BIN2BCD(alarm_time->tm_hour);
Mahir Ozturk 0:1efa49a69ff8 364
Mahir Ozturk 0:1efa49a69ff8 365 if (regs.day_date.bits.dy_dt == 0) {
Mahir Ozturk 0:1efa49a69ff8 366 /* Date match */
Mahir Ozturk 0:1efa49a69ff8 367 regs.day_date.bcd_date.value = BIN2BCD(alarm_time->tm_mday);
Mahir Ozturk 0:1efa49a69ff8 368 } else {
Mahir Ozturk 0:1efa49a69ff8 369 /* Day match */
Mahir Ozturk 0:1efa49a69ff8 370 regs.day_date.bcd_day.value = BIN2BCD(alarm_time->tm_wday);
Mahir Ozturk 0:1efa49a69ff8 371 }
Mahir Ozturk 0:1efa49a69ff8 372 regs.mon.bcd.value = BIN2BCD(alarm_time->tm_mon);
Mahir Ozturk 0:1efa49a69ff8 373
Mahir Ozturk 0:1efa49a69ff8 374 return 0;
Mahir Ozturk 0:1efa49a69ff8 375 }
Mahir Ozturk 0:1efa49a69ff8 376
Mahir Ozturk 0:1efa49a69ff8 377 int RtcBase::alarm_regs_to_time(struct tm *alarm_time, const alarm_regs_t *regs)
Mahir Ozturk 0:1efa49a69ff8 378 {
Mahir Ozturk 0:1efa49a69ff8 379 alarm_time->tm_sec = BCD2BIN(regs->sec.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 380 alarm_time->tm_min = BCD2BIN(regs->min.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 381 alarm_time->tm_hour = BCD2BIN(regs->hrs.bcd.value);
Mahir Ozturk 0:1efa49a69ff8 382
Mahir Ozturk 0:1efa49a69ff8 383 if (regs->day_date.bits.dy_dt == 0) { /* date */
Mahir Ozturk 0:1efa49a69ff8 384 alarm_time->tm_mday = BCD2BIN(regs->day_date.bcd_date.value);
Mahir Ozturk 0:1efa49a69ff8 385 } else { /* day */
Mahir Ozturk 0:1efa49a69ff8 386 alarm_time->tm_wday = BCD2BIN(regs->day_date.bcd_day.value);
Mahir Ozturk 0:1efa49a69ff8 387 }
Mahir Ozturk 0:1efa49a69ff8 388
Mahir Ozturk 0:1efa49a69ff8 389 if (regmap->alm1_mon != REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 390 alarm_time->tm_mon = BCD2BIN(regs->mon.bcd.value) - 1;
Mahir Ozturk 0:1efa49a69ff8 391 }
Mahir Ozturk 0:1efa49a69ff8 392
Mahir Ozturk 0:1efa49a69ff8 393 if (regmap->alm1_year != REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 394 alarm_time->tm_year = BCD2BIN(regs->year.bcd.value) + 100; /* XXX no century bit */
Mahir Ozturk 0:1efa49a69ff8 395 }
Mahir Ozturk 0:1efa49a69ff8 396
Mahir Ozturk 0:1efa49a69ff8 397 return 0;
Mahir Ozturk 0:1efa49a69ff8 398 }
Mahir Ozturk 0:1efa49a69ff8 399
Mahir Ozturk 0:1efa49a69ff8 400 int RtcBase::set_alarm_period(alarm_no_t alarm_no, alarm_regs_t &regs, alarm_period_t period)
Mahir Ozturk 0:1efa49a69ff8 401 {
Mahir Ozturk 0:1efa49a69ff8 402 regs.sec.bits.a1m1 = 1;
Mahir Ozturk 0:1efa49a69ff8 403 regs.min.bits.a1m2 = 1;
Mahir Ozturk 0:1efa49a69ff8 404 regs.hrs.bits.a1m3 = 1;
Mahir Ozturk 0:1efa49a69ff8 405 regs.day_date.bits.a1m4 = 1;
Mahir Ozturk 0:1efa49a69ff8 406 regs.mon.bits.a1m5 = 1;
Mahir Ozturk 0:1efa49a69ff8 407 regs.mon.bits.a1m6 = 1;
Mahir Ozturk 0:1efa49a69ff8 408 regs.day_date.bits.dy_dt = 1;
Mahir Ozturk 0:1efa49a69ff8 409
Mahir Ozturk 0:1efa49a69ff8 410 switch (period) {
Mahir Ozturk 0:1efa49a69ff8 411 case ALARM_PERIOD_ONETIME:
Mahir Ozturk 0:1efa49a69ff8 412 if ((alarm_no == ALARM2) || (regmap->alm1_year == REG_NOT_AVAILABLE)) { /* not supported! */
Mahir Ozturk 0:1efa49a69ff8 413 return -1;
Mahir Ozturk 0:1efa49a69ff8 414 }
Mahir Ozturk 0:1efa49a69ff8 415 regs.mon.bits.a1m6 = 0;
Mahir Ozturk 0:1efa49a69ff8 416 case ALARM_PERIOD_YEARLY:
Mahir Ozturk 0:1efa49a69ff8 417 if ((alarm_no == ALARM2) || (regmap->alm1_mon == REG_NOT_AVAILABLE)) { /* not supported! */
Mahir Ozturk 0:1efa49a69ff8 418 return -1;
Mahir Ozturk 0:1efa49a69ff8 419 }
Mahir Ozturk 0:1efa49a69ff8 420 regs.mon.bits.a1m5 = 0;
Mahir Ozturk 0:1efa49a69ff8 421 case ALARM_PERIOD_MONTHLY:
Mahir Ozturk 0:1efa49a69ff8 422 regs.day_date.bits.dy_dt = 0;
Mahir Ozturk 0:1efa49a69ff8 423 case ALARM_PERIOD_WEEKLY:
Mahir Ozturk 0:1efa49a69ff8 424 regs.day_date.bits.a1m4 = 0;
Mahir Ozturk 0:1efa49a69ff8 425 case ALARM_PERIOD_DAILY:
Mahir Ozturk 0:1efa49a69ff8 426 regs.hrs.bits.a1m3 = 0;
Mahir Ozturk 0:1efa49a69ff8 427 case ALARM_PERIOD_HOURLY:
Mahir Ozturk 0:1efa49a69ff8 428 regs.min.bits.a1m2 = 0;
Mahir Ozturk 0:1efa49a69ff8 429 case ALARM_PERIOD_EVERYMINUTE:
Mahir Ozturk 0:1efa49a69ff8 430 regs.sec.bits.a1m1 = 0;
Mahir Ozturk 0:1efa49a69ff8 431 case ALARM_PERIOD_EVERYSECOND:
Mahir Ozturk 0:1efa49a69ff8 432 if ((alarm_no == ALARM2) && (period == ALARM_PERIOD_EVERYSECOND)) {
Mahir Ozturk 0:1efa49a69ff8 433 return -1; /* Alarm2 does not support "once per second" alarm*/
Mahir Ozturk 0:1efa49a69ff8 434 }
Mahir Ozturk 0:1efa49a69ff8 435 break;
Mahir Ozturk 0:1efa49a69ff8 436 default:
Mahir Ozturk 0:1efa49a69ff8 437 return -1;
Mahir Ozturk 0:1efa49a69ff8 438 }
Mahir Ozturk 0:1efa49a69ff8 439
Mahir Ozturk 0:1efa49a69ff8 440 return 0;
Mahir Ozturk 0:1efa49a69ff8 441 }
Mahir Ozturk 0:1efa49a69ff8 442
Mahir Ozturk 0:1efa49a69ff8 443 int RtcBase::set_alarm_regs(alarm_no_t alarm_no, const alarm_regs_t *regs)
Mahir Ozturk 0:1efa49a69ff8 444 {
Mahir Ozturk 0:1efa49a69ff8 445 uint8_t *ptr_regs = (uint8_t *)regs;
Mahir Ozturk 0:1efa49a69ff8 446 uint8_t off = 0;
Mahir Ozturk 0:1efa49a69ff8 447 uint8_t dev_ba;
Mahir Ozturk 0:1efa49a69ff8 448 uint8_t len = sizeof(alarm_regs_t);
Mahir Ozturk 0:1efa49a69ff8 449
Mahir Ozturk 0:1efa49a69ff8 450 if (alarm_no == ALARM1) {
Mahir Ozturk 0:1efa49a69ff8 451 dev_ba = regmap->alm1_sec;
Mahir Ozturk 0:1efa49a69ff8 452 if (regmap->alm1_mon == REG_NOT_AVAILABLE) len -= 2; /* discard mon & year registers */
Mahir Ozturk 0:1efa49a69ff8 453 } else {
Mahir Ozturk 0:1efa49a69ff8 454 dev_ba = regmap->alm2_min;
Mahir Ozturk 0:1efa49a69ff8 455 off = 1; /* starts from min register */
Mahir Ozturk 0:1efa49a69ff8 456 len -= 3; /* discard min, mon & sec registers */
Mahir Ozturk 0:1efa49a69ff8 457 }
Mahir Ozturk 0:1efa49a69ff8 458
Mahir Ozturk 0:1efa49a69ff8 459 return write_register(dev_ba, &ptr_regs[off], len);
Mahir Ozturk 0:1efa49a69ff8 460 }
Mahir Ozturk 0:1efa49a69ff8 461
Mahir Ozturk 0:1efa49a69ff8 462 int RtcBase::get_alarm_regs(alarm_no_t alarm_no, alarm_regs_t *regs)
Mahir Ozturk 0:1efa49a69ff8 463 {
Mahir Ozturk 0:1efa49a69ff8 464 uint8_t *ptr_regs = (uint8_t *)regs;
Mahir Ozturk 0:1efa49a69ff8 465 uint8_t off = 0;
Mahir Ozturk 0:1efa49a69ff8 466 uint8_t dev_ba;
Mahir Ozturk 0:1efa49a69ff8 467 uint8_t len = sizeof(alarm_regs_t);
Mahir Ozturk 0:1efa49a69ff8 468
Mahir Ozturk 0:1efa49a69ff8 469 if (alarm_no == ALARM1) {
Mahir Ozturk 0:1efa49a69ff8 470 dev_ba = regmap->alm1_sec;
Mahir Ozturk 0:1efa49a69ff8 471 if (regmap->alm1_mon == REG_NOT_AVAILABLE) len -= 2; /* discard mon & year registers */
Mahir Ozturk 0:1efa49a69ff8 472 } else {
Mahir Ozturk 0:1efa49a69ff8 473 regs->sec.raw = 0; /* zeroise second register for alarm2 */
Mahir Ozturk 0:1efa49a69ff8 474 dev_ba = regmap->alm2_min;
Mahir Ozturk 0:1efa49a69ff8 475 off = 1; /* starts from min register (no sec register) */
Mahir Ozturk 0:1efa49a69ff8 476 len -= 2; /* discard mon & sec registers */
Mahir Ozturk 0:1efa49a69ff8 477 }
Mahir Ozturk 0:1efa49a69ff8 478
Mahir Ozturk 0:1efa49a69ff8 479 return read_register(dev_ba, &ptr_regs[off], len);
Mahir Ozturk 0:1efa49a69ff8 480 }
Mahir Ozturk 0:1efa49a69ff8 481
Mahir Ozturk 0:1efa49a69ff8 482 int RtcBase::set_alarm(alarm_no_t alarm_no, const struct tm *alarm_time, alarm_period_t period)
Mahir Ozturk 0:1efa49a69ff8 483 {
Mahir Ozturk 0:1efa49a69ff8 484 int ret;
Mahir Ozturk 0:1efa49a69ff8 485 alarm_regs_t regs;
Mahir Ozturk 0:1efa49a69ff8 486
Mahir Ozturk 0:1efa49a69ff8 487 ret = set_alarm_period(alarm_no, regs, period);
Mahir Ozturk 0:1efa49a69ff8 488 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 489 return ret;
Mahir Ozturk 0:1efa49a69ff8 490 }
Mahir Ozturk 0:1efa49a69ff8 491
Mahir Ozturk 0:1efa49a69ff8 492 /* Convert time structure to alarm registers */
Mahir Ozturk 0:1efa49a69ff8 493 ret = time_to_alarm_regs(regs, alarm_time);
Mahir Ozturk 0:1efa49a69ff8 494 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 495 return ret;
Mahir Ozturk 0:1efa49a69ff8 496 }
Mahir Ozturk 0:1efa49a69ff8 497
Mahir Ozturk 0:1efa49a69ff8 498 ret = set_alarm_regs(alarm_no, &regs);
Mahir Ozturk 0:1efa49a69ff8 499 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 500 return ret;
Mahir Ozturk 0:1efa49a69ff8 501 }
Mahir Ozturk 0:1efa49a69ff8 502
Mahir Ozturk 0:1efa49a69ff8 503 return 0;
Mahir Ozturk 0:1efa49a69ff8 504 }
Mahir Ozturk 0:1efa49a69ff8 505
Mahir Ozturk 0:1efa49a69ff8 506 int RtcBase::get_alarm(alarm_no_t alarm_no, struct tm *alarm_time, alarm_period_t *period, bool *is_enabled)
Mahir Ozturk 0:1efa49a69ff8 507 {
Mahir Ozturk 0:1efa49a69ff8 508 int ret;
Mahir Ozturk 0:1efa49a69ff8 509 alarm_regs_t regs;
Mahir Ozturk 0:1efa49a69ff8 510 uint8_t reg;
Mahir Ozturk 0:1efa49a69ff8 511
Mahir Ozturk 0:1efa49a69ff8 512 ret = get_alarm_regs(alarm_no, &regs);
Mahir Ozturk 0:1efa49a69ff8 513 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 514 return ret;
Mahir Ozturk 0:1efa49a69ff8 515 }
Mahir Ozturk 0:1efa49a69ff8 516
Mahir Ozturk 0:1efa49a69ff8 517 /* Convert alarm registers to time structure */
Mahir Ozturk 0:1efa49a69ff8 518 ret = alarm_regs_to_time(alarm_time, &regs);
Mahir Ozturk 0:1efa49a69ff8 519 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 520 return ret;
Mahir Ozturk 0:1efa49a69ff8 521 }
Mahir Ozturk 0:1efa49a69ff8 522
Mahir Ozturk 0:1efa49a69ff8 523 *period = (alarm_no == ALARM1) ? ALARM_PERIOD_EVERYSECOND : ALARM_PERIOD_EVERYMINUTE;
Mahir Ozturk 0:1efa49a69ff8 524
Mahir Ozturk 0:1efa49a69ff8 525 if ((alarm_no == ALARM1) && (regs.sec.bits.a1m1 == 0)) *period = ALARM_PERIOD_EVERYMINUTE;
Mahir Ozturk 0:1efa49a69ff8 526 if (regs.min.bits.a1m2 == 0) *period = ALARM_PERIOD_HOURLY;
Mahir Ozturk 0:1efa49a69ff8 527 if (regs.hrs.bits.a1m3 == 0) *period = ALARM_PERIOD_DAILY;
Mahir Ozturk 0:1efa49a69ff8 528 if (regs.day_date.bits.a1m4 == 0) *period = ALARM_PERIOD_WEEKLY;
Mahir Ozturk 0:1efa49a69ff8 529 if (regs.day_date.bits.dy_dt == 0) *period = ALARM_PERIOD_MONTHLY;
Mahir Ozturk 0:1efa49a69ff8 530 if ((alarm_no == ALARM1) && (regmap->alm1_mon != REG_NOT_AVAILABLE) && (regs.mon.bits.a1m5 == 0)) *period = ALARM_PERIOD_YEARLY;
Mahir Ozturk 0:1efa49a69ff8 531 if ((alarm_no == ALARM1) && (regmap->alm1_mon != REG_NOT_AVAILABLE) && (regs.mon.bits.a1m6 == 0)) *period = ALARM_PERIOD_ONETIME;
Mahir Ozturk 0:1efa49a69ff8 532
Mahir Ozturk 0:1efa49a69ff8 533 ret = read_register(regmap->int_en_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 534 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 535 return ret;
Mahir Ozturk 0:1efa49a69ff8 536 }
Mahir Ozturk 0:1efa49a69ff8 537
Mahir Ozturk 0:1efa49a69ff8 538 if (alarm_no == ALARM1) {
Mahir Ozturk 0:1efa49a69ff8 539 *is_enabled = (reg & (1 << INTR_ID_ALARM1)) != 0;
Mahir Ozturk 0:1efa49a69ff8 540 } else {
Mahir Ozturk 0:1efa49a69ff8 541 *is_enabled = (reg & (1 << INTR_ID_ALARM2)) != 0;
Mahir Ozturk 0:1efa49a69ff8 542 }
Mahir Ozturk 0:1efa49a69ff8 543
Mahir Ozturk 0:1efa49a69ff8 544 return 0;
Mahir Ozturk 0:1efa49a69ff8 545 }
Mahir Ozturk 0:1efa49a69ff8 546
Mahir Ozturk 0:1efa49a69ff8 547 int RtcBase::set_power_mgmt_mode(power_mgmt_mode_t mode)
Mahir Ozturk 0:1efa49a69ff8 548 {
Mahir Ozturk 0:1efa49a69ff8 549 int ret;
Mahir Ozturk 0:1efa49a69ff8 550 pwr_mgmt_reg_t reg;
Mahir Ozturk 0:1efa49a69ff8 551
Mahir Ozturk 0:1efa49a69ff8 552 if (regmap->pwr_mgmt_reg == REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 553 pr_err("Device does not support power mgmt!");
Mahir Ozturk 0:1efa49a69ff8 554 return -1;
Mahir Ozturk 0:1efa49a69ff8 555 }
Mahir Ozturk 0:1efa49a69ff8 556
Mahir Ozturk 0:1efa49a69ff8 557 ret = read_register(regmap->pwr_mgmt_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 558 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 559 return ret;
Mahir Ozturk 0:1efa49a69ff8 560 }
Mahir Ozturk 0:1efa49a69ff8 561
Mahir Ozturk 0:1efa49a69ff8 562 reg.bits.d_mode = mode;
Mahir Ozturk 0:1efa49a69ff8 563
Mahir Ozturk 0:1efa49a69ff8 564 ret = write_register(regmap->pwr_mgmt_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 565 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 566 return ret;
Mahir Ozturk 0:1efa49a69ff8 567 }
Mahir Ozturk 0:1efa49a69ff8 568
Mahir Ozturk 0:1efa49a69ff8 569 return 0;
Mahir Ozturk 0:1efa49a69ff8 570 }
Mahir Ozturk 0:1efa49a69ff8 571
Mahir Ozturk 0:1efa49a69ff8 572 int RtcBase::comparator_threshold_level(comp_thresh_t th)
Mahir Ozturk 0:1efa49a69ff8 573 {
Mahir Ozturk 0:1efa49a69ff8 574 int ret;
Mahir Ozturk 0:1efa49a69ff8 575 config_reg2_t reg;
Mahir Ozturk 0:1efa49a69ff8 576
Mahir Ozturk 0:1efa49a69ff8 577 if (regmap->pwr_mgmt_reg == REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 578 pr_err("Device does not support analog comparator!");
Mahir Ozturk 0:1efa49a69ff8 579 return -1;
Mahir Ozturk 0:1efa49a69ff8 580 }
Mahir Ozturk 0:1efa49a69ff8 581
Mahir Ozturk 0:1efa49a69ff8 582 ret = read_register(regmap->config_reg2, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 583 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 584 return ret;
Mahir Ozturk 0:1efa49a69ff8 585 }
Mahir Ozturk 0:1efa49a69ff8 586
Mahir Ozturk 0:1efa49a69ff8 587 reg.bits.bref = th;
Mahir Ozturk 0:1efa49a69ff8 588
Mahir Ozturk 0:1efa49a69ff8 589 ret = write_register(regmap->config_reg2, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 590 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 591 return ret;
Mahir Ozturk 0:1efa49a69ff8 592 }
Mahir Ozturk 0:1efa49a69ff8 593
Mahir Ozturk 0:1efa49a69ff8 594 return 0;
Mahir Ozturk 0:1efa49a69ff8 595 }
Mahir Ozturk 0:1efa49a69ff8 596
Mahir Ozturk 0:1efa49a69ff8 597 int RtcBase::supply_select(power_mgmt_supply_t supply)
Mahir Ozturk 0:1efa49a69ff8 598 {
Mahir Ozturk 0:1efa49a69ff8 599 int ret;
Mahir Ozturk 0:1efa49a69ff8 600 pwr_mgmt_reg_t reg;
Mahir Ozturk 0:1efa49a69ff8 601
Mahir Ozturk 0:1efa49a69ff8 602 if (regmap->pwr_mgmt_reg == REG_NOT_AVAILABLE) {
Mahir Ozturk 0:1efa49a69ff8 603 pr_err("Device does not support power mgmt!");
Mahir Ozturk 0:1efa49a69ff8 604 return -1;
Mahir Ozturk 0:1efa49a69ff8 605 }
Mahir Ozturk 0:1efa49a69ff8 606
Mahir Ozturk 0:1efa49a69ff8 607 ret = read_register(regmap->pwr_mgmt_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 608 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 609 return ret;
Mahir Ozturk 0:1efa49a69ff8 610 }
Mahir Ozturk 0:1efa49a69ff8 611
Mahir Ozturk 0:1efa49a69ff8 612 switch (supply) {
Mahir Ozturk 0:1efa49a69ff8 613 case POW_MGMT_SUPPLY_SEL_VCC:
Mahir Ozturk 0:1efa49a69ff8 614 reg.bits.d_man_sel = 1;
Mahir Ozturk 0:1efa49a69ff8 615 reg.bits.d_vback_sel = 0;
Mahir Ozturk 0:1efa49a69ff8 616 break;
Mahir Ozturk 0:1efa49a69ff8 617 case POW_MGMT_SUPPLY_SEL_AIN:
Mahir Ozturk 0:1efa49a69ff8 618 reg.bits.d_man_sel = 1;
Mahir Ozturk 0:1efa49a69ff8 619 reg.bits.d_vback_sel = 1;
Mahir Ozturk 0:1efa49a69ff8 620 break;
Mahir Ozturk 0:1efa49a69ff8 621 case POW_MGMT_SUPPLY_SEL_AUTO:
Mahir Ozturk 0:1efa49a69ff8 622 default:
Mahir Ozturk 0:1efa49a69ff8 623 reg.bits.d_man_sel = 0;
Mahir Ozturk 0:1efa49a69ff8 624 break;
Mahir Ozturk 0:1efa49a69ff8 625 }
Mahir Ozturk 0:1efa49a69ff8 626
Mahir Ozturk 0:1efa49a69ff8 627 ret = write_register(regmap->pwr_mgmt_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 628 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 629 return ret;
Mahir Ozturk 0:1efa49a69ff8 630 }
Mahir Ozturk 0:1efa49a69ff8 631
Mahir Ozturk 0:1efa49a69ff8 632 return 0;
Mahir Ozturk 0:1efa49a69ff8 633 }
Mahir Ozturk 0:1efa49a69ff8 634
Mahir Ozturk 0:1efa49a69ff8 635 int RtcBase::trickle_charger_enable(trickle_charger_ohm_t res, bool diode)
Mahir Ozturk 0:1efa49a69ff8 636 {
Mahir Ozturk 0:1efa49a69ff8 637 int ret;
Mahir Ozturk 0:1efa49a69ff8 638 struct {
Mahir Ozturk 0:1efa49a69ff8 639 unsigned char ohm : 2;
Mahir Ozturk 0:1efa49a69ff8 640 unsigned char diode : 1;
Mahir Ozturk 0:1efa49a69ff8 641 unsigned char schottky : 1;
Mahir Ozturk 0:1efa49a69ff8 642 unsigned char : 4;
Mahir Ozturk 0:1efa49a69ff8 643 } reg;
Mahir Ozturk 0:1efa49a69ff8 644
Mahir Ozturk 0:1efa49a69ff8 645 if (regmap->trickle_reg == REG_NOT_AVAILABLE) { /* trickle charger not supported! */
Mahir Ozturk 0:1efa49a69ff8 646 pr_err("Device does not support trickle charger!");
Mahir Ozturk 0:1efa49a69ff8 647 return -1;
Mahir Ozturk 0:1efa49a69ff8 648 }
Mahir Ozturk 0:1efa49a69ff8 649
Mahir Ozturk 0:1efa49a69ff8 650 reg.ohm = res;
Mahir Ozturk 0:1efa49a69ff8 651
Mahir Ozturk 0:1efa49a69ff8 652 reg.diode = (diode) ? 1 : 0;
Mahir Ozturk 0:1efa49a69ff8 653
Mahir Ozturk 0:1efa49a69ff8 654 reg.schottky = 1; /* always enabled */
Mahir Ozturk 0:1efa49a69ff8 655
Mahir Ozturk 0:1efa49a69ff8 656 ret = write_register(regmap->trickle_reg, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 657 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 658 return ret;
Mahir Ozturk 0:1efa49a69ff8 659 }
Mahir Ozturk 0:1efa49a69ff8 660
Mahir Ozturk 0:1efa49a69ff8 661 return 0;
Mahir Ozturk 0:1efa49a69ff8 662 }
Mahir Ozturk 0:1efa49a69ff8 663
Mahir Ozturk 0:1efa49a69ff8 664 int RtcBase::trickle_charger_disable()
Mahir Ozturk 0:1efa49a69ff8 665 {
Mahir Ozturk 0:1efa49a69ff8 666 int ret;
Mahir Ozturk 0:1efa49a69ff8 667 uint8_t reg;
Mahir Ozturk 0:1efa49a69ff8 668
Mahir Ozturk 0:1efa49a69ff8 669 if (regmap->trickle_reg == REG_NOT_AVAILABLE) { /* trickle charger not supported! */
Mahir Ozturk 0:1efa49a69ff8 670 pr_err("Device does not support trickle charger!");
Mahir Ozturk 0:1efa49a69ff8 671 return -1;
Mahir Ozturk 0:1efa49a69ff8 672 }
Mahir Ozturk 0:1efa49a69ff8 673
Mahir Ozturk 0:1efa49a69ff8 674 reg = 0;
Mahir Ozturk 0:1efa49a69ff8 675
Mahir Ozturk 0:1efa49a69ff8 676 ret = write_register(regmap->trickle_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 677 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 678 return ret;
Mahir Ozturk 0:1efa49a69ff8 679 }
Mahir Ozturk 0:1efa49a69ff8 680
Mahir Ozturk 0:1efa49a69ff8 681 return 0;
Mahir Ozturk 0:1efa49a69ff8 682 }
Mahir Ozturk 0:1efa49a69ff8 683
Mahir Ozturk 0:1efa49a69ff8 684
Mahir Ozturk 0:1efa49a69ff8 685 int RtcBase::set_output_square_wave_frequency(square_wave_out_freq_t freq)
Mahir Ozturk 0:1efa49a69ff8 686 {
Mahir Ozturk 0:1efa49a69ff8 687 int ret;
Mahir Ozturk 0:1efa49a69ff8 688 config_reg1_t reg;
Mahir Ozturk 0:1efa49a69ff8 689
Mahir Ozturk 0:1efa49a69ff8 690 ret = read_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 691 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 692 return ret;
Mahir Ozturk 0:1efa49a69ff8 693 }
Mahir Ozturk 0:1efa49a69ff8 694
Mahir Ozturk 0:1efa49a69ff8 695 reg.bits.rs = freq;
Mahir Ozturk 0:1efa49a69ff8 696
Mahir Ozturk 0:1efa49a69ff8 697 ret = write_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 698 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 699 return ret;
Mahir Ozturk 0:1efa49a69ff8 700 }
Mahir Ozturk 0:1efa49a69ff8 701
Mahir Ozturk 0:1efa49a69ff8 702 return 0;
Mahir Ozturk 0:1efa49a69ff8 703 }
Mahir Ozturk 0:1efa49a69ff8 704
Mahir Ozturk 0:1efa49a69ff8 705 int RtcBase::set_clock_sync_delay(sync_delay_t delay)
Mahir Ozturk 0:1efa49a69ff8 706 {
Mahir Ozturk 0:1efa49a69ff8 707 int ret;
Mahir Ozturk 0:1efa49a69ff8 708 clock_sync_reg_t reg;
Mahir Ozturk 0:1efa49a69ff8 709
Mahir Ozturk 0:1efa49a69ff8 710 ret = read_register(regmap->clock_sync_delay, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 711 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 712 return ret;
Mahir Ozturk 0:1efa49a69ff8 713 }
Mahir Ozturk 0:1efa49a69ff8 714
Mahir Ozturk 0:1efa49a69ff8 715 reg.bits.sync_delay = delay;
Mahir Ozturk 0:1efa49a69ff8 716
Mahir Ozturk 0:1efa49a69ff8 717 ret = write_register(regmap->clock_sync_delay, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 718 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 719 return ret;
Mahir Ozturk 0:1efa49a69ff8 720 }
Mahir Ozturk 0:1efa49a69ff8 721
Mahir Ozturk 0:1efa49a69ff8 722 return 0;
Mahir Ozturk 0:1efa49a69ff8 723 }
Mahir Ozturk 0:1efa49a69ff8 724
Mahir Ozturk 0:1efa49a69ff8 725 int RtcBase::set_clkin_frequency(clkin_freq_t freq)
Mahir Ozturk 0:1efa49a69ff8 726 {
Mahir Ozturk 0:1efa49a69ff8 727 int ret;
Mahir Ozturk 0:1efa49a69ff8 728 config_reg1_t reg;
Mahir Ozturk 0:1efa49a69ff8 729
Mahir Ozturk 0:1efa49a69ff8 730 ret = read_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 731 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 732 return ret;
Mahir Ozturk 0:1efa49a69ff8 733 }
Mahir Ozturk 0:1efa49a69ff8 734
Mahir Ozturk 0:1efa49a69ff8 735 reg.bits.clksel = freq;
Mahir Ozturk 0:1efa49a69ff8 736
Mahir Ozturk 0:1efa49a69ff8 737 ret = write_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 738 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 739 return ret;
Mahir Ozturk 0:1efa49a69ff8 740 }
Mahir Ozturk 0:1efa49a69ff8 741
Mahir Ozturk 0:1efa49a69ff8 742 if (freq == CLKIN_FREQ_1HZ) {
Mahir Ozturk 0:1efa49a69ff8 743 ret = set_clock_sync_delay(SYNC_DLY_LESS_THAN_1SEC);
Mahir Ozturk 0:1efa49a69ff8 744 } else {
Mahir Ozturk 0:1efa49a69ff8 745 ret = set_clock_sync_delay(SYNC_DLY_LESS_THAN_100MS);
Mahir Ozturk 0:1efa49a69ff8 746 }
Mahir Ozturk 0:1efa49a69ff8 747
Mahir Ozturk 0:1efa49a69ff8 748 return ret;
Mahir Ozturk 0:1efa49a69ff8 749 }
Mahir Ozturk 0:1efa49a69ff8 750
Mahir Ozturk 0:1efa49a69ff8 751 int RtcBase::configure_intb_clkout_pin(config_intb_clkout_pin_t sel)
Mahir Ozturk 0:1efa49a69ff8 752 {
Mahir Ozturk 0:1efa49a69ff8 753 int ret;
Mahir Ozturk 0:1efa49a69ff8 754 config_reg1_t reg;
Mahir Ozturk 0:1efa49a69ff8 755
Mahir Ozturk 0:1efa49a69ff8 756 ret = read_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 757 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 758 return ret;
Mahir Ozturk 0:1efa49a69ff8 759 }
Mahir Ozturk 0:1efa49a69ff8 760
Mahir Ozturk 0:1efa49a69ff8 761 reg.bits.intcn = (sel == CONFIGURE_PIN_AS_INTB) ? 1 : 0;
Mahir Ozturk 0:1efa49a69ff8 762
Mahir Ozturk 0:1efa49a69ff8 763 ret = write_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 764 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 765 return ret;
Mahir Ozturk 0:1efa49a69ff8 766 }
Mahir Ozturk 0:1efa49a69ff8 767
Mahir Ozturk 0:1efa49a69ff8 768 return 0;
Mahir Ozturk 0:1efa49a69ff8 769 }
Mahir Ozturk 0:1efa49a69ff8 770
Mahir Ozturk 0:1efa49a69ff8 771 int RtcBase::configure_inta_clkin_pin(config_inta_clkin_pin_t sel)
Mahir Ozturk 0:1efa49a69ff8 772 {
Mahir Ozturk 0:1efa49a69ff8 773 int ret;
Mahir Ozturk 0:1efa49a69ff8 774 config_reg1_t reg;
Mahir Ozturk 0:1efa49a69ff8 775
Mahir Ozturk 0:1efa49a69ff8 776 ret = read_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 777 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 778 return ret;
Mahir Ozturk 0:1efa49a69ff8 779 }
Mahir Ozturk 0:1efa49a69ff8 780
Mahir Ozturk 0:1efa49a69ff8 781 reg.bits.eclk = (sel == CONFIGURE_PIN_AS_CLKIN) ? 1 : 0;
Mahir Ozturk 0:1efa49a69ff8 782
Mahir Ozturk 0:1efa49a69ff8 783 ret = write_register(regmap->config_reg1, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 784 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 785 return ret;
Mahir Ozturk 0:1efa49a69ff8 786 }
Mahir Ozturk 0:1efa49a69ff8 787
Mahir Ozturk 0:1efa49a69ff8 788 if (sel == CONFIGURE_PIN_AS_CLKIN) {
Mahir Ozturk 0:1efa49a69ff8 789 /* Default synchronization delay for external clock mode */
Mahir Ozturk 0:1efa49a69ff8 790 ret = set_clock_sync_delay(SYNC_DLY_LESS_THAN_1SEC);
Mahir Ozturk 0:1efa49a69ff8 791 } else {
Mahir Ozturk 0:1efa49a69ff8 792 /* Synchronization delay for internal oscillator mode */
Mahir Ozturk 0:1efa49a69ff8 793 ret = set_clock_sync_delay(SYNC_DLY_LESS_THAN_20MS);
Mahir Ozturk 0:1efa49a69ff8 794 }
Mahir Ozturk 0:1efa49a69ff8 795
Mahir Ozturk 0:1efa49a69ff8 796 return ret;
Mahir Ozturk 0:1efa49a69ff8 797 }
Mahir Ozturk 0:1efa49a69ff8 798
Mahir Ozturk 0:1efa49a69ff8 799 int RtcBase::timer_init(uint8_t value, bool repeat, timer_freq_t freq)
Mahir Ozturk 0:1efa49a69ff8 800 {
Mahir Ozturk 0:1efa49a69ff8 801 int ret;
Mahir Ozturk 0:1efa49a69ff8 802 timer_config_t reg_cfg;
Mahir Ozturk 0:1efa49a69ff8 803
Mahir Ozturk 0:1efa49a69ff8 804 ret = read_register(regmap->timer_config, (uint8_t *)&reg_cfg, 1);
Mahir Ozturk 0:1efa49a69ff8 805 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 806 return ret;
Mahir Ozturk 0:1efa49a69ff8 807 }
Mahir Ozturk 0:1efa49a69ff8 808
Mahir Ozturk 0:1efa49a69ff8 809 reg_cfg.bits.te = 0; /* timer is reset */
Mahir Ozturk 0:1efa49a69ff8 810 reg_cfg.bits.tpause = 1; /* timer is paused */
Mahir Ozturk 0:1efa49a69ff8 811 reg_cfg.bits.trpt = repeat ? 1 : 0; /* Timer repeat mode */
Mahir Ozturk 0:1efa49a69ff8 812 reg_cfg.bits.tfs = freq; /* Timer frequency */
Mahir Ozturk 0:1efa49a69ff8 813
Mahir Ozturk 0:1efa49a69ff8 814 ret = write_register(regmap->timer_config, (uint8_t *)&reg_cfg, 1);
Mahir Ozturk 0:1efa49a69ff8 815 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 816 return ret;
Mahir Ozturk 0:1efa49a69ff8 817 }
Mahir Ozturk 0:1efa49a69ff8 818
Mahir Ozturk 0:1efa49a69ff8 819 ret = write_register(regmap->timer_init, (uint8_t *)&value, 1);
Mahir Ozturk 0:1efa49a69ff8 820 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 821 return ret;
Mahir Ozturk 0:1efa49a69ff8 822 }
Mahir Ozturk 0:1efa49a69ff8 823
Mahir Ozturk 0:1efa49a69ff8 824 return 0;
Mahir Ozturk 0:1efa49a69ff8 825 }
Mahir Ozturk 0:1efa49a69ff8 826
Mahir Ozturk 0:1efa49a69ff8 827 uint8_t RtcBase::timer_get()
Mahir Ozturk 0:1efa49a69ff8 828 {
Mahir Ozturk 0:1efa49a69ff8 829 int ret;
Mahir Ozturk 0:1efa49a69ff8 830 uint8_t reg;
Mahir Ozturk 0:1efa49a69ff8 831
Mahir Ozturk 0:1efa49a69ff8 832 ret = read_register(regmap->timer_count, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 833 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 834 return (uint8_t) - 1;
Mahir Ozturk 0:1efa49a69ff8 835 }
Mahir Ozturk 0:1efa49a69ff8 836
Mahir Ozturk 0:1efa49a69ff8 837 return reg;
Mahir Ozturk 0:1efa49a69ff8 838 }
Mahir Ozturk 0:1efa49a69ff8 839
Mahir Ozturk 0:1efa49a69ff8 840 int RtcBase::timer_start()
Mahir Ozturk 0:1efa49a69ff8 841 {
Mahir Ozturk 0:1efa49a69ff8 842 int ret;
Mahir Ozturk 0:1efa49a69ff8 843 timer_config_t reg;
Mahir Ozturk 0:1efa49a69ff8 844
Mahir Ozturk 0:1efa49a69ff8 845 ret = read_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 846 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 847 return ret;
Mahir Ozturk 0:1efa49a69ff8 848 }
Mahir Ozturk 0:1efa49a69ff8 849
Mahir Ozturk 0:1efa49a69ff8 850 reg.bits.te = 1;
Mahir Ozturk 0:1efa49a69ff8 851 reg.bits.tpause = 0;
Mahir Ozturk 0:1efa49a69ff8 852
Mahir Ozturk 0:1efa49a69ff8 853 ret = write_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 854 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 855 return ret;
Mahir Ozturk 0:1efa49a69ff8 856 }
Mahir Ozturk 0:1efa49a69ff8 857
Mahir Ozturk 0:1efa49a69ff8 858 return 0;
Mahir Ozturk 0:1efa49a69ff8 859 }
Mahir Ozturk 0:1efa49a69ff8 860
Mahir Ozturk 0:1efa49a69ff8 861 int RtcBase::timer_pause()
Mahir Ozturk 0:1efa49a69ff8 862 {
Mahir Ozturk 0:1efa49a69ff8 863 int ret;
Mahir Ozturk 0:1efa49a69ff8 864 timer_config_t reg;
Mahir Ozturk 0:1efa49a69ff8 865
Mahir Ozturk 0:1efa49a69ff8 866 ret = read_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 867 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 868 return ret;
Mahir Ozturk 0:1efa49a69ff8 869 }
Mahir Ozturk 0:1efa49a69ff8 870
Mahir Ozturk 0:1efa49a69ff8 871 reg.bits.te = 1;
Mahir Ozturk 0:1efa49a69ff8 872 reg.bits.tpause = 1;
Mahir Ozturk 0:1efa49a69ff8 873
Mahir Ozturk 0:1efa49a69ff8 874 ret = write_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 875 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 876 return ret;
Mahir Ozturk 0:1efa49a69ff8 877 }
Mahir Ozturk 0:1efa49a69ff8 878
Mahir Ozturk 0:1efa49a69ff8 879 return 0;
Mahir Ozturk 0:1efa49a69ff8 880 }
Mahir Ozturk 0:1efa49a69ff8 881
Mahir Ozturk 0:1efa49a69ff8 882 int RtcBase::timer_continue()
Mahir Ozturk 0:1efa49a69ff8 883 {
Mahir Ozturk 0:1efa49a69ff8 884 int ret;
Mahir Ozturk 0:1efa49a69ff8 885 timer_config_t reg;
Mahir Ozturk 0:1efa49a69ff8 886
Mahir Ozturk 0:1efa49a69ff8 887 ret = read_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 888 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 889 return ret;
Mahir Ozturk 0:1efa49a69ff8 890 }
Mahir Ozturk 0:1efa49a69ff8 891
Mahir Ozturk 0:1efa49a69ff8 892 reg.bits.te = 1;
Mahir Ozturk 0:1efa49a69ff8 893 reg.bits.tpause = 0;
Mahir Ozturk 0:1efa49a69ff8 894
Mahir Ozturk 0:1efa49a69ff8 895 ret = write_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 896 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 897 return ret;
Mahir Ozturk 0:1efa49a69ff8 898 }
Mahir Ozturk 0:1efa49a69ff8 899
Mahir Ozturk 0:1efa49a69ff8 900 return 0;
Mahir Ozturk 0:1efa49a69ff8 901 }
Mahir Ozturk 0:1efa49a69ff8 902
Mahir Ozturk 0:1efa49a69ff8 903 int RtcBase::timer_stop()
Mahir Ozturk 0:1efa49a69ff8 904 {
Mahir Ozturk 0:1efa49a69ff8 905 int ret;
Mahir Ozturk 0:1efa49a69ff8 906 timer_config_t reg;
Mahir Ozturk 0:1efa49a69ff8 907
Mahir Ozturk 0:1efa49a69ff8 908 ret = read_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 909 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 910 return ret;
Mahir Ozturk 0:1efa49a69ff8 911 }
Mahir Ozturk 0:1efa49a69ff8 912
Mahir Ozturk 0:1efa49a69ff8 913 reg.bits.te = 0;
Mahir Ozturk 0:1efa49a69ff8 914 reg.bits.tpause = 1;
Mahir Ozturk 0:1efa49a69ff8 915
Mahir Ozturk 0:1efa49a69ff8 916 ret = write_register(regmap->timer_config, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 917 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 918 return ret;
Mahir Ozturk 0:1efa49a69ff8 919 }
Mahir Ozturk 0:1efa49a69ff8 920
Mahir Ozturk 0:1efa49a69ff8 921 return 0;
Mahir Ozturk 0:1efa49a69ff8 922 }
Mahir Ozturk 0:1efa49a69ff8 923
Mahir Ozturk 0:1efa49a69ff8 924 int RtcBase::data_retention_mode_config(int state)
Mahir Ozturk 0:1efa49a69ff8 925 {
Mahir Ozturk 0:1efa49a69ff8 926 int ret;
Mahir Ozturk 0:1efa49a69ff8 927 config_reg1_t cfg1;
Mahir Ozturk 0:1efa49a69ff8 928 config_reg2_t cfg2;
Mahir Ozturk 0:1efa49a69ff8 929
Mahir Ozturk 0:1efa49a69ff8 930 ret = read_register(regmap->config_reg1, (uint8_t *)&cfg1, 1);
Mahir Ozturk 0:1efa49a69ff8 931 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 932 return ret;
Mahir Ozturk 0:1efa49a69ff8 933 }
Mahir Ozturk 0:1efa49a69ff8 934
Mahir Ozturk 0:1efa49a69ff8 935 ret = read_register(regmap->config_reg2, (uint8_t *)&cfg2, 1);
Mahir Ozturk 0:1efa49a69ff8 936 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 937 return ret;
Mahir Ozturk 0:1efa49a69ff8 938 }
Mahir Ozturk 0:1efa49a69ff8 939
Mahir Ozturk 0:1efa49a69ff8 940 if (state) {
Mahir Ozturk 0:1efa49a69ff8 941 cfg1.bits.osconz = 1;
Mahir Ozturk 0:1efa49a69ff8 942 cfg2.bits.data_reten = 1;
Mahir Ozturk 0:1efa49a69ff8 943 } else {
Mahir Ozturk 0:1efa49a69ff8 944 cfg1.bits.osconz = 0;
Mahir Ozturk 0:1efa49a69ff8 945 cfg2.bits.data_reten = 0;
Mahir Ozturk 0:1efa49a69ff8 946 }
Mahir Ozturk 0:1efa49a69ff8 947
Mahir Ozturk 0:1efa49a69ff8 948 ret = write_register(regmap->config_reg1, (uint8_t *)&cfg1, 1);
Mahir Ozturk 0:1efa49a69ff8 949 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 950 return ret;
Mahir Ozturk 0:1efa49a69ff8 951 }
Mahir Ozturk 0:1efa49a69ff8 952
Mahir Ozturk 0:1efa49a69ff8 953 ret = write_register(regmap->config_reg2, (uint8_t *)&cfg2, 1);
Mahir Ozturk 0:1efa49a69ff8 954 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 955 return ret;
Mahir Ozturk 0:1efa49a69ff8 956 }
Mahir Ozturk 0:1efa49a69ff8 957
Mahir Ozturk 0:1efa49a69ff8 958 return 0;
Mahir Ozturk 0:1efa49a69ff8 959 }
Mahir Ozturk 0:1efa49a69ff8 960
Mahir Ozturk 0:1efa49a69ff8 961 int RtcBase::data_retention_mode_enter()
Mahir Ozturk 0:1efa49a69ff8 962 {
Mahir Ozturk 0:1efa49a69ff8 963 return data_retention_mode_config(1);
Mahir Ozturk 0:1efa49a69ff8 964 }
Mahir Ozturk 0:1efa49a69ff8 965
Mahir Ozturk 0:1efa49a69ff8 966 int RtcBase::data_retention_mode_exit()
Mahir Ozturk 0:1efa49a69ff8 967 {
Mahir Ozturk 0:1efa49a69ff8 968 return data_retention_mode_config(0);
Mahir Ozturk 0:1efa49a69ff8 969 }
Mahir Ozturk 0:1efa49a69ff8 970
Mahir Ozturk 0:1efa49a69ff8 971 int RtcBase::i2c_timeout_config(int enable)
Mahir Ozturk 0:1efa49a69ff8 972 {
Mahir Ozturk 0:1efa49a69ff8 973 int ret;
Mahir Ozturk 0:1efa49a69ff8 974 config_reg2_t reg;
Mahir Ozturk 0:1efa49a69ff8 975
Mahir Ozturk 0:1efa49a69ff8 976 ret = read_register(regmap->config_reg2, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 977 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 978 return ret;
Mahir Ozturk 0:1efa49a69ff8 979 }
Mahir Ozturk 0:1efa49a69ff8 980
Mahir Ozturk 0:1efa49a69ff8 981 reg.bits.i2c_timeout = (enable) ? 1 : 0;
Mahir Ozturk 0:1efa49a69ff8 982
Mahir Ozturk 0:1efa49a69ff8 983 ret = write_register(regmap->config_reg2, (uint8_t *)&reg, 1);
Mahir Ozturk 0:1efa49a69ff8 984 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 985 return ret;
Mahir Ozturk 0:1efa49a69ff8 986 }
Mahir Ozturk 0:1efa49a69ff8 987
Mahir Ozturk 0:1efa49a69ff8 988 return 0;
Mahir Ozturk 0:1efa49a69ff8 989 }
Mahir Ozturk 0:1efa49a69ff8 990
Mahir Ozturk 0:1efa49a69ff8 991 int RtcBase::i2c_timeout_enable()
Mahir Ozturk 0:1efa49a69ff8 992 {
Mahir Ozturk 0:1efa49a69ff8 993 return i2c_timeout_config(1);
Mahir Ozturk 0:1efa49a69ff8 994 }
Mahir Ozturk 0:1efa49a69ff8 995
Mahir Ozturk 0:1efa49a69ff8 996 int RtcBase::i2c_timeout_disable()
Mahir Ozturk 0:1efa49a69ff8 997 {
Mahir Ozturk 0:1efa49a69ff8 998 return i2c_timeout_config(0);
Mahir Ozturk 0:1efa49a69ff8 999 }
Mahir Ozturk 0:1efa49a69ff8 1000
Mahir Ozturk 0:1efa49a69ff8 1001 int RtcBase::irq_enable(intr_id_t id)
Mahir Ozturk 0:1efa49a69ff8 1002 {
Mahir Ozturk 0:1efa49a69ff8 1003 int ret;
Mahir Ozturk 0:1efa49a69ff8 1004 uint8_t reg;
Mahir Ozturk 0:1efa49a69ff8 1005
Mahir Ozturk 0:1efa49a69ff8 1006 ret = read_register(regmap->int_en_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1007 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1008 return ret;
Mahir Ozturk 0:1efa49a69ff8 1009 }
Mahir Ozturk 0:1efa49a69ff8 1010
Mahir Ozturk 0:1efa49a69ff8 1011 reg |= (1 << id);
Mahir Ozturk 0:1efa49a69ff8 1012
Mahir Ozturk 0:1efa49a69ff8 1013 ret = write_register(regmap->int_en_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1014 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1015 return ret;
Mahir Ozturk 0:1efa49a69ff8 1016 }
Mahir Ozturk 0:1efa49a69ff8 1017
Mahir Ozturk 0:1efa49a69ff8 1018 return 0;
Mahir Ozturk 0:1efa49a69ff8 1019 }
Mahir Ozturk 0:1efa49a69ff8 1020
Mahir Ozturk 0:1efa49a69ff8 1021 int RtcBase::irq_disable(intr_id_t id)
Mahir Ozturk 0:1efa49a69ff8 1022 {
Mahir Ozturk 0:1efa49a69ff8 1023 int ret;
Mahir Ozturk 0:1efa49a69ff8 1024 uint8_t reg;
Mahir Ozturk 0:1efa49a69ff8 1025
Mahir Ozturk 0:1efa49a69ff8 1026 ret = read_register(regmap->int_en_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1027 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1028 return ret;
Mahir Ozturk 0:1efa49a69ff8 1029 }
Mahir Ozturk 0:1efa49a69ff8 1030
Mahir Ozturk 0:1efa49a69ff8 1031 reg &= ~(1 << id);
Mahir Ozturk 0:1efa49a69ff8 1032
Mahir Ozturk 0:1efa49a69ff8 1033 ret = write_register(regmap->int_en_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1034 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1035 return ret;
Mahir Ozturk 0:1efa49a69ff8 1036 }
Mahir Ozturk 0:1efa49a69ff8 1037
Mahir Ozturk 0:1efa49a69ff8 1038 return 0;
Mahir Ozturk 0:1efa49a69ff8 1039 }
Mahir Ozturk 0:1efa49a69ff8 1040
Mahir Ozturk 0:1efa49a69ff8 1041 int RtcBase::irq_disable_all()
Mahir Ozturk 0:1efa49a69ff8 1042 {
Mahir Ozturk 0:1efa49a69ff8 1043 int ret;
Mahir Ozturk 0:1efa49a69ff8 1044 uint8_t reg = 0;
Mahir Ozturk 0:1efa49a69ff8 1045
Mahir Ozturk 0:1efa49a69ff8 1046 ret = write_register(regmap->int_en_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1047 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1048 return ret;
Mahir Ozturk 0:1efa49a69ff8 1049 }
Mahir Ozturk 0:1efa49a69ff8 1050
Mahir Ozturk 0:1efa49a69ff8 1051 return 0;
Mahir Ozturk 0:1efa49a69ff8 1052 }
Mahir Ozturk 0:1efa49a69ff8 1053
Mahir Ozturk 0:1efa49a69ff8 1054 void RtcBase::set_intr_handler(intr_id_t id, interrupt_handler_function func, void *cb)
Mahir Ozturk 0:1efa49a69ff8 1055 {
Mahir Ozturk 0:1efa49a69ff8 1056 interrupt_handler_list[id].func = func;
Mahir Ozturk 0:1efa49a69ff8 1057 interrupt_handler_list[id].cb = cb;
Mahir Ozturk 0:1efa49a69ff8 1058 }
Mahir Ozturk 0:1efa49a69ff8 1059
Mahir Ozturk 0:1efa49a69ff8 1060 void RtcBase::post_interrupt_work()
Mahir Ozturk 0:1efa49a69ff8 1061 {
Mahir Ozturk 0:1efa49a69ff8 1062 int ret;
Mahir Ozturk 0:1efa49a69ff8 1063 uint8_t reg, inten, mask;
Mahir Ozturk 0:1efa49a69ff8 1064
Mahir Ozturk 0:1efa49a69ff8 1065
Mahir Ozturk 0:1efa49a69ff8 1066 while (true) {
Mahir Ozturk 0:1efa49a69ff8 1067 Thread::signal_wait(POST_INTR_WORK_SIGNAL_ID);
Mahir Ozturk 0:1efa49a69ff8 1068
Mahir Ozturk 0:1efa49a69ff8 1069 ret = read_register(regmap->int_status_reg, &reg, 1);
Mahir Ozturk 0:1efa49a69ff8 1070 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1071 pr_err("Read interrupt status register failed!");
Mahir Ozturk 0:1efa49a69ff8 1072 }
Mahir Ozturk 0:1efa49a69ff8 1073
Mahir Ozturk 0:1efa49a69ff8 1074 ret = read_register(regmap->int_en_reg, &inten, 1);
Mahir Ozturk 0:1efa49a69ff8 1075 if (ret) {
Mahir Ozturk 0:1efa49a69ff8 1076 pr_err("Read interrupt enable register failed!");
Mahir Ozturk 0:1efa49a69ff8 1077 }
Mahir Ozturk 0:1efa49a69ff8 1078
Mahir Ozturk 0:1efa49a69ff8 1079 for (int i = 0; i < INTR_ID_END; i++) {
Mahir Ozturk 0:1efa49a69ff8 1080 mask = (1 << i);
Mahir Ozturk 0:1efa49a69ff8 1081 if ((reg & mask) && (inten & mask)) {
Mahir Ozturk 0:1efa49a69ff8 1082 if (interrupt_handler_list[i].func != NULL) {
Mahir Ozturk 0:1efa49a69ff8 1083 interrupt_handler_list[i].func(interrupt_handler_list[i].cb);
Mahir Ozturk 0:1efa49a69ff8 1084 }
Mahir Ozturk 0:1efa49a69ff8 1085 }
Mahir Ozturk 0:1efa49a69ff8 1086 }
Mahir Ozturk 0:1efa49a69ff8 1087 }
Mahir Ozturk 0:1efa49a69ff8 1088 }
Mahir Ozturk 0:1efa49a69ff8 1089
Mahir Ozturk 0:1efa49a69ff8 1090 void RtcBase::interrupt_handler()
Mahir Ozturk 0:1efa49a69ff8 1091 {
Mahir Ozturk 0:1efa49a69ff8 1092 post_intr_work_thread->signal_set(POST_INTR_WORK_SIGNAL_ID);
Mahir Ozturk 0:1efa49a69ff8 1093 }
Mahir Ozturk 0:1efa49a69ff8 1094
Mahir Ozturk 0:1efa49a69ff8 1095 int RtcBase::sw_reset_assert()
Mahir Ozturk 0:1efa49a69ff8 1096 {
Mahir Ozturk 0:1efa49a69ff8 1097 int ret;
Mahir Ozturk 0:1efa49a69ff8 1098 config_reg1_t config_reg1;
Mahir Ozturk 0:1efa49a69ff8 1099
Mahir Ozturk 0:1efa49a69ff8 1100 ret = read_register(regmap->config_reg1, (uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1101 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1102 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1103 return ret;
Mahir Ozturk 0:1efa49a69ff8 1104 }
Mahir Ozturk 0:1efa49a69ff8 1105
Mahir Ozturk 0:1efa49a69ff8 1106 config_reg1.bits.swrstn = 0; /* Put device in reset state */
Mahir Ozturk 0:1efa49a69ff8 1107
Mahir Ozturk 0:1efa49a69ff8 1108 ret = write_register(regmap->config_reg1, (const uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1109 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1110 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1111 return ret;
Mahir Ozturk 0:1efa49a69ff8 1112 }
Mahir Ozturk 0:1efa49a69ff8 1113
Mahir Ozturk 0:1efa49a69ff8 1114 return 0;
Mahir Ozturk 0:1efa49a69ff8 1115 }
Mahir Ozturk 0:1efa49a69ff8 1116
Mahir Ozturk 0:1efa49a69ff8 1117 int RtcBase::sw_reset_release()
Mahir Ozturk 0:1efa49a69ff8 1118 {
Mahir Ozturk 0:1efa49a69ff8 1119 int ret;
Mahir Ozturk 0:1efa49a69ff8 1120 config_reg1_t config_reg1;
Mahir Ozturk 0:1efa49a69ff8 1121
Mahir Ozturk 0:1efa49a69ff8 1122 ret = read_register(regmap->config_reg1, (uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1123 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1124 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1125 return ret;
Mahir Ozturk 0:1efa49a69ff8 1126 }
Mahir Ozturk 0:1efa49a69ff8 1127
Mahir Ozturk 0:1efa49a69ff8 1128 config_reg1.bits.swrstn = 1; /* Remove device from reset state */
Mahir Ozturk 0:1efa49a69ff8 1129
Mahir Ozturk 0:1efa49a69ff8 1130 ret = write_register(regmap->config_reg1, (const uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1131 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1132 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1133 return ret;
Mahir Ozturk 0:1efa49a69ff8 1134 }
Mahir Ozturk 0:1efa49a69ff8 1135
Mahir Ozturk 0:1efa49a69ff8 1136 return 0;
Mahir Ozturk 0:1efa49a69ff8 1137 }
Mahir Ozturk 0:1efa49a69ff8 1138
Mahir Ozturk 0:1efa49a69ff8 1139 int RtcBase::rtc_start()
Mahir Ozturk 0:1efa49a69ff8 1140 {
Mahir Ozturk 0:1efa49a69ff8 1141 int ret;
Mahir Ozturk 0:1efa49a69ff8 1142 config_reg1_t config_reg1;
Mahir Ozturk 0:1efa49a69ff8 1143
Mahir Ozturk 0:1efa49a69ff8 1144 ret = read_register(regmap->config_reg1, (uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1145 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1146 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1147 return ret;
Mahir Ozturk 0:1efa49a69ff8 1148 }
Mahir Ozturk 0:1efa49a69ff8 1149
Mahir Ozturk 0:1efa49a69ff8 1150 config_reg1.bits.osconz = 0; /* Enable the oscillator */
Mahir Ozturk 0:1efa49a69ff8 1151
Mahir Ozturk 0:1efa49a69ff8 1152 ret = write_register(regmap->config_reg1, (const uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1153 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1154 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1155 return ret;
Mahir Ozturk 0:1efa49a69ff8 1156 }
Mahir Ozturk 0:1efa49a69ff8 1157
Mahir Ozturk 0:1efa49a69ff8 1158 return 0;
Mahir Ozturk 0:1efa49a69ff8 1159 }
Mahir Ozturk 0:1efa49a69ff8 1160
Mahir Ozturk 0:1efa49a69ff8 1161 int RtcBase::rtc_stop()
Mahir Ozturk 0:1efa49a69ff8 1162 {
Mahir Ozturk 0:1efa49a69ff8 1163 int ret;
Mahir Ozturk 0:1efa49a69ff8 1164 config_reg1_t config_reg1;
Mahir Ozturk 0:1efa49a69ff8 1165
Mahir Ozturk 0:1efa49a69ff8 1166 ret = read_register(regmap->config_reg1, (uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1167 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1168 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1169 return ret;
Mahir Ozturk 0:1efa49a69ff8 1170 }
Mahir Ozturk 0:1efa49a69ff8 1171
Mahir Ozturk 0:1efa49a69ff8 1172 config_reg1.bits.osconz = 1; /* Disable the oscillator */
Mahir Ozturk 0:1efa49a69ff8 1173
Mahir Ozturk 0:1efa49a69ff8 1174 ret = write_register(regmap->config_reg1, (const uint8_t *) &config_reg1, 1);
Mahir Ozturk 0:1efa49a69ff8 1175 if (ret < 0) {
Mahir Ozturk 0:1efa49a69ff8 1176 pr_err("read_register failed!");
Mahir Ozturk 0:1efa49a69ff8 1177 return ret;
Mahir Ozturk 0:1efa49a69ff8 1178 }
Mahir Ozturk 0:1efa49a69ff8 1179
Mahir Ozturk 0:1efa49a69ff8 1180 return 0;
Mahir Ozturk 0:1efa49a69ff8 1181 }