Maxim Integrated / Mbed OS Smart_E_Load_MAXREFDES1213

Firmware for MAXREFDES1213

Dependencies:   max32630fthr USBDevice

MAX11311_Electronic_Load.h@9:29c618fec8fc, 2019-07-18 (annotated)

Committer:
venkik
Date:
Thu Jul 18 21:03:58 2019 +0000
Revision:
9:29c618fec8fc
Initial commit

Who changed what in which revision?

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venkik 9:29c618fec8fc 1 /*******************************************************************************
venkik 9:29c618fec8fc 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
venkik 9:29c618fec8fc 3 *
venkik 9:29c618fec8fc 4 * Permission is hereby granted, free of charge, to any person obtaining a
venkik 9:29c618fec8fc 5 * copy of this software and associated documentation files (the "Software"),
venkik 9:29c618fec8fc 6 * to deal in the Software without restriction, including without limitation
venkik 9:29c618fec8fc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
venkik 9:29c618fec8fc 8 * and/or sell copies of the Software, and to permit persons to whom the
venkik 9:29c618fec8fc 9 * Software is furnished to do so, subject to the following conditions:
venkik 9:29c618fec8fc 10 *
venkik 9:29c618fec8fc 11 * The above copyright notice and this permission notice shall be included
venkik 9:29c618fec8fc 12 * in all copies or substantial portions of the Software.
venkik 9:29c618fec8fc 13 *
venkik 9:29c618fec8fc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
venkik 9:29c618fec8fc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
venkik 9:29c618fec8fc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
venkik 9:29c618fec8fc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
venkik 9:29c618fec8fc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
venkik 9:29c618fec8fc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
venkik 9:29c618fec8fc 20 * OTHER DEALINGS IN THE SOFTWARE.
venkik 9:29c618fec8fc 21 *
venkik 9:29c618fec8fc 22 * Except as contained in this notice, the name of Maxim Integrated
venkik 9:29c618fec8fc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
venkik 9:29c618fec8fc 24 * Products, Inc. Branding Policy.
venkik 9:29c618fec8fc 25 *
venkik 9:29c618fec8fc 26 * The mere transfer of this software does not imply any licenses
venkik 9:29c618fec8fc 27 * of trade secrets, proprietary technology, copyrights, patents,
venkik 9:29c618fec8fc 28 * trademarks, maskwork rights, or any other form of intellectual
venkik 9:29c618fec8fc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
venkik 9:29c618fec8fc 30 * ownership rights.
venkik 9:29c618fec8fc 31 *******************************************************************************
venkik 9:29c618fec8fc 32 */
venkik 9:29c618fec8fc 33 /// Generated by: MAX11300/01/11/12 Configuration Software (Ver. 1.1.0.5) 13/03/2019 12:16
venkik 9:29c618fec8fc 34 /// Description: Electronic load
venkik 9:29c618fec8fc 35 /// Port P0: Differential in+ for measuring the source voltage
venkik 9:29c618fec8fc 36 /// Port P1: Differential in- for measuring the source voltage
venkik 9:29c618fec8fc 37 /// Port P2: ADC for measuring the low current
venkik 9:29c618fec8fc 38 /// Port P3: DAC for setting the low current
venkik 9:29c618fec8fc 39 /// Port P4: Input for dynamic current control
venkik 9:29c618fec8fc 40 /// Port P5: DAC for setting the high current
venkik 9:29c618fec8fc 41 /// Port P6: ADC for measuring the low current
venkik 9:29c618fec8fc 42 /// Port P7: Not used
venkik 9:29c618fec8fc 43 /// Port P8: Not used
venkik 9:29c618fec8fc 44 /// Port P9: Clamp for lower limit curve
venkik 9:29c618fec8fc 45 /// Port P10: Clamp for higher limit curve
venkik 9:29c618fec8fc 46 /// Port P11: DAC for driving ramp generator
venkik 9:29c618fec8fc 47 /// Notes: Optional: Enter design notes here
venkik 9:29c618fec8fc 48
venkik 9:29c618fec8fc 49 #ifndef _MAX11311_DESIGNVALUE_H_
venkik 9:29c618fec8fc 50 #define _MAX11311_DESIGNVALUE_H_
venkik 9:29c618fec8fc 51
venkik 9:29c618fec8fc 52 /// Supply voltage on AVSSIO
venkik 9:29c618fec8fc 53 #define MAX11300_AVSSIO_VOLTAGE -7
venkik 9:29c618fec8fc 54
venkik 9:29c618fec8fc 55 /// Supply voltage on AVDDIO
venkik 9:29c618fec8fc 56 #define MAX11300_AVDDIO_VOLTAGE 12
venkik 9:29c618fec8fc 57
venkik 9:29c618fec8fc 58 /// Supply voltage on DVDD
venkik 9:29c618fec8fc 59 #define MAX11300_DVDD_VOLTAGE 1.8
venkik 9:29c618fec8fc 60
venkik 9:29c618fec8fc 61 /// Supply voltage on AVDD
venkik 9:29c618fec8fc 62 #define MAX11300_AVDD_VOLTAGE 5
venkik 9:29c618fec8fc 63
venkik 9:29c618fec8fc 64 /// Supply voltage on DAC_REF
venkik 9:29c618fec8fc 65 #define MAX11300_DAC_REF_VOLTAGE 2.5
venkik 9:29c618fec8fc 66
venkik 9:29c618fec8fc 67 /// Supply voltage on ADC_EXT_REF
venkik 9:29c618fec8fc 68 #define MAX11300_ADC_EXT_REF_VOLTAGE 2.5
venkik 9:29c618fec8fc 69
venkik 9:29c618fec8fc 70 /// SPI first byte when writing MAX11300 (7-bit address in bits 0x7E; LSB=0 for write)
venkik 9:29c618fec8fc 71 #define MAX11311Addr_SPI_Write(RegAddr) ( (RegAddr << 1) )
venkik 9:29c618fec8fc 72
venkik 9:29c618fec8fc 73 /// SPI first byte when reading MAX11300 (7-bit address in bits 0x7E; LSB=1 for read)
venkik 9:29c618fec8fc 74 #define MAX11311Addr_SPI_Read(RegAddr) ( (RegAddr << 1) | 1 )
venkik 9:29c618fec8fc 75
venkik 9:29c618fec8fc 76 /// MAX11300EVKIT Register Addresses
venkik 9:29c618fec8fc 77 typedef enum MAX11311RegAddressEnum {
venkik 9:29c618fec8fc 78
venkik 9:29c618fec8fc 79 /// 0x00 r/o dev_id Device Identification
venkik 9:29c618fec8fc 80 dev_id = 0x00,
venkik 9:29c618fec8fc 81
venkik 9:29c618fec8fc 82 /// 0x01 r/o interrupt_flag Interrupt flags
venkik 9:29c618fec8fc 83 interrupt_flag = 0x01,
venkik 9:29c618fec8fc 84
venkik 9:29c618fec8fc 85 /// 0x02 r/o adc_status_P10P6_P5P0 new ADC data available
venkik 9:29c618fec8fc 86 adc_status_P10P6_P5P0 = 0x02,
venkik 9:29c618fec8fc 87
venkik 9:29c618fec8fc 88 /// 0x03 r/o adc_status_P11 new ADC data available
venkik 9:29c618fec8fc 89 adc_status_P11 = 0x03,
venkik 9:29c618fec8fc 90
venkik 9:29c618fec8fc 91 /// 0x04 r/o dac_oi_status_P10P6_P5P0 DAC Overcurrent Interrupt
venkik 9:29c618fec8fc 92 dac_oi_status_P10P6_P5P0 = 0x04,
venkik 9:29c618fec8fc 93
venkik 9:29c618fec8fc 94 /// 0x05 r/o dac_oi_status_P11 DAC Overcurrent Interrupt
venkik 9:29c618fec8fc 95 dac_oi_status_P11 = 0x05,
venkik 9:29c618fec8fc 96
venkik 9:29c618fec8fc 97 /// 0x06 r/o gpi_status_P10P6_P5P0 GPI event ready
venkik 9:29c618fec8fc 98 gpi_status_P10P6_P5P0 = 0x06,
venkik 9:29c618fec8fc 99
venkik 9:29c618fec8fc 100 /// 0x07 r/o gpi_status_P11 GPI event ready
venkik 9:29c618fec8fc 101 gpi_status_P11 = 0x07,
venkik 9:29c618fec8fc 102
venkik 9:29c618fec8fc 103 /// 0x08 r/o tmp_int_data Internal Temeprature
venkik 9:29c618fec8fc 104 tmp_int_data = 0x08,
venkik 9:29c618fec8fc 105
venkik 9:29c618fec8fc 106 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N
venkik 9:29c618fec8fc 107 tmp_ext1_data = 0x09,
venkik 9:29c618fec8fc 108
venkik 9:29c618fec8fc 109 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N
venkik 9:29c618fec8fc 110 tmp_ext2_data = 0x0a,
venkik 9:29c618fec8fc 111
venkik 9:29c618fec8fc 112 /// 0x0b r/o gpi_data_P10P6_P5P0 GPI input ports data
venkik 9:29c618fec8fc 113 gpi_data_P10P6_P5P0 = 0x0b,
venkik 9:29c618fec8fc 114
venkik 9:29c618fec8fc 115 /// 0x0c r/o gpi_data_P11 GPI input ports data
venkik 9:29c618fec8fc 116 gpi_data_P11 = 0x0c,
venkik 9:29c618fec8fc 117
venkik 9:29c618fec8fc 118 /// 0x0d r/w gpo_data_P10P6_P5P0 GPO output ports data
venkik 9:29c618fec8fc 119 gpo_data_P10P6_P5P0 = 0x0d,
venkik 9:29c618fec8fc 120
venkik 9:29c618fec8fc 121 /// 0x0e r/w gpo_data_P11 GPO output ports data
venkik 9:29c618fec8fc 122 gpo_data_P11 = 0x0e,
venkik 9:29c618fec8fc 123
venkik 9:29c618fec8fc 124 /// 0x0f r/o reserved_0F reserved
venkik 9:29c618fec8fc 125 reserved_0F = 0x0f,
venkik 9:29c618fec8fc 126
venkik 9:29c618fec8fc 127 /// 0x10 r/w device_control Global device control register
venkik 9:29c618fec8fc 128 device_control = 0x10,
venkik 9:29c618fec8fc 129
venkik 9:29c618fec8fc 130 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source)
venkik 9:29c618fec8fc 131 interrupt_mask = 0x11,
venkik 9:29c618fec8fc 132
venkik 9:29c618fec8fc 133 /// 0x12 r/w gpi_irqmode_P5_P0 GPI ports P5 to P0 mode register
venkik 9:29c618fec8fc 134 gpi_irqmode_P5_P0 = 0x12,
venkik 9:29c618fec8fc 135
venkik 9:29c618fec8fc 136 /// 0x13 r/w gpi_irqmode_P10_P6 GPI ports P10 to P6 mode register
venkik 9:29c618fec8fc 137 gpi_irqmode_P10_P6 = 0x13,
venkik 9:29c618fec8fc 138
venkik 9:29c618fec8fc 139 /// 0x14 r/w gpi_irqmode_P11 GPI port P11 mode register
venkik 9:29c618fec8fc 140 gpi_irqmode_P11 = 0x14,
venkik 9:29c618fec8fc 141
venkik 9:29c618fec8fc 142 /// 0x15 r/w reserved_15 (reserved)
venkik 9:29c618fec8fc 143 reserved_15 = 0x15,
venkik 9:29c618fec8fc 144
venkik 9:29c618fec8fc 145 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/>
venkik 9:29c618fec8fc 146 dac_preset_data_1 = 0x16,
venkik 9:29c618fec8fc 147
venkik 9:29c618fec8fc 148 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/>
venkik 9:29c618fec8fc 149 dac_preset_data_2 = 0x17,
venkik 9:29c618fec8fc 150
venkik 9:29c618fec8fc 151 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration
venkik 9:29c618fec8fc 152 tmp_mon_cfg = 0x18,
venkik 9:29c618fec8fc 153
venkik 9:29c618fec8fc 154 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold
venkik 9:29c618fec8fc 155 tmp_mon_int_hi_thresh = 0x19,
venkik 9:29c618fec8fc 156
venkik 9:29c618fec8fc 157 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold
venkik 9:29c618fec8fc 158 tmp_mon_int_lo_thresh = 0x1a,
venkik 9:29c618fec8fc 159
venkik 9:29c618fec8fc 160 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold
venkik 9:29c618fec8fc 161 tmp_mon_ext1_hi_thresh = 0x1b,
venkik 9:29c618fec8fc 162
venkik 9:29c618fec8fc 163 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold
venkik 9:29c618fec8fc 164 tmp_mon_ext1_lo_thresh = 0x1c,
venkik 9:29c618fec8fc 165
venkik 9:29c618fec8fc 166 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold
venkik 9:29c618fec8fc 167 tmp_mon_ext2_hi_thresh = 0x1d,
venkik 9:29c618fec8fc 168
venkik 9:29c618fec8fc 169 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold
venkik 9:29c618fec8fc 170 tmp_mon_ext2_lo_thresh = 0x1e,
venkik 9:29c618fec8fc 171
venkik 9:29c618fec8fc 172 /// 0x1f r/w reserved_1F reserved
venkik 9:29c618fec8fc 173 reserved_1F = 0x1f,
venkik 9:29c618fec8fc 174
venkik 9:29c618fec8fc 175 /// 0x20 r/w reserved_20 (reserved) configuration register
venkik 9:29c618fec8fc 176 reserved_20 = 0x20,
venkik 9:29c618fec8fc 177
venkik 9:29c618fec8fc 178 /// 0x21 r/w reserved_21 (reserved) configuration register
venkik 9:29c618fec8fc 179 reserved_21 = 0x21,
venkik 9:29c618fec8fc 180
venkik 9:29c618fec8fc 181 /// 0x22 r/w port_cfg_p0 PIXI port P0 configuration register
venkik 9:29c618fec8fc 182 port_cfg_p0 = 0x22,
venkik 9:29c618fec8fc 183
venkik 9:29c618fec8fc 184 /// 0x23 r/w port_cfg_p1 PIXI port P1 configuration register
venkik 9:29c618fec8fc 185 port_cfg_p1 = 0x23,
venkik 9:29c618fec8fc 186
venkik 9:29c618fec8fc 187 /// 0x24 r/w port_cfg_p2 PIXI port P2 configuration register
venkik 9:29c618fec8fc 188 port_cfg_p2 = 0x24,
venkik 9:29c618fec8fc 189
venkik 9:29c618fec8fc 190 /// 0x25 r/w port_cfg_p3 PIXI port P3 configuration register
venkik 9:29c618fec8fc 191 port_cfg_p3 = 0x25,
venkik 9:29c618fec8fc 192
venkik 9:29c618fec8fc 193 /// 0x26 r/w port_cfg_p4 PIXI port P4 configuration register
venkik 9:29c618fec8fc 194 port_cfg_p4 = 0x26,
venkik 9:29c618fec8fc 195
venkik 9:29c618fec8fc 196 /// 0x27 r/w port_cfg_p5 PIXI port P5 configuration register
venkik 9:29c618fec8fc 197 port_cfg_p5 = 0x27,
venkik 9:29c618fec8fc 198
venkik 9:29c618fec8fc 199 /// 0x28 r/w reserved_28 (reserved) configuration register
venkik 9:29c618fec8fc 200 reserved_28 = 0x28,
venkik 9:29c618fec8fc 201
venkik 9:29c618fec8fc 202 /// 0x29 r/w reserved_29 (reserved) configuration register
venkik 9:29c618fec8fc 203 reserved_29 = 0x29,
venkik 9:29c618fec8fc 204
venkik 9:29c618fec8fc 205 /// 0x2a r/w reserved_2A (reserved) configuration register
venkik 9:29c618fec8fc 206 reserved_2A = 0x2a,
venkik 9:29c618fec8fc 207
venkik 9:29c618fec8fc 208 /// 0x2b r/w port_cfg_p6 PIXI port P6 configuration register
venkik 9:29c618fec8fc 209 port_cfg_p6 = 0x2b,
venkik 9:29c618fec8fc 210
venkik 9:29c618fec8fc 211 /// 0x2c r/w port_cfg_p7 PIXI port P7 configuration register
venkik 9:29c618fec8fc 212 port_cfg_p7 = 0x2c,
venkik 9:29c618fec8fc 213
venkik 9:29c618fec8fc 214 /// 0x2d r/w port_cfg_p8 PIXI port P8 configuration register
venkik 9:29c618fec8fc 215 port_cfg_p8 = 0x2d,
venkik 9:29c618fec8fc 216
venkik 9:29c618fec8fc 217 /// 0x2e r/w port_cfg_p9 PIXI port P9 configuration register
venkik 9:29c618fec8fc 218 port_cfg_p9 = 0x2e,
venkik 9:29c618fec8fc 219
venkik 9:29c618fec8fc 220 /// 0x2f r/w port_cfg_p10 PIXI port P10 configuration register
venkik 9:29c618fec8fc 221 port_cfg_p10 = 0x2f,
venkik 9:29c618fec8fc 222
venkik 9:29c618fec8fc 223 /// 0x30 r/w port_cfg_p11 PIXI port P11 configuration register
venkik 9:29c618fec8fc 224 port_cfg_p11 = 0x30,
venkik 9:29c618fec8fc 225
venkik 9:29c618fec8fc 226 /// 0x31 r/w reserved_31 (reserved) configuration register
venkik 9:29c618fec8fc 227 reserved_31 = 0x31,
venkik 9:29c618fec8fc 228
venkik 9:29c618fec8fc 229 /// 0x32 r/w reserved_32 (reserved) configuration register
venkik 9:29c618fec8fc 230 reserved_32 = 0x32,
venkik 9:29c618fec8fc 231
venkik 9:29c618fec8fc 232 /// 0x33 r/w reserved_33 (reserved) configuration register
venkik 9:29c618fec8fc 233 reserved_33 = 0x33,
venkik 9:29c618fec8fc 234
venkik 9:29c618fec8fc 235 /// 0x40 r/o reserved_40 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 236 reserved_40 = 0x40,
venkik 9:29c618fec8fc 237
venkik 9:29c618fec8fc 238 /// 0x41 r/o reserved_41 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 239 reserved_41 = 0x41,
venkik 9:29c618fec8fc 240
venkik 9:29c618fec8fc 241 /// 0x42 r/o adc_data_port_p0 PIXI port P0 Analog to Digital Converter register
venkik 9:29c618fec8fc 242 adc_data_port_p0 = 0x42,
venkik 9:29c618fec8fc 243
venkik 9:29c618fec8fc 244 /// 0x43 r/o adc_data_port_p1 PIXI port P1 Analog to Digital Converter register
venkik 9:29c618fec8fc 245 adc_data_port_p1 = 0x43,
venkik 9:29c618fec8fc 246
venkik 9:29c618fec8fc 247 /// 0x44 r/o adc_data_port_p2 PIXI port P2 Analog to Digital Converter register
venkik 9:29c618fec8fc 248 adc_data_port_p2 = 0x44,
venkik 9:29c618fec8fc 249
venkik 9:29c618fec8fc 250 /// 0x45 r/o adc_data_port_p3 PIXI port P3 Analog to Digital Converter register
venkik 9:29c618fec8fc 251 adc_data_port_p3 = 0x45,
venkik 9:29c618fec8fc 252
venkik 9:29c618fec8fc 253 /// 0x46 r/o adc_data_port_p4 PIXI port P4 Analog to Digital Converter register
venkik 9:29c618fec8fc 254 adc_data_port_p4 = 0x46,
venkik 9:29c618fec8fc 255
venkik 9:29c618fec8fc 256 /// 0x47 r/o adc_data_port_p5 PIXI port P5 Analog to Digital Converter register
venkik 9:29c618fec8fc 257 adc_data_port_p5 = 0x47,
venkik 9:29c618fec8fc 258
venkik 9:29c618fec8fc 259 /// 0x48 r/o reserved_48 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 260 reserved_48 = 0x48,
venkik 9:29c618fec8fc 261
venkik 9:29c618fec8fc 262 /// 0x49 r/o reserved_49 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 263 reserved_49 = 0x49,
venkik 9:29c618fec8fc 264
venkik 9:29c618fec8fc 265 /// 0x4a r/o reserved_4A (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 266 reserved_4A = 0x4a,
venkik 9:29c618fec8fc 267
venkik 9:29c618fec8fc 268 /// 0x4b r/o adc_data_port_p6 PIXI port P6 Analog to Digital Converter register
venkik 9:29c618fec8fc 269 adc_data_port_p6 = 0x4b,
venkik 9:29c618fec8fc 270
venkik 9:29c618fec8fc 271 /// 0x4c r/o adc_data_port_p7 PIXI port P7 Analog to Digital Converter register
venkik 9:29c618fec8fc 272 adc_data_port_p7 = 0x4c,
venkik 9:29c618fec8fc 273
venkik 9:29c618fec8fc 274 /// 0x4d r/o adc_data_port_p8 PIXI port P8 Analog to Digital Converter register
venkik 9:29c618fec8fc 275 adc_data_port_p8 = 0x4d,
venkik 9:29c618fec8fc 276
venkik 9:29c618fec8fc 277 /// 0x4e r/o adc_data_port_p9 PIXI port P9 Analog to Digital Converter register
venkik 9:29c618fec8fc 278 adc_data_port_p9 = 0x4e,
venkik 9:29c618fec8fc 279
venkik 9:29c618fec8fc 280 /// 0x4f r/o adc_data_port_p10 PIXI port P10 Analog to Digital Converter register
venkik 9:29c618fec8fc 281 adc_data_port_p10 = 0x4f,
venkik 9:29c618fec8fc 282
venkik 9:29c618fec8fc 283 /// 0x50 r/o adc_data_port_p11 PIXI port P11 Analog to Digital Converter register
venkik 9:29c618fec8fc 284 adc_data_port_p11 = 0x50,
venkik 9:29c618fec8fc 285
venkik 9:29c618fec8fc 286 /// 0x51 r/o reserved_51 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 287 reserved_51 = 0x51,
venkik 9:29c618fec8fc 288
venkik 9:29c618fec8fc 289 /// 0x52 r/o reserved_52 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 290 reserved_52 = 0x52,
venkik 9:29c618fec8fc 291
venkik 9:29c618fec8fc 292 /// 0x53 r/o reserved_53 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 293 reserved_53 = 0x53,
venkik 9:29c618fec8fc 294
venkik 9:29c618fec8fc 295 /// 0x60 r/w reserved_60 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 296 reserved_60 = 0x60,
venkik 9:29c618fec8fc 297
venkik 9:29c618fec8fc 298 /// 0x61 r/w reserved_61 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 299 reserved_61 = 0x61,
venkik 9:29c618fec8fc 300
venkik 9:29c618fec8fc 301 /// 0x62 r/w dac_data_port_p0 PIXI port P0 Digital to Analog Converter register
venkik 9:29c618fec8fc 302 dac_data_port_p0 = 0x62,
venkik 9:29c618fec8fc 303
venkik 9:29c618fec8fc 304 /// 0x63 r/w dac_data_port_p1 PIXI port P1 Digital to Analog Converter register
venkik 9:29c618fec8fc 305 dac_data_port_p1 = 0x63,
venkik 9:29c618fec8fc 306
venkik 9:29c618fec8fc 307 /// 0x64 r/w dac_data_port_p2 PIXI port P2 Digital to Analog Converter register
venkik 9:29c618fec8fc 308 dac_data_port_p2 = 0x64,
venkik 9:29c618fec8fc 309
venkik 9:29c618fec8fc 310 /// 0x65 r/w dac_data_port_p3 PIXI port P3 Digital to Analog Converter register
venkik 9:29c618fec8fc 311 dac_data_port_p3 = 0x65,
venkik 9:29c618fec8fc 312
venkik 9:29c618fec8fc 313 /// 0x66 r/w dac_data_port_p4 PIXI port P4 Digital to Analog Converter register
venkik 9:29c618fec8fc 314 dac_data_port_p4 = 0x66,
venkik 9:29c618fec8fc 315
venkik 9:29c618fec8fc 316 /// 0x67 r/w dac_data_port_p5 PIXI port P5 Digital to Analog Converter register
venkik 9:29c618fec8fc 317 dac_data_port_p5 = 0x67,
venkik 9:29c618fec8fc 318
venkik 9:29c618fec8fc 319 /// 0x68 r/w reserved_68 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 320 reserved_68 = 0x68,
venkik 9:29c618fec8fc 321
venkik 9:29c618fec8fc 322 /// 0x69 r/w reserved_69 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 323 reserved_69 = 0x69,
venkik 9:29c618fec8fc 324
venkik 9:29c618fec8fc 325 /// 0x6a r/w reserved_6A (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 326 reserved_6A = 0x6a,
venkik 9:29c618fec8fc 327
venkik 9:29c618fec8fc 328 /// 0x6b r/w dac_data_port_p6 PIXI port P6 Digital to Analog Converter register
venkik 9:29c618fec8fc 329 dac_data_port_p6 = 0x6b,
venkik 9:29c618fec8fc 330
venkik 9:29c618fec8fc 331 /// 0x6c r/w dac_data_port_p7 PIXI port P7 Digital to Analog Converter register
venkik 9:29c618fec8fc 332 dac_data_port_p7 = 0x6c,
venkik 9:29c618fec8fc 333
venkik 9:29c618fec8fc 334 /// 0x6d r/w dac_data_port_p8 PIXI port P8 Digital to Analog Converter register
venkik 9:29c618fec8fc 335 dac_data_port_p8 = 0x6d,
venkik 9:29c618fec8fc 336
venkik 9:29c618fec8fc 337 /// 0x6e r/w dac_data_port_p9 PIXI port P9 Digital to Analog Converter register
venkik 9:29c618fec8fc 338 dac_data_port_p9 = 0x6e,
venkik 9:29c618fec8fc 339
venkik 9:29c618fec8fc 340 /// 0x6f r/w dac_data_port_p10 PIXI port P10 Digital to Analog Converter register
venkik 9:29c618fec8fc 341 dac_data_port_p10 = 0x6f,
venkik 9:29c618fec8fc 342
venkik 9:29c618fec8fc 343 /// 0x70 r/w dac_data_port_p11 PIXI port P11 Digital to Analog Converter register
venkik 9:29c618fec8fc 344 dac_data_port_p11 = 0x70,
venkik 9:29c618fec8fc 345
venkik 9:29c618fec8fc 346 /// 0x71 r/w reserved_71 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 347 reserved_71 = 0x71,
venkik 9:29c618fec8fc 348
venkik 9:29c618fec8fc 349 /// 0x72 r/w reserved_72 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 350 reserved_72 = 0x72,
venkik 9:29c618fec8fc 351
venkik 9:29c618fec8fc 352 /// 0x73 r/w reserved_73 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 353 reserved_73 = 0x73,
venkik 9:29c618fec8fc 354
venkik 9:29c618fec8fc 355 } MAX11311RegAddress_t;
venkik 9:29c618fec8fc 356
venkik 9:29c618fec8fc 357 /// 0x00 r/o dev_id Device Identification
venkik 9:29c618fec8fc 358 /// <code>1111xxxxxxxxxxxx</code> PART Part field
venkik 9:29c618fec8fc 359 /// <code>xxxx11xxxxxxxxxx</code> REV Revision
venkik 9:29c618fec8fc 360 /// <code>xxxxxx11xxxxxxxx</code> IFMODE Inteface Mode
venkik 9:29c618fec8fc 361 /// <code>xxxxxxxx11xxxxxx</code> IFSP Inteface Speed
venkik 9:29c618fec8fc 362 /// <code>xxxxxxxxxx11xxxx</code> NBRPRTS Number of ports
venkik 9:29c618fec8fc 363 /// <code>xxxxxxxxxxxx11xx</code> RES Resolution
venkik 9:29c618fec8fc 364 /// <code>xxxxxxxxxxxxxx11</code> VRNG Voltage Range
venkik 9:29c618fec8fc 365 #define dev_id_PART 0xf000
venkik 9:29c618fec8fc 366 #define dev_id_REV 0x0c00
venkik 9:29c618fec8fc 367 #define dev_id_IFMODE 0x0300
venkik 9:29c618fec8fc 368 #define dev_id_IFSP 0x00c0
venkik 9:29c618fec8fc 369 #define dev_id_NBRPRTS 0x0030
venkik 9:29c618fec8fc 370 #define dev_id_RES 0x000c
venkik 9:29c618fec8fc 371 #define dev_id_VRNG 0x0003
venkik 9:29c618fec8fc 372
venkik 9:29c618fec8fc 373 /// 0x01 r/o interrupt_flag Interrupt flags
venkik 9:29c618fec8fc 374 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor
venkik 9:29c618fec8fc 375 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot
venkik 9:29c618fec8fc 376 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold
venkik 9:29c618fec8fc 377 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New
venkik 9:29c618fec8fc 378 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot
venkik 9:29c618fec8fc 379 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold
venkik 9:29c618fec8fc 380 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New
venkik 9:29c618fec8fc 381 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot
venkik 9:29c618fec8fc 382 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold
venkik 9:29c618fec8fc 383 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New
venkik 9:29c618fec8fc 384 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current
venkik 9:29c618fec8fc 385 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed
venkik 9:29c618fec8fc 386 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready
venkik 9:29c618fec8fc 387 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed
venkik 9:29c618fec8fc 388 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready
venkik 9:29c618fec8fc 389 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete
venkik 9:29c618fec8fc 390 #define interrupt_flag_VMON 0x8000
venkik 9:29c618fec8fc 391 #define interrupt_flag_TMPEXT2HOT 0x4000
venkik 9:29c618fec8fc 392 #define interrupt_flag_TMPEXT2COLD 0x2000
venkik 9:29c618fec8fc 393 #define interrupt_flag_TMPEXT2NEW 0x1000
venkik 9:29c618fec8fc 394 #define interrupt_flag_TMPEXT1HOT 0x0800
venkik 9:29c618fec8fc 395 #define interrupt_flag_TMPEXT1COLD 0x0400
venkik 9:29c618fec8fc 396 #define interrupt_flag_TMPEXT1NEW 0x0200
venkik 9:29c618fec8fc 397 #define interrupt_flag_TMPINTHOT 0x0100
venkik 9:29c618fec8fc 398 #define interrupt_flag_TMPINTCOLD 0x0080
venkik 9:29c618fec8fc 399 #define interrupt_flag_TMPINTNEW 0x0040
venkik 9:29c618fec8fc 400 #define interrupt_flag_DACOI 0x0020
venkik 9:29c618fec8fc 401 #define interrupt_flag_GPIDM 0x0010
venkik 9:29c618fec8fc 402 #define interrupt_flag_GPIDR 0x0008
venkik 9:29c618fec8fc 403 #define interrupt_flag_ADCDM 0x0004
venkik 9:29c618fec8fc 404 #define interrupt_flag_ADCDR 0x0002
venkik 9:29c618fec8fc 405 #define interrupt_flag_ADCFLAG 0x0001
venkik 9:29c618fec8fc 406
venkik 9:29c618fec8fc 407 /// 0x02 r/o adc_status_P10P6_P5P0 new ADC data available
venkik 9:29c618fec8fc 408 /// <code>1xxxxxxxxxxxxxxx</code> ADCSTp10 ADCST[P10] new <see cref="adc_data_port_p10"/>
venkik 9:29c618fec8fc 409 /// <code>x1xxxxxxxxxxxxxx</code> ADCSTp09 ADCST[P9] new <see cref="adc_data_port_p9"/>
venkik 9:29c618fec8fc 410 /// <code>xx1xxxxxxxxxxxxx</code> ADCSTp08 ADCST[P8] new <see cref="adc_data_port_p8"/>
venkik 9:29c618fec8fc 411 /// <code>xxx1xxxxxxxxxxxx</code> ADCSTp07 ADCST[P7] new <see cref="adc_data_port_p7"/>
venkik 9:29c618fec8fc 412 /// <code>xxxx1xxxxxxxxxxx</code> ADCSTp06 ADCST[P6] new <see cref="adc_data_port_p6"/>
venkik 9:29c618fec8fc 413 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_10 new <see cref="reserved_4A"/>
venkik 9:29c618fec8fc 414 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_09 new <see cref="reserved_49"/>
venkik 9:29c618fec8fc 415 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_08 new <see cref="reserved_48"/>
venkik 9:29c618fec8fc 416 /// <code>xxxxxxxx1xxxxxxx</code> ADCSTp05 ADCST[P5] new <see cref="adc_data_port_p5"/>
venkik 9:29c618fec8fc 417 /// <code>xxxxxxxxx1xxxxxx</code> ADCSTp04 ADCST[P4] new <see cref="adc_data_port_p4"/>
venkik 9:29c618fec8fc 418 /// <code>xxxxxxxxxx1xxxxx</code> ADCSTp03 ADCST[P3] new <see cref="adc_data_port_p3"/>
venkik 9:29c618fec8fc 419 /// <code>xxxxxxxxxxx1xxxx</code> ADCSTp02 ADCST[P2] new <see cref="adc_data_port_p2"/>
venkik 9:29c618fec8fc 420 /// <code>xxxxxxxxxxxx1xxx</code> ADCSTp01 ADCST[P1] new <see cref="adc_data_port_p1"/>
venkik 9:29c618fec8fc 421 /// <code>xxxxxxxxxxxxx1xx</code> ADCSTp00 ADCST[P0] new <see cref="adc_data_port_p0"/>
venkik 9:29c618fec8fc 422 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_01 new <see cref="reserved_41"/>
venkik 9:29c618fec8fc 423 /// <code>xxxxxxxxxxxxxxx1</code> RESERVED_00 new <see cref="reserved_40"/>
venkik 9:29c618fec8fc 424 #define adc_status_P10P6_P5P0_ADCSTp10 0x8000
venkik 9:29c618fec8fc 425 #define adc_status_P10P6_P5P0_ADCSTp09 0x4000
venkik 9:29c618fec8fc 426 #define adc_status_P10P6_P5P0_ADCSTp08 0x2000
venkik 9:29c618fec8fc 427 #define adc_status_P10P6_P5P0_ADCSTp07 0x1000
venkik 9:29c618fec8fc 428 #define adc_status_P10P6_P5P0_ADCSTp06 0x0800
venkik 9:29c618fec8fc 429 #define adc_status_P10P6_P5P0_RESERVED_10 0x0400
venkik 9:29c618fec8fc 430 #define adc_status_P10P6_P5P0_RESERVED_09 0x0200
venkik 9:29c618fec8fc 431 #define adc_status_P10P6_P5P0_RESERVED_08 0x0100
venkik 9:29c618fec8fc 432 #define adc_status_P10P6_P5P0_ADCSTp05 0x0080
venkik 9:29c618fec8fc 433 #define adc_status_P10P6_P5P0_ADCSTp04 0x0040
venkik 9:29c618fec8fc 434 #define adc_status_P10P6_P5P0_ADCSTp03 0x0020
venkik 9:29c618fec8fc 435 #define adc_status_P10P6_P5P0_ADCSTp02 0x0010
venkik 9:29c618fec8fc 436 #define adc_status_P10P6_P5P0_ADCSTp01 0x0008
venkik 9:29c618fec8fc 437 #define adc_status_P10P6_P5P0_ADCSTp00 0x0004
venkik 9:29c618fec8fc 438 #define adc_status_P10P6_P5P0_RESERVED_01 0x0002
venkik 9:29c618fec8fc 439 #define adc_status_P10P6_P5P0_RESERVED_00 0x0001
venkik 9:29c618fec8fc 440
venkik 9:29c618fec8fc 441 /// 0x03 r/o adc_status_P11 new ADC data available
venkik 9:29c618fec8fc 442 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_31 new <see cref="adc_data_port_31"/>
venkik 9:29c618fec8fc 443 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_30 new <see cref="adc_data_port_30"/>
venkik 9:29c618fec8fc 444 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_29 new <see cref="adc_data_port_29"/>
venkik 9:29c618fec8fc 445 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_28 new <see cref="adc_data_port_28"/>
venkik 9:29c618fec8fc 446 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_27 new <see cref="adc_data_port_27"/>
venkik 9:29c618fec8fc 447 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_26 new <see cref="adc_data_port_26"/>
venkik 9:29c618fec8fc 448 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_25 new <see cref="adc_data_port_25"/>
venkik 9:29c618fec8fc 449 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_24 new <see cref="adc_data_port_24"/>
venkik 9:29c618fec8fc 450 /// <code>xxxxxxxx1xxxxxxx</code> RESERVED_23 new <see cref="adc_data_port_23"/>
venkik 9:29c618fec8fc 451 /// <code>xxxxxxxxx1xxxxxx</code> RESERVED_22 new <see cref="adc_data_port_22"/>
venkik 9:29c618fec8fc 452 /// <code>xxxxxxxxxx1xxxxx</code> RESERVED_21 new <see cref="adc_data_port_21"/>
venkik 9:29c618fec8fc 453 /// <code>xxxxxxxxxxx1xxxx</code> RESERVED_20 new <see cref="adc_data_port_20"/>
venkik 9:29c618fec8fc 454 /// <code>xxxxxxxxxxxx1xxx</code> RESERVED_19 new <see cref="reserved_53"/>
venkik 9:29c618fec8fc 455 /// <code>xxxxxxxxxxxxx1xx</code> RESERVED_18 new <see cref="reserved_52"/>
venkik 9:29c618fec8fc 456 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_17 new <see cref="reserved_51"/>
venkik 9:29c618fec8fc 457 /// <code>xxxxxxxxxxxxxxx1</code> ADCSTp11 ADCST[P11] new <see cref="adc_data_port_p11"/>
venkik 9:29c618fec8fc 458 #define adc_status_P11_RESERVED_31 0x8000
venkik 9:29c618fec8fc 459 #define adc_status_P11_RESERVED_30 0x4000
venkik 9:29c618fec8fc 460 #define adc_status_P11_RESERVED_29 0x2000
venkik 9:29c618fec8fc 461 #define adc_status_P11_RESERVED_28 0x1000
venkik 9:29c618fec8fc 462 #define adc_status_P11_RESERVED_27 0x0800
venkik 9:29c618fec8fc 463 #define adc_status_P11_RESERVED_26 0x0400
venkik 9:29c618fec8fc 464 #define adc_status_P11_RESERVED_25 0x0200
venkik 9:29c618fec8fc 465 #define adc_status_P11_RESERVED_24 0x0100
venkik 9:29c618fec8fc 466 #define adc_status_P11_RESERVED_23 0x0080
venkik 9:29c618fec8fc 467 #define adc_status_P11_RESERVED_22 0x0040
venkik 9:29c618fec8fc 468 #define adc_status_P11_RESERVED_21 0x0020
venkik 9:29c618fec8fc 469 #define adc_status_P11_RESERVED_20 0x0010
venkik 9:29c618fec8fc 470 #define adc_status_P11_RESERVED_19 0x0008
venkik 9:29c618fec8fc 471 #define adc_status_P11_RESERVED_18 0x0004
venkik 9:29c618fec8fc 472 #define adc_status_P11_RESERVED_17 0x0002
venkik 9:29c618fec8fc 473 #define adc_status_P11_ADCSTp11 0x0001
venkik 9:29c618fec8fc 474
venkik 9:29c618fec8fc 475 /// 0x04 r/o dac_oi_status_P10P6_P5P0 DAC Overcurrent Interrupt
venkik 9:29c618fec8fc 476 /// <code>1xxxxxxxxxxxxxxx</code> DACOISTp10 DACOIST[15] new <see cref="dac_data_port_p10"/>
venkik 9:29c618fec8fc 477 /// <code>x1xxxxxxxxxxxxxx</code> DACOISTp09 DACOIST[14] new <see cref="dac_data_port_p9"/>
venkik 9:29c618fec8fc 478 /// <code>xx1xxxxxxxxxxxxx</code> DACOISTp08 DACOIST[13] new <see cref="dac_data_port_p8"/>
venkik 9:29c618fec8fc 479 /// <code>xxx1xxxxxxxxxxxx</code> DACOISTp07 DACOIST[12] new <see cref="dac_data_port_p7"/>
venkik 9:29c618fec8fc 480 /// <code>xxxx1xxxxxxxxxxx</code> DACOISTp06 DACOIST[11] new <see cref="dac_data_port_p6"/>
venkik 9:29c618fec8fc 481 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_10 DACOIST[10] new <see cref="reserved_6A"/>
venkik 9:29c618fec8fc 482 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_09 DACOIST[9] new <see cref="reserved_69"/>
venkik 9:29c618fec8fc 483 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_08 DACOIST[8] new <see cref="reserved_68"/>
venkik 9:29c618fec8fc 484 /// <code>xxxxxxxx1xxxxxxx</code> DACOISTp05 DACOIST[7] new <see cref="dac_data_port_p5"/>
venkik 9:29c618fec8fc 485 /// <code>xxxxxxxxx1xxxxxx</code> DACOISTp04 DACOIST[6] new <see cref="dac_data_port_p4"/>
venkik 9:29c618fec8fc 486 /// <code>xxxxxxxxxx1xxxxx</code> DACOISTp03 DACOIST[5] new <see cref="dac_data_port_p3"/>
venkik 9:29c618fec8fc 487 /// <code>xxxxxxxxxxx1xxxx</code> DACOISTp02 DACOIST[4] new <see cref="dac_data_port_p2"/>
venkik 9:29c618fec8fc 488 /// <code>xxxxxxxxxxxx1xxx</code> DACOISTp01 DACOIST[3] new <see cref="dac_data_port_p1"/>
venkik 9:29c618fec8fc 489 /// <code>xxxxxxxxxxxxx1xx</code> DACOISTp00 DACOIST[2] new <see cref="dac_data_port_p0"/>
venkik 9:29c618fec8fc 490 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_01 DACOIST[1] new <see cref="reserved_61"/>
venkik 9:29c618fec8fc 491 /// <code>xxxxxxxxxxxxxxx1</code> RESERVED_00 DACOIST[0] new <see cref="reserved_60"/>
venkik 9:29c618fec8fc 492 #define dac_oi_status_P10P6_P5P0_DACOISTp10 0x8000
venkik 9:29c618fec8fc 493 #define dac_oi_status_P10P6_P5P0_DACOISTp09 0x4000
venkik 9:29c618fec8fc 494 #define dac_oi_status_P10P6_P5P0_DACOISTp08 0x2000
venkik 9:29c618fec8fc 495 #define dac_oi_status_P10P6_P5P0_DACOISTp07 0x1000
venkik 9:29c618fec8fc 496 #define dac_oi_status_P10P6_P5P0_DACOISTp06 0x0800
venkik 9:29c618fec8fc 497 #define dac_oi_status_P10P6_P5P0_RESERVED_10 0x0400
venkik 9:29c618fec8fc 498 #define dac_oi_status_P10P6_P5P0_RESERVED_09 0x0200
venkik 9:29c618fec8fc 499 #define dac_oi_status_P10P6_P5P0_RESERVED_08 0x0100
venkik 9:29c618fec8fc 500 #define dac_oi_status_P10P6_P5P0_DACOISTp05 0x0080
venkik 9:29c618fec8fc 501 #define dac_oi_status_P10P6_P5P0_DACOISTp04 0x0040
venkik 9:29c618fec8fc 502 #define dac_oi_status_P10P6_P5P0_DACOISTp03 0x0020
venkik 9:29c618fec8fc 503 #define dac_oi_status_P10P6_P5P0_DACOISTp02 0x0010
venkik 9:29c618fec8fc 504 #define dac_oi_status_P10P6_P5P0_DACOISTp01 0x0008
venkik 9:29c618fec8fc 505 #define dac_oi_status_P10P6_P5P0_DACOISTp00 0x0004
venkik 9:29c618fec8fc 506 #define dac_oi_status_P10P6_P5P0_RESERVED_01 0x0002
venkik 9:29c618fec8fc 507 #define dac_oi_status_P10P6_P5P0_RESERVED_00 0x0001
venkik 9:29c618fec8fc 508
venkik 9:29c618fec8fc 509 /// 0x05 r/o dac_oi_status_P11 DAC Overcurrent Interrupt
venkik 9:29c618fec8fc 510 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_31 DACOIST[31] new <see cref="dac_data_port_31"/>
venkik 9:29c618fec8fc 511 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_30 DACOIST[30] new <see cref="dac_data_port_30"/>
venkik 9:29c618fec8fc 512 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_29 DACOIST[29] new <see cref="dac_data_port_29"/>
venkik 9:29c618fec8fc 513 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_28 DACOIST[28] new <see cref="dac_data_port_28"/>
venkik 9:29c618fec8fc 514 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_27 DACOIST[27] new <see cref="dac_data_port_27"/>
venkik 9:29c618fec8fc 515 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_26 DACOIST[26] new <see cref="dac_data_port_26"/>
venkik 9:29c618fec8fc 516 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_25 DACOIST[25] new <see cref="dac_data_port_25"/>
venkik 9:29c618fec8fc 517 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_24 DACOIST[24] new <see cref="dac_data_port_24"/>
venkik 9:29c618fec8fc 518 /// <code>xxxxxxxx1xxxxxxx</code> RESERVED_23 DACOIST[23] new <see cref="dac_data_port_23"/>
venkik 9:29c618fec8fc 519 /// <code>xxxxxxxxx1xxxxxx</code> RESERVED_22 DACOIST[22] new <see cref="dac_data_port_22"/>
venkik 9:29c618fec8fc 520 /// <code>xxxxxxxxxx1xxxxx</code> RESERVED_21 DACOIST[21] new <see cref="dac_data_port_21"/>
venkik 9:29c618fec8fc 521 /// <code>xxxxxxxxxxx1xxxx</code> RESERVED_20 DACOIST[20] new <see cref="dac_data_port_20"/>
venkik 9:29c618fec8fc 522 /// <code>xxxxxxxxxxxx1xxx</code> RESERVED_19 DACOIST[19] new <see cref="reserved_73"/>
venkik 9:29c618fec8fc 523 /// <code>xxxxxxxxxxxxx1xx</code> RESERVED_18 DACOIST[18] new <see cref="reserved_72"/>
venkik 9:29c618fec8fc 524 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_17 DACOIST[17] new <see cref="reserved_71"/>
venkik 9:29c618fec8fc 525 /// <code>xxxxxxxxxxxxxxx1</code> DACOISTp11 DACOIST[16] new <see cref="dac_data_port_p11"/>
venkik 9:29c618fec8fc 526 #define dac_oi_status_P11_RESERVED_31 0x8000
venkik 9:29c618fec8fc 527 #define dac_oi_status_P11_RESERVED_30 0x4000
venkik 9:29c618fec8fc 528 #define dac_oi_status_P11_RESERVED_29 0x2000
venkik 9:29c618fec8fc 529 #define dac_oi_status_P11_RESERVED_28 0x1000
venkik 9:29c618fec8fc 530 #define dac_oi_status_P11_RESERVED_27 0x0800
venkik 9:29c618fec8fc 531 #define dac_oi_status_P11_RESERVED_26 0x0400
venkik 9:29c618fec8fc 532 #define dac_oi_status_P11_RESERVED_25 0x0200
venkik 9:29c618fec8fc 533 #define dac_oi_status_P11_RESERVED_24 0x0100
venkik 9:29c618fec8fc 534 #define dac_oi_status_P11_RESERVED_23 0x0080
venkik 9:29c618fec8fc 535 #define dac_oi_status_P11_RESERVED_22 0x0040
venkik 9:29c618fec8fc 536 #define dac_oi_status_P11_RESERVED_21 0x0020
venkik 9:29c618fec8fc 537 #define dac_oi_status_P11_RESERVED_20 0x0010
venkik 9:29c618fec8fc 538 #define dac_oi_status_P11_RESERVED_19 0x0008
venkik 9:29c618fec8fc 539 #define dac_oi_status_P11_RESERVED_18 0x0004
venkik 9:29c618fec8fc 540 #define dac_oi_status_P11_RESERVED_17 0x0002
venkik 9:29c618fec8fc 541 #define dac_oi_status_P11_DACOISTp11 0x0001
venkik 9:29c618fec8fc 542
venkik 9:29c618fec8fc 543 /// 0x06 r/o gpi_status_P10P6_P5P0 GPI event ready
venkik 9:29c618fec8fc 544 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_010 GPIST[15]
venkik 9:29c618fec8fc 545 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_009 GPIST[14]
venkik 9:29c618fec8fc 546 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_008 GPIST[13]
venkik 9:29c618fec8fc 547 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_007 GPIST[12]
venkik 9:29c618fec8fc 548 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_006 GPIST[11]
venkik 9:29c618fec8fc 549 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_10 GPIST[10]
venkik 9:29c618fec8fc 550 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_09 GPIST[9]
venkik 9:29c618fec8fc 551 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_08 GPIST[8]
venkik 9:29c618fec8fc 552 /// <code>xxxxxxxx1xxxxxxx</code> GPISTp05 GPIST[7]
venkik 9:29c618fec8fc 553 /// <code>xxxxxxxxx1xxxxxx</code> GPISTp04 GPIST[6]
venkik 9:29c618fec8fc 554 /// <code>xxxxxxxxxx1xxxxx</code> GPISTp03 GPIST[5]
venkik 9:29c618fec8fc 555 /// <code>xxxxxxxxxxx1xxxx</code> GPISTp02 GPIST[4]
venkik 9:29c618fec8fc 556 /// <code>xxxxxxxxxxxx1xxx</code> GPISTp01 GPIST[3]
venkik 9:29c618fec8fc 557 /// <code>xxxxxxxxxxxxx1xx</code> GPISTp00 GPIST[2]
venkik 9:29c618fec8fc 558 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_01 GPIST[1]
venkik 9:29c618fec8fc 559 /// <code>xxxxxxxxxxxxxxx1</code> RESERVED_00 GPIST[0]
venkik 9:29c618fec8fc 560 #define gpi_status_P10P6_P5P0_RESERVED_010 0x8000
venkik 9:29c618fec8fc 561 #define gpi_status_P10P6_P5P0_RESERVED_009 0x4000
venkik 9:29c618fec8fc 562 #define gpi_status_P10P6_P5P0_RESERVED_008 0x2000
venkik 9:29c618fec8fc 563 #define gpi_status_P10P6_P5P0_RESERVED_007 0x1000
venkik 9:29c618fec8fc 564 #define gpi_status_P10P6_P5P0_RESERVED_006 0x0800
venkik 9:29c618fec8fc 565 #define gpi_status_P10P6_P5P0_RESERVED_10 0x0400
venkik 9:29c618fec8fc 566 #define gpi_status_P10P6_P5P0_RESERVED_09 0x0200
venkik 9:29c618fec8fc 567 #define gpi_status_P10P6_P5P0_RESERVED_08 0x0100
venkik 9:29c618fec8fc 568 #define gpi_status_P10P6_P5P0_GPISTp05 0x0080
venkik 9:29c618fec8fc 569 #define gpi_status_P10P6_P5P0_GPISTp04 0x0040
venkik 9:29c618fec8fc 570 #define gpi_status_P10P6_P5P0_GPISTp03 0x0020
venkik 9:29c618fec8fc 571 #define gpi_status_P10P6_P5P0_GPISTp02 0x0010
venkik 9:29c618fec8fc 572 #define gpi_status_P10P6_P5P0_GPISTp01 0x0008
venkik 9:29c618fec8fc 573 #define gpi_status_P10P6_P5P0_GPISTp00 0x0004
venkik 9:29c618fec8fc 574 #define gpi_status_P10P6_P5P0_RESERVED_01 0x0002
venkik 9:29c618fec8fc 575 #define gpi_status_P10P6_P5P0_RESERVED_00 0x0001
venkik 9:29c618fec8fc 576
venkik 9:29c618fec8fc 577 /// 0x07 r/o gpi_status_P11 GPI event ready
venkik 9:29c618fec8fc 578 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_31 GPIST[31]
venkik 9:29c618fec8fc 579 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_30 GPIST[30]
venkik 9:29c618fec8fc 580 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_29 GPIST[29]
venkik 9:29c618fec8fc 581 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_28 GPIST[28]
venkik 9:29c618fec8fc 582 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_27 GPIST[27]
venkik 9:29c618fec8fc 583 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_26 GPIST[26]
venkik 9:29c618fec8fc 584 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_25 GPIST[25]
venkik 9:29c618fec8fc 585 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_24 GPIST[24]
venkik 9:29c618fec8fc 586 /// <code>xxxxxxxx1xxxxxxx</code> RESERVED_23 GPIST[23]
venkik 9:29c618fec8fc 587 /// <code>xxxxxxxxx1xxxxxx</code> RESERVED_22 GPIST[22]
venkik 9:29c618fec8fc 588 /// <code>xxxxxxxxxx1xxxxx</code> RESERVED_21 GPIST[21]
venkik 9:29c618fec8fc 589 /// <code>xxxxxxxxxxx1xxxx</code> RESERVED_20 GPIST[20]
venkik 9:29c618fec8fc 590 /// <code>xxxxxxxxxxxx1xxx</code> RESERVED_19 GPIST[19]
venkik 9:29c618fec8fc 591 /// <code>xxxxxxxxxxxxx1xx</code> RESERVED_18 GPIST[18]
venkik 9:29c618fec8fc 592 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_17 GPIST[17]
venkik 9:29c618fec8fc 593 /// <code>xxxxxxxxxxxxxxx1</code> GPISTp11 GPIST[16]
venkik 9:29c618fec8fc 594 #define gpi_status_P11_RESERVED_31 0x8000
venkik 9:29c618fec8fc 595 #define gpi_status_P11_RESERVED_30 0x4000
venkik 9:29c618fec8fc 596 #define gpi_status_P11_RESERVED_29 0x2000
venkik 9:29c618fec8fc 597 #define gpi_status_P11_RESERVED_28 0x1000
venkik 9:29c618fec8fc 598 #define gpi_status_P11_RESERVED_27 0x0800
venkik 9:29c618fec8fc 599 #define gpi_status_P11_RESERVED_26 0x0400
venkik 9:29c618fec8fc 600 #define gpi_status_P11_RESERVED_25 0x0200
venkik 9:29c618fec8fc 601 #define gpi_status_P11_RESERVED_24 0x0100
venkik 9:29c618fec8fc 602 #define gpi_status_P11_RESERVED_23 0x0080
venkik 9:29c618fec8fc 603 #define gpi_status_P11_RESERVED_22 0x0040
venkik 9:29c618fec8fc 604 #define gpi_status_P11_RESERVED_21 0x0020
venkik 9:29c618fec8fc 605 #define gpi_status_P11_RESERVED_20 0x0010
venkik 9:29c618fec8fc 606 #define gpi_status_P11_RESERVED_19 0x0008
venkik 9:29c618fec8fc 607 #define gpi_status_P11_RESERVED_18 0x0004
venkik 9:29c618fec8fc 608 #define gpi_status_P11_RESERVED_17 0x0002
venkik 9:29c618fec8fc 609 #define gpi_status_P11_GPISTp11 0x0001
venkik 9:29c618fec8fc 610
venkik 9:29c618fec8fc 611 /// 0x08 r/o tmp_int_data Internal Temeprature
venkik 9:29c618fec8fc 612 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 613 #define tmp_int_data_tempcode 0x0fff
venkik 9:29c618fec8fc 614
venkik 9:29c618fec8fc 615 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N
venkik 9:29c618fec8fc 616 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 617 #define tmp_ext1_data_tempcode 0x0fff
venkik 9:29c618fec8fc 618
venkik 9:29c618fec8fc 619 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N
venkik 9:29c618fec8fc 620 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 621 #define tmp_ext2_data_tempcode 0x0fff
venkik 9:29c618fec8fc 622
venkik 9:29c618fec8fc 623 /// 0x0b r/o gpi_data_P10P6_P5P0 GPI input ports data
venkik 9:29c618fec8fc 624 /// <code>1xxxxxxxxxxxxxxx</code> GPIDATp10 GPIDAT[15]
venkik 9:29c618fec8fc 625 /// <code>x1xxxxxxxxxxxxxx</code> GPIDATp09 GPIDAT[14]
venkik 9:29c618fec8fc 626 /// <code>xx1xxxxxxxxxxxxx</code> GPIDATp08 GPIDAT[13]
venkik 9:29c618fec8fc 627 /// <code>xxx1xxxxxxxxxxxx</code> GPIDATp07 GPIDAT[12]
venkik 9:29c618fec8fc 628 /// <code>xxxx1xxxxxxxxxxx</code> GPIDATp06 GPIDAT[11]
venkik 9:29c618fec8fc 629 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_10 GPIDAT[10]
venkik 9:29c618fec8fc 630 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_09 GPIDAT[9]
venkik 9:29c618fec8fc 631 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_08 GPIDAT[8]
venkik 9:29c618fec8fc 632 /// <code>xxxxxxxx1xxxxxxx</code> GPIDATp05 GPIDAT[7]
venkik 9:29c618fec8fc 633 /// <code>xxxxxxxxx1xxxxxx</code> GPIDATp04 GPIDAT[6]
venkik 9:29c618fec8fc 634 /// <code>xxxxxxxxxx1xxxxx</code> GPIDATp03 GPIDAT[5]
venkik 9:29c618fec8fc 635 /// <code>xxxxxxxxxxx1xxxx</code> GPIDATp02 GPIDAT[4]
venkik 9:29c618fec8fc 636 /// <code>xxxxxxxxxxxx1xxx</code> GPIDATp01 GPIDAT[3]
venkik 9:29c618fec8fc 637 /// <code>xxxxxxxxxxxxx1xx</code> GPIDATp00 GPIDAT[2]
venkik 9:29c618fec8fc 638 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_01 GPIDAT[1]
venkik 9:29c618fec8fc 639 /// <code>xxxxxxxxxxxxxxx1</code> RESERVED_00 GPIDAT[0]
venkik 9:29c618fec8fc 640 #define gpi_data_P10P6_P5P0_GPIDATp10 0x8000
venkik 9:29c618fec8fc 641 #define gpi_data_P10P6_P5P0_GPIDATp09 0x4000
venkik 9:29c618fec8fc 642 #define gpi_data_P10P6_P5P0_GPIDATp08 0x2000
venkik 9:29c618fec8fc 643 #define gpi_data_P10P6_P5P0_GPIDATp07 0x1000
venkik 9:29c618fec8fc 644 #define gpi_data_P10P6_P5P0_GPIDATp06 0x0800
venkik 9:29c618fec8fc 645 #define gpi_data_P10P6_P5P0_RESERVED_10 0x0400
venkik 9:29c618fec8fc 646 #define gpi_data_P10P6_P5P0_RESERVED_09 0x0200
venkik 9:29c618fec8fc 647 #define gpi_data_P10P6_P5P0_RESERVED_08 0x0100
venkik 9:29c618fec8fc 648 #define gpi_data_P10P6_P5P0_GPIDATp05 0x0080
venkik 9:29c618fec8fc 649 #define gpi_data_P10P6_P5P0_GPIDATp04 0x0040
venkik 9:29c618fec8fc 650 #define gpi_data_P10P6_P5P0_GPIDATp03 0x0020
venkik 9:29c618fec8fc 651 #define gpi_data_P10P6_P5P0_GPIDATp02 0x0010
venkik 9:29c618fec8fc 652 #define gpi_data_P10P6_P5P0_GPIDATp01 0x0008
venkik 9:29c618fec8fc 653 #define gpi_data_P10P6_P5P0_GPIDATp00 0x0004
venkik 9:29c618fec8fc 654 #define gpi_data_P10P6_P5P0_RESERVED_01 0x0002
venkik 9:29c618fec8fc 655 #define gpi_data_P10P6_P5P0_RESERVED_00 0x0001
venkik 9:29c618fec8fc 656
venkik 9:29c618fec8fc 657 /// 0x0c r/o gpi_data_P11 GPI input ports data
venkik 9:29c618fec8fc 658 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_31 GPIDAT[31]
venkik 9:29c618fec8fc 659 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_30 GPIDAT[30]
venkik 9:29c618fec8fc 660 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_29 GPIDAT[29]
venkik 9:29c618fec8fc 661 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_28 GPIDAT[28]
venkik 9:29c618fec8fc 662 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_27 GPIDAT[27]
venkik 9:29c618fec8fc 663 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_26 GPIDAT[26]
venkik 9:29c618fec8fc 664 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_25 GPIDAT[25]
venkik 9:29c618fec8fc 665 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_24 GPIDAT[24]
venkik 9:29c618fec8fc 666 /// <code>xxxxxxxx1xxxxxxx</code> RESERVED_23 GPIDAT[23]
venkik 9:29c618fec8fc 667 /// <code>xxxxxxxxx1xxxxxx</code> RESERVED_22 GPIDAT[22]
venkik 9:29c618fec8fc 668 /// <code>xxxxxxxxxx1xxxxx</code> RESERVED_21 GPIDAT[21]
venkik 9:29c618fec8fc 669 /// <code>xxxxxxxxxxx1xxxx</code> RESERVED_20 GPIDAT[20]
venkik 9:29c618fec8fc 670 /// <code>xxxxxxxxxxxx1xxx</code> RESERVED_19 GPIDAT[19]
venkik 9:29c618fec8fc 671 /// <code>xxxxxxxxxxxxx1xx</code> RESERVED_18 GPIDAT[18]
venkik 9:29c618fec8fc 672 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_17 GPIDAT[17]
venkik 9:29c618fec8fc 673 /// <code>xxxxxxxxxxxxxxx1</code> GPIDATp11 GPIDAT[16]
venkik 9:29c618fec8fc 674 #define gpi_data_P11_RESERVED_31 0x8000
venkik 9:29c618fec8fc 675 #define gpi_data_P11_RESERVED_30 0x4000
venkik 9:29c618fec8fc 676 #define gpi_data_P11_RESERVED_29 0x2000
venkik 9:29c618fec8fc 677 #define gpi_data_P11_RESERVED_28 0x1000
venkik 9:29c618fec8fc 678 #define gpi_data_P11_RESERVED_27 0x0800
venkik 9:29c618fec8fc 679 #define gpi_data_P11_RESERVED_26 0x0400
venkik 9:29c618fec8fc 680 #define gpi_data_P11_RESERVED_25 0x0200
venkik 9:29c618fec8fc 681 #define gpi_data_P11_RESERVED_24 0x0100
venkik 9:29c618fec8fc 682 #define gpi_data_P11_RESERVED_23 0x0080
venkik 9:29c618fec8fc 683 #define gpi_data_P11_RESERVED_22 0x0040
venkik 9:29c618fec8fc 684 #define gpi_data_P11_RESERVED_21 0x0020
venkik 9:29c618fec8fc 685 #define gpi_data_P11_RESERVED_20 0x0010
venkik 9:29c618fec8fc 686 #define gpi_data_P11_RESERVED_19 0x0008
venkik 9:29c618fec8fc 687 #define gpi_data_P11_RESERVED_18 0x0004
venkik 9:29c618fec8fc 688 #define gpi_data_P11_RESERVED_17 0x0002
venkik 9:29c618fec8fc 689 #define gpi_data_P11_GPIDATp11 0x0001
venkik 9:29c618fec8fc 690
venkik 9:29c618fec8fc 691 /// 0x0d r/w gpo_data_P10P6_P5P0 GPO output ports data
venkik 9:29c618fec8fc 692 /// <code>1xxxxxxxxxxxxxxx</code> GPODATp10 GPODAT[15]
venkik 9:29c618fec8fc 693 /// <code>x1xxxxxxxxxxxxxx</code> GPODATp09 GPODAT[14]
venkik 9:29c618fec8fc 694 /// <code>xx1xxxxxxxxxxxxx</code> GPODATp08 GPODAT[13]
venkik 9:29c618fec8fc 695 /// <code>xxx1xxxxxxxxxxxx</code> GPODATp07 GPODAT[12]
venkik 9:29c618fec8fc 696 /// <code>xxxx1xxxxxxxxxxx</code> GPODATp06 GPODAT[11]
venkik 9:29c618fec8fc 697 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_10 GPODAT[10]
venkik 9:29c618fec8fc 698 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_09 GPODAT[9]
venkik 9:29c618fec8fc 699 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_08 GPODAT[8]
venkik 9:29c618fec8fc 700 /// <code>xxxxxxxx1xxxxxxx</code> GPODATp05 GPODAT[7]
venkik 9:29c618fec8fc 701 /// <code>xxxxxxxxx1xxxxxx</code> GPODATp04 GPODAT[6]
venkik 9:29c618fec8fc 702 /// <code>xxxxxxxxxx1xxxxx</code> GPODATp03 GPODAT[5]
venkik 9:29c618fec8fc 703 /// <code>xxxxxxxxxxx1xxxx</code> GPODATp02 GPODAT[4]
venkik 9:29c618fec8fc 704 /// <code>xxxxxxxxxxxx1xxx</code> GPODATp01 GPODAT[3]
venkik 9:29c618fec8fc 705 /// <code>xxxxxxxxxxxxx1xx</code> GPODATp00 GPODAT[2]
venkik 9:29c618fec8fc 706 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_01 GPODAT[1]
venkik 9:29c618fec8fc 707 /// <code>xxxxxxxxxxxxxxx1</code> RESERVED_00 GPODAT[0]
venkik 9:29c618fec8fc 708 #define gpo_data_P10P6_P5P0_GPODATp10 0x8000
venkik 9:29c618fec8fc 709 #define gpo_data_P10P6_P5P0_GPODATp09 0x4000
venkik 9:29c618fec8fc 710 #define gpo_data_P10P6_P5P0_GPODATp08 0x2000
venkik 9:29c618fec8fc 711 #define gpo_data_P10P6_P5P0_GPODATp07 0x1000
venkik 9:29c618fec8fc 712 #define gpo_data_P10P6_P5P0_GPODATp06 0x0800
venkik 9:29c618fec8fc 713 #define gpo_data_P10P6_P5P0_RESERVED_10 0x0400
venkik 9:29c618fec8fc 714 #define gpo_data_P10P6_P5P0_RESERVED_09 0x0200
venkik 9:29c618fec8fc 715 #define gpo_data_P10P6_P5P0_RESERVED_08 0x0100
venkik 9:29c618fec8fc 716 #define gpo_data_P10P6_P5P0_GPODATp05 0x0080
venkik 9:29c618fec8fc 717 #define gpo_data_P10P6_P5P0_GPODATp04 0x0040
venkik 9:29c618fec8fc 718 #define gpo_data_P10P6_P5P0_GPODATp03 0x0020
venkik 9:29c618fec8fc 719 #define gpo_data_P10P6_P5P0_GPODATp02 0x0010
venkik 9:29c618fec8fc 720 #define gpo_data_P10P6_P5P0_GPODATp01 0x0008
venkik 9:29c618fec8fc 721 #define gpo_data_P10P6_P5P0_GPODATp00 0x0004
venkik 9:29c618fec8fc 722 #define gpo_data_P10P6_P5P0_RESERVED_01 0x0002
venkik 9:29c618fec8fc 723 #define gpo_data_P10P6_P5P0_RESERVED_00 0x0001
venkik 9:29c618fec8fc 724 #define gpo_data_P10P6_P5P0_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 725
venkik 9:29c618fec8fc 726 /// 0x0e r/w gpo_data_P11 GPO output ports data
venkik 9:29c618fec8fc 727 /// <code>1xxxxxxxxxxxxxxx</code> RESERVED_31 GPODAT[31]
venkik 9:29c618fec8fc 728 /// <code>x1xxxxxxxxxxxxxx</code> RESERVED_30 GPODAT[30]
venkik 9:29c618fec8fc 729 /// <code>xx1xxxxxxxxxxxxx</code> RESERVED_29 GPODAT[29]
venkik 9:29c618fec8fc 730 /// <code>xxx1xxxxxxxxxxxx</code> RESERVED_28 GPODAT[28]
venkik 9:29c618fec8fc 731 /// <code>xxxx1xxxxxxxxxxx</code> RESERVED_27 GPODAT[27]
venkik 9:29c618fec8fc 732 /// <code>xxxxx1xxxxxxxxxx</code> RESERVED_26 GPODAT[26]
venkik 9:29c618fec8fc 733 /// <code>xxxxxx1xxxxxxxxx</code> RESERVED_25 GPODAT[25]
venkik 9:29c618fec8fc 734 /// <code>xxxxxxx1xxxxxxxx</code> RESERVED_24 GPODAT[24]
venkik 9:29c618fec8fc 735 /// <code>xxxxxxxx1xxxxxxx</code> RESERVED_23 GPODAT[23]
venkik 9:29c618fec8fc 736 /// <code>xxxxxxxxx1xxxxxx</code> RESERVED_22 GPODAT[22]
venkik 9:29c618fec8fc 737 /// <code>xxxxxxxxxx1xxxxx</code> RESERVED_21 GPODAT[21]
venkik 9:29c618fec8fc 738 /// <code>xxxxxxxxxxx1xxxx</code> RESERVED_20 GPODAT[20]
venkik 9:29c618fec8fc 739 /// <code>xxxxxxxxxxxx1xxx</code> RESERVED_19 GPODAT[19]
venkik 9:29c618fec8fc 740 /// <code>xxxxxxxxxxxxx1xx</code> RESERVED_18 GPODAT[18]
venkik 9:29c618fec8fc 741 /// <code>xxxxxxxxxxxxxx1x</code> RESERVED_17 GPODAT[17]
venkik 9:29c618fec8fc 742 /// <code>xxxxxxxxxxxxxxx1</code> GPODATp11 GPODAT[16]
venkik 9:29c618fec8fc 743 #define gpo_data_P11_RESERVED_31 0x8000
venkik 9:29c618fec8fc 744 #define gpo_data_P11_RESERVED_30 0x4000
venkik 9:29c618fec8fc 745 #define gpo_data_P11_RESERVED_29 0x2000
venkik 9:29c618fec8fc 746 #define gpo_data_P11_RESERVED_28 0x1000
venkik 9:29c618fec8fc 747 #define gpo_data_P11_RESERVED_27 0x0800
venkik 9:29c618fec8fc 748 #define gpo_data_P11_RESERVED_26 0x0400
venkik 9:29c618fec8fc 749 #define gpo_data_P11_RESERVED_25 0x0200
venkik 9:29c618fec8fc 750 #define gpo_data_P11_RESERVED_24 0x0100
venkik 9:29c618fec8fc 751 #define gpo_data_P11_RESERVED_23 0x0080
venkik 9:29c618fec8fc 752 #define gpo_data_P11_RESERVED_22 0x0040
venkik 9:29c618fec8fc 753 #define gpo_data_P11_RESERVED_21 0x0020
venkik 9:29c618fec8fc 754 #define gpo_data_P11_RESERVED_20 0x0010
venkik 9:29c618fec8fc 755 #define gpo_data_P11_RESERVED_19 0x0008
venkik 9:29c618fec8fc 756 #define gpo_data_P11_RESERVED_18 0x0004
venkik 9:29c618fec8fc 757 #define gpo_data_P11_RESERVED_17 0x0002
venkik 9:29c618fec8fc 758 #define gpo_data_P11_GPODATp11 0x0001
venkik 9:29c618fec8fc 759 #define gpo_data_P11_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 760
venkik 9:29c618fec8fc 761 /// 0x0f r/o reserved_0F reserved
venkik 9:29c618fec8fc 762
venkik 9:29c618fec8fc 763
venkik 9:29c618fec8fc 764 /// 0x10 r/w device_control Global device control register
venkik 9:29c618fec8fc 765 /// <code>1xxxxxxxxxxxxxxx</code> RESET Soft reset command
venkik 9:29c618fec8fc 766 /// - 0 = No operation
venkik 9:29c618fec8fc 767 /// - 1 = Perform power-on reset. (This bit is self-clearing.)
venkik 9:29c618fec8fc 768 /// <code>x1xxxxxxxxxxxxxx</code> BRST Burst Mode
venkik 9:29c618fec8fc 769 /// - 0 = Automatically increment register address in serial interface burst mode.
venkik 9:29c618fec8fc 770 /// - 1 = Burst Read cycle through only the ADC data ports;
venkik 9:29c618fec8fc 771 /// Burst Write cycle through only the DAC data ports.
venkik 9:29c618fec8fc 772 /// <code>xx1xxxxxxxxxxxxx</code> LPEN Low Power Enable
venkik 9:29c618fec8fc 773 /// - 0 = Normal operation
venkik 9:29c618fec8fc 774 /// - 1 = Sleep mode
venkik 9:29c618fec8fc 775 /// <code>xxx1xxxxxxxxxxxx</code> RS_CANCEL series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
venkik 9:29c618fec8fc 776 /// - 0 = Disable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
venkik 9:29c618fec8fc 777 /// - 1 = Enable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
venkik 9:29c618fec8fc 778 /// <code>xxxx1xxxxxxxxxxx</code> TMPPER temperature monitor period
venkik 9:29c618fec8fc 779 /// - 0 = min IH period is 32.5μsec, hold time of SAMPLE is 7μsec.
venkik 9:29c618fec8fc 780 /// - 1 = min IH period is 65.0μsec, hold time of SAMPLE is 15μsec.
venkik 9:29c618fec8fc 781 /// <code>xxxxx1xxxxxxxxxx</code> TMPCTLEXT1 monitor external temperature D1P/D1N
venkik 9:29c618fec8fc 782 /// <code>xxxxxx1xxxxxxxxx</code> TMPCTLEXT0 monitor external temperature D0P/D0N
venkik 9:29c618fec8fc 783 /// <code>xxxxxxx1xxxxxxxx</code> TMPCTLINT monitor internal temperature
venkik 9:29c618fec8fc 784 /// <code>xxxxxxxx1xxxxxxx</code> THSHDN Thermal Shutdown
venkik 9:29c618fec8fc 785 /// - 0 = Disable Thermal Shutdown
venkik 9:29c618fec8fc 786 /// - 1 = Enable Thermal Shutdown: reset all ports to hi-Z if <see cref="tmp_int_data"/> is greater than 145 degrees C
venkik 9:29c618fec8fc 787 /// <code>xxxxxxxxx1xxxxxx</code> DACREF DAC voltage reference
venkik 9:29c618fec8fc 788 /// - 0 = External DAC voltage reference
venkik 9:29c618fec8fc 789 /// - 1 = Internal DAC voltage reference
venkik 9:29c618fec8fc 790 /// <code>xxxxxxxxxx11xxxx</code> ADCCONV ADC conversion rate
venkik 9:29c618fec8fc 791 /// - 0 = 200Ksps
venkik 9:29c618fec8fc 792 /// - 1 = 250Ksps
venkik 9:29c618fec8fc 793 /// - 2 = 333Ksps
venkik 9:29c618fec8fc 794 /// - 3 = 400Ksps
venkik 9:29c618fec8fc 795 /// <code>xxxxxxxxxxxx11xx</code> DACCTL DAC update mode
venkik 9:29c618fec8fc 796 /// - 0 = Update DAC values in normal sequence
venkik 9:29c618fec8fc 797 /// - 1 = Update DAC immediately after dac_data_port_xx write
venkik 9:29c618fec8fc 798 /// - 2 = All DAC data registers loaded with <see cref="dac_preset_data_1"/>
venkik 9:29c618fec8fc 799 /// - 3 = All DAC data registers loaded with <see cref="dac_preset_data_2"/>
venkik 9:29c618fec8fc 800 /// <code>xxxxxxxxxxxxxx11</code> ADCCTL ADC conversion mode
venkik 9:29c618fec8fc 801 /// - 0 = Idle mode
venkik 9:29c618fec8fc 802 /// - 1 = Single sweep triggered by CNVTB pin
venkik 9:29c618fec8fc 803 /// - 2 = Single conversion triggered by CNVTB pin
venkik 9:29c618fec8fc 804 /// - 3 = Continuous sweep
venkik 9:29c618fec8fc 805 #define device_control_RESET 0x8000
venkik 9:29c618fec8fc 806 #define device_control_BRST 0x4000
venkik 9:29c618fec8fc 807 #define device_control_LPEN 0x2000
venkik 9:29c618fec8fc 808 #define device_control_RS_CANCEL 0x1000
venkik 9:29c618fec8fc 809 #define device_control_TMPPER 0x0800
venkik 9:29c618fec8fc 810 #define device_control_TMPCTLEXT1 0x0400
venkik 9:29c618fec8fc 811 #define device_control_TMPCTLEXT0 0x0200
venkik 9:29c618fec8fc 812 #define device_control_TMPCTLINT 0x0100
venkik 9:29c618fec8fc 813 #define device_control_THSHDN 0x0080
venkik 9:29c618fec8fc 814 #define device_control_DACREF 0x0040
venkik 9:29c618fec8fc 815 #define device_control_ADCCONV 0x0030
venkik 9:29c618fec8fc 816 #define device_control_DACCTL 0x000c
venkik 9:29c618fec8fc 817 #define device_control_ADCCTL 0x0003
venkik 9:29c618fec8fc 818 #define device_control_DESIGNVALUE 0x17c1
venkik 9:29c618fec8fc 819
venkik 9:29c618fec8fc 820 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source)
venkik 9:29c618fec8fc 821 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor
venkik 9:29c618fec8fc 822 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot
venkik 9:29c618fec8fc 823 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold
venkik 9:29c618fec8fc 824 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New
venkik 9:29c618fec8fc 825 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot
venkik 9:29c618fec8fc 826 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold
venkik 9:29c618fec8fc 827 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New
venkik 9:29c618fec8fc 828 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot
venkik 9:29c618fec8fc 829 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold
venkik 9:29c618fec8fc 830 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New
venkik 9:29c618fec8fc 831 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current
venkik 9:29c618fec8fc 832 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed
venkik 9:29c618fec8fc 833 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready
venkik 9:29c618fec8fc 834 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed
venkik 9:29c618fec8fc 835 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready
venkik 9:29c618fec8fc 836 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete
venkik 9:29c618fec8fc 837 #define interrupt_mask_VMON 0x8000
venkik 9:29c618fec8fc 838 #define interrupt_mask_TMPEXT2HOT 0x4000
venkik 9:29c618fec8fc 839 #define interrupt_mask_TMPEXT2COLD 0x2000
venkik 9:29c618fec8fc 840 #define interrupt_mask_TMPEXT2NEW 0x1000
venkik 9:29c618fec8fc 841 #define interrupt_mask_TMPEXT1HOT 0x0800
venkik 9:29c618fec8fc 842 #define interrupt_mask_TMPEXT1COLD 0x0400
venkik 9:29c618fec8fc 843 #define interrupt_mask_TMPEXT1NEW 0x0200
venkik 9:29c618fec8fc 844 #define interrupt_mask_TMPINTHOT 0x0100
venkik 9:29c618fec8fc 845 #define interrupt_mask_TMPINTCOLD 0x0080
venkik 9:29c618fec8fc 846 #define interrupt_mask_TMPINTNEW 0x0040
venkik 9:29c618fec8fc 847 #define interrupt_mask_DACOI 0x0020
venkik 9:29c618fec8fc 848 #define interrupt_mask_GPIDM 0x0010
venkik 9:29c618fec8fc 849 #define interrupt_mask_GPIDR 0x0008
venkik 9:29c618fec8fc 850 #define interrupt_mask_ADCDM 0x0004
venkik 9:29c618fec8fc 851 #define interrupt_mask_ADCDR 0x0002
venkik 9:29c618fec8fc 852 #define interrupt_mask_ADCFLAG 0x0001
venkik 9:29c618fec8fc 853 #define interrupt_mask_DESIGNVALUE 0xfffd
venkik 9:29c618fec8fc 854
venkik 9:29c618fec8fc 855 /// 0x12 r/w gpi_irqmode_P5_P0 GPI ports P5 to P0 mode register
venkik 9:29c618fec8fc 856 /// <code>11xxxxxxxxxxxxxx</code> GPIMDp05 GPIMD[7]
venkik 9:29c618fec8fc 857 /// <code>xx11xxxxxxxxxxxx</code> GPIMDp04 GPIMD[6]
venkik 9:29c618fec8fc 858 /// <code>xxxx11xxxxxxxxxx</code> GPIMDp03 GPIMD[5]
venkik 9:29c618fec8fc 859 /// <code>xxxxxx11xxxxxxxx</code> GPIMDp02 GPIMD[4]
venkik 9:29c618fec8fc 860 /// <code>xxxxxxxx11xxxxxx</code> GPIMDp01 GPIMD[3]
venkik 9:29c618fec8fc 861 /// <code>xxxxxxxxxx11xxxx</code> GPIMDp00 GPIMD[2]
venkik 9:29c618fec8fc 862 /// <code>xxxxxxxxxxxx11xx</code> RESERVED_01 GPIMD[1]
venkik 9:29c618fec8fc 863 /// <code>xxxxxxxxxxxxxx11</code> RESERVED_00 GPIMD[0]
venkik 9:29c618fec8fc 864 /// <para>GPIMD[portId] interrupt mask bits:
venkik 9:29c618fec8fc 865 /// - 0 = masked
venkik 9:29c618fec8fc 866 /// - 1 = detect positive edge
venkik 9:29c618fec8fc 867 /// - 2 = detect negative edge
venkik 9:29c618fec8fc 868 /// - 3 = detect positive or negative edge
venkik 9:29c618fec8fc 869 /// </para>
venkik 9:29c618fec8fc 870 #define gpi_irqmode_P5_P0_GPIMDp05 0xc000
venkik 9:29c618fec8fc 871 #define gpi_irqmode_P5_P0_GPIMDp04 0x3000
venkik 9:29c618fec8fc 872 #define gpi_irqmode_P5_P0_GPIMDp03 0x0c00
venkik 9:29c618fec8fc 873 #define gpi_irqmode_P5_P0_GPIMDp02 0x0300
venkik 9:29c618fec8fc 874 #define gpi_irqmode_P5_P0_GPIMDp01 0x00c0
venkik 9:29c618fec8fc 875 #define gpi_irqmode_P5_P0_GPIMDp00 0x0030
venkik 9:29c618fec8fc 876 #define gpi_irqmode_P5_P0_RESERVED_01 0x000c
venkik 9:29c618fec8fc 877 #define gpi_irqmode_P5_P0_RESERVED_00 0x0003
venkik 9:29c618fec8fc 878 #define gpi_irqmode_P5_P0_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 879
venkik 9:29c618fec8fc 880 /// 0x13 r/w gpi_irqmode_P10_P6 GPI ports P10 to P6 mode register
venkik 9:29c618fec8fc 881 /// <code>11xxxxxxxxxxxxxx</code> GPIMDp10 GPIMD[15]
venkik 9:29c618fec8fc 882 /// <code>xx11xxxxxxxxxxxx</code> GPIMDp09 GPIMD[14]
venkik 9:29c618fec8fc 883 /// <code>xxxx11xxxxxxxxxx</code> GPIMDp08 GPIMD[13]
venkik 9:29c618fec8fc 884 /// <code>xxxxxx11xxxxxxxx</code> GPIMDp07 GPIMD[12]
venkik 9:29c618fec8fc 885 /// <code>xxxxxxxx11xxxxxx</code> GPIMDp06 GPIMD[11]
venkik 9:29c618fec8fc 886 /// <code>xxxxxxxxxx11xxxx</code> RESERVED_10 GPIMD[10]
venkik 9:29c618fec8fc 887 /// <code>xxxxxxxxxxxx11xx</code> RESERVED_09 GPIMD[9]
venkik 9:29c618fec8fc 888 /// <code>xxxxxxxxxxxxxx11</code> RESERVED_08 GPIMD[8]
venkik 9:29c618fec8fc 889 /// <para>GPIMD[portId] interrupt mask bits:
venkik 9:29c618fec8fc 890 /// - 0 = masked
venkik 9:29c618fec8fc 891 /// - 1 = detect positive edge
venkik 9:29c618fec8fc 892 /// - 2 = detect negative edge
venkik 9:29c618fec8fc 893 /// - 3 = detect positive or negative edge
venkik 9:29c618fec8fc 894 /// </para>
venkik 9:29c618fec8fc 895 #define gpi_irqmode_P10_P6_GPIMDp10 0xc000
venkik 9:29c618fec8fc 896 #define gpi_irqmode_P10_P6_GPIMDp09 0x3000
venkik 9:29c618fec8fc 897 #define gpi_irqmode_P10_P6_GPIMDp08 0x0c00
venkik 9:29c618fec8fc 898 #define gpi_irqmode_P10_P6_GPIMDp07 0x0300
venkik 9:29c618fec8fc 899 #define gpi_irqmode_P10_P6_GPIMDp06 0x00c0
venkik 9:29c618fec8fc 900 #define gpi_irqmode_P10_P6_RESERVED_10 0x0030
venkik 9:29c618fec8fc 901 #define gpi_irqmode_P10_P6_RESERVED_09 0x000c
venkik 9:29c618fec8fc 902 #define gpi_irqmode_P10_P6_RESERVED_08 0x0003
venkik 9:29c618fec8fc 903 #define gpi_irqmode_P10_P6_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 904
venkik 9:29c618fec8fc 905 /// 0x14 r/w gpi_irqmode_P11 GPI port P11 mode register
venkik 9:29c618fec8fc 906 /// <code>11xxxxxxxxxxxxxx</code> RESERVED_23 GPIMD[23]
venkik 9:29c618fec8fc 907 /// <code>xx11xxxxxxxxxxxx</code> RESERVED_22 GPIMD[22]
venkik 9:29c618fec8fc 908 /// <code>xxxx11xxxxxxxxxx</code> RESERVED_21 GPIMD[21]
venkik 9:29c618fec8fc 909 /// <code>xxxxxx11xxxxxxxx</code> RESERVED_20 GPIMD[20]
venkik 9:29c618fec8fc 910 /// <code>xxxxxxxx11xxxxxx</code> RESERVED_19 GPIMD[19]
venkik 9:29c618fec8fc 911 /// <code>xxxxxxxxxx11xxxx</code> RESERVED_18 GPIMD[18]
venkik 9:29c618fec8fc 912 /// <code>xxxxxxxxxxxx11xx</code> RESERVED_17 GPIMD[17]
venkik 9:29c618fec8fc 913 /// <code>xxxxxxxxxxxxxx11</code> GPIMDp11 GPIMD[16]
venkik 9:29c618fec8fc 914 /// <para>GPIMD[portId] interrupt mask bits:
venkik 9:29c618fec8fc 915 /// - 0 = masked
venkik 9:29c618fec8fc 916 /// - 1 = detect positive edge
venkik 9:29c618fec8fc 917 /// - 2 = detect negative edge
venkik 9:29c618fec8fc 918 /// - 3 = detect positive or negative edge
venkik 9:29c618fec8fc 919 /// </para>
venkik 9:29c618fec8fc 920 #define gpi_irqmode_P11_RESERVED_23 0xc000
venkik 9:29c618fec8fc 921 #define gpi_irqmode_P11_RESERVED_22 0x3000
venkik 9:29c618fec8fc 922 #define gpi_irqmode_P11_RESERVED_21 0x0c00
venkik 9:29c618fec8fc 923 #define gpi_irqmode_P11_RESERVED_20 0x0300
venkik 9:29c618fec8fc 924 #define gpi_irqmode_P11_RESERVED_19 0x00c0
venkik 9:29c618fec8fc 925 #define gpi_irqmode_P11_RESERVED_18 0x0030
venkik 9:29c618fec8fc 926 #define gpi_irqmode_P11_RESERVED_17 0x000c
venkik 9:29c618fec8fc 927 #define gpi_irqmode_P11_GPIMDp11 0x0003
venkik 9:29c618fec8fc 928 #define gpi_irqmode_P11_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 929
venkik 9:29c618fec8fc 930 /// 0x15 r/w reserved_15 (reserved)
venkik 9:29c618fec8fc 931 /// <code>11xxxxxxxxxxxxxx</code> RESERVED_31 GPIMD[31]
venkik 9:29c618fec8fc 932 /// <code>xx11xxxxxxxxxxxx</code> RESERVED_30 GPIMD[30]
venkik 9:29c618fec8fc 933 /// <code>xxxx11xxxxxxxxxx</code> RESERVED_29 GPIMD[29]
venkik 9:29c618fec8fc 934 /// <code>xxxxxx11xxxxxxxx</code> RESERVED_28 GPIMD[28]
venkik 9:29c618fec8fc 935 /// <code>xxxxxxxx11xxxxxx</code> RESERVED_27 GPIMD[27]
venkik 9:29c618fec8fc 936 /// <code>xxxxxxxxxx11xxxx</code> RESERVED_26 GPIMD[26]
venkik 9:29c618fec8fc 937 /// <code>xxxxxxxxxxxx11xx</code> RESERVED_25 GPIMD[25]
venkik 9:29c618fec8fc 938 /// <code>xxxxxxxxxxxxxx11</code> RESERVED_24 GPIMD[24]
venkik 9:29c618fec8fc 939 /// <para>GPIMD[portId] interrupt mask bits:
venkik 9:29c618fec8fc 940 /// - 0 = masked
venkik 9:29c618fec8fc 941 /// - 1 = detect positive edge
venkik 9:29c618fec8fc 942 /// - 2 = detect negative edge
venkik 9:29c618fec8fc 943 /// - 3 = detect positive or negative edge
venkik 9:29c618fec8fc 944 /// </para>
venkik 9:29c618fec8fc 945 #define reserved_15_RESERVED_31 0xc000
venkik 9:29c618fec8fc 946 #define reserved_15_RESERVED_30 0x3000
venkik 9:29c618fec8fc 947 #define reserved_15_RESERVED_29 0x0c00
venkik 9:29c618fec8fc 948 #define reserved_15_RESERVED_28 0x0300
venkik 9:29c618fec8fc 949 #define reserved_15_RESERVED_27 0x00c0
venkik 9:29c618fec8fc 950 #define reserved_15_RESERVED_26 0x0030
venkik 9:29c618fec8fc 951 #define reserved_15_RESERVED_25 0x000c
venkik 9:29c618fec8fc 952 #define reserved_15_RESERVED_24 0x0003
venkik 9:29c618fec8fc 953
venkik 9:29c618fec8fc 954 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/>
venkik 9:29c618fec8fc 955 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 956 #define dac_preset_data_1_daccode 0x0fff
venkik 9:29c618fec8fc 957 #define dac_preset_data_1_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 958
venkik 9:29c618fec8fc 959 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/>
venkik 9:29c618fec8fc 960 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 961 #define dac_preset_data_2_daccode 0x0fff
venkik 9:29c618fec8fc 962 #define dac_preset_data_2_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 963
venkik 9:29c618fec8fc 964 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration
venkik 9:29c618fec8fc 965 /// <code>xxxxxxxxxx11xxxx</code> TMPEXT2MONCFG average 4, 8, 16, or 32 measurements
venkik 9:29c618fec8fc 966 /// <code>xxxxxxxxxxxx11xx</code> TMPEXT1MONCFG average 4, 8, 16, or 32 measurements
venkik 9:29c618fec8fc 967 /// <code>xxxxxxxxxxxxxx11</code> TMPINTMONCFG average 4, 8, 16, or 32 measurements
venkik 9:29c618fec8fc 968 /// <para>Temperautre Monitor Configuration:
venkik 9:29c618fec8fc 969 /// - 0 = 4 measurements (default)
venkik 9:29c618fec8fc 970 /// - 1 = 8 measurements
venkik 9:29c618fec8fc 971 /// - 2 = 16 measurements
venkik 9:29c618fec8fc 972 /// - 3 = 32 measurements
venkik 9:29c618fec8fc 973 /// </para>
venkik 9:29c618fec8fc 974 #define tmp_mon_cfg_TMPEXT2MONCFG 0x0030
venkik 9:29c618fec8fc 975 #define tmp_mon_cfg_TMPEXT1MONCFG 0x000c
venkik 9:29c618fec8fc 976 #define tmp_mon_cfg_TMPINTMONCFG 0x0003
venkik 9:29c618fec8fc 977 #define tmp_mon_cfg_DESIGNVALUE 0x003f
venkik 9:29c618fec8fc 978
venkik 9:29c618fec8fc 979 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold
venkik 9:29c618fec8fc 980 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 981 #define tmp_mon_int_hi_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 982 #define tmp_mon_int_hi_thresh_DESIGNVALUE 0x07ff
venkik 9:29c618fec8fc 983
venkik 9:29c618fec8fc 984 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold
venkik 9:29c618fec8fc 985 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 986 #define tmp_mon_int_lo_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 987 #define tmp_mon_int_lo_thresh_DESIGNVALUE 0x0800
venkik 9:29c618fec8fc 988
venkik 9:29c618fec8fc 989 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold
venkik 9:29c618fec8fc 990 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 991 #define tmp_mon_ext1_hi_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 992 #define tmp_mon_ext1_hi_thresh_DESIGNVALUE 0x07ff
venkik 9:29c618fec8fc 993
venkik 9:29c618fec8fc 994 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold
venkik 9:29c618fec8fc 995 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 996 #define tmp_mon_ext1_lo_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 997 #define tmp_mon_ext1_lo_thresh_DESIGNVALUE 0x0800
venkik 9:29c618fec8fc 998
venkik 9:29c618fec8fc 999 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold
venkik 9:29c618fec8fc 1000 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 1001 #define tmp_mon_ext2_hi_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 1002 #define tmp_mon_ext2_hi_thresh_DESIGNVALUE 0x07ff
venkik 9:29c618fec8fc 1003
venkik 9:29c618fec8fc 1004 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold
venkik 9:29c618fec8fc 1005 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
venkik 9:29c618fec8fc 1006 #define tmp_mon_ext2_lo_thresh_tempcode 0x0fff
venkik 9:29c618fec8fc 1007 #define tmp_mon_ext2_lo_thresh_DESIGNVALUE 0x0800
venkik 9:29c618fec8fc 1008
venkik 9:29c618fec8fc 1009 /// 0x1f r/w reserved_1F reserved
venkik 9:29c618fec8fc 1010
venkik 9:29c618fec8fc 1011
venkik 9:29c618fec8fc 1012 /// 0x20 r/w reserved_20 (reserved) configuration register
venkik 9:29c618fec8fc 1013 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1014 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1015 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1016 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1017 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1018 #define reserved_20_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1019 #define reserved_20_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1020 #define reserved_20_funcprm_range 0x0700
venkik 9:29c618fec8fc 1021 #define reserved_20_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1022 #define reserved_20_funcprm_port 0x001f
venkik 9:29c618fec8fc 1023 #define reserved_20_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1024
venkik 9:29c618fec8fc 1025 /// 0x21 r/w reserved_21 (reserved) configuration register
venkik 9:29c618fec8fc 1026 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1027 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1028 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1029 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1030 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1031 #define reserved_21_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1032 #define reserved_21_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1033 #define reserved_21_funcprm_range 0x0700
venkik 9:29c618fec8fc 1034 #define reserved_21_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1035 #define reserved_21_funcprm_port 0x001f
venkik 9:29c618fec8fc 1036 #define reserved_21_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1037
venkik 9:29c618fec8fc 1038 /// 0x22 r/w port_cfg_p0 PIXI port P0 configuration register
venkik 9:29c618fec8fc 1039 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1040 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1041 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1042 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1043 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1044 #define port_cfg_p0_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1045 #define port_cfg_p0_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1046 #define port_cfg_p0_funcprm_range 0x0700
venkik 9:29c618fec8fc 1047 #define port_cfg_p0_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1048 #define port_cfg_p0_funcprm_port 0x001f
venkik 9:29c618fec8fc 1049 #define port_cfg_p0_DESIGNVALUE 0x74e0
venkik 9:29c618fec8fc 1050
venkik 9:29c618fec8fc 1051 /// 0x23 r/w port_cfg_p1 PIXI port P1 configuration register
venkik 9:29c618fec8fc 1052 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1053 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1054 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1055 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1056 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1057 #define port_cfg_p1_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1058 #define port_cfg_p1_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1059 #define port_cfg_p1_funcprm_range 0x0700
venkik 9:29c618fec8fc 1060 #define port_cfg_p1_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1061 #define port_cfg_p1_funcprm_port 0x001f
venkik 9:29c618fec8fc 1062 #define port_cfg_p1_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1063
venkik 9:29c618fec8fc 1064 /// 0x24 r/w port_cfg_p2 PIXI port P2 configuration register
venkik 9:29c618fec8fc 1065 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1066 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1067 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1068 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1069 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1070 #define port_cfg_p2_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1071 #define port_cfg_p2_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1072 #define port_cfg_p2_funcprm_range 0x0700
venkik 9:29c618fec8fc 1073 #define port_cfg_p2_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1074 #define port_cfg_p2_funcprm_port 0x001f
venkik 9:29c618fec8fc 1075 #define port_cfg_p2_DESIGNVALUE 0x74e0
venkik 9:29c618fec8fc 1076
venkik 9:29c618fec8fc 1077 /// 0x25 r/w port_cfg_p3 PIXI port P3 configuration register
venkik 9:29c618fec8fc 1078 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1079 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1080 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1081 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1082 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1083 #define port_cfg_p3_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1084 #define port_cfg_p3_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1085 #define port_cfg_p3_funcprm_range 0x0700
venkik 9:29c618fec8fc 1086 #define port_cfg_p3_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1087 #define port_cfg_p3_funcprm_port 0x001f
venkik 9:29c618fec8fc 1088 #define port_cfg_p3_DESIGNVALUE 0x5100
venkik 9:29c618fec8fc 1089
venkik 9:29c618fec8fc 1090 /// 0x26 r/w port_cfg_p4 PIXI port P4 configuration register
venkik 9:29c618fec8fc 1091 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1092 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1093 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1094 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1095 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1096 #define port_cfg_p4_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1097 #define port_cfg_p4_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1098 #define port_cfg_p4_funcprm_range 0x0700
venkik 9:29c618fec8fc 1099 #define port_cfg_p4_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1100 #define port_cfg_p4_funcprm_port 0x001f
venkik 9:29c618fec8fc 1101 #define port_cfg_p4_DESIGNVALUE 0x71e0
venkik 9:29c618fec8fc 1102
venkik 9:29c618fec8fc 1103 /// 0x27 r/w port_cfg_p5 PIXI port P5 configuration register
venkik 9:29c618fec8fc 1104 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1105 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1106 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1107 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1108 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1109 #define port_cfg_p5_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1110 #define port_cfg_p5_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1111 #define port_cfg_p5_funcprm_range 0x0700
venkik 9:29c618fec8fc 1112 #define port_cfg_p5_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1113 #define port_cfg_p5_funcprm_port 0x001f
venkik 9:29c618fec8fc 1114 #define port_cfg_p5_DESIGNVALUE 0x5100
venkik 9:29c618fec8fc 1115
venkik 9:29c618fec8fc 1116 /// 0x28 r/w reserved_28 (reserved) configuration register
venkik 9:29c618fec8fc 1117 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1118 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1119 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1120 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1121 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1122 #define reserved_28_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1123 #define reserved_28_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1124 #define reserved_28_funcprm_range 0x0700
venkik 9:29c618fec8fc 1125 #define reserved_28_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1126 #define reserved_28_funcprm_port 0x001f
venkik 9:29c618fec8fc 1127 #define reserved_28_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1128
venkik 9:29c618fec8fc 1129 /// 0x29 r/w reserved_29 (reserved) configuration register
venkik 9:29c618fec8fc 1130 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1131 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1132 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1133 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1134 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1135 #define reserved_29_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1136 #define reserved_29_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1137 #define reserved_29_funcprm_range 0x0700
venkik 9:29c618fec8fc 1138 #define reserved_29_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1139 #define reserved_29_funcprm_port 0x001f
venkik 9:29c618fec8fc 1140 #define reserved_29_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1141
venkik 9:29c618fec8fc 1142 /// 0x2a r/w reserved_2A (reserved) configuration register
venkik 9:29c618fec8fc 1143 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1144 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1145 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1146 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1147 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1148 #define reserved_2A_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1149 #define reserved_2A_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1150 #define reserved_2A_funcprm_range 0x0700
venkik 9:29c618fec8fc 1151 #define reserved_2A_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1152 #define reserved_2A_funcprm_port 0x001f
venkik 9:29c618fec8fc 1153 #define reserved_2A_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1154
venkik 9:29c618fec8fc 1155 /// 0x2b r/w port_cfg_p6 PIXI port P6 configuration register
venkik 9:29c618fec8fc 1156 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1157 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1158 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1159 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1160 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1161 #define port_cfg_p6_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1162 #define port_cfg_p6_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1163 #define port_cfg_p6_funcprm_range 0x0700
venkik 9:29c618fec8fc 1164 #define port_cfg_p6_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1165 #define port_cfg_p6_funcprm_port 0x001f
venkik 9:29c618fec8fc 1166 #define port_cfg_p6_DESIGNVALUE 0x74e0
venkik 9:29c618fec8fc 1167
venkik 9:29c618fec8fc 1168 /// 0x2c r/w port_cfg_p7 PIXI port P7 configuration register
venkik 9:29c618fec8fc 1169 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1170 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1171 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1172 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1173 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1174 #define port_cfg_p7_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1175 #define port_cfg_p7_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1176 #define port_cfg_p7_funcprm_range 0x0700
venkik 9:29c618fec8fc 1177 #define port_cfg_p7_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1178 #define port_cfg_p7_funcprm_port 0x001f
venkik 9:29c618fec8fc 1179 #define port_cfg_p7_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1180
venkik 9:29c618fec8fc 1181 /// 0x2d r/w port_cfg_p8 PIXI port P8 configuration register
venkik 9:29c618fec8fc 1182 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1183 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1184 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1185 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1186 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1187 #define port_cfg_p8_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1188 #define port_cfg_p8_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1189 #define port_cfg_p8_funcprm_range 0x0700
venkik 9:29c618fec8fc 1190 #define port_cfg_p8_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1191 #define port_cfg_p8_funcprm_port 0x001f
venkik 9:29c618fec8fc 1192 #define port_cfg_p8_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1193
venkik 9:29c618fec8fc 1194 /// 0x2e r/w port_cfg_p9 PIXI port P9 configuration register
venkik 9:29c618fec8fc 1195 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1196 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1197 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1198 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1199 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1200 #define port_cfg_p9_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1201 #define port_cfg_p9_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1202 #define port_cfg_p9_funcprm_range 0x0700
venkik 9:29c618fec8fc 1203 #define port_cfg_p9_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1204 #define port_cfg_p9_funcprm_port 0x001f
venkik 9:29c618fec8fc 1205 #define port_cfg_p9_DESIGNVALUE 0x5100
venkik 9:29c618fec8fc 1206
venkik 9:29c618fec8fc 1207 /// 0x2f r/w port_cfg_p10 PIXI port P10 configuration register
venkik 9:29c618fec8fc 1208 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1209 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1210 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1211 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1212 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1213 #define port_cfg_p10_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1214 #define port_cfg_p10_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1215 #define port_cfg_p10_funcprm_range 0x0700
venkik 9:29c618fec8fc 1216 #define port_cfg_p10_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1217 #define port_cfg_p10_funcprm_port 0x001f
venkik 9:29c618fec8fc 1218 #define port_cfg_p10_DESIGNVALUE 0x5100
venkik 9:29c618fec8fc 1219
venkik 9:29c618fec8fc 1220 /// 0x30 r/w port_cfg_p11 PIXI port P11 configuration register
venkik 9:29c618fec8fc 1221 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1222 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1223 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1224 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1225 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1226 #define port_cfg_p11_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1227 #define port_cfg_p11_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1228 #define port_cfg_p11_funcprm_range 0x0700
venkik 9:29c618fec8fc 1229 #define port_cfg_p11_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1230 #define port_cfg_p11_funcprm_port 0x001f
venkik 9:29c618fec8fc 1231 #define port_cfg_p11_DESIGNVALUE 0x5200
venkik 9:29c618fec8fc 1232
venkik 9:29c618fec8fc 1233 /// 0x31 r/w reserved_31 (reserved) configuration register
venkik 9:29c618fec8fc 1234 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1235 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1236 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1237 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1238 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1239 #define reserved_31_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1240 #define reserved_31_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1241 #define reserved_31_funcprm_range 0x0700
venkik 9:29c618fec8fc 1242 #define reserved_31_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1243 #define reserved_31_funcprm_port 0x001f
venkik 9:29c618fec8fc 1244 #define reserved_31_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1245
venkik 9:29c618fec8fc 1246 /// 0x32 r/w reserved_32 (reserved) configuration register
venkik 9:29c618fec8fc 1247 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1248 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1249 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1250 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1251 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1252 #define reserved_32_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1253 #define reserved_32_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1254 #define reserved_32_funcprm_range 0x0700
venkik 9:29c618fec8fc 1255 #define reserved_32_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1256 #define reserved_32_funcprm_port 0x001f
venkik 9:29c618fec8fc 1257 #define reserved_32_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1258
venkik 9:29c618fec8fc 1259 /// 0x33 r/w reserved_33 (reserved) configuration register
venkik 9:29c618fec8fc 1260 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
venkik 9:29c618fec8fc 1261 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
venkik 9:29c618fec8fc 1262 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
venkik 9:29c618fec8fc 1263 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
venkik 9:29c618fec8fc 1264 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
venkik 9:29c618fec8fc 1265 #define reserved_33_PortCfgFuncID 0xf000
venkik 9:29c618fec8fc 1266 #define reserved_33_funcprm_avrInv 0x0800
venkik 9:29c618fec8fc 1267 #define reserved_33_funcprm_range 0x0700
venkik 9:29c618fec8fc 1268 #define reserved_33_funcprm_nsamples 0x00e0
venkik 9:29c618fec8fc 1269 #define reserved_33_funcprm_port 0x001f
venkik 9:29c618fec8fc 1270 #define reserved_33_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1271
venkik 9:29c618fec8fc 1272 /// 0x40 r/o reserved_40 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1273 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1274 #define reserved_40_adccode 0x0fff
venkik 9:29c618fec8fc 1275
venkik 9:29c618fec8fc 1276 /// 0x41 r/o reserved_41 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1277 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1278 #define reserved_41_adccode 0x0fff
venkik 9:29c618fec8fc 1279
venkik 9:29c618fec8fc 1280 /// 0x42 r/o adc_data_port_p0 PIXI port P0 Analog to Digital Converter register
venkik 9:29c618fec8fc 1281 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1282 #define adc_data_port_p0_adccode 0x0fff
venkik 9:29c618fec8fc 1283
venkik 9:29c618fec8fc 1284 /// 0x43 r/o adc_data_port_p1 PIXI port P1 Analog to Digital Converter register
venkik 9:29c618fec8fc 1285 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1286 #define adc_data_port_p1_adccode 0x0fff
venkik 9:29c618fec8fc 1287
venkik 9:29c618fec8fc 1288 /// 0x44 r/o adc_data_port_p2 PIXI port P2 Analog to Digital Converter register
venkik 9:29c618fec8fc 1289 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1290 #define adc_data_port_p2_adccode 0x0fff
venkik 9:29c618fec8fc 1291
venkik 9:29c618fec8fc 1292 /// 0x45 r/o adc_data_port_p3 PIXI port P3 Analog to Digital Converter register
venkik 9:29c618fec8fc 1293 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1294 #define adc_data_port_p3_adccode 0x0fff
venkik 9:29c618fec8fc 1295
venkik 9:29c618fec8fc 1296 /// 0x46 r/o adc_data_port_p4 PIXI port P4 Analog to Digital Converter register
venkik 9:29c618fec8fc 1297 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1298 #define adc_data_port_p4_adccode 0x0fff
venkik 9:29c618fec8fc 1299
venkik 9:29c618fec8fc 1300 /// 0x47 r/o adc_data_port_p5 PIXI port P5 Analog to Digital Converter register
venkik 9:29c618fec8fc 1301 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1302 #define adc_data_port_p5_adccode 0x0fff
venkik 9:29c618fec8fc 1303
venkik 9:29c618fec8fc 1304 /// 0x48 r/o reserved_48 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1305 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1306 #define reserved_48_adccode 0x0fff
venkik 9:29c618fec8fc 1307
venkik 9:29c618fec8fc 1308 /// 0x49 r/o reserved_49 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1309 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1310 #define reserved_49_adccode 0x0fff
venkik 9:29c618fec8fc 1311
venkik 9:29c618fec8fc 1312 /// 0x4a r/o reserved_4A (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1313 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1314 #define reserved_4A_adccode 0x0fff
venkik 9:29c618fec8fc 1315
venkik 9:29c618fec8fc 1316 /// 0x4b r/o adc_data_port_p6 PIXI port P6 Analog to Digital Converter register
venkik 9:29c618fec8fc 1317 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1318 #define adc_data_port_p6_adccode 0x0fff
venkik 9:29c618fec8fc 1319
venkik 9:29c618fec8fc 1320 /// 0x4c r/o adc_data_port_p7 PIXI port P7 Analog to Digital Converter register
venkik 9:29c618fec8fc 1321 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1322 #define adc_data_port_p7_adccode 0x0fff
venkik 9:29c618fec8fc 1323
venkik 9:29c618fec8fc 1324 /// 0x4d r/o adc_data_port_p8 PIXI port P8 Analog to Digital Converter register
venkik 9:29c618fec8fc 1325 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1326 #define adc_data_port_p8_adccode 0x0fff
venkik 9:29c618fec8fc 1327
venkik 9:29c618fec8fc 1328 /// 0x4e r/o adc_data_port_p9 PIXI port P9 Analog to Digital Converter register
venkik 9:29c618fec8fc 1329 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1330 #define adc_data_port_p9_adccode 0x0fff
venkik 9:29c618fec8fc 1331
venkik 9:29c618fec8fc 1332 /// 0x4f r/o adc_data_port_p10 PIXI port P10 Analog to Digital Converter register
venkik 9:29c618fec8fc 1333 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1334 #define adc_data_port_p10_adccode 0x0fff
venkik 9:29c618fec8fc 1335
venkik 9:29c618fec8fc 1336 /// 0x50 r/o adc_data_port_p11 PIXI port P11 Analog to Digital Converter register
venkik 9:29c618fec8fc 1337 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1338 #define adc_data_port_p11_adccode 0x0fff
venkik 9:29c618fec8fc 1339
venkik 9:29c618fec8fc 1340 /// 0x51 r/o reserved_51 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1341 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1342 #define reserved_51_adccode 0x0fff
venkik 9:29c618fec8fc 1343
venkik 9:29c618fec8fc 1344 /// 0x52 r/o reserved_52 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1345 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1346 #define reserved_52_adccode 0x0fff
venkik 9:29c618fec8fc 1347
venkik 9:29c618fec8fc 1348 /// 0x53 r/o reserved_53 (reserved) Analog to Digital Converter register
venkik 9:29c618fec8fc 1349 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
venkik 9:29c618fec8fc 1350 #define reserved_53_adccode 0x0fff
venkik 9:29c618fec8fc 1351
venkik 9:29c618fec8fc 1352 /// 0x60 r/w reserved_60 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1353 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1354 #define reserved_60_daccode 0x0fff
venkik 9:29c618fec8fc 1355 #define reserved_60_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1356
venkik 9:29c618fec8fc 1357 /// 0x61 r/w reserved_61 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1358 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1359 #define reserved_61_daccode 0x0fff
venkik 9:29c618fec8fc 1360 #define reserved_61_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1361
venkik 9:29c618fec8fc 1362 /// 0x62 r/w dac_data_port_p0 PIXI port P0 Digital to Analog Converter register
venkik 9:29c618fec8fc 1363 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1364 #define dac_data_port_p0_daccode 0x0fff
venkik 9:29c618fec8fc 1365 #define dac_data_port_p0_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1366
venkik 9:29c618fec8fc 1367 /// 0x63 r/w dac_data_port_p1 PIXI port P1 Digital to Analog Converter register
venkik 9:29c618fec8fc 1368 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1369 #define dac_data_port_p1_daccode 0x0fff
venkik 9:29c618fec8fc 1370 #define dac_data_port_p1_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1371
venkik 9:29c618fec8fc 1372 /// 0x64 r/w dac_data_port_p2 PIXI port P2 Digital to Analog Converter register
venkik 9:29c618fec8fc 1373 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1374 #define dac_data_port_p2_daccode 0x0fff
venkik 9:29c618fec8fc 1375 #define dac_data_port_p2_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1376
venkik 9:29c618fec8fc 1377 /// 0x65 r/w dac_data_port_p3 PIXI port P3 Digital to Analog Converter register
venkik 9:29c618fec8fc 1378 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1379 #define dac_data_port_p3_daccode 0x0fff
venkik 9:29c618fec8fc 1380 #define dac_data_port_p3_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1381
venkik 9:29c618fec8fc 1382 /// 0x66 r/w dac_data_port_p4 PIXI port P4 Digital to Analog Converter register
venkik 9:29c618fec8fc 1383 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1384 #define dac_data_port_p4_daccode 0x0fff
venkik 9:29c618fec8fc 1385 #define dac_data_port_p4_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1386
venkik 9:29c618fec8fc 1387 /// 0x67 r/w dac_data_port_p5 PIXI port P5 Digital to Analog Converter register
venkik 9:29c618fec8fc 1388 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1389 #define dac_data_port_p5_daccode 0x0fff
venkik 9:29c618fec8fc 1390 #define dac_data_port_p5_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1391
venkik 9:29c618fec8fc 1392 /// 0x68 r/w reserved_68 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1393 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1394 #define reserved_68_daccode 0x0fff
venkik 9:29c618fec8fc 1395 #define reserved_68_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1396
venkik 9:29c618fec8fc 1397 /// 0x69 r/w reserved_69 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1398 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1399 #define reserved_69_daccode 0x0fff
venkik 9:29c618fec8fc 1400 #define reserved_69_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1401
venkik 9:29c618fec8fc 1402 /// 0x6a r/w reserved_6A (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1403 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1404 #define reserved_6A_daccode 0x0fff
venkik 9:29c618fec8fc 1405 #define reserved_6A_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1406
venkik 9:29c618fec8fc 1407 /// 0x6b r/w dac_data_port_p6 PIXI port P6 Digital to Analog Converter register
venkik 9:29c618fec8fc 1408 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1409 #define dac_data_port_p6_daccode 0x0fff
venkik 9:29c618fec8fc 1410 #define dac_data_port_p6_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1411
venkik 9:29c618fec8fc 1412 /// 0x6c r/w dac_data_port_p7 PIXI port P7 Digital to Analog Converter register
venkik 9:29c618fec8fc 1413 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1414 #define dac_data_port_p7_daccode 0x0fff
venkik 9:29c618fec8fc 1415 #define dac_data_port_p7_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1416
venkik 9:29c618fec8fc 1417 /// 0x6d r/w dac_data_port_p8 PIXI port P8 Digital to Analog Converter register
venkik 9:29c618fec8fc 1418 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1419 #define dac_data_port_p8_daccode 0x0fff
venkik 9:29c618fec8fc 1420 #define dac_data_port_p8_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1421
venkik 9:29c618fec8fc 1422 /// 0x6e r/w dac_data_port_p9 PIXI port P9 Digital to Analog Converter register
venkik 9:29c618fec8fc 1423 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1424 #define dac_data_port_p9_daccode 0x0fff
venkik 9:29c618fec8fc 1425 #define dac_data_port_p9_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1426
venkik 9:29c618fec8fc 1427 /// 0x6f r/w dac_data_port_p10 PIXI port P10 Digital to Analog Converter register
venkik 9:29c618fec8fc 1428 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1429 #define dac_data_port_p10_daccode 0x0fff
venkik 9:29c618fec8fc 1430 #define dac_data_port_p10_DESIGNVALUE 0x0fff
venkik 9:29c618fec8fc 1431
venkik 9:29c618fec8fc 1432 /// 0x70 r/w dac_data_port_p11 PIXI port P11 Digital to Analog Converter register
venkik 9:29c618fec8fc 1433 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1434 #define dac_data_port_p11_daccode 0x0fff
venkik 9:29c618fec8fc 1435 #define dac_data_port_p11_DESIGNVALUE 0x019a
venkik 9:29c618fec8fc 1436
venkik 9:29c618fec8fc 1437 /// 0x71 r/w reserved_71 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1438 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1439 #define reserved_71_daccode 0x0fff
venkik 9:29c618fec8fc 1440 #define reserved_71_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1441
venkik 9:29c618fec8fc 1442 /// 0x72 r/w reserved_72 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1443 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1444 #define reserved_72_daccode 0x0fff
venkik 9:29c618fec8fc 1445 #define reserved_72_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1446
venkik 9:29c618fec8fc 1447 /// 0x73 r/w reserved_73 (reserved) Digital to Analog Converter register
venkik 9:29c618fec8fc 1448 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
venkik 9:29c618fec8fc 1449 #define reserved_73_daccode 0x0fff
venkik 9:29c618fec8fc 1450 #define reserved_73_DESIGNVALUE 0x0000
venkik 9:29c618fec8fc 1451
venkik 9:29c618fec8fc 1452 /// Initialize registers in sequence recommended by PIXI Port Configuration Flow Chart.
venkik 9:29c618fec8fc 1453 /// Requires user-provided function MAX11300regWrite(regAddress8, regData16)
venkik 9:29c618fec8fc 1454 uint16_t MAX11300regWrite(uint8_t regAddress8, uint16_t regData16);
venkik 9:29c618fec8fc 1455 uint16_t MAX11300regRead(uint8_t regAddress8);
venkik 9:29c618fec8fc 1456 /// Requires user-provided function MAX11300initDelayus(delay_us)
venkik 9:29c618fec8fc 1457 void MAX11300initDelayus(uint8_t delay_us);
venkik 9:29c618fec8fc 1458 ///
venkik 9:29c618fec8fc 1459 /// PIXI ports to configure as Mode 0 HighImpedance:
venkik 9:29c618fec8fc 1460 /// portIndex 0 PIXI port --- N.C.
venkik 9:29c618fec8fc 1461 /// portIndex 1 PIXI port --- N.C.
venkik 9:29c618fec8fc 1462 /// portIndex 3 PIXI port P1 Differential in- for measuring the source voltage
venkik 9:29c618fec8fc 1463 /// portIndex 8 PIXI port --- N.C.
venkik 9:29c618fec8fc 1464 /// portIndex 9 PIXI port --- N.C.
venkik 9:29c618fec8fc 1465 /// portIndex 10 PIXI port --- N.C.
venkik 9:29c618fec8fc 1466 /// portIndex 12 PIXI port P7 Not used
venkik 9:29c618fec8fc 1467 /// portIndex 13 PIXI port P8 Not used
venkik 9:29c618fec8fc 1468 /// portIndex 17 PIXI port --- N.C.
venkik 9:29c618fec8fc 1469 /// portIndex 18 PIXI port --- N.C.
venkik 9:29c618fec8fc 1470 /// portIndex 19 PIXI port --- N.C.
venkik 9:29c618fec8fc 1471 /// PIXI ports to configure as Mode 1 GPIOinPgmThreshold:
venkik 9:29c618fec8fc 1472 /// none
venkik 9:29c618fec8fc 1473 /// PIXI ports to configure as Mode 2 GPIOinOutBidirLevelTrans:
venkik 9:29c618fec8fc 1474 /// none
venkik 9:29c618fec8fc 1475 /// PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel:
venkik 9:29c618fec8fc 1476 /// none
venkik 9:29c618fec8fc 1477 /// PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel:
venkik 9:29c618fec8fc 1478 /// none
venkik 9:29c618fec8fc 1479 /// PIXI ports to configure as Mode 5 DACout:
venkik 9:29c618fec8fc 1480 /// portIndex 5 PIXI port P3 DAC for setting the low current
venkik 9:29c618fec8fc 1481 /// portIndex 7 PIXI port P5 DAC for setting the high current
venkik 9:29c618fec8fc 1482 /// portIndex 14 PIXI port P9 Clamp for lower limit curve
venkik 9:29c618fec8fc 1483 /// portIndex 15 PIXI port P10 Clamp for higher limit curve
venkik 9:29c618fec8fc 1484 /// portIndex 16 PIXI port P11 DAC for driving ramp generator
venkik 9:29c618fec8fc 1485 /// PIXI ports to configure as Mode 6 DACoutWithADCmonitor:
venkik 9:29c618fec8fc 1486 /// none
venkik 9:29c618fec8fc 1487 /// PIXI ports to configure as Mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1488 /// portIndex 2 PIXI port P0 Differential in+ for measuring the source voltage
venkik 9:29c618fec8fc 1489 /// portIndex 4 PIXI port P2 ADC for measuring the low current
venkik 9:29c618fec8fc 1490 /// portIndex 6 PIXI port P4 Input for dynamic current control
venkik 9:29c618fec8fc 1491 /// portIndex 11 PIXI port P6 ADC for measuring the low current
venkik 9:29c618fec8fc 1492 /// PIXI ports to configure as Mode 8 ADCinPosDifferential:
venkik 9:29c618fec8fc 1493 /// none
venkik 9:29c618fec8fc 1494 /// PIXI ports to configure as Mode 9 ADCinNegDifferential:
venkik 9:29c618fec8fc 1495 /// none
venkik 9:29c618fec8fc 1496 /// PIXI ports to configure as Mode 10 DACoutADCinNegDifferential:
venkik 9:29c618fec8fc 1497 /// none
venkik 9:29c618fec8fc 1498 /// PIXI ports to configure as Mode 11 GPIOBidirAnalogSwitchExtControlled:
venkik 9:29c618fec8fc 1499 /// none
venkik 9:29c618fec8fc 1500 /// PIXI ports to configure as Mode 12 GPIOBidirAnalogSwitch:
venkik 9:29c618fec8fc 1501 /// none
venkik 9:29c618fec8fc 1502 /// PIXI ports to configure as Mode 13 Reserved13:
venkik 9:29c618fec8fc 1503 /// none
venkik 9:29c618fec8fc 1504 /// PIXI ports to configure as Mode 14 Reserved14:
venkik 9:29c618fec8fc 1505 /// none
venkik 9:29c618fec8fc 1506 /// PIXI ports to configure as Mode 15 Reserved15:
venkik 9:29c618fec8fc 1507 /// none
venkik 9:29c618fec8fc 1508 ///
venkik 9:29c618fec8fc 1509 inline void MAX11311init()
venkik 9:29c618fec8fc 1510 {
venkik 9:29c618fec8fc 1511 // SPI.begin();
venkik 9:29c618fec8fc 1512 // extern bool MAX11311regWrite(int regAddress8, int regData16);
venkik 9:29c618fec8fc 1513 // extern void MAX11311initDelayus(int delay_us);
venkik 9:29c618fec8fc 1514
venkik 9:29c618fec8fc 1515 // ------------------------------------------------------
venkik 9:29c618fec8fc 1516 // Soft Reset device registers by device_control 8000_RESET
venkik 9:29c618fec8fc 1517 // ------------------------------------------------------
venkik 9:29c618fec8fc 1518 MAX11300regWrite(device_control, 0x8000); // 1xxx xxxx xxxx xxxx RESET Soft reset command
venkik 9:29c618fec8fc 1519
venkik 9:29c618fec8fc 1520 // ------------------------------------------------------
venkik 9:29c618fec8fc 1521 // FLOWCHART: "Configure device_control 4000_BRST, 0080_THSHDN, 0030_ADCCONV"
venkik 9:29c618fec8fc 1522 // ------------------------------------------------------
venkik 9:29c618fec8fc 1523 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40B0));
venkik 9:29c618fec8fc 1524
venkik 9:29c618fec8fc 1525 // ------------------------------------------------------
venkik 9:29c618fec8fc 1526 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?"
venkik 9:29c618fec8fc 1527 // ------------------------------------------------------
venkik 9:29c618fec8fc 1528 // PIXI ports to configure as Mode 1 GPIOinPgmThreshold:
venkik 9:29c618fec8fc 1529 // none
venkik 9:29c618fec8fc 1530 // PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel:
venkik 9:29c618fec8fc 1531 // none
venkik 9:29c618fec8fc 1532 // PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel:
venkik 9:29c618fec8fc 1533 // none
venkik 9:29c618fec8fc 1534 // PIXI ports to configure as Mode 5 DACout:
venkik 9:29c618fec8fc 1535 // portIndex 5 PIXI port P3 DAC for setting the low current
venkik 9:29c618fec8fc 1536 // portIndex 7 PIXI port P5 DAC for setting the high current
venkik 9:29c618fec8fc 1537 // portIndex 14 PIXI port P9 Clamp for lower limit curve
venkik 9:29c618fec8fc 1538 // portIndex 15 PIXI port P10 Clamp for higher limit curve
venkik 9:29c618fec8fc 1539 // portIndex 16 PIXI port P11 DAC for driving ramp generator
venkik 9:29c618fec8fc 1540 // PIXI ports to configure as Mode 6 DACoutWithADCmonitor:
venkik 9:29c618fec8fc 1541 // none
venkik 9:29c618fec8fc 1542 // PIXI ports to configure as Mode 10 DACoutADCinNegDifferential:
venkik 9:29c618fec8fc 1543 // none
venkik 9:29c618fec8fc 1544 // ------------------------------------------------------
venkik 9:29c618fec8fc 1545 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1546 // FLOWCHART: "Configure device_control 0040_DACREF, 000C_DACCTL"
venkik 9:29c618fec8fc 1547 // ------------------------------------------------------
venkik 9:29c618fec8fc 1548 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FC));
venkik 9:29c618fec8fc 1549
venkik 9:29c618fec8fc 1550 // ------------------------------------------------------
venkik 9:29c618fec8fc 1551 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1552 // FLOWCHART: "Wait 200us"
venkik 9:29c618fec8fc 1553 // ------------------------------------------------------
venkik 9:29c618fec8fc 1554 MAX11300initDelayus(200);
venkik 9:29c618fec8fc 1555
venkik 9:29c618fec8fc 1556 // ------------------------------------------------------
venkik 9:29c618fec8fc 1557 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1558 // Configure DACDAT[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1559 // portIndex 5 PIXI port P3 DAC for setting the low current
venkik 9:29c618fec8fc 1560 // ------------------------------------------------------
venkik 9:29c618fec8fc 1561 MAX11300regWrite(dac_data_port_p3, dac_data_port_p3_DESIGNVALUE);
venkik 9:29c618fec8fc 1562
venkik 9:29c618fec8fc 1563 // ------------------------------------------------------
venkik 9:29c618fec8fc 1564 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1565 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1566 // ------------------------------------------------------
venkik 9:29c618fec8fc 1567 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1568
venkik 9:29c618fec8fc 1569 // ------------------------------------------------------
venkik 9:29c618fec8fc 1570 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1571 // Configure DACDAT[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1572 // portIndex 7 PIXI port P5 DAC for setting the high current
venkik 9:29c618fec8fc 1573 // ------------------------------------------------------
venkik 9:29c618fec8fc 1574 MAX11300regWrite(dac_data_port_p5, dac_data_port_p5_DESIGNVALUE);
venkik 9:29c618fec8fc 1575
venkik 9:29c618fec8fc 1576 // ------------------------------------------------------
venkik 9:29c618fec8fc 1577 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1578 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1579 // ------------------------------------------------------
venkik 9:29c618fec8fc 1580 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1581
venkik 9:29c618fec8fc 1582 // ------------------------------------------------------
venkik 9:29c618fec8fc 1583 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1584 // Configure DACDAT[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1585 // portIndex 14 PIXI port P9 Clamp for lower limit curve
venkik 9:29c618fec8fc 1586 // ------------------------------------------------------
venkik 9:29c618fec8fc 1587 MAX11300regWrite(dac_data_port_p9, dac_data_port_p9_DESIGNVALUE);
venkik 9:29c618fec8fc 1588
venkik 9:29c618fec8fc 1589 // ------------------------------------------------------
venkik 9:29c618fec8fc 1590 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1591 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1592 // ------------------------------------------------------
venkik 9:29c618fec8fc 1593 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1594
venkik 9:29c618fec8fc 1595 // ------------------------------------------------------
venkik 9:29c618fec8fc 1596 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1597 // Configure DACDAT[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1598 // portIndex 15 PIXI port P10 Clamp for higher limit curve
venkik 9:29c618fec8fc 1599 // ------------------------------------------------------
venkik 9:29c618fec8fc 1600 MAX11300regWrite(dac_data_port_p10, dac_data_port_p10_DESIGNVALUE);
venkik 9:29c618fec8fc 1601
venkik 9:29c618fec8fc 1602 // ------------------------------------------------------
venkik 9:29c618fec8fc 1603 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1604 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1605 // ------------------------------------------------------
venkik 9:29c618fec8fc 1606 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1607
venkik 9:29c618fec8fc 1608 // ------------------------------------------------------
venkik 9:29c618fec8fc 1609 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1610 // Configure DACDAT[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1611 // portIndex 16 PIXI port P11 DAC for driving ramp generator
venkik 9:29c618fec8fc 1612 // ------------------------------------------------------
venkik 9:29c618fec8fc 1613 MAX11300regWrite(dac_data_port_p11, dac_data_port_p11_DESIGNVALUE);
venkik 9:29c618fec8fc 1614
venkik 9:29c618fec8fc 1615 // ------------------------------------------------------
venkik 9:29c618fec8fc 1616 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1617 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1618 // ------------------------------------------------------
venkik 9:29c618fec8fc 1619 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1620
venkik 9:29c618fec8fc 1621
venkik 9:29c618fec8fc 1622 // ------------------------------------------------------
venkik 9:29c618fec8fc 1623 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1624 // FLOWCHART: "Enter DACPRSTDAT1 or DACPRSTDAT2"
venkik 9:29c618fec8fc 1625 // ------------------------------------------------------
venkik 9:29c618fec8fc 1626 MAX11300regWrite(dac_preset_data_1, dac_preset_data_1_DESIGNVALUE);
venkik 9:29c618fec8fc 1627 MAX11300regWrite(dac_preset_data_2, dac_preset_data_2_DESIGNVALUE);
venkik 9:29c618fec8fc 1628
venkik 9:29c618fec8fc 1629 // ------------------------------------------------------
venkik 9:29c618fec8fc 1630 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1631 // FLOWCHART: "Wait 200us x number of ports in mode 1"
venkik 9:29c618fec8fc 1632 // ------------------------------------------------------
venkik 9:29c618fec8fc 1633
venkik 9:29c618fec8fc 1634 // ------------------------------------------------------
venkik 9:29c618fec8fc 1635 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1636 // FLOWCHART: "Configure GPODAT[i] for ports in mode 3"
venkik 9:29c618fec8fc 1637 // ------------------------------------------------------
venkik 9:29c618fec8fc 1638
venkik 9:29c618fec8fc 1639 // ------------------------------------------------------
venkik 9:29c618fec8fc 1640 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1641 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1642 // portIndex 5 PIXI port P3 DAC for setting the low current
venkik 9:29c618fec8fc 1643 // ------------------------------------------------------
venkik 9:29c618fec8fc 1644 MAX11300regWrite(port_cfg_p3, port_cfg_p3_DESIGNVALUE);
venkik 9:29c618fec8fc 1645
venkik 9:29c618fec8fc 1646 // ------------------------------------------------------
venkik 9:29c618fec8fc 1647 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1648 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1649 // ------------------------------------------------------
venkik 9:29c618fec8fc 1650 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1651
venkik 9:29c618fec8fc 1652 // ------------------------------------------------------
venkik 9:29c618fec8fc 1653 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1654 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1655 // portIndex 7 PIXI port P5 DAC for setting the high current
venkik 9:29c618fec8fc 1656 // ------------------------------------------------------
venkik 9:29c618fec8fc 1657 MAX11300regWrite(port_cfg_p5, port_cfg_p5_DESIGNVALUE);
venkik 9:29c618fec8fc 1658
venkik 9:29c618fec8fc 1659 // ------------------------------------------------------
venkik 9:29c618fec8fc 1660 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1661 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1662 // ------------------------------------------------------
venkik 9:29c618fec8fc 1663 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1664
venkik 9:29c618fec8fc 1665 // ------------------------------------------------------
venkik 9:29c618fec8fc 1666 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1667 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1668 // portIndex 14 PIXI port P9 Clamp for lower limit curve
venkik 9:29c618fec8fc 1669 // ------------------------------------------------------
venkik 9:29c618fec8fc 1670 MAX11300regWrite(port_cfg_p9, port_cfg_p9_DESIGNVALUE);
venkik 9:29c618fec8fc 1671
venkik 9:29c618fec8fc 1672 // ------------------------------------------------------
venkik 9:29c618fec8fc 1673 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1674 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1675 // ------------------------------------------------------
venkik 9:29c618fec8fc 1676 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1677
venkik 9:29c618fec8fc 1678 // ------------------------------------------------------
venkik 9:29c618fec8fc 1679 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1680 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1681 // portIndex 15 PIXI port P10 Clamp for higher limit curve
venkik 9:29c618fec8fc 1682 // ------------------------------------------------------
venkik 9:29c618fec8fc 1683 MAX11300regWrite(port_cfg_p10, port_cfg_p10_DESIGNVALUE);
venkik 9:29c618fec8fc 1684
venkik 9:29c618fec8fc 1685 // ------------------------------------------------------
venkik 9:29c618fec8fc 1686 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1687 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1688 // ------------------------------------------------------
venkik 9:29c618fec8fc 1689 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1690
venkik 9:29c618fec8fc 1691 // ------------------------------------------------------
venkik 9:29c618fec8fc 1692 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1693 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
venkik 9:29c618fec8fc 1694 // portIndex 16 PIXI port P11 DAC for driving ramp generator
venkik 9:29c618fec8fc 1695 // ------------------------------------------------------
venkik 9:29c618fec8fc 1696 MAX11300regWrite(port_cfg_p11, port_cfg_p11_DESIGNVALUE);
venkik 9:29c618fec8fc 1697
venkik 9:29c618fec8fc 1698 // ------------------------------------------------------
venkik 9:29c618fec8fc 1699 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1700 // FLOWCHART: "Wait 1ms"
venkik 9:29c618fec8fc 1701 // ------------------------------------------------------
venkik 9:29c618fec8fc 1702 MAX11300initDelayus(1000);
venkik 9:29c618fec8fc 1703
venkik 9:29c618fec8fc 1704 // ------------------------------------------------------
venkik 9:29c618fec8fc 1705 // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
venkik 9:29c618fec8fc 1706 // FLOWCHART: "Configure GPIMD[i] for ports in mode 1"
venkik 9:29c618fec8fc 1707 // ------------------------------------------------------
venkik 9:29c618fec8fc 1708 MAX11300regWrite(gpi_irqmode_P5_P0, gpi_irqmode_P5_P0_DESIGNVALUE);
venkik 9:29c618fec8fc 1709 MAX11300regWrite(gpi_irqmode_P10_P6, gpi_irqmode_P10_P6_DESIGNVALUE);
venkik 9:29c618fec8fc 1710 MAX11300regWrite(gpi_irqmode_P11, gpi_irqmode_P11_DESIGNVALUE);
venkik 9:29c618fec8fc 1711
venkik 9:29c618fec8fc 1712
venkik 9:29c618fec8fc 1713 // ------------------------------------------------------
venkik 9:29c618fec8fc 1714 // FLOWCHART: decision "Is mode 7, 8, or 9 used?"
venkik 9:29c618fec8fc 1715 // ------------------------------------------------------
venkik 9:29c618fec8fc 1716 // PIXI ports to configure as Mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1717 // portIndex 2 PIXI port P0 Differential in+ for measuring the source voltage
venkik 9:29c618fec8fc 1718 // portIndex 4 PIXI port P2 ADC for measuring the low current
venkik 9:29c618fec8fc 1719 // portIndex 6 PIXI port P4 Input for dynamic current control
venkik 9:29c618fec8fc 1720 // portIndex 11 PIXI port P6 ADC for measuring the low current
venkik 9:29c618fec8fc 1721 // PIXI ports to configure as Mode 8 ADCinPosDifferential:
venkik 9:29c618fec8fc 1722 // none
venkik 9:29c618fec8fc 1723 // PIXI ports to configure as Mode 9 ADCinNegDifferential:
venkik 9:29c618fec8fc 1724 // none
venkik 9:29c618fec8fc 1725 // ------------------------------------------------------
venkik 9:29c618fec8fc 1726 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1727 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1728 // portIndex 2 PIXI port P0 Differential in+ for measuring the source voltage
venkik 9:29c618fec8fc 1729 // ------------------------------------------------------
venkik 9:29c618fec8fc 1730 MAX11300regWrite(port_cfg_p0, port_cfg_p0_DESIGNVALUE);
venkik 9:29c618fec8fc 1731
venkik 9:29c618fec8fc 1732 // ------------------------------------------------------
venkik 9:29c618fec8fc 1733 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1734 // FLOWCHART: "Wait 100us"
venkik 9:29c618fec8fc 1735 // ------------------------------------------------------
venkik 9:29c618fec8fc 1736 MAX11300initDelayus(100);
venkik 9:29c618fec8fc 1737
venkik 9:29c618fec8fc 1738 // ------------------------------------------------------
venkik 9:29c618fec8fc 1739 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1740 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1741 // portIndex 4 PIXI port P2 ADC for measuring the low current
venkik 9:29c618fec8fc 1742 // ------------------------------------------------------
venkik 9:29c618fec8fc 1743 MAX11300regWrite(port_cfg_p2, port_cfg_p2_DESIGNVALUE);
venkik 9:29c618fec8fc 1744
venkik 9:29c618fec8fc 1745 // ------------------------------------------------------
venkik 9:29c618fec8fc 1746 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1747 // FLOWCHART: "Wait 100us"
venkik 9:29c618fec8fc 1748 // ------------------------------------------------------
venkik 9:29c618fec8fc 1749 MAX11300initDelayus(100);
venkik 9:29c618fec8fc 1750
venkik 9:29c618fec8fc 1751 // ------------------------------------------------------
venkik 9:29c618fec8fc 1752 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1753 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1754 // portIndex 6 PIXI port P4 Input for dynamic current control
venkik 9:29c618fec8fc 1755 // ------------------------------------------------------
venkik 9:29c618fec8fc 1756 MAX11300regWrite(port_cfg_p4, port_cfg_p4_DESIGNVALUE);
venkik 9:29c618fec8fc 1757
venkik 9:29c618fec8fc 1758 // ------------------------------------------------------
venkik 9:29c618fec8fc 1759 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1760 // FLOWCHART: "Wait 100us"
venkik 9:29c618fec8fc 1761 // ------------------------------------------------------
venkik 9:29c618fec8fc 1762 MAX11300initDelayus(100);
venkik 9:29c618fec8fc 1763
venkik 9:29c618fec8fc 1764 // ------------------------------------------------------
venkik 9:29c618fec8fc 1765 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1766 // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded:
venkik 9:29c618fec8fc 1767 // portIndex 11 PIXI port P6 ADC for measuring the low current
venkik 9:29c618fec8fc 1768 // ------------------------------------------------------
venkik 9:29c618fec8fc 1769 MAX11300regWrite(port_cfg_p6, port_cfg_p6_DESIGNVALUE);
venkik 9:29c618fec8fc 1770
venkik 9:29c618fec8fc 1771 // ------------------------------------------------------
venkik 9:29c618fec8fc 1772 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1773 // FLOWCHART: "Wait 100us"
venkik 9:29c618fec8fc 1774 // ------------------------------------------------------
venkik 9:29c618fec8fc 1775 MAX11300initDelayus(100);
venkik 9:29c618fec8fc 1776
venkik 9:29c618fec8fc 1777 // ------------------------------------------------------
venkik 9:29c618fec8fc 1778 // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
venkik 9:29c618fec8fc 1779 // FLOWCHART: "Configure device_control 0003_ADCCTL"
venkik 9:29c618fec8fc 1780 // ------------------------------------------------------
venkik 9:29c618fec8fc 1781 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FF));
venkik 9:29c618fec8fc 1782
venkik 9:29c618fec8fc 1783
venkik 9:29c618fec8fc 1784 // ------------------------------------------------------
venkik 9:29c618fec8fc 1785 // FLOWCHART: decision "Is mode 2, 11, or 12 used?"
venkik 9:29c618fec8fc 1786 // ------------------------------------------------------
venkik 9:29c618fec8fc 1787
venkik 9:29c618fec8fc 1788 // ------------------------------------------------------
venkik 9:29c618fec8fc 1789 // FLOWCHART: decision "Are temperature sensors used?"
venkik 9:29c618fec8fc 1790 // ------------------------------------------------------
venkik 9:29c618fec8fc 1791 // ------------------------------------------------------
venkik 9:29c618fec8fc 1792 // FLOWCHART: decision "Are temperature sensors used?" branch "Y"
venkik 9:29c618fec8fc 1793 // FLOWCHART: "Configure device_control 0800_TMPPER"
venkik 9:29c618fec8fc 1794 // ------------------------------------------------------
venkik 9:29c618fec8fc 1795 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x48FF));
venkik 9:29c618fec8fc 1796
venkik 9:29c618fec8fc 1797 // ------------------------------------------------------
venkik 9:29c618fec8fc 1798 // FLOWCHART: decision "Are temperature sensors used?" branch "Y"
venkik 9:29c618fec8fc 1799 // FLOWCHART: "Configure device_control 1000_RS_CANCEL"
venkik 9:29c618fec8fc 1800 // ------------------------------------------------------
venkik 9:29c618fec8fc 1801 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x58FF));
venkik 9:29c618fec8fc 1802
venkik 9:29c618fec8fc 1803 // ------------------------------------------------------
venkik 9:29c618fec8fc 1804 // FLOWCHART: decision "Are temperature sensors used?" branch "Y"
venkik 9:29c618fec8fc 1805 // FLOWCHART: "Configure tmp_mon_cfg"
venkik 9:29c618fec8fc 1806 // ------------------------------------------------------
venkik 9:29c618fec8fc 1807 MAX11300regWrite(tmp_mon_cfg, tmp_mon_cfg_DESIGNVALUE);
venkik 9:29c618fec8fc 1808
venkik 9:29c618fec8fc 1809 // ------------------------------------------------------
venkik 9:29c618fec8fc 1810 // FLOWCHART: decision "Are temperature sensors used?" branch "Y"
venkik 9:29c618fec8fc 1811 // FLOWCHART: "Configure TMPHI and TMPLO alarm thresholds"
venkik 9:29c618fec8fc 1812 // ------------------------------------------------------
venkik 9:29c618fec8fc 1813 MAX11300regWrite(tmp_mon_int_hi_thresh, tmp_mon_int_hi_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1814 MAX11300regWrite(tmp_mon_int_lo_thresh, tmp_mon_int_lo_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1815 MAX11300regWrite(tmp_mon_ext1_hi_thresh, tmp_mon_ext1_hi_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1816 MAX11300regWrite(tmp_mon_ext1_lo_thresh, tmp_mon_ext1_lo_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1817 MAX11300regWrite(tmp_mon_ext2_hi_thresh, tmp_mon_ext2_hi_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1818 MAX11300regWrite(tmp_mon_ext2_lo_thresh, tmp_mon_ext2_lo_thresh_DESIGNVALUE);
venkik 9:29c618fec8fc 1819
venkik 9:29c618fec8fc 1820 // ------------------------------------------------------
venkik 9:29c618fec8fc 1821 // FLOWCHART: decision "Are temperature sensors used?" branch "Y"
venkik 9:29c618fec8fc 1822 // FLOWCHART: "Configure device_control 0400_TMPCTL_EXT1, 0200_TMPCTL_EXT0, 0100_TMPCTL_INT"
venkik 9:29c618fec8fc 1823 // ------------------------------------------------------
venkik 9:29c618fec8fc 1824 MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x5FFF));
venkik 9:29c618fec8fc 1825
venkik 9:29c618fec8fc 1826
venkik 9:29c618fec8fc 1827 // ------------------------------------------------------
venkik 9:29c618fec8fc 1828 // Configure final device_control design value 2000_LPEN
venkik 9:29c618fec8fc 1829 // ------------------------------------------------------
venkik 9:29c618fec8fc 1830 MAX11300regWrite(device_control, (device_control_DESIGNVALUE));
venkik 9:29c618fec8fc 1831
venkik 9:29c618fec8fc 1832 // ------------------------------------------------------
venkik 9:29c618fec8fc 1833 // FLOWCHART: Configure Interrupt Masks
venkik 9:29c618fec8fc 1834 // ------------------------------------------------------
venkik 9:29c618fec8fc 1835 MAX11300regWrite(interrupt_mask, interrupt_mask_DESIGNVALUE);
venkik 9:29c618fec8fc 1836
venkik 9:29c618fec8fc 1837
venkik 9:29c618fec8fc 1838 }
venkik 9:29c618fec8fc 1839
venkik 9:29c618fec8fc 1840
venkik 9:29c618fec8fc 1841 #endif /* _MAX11311_DESIGNVALUE_H_ */
venkik 9:29c618fec8fc 1842
venkik 9:29c618fec8fc 1843 // End of file