SIMO PMIC with 300mA Switching Charger
MAX77659.cpp@0:047a7089311e, 2022-08-22 (annotated)
- Committer:
- Okan Sahin
- Date:
- Mon Aug 22 19:05:12 2022 +0300
- Revision:
- 0:047a7089311e
Initial Commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Okan Sahin |
0:047a7089311e | 1 | /******************************************************************************* |
Okan Sahin |
0:047a7089311e | 2 | * Copyright (C) 2022 Analog Devices, Inc., All rights Reserved. |
Okan Sahin |
0:047a7089311e | 3 | * |
Okan Sahin |
0:047a7089311e | 4 | * This software is protected by copyright laws of the United States and |
Okan Sahin |
0:047a7089311e | 5 | * of foreign countries. This material may also be protected by patent laws |
Okan Sahin |
0:047a7089311e | 6 | * and technology transfer regulations of the United States and of foreign |
Okan Sahin |
0:047a7089311e | 7 | * countries. This software is furnished under a license agreement and/or a |
Okan Sahin |
0:047a7089311e | 8 | * nondisclosure agreement and may only be used or reproduced in accordance |
Okan Sahin |
0:047a7089311e | 9 | * with the terms of those agreements. Dissemination of this information to |
Okan Sahin |
0:047a7089311e | 10 | * any party or parties not specified in the license agreement and/or |
Okan Sahin |
0:047a7089311e | 11 | * nondisclosure agreement is expressly prohibited. |
Okan Sahin |
0:047a7089311e | 12 | * |
Okan Sahin |
0:047a7089311e | 13 | * The above copyright notice and this permission notice shall be included |
Okan Sahin |
0:047a7089311e | 14 | * in all copies or substantial portions of the Software. |
Okan Sahin |
0:047a7089311e | 15 | * |
Okan Sahin |
0:047a7089311e | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Okan Sahin |
0:047a7089311e | 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Okan Sahin |
0:047a7089311e | 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Okan Sahin |
0:047a7089311e | 19 | * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES |
Okan Sahin |
0:047a7089311e | 20 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Okan Sahin |
0:047a7089311e | 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Okan Sahin |
0:047a7089311e | 22 | * OTHER DEALINGS IN THE SOFTWARE. |
Okan Sahin |
0:047a7089311e | 23 | * |
Okan Sahin |
0:047a7089311e | 24 | * Except as contained in this notice, the name of Maxim Integrated |
Okan Sahin |
0:047a7089311e | 25 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Okan Sahin |
0:047a7089311e | 26 | * Products, Inc. Branding Policy. |
Okan Sahin |
0:047a7089311e | 27 | * |
Okan Sahin |
0:047a7089311e | 28 | * The mere transfer of this software does not imply any licenses |
Okan Sahin |
0:047a7089311e | 29 | * of trade secrets, proprietary technology, copyrights, patents, |
Okan Sahin |
0:047a7089311e | 30 | * trademarks, maskwork rights, or any other form of intellectual |
Okan Sahin |
0:047a7089311e | 31 | * property whatsoever. Analog Devices, Inc. retains all |
Okan Sahin |
0:047a7089311e | 32 | * ownership rights. |
Okan Sahin |
0:047a7089311e | 33 | ******************************************************************************* |
Okan Sahin |
0:047a7089311e | 34 | */ |
Okan Sahin |
0:047a7089311e | 35 | |
Okan Sahin |
0:047a7089311e | 36 | #include <Thread.h> |
Okan Sahin |
0:047a7089311e | 37 | #include "MAX77659.h" |
Okan Sahin |
0:047a7089311e | 38 | #include <math.h> |
Okan Sahin |
0:047a7089311e | 39 | |
Okan Sahin |
0:047a7089311e | 40 | #define POST_INTR_WORK_SIGNAL_ID 0x1 |
Okan Sahin |
0:047a7089311e | 41 | #define TO_UINT8 0xFF |
Okan Sahin |
0:047a7089311e | 42 | #define TO_UINT16 0xFFFF |
Okan Sahin |
0:047a7089311e | 43 | |
Okan Sahin |
0:047a7089311e | 44 | MAX77659::MAX77659(I2C *i2c, PinName IRQPin) |
Okan Sahin |
0:047a7089311e | 45 | { |
Okan Sahin |
0:047a7089311e | 46 | if (i2c == NULL) |
Okan Sahin |
0:047a7089311e | 47 | return; |
Okan Sahin |
0:047a7089311e | 48 | |
Okan Sahin |
0:047a7089311e | 49 | i2c_handler = i2c; |
Okan Sahin |
0:047a7089311e | 50 | |
Okan Sahin |
0:047a7089311e | 51 | interrupt_handler_list = new handler[INT_CHG_END] {}; |
Okan Sahin |
0:047a7089311e | 52 | |
Okan Sahin |
0:047a7089311e | 53 | if (IRQPin != NC) { |
Okan Sahin |
0:047a7089311e | 54 | irq_disable_all(); |
Okan Sahin |
0:047a7089311e | 55 | post_intr_work_thread = new Thread(); |
Okan Sahin |
0:047a7089311e | 56 | post_intr_work_thread->start(Callback<void()>(this, &MAX77659::post_interrupt_work)); |
Okan Sahin |
0:047a7089311e | 57 | |
Okan Sahin |
0:047a7089311e | 58 | this->irq_pin = new InterruptIn(IRQPin); |
Okan Sahin |
0:047a7089311e | 59 | this->irq_pin->fall(Callback<void()>(this, &MAX77659::interrupt_handler)); |
Okan Sahin |
0:047a7089311e | 60 | this->irq_pin->enable_irq(); |
Okan Sahin |
0:047a7089311e | 61 | } else { |
Okan Sahin |
0:047a7089311e | 62 | this->irq_pin = NULL; |
Okan Sahin |
0:047a7089311e | 63 | } |
Okan Sahin |
0:047a7089311e | 64 | } |
Okan Sahin |
0:047a7089311e | 65 | |
Okan Sahin |
0:047a7089311e | 66 | MAX77659::~MAX77659() |
Okan Sahin |
0:047a7089311e | 67 | { |
Okan Sahin |
0:047a7089311e | 68 | if (post_intr_work_thread) |
Okan Sahin |
0:047a7089311e | 69 | delete post_intr_work_thread; |
Okan Sahin |
0:047a7089311e | 70 | |
Okan Sahin |
0:047a7089311e | 71 | if (irq_pin) |
Okan Sahin |
0:047a7089311e | 72 | delete irq_pin; |
Okan Sahin |
0:047a7089311e | 73 | |
Okan Sahin |
0:047a7089311e | 74 | if (interrupt_handler_list) |
Okan Sahin |
0:047a7089311e | 75 | delete [] interrupt_handler_list; |
Okan Sahin |
0:047a7089311e | 76 | } |
Okan Sahin |
0:047a7089311e | 77 | |
Okan Sahin |
0:047a7089311e | 78 | int MAX77659::read_register(uint8_t reg, uint8_t *value) |
Okan Sahin |
0:047a7089311e | 79 | { |
Okan Sahin |
0:047a7089311e | 80 | int rtn_val; |
Okan Sahin |
0:047a7089311e | 81 | |
Okan Sahin |
0:047a7089311e | 82 | if (value == NULL) |
Okan Sahin |
0:047a7089311e | 83 | return MAX77659_VALUE_NULL; |
Okan Sahin |
0:047a7089311e | 84 | |
Okan Sahin |
0:047a7089311e | 85 | rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)®, 1, true); |
Okan Sahin |
0:047a7089311e | 86 | if (rtn_val != MAX77659_NO_ERROR) |
Okan Sahin |
0:047a7089311e | 87 | return MAX77659_WRITE_DATA_FAILED; |
Okan Sahin |
0:047a7089311e | 88 | |
Okan Sahin |
0:047a7089311e | 89 | rtn_val = i2c_handler->read(MAX77659_I2C_ADDRESS, (char *) value, 1, false); |
Okan Sahin |
0:047a7089311e | 90 | if (rtn_val != MAX77659_NO_ERROR) |
Okan Sahin |
0:047a7089311e | 91 | return MAX77659_READ_DATA_FAILED; |
Okan Sahin |
0:047a7089311e | 92 | |
Okan Sahin |
0:047a7089311e | 93 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 94 | } |
Okan Sahin |
0:047a7089311e | 95 | |
Okan Sahin |
0:047a7089311e | 96 | int MAX77659::write_register(uint8_t reg, const uint8_t *value) |
Okan Sahin |
0:047a7089311e | 97 | { |
Okan Sahin |
0:047a7089311e | 98 | int rtn_val; |
Okan Sahin |
0:047a7089311e | 99 | unsigned char local_data[2] = {0}; |
Okan Sahin |
0:047a7089311e | 100 | |
Okan Sahin |
0:047a7089311e | 101 | if (value == NULL) |
Okan Sahin |
0:047a7089311e | 102 | return MAX77659_VALUE_NULL; |
Okan Sahin |
0:047a7089311e | 103 | |
Okan Sahin |
0:047a7089311e | 104 | local_data[0] = reg; |
Okan Sahin |
0:047a7089311e | 105 | |
Okan Sahin |
0:047a7089311e | 106 | memcpy(&local_data[1], value, 1); |
Okan Sahin |
0:047a7089311e | 107 | |
Okan Sahin |
0:047a7089311e | 108 | rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)local_data, sizeof(local_data)); |
Okan Sahin |
0:047a7089311e | 109 | if (rtn_val != MAX77659_NO_ERROR) |
Okan Sahin |
0:047a7089311e | 110 | return MAX77659_WRITE_DATA_FAILED; |
Okan Sahin |
0:047a7089311e | 111 | |
Okan Sahin |
0:047a7089311e | 112 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 113 | } |
Okan Sahin |
0:047a7089311e | 114 | |
Okan Sahin |
0:047a7089311e | 115 | #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \ |
Okan Sahin |
0:047a7089311e | 116 | int ret_val; \ |
Okan Sahin |
0:047a7089311e | 117 | ret_val = read_register(address, (uint8_t *)&(reg_name)); \ |
Okan Sahin |
0:047a7089311e | 118 | if (ret_val) { \ |
Okan Sahin |
0:047a7089311e | 119 | return ret_val; \ |
Okan Sahin |
0:047a7089311e | 120 | } \ |
Okan Sahin |
0:047a7089311e | 121 | bit_field_name = value; \ |
Okan Sahin |
0:047a7089311e | 122 | ret_val = write_register(address, (uint8_t *)&(reg_name)); \ |
Okan Sahin |
0:047a7089311e | 123 | if (ret_val) { \ |
Okan Sahin |
0:047a7089311e | 124 | return ret_val; \ |
Okan Sahin |
0:047a7089311e | 125 | } |
Okan Sahin |
0:047a7089311e | 126 | |
Okan Sahin |
0:047a7089311e | 127 | int MAX77659::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag) |
Okan Sahin |
0:047a7089311e | 128 | { |
Okan Sahin |
0:047a7089311e | 129 | int ret; |
Okan Sahin |
0:047a7089311e | 130 | reg_ercflag_t reg_ercflag = {0}; |
Okan Sahin |
0:047a7089311e | 131 | |
Okan Sahin |
0:047a7089311e | 132 | ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag)); |
Okan Sahin |
0:047a7089311e | 133 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 134 | |
Okan Sahin |
0:047a7089311e | 135 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 136 | { |
Okan Sahin |
0:047a7089311e | 137 | case ERCFLAG_TOVLD: |
Okan Sahin |
0:047a7089311e | 138 | *flag = (uint8_t)reg_ercflag.bits.tovld; |
Okan Sahin |
0:047a7089311e | 139 | break; |
Okan Sahin |
0:047a7089311e | 140 | case ERCFLAG_SYSOVLO: |
Okan Sahin |
0:047a7089311e | 141 | *flag = (uint8_t)reg_ercflag.bits.sysovlo; |
Okan Sahin |
0:047a7089311e | 142 | break; |
Okan Sahin |
0:047a7089311e | 143 | case ERCFLAG_AVLUVLO: |
Okan Sahin |
0:047a7089311e | 144 | *flag = (uint8_t)reg_ercflag.bits.avluvlo; |
Okan Sahin |
0:047a7089311e | 145 | break; |
Okan Sahin |
0:047a7089311e | 146 | case ERCFLAG_MRST: |
Okan Sahin |
0:047a7089311e | 147 | *flag = (uint8_t)reg_ercflag.bits.mrst; |
Okan Sahin |
0:047a7089311e | 148 | break; |
Okan Sahin |
0:047a7089311e | 149 | case ERCFLAG_SFT_OFF_F: |
Okan Sahin |
0:047a7089311e | 150 | *flag = (uint8_t)reg_ercflag.bits.sft_off_f; |
Okan Sahin |
0:047a7089311e | 151 | break; |
Okan Sahin |
0:047a7089311e | 152 | case ERCFLAG_SFT_CRST_F: |
Okan Sahin |
0:047a7089311e | 153 | *flag = (uint8_t)reg_ercflag.bits.sft_crst_f; |
Okan Sahin |
0:047a7089311e | 154 | break; |
Okan Sahin |
0:047a7089311e | 155 | case ERCFLAG_WDT_OFF: |
Okan Sahin |
0:047a7089311e | 156 | *flag = (uint8_t)reg_ercflag.bits.wdt_off; |
Okan Sahin |
0:047a7089311e | 157 | break; |
Okan Sahin |
0:047a7089311e | 158 | case ERCFLAG_WDT_RST: |
Okan Sahin |
0:047a7089311e | 159 | *flag = (uint8_t)reg_ercflag.bits.wdt_rst; |
Okan Sahin |
0:047a7089311e | 160 | break; |
Okan Sahin |
0:047a7089311e | 161 | default: |
Okan Sahin |
0:047a7089311e | 162 | ret = MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 163 | break; |
Okan Sahin |
0:047a7089311e | 164 | } |
Okan Sahin |
0:047a7089311e | 165 | |
Okan Sahin |
0:047a7089311e | 166 | return ret; |
Okan Sahin |
0:047a7089311e | 167 | } |
Okan Sahin |
0:047a7089311e | 168 | |
Okan Sahin |
0:047a7089311e | 169 | int MAX77659::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status) |
Okan Sahin |
0:047a7089311e | 170 | { |
Okan Sahin |
0:047a7089311e | 171 | int ret; |
Okan Sahin |
0:047a7089311e | 172 | reg_stat_glbl_t reg_stat_glbl = {0}; |
Okan Sahin |
0:047a7089311e | 173 | |
Okan Sahin |
0:047a7089311e | 174 | ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl)); |
Okan Sahin |
0:047a7089311e | 175 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 176 | |
Okan Sahin |
0:047a7089311e | 177 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 178 | { |
Okan Sahin |
0:047a7089311e | 179 | case STAT_GLBL_STAT_IRQ: |
Okan Sahin |
0:047a7089311e | 180 | *status = (uint8_t)reg_stat_glbl.bits.stat_irq; |
Okan Sahin |
0:047a7089311e | 181 | break; |
Okan Sahin |
0:047a7089311e | 182 | case STAT_GLBL_STAT_EN: |
Okan Sahin |
0:047a7089311e | 183 | *status = (uint8_t)reg_stat_glbl.bits.stat_en; |
Okan Sahin |
0:047a7089311e | 184 | break; |
Okan Sahin |
0:047a7089311e | 185 | case STAT_GLBL_TJAL1_S: |
Okan Sahin |
0:047a7089311e | 186 | *status = (uint8_t)reg_stat_glbl.bits.tjal1_s; |
Okan Sahin |
0:047a7089311e | 187 | break; |
Okan Sahin |
0:047a7089311e | 188 | case STAT_GLBL_TJAL2_S: |
Okan Sahin |
0:047a7089311e | 189 | *status = (uint8_t)reg_stat_glbl.bits.tjal2_s; |
Okan Sahin |
0:047a7089311e | 190 | break; |
Okan Sahin |
0:047a7089311e | 191 | case STAT_GLBL_RSVD: |
Okan Sahin |
0:047a7089311e | 192 | *status = (uint8_t)reg_stat_glbl.bits.rsvd; |
Okan Sahin |
0:047a7089311e | 193 | break; |
Okan Sahin |
0:047a7089311e | 194 | case STAT_GLBL_DOD_S: |
Okan Sahin |
0:047a7089311e | 195 | *status = (uint8_t)reg_stat_glbl.bits.dod_s; |
Okan Sahin |
0:047a7089311e | 196 | break; |
Okan Sahin |
0:047a7089311e | 197 | case STAT_GLBL_BOK: |
Okan Sahin |
0:047a7089311e | 198 | *status = (uint8_t)reg_stat_glbl.bits.bok; |
Okan Sahin |
0:047a7089311e | 199 | break; |
Okan Sahin |
0:047a7089311e | 200 | case STAT_GLBL_DIDM: |
Okan Sahin |
0:047a7089311e | 201 | *status = (uint8_t)reg_stat_glbl.bits.didm; |
Okan Sahin |
0:047a7089311e | 202 | break; |
Okan Sahin |
0:047a7089311e | 203 | default: |
Okan Sahin |
0:047a7089311e | 204 | ret = MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 205 | break; |
Okan Sahin |
0:047a7089311e | 206 | } |
Okan Sahin |
0:047a7089311e | 207 | |
Okan Sahin |
0:047a7089311e | 208 | return ret; |
Okan Sahin |
0:047a7089311e | 209 | } |
Okan Sahin |
0:047a7089311e | 210 | |
Okan Sahin |
0:047a7089311e | 211 | int MAX77659::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit) |
Okan Sahin |
0:047a7089311e | 212 | { |
Okan Sahin |
0:047a7089311e | 213 | int ret; |
Okan Sahin |
0:047a7089311e | 214 | uint8_t reg_addr; |
Okan Sahin |
0:047a7089311e | 215 | reg_int_m_chg_t reg_int_m_chg = {0}; |
Okan Sahin |
0:047a7089311e | 216 | reg_intm_glbl0_t reg_intm_glbl0 = {0}; |
Okan Sahin |
0:047a7089311e | 217 | reg_intm_glbl1_t reg_intm_glbl1 = {0}; |
Okan Sahin |
0:047a7089311e | 218 | |
Okan Sahin |
0:047a7089311e | 219 | //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09) |
Okan Sahin |
0:047a7089311e | 220 | reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07; |
Okan Sahin |
0:047a7089311e | 221 | |
Okan Sahin |
0:047a7089311e | 222 | if (reg_addr == INT_M_CHG) |
Okan Sahin |
0:047a7089311e | 223 | ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); |
Okan Sahin |
0:047a7089311e | 224 | else if (reg_addr == INTM_GLBL0) |
Okan Sahin |
0:047a7089311e | 225 | ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); |
Okan Sahin |
0:047a7089311e | 226 | else if (reg_addr == INTM_GLBL1) |
Okan Sahin |
0:047a7089311e | 227 | ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); |
Okan Sahin |
0:047a7089311e | 228 | else |
Okan Sahin |
0:047a7089311e | 229 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 230 | |
Okan Sahin |
0:047a7089311e | 231 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 232 | |
Okan Sahin |
0:047a7089311e | 233 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 234 | { |
Okan Sahin |
0:047a7089311e | 235 | case INT_M_CHG_THM_M: |
Okan Sahin |
0:047a7089311e | 236 | reg_int_m_chg.bits.thm_m = maskBit; |
Okan Sahin |
0:047a7089311e | 237 | break; |
Okan Sahin |
0:047a7089311e | 238 | case INT_M_CHG_CHG_M: |
Okan Sahin |
0:047a7089311e | 239 | reg_int_m_chg.bits.chg_m = maskBit; |
Okan Sahin |
0:047a7089311e | 240 | break; |
Okan Sahin |
0:047a7089311e | 241 | case INT_M_CHG_CHGIN_M: |
Okan Sahin |
0:047a7089311e | 242 | reg_int_m_chg.bits.chgin_m = maskBit; |
Okan Sahin |
0:047a7089311e | 243 | break; |
Okan Sahin |
0:047a7089311e | 244 | case INT_M_CHG_TJ_REG_M: |
Okan Sahin |
0:047a7089311e | 245 | reg_int_m_chg.bits.tj_reg_m = maskBit; |
Okan Sahin |
0:047a7089311e | 246 | break; |
Okan Sahin |
0:047a7089311e | 247 | case INT_M_CHG_SYS_CTRL_M: |
Okan Sahin |
0:047a7089311e | 248 | reg_int_m_chg.bits.sys_ctrl_m = maskBit; |
Okan Sahin |
0:047a7089311e | 249 | break; |
Okan Sahin |
0:047a7089311e | 250 | case INTM_GLBL0_GPI0_FM: |
Okan Sahin |
0:047a7089311e | 251 | reg_intm_glbl0.bits.gpi0_fm = maskBit; |
Okan Sahin |
0:047a7089311e | 252 | break; |
Okan Sahin |
0:047a7089311e | 253 | case INTM_GLBL1_GPI1_FM: |
Okan Sahin |
0:047a7089311e | 254 | reg_intm_glbl1.bits.gpi1_fm = maskBit; |
Okan Sahin |
0:047a7089311e | 255 | break; |
Okan Sahin |
0:047a7089311e | 256 | case INTM_GLBL1_GPI1_RM: |
Okan Sahin |
0:047a7089311e | 257 | reg_intm_glbl1.bits.gpi1_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 258 | break; |
Okan Sahin |
0:047a7089311e | 259 | case INTM_GLBL1_SBB_TO_M: |
Okan Sahin |
0:047a7089311e | 260 | reg_intm_glbl1.bits.sbb_to_m = maskBit; |
Okan Sahin |
0:047a7089311e | 261 | break; |
Okan Sahin |
0:047a7089311e | 262 | case INTM_GLBL1_LDO_M: |
Okan Sahin |
0:047a7089311e | 263 | reg_intm_glbl1.bits.ldo_m = maskBit; |
Okan Sahin |
0:047a7089311e | 264 | break; |
Okan Sahin |
0:047a7089311e | 265 | case INTM_GLBL0_GPI0_RM: |
Okan Sahin |
0:047a7089311e | 266 | reg_intm_glbl0.bits.gpi0_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 267 | break; |
Okan Sahin |
0:047a7089311e | 268 | case INTM_GLBL0_nEN_FM: |
Okan Sahin |
0:047a7089311e | 269 | reg_intm_glbl0.bits.nen_fm = maskBit; |
Okan Sahin |
0:047a7089311e | 270 | break; |
Okan Sahin |
0:047a7089311e | 271 | case INTM_GLBL0_nEN_RM: |
Okan Sahin |
0:047a7089311e | 272 | reg_intm_glbl0.bits.nen_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 273 | break; |
Okan Sahin |
0:047a7089311e | 274 | case INTM_GLBL0_TJAL1_RM: |
Okan Sahin |
0:047a7089311e | 275 | reg_intm_glbl0.bits.tjal1_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 276 | break; |
Okan Sahin |
0:047a7089311e | 277 | case INTM_GLBL0_TJAL2_RM: |
Okan Sahin |
0:047a7089311e | 278 | reg_intm_glbl0.bits.tjal2_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 279 | break; |
Okan Sahin |
0:047a7089311e | 280 | case INTM_GLBL0_DOD_RM: |
Okan Sahin |
0:047a7089311e | 281 | reg_intm_glbl0.bits.dod_rm = maskBit; |
Okan Sahin |
0:047a7089311e | 282 | break; |
Okan Sahin |
0:047a7089311e | 283 | default: |
Okan Sahin |
0:047a7089311e | 284 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 285 | break; |
Okan Sahin |
0:047a7089311e | 286 | } |
Okan Sahin |
0:047a7089311e | 287 | |
Okan Sahin |
0:047a7089311e | 288 | if (reg_addr == INT_M_CHG) |
Okan Sahin |
0:047a7089311e | 289 | return write_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); |
Okan Sahin |
0:047a7089311e | 290 | else if (reg_addr == INTM_GLBL0) |
Okan Sahin |
0:047a7089311e | 291 | return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); |
Okan Sahin |
0:047a7089311e | 292 | else if (reg_addr == INTM_GLBL1) |
Okan Sahin |
0:047a7089311e | 293 | return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); |
Okan Sahin |
0:047a7089311e | 294 | else |
Okan Sahin |
0:047a7089311e | 295 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 296 | } |
Okan Sahin |
0:047a7089311e | 297 | |
Okan Sahin |
0:047a7089311e | 298 | int MAX77659::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit) |
Okan Sahin |
0:047a7089311e | 299 | { |
Okan Sahin |
0:047a7089311e | 300 | int ret; |
Okan Sahin |
0:047a7089311e | 301 | uint8_t reg_addr; |
Okan Sahin |
0:047a7089311e | 302 | reg_int_m_chg_t reg_int_m_chg = {0}; |
Okan Sahin |
0:047a7089311e | 303 | reg_intm_glbl0_t reg_intm_glbl0 = {0}; |
Okan Sahin |
0:047a7089311e | 304 | reg_intm_glbl1_t reg_intm_glbl1 = {0}; |
Okan Sahin |
0:047a7089311e | 305 | |
Okan Sahin |
0:047a7089311e | 306 | //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09) |
Okan Sahin |
0:047a7089311e | 307 | reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07; |
Okan Sahin |
0:047a7089311e | 308 | |
Okan Sahin |
0:047a7089311e | 309 | if (reg_addr == INT_M_CHG) |
Okan Sahin |
0:047a7089311e | 310 | ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); |
Okan Sahin |
0:047a7089311e | 311 | else if (reg_addr == INTM_GLBL0) |
Okan Sahin |
0:047a7089311e | 312 | ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); |
Okan Sahin |
0:047a7089311e | 313 | else if (reg_addr == INTM_GLBL1) |
Okan Sahin |
0:047a7089311e | 314 | ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); |
Okan Sahin |
0:047a7089311e | 315 | else |
Okan Sahin |
0:047a7089311e | 316 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 317 | |
Okan Sahin |
0:047a7089311e | 318 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 319 | |
Okan Sahin |
0:047a7089311e | 320 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 321 | { |
Okan Sahin |
0:047a7089311e | 322 | case INT_M_CHG_THM_M: |
Okan Sahin |
0:047a7089311e | 323 | *maskBit = (uint8_t)reg_int_m_chg.bits.thm_m; |
Okan Sahin |
0:047a7089311e | 324 | break; |
Okan Sahin |
0:047a7089311e | 325 | case INT_M_CHG_CHG_M: |
Okan Sahin |
0:047a7089311e | 326 | *maskBit = (uint8_t)reg_int_m_chg.bits.chg_m; |
Okan Sahin |
0:047a7089311e | 327 | break; |
Okan Sahin |
0:047a7089311e | 328 | case INT_M_CHG_CHGIN_M: |
Okan Sahin |
0:047a7089311e | 329 | *maskBit = (uint8_t)reg_int_m_chg.bits.chgin_m; |
Okan Sahin |
0:047a7089311e | 330 | break; |
Okan Sahin |
0:047a7089311e | 331 | case INT_M_CHG_TJ_REG_M: |
Okan Sahin |
0:047a7089311e | 332 | *maskBit = (uint8_t)reg_int_m_chg.bits.tj_reg_m; |
Okan Sahin |
0:047a7089311e | 333 | break; |
Okan Sahin |
0:047a7089311e | 334 | case INT_M_CHG_SYS_CTRL_M: |
Okan Sahin |
0:047a7089311e | 335 | *maskBit = (uint8_t)reg_int_m_chg.bits.sys_ctrl_m; |
Okan Sahin |
0:047a7089311e | 336 | break; |
Okan Sahin |
0:047a7089311e | 337 | case INTM_GLBL1_GPI1_FM: |
Okan Sahin |
0:047a7089311e | 338 | *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm; |
Okan Sahin |
0:047a7089311e | 339 | break; |
Okan Sahin |
0:047a7089311e | 340 | case INTM_GLBL1_GPI1_RM: |
Okan Sahin |
0:047a7089311e | 341 | *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm; |
Okan Sahin |
0:047a7089311e | 342 | break; |
Okan Sahin |
0:047a7089311e | 343 | case INTM_GLBL1_SBB_TO_M: |
Okan Sahin |
0:047a7089311e | 344 | *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb_to_m; |
Okan Sahin |
0:047a7089311e | 345 | break; |
Okan Sahin |
0:047a7089311e | 346 | case INTM_GLBL1_LDO_M: |
Okan Sahin |
0:047a7089311e | 347 | *maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m; |
Okan Sahin |
0:047a7089311e | 348 | break; |
Okan Sahin |
0:047a7089311e | 349 | case INTM_GLBL0_GPI0_FM: |
Okan Sahin |
0:047a7089311e | 350 | *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm; |
Okan Sahin |
0:047a7089311e | 351 | break; |
Okan Sahin |
0:047a7089311e | 352 | case INTM_GLBL0_GPI0_RM: |
Okan Sahin |
0:047a7089311e | 353 | *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm; |
Okan Sahin |
0:047a7089311e | 354 | break; |
Okan Sahin |
0:047a7089311e | 355 | case INTM_GLBL0_nEN_FM: |
Okan Sahin |
0:047a7089311e | 356 | *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm; |
Okan Sahin |
0:047a7089311e | 357 | break; |
Okan Sahin |
0:047a7089311e | 358 | case INTM_GLBL0_nEN_RM: |
Okan Sahin |
0:047a7089311e | 359 | *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm; |
Okan Sahin |
0:047a7089311e | 360 | break; |
Okan Sahin |
0:047a7089311e | 361 | case INTM_GLBL0_TJAL1_RM: |
Okan Sahin |
0:047a7089311e | 362 | *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm; |
Okan Sahin |
0:047a7089311e | 363 | break; |
Okan Sahin |
0:047a7089311e | 364 | case INTM_GLBL0_TJAL2_RM: |
Okan Sahin |
0:047a7089311e | 365 | *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm; |
Okan Sahin |
0:047a7089311e | 366 | break; |
Okan Sahin |
0:047a7089311e | 367 | case INTM_GLBL0_DOD_RM: |
Okan Sahin |
0:047a7089311e | 368 | *maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm; |
Okan Sahin |
0:047a7089311e | 369 | break; |
Okan Sahin |
0:047a7089311e | 370 | default: |
Okan Sahin |
0:047a7089311e | 371 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 372 | break; |
Okan Sahin |
0:047a7089311e | 373 | } |
Okan Sahin |
0:047a7089311e | 374 | |
Okan Sahin |
0:047a7089311e | 375 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 376 | } |
Okan Sahin |
0:047a7089311e | 377 | |
Okan Sahin |
0:047a7089311e | 378 | int MAX77659::set_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t config) |
Okan Sahin |
0:047a7089311e | 379 | { |
Okan Sahin |
0:047a7089311e | 380 | int ret; |
Okan Sahin |
0:047a7089311e | 381 | reg_cnfg_glbl_t reg_cnfg_glbl = {0}; |
Okan Sahin |
0:047a7089311e | 382 | |
Okan Sahin |
0:047a7089311e | 383 | ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); |
Okan Sahin |
0:047a7089311e | 384 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 385 | |
Okan Sahin |
0:047a7089311e | 386 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 387 | { |
Okan Sahin |
0:047a7089311e | 388 | case CNFG_GLBL_SFT_CTRL: |
Okan Sahin |
0:047a7089311e | 389 | reg_cnfg_glbl.bits.sft_ctrl = config; |
Okan Sahin |
0:047a7089311e | 390 | break; |
Okan Sahin |
0:047a7089311e | 391 | case CNFG_GLBL_DBEN_nEN: |
Okan Sahin |
0:047a7089311e | 392 | reg_cnfg_glbl.bits.dben_nen = config; |
Okan Sahin |
0:047a7089311e | 393 | break; |
Okan Sahin |
0:047a7089311e | 394 | case CNFG_GLBL_nEN_MODE: |
Okan Sahin |
0:047a7089311e | 395 | reg_cnfg_glbl.bits.nen_mode = config; |
Okan Sahin |
0:047a7089311e | 396 | break; |
Okan Sahin |
0:047a7089311e | 397 | case CNFG_GLBL_SBIA_EN: |
Okan Sahin |
0:047a7089311e | 398 | reg_cnfg_glbl.bits.sbia_en = config; |
Okan Sahin |
0:047a7089311e | 399 | break; |
Okan Sahin |
0:047a7089311e | 400 | case CNFG_GLBL_SBIA_LPM: |
Okan Sahin |
0:047a7089311e | 401 | reg_cnfg_glbl.bits.sbia_lpm = config; |
Okan Sahin |
0:047a7089311e | 402 | break; |
Okan Sahin |
0:047a7089311e | 403 | case CNFG_GLBL_T_MRST: |
Okan Sahin |
0:047a7089311e | 404 | reg_cnfg_glbl.bits.t_mrst = config; |
Okan Sahin |
0:047a7089311e | 405 | break; |
Okan Sahin |
0:047a7089311e | 406 | case CNFG_GLBL_PU_DIS: |
Okan Sahin |
0:047a7089311e | 407 | reg_cnfg_glbl.bits.pu_dis = config; |
Okan Sahin |
0:047a7089311e | 408 | break; |
Okan Sahin |
0:047a7089311e | 409 | default: |
Okan Sahin |
0:047a7089311e | 410 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 411 | break; |
Okan Sahin |
0:047a7089311e | 412 | } |
Okan Sahin |
0:047a7089311e | 413 | |
Okan Sahin |
0:047a7089311e | 414 | return write_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); |
Okan Sahin |
0:047a7089311e | 415 | } |
Okan Sahin |
0:047a7089311e | 416 | |
Okan Sahin |
0:047a7089311e | 417 | int MAX77659::get_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t *config) |
Okan Sahin |
0:047a7089311e | 418 | { |
Okan Sahin |
0:047a7089311e | 419 | int ret; |
Okan Sahin |
0:047a7089311e | 420 | reg_cnfg_glbl_t reg_cnfg_glbl = {0}; |
Okan Sahin |
0:047a7089311e | 421 | |
Okan Sahin |
0:047a7089311e | 422 | ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); |
Okan Sahin |
0:047a7089311e | 423 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 424 | |
Okan Sahin |
0:047a7089311e | 425 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 426 | { |
Okan Sahin |
0:047a7089311e | 427 | case CNFG_GLBL_SFT_CTRL: |
Okan Sahin |
0:047a7089311e | 428 | *config = (uint8_t)reg_cnfg_glbl.bits.sft_ctrl; |
Okan Sahin |
0:047a7089311e | 429 | break; |
Okan Sahin |
0:047a7089311e | 430 | case CNFG_GLBL_DBEN_nEN: |
Okan Sahin |
0:047a7089311e | 431 | *config = (uint8_t)reg_cnfg_glbl.bits.dben_nen; |
Okan Sahin |
0:047a7089311e | 432 | break; |
Okan Sahin |
0:047a7089311e | 433 | case CNFG_GLBL_nEN_MODE: |
Okan Sahin |
0:047a7089311e | 434 | *config = (uint8_t)reg_cnfg_glbl.bits.nen_mode; |
Okan Sahin |
0:047a7089311e | 435 | break; |
Okan Sahin |
0:047a7089311e | 436 | case CNFG_GLBL_SBIA_EN: |
Okan Sahin |
0:047a7089311e | 437 | *config = (uint8_t)reg_cnfg_glbl.bits.sbia_en; |
Okan Sahin |
0:047a7089311e | 438 | break; |
Okan Sahin |
0:047a7089311e | 439 | case CNFG_GLBL_SBIA_LPM: |
Okan Sahin |
0:047a7089311e | 440 | *config = (uint8_t)reg_cnfg_glbl.bits.sbia_lpm; |
Okan Sahin |
0:047a7089311e | 441 | break; |
Okan Sahin |
0:047a7089311e | 442 | case CNFG_GLBL_T_MRST: |
Okan Sahin |
0:047a7089311e | 443 | *config = (uint8_t)reg_cnfg_glbl.bits.t_mrst; |
Okan Sahin |
0:047a7089311e | 444 | break; |
Okan Sahin |
0:047a7089311e | 445 | case CNFG_GLBL_PU_DIS: |
Okan Sahin |
0:047a7089311e | 446 | *config = (uint8_t)reg_cnfg_glbl.bits.pu_dis; |
Okan Sahin |
0:047a7089311e | 447 | break; |
Okan Sahin |
0:047a7089311e | 448 | default: |
Okan Sahin |
0:047a7089311e | 449 | ret = MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 450 | break; |
Okan Sahin |
0:047a7089311e | 451 | } |
Okan Sahin |
0:047a7089311e | 452 | |
Okan Sahin |
0:047a7089311e | 453 | return ret; |
Okan Sahin |
0:047a7089311e | 454 | } |
Okan Sahin |
0:047a7089311e | 455 | |
Okan Sahin |
0:047a7089311e | 456 | int MAX77659::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config) |
Okan Sahin |
0:047a7089311e | 457 | { |
Okan Sahin |
0:047a7089311e | 458 | int ret; |
Okan Sahin |
0:047a7089311e | 459 | reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; |
Okan Sahin |
0:047a7089311e | 460 | reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; |
Okan Sahin |
0:047a7089311e | 461 | |
Okan Sahin |
0:047a7089311e | 462 | if (channel == 0) |
Okan Sahin |
0:047a7089311e | 463 | { |
Okan Sahin |
0:047a7089311e | 464 | ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); |
Okan Sahin |
0:047a7089311e | 465 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 466 | |
Okan Sahin |
0:047a7089311e | 467 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 468 | { |
Okan Sahin |
0:047a7089311e | 469 | case CNFG_GPIO_DIR: |
Okan Sahin |
0:047a7089311e | 470 | reg_cnfg_gpio0.bits.gpo_dir = config; |
Okan Sahin |
0:047a7089311e | 471 | break; |
Okan Sahin |
0:047a7089311e | 472 | case CNFG_GPIO_DI: |
Okan Sahin |
0:047a7089311e | 473 | reg_cnfg_gpio0.bits.gpo_di = config; |
Okan Sahin |
0:047a7089311e | 474 | break; |
Okan Sahin |
0:047a7089311e | 475 | case CNFG_GPIO_DRV: |
Okan Sahin |
0:047a7089311e | 476 | reg_cnfg_gpio0.bits.gpo_drv = config; |
Okan Sahin |
0:047a7089311e | 477 | break; |
Okan Sahin |
0:047a7089311e | 478 | case CNFG_GPIO_DO: |
Okan Sahin |
0:047a7089311e | 479 | reg_cnfg_gpio0.bits.gpo_do = config; |
Okan Sahin |
0:047a7089311e | 480 | break; |
Okan Sahin |
0:047a7089311e | 481 | case CNFG_GPIO_DBEN_GPI: |
Okan Sahin |
0:047a7089311e | 482 | reg_cnfg_gpio0.bits.dben_gpi = config; |
Okan Sahin |
0:047a7089311e | 483 | break; |
Okan Sahin |
0:047a7089311e | 484 | case CNFG_GPIO_ALT_GPIO: |
Okan Sahin |
0:047a7089311e | 485 | reg_cnfg_gpio0.bits.alt_gpio = config; |
Okan Sahin |
0:047a7089311e | 486 | break; |
Okan Sahin |
0:047a7089311e | 487 | default: |
Okan Sahin |
0:047a7089311e | 488 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 489 | break; |
Okan Sahin |
0:047a7089311e | 490 | } |
Okan Sahin |
0:047a7089311e | 491 | |
Okan Sahin |
0:047a7089311e | 492 | return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); |
Okan Sahin |
0:047a7089311e | 493 | } |
Okan Sahin |
0:047a7089311e | 494 | else if (channel == 1) |
Okan Sahin |
0:047a7089311e | 495 | { |
Okan Sahin |
0:047a7089311e | 496 | ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); |
Okan Sahin |
0:047a7089311e | 497 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 498 | |
Okan Sahin |
0:047a7089311e | 499 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 500 | { |
Okan Sahin |
0:047a7089311e | 501 | case CNFG_GPIO_DIR: |
Okan Sahin |
0:047a7089311e | 502 | reg_cnfg_gpio1.bits.gpo_dir = config; |
Okan Sahin |
0:047a7089311e | 503 | break; |
Okan Sahin |
0:047a7089311e | 504 | case CNFG_GPIO_DI: |
Okan Sahin |
0:047a7089311e | 505 | reg_cnfg_gpio1.bits.gpo_di = config; |
Okan Sahin |
0:047a7089311e | 506 | break; |
Okan Sahin |
0:047a7089311e | 507 | case CNFG_GPIO_DRV: |
Okan Sahin |
0:047a7089311e | 508 | reg_cnfg_gpio1.bits.gpo_drv = config; |
Okan Sahin |
0:047a7089311e | 509 | break; |
Okan Sahin |
0:047a7089311e | 510 | case CNFG_GPIO_DO: |
Okan Sahin |
0:047a7089311e | 511 | reg_cnfg_gpio1.bits.gpo_do = config; |
Okan Sahin |
0:047a7089311e | 512 | break; |
Okan Sahin |
0:047a7089311e | 513 | case CNFG_GPIO_DBEN_GPI: |
Okan Sahin |
0:047a7089311e | 514 | reg_cnfg_gpio1.bits.dben_gpi = config; |
Okan Sahin |
0:047a7089311e | 515 | break; |
Okan Sahin |
0:047a7089311e | 516 | case CNFG_GPIO_ALT_GPIO: |
Okan Sahin |
0:047a7089311e | 517 | reg_cnfg_gpio1.bits.alt_gpio = config; |
Okan Sahin |
0:047a7089311e | 518 | break; |
Okan Sahin |
0:047a7089311e | 519 | default: |
Okan Sahin |
0:047a7089311e | 520 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 521 | break; |
Okan Sahin |
0:047a7089311e | 522 | } |
Okan Sahin |
0:047a7089311e | 523 | |
Okan Sahin |
0:047a7089311e | 524 | return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); |
Okan Sahin |
0:047a7089311e | 525 | } |
Okan Sahin |
0:047a7089311e | 526 | else { |
Okan Sahin |
0:047a7089311e | 527 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 528 | } |
Okan Sahin |
0:047a7089311e | 529 | } |
Okan Sahin |
0:047a7089311e | 530 | |
Okan Sahin |
0:047a7089311e | 531 | int MAX77659::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config) |
Okan Sahin |
0:047a7089311e | 532 | { |
Okan Sahin |
0:047a7089311e | 533 | int ret; |
Okan Sahin |
0:047a7089311e | 534 | reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; |
Okan Sahin |
0:047a7089311e | 535 | reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; |
Okan Sahin |
0:047a7089311e | 536 | |
Okan Sahin |
0:047a7089311e | 537 | if (channel == 0) |
Okan Sahin |
0:047a7089311e | 538 | { |
Okan Sahin |
0:047a7089311e | 539 | ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); |
Okan Sahin |
0:047a7089311e | 540 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 541 | |
Okan Sahin |
0:047a7089311e | 542 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 543 | { |
Okan Sahin |
0:047a7089311e | 544 | case CNFG_GPIO_DIR: |
Okan Sahin |
0:047a7089311e | 545 | *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir; |
Okan Sahin |
0:047a7089311e | 546 | break; |
Okan Sahin |
0:047a7089311e | 547 | case CNFG_GPIO_DI: |
Okan Sahin |
0:047a7089311e | 548 | *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di; |
Okan Sahin |
0:047a7089311e | 549 | break; |
Okan Sahin |
0:047a7089311e | 550 | case CNFG_GPIO_DRV: |
Okan Sahin |
0:047a7089311e | 551 | *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv; |
Okan Sahin |
0:047a7089311e | 552 | break; |
Okan Sahin |
0:047a7089311e | 553 | case CNFG_GPIO_DO: |
Okan Sahin |
0:047a7089311e | 554 | *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do; |
Okan Sahin |
0:047a7089311e | 555 | break; |
Okan Sahin |
0:047a7089311e | 556 | case CNFG_GPIO_DBEN_GPI: |
Okan Sahin |
0:047a7089311e | 557 | *config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi; |
Okan Sahin |
0:047a7089311e | 558 | break; |
Okan Sahin |
0:047a7089311e | 559 | case CNFG_GPIO_ALT_GPIO: |
Okan Sahin |
0:047a7089311e | 560 | *config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio; |
Okan Sahin |
0:047a7089311e | 561 | break; |
Okan Sahin |
0:047a7089311e | 562 | default: |
Okan Sahin |
0:047a7089311e | 563 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 564 | break; |
Okan Sahin |
0:047a7089311e | 565 | } |
Okan Sahin |
0:047a7089311e | 566 | } |
Okan Sahin |
0:047a7089311e | 567 | else if (channel == 1) |
Okan Sahin |
0:047a7089311e | 568 | { |
Okan Sahin |
0:047a7089311e | 569 | ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); |
Okan Sahin |
0:047a7089311e | 570 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 571 | |
Okan Sahin |
0:047a7089311e | 572 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 573 | { |
Okan Sahin |
0:047a7089311e | 574 | case CNFG_GPIO_DIR: |
Okan Sahin |
0:047a7089311e | 575 | *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir; |
Okan Sahin |
0:047a7089311e | 576 | break; |
Okan Sahin |
0:047a7089311e | 577 | case CNFG_GPIO_DI: |
Okan Sahin |
0:047a7089311e | 578 | *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di; |
Okan Sahin |
0:047a7089311e | 579 | break; |
Okan Sahin |
0:047a7089311e | 580 | case CNFG_GPIO_DRV: |
Okan Sahin |
0:047a7089311e | 581 | *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv; |
Okan Sahin |
0:047a7089311e | 582 | break; |
Okan Sahin |
0:047a7089311e | 583 | case CNFG_GPIO_DO: |
Okan Sahin |
0:047a7089311e | 584 | *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do; |
Okan Sahin |
0:047a7089311e | 585 | break; |
Okan Sahin |
0:047a7089311e | 586 | case CNFG_GPIO_DBEN_GPI: |
Okan Sahin |
0:047a7089311e | 587 | *config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi; |
Okan Sahin |
0:047a7089311e | 588 | break; |
Okan Sahin |
0:047a7089311e | 589 | case CNFG_GPIO_ALT_GPIO: |
Okan Sahin |
0:047a7089311e | 590 | *config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio; |
Okan Sahin |
0:047a7089311e | 591 | break; |
Okan Sahin |
0:047a7089311e | 592 | default: |
Okan Sahin |
0:047a7089311e | 593 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 594 | break; |
Okan Sahin |
0:047a7089311e | 595 | } |
Okan Sahin |
0:047a7089311e | 596 | } |
Okan Sahin |
0:047a7089311e | 597 | else { |
Okan Sahin |
0:047a7089311e | 598 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 599 | } |
Okan Sahin |
0:047a7089311e | 600 | |
Okan Sahin |
0:047a7089311e | 601 | return ret; |
Okan Sahin |
0:047a7089311e | 602 | } |
Okan Sahin |
0:047a7089311e | 603 | |
Okan Sahin |
0:047a7089311e | 604 | int MAX77659::get_cid(void) { |
Okan Sahin |
0:047a7089311e | 605 | char rbuf[1] = {0}; |
Okan Sahin |
0:047a7089311e | 606 | int ret; |
Okan Sahin |
0:047a7089311e | 607 | |
Okan Sahin |
0:047a7089311e | 608 | ret = read_register(CID, (uint8_t *)&(rbuf)); |
Okan Sahin |
0:047a7089311e | 609 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 610 | |
Okan Sahin |
0:047a7089311e | 611 | return *rbuf; |
Okan Sahin |
0:047a7089311e | 612 | } |
Okan Sahin |
0:047a7089311e | 613 | |
Okan Sahin |
0:047a7089311e | 614 | int MAX77659::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config) |
Okan Sahin |
0:047a7089311e | 615 | { |
Okan Sahin |
0:047a7089311e | 616 | int ret; |
Okan Sahin |
0:047a7089311e | 617 | reg_cnfg_wdt_t reg_cnfg_wdt = {0}; |
Okan Sahin |
0:047a7089311e | 618 | |
Okan Sahin |
0:047a7089311e | 619 | ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); |
Okan Sahin |
0:047a7089311e | 620 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 621 | |
Okan Sahin |
0:047a7089311e | 622 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 623 | { |
Okan Sahin |
0:047a7089311e | 624 | case CNFG_WDT_WDT_LOCK: |
Okan Sahin |
0:047a7089311e | 625 | reg_cnfg_wdt.bits.wdt_lock = config; |
Okan Sahin |
0:047a7089311e | 626 | break; |
Okan Sahin |
0:047a7089311e | 627 | case CNFG_WDT_WDT_EN: |
Okan Sahin |
0:047a7089311e | 628 | reg_cnfg_wdt.bits.wdt_en = config; |
Okan Sahin |
0:047a7089311e | 629 | break; |
Okan Sahin |
0:047a7089311e | 630 | case CNFG_WDT_WDT_CLR: |
Okan Sahin |
0:047a7089311e | 631 | reg_cnfg_wdt.bits.wdt_clr = config; |
Okan Sahin |
0:047a7089311e | 632 | break; |
Okan Sahin |
0:047a7089311e | 633 | case CNFG_WDT_WDT_MODE: |
Okan Sahin |
0:047a7089311e | 634 | reg_cnfg_wdt.bits.wdt_mode = config; |
Okan Sahin |
0:047a7089311e | 635 | break; |
Okan Sahin |
0:047a7089311e | 636 | case CNFG_WDT_WDT_PER: |
Okan Sahin |
0:047a7089311e | 637 | reg_cnfg_wdt.bits.wdt_per = config; |
Okan Sahin |
0:047a7089311e | 638 | break; |
Okan Sahin |
0:047a7089311e | 639 | default: |
Okan Sahin |
0:047a7089311e | 640 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 641 | break; |
Okan Sahin |
0:047a7089311e | 642 | } |
Okan Sahin |
0:047a7089311e | 643 | |
Okan Sahin |
0:047a7089311e | 644 | return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); |
Okan Sahin |
0:047a7089311e | 645 | } |
Okan Sahin |
0:047a7089311e | 646 | |
Okan Sahin |
0:047a7089311e | 647 | int MAX77659::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config) |
Okan Sahin |
0:047a7089311e | 648 | { |
Okan Sahin |
0:047a7089311e | 649 | int ret; |
Okan Sahin |
0:047a7089311e | 650 | reg_cnfg_wdt_t reg_cnfg_wdt = {0}; |
Okan Sahin |
0:047a7089311e | 651 | |
Okan Sahin |
0:047a7089311e | 652 | ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); |
Okan Sahin |
0:047a7089311e | 653 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 654 | |
Okan Sahin |
0:047a7089311e | 655 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 656 | { |
Okan Sahin |
0:047a7089311e | 657 | case CNFG_WDT_WDT_LOCK: |
Okan Sahin |
0:047a7089311e | 658 | *config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock; |
Okan Sahin |
0:047a7089311e | 659 | break; |
Okan Sahin |
0:047a7089311e | 660 | case CNFG_WDT_WDT_EN: |
Okan Sahin |
0:047a7089311e | 661 | *config = (uint8_t)reg_cnfg_wdt.bits.wdt_en; |
Okan Sahin |
0:047a7089311e | 662 | break; |
Okan Sahin |
0:047a7089311e | 663 | case CNFG_WDT_WDT_CLR: |
Okan Sahin |
0:047a7089311e | 664 | *config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr; |
Okan Sahin |
0:047a7089311e | 665 | break; |
Okan Sahin |
0:047a7089311e | 666 | case CNFG_WDT_WDT_MODE: |
Okan Sahin |
0:047a7089311e | 667 | *config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode; |
Okan Sahin |
0:047a7089311e | 668 | break; |
Okan Sahin |
0:047a7089311e | 669 | case CNFG_WDT_WDT_PER: |
Okan Sahin |
0:047a7089311e | 670 | *config = (uint8_t)reg_cnfg_wdt.bits.wdt_per; |
Okan Sahin |
0:047a7089311e | 671 | break; |
Okan Sahin |
0:047a7089311e | 672 | default: |
Okan Sahin |
0:047a7089311e | 673 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 674 | break; |
Okan Sahin |
0:047a7089311e | 675 | } |
Okan Sahin |
0:047a7089311e | 676 | |
Okan Sahin |
0:047a7089311e | 677 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 678 | } |
Okan Sahin |
0:047a7089311e | 679 | |
Okan Sahin |
0:047a7089311e | 680 | int MAX77659::get_stat_chg_a(reg_bit_stat_chg_a_t bit_field, uint8_t *status) |
Okan Sahin |
0:047a7089311e | 681 | { |
Okan Sahin |
0:047a7089311e | 682 | int ret; |
Okan Sahin |
0:047a7089311e | 683 | reg_stat_chg_a_t reg_stat_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 684 | |
Okan Sahin |
0:047a7089311e | 685 | ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a)); |
Okan Sahin |
0:047a7089311e | 686 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 687 | |
Okan Sahin |
0:047a7089311e | 688 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 689 | { |
Okan Sahin |
0:047a7089311e | 690 | case STAT_CHG_A_THM_DTLS: |
Okan Sahin |
0:047a7089311e | 691 | *status = (uint8_t)reg_stat_chg_a.bits.thm_dtls; |
Okan Sahin |
0:047a7089311e | 692 | break; |
Okan Sahin |
0:047a7089311e | 693 | case STAT_CHG_A_TJ_REG_STAT: |
Okan Sahin |
0:047a7089311e | 694 | *status = (uint8_t)reg_stat_chg_a.bits.tj_reg_stat; |
Okan Sahin |
0:047a7089311e | 695 | break; |
Okan Sahin |
0:047a7089311e | 696 | case STAT_CHG_A_VSYS_MIN_STAT: |
Okan Sahin |
0:047a7089311e | 697 | *status = (uint8_t)reg_stat_chg_a.bits.vsys_min_stat; |
Okan Sahin |
0:047a7089311e | 698 | break; |
Okan Sahin |
0:047a7089311e | 699 | default: |
Okan Sahin |
0:047a7089311e | 700 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 701 | break; |
Okan Sahin |
0:047a7089311e | 702 | } |
Okan Sahin |
0:047a7089311e | 703 | |
Okan Sahin |
0:047a7089311e | 704 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 705 | } |
Okan Sahin |
0:047a7089311e | 706 | |
Okan Sahin |
0:047a7089311e | 707 | int MAX77659::get_thm_dtls(decode_thm_dtls_t *thm_dtls) |
Okan Sahin |
0:047a7089311e | 708 | { |
Okan Sahin |
0:047a7089311e | 709 | int ret; |
Okan Sahin |
0:047a7089311e | 710 | reg_stat_chg_a_t reg_stat_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 711 | |
Okan Sahin |
0:047a7089311e | 712 | ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a)); |
Okan Sahin |
0:047a7089311e | 713 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 714 | |
Okan Sahin |
0:047a7089311e | 715 | *thm_dtls = (decode_thm_dtls_t)reg_stat_chg_a.bits.thm_dtls; |
Okan Sahin |
0:047a7089311e | 716 | |
Okan Sahin |
0:047a7089311e | 717 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 718 | } |
Okan Sahin |
0:047a7089311e | 719 | |
Okan Sahin |
0:047a7089311e | 720 | int MAX77659::get_stat_chg_b(reg_bit_stat_chg_b_t bit_field, uint8_t *status) |
Okan Sahin |
0:047a7089311e | 721 | { |
Okan Sahin |
0:047a7089311e | 722 | int ret; |
Okan Sahin |
0:047a7089311e | 723 | reg_stat_chg_b_t reg_stat_chg_b = {0}; |
Okan Sahin |
0:047a7089311e | 724 | |
Okan Sahin |
0:047a7089311e | 725 | ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b)); |
Okan Sahin |
0:047a7089311e | 726 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 727 | |
Okan Sahin |
0:047a7089311e | 728 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 729 | { |
Okan Sahin |
0:047a7089311e | 730 | case STAT_CHG_B_TIME_SUS: |
Okan Sahin |
0:047a7089311e | 731 | *status = (uint8_t)reg_stat_chg_b.bits.time_sus; |
Okan Sahin |
0:047a7089311e | 732 | break; |
Okan Sahin |
0:047a7089311e | 733 | case STAT_CHG_B_CHG: |
Okan Sahin |
0:047a7089311e | 734 | *status = (uint8_t)reg_stat_chg_b.bits.chg; |
Okan Sahin |
0:047a7089311e | 735 | break; |
Okan Sahin |
0:047a7089311e | 736 | case STAT_CHG_B_CHGIN_DTLS: |
Okan Sahin |
0:047a7089311e | 737 | *status = (uint8_t)reg_stat_chg_b.bits.chgin_dtls; |
Okan Sahin |
0:047a7089311e | 738 | break; |
Okan Sahin |
0:047a7089311e | 739 | case STAT_CHG_B_CHG_DTLS: |
Okan Sahin |
0:047a7089311e | 740 | *status = (uint8_t)reg_stat_chg_b.bits.chg_dtls; |
Okan Sahin |
0:047a7089311e | 741 | break; |
Okan Sahin |
0:047a7089311e | 742 | default: |
Okan Sahin |
0:047a7089311e | 743 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 744 | break; |
Okan Sahin |
0:047a7089311e | 745 | } |
Okan Sahin |
0:047a7089311e | 746 | |
Okan Sahin |
0:047a7089311e | 747 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 748 | } |
Okan Sahin |
0:047a7089311e | 749 | |
Okan Sahin |
0:047a7089311e | 750 | int MAX77659::get_chg_dtls(decode_chg_dtls_t *chg_dtls) |
Okan Sahin |
0:047a7089311e | 751 | { |
Okan Sahin |
0:047a7089311e | 752 | int ret; |
Okan Sahin |
0:047a7089311e | 753 | reg_stat_chg_b_t reg_stat_chg_b = {0}; |
Okan Sahin |
0:047a7089311e | 754 | |
Okan Sahin |
0:047a7089311e | 755 | ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b)); |
Okan Sahin |
0:047a7089311e | 756 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 757 | |
Okan Sahin |
0:047a7089311e | 758 | *chg_dtls = (decode_chg_dtls_t)reg_stat_chg_b.bits.chg_dtls; |
Okan Sahin |
0:047a7089311e | 759 | |
Okan Sahin |
0:047a7089311e | 760 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 761 | } |
Okan Sahin |
0:047a7089311e | 762 | |
Okan Sahin |
0:047a7089311e | 763 | int MAX77659::set_thm_hot(decode_thm_hot_t thm_hot) |
Okan Sahin |
0:047a7089311e | 764 | { |
Okan Sahin |
0:047a7089311e | 765 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 766 | |
Okan Sahin |
0:047a7089311e | 767 | SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_hot, thm_hot); |
Okan Sahin |
0:047a7089311e | 768 | |
Okan Sahin |
0:047a7089311e | 769 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 770 | } |
Okan Sahin |
0:047a7089311e | 771 | |
Okan Sahin |
0:047a7089311e | 772 | int MAX77659::get_thm_hot(decode_thm_hot_t *thm_hot) |
Okan Sahin |
0:047a7089311e | 773 | { |
Okan Sahin |
0:047a7089311e | 774 | int ret; |
Okan Sahin |
0:047a7089311e | 775 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 776 | |
Okan Sahin |
0:047a7089311e | 777 | ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); |
Okan Sahin |
0:047a7089311e | 778 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 779 | |
Okan Sahin |
0:047a7089311e | 780 | *thm_hot = (decode_thm_hot_t)reg_cnfg_chg_a.bits.thm_hot; |
Okan Sahin |
0:047a7089311e | 781 | |
Okan Sahin |
0:047a7089311e | 782 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 783 | } |
Okan Sahin |
0:047a7089311e | 784 | |
Okan Sahin |
0:047a7089311e | 785 | int MAX77659::set_thm_warm(decode_thm_warm_t thm_warm) |
Okan Sahin |
0:047a7089311e | 786 | { |
Okan Sahin |
0:047a7089311e | 787 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 788 | |
Okan Sahin |
0:047a7089311e | 789 | SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_warm, thm_warm); |
Okan Sahin |
0:047a7089311e | 790 | |
Okan Sahin |
0:047a7089311e | 791 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 792 | } |
Okan Sahin |
0:047a7089311e | 793 | |
Okan Sahin |
0:047a7089311e | 794 | int MAX77659::get_thm_warm(decode_thm_warm_t *thm_warm) |
Okan Sahin |
0:047a7089311e | 795 | { |
Okan Sahin |
0:047a7089311e | 796 | int ret; |
Okan Sahin |
0:047a7089311e | 797 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 798 | |
Okan Sahin |
0:047a7089311e | 799 | ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); |
Okan Sahin |
0:047a7089311e | 800 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 801 | |
Okan Sahin |
0:047a7089311e | 802 | *thm_warm = (decode_thm_warm_t)reg_cnfg_chg_a.bits.thm_warm; |
Okan Sahin |
0:047a7089311e | 803 | |
Okan Sahin |
0:047a7089311e | 804 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 805 | } |
Okan Sahin |
0:047a7089311e | 806 | |
Okan Sahin |
0:047a7089311e | 807 | int MAX77659::set_thm_cool(decode_thm_cool_t thm_cool) |
Okan Sahin |
0:047a7089311e | 808 | { |
Okan Sahin |
0:047a7089311e | 809 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 810 | |
Okan Sahin |
0:047a7089311e | 811 | SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cool, thm_cool); |
Okan Sahin |
0:047a7089311e | 812 | |
Okan Sahin |
0:047a7089311e | 813 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 814 | } |
Okan Sahin |
0:047a7089311e | 815 | |
Okan Sahin |
0:047a7089311e | 816 | int MAX77659::get_thm_cool(decode_thm_cool_t *thm_cool) |
Okan Sahin |
0:047a7089311e | 817 | { |
Okan Sahin |
0:047a7089311e | 818 | int ret; |
Okan Sahin |
0:047a7089311e | 819 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 820 | |
Okan Sahin |
0:047a7089311e | 821 | ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); |
Okan Sahin |
0:047a7089311e | 822 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 823 | |
Okan Sahin |
0:047a7089311e | 824 | *thm_cool = (decode_thm_cool_t)reg_cnfg_chg_a.bits.thm_cool; |
Okan Sahin |
0:047a7089311e | 825 | |
Okan Sahin |
0:047a7089311e | 826 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 827 | } |
Okan Sahin |
0:047a7089311e | 828 | |
Okan Sahin |
0:047a7089311e | 829 | int MAX77659::set_thm_cold(decode_thm_cold_t thm_cold) |
Okan Sahin |
0:047a7089311e | 830 | { |
Okan Sahin |
0:047a7089311e | 831 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 832 | |
Okan Sahin |
0:047a7089311e | 833 | SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cold, thm_cold); |
Okan Sahin |
0:047a7089311e | 834 | |
Okan Sahin |
0:047a7089311e | 835 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 836 | } |
Okan Sahin |
0:047a7089311e | 837 | |
Okan Sahin |
0:047a7089311e | 838 | int MAX77659:: get_thm_cold(decode_thm_cold_t *thm_cold) |
Okan Sahin |
0:047a7089311e | 839 | { |
Okan Sahin |
0:047a7089311e | 840 | int ret; |
Okan Sahin |
0:047a7089311e | 841 | reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; |
Okan Sahin |
0:047a7089311e | 842 | |
Okan Sahin |
0:047a7089311e | 843 | ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); |
Okan Sahin |
0:047a7089311e | 844 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 845 | |
Okan Sahin |
0:047a7089311e | 846 | *thm_cold = (decode_thm_cold_t)reg_cnfg_chg_a.bits.thm_cold; |
Okan Sahin |
0:047a7089311e | 847 | |
Okan Sahin |
0:047a7089311e | 848 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 849 | } |
Okan Sahin |
0:047a7089311e | 850 | |
Okan Sahin |
0:047a7089311e | 851 | int MAX77659::set_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t config) |
Okan Sahin |
0:047a7089311e | 852 | { |
Okan Sahin |
0:047a7089311e | 853 | int ret; |
Okan Sahin |
0:047a7089311e | 854 | reg_cnfg_chg_b_t reg_cnfg_chg_b = {0}; |
Okan Sahin |
0:047a7089311e | 855 | |
Okan Sahin |
0:047a7089311e | 856 | ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); |
Okan Sahin |
0:047a7089311e | 857 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 858 | |
Okan Sahin |
0:047a7089311e | 859 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 860 | { |
Okan Sahin |
0:047a7089311e | 861 | case CNFG_CHG_B_CHG_EN: |
Okan Sahin |
0:047a7089311e | 862 | reg_cnfg_chg_b.bits.chg_en = config; |
Okan Sahin |
0:047a7089311e | 863 | break; |
Okan Sahin |
0:047a7089311e | 864 | case CNFG_CHG_B_I_PQ: |
Okan Sahin |
0:047a7089311e | 865 | reg_cnfg_chg_b.bits.i_pq = config; |
Okan Sahin |
0:047a7089311e | 866 | break; |
Okan Sahin |
0:047a7089311e | 867 | case CNFG_CHG_B_RSVD: |
Okan Sahin |
0:047a7089311e | 868 | reg_cnfg_chg_b.bits.rsvd = config; |
Okan Sahin |
0:047a7089311e | 869 | break; |
Okan Sahin |
0:047a7089311e | 870 | default: |
Okan Sahin |
0:047a7089311e | 871 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 872 | break; |
Okan Sahin |
0:047a7089311e | 873 | } |
Okan Sahin |
0:047a7089311e | 874 | |
Okan Sahin |
0:047a7089311e | 875 | return write_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); |
Okan Sahin |
0:047a7089311e | 876 | } |
Okan Sahin |
0:047a7089311e | 877 | |
Okan Sahin |
0:047a7089311e | 878 | int MAX77659::get_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t *config) |
Okan Sahin |
0:047a7089311e | 879 | { |
Okan Sahin |
0:047a7089311e | 880 | int ret; |
Okan Sahin |
0:047a7089311e | 881 | reg_cnfg_chg_b_t reg_cnfg_chg_b = {0}; |
Okan Sahin |
0:047a7089311e | 882 | |
Okan Sahin |
0:047a7089311e | 883 | ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); |
Okan Sahin |
0:047a7089311e | 884 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 885 | |
Okan Sahin |
0:047a7089311e | 886 | switch (bit_field) |
Okan Sahin |
0:047a7089311e | 887 | { |
Okan Sahin |
0:047a7089311e | 888 | case CNFG_CHG_B_CHG_EN: |
Okan Sahin |
0:047a7089311e | 889 | *config = (uint8_t)reg_cnfg_chg_b.bits.chg_en; |
Okan Sahin |
0:047a7089311e | 890 | break; |
Okan Sahin |
0:047a7089311e | 891 | case CNFG_CHG_B_I_PQ: |
Okan Sahin |
0:047a7089311e | 892 | *config = (uint8_t)reg_cnfg_chg_b.bits.i_pq; |
Okan Sahin |
0:047a7089311e | 893 | break; |
Okan Sahin |
0:047a7089311e | 894 | case CNFG_CHG_B_RSVD: |
Okan Sahin |
0:047a7089311e | 895 | *config = (uint8_t)reg_cnfg_chg_b.bits.rsvd; |
Okan Sahin |
0:047a7089311e | 896 | break; |
Okan Sahin |
0:047a7089311e | 897 | default: |
Okan Sahin |
0:047a7089311e | 898 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 899 | break; |
Okan Sahin |
0:047a7089311e | 900 | } |
Okan Sahin |
0:047a7089311e | 901 | |
Okan Sahin |
0:047a7089311e | 902 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 903 | } |
Okan Sahin |
0:047a7089311e | 904 | |
Okan Sahin |
0:047a7089311e | 905 | int MAX77659::set_chg_pq(float voltV) |
Okan Sahin |
0:047a7089311e | 906 | { |
Okan Sahin |
0:047a7089311e | 907 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 908 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 909 | float voltmV = voltV * 1000; |
Okan Sahin |
0:047a7089311e | 910 | |
Okan Sahin |
0:047a7089311e | 911 | if (voltmV < 2300) voltmV = 2300; |
Okan Sahin |
0:047a7089311e | 912 | else if (voltmV > 3000) voltmV = 3000; |
Okan Sahin |
0:047a7089311e | 913 | |
Okan Sahin |
0:047a7089311e | 914 | value = (voltmV - 2300) / 100; |
Okan Sahin |
0:047a7089311e | 915 | |
Okan Sahin |
0:047a7089311e | 916 | SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.chg_pq, value); |
Okan Sahin |
0:047a7089311e | 917 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 918 | } |
Okan Sahin |
0:047a7089311e | 919 | |
Okan Sahin |
0:047a7089311e | 920 | int MAX77659::get_chg_pq(float *voltV) |
Okan Sahin |
0:047a7089311e | 921 | { |
Okan Sahin |
0:047a7089311e | 922 | int ret; |
Okan Sahin |
0:047a7089311e | 923 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 924 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 925 | |
Okan Sahin |
0:047a7089311e | 926 | ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); |
Okan Sahin |
0:047a7089311e | 927 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 928 | |
Okan Sahin |
0:047a7089311e | 929 | bit_value = (uint8_t)reg_cnfg_chg_c.bits.chg_pq; |
Okan Sahin |
0:047a7089311e | 930 | *voltV = (bit_value * 0.1f) + 2.3f; |
Okan Sahin |
0:047a7089311e | 931 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 932 | } |
Okan Sahin |
0:047a7089311e | 933 | |
Okan Sahin |
0:047a7089311e | 934 | int MAX77659::set_i_term(float percent) |
Okan Sahin |
0:047a7089311e | 935 | { |
Okan Sahin |
0:047a7089311e | 936 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 937 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 938 | |
Okan Sahin |
0:047a7089311e | 939 | if (percent < 7.5f) value = 0; |
Okan Sahin |
0:047a7089311e | 940 | else if ((percent >= 7.5f) && (percent < 10)) value = 1; |
Okan Sahin |
0:047a7089311e | 941 | else if ((percent >= 10) && (percent < 15)) value = 2; |
Okan Sahin |
0:047a7089311e | 942 | else if (percent >= 15) value = 3; |
Okan Sahin |
0:047a7089311e | 943 | |
Okan Sahin |
0:047a7089311e | 944 | SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.i_term, value); |
Okan Sahin |
0:047a7089311e | 945 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 946 | } |
Okan Sahin |
0:047a7089311e | 947 | |
Okan Sahin |
0:047a7089311e | 948 | int MAX77659::get_i_term(float *percent) |
Okan Sahin |
0:047a7089311e | 949 | { |
Okan Sahin |
0:047a7089311e | 950 | int ret; |
Okan Sahin |
0:047a7089311e | 951 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 952 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 953 | |
Okan Sahin |
0:047a7089311e | 954 | ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); |
Okan Sahin |
0:047a7089311e | 955 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 956 | |
Okan Sahin |
0:047a7089311e | 957 | bit_value = (uint8_t)reg_cnfg_chg_c.bits.i_term; |
Okan Sahin |
0:047a7089311e | 958 | |
Okan Sahin |
0:047a7089311e | 959 | if (bit_value == 0) *percent = 5.0f; |
Okan Sahin |
0:047a7089311e | 960 | else if (bit_value == 1) *percent = 7.5f; |
Okan Sahin |
0:047a7089311e | 961 | else if (bit_value == 2) *percent = 10.0f; |
Okan Sahin |
0:047a7089311e | 962 | else if (bit_value == 3) *percent = 15.0f; |
Okan Sahin |
0:047a7089311e | 963 | else return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 964 | |
Okan Sahin |
0:047a7089311e | 965 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 966 | } |
Okan Sahin |
0:047a7089311e | 967 | |
Okan Sahin |
0:047a7089311e | 968 | int MAX77659::set_t_topoff(uint8_t minute) |
Okan Sahin |
0:047a7089311e | 969 | { |
Okan Sahin |
0:047a7089311e | 970 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 971 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 972 | |
Okan Sahin |
0:047a7089311e | 973 | if (minute > 35) minute = 35; |
Okan Sahin |
0:047a7089311e | 974 | |
Okan Sahin |
0:047a7089311e | 975 | value = (uint8_t)(minute / 5); |
Okan Sahin |
0:047a7089311e | 976 | |
Okan Sahin |
0:047a7089311e | 977 | SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.t_topoff, value); |
Okan Sahin |
0:047a7089311e | 978 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 979 | } |
Okan Sahin |
0:047a7089311e | 980 | |
Okan Sahin |
0:047a7089311e | 981 | int MAX77659::get_t_topoff(uint8_t *minute) |
Okan Sahin |
0:047a7089311e | 982 | { |
Okan Sahin |
0:047a7089311e | 983 | int ret; |
Okan Sahin |
0:047a7089311e | 984 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 985 | reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; |
Okan Sahin |
0:047a7089311e | 986 | |
Okan Sahin |
0:047a7089311e | 987 | ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); |
Okan Sahin |
0:047a7089311e | 988 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 989 | |
Okan Sahin |
0:047a7089311e | 990 | bit_value = (uint8_t)reg_cnfg_chg_c.bits.t_topoff; |
Okan Sahin |
0:047a7089311e | 991 | *minute = (bit_value * 5); |
Okan Sahin |
0:047a7089311e | 992 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 993 | } |
Okan Sahin |
0:047a7089311e | 994 | |
Okan Sahin |
0:047a7089311e | 995 | int MAX77659::set_tj_reg(uint8_t tempDegC) |
Okan Sahin |
0:047a7089311e | 996 | { |
Okan Sahin |
0:047a7089311e | 997 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 998 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 999 | |
Okan Sahin |
0:047a7089311e | 1000 | if (tempDegC < 60) tempDegC = 60; |
Okan Sahin |
0:047a7089311e | 1001 | else if (tempDegC > 100) tempDegC = 100; |
Okan Sahin |
0:047a7089311e | 1002 | |
Okan Sahin |
0:047a7089311e | 1003 | value = (tempDegC - 60) / 10; |
Okan Sahin |
0:047a7089311e | 1004 | |
Okan Sahin |
0:047a7089311e | 1005 | SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.tj_reg, value); |
Okan Sahin |
0:047a7089311e | 1006 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1007 | } |
Okan Sahin |
0:047a7089311e | 1008 | |
Okan Sahin |
0:047a7089311e | 1009 | int MAX77659::get_tj_reg(uint8_t *tempDegC) |
Okan Sahin |
0:047a7089311e | 1010 | { |
Okan Sahin |
0:047a7089311e | 1011 | int ret; |
Okan Sahin |
0:047a7089311e | 1012 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1013 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 1014 | |
Okan Sahin |
0:047a7089311e | 1015 | ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); |
Okan Sahin |
0:047a7089311e | 1016 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1017 | |
Okan Sahin |
0:047a7089311e | 1018 | bit_value = (uint8_t)reg_cnfg_chg_d.bits.tj_reg; |
Okan Sahin |
0:047a7089311e | 1019 | *tempDegC = (bit_value * 10) + 60; |
Okan Sahin |
0:047a7089311e | 1020 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1021 | } |
Okan Sahin |
0:047a7089311e | 1022 | |
Okan Sahin |
0:047a7089311e | 1023 | int MAX77659::set_vsys_hdrm(decode_vsys_hdrm_t vsys_hdrm) |
Okan Sahin |
0:047a7089311e | 1024 | { |
Okan Sahin |
0:047a7089311e | 1025 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 1026 | |
Okan Sahin |
0:047a7089311e | 1027 | SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_hdrm, vsys_hdrm); |
Okan Sahin |
0:047a7089311e | 1028 | |
Okan Sahin |
0:047a7089311e | 1029 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1030 | } |
Okan Sahin |
0:047a7089311e | 1031 | |
Okan Sahin |
0:047a7089311e | 1032 | int MAX77659::get_vsys_hdrm(decode_vsys_hdrm_t *vsys_hdrm) |
Okan Sahin |
0:047a7089311e | 1033 | { |
Okan Sahin |
0:047a7089311e | 1034 | int ret; |
Okan Sahin |
0:047a7089311e | 1035 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 1036 | |
Okan Sahin |
0:047a7089311e | 1037 | ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); |
Okan Sahin |
0:047a7089311e | 1038 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1039 | |
Okan Sahin |
0:047a7089311e | 1040 | *vsys_hdrm = (decode_vsys_hdrm_t)reg_cnfg_chg_d.bits.vsys_hdrm; |
Okan Sahin |
0:047a7089311e | 1041 | |
Okan Sahin |
0:047a7089311e | 1042 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1043 | } |
Okan Sahin |
0:047a7089311e | 1044 | |
Okan Sahin |
0:047a7089311e | 1045 | int MAX77659::set_vsys_min(decode_vsys_min_t vsys_min) |
Okan Sahin |
0:047a7089311e | 1046 | { |
Okan Sahin |
0:047a7089311e | 1047 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 1048 | |
Okan Sahin |
0:047a7089311e | 1049 | SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_min, vsys_min); |
Okan Sahin |
0:047a7089311e | 1050 | |
Okan Sahin |
0:047a7089311e | 1051 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1052 | } |
Okan Sahin |
0:047a7089311e | 1053 | |
Okan Sahin |
0:047a7089311e | 1054 | int MAX77659::get_vsys_min(decode_vsys_min_t *vsys_min) |
Okan Sahin |
0:047a7089311e | 1055 | { |
Okan Sahin |
0:047a7089311e | 1056 | int ret; |
Okan Sahin |
0:047a7089311e | 1057 | reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; |
Okan Sahin |
0:047a7089311e | 1058 | |
Okan Sahin |
0:047a7089311e | 1059 | ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); |
Okan Sahin |
0:047a7089311e | 1060 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1061 | |
Okan Sahin |
0:047a7089311e | 1062 | *vsys_min = (decode_vsys_min_t)reg_cnfg_chg_d.bits.vsys_min; |
Okan Sahin |
0:047a7089311e | 1063 | |
Okan Sahin |
0:047a7089311e | 1064 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1065 | } |
Okan Sahin |
0:047a7089311e | 1066 | |
Okan Sahin |
0:047a7089311e | 1067 | int MAX77659::set_chg_cc(float currentmA) |
Okan Sahin |
0:047a7089311e | 1068 | { |
Okan Sahin |
0:047a7089311e | 1069 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1070 | reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; |
Okan Sahin |
0:047a7089311e | 1071 | float currentuA = currentmA * 1000; |
Okan Sahin |
0:047a7089311e | 1072 | |
Okan Sahin |
0:047a7089311e | 1073 | if (currentuA < 7500) currentuA = 7500; |
Okan Sahin |
0:047a7089311e | 1074 | if (currentuA > 300000) currentuA = 300000; |
Okan Sahin |
0:047a7089311e | 1075 | |
Okan Sahin |
0:047a7089311e | 1076 | value = (currentuA - 7500) / 7500; |
Okan Sahin |
0:047a7089311e | 1077 | |
Okan Sahin |
0:047a7089311e | 1078 | SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.chg_cc, value); |
Okan Sahin |
0:047a7089311e | 1079 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1080 | } |
Okan Sahin |
0:047a7089311e | 1081 | |
Okan Sahin |
0:047a7089311e | 1082 | int MAX77659::get_chg_cc(float *currentmA) |
Okan Sahin |
0:047a7089311e | 1083 | { |
Okan Sahin |
0:047a7089311e | 1084 | int ret; |
Okan Sahin |
0:047a7089311e | 1085 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1086 | reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; |
Okan Sahin |
0:047a7089311e | 1087 | |
Okan Sahin |
0:047a7089311e | 1088 | ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e)); |
Okan Sahin |
0:047a7089311e | 1089 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1090 | |
Okan Sahin |
0:047a7089311e | 1091 | bit_value = (uint8_t)reg_cnfg_chg_e.bits.chg_cc; |
Okan Sahin |
0:047a7089311e | 1092 | if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA |
Okan Sahin |
0:047a7089311e | 1093 | |
Okan Sahin |
0:047a7089311e | 1094 | *currentmA = (bit_value * 7.5f) + 7.5f; |
Okan Sahin |
0:047a7089311e | 1095 | |
Okan Sahin |
0:047a7089311e | 1096 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1097 | } |
Okan Sahin |
0:047a7089311e | 1098 | |
Okan Sahin |
0:047a7089311e | 1099 | int MAX77659::set_t_fast_chg(decode_t_fast_chg_t t_fast_chg) |
Okan Sahin |
0:047a7089311e | 1100 | { |
Okan Sahin |
0:047a7089311e | 1101 | reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; |
Okan Sahin |
0:047a7089311e | 1102 | |
Okan Sahin |
0:047a7089311e | 1103 | SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.t_fast_chg, t_fast_chg); |
Okan Sahin |
0:047a7089311e | 1104 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1105 | } |
Okan Sahin |
0:047a7089311e | 1106 | |
Okan Sahin |
0:047a7089311e | 1107 | int MAX77659::get_t_fast_chg(decode_t_fast_chg_t *t_fast_chg) |
Okan Sahin |
0:047a7089311e | 1108 | { |
Okan Sahin |
0:047a7089311e | 1109 | int ret; |
Okan Sahin |
0:047a7089311e | 1110 | reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; |
Okan Sahin |
0:047a7089311e | 1111 | |
Okan Sahin |
0:047a7089311e | 1112 | ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e)); |
Okan Sahin |
0:047a7089311e | 1113 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1114 | |
Okan Sahin |
0:047a7089311e | 1115 | *t_fast_chg = (decode_t_fast_chg_t)reg_cnfg_chg_e.bits.t_fast_chg; |
Okan Sahin |
0:047a7089311e | 1116 | |
Okan Sahin |
0:047a7089311e | 1117 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1118 | } |
Okan Sahin |
0:047a7089311e | 1119 | |
Okan Sahin |
0:047a7089311e | 1120 | int MAX77659::set_chg_cc_jeita(float currentmA) |
Okan Sahin |
0:047a7089311e | 1121 | { |
Okan Sahin |
0:047a7089311e | 1122 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1123 | reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; |
Okan Sahin |
0:047a7089311e | 1124 | float currentuA = currentmA * 1000; |
Okan Sahin |
0:047a7089311e | 1125 | |
Okan Sahin |
0:047a7089311e | 1126 | if (currentuA < 7500) currentuA = 7500; |
Okan Sahin |
0:047a7089311e | 1127 | else if (currentuA > 300000) currentuA = 300000; |
Okan Sahin |
0:047a7089311e | 1128 | |
Okan Sahin |
0:047a7089311e | 1129 | value = round(currentuA - 7500) / 7500; |
Okan Sahin |
0:047a7089311e | 1130 | |
Okan Sahin |
0:047a7089311e | 1131 | SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.chg_cc_jeita, value); |
Okan Sahin |
0:047a7089311e | 1132 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1133 | } |
Okan Sahin |
0:047a7089311e | 1134 | |
Okan Sahin |
0:047a7089311e | 1135 | int MAX77659::get_chg_cc_jeita(float *currentmA) |
Okan Sahin |
0:047a7089311e | 1136 | { |
Okan Sahin |
0:047a7089311e | 1137 | int ret; |
Okan Sahin |
0:047a7089311e | 1138 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1139 | reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; |
Okan Sahin |
0:047a7089311e | 1140 | |
Okan Sahin |
0:047a7089311e | 1141 | ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f)); |
Okan Sahin |
0:047a7089311e | 1142 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1143 | |
Okan Sahin |
0:047a7089311e | 1144 | bit_value = (uint8_t)reg_cnfg_chg_f.bits.chg_cc_jeita; |
Okan Sahin |
0:047a7089311e | 1145 | if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA |
Okan Sahin |
0:047a7089311e | 1146 | |
Okan Sahin |
0:047a7089311e | 1147 | *currentmA = (bit_value * 7.5f) + 7.5f; |
Okan Sahin |
0:047a7089311e | 1148 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1149 | } |
Okan Sahin |
0:047a7089311e | 1150 | |
Okan Sahin |
0:047a7089311e | 1151 | |
Okan Sahin |
0:047a7089311e | 1152 | |
Okan Sahin |
0:047a7089311e | 1153 | int MAX77659::set_thm_en(decode_thm_en_t thm_en) |
Okan Sahin |
0:047a7089311e | 1154 | { |
Okan Sahin |
0:047a7089311e | 1155 | reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; |
Okan Sahin |
0:047a7089311e | 1156 | |
Okan Sahin |
0:047a7089311e | 1157 | SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.thm_en, thm_en); |
Okan Sahin |
0:047a7089311e | 1158 | |
Okan Sahin |
0:047a7089311e | 1159 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1160 | } |
Okan Sahin |
0:047a7089311e | 1161 | |
Okan Sahin |
0:047a7089311e | 1162 | int MAX77659::get_thm_en(decode_thm_en_t *thm_en) |
Okan Sahin |
0:047a7089311e | 1163 | { |
Okan Sahin |
0:047a7089311e | 1164 | int ret; |
Okan Sahin |
0:047a7089311e | 1165 | reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; |
Okan Sahin |
0:047a7089311e | 1166 | |
Okan Sahin |
0:047a7089311e | 1167 | ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f)); |
Okan Sahin |
0:047a7089311e | 1168 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1169 | |
Okan Sahin |
0:047a7089311e | 1170 | *thm_en = (decode_thm_en_t)reg_cnfg_chg_f.bits.thm_en; |
Okan Sahin |
0:047a7089311e | 1171 | |
Okan Sahin |
0:047a7089311e | 1172 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1173 | } |
Okan Sahin |
0:047a7089311e | 1174 | |
Okan Sahin |
0:047a7089311e | 1175 | int MAX77659::set_chg_cv(float voltV) |
Okan Sahin |
0:047a7089311e | 1176 | { |
Okan Sahin |
0:047a7089311e | 1177 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1178 | reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; |
Okan Sahin |
0:047a7089311e | 1179 | float voltmV = voltV * 1000; |
Okan Sahin |
0:047a7089311e | 1180 | |
Okan Sahin |
0:047a7089311e | 1181 | if (voltmV < 3600) voltmV = 3600; |
Okan Sahin |
0:047a7089311e | 1182 | else if (voltmV > 4600) voltmV = 4600; |
Okan Sahin |
0:047a7089311e | 1183 | |
Okan Sahin |
0:047a7089311e | 1184 | value = (voltmV - 3600) / 25; |
Okan Sahin |
0:047a7089311e | 1185 | |
Okan Sahin |
0:047a7089311e | 1186 | SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.chg_cv, value); |
Okan Sahin |
0:047a7089311e | 1187 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1188 | } |
Okan Sahin |
0:047a7089311e | 1189 | |
Okan Sahin |
0:047a7089311e | 1190 | int MAX77659::get_chg_cv(float *voltV) |
Okan Sahin |
0:047a7089311e | 1191 | { |
Okan Sahin |
0:047a7089311e | 1192 | int ret; |
Okan Sahin |
0:047a7089311e | 1193 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1194 | reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; |
Okan Sahin |
0:047a7089311e | 1195 | |
Okan Sahin |
0:047a7089311e | 1196 | ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g)); |
Okan Sahin |
0:047a7089311e | 1197 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1198 | |
Okan Sahin |
0:047a7089311e | 1199 | bit_value = (uint8_t)reg_cnfg_chg_g.bits.chg_cv; |
Okan Sahin |
0:047a7089311e | 1200 | *voltV = (bit_value * 0.025f) + 3.6f; |
Okan Sahin |
0:047a7089311e | 1201 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1202 | } |
Okan Sahin |
0:047a7089311e | 1203 | |
Okan Sahin |
0:047a7089311e | 1204 | int MAX77659::set_usbs(decode_usbs_t usbs) |
Okan Sahin |
0:047a7089311e | 1205 | { |
Okan Sahin |
0:047a7089311e | 1206 | reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; |
Okan Sahin |
0:047a7089311e | 1207 | |
Okan Sahin |
0:047a7089311e | 1208 | SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.usbs, usbs); |
Okan Sahin |
0:047a7089311e | 1209 | |
Okan Sahin |
0:047a7089311e | 1210 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1211 | } |
Okan Sahin |
0:047a7089311e | 1212 | |
Okan Sahin |
0:047a7089311e | 1213 | int MAX77659::get_usbs(decode_usbs_t *usbs) |
Okan Sahin |
0:047a7089311e | 1214 | { |
Okan Sahin |
0:047a7089311e | 1215 | int ret; |
Okan Sahin |
0:047a7089311e | 1216 | reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; |
Okan Sahin |
0:047a7089311e | 1217 | |
Okan Sahin |
0:047a7089311e | 1218 | ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g)); |
Okan Sahin |
0:047a7089311e | 1219 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1220 | |
Okan Sahin |
0:047a7089311e | 1221 | *usbs = (decode_usbs_t)reg_cnfg_chg_g.bits.usbs; |
Okan Sahin |
0:047a7089311e | 1222 | |
Okan Sahin |
0:047a7089311e | 1223 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1224 | } |
Okan Sahin |
0:047a7089311e | 1225 | |
Okan Sahin |
0:047a7089311e | 1226 | int MAX77659::set_chg_cv_jeita(float voltV) |
Okan Sahin |
0:047a7089311e | 1227 | { |
Okan Sahin |
0:047a7089311e | 1228 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1229 | reg_cnfg_chg_h_t reg_cnfg_chg_h = {0}; |
Okan Sahin |
0:047a7089311e | 1230 | float voltmV = voltV * 1000; |
Okan Sahin |
0:047a7089311e | 1231 | |
Okan Sahin |
0:047a7089311e | 1232 | if (voltmV < 3600) voltmV = 3600; |
Okan Sahin |
0:047a7089311e | 1233 | else if (voltmV > 4600) voltmV = 4600; |
Okan Sahin |
0:047a7089311e | 1234 | |
Okan Sahin |
0:047a7089311e | 1235 | value = round(voltmV - 3600) / 25; |
Okan Sahin |
0:047a7089311e | 1236 | |
Okan Sahin |
0:047a7089311e | 1237 | SET_BIT_FIELD(CNFG_CHG_H, reg_cnfg_chg_h, reg_cnfg_chg_h.bits.chg_cv_jeita, value); |
Okan Sahin |
0:047a7089311e | 1238 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1239 | } |
Okan Sahin |
0:047a7089311e | 1240 | |
Okan Sahin |
0:047a7089311e | 1241 | int MAX77659::get_chg_cv_jeita(float *voltV) |
Okan Sahin |
0:047a7089311e | 1242 | { |
Okan Sahin |
0:047a7089311e | 1243 | int ret; |
Okan Sahin |
0:047a7089311e | 1244 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1245 | reg_cnfg_chg_h_t reg_cnfg_chg_h = {0}; |
Okan Sahin |
0:047a7089311e | 1246 | |
Okan Sahin |
0:047a7089311e | 1247 | ret = read_register(CNFG_CHG_H, (uint8_t *)&(reg_cnfg_chg_h)); |
Okan Sahin |
0:047a7089311e | 1248 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1249 | |
Okan Sahin |
0:047a7089311e | 1250 | bit_value = (uint8_t)reg_cnfg_chg_h.bits.chg_cv_jeita; |
Okan Sahin |
0:047a7089311e | 1251 | *voltV = (bit_value * 0.025f) + 3.6f; |
Okan Sahin |
0:047a7089311e | 1252 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1253 | } |
Okan Sahin |
0:047a7089311e | 1254 | |
Okan Sahin |
0:047a7089311e | 1255 | int MAX77659::set_imon_dischg_scale(float currentmA) |
Okan Sahin |
0:047a7089311e | 1256 | { |
Okan Sahin |
0:047a7089311e | 1257 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1258 | reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; |
Okan Sahin |
0:047a7089311e | 1259 | |
Okan Sahin |
0:047a7089311e | 1260 | if (currentmA < 40.5f) value = 0; |
Okan Sahin |
0:047a7089311e | 1261 | else if ((currentmA >= 40.5f) && (currentmA < 72.3f)) value = 1; |
Okan Sahin |
0:047a7089311e | 1262 | else if ((currentmA >= 72.3f) && (currentmA < 103.4f)) value = 2; |
Okan Sahin |
0:047a7089311e | 1263 | else if ((currentmA >= 103.4f) && (currentmA < 134.1f)) value = 3; |
Okan Sahin |
0:047a7089311e | 1264 | else if ((currentmA >= 134.1f) && (currentmA < 164.1f)) value = 4; |
Okan Sahin |
0:047a7089311e | 1265 | else if ((currentmA >= 164.1f) && (currentmA < 193.7f)) value = 5; |
Okan Sahin |
0:047a7089311e | 1266 | else if ((currentmA >= 193.7f) && (currentmA < 222.7f)) value = 6; |
Okan Sahin |
0:047a7089311e | 1267 | else if ((currentmA >= 222.7f) && (currentmA < 251.2f)) value = 7; |
Okan Sahin |
0:047a7089311e | 1268 | else if ((currentmA >= 251.2f) && (currentmA < 279.3f)) value = 8; |
Okan Sahin |
0:047a7089311e | 1269 | else if ((currentmA >= 279.3f) && (currentmA < 300.0f)) value = 9; |
Okan Sahin |
0:047a7089311e | 1270 | else if (currentmA >= 300.0f) value = 10; |
Okan Sahin |
0:047a7089311e | 1271 | |
Okan Sahin |
0:047a7089311e | 1272 | SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.imon_dischg_scale, value); |
Okan Sahin |
0:047a7089311e | 1273 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1274 | } |
Okan Sahin |
0:047a7089311e | 1275 | |
Okan Sahin |
0:047a7089311e | 1276 | int MAX77659::get_imon_dischg_scale(float *currentmA) |
Okan Sahin |
0:047a7089311e | 1277 | { |
Okan Sahin |
0:047a7089311e | 1278 | int ret; |
Okan Sahin |
0:047a7089311e | 1279 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1280 | reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; |
Okan Sahin |
0:047a7089311e | 1281 | |
Okan Sahin |
0:047a7089311e | 1282 | ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i)); |
Okan Sahin |
0:047a7089311e | 1283 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1284 | |
Okan Sahin |
0:047a7089311e | 1285 | bit_value = (uint8_t)reg_cnfg_chg_i.bits.imon_dischg_scale; |
Okan Sahin |
0:047a7089311e | 1286 | |
Okan Sahin |
0:047a7089311e | 1287 | if (bit_value == 0) *currentmA = 8.2f; |
Okan Sahin |
0:047a7089311e | 1288 | else if (bit_value == 1) *currentmA = 40.5f; |
Okan Sahin |
0:047a7089311e | 1289 | else if (bit_value == 2) *currentmA = 72.3f; |
Okan Sahin |
0:047a7089311e | 1290 | else if (bit_value == 3) *currentmA = 103.4f; |
Okan Sahin |
0:047a7089311e | 1291 | else if (bit_value == 4) *currentmA = 134.1f; |
Okan Sahin |
0:047a7089311e | 1292 | else if (bit_value == 5) *currentmA = 164.1f; |
Okan Sahin |
0:047a7089311e | 1293 | else if (bit_value == 6) *currentmA = 193.7f; |
Okan Sahin |
0:047a7089311e | 1294 | else if (bit_value == 7) *currentmA = 222.7f; |
Okan Sahin |
0:047a7089311e | 1295 | else if (bit_value == 8) *currentmA = 251.2f; |
Okan Sahin |
0:047a7089311e | 1296 | else if (bit_value == 9) *currentmA = 279.3f; |
Okan Sahin |
0:047a7089311e | 1297 | else *currentmA = 300.0f; //0xA to 0xF = 300.0mA |
Okan Sahin |
0:047a7089311e | 1298 | |
Okan Sahin |
0:047a7089311e | 1299 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1300 | } |
Okan Sahin |
0:047a7089311e | 1301 | |
Okan Sahin |
0:047a7089311e | 1302 | int MAX77659::set_mux_sel(decode_mux_sel_t selection) |
Okan Sahin |
0:047a7089311e | 1303 | { |
Okan Sahin |
0:047a7089311e | 1304 | reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; |
Okan Sahin |
0:047a7089311e | 1305 | |
Okan Sahin |
0:047a7089311e | 1306 | SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.mux_sel, selection); |
Okan Sahin |
0:047a7089311e | 1307 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1308 | } |
Okan Sahin |
0:047a7089311e | 1309 | |
Okan Sahin |
0:047a7089311e | 1310 | int MAX77659::get_mux_sel(decode_mux_sel_t *selection) |
Okan Sahin |
0:047a7089311e | 1311 | { |
Okan Sahin |
0:047a7089311e | 1312 | int ret; |
Okan Sahin |
0:047a7089311e | 1313 | reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; |
Okan Sahin |
0:047a7089311e | 1314 | |
Okan Sahin |
0:047a7089311e | 1315 | ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i)); |
Okan Sahin |
0:047a7089311e | 1316 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1317 | |
Okan Sahin |
0:047a7089311e | 1318 | *selection = (decode_mux_sel_t)reg_cnfg_chg_i.bits.mux_sel; |
Okan Sahin |
0:047a7089311e | 1319 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1320 | } |
Okan Sahin |
0:047a7089311e | 1321 | |
Okan Sahin |
0:047a7089311e | 1322 | int MAX77659::set_tv_sbb(uint8_t channel, float voltV) |
Okan Sahin |
0:047a7089311e | 1323 | { |
Okan Sahin |
0:047a7089311e | 1324 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1325 | reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1326 | reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; |
Okan Sahin |
0:047a7089311e | 1327 | reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; |
Okan Sahin |
0:047a7089311e | 1328 | float voltmV = voltV * 1000; |
Okan Sahin |
0:047a7089311e | 1329 | |
Okan Sahin |
0:047a7089311e | 1330 | if (voltmV < 500) voltmV = 500; |
Okan Sahin |
0:047a7089311e | 1331 | else if (voltmV > 5500) voltmV = 5500; |
Okan Sahin |
0:047a7089311e | 1332 | |
Okan Sahin |
0:047a7089311e | 1333 | value = (voltmV - 500) / 25; |
Okan Sahin |
0:047a7089311e | 1334 | |
Okan Sahin |
0:047a7089311e | 1335 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1336 | SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value); |
Okan Sahin |
0:047a7089311e | 1337 | } |
Okan Sahin |
0:047a7089311e | 1338 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1339 | SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value); |
Okan Sahin |
0:047a7089311e | 1340 | } |
Okan Sahin |
0:047a7089311e | 1341 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1342 | SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value); |
Okan Sahin |
0:047a7089311e | 1343 | } |
Okan Sahin |
0:047a7089311e | 1344 | else { |
Okan Sahin |
0:047a7089311e | 1345 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1346 | } |
Okan Sahin |
0:047a7089311e | 1347 | |
Okan Sahin |
0:047a7089311e | 1348 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1349 | } |
Okan Sahin |
0:047a7089311e | 1350 | |
Okan Sahin |
0:047a7089311e | 1351 | int MAX77659::get_tv_sbb(uint8_t channel, float *voltV) |
Okan Sahin |
0:047a7089311e | 1352 | { |
Okan Sahin |
0:047a7089311e | 1353 | int ret; |
Okan Sahin |
0:047a7089311e | 1354 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1355 | reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1356 | reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; |
Okan Sahin |
0:047a7089311e | 1357 | reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; |
Okan Sahin |
0:047a7089311e | 1358 | |
Okan Sahin |
0:047a7089311e | 1359 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1360 | ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a)); |
Okan Sahin |
0:047a7089311e | 1361 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1362 | |
Okan Sahin |
0:047a7089311e | 1363 | bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0; |
Okan Sahin |
0:047a7089311e | 1364 | } |
Okan Sahin |
0:047a7089311e | 1365 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1366 | ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a)); |
Okan Sahin |
0:047a7089311e | 1367 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1368 | |
Okan Sahin |
0:047a7089311e | 1369 | bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1; |
Okan Sahin |
0:047a7089311e | 1370 | } |
Okan Sahin |
0:047a7089311e | 1371 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1372 | ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a)); |
Okan Sahin |
0:047a7089311e | 1373 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1374 | |
Okan Sahin |
0:047a7089311e | 1375 | bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2; |
Okan Sahin |
0:047a7089311e | 1376 | } |
Okan Sahin |
0:047a7089311e | 1377 | else { |
Okan Sahin |
0:047a7089311e | 1378 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1379 | } |
Okan Sahin |
0:047a7089311e | 1380 | |
Okan Sahin |
0:047a7089311e | 1381 | if (bit_value > 200) bit_value = 200; |
Okan Sahin |
0:047a7089311e | 1382 | *voltV = (bit_value * 0.025f) + 0.5f; |
Okan Sahin |
0:047a7089311e | 1383 | |
Okan Sahin |
0:047a7089311e | 1384 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1385 | } |
Okan Sahin |
0:047a7089311e | 1386 | |
Okan Sahin |
0:047a7089311e | 1387 | int MAX77659::set_op_mode(uint8_t channel, decode_op_mode_t mode) |
Okan Sahin |
0:047a7089311e | 1388 | { |
Okan Sahin |
0:047a7089311e | 1389 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1390 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1391 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1392 | |
Okan Sahin |
0:047a7089311e | 1393 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1394 | SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode, mode); |
Okan Sahin |
0:047a7089311e | 1395 | } |
Okan Sahin |
0:047a7089311e | 1396 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1397 | SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode, mode); |
Okan Sahin |
0:047a7089311e | 1398 | } |
Okan Sahin |
0:047a7089311e | 1399 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1400 | SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode, mode); |
Okan Sahin |
0:047a7089311e | 1401 | } |
Okan Sahin |
0:047a7089311e | 1402 | else { |
Okan Sahin |
0:047a7089311e | 1403 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1404 | } |
Okan Sahin |
0:047a7089311e | 1405 | |
Okan Sahin |
0:047a7089311e | 1406 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1407 | } |
Okan Sahin |
0:047a7089311e | 1408 | |
Okan Sahin |
0:047a7089311e | 1409 | int MAX77659::get_op_mode(uint8_t channel, decode_op_mode_t *mode) |
Okan Sahin |
0:047a7089311e | 1410 | { |
Okan Sahin |
0:047a7089311e | 1411 | int ret; |
Okan Sahin |
0:047a7089311e | 1412 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1413 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1414 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1415 | |
Okan Sahin |
0:047a7089311e | 1416 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1417 | ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); |
Okan Sahin |
0:047a7089311e | 1418 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1419 | |
Okan Sahin |
0:047a7089311e | 1420 | *mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode; |
Okan Sahin |
0:047a7089311e | 1421 | } |
Okan Sahin |
0:047a7089311e | 1422 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1423 | ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); |
Okan Sahin |
0:047a7089311e | 1424 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1425 | |
Okan Sahin |
0:047a7089311e | 1426 | *mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode; |
Okan Sahin |
0:047a7089311e | 1427 | } |
Okan Sahin |
0:047a7089311e | 1428 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1429 | ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); |
Okan Sahin |
0:047a7089311e | 1430 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1431 | |
Okan Sahin |
0:047a7089311e | 1432 | *mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode; |
Okan Sahin |
0:047a7089311e | 1433 | } |
Okan Sahin |
0:047a7089311e | 1434 | else { |
Okan Sahin |
0:047a7089311e | 1435 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1436 | } |
Okan Sahin |
0:047a7089311e | 1437 | |
Okan Sahin |
0:047a7089311e | 1438 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1439 | } |
Okan Sahin |
0:047a7089311e | 1440 | |
Okan Sahin |
0:047a7089311e | 1441 | int MAX77659::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb) |
Okan Sahin |
0:047a7089311e | 1442 | { |
Okan Sahin |
0:047a7089311e | 1443 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1444 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1445 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1446 | |
Okan Sahin |
0:047a7089311e | 1447 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1448 | SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb); |
Okan Sahin |
0:047a7089311e | 1449 | } |
Okan Sahin |
0:047a7089311e | 1450 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1451 | SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb); |
Okan Sahin |
0:047a7089311e | 1452 | } |
Okan Sahin |
0:047a7089311e | 1453 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1454 | SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb); |
Okan Sahin |
0:047a7089311e | 1455 | } |
Okan Sahin |
0:047a7089311e | 1456 | else { |
Okan Sahin |
0:047a7089311e | 1457 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1458 | } |
Okan Sahin |
0:047a7089311e | 1459 | |
Okan Sahin |
0:047a7089311e | 1460 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1461 | } |
Okan Sahin |
0:047a7089311e | 1462 | |
Okan Sahin |
0:047a7089311e | 1463 | int MAX77659::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb) |
Okan Sahin |
0:047a7089311e | 1464 | { |
Okan Sahin |
0:047a7089311e | 1465 | int ret; |
Okan Sahin |
0:047a7089311e | 1466 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1467 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1468 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1469 | |
Okan Sahin |
0:047a7089311e | 1470 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1471 | ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); |
Okan Sahin |
0:047a7089311e | 1472 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1473 | |
Okan Sahin |
0:047a7089311e | 1474 | *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0; |
Okan Sahin |
0:047a7089311e | 1475 | } |
Okan Sahin |
0:047a7089311e | 1476 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1477 | ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); |
Okan Sahin |
0:047a7089311e | 1478 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1479 | |
Okan Sahin |
0:047a7089311e | 1480 | *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1; |
Okan Sahin |
0:047a7089311e | 1481 | } |
Okan Sahin |
0:047a7089311e | 1482 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1483 | ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); |
Okan Sahin |
0:047a7089311e | 1484 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1485 | |
Okan Sahin |
0:047a7089311e | 1486 | *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2; |
Okan Sahin |
0:047a7089311e | 1487 | } |
Okan Sahin |
0:047a7089311e | 1488 | else { |
Okan Sahin |
0:047a7089311e | 1489 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1490 | } |
Okan Sahin |
0:047a7089311e | 1491 | |
Okan Sahin |
0:047a7089311e | 1492 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1493 | } |
Okan Sahin |
0:047a7089311e | 1494 | |
Okan Sahin |
0:047a7089311e | 1495 | int MAX77659::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb) |
Okan Sahin |
0:047a7089311e | 1496 | { |
Okan Sahin |
0:047a7089311e | 1497 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1498 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1499 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1500 | |
Okan Sahin |
0:047a7089311e | 1501 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1502 | SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb); |
Okan Sahin |
0:047a7089311e | 1503 | } |
Okan Sahin |
0:047a7089311e | 1504 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1505 | SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb); |
Okan Sahin |
0:047a7089311e | 1506 | } |
Okan Sahin |
0:047a7089311e | 1507 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1508 | SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb); |
Okan Sahin |
0:047a7089311e | 1509 | } |
Okan Sahin |
0:047a7089311e | 1510 | else { |
Okan Sahin |
0:047a7089311e | 1511 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1512 | } |
Okan Sahin |
0:047a7089311e | 1513 | |
Okan Sahin |
0:047a7089311e | 1514 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1515 | } |
Okan Sahin |
0:047a7089311e | 1516 | |
Okan Sahin |
0:047a7089311e | 1517 | int MAX77659::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb) |
Okan Sahin |
0:047a7089311e | 1518 | { |
Okan Sahin |
0:047a7089311e | 1519 | int ret; |
Okan Sahin |
0:047a7089311e | 1520 | reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1521 | reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; |
Okan Sahin |
0:047a7089311e | 1522 | reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; |
Okan Sahin |
0:047a7089311e | 1523 | |
Okan Sahin |
0:047a7089311e | 1524 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1525 | ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); |
Okan Sahin |
0:047a7089311e | 1526 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1527 | |
Okan Sahin |
0:047a7089311e | 1528 | *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0; |
Okan Sahin |
0:047a7089311e | 1529 | } |
Okan Sahin |
0:047a7089311e | 1530 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1531 | ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); |
Okan Sahin |
0:047a7089311e | 1532 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1533 | |
Okan Sahin |
0:047a7089311e | 1534 | *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1; |
Okan Sahin |
0:047a7089311e | 1535 | } |
Okan Sahin |
0:047a7089311e | 1536 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1537 | ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); |
Okan Sahin |
0:047a7089311e | 1538 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1539 | |
Okan Sahin |
0:047a7089311e | 1540 | *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2; |
Okan Sahin |
0:047a7089311e | 1541 | } |
Okan Sahin |
0:047a7089311e | 1542 | else { |
Okan Sahin |
0:047a7089311e | 1543 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1544 | } |
Okan Sahin |
0:047a7089311e | 1545 | |
Okan Sahin |
0:047a7089311e | 1546 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1547 | } |
Okan Sahin |
0:047a7089311e | 1548 | |
Okan Sahin |
0:047a7089311e | 1549 | int MAX77659::set_op_mode_chg(decode_op_mode_chg_t op_mode_chg) |
Okan Sahin |
0:047a7089311e | 1550 | { |
Okan Sahin |
0:047a7089311e | 1551 | reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; |
Okan Sahin |
0:047a7089311e | 1552 | |
Okan Sahin |
0:047a7089311e | 1553 | SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.op_mode_chg, op_mode_chg); |
Okan Sahin |
0:047a7089311e | 1554 | |
Okan Sahin |
0:047a7089311e | 1555 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1556 | } |
Okan Sahin |
0:047a7089311e | 1557 | |
Okan Sahin |
0:047a7089311e | 1558 | int MAX77659::get_op_mode_chg(decode_op_mode_chg_t *op_mode_chg) |
Okan Sahin |
0:047a7089311e | 1559 | { |
Okan Sahin |
0:047a7089311e | 1560 | int ret; |
Okan Sahin |
0:047a7089311e | 1561 | reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; |
Okan Sahin |
0:047a7089311e | 1562 | |
Okan Sahin |
0:047a7089311e | 1563 | ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); |
Okan Sahin |
0:047a7089311e | 1564 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1565 | |
Okan Sahin |
0:047a7089311e | 1566 | *op_mode_chg = (decode_op_mode_chg_t)reg_cnfg_sbb_top.bits.op_mode_chg; |
Okan Sahin |
0:047a7089311e | 1567 | |
Okan Sahin |
0:047a7089311e | 1568 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1569 | } |
Okan Sahin |
0:047a7089311e | 1570 | |
Okan Sahin |
0:047a7089311e | 1571 | int MAX77659::set_drv_sbb(decode_drv_sbb_t drv_sbb) |
Okan Sahin |
0:047a7089311e | 1572 | { |
Okan Sahin |
0:047a7089311e | 1573 | reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; |
Okan Sahin |
0:047a7089311e | 1574 | |
Okan Sahin |
0:047a7089311e | 1575 | SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.drv_sbb, drv_sbb); |
Okan Sahin |
0:047a7089311e | 1576 | |
Okan Sahin |
0:047a7089311e | 1577 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1578 | } |
Okan Sahin |
0:047a7089311e | 1579 | |
Okan Sahin |
0:047a7089311e | 1580 | int MAX77659::get_drv_sbb(decode_drv_sbb_t *drv_sbb) |
Okan Sahin |
0:047a7089311e | 1581 | { |
Okan Sahin |
0:047a7089311e | 1582 | int ret; |
Okan Sahin |
0:047a7089311e | 1583 | reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; |
Okan Sahin |
0:047a7089311e | 1584 | |
Okan Sahin |
0:047a7089311e | 1585 | ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); |
Okan Sahin |
0:047a7089311e | 1586 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1587 | |
Okan Sahin |
0:047a7089311e | 1588 | *drv_sbb = (decode_drv_sbb_t)reg_cnfg_sbb_top.bits.drv_sbb; |
Okan Sahin |
0:047a7089311e | 1589 | |
Okan Sahin |
0:047a7089311e | 1590 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1591 | } |
Okan Sahin |
0:047a7089311e | 1592 | |
Okan Sahin |
0:047a7089311e | 1593 | int MAX77659::set_ip_chg(decode_ip_chg_t ip_chg) |
Okan Sahin |
0:047a7089311e | 1594 | { |
Okan Sahin |
0:047a7089311e | 1595 | reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; |
Okan Sahin |
0:047a7089311e | 1596 | |
Okan Sahin |
0:047a7089311e | 1597 | SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_chg, ip_chg); |
Okan Sahin |
0:047a7089311e | 1598 | |
Okan Sahin |
0:047a7089311e | 1599 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1600 | } |
Okan Sahin |
0:047a7089311e | 1601 | |
Okan Sahin |
0:047a7089311e | 1602 | int MAX77659::get_ip_chg(decode_ip_chg_t *ip_chg) |
Okan Sahin |
0:047a7089311e | 1603 | { |
Okan Sahin |
0:047a7089311e | 1604 | int ret; |
Okan Sahin |
0:047a7089311e | 1605 | reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; |
Okan Sahin |
0:047a7089311e | 1606 | |
Okan Sahin |
0:047a7089311e | 1607 | ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b)); |
Okan Sahin |
0:047a7089311e | 1608 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1609 | |
Okan Sahin |
0:047a7089311e | 1610 | *ip_chg = (decode_ip_chg_t)reg_cnfg_sbb_top_b.bits.ip_chg; |
Okan Sahin |
0:047a7089311e | 1611 | |
Okan Sahin |
0:047a7089311e | 1612 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1613 | } |
Okan Sahin |
0:047a7089311e | 1614 | |
Okan Sahin |
0:047a7089311e | 1615 | int MAX77659::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb) |
Okan Sahin |
0:047a7089311e | 1616 | { |
Okan Sahin |
0:047a7089311e | 1617 | reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; |
Okan Sahin |
0:047a7089311e | 1618 | |
Okan Sahin |
0:047a7089311e | 1619 | if (channel == 0) { |
Okan Sahin |
0:047a7089311e | 1620 | SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb0, ip_sbb); |
Okan Sahin |
0:047a7089311e | 1621 | } |
Okan Sahin |
0:047a7089311e | 1622 | else if (channel == 1) { |
Okan Sahin |
0:047a7089311e | 1623 | SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb1, ip_sbb); |
Okan Sahin |
0:047a7089311e | 1624 | } |
Okan Sahin |
0:047a7089311e | 1625 | else if (channel == 2) { |
Okan Sahin |
0:047a7089311e | 1626 | SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb2, ip_sbb); |
Okan Sahin |
0:047a7089311e | 1627 | } |
Okan Sahin |
0:047a7089311e | 1628 | else { |
Okan Sahin |
0:047a7089311e | 1629 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1630 | } |
Okan Sahin |
0:047a7089311e | 1631 | |
Okan Sahin |
0:047a7089311e | 1632 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1633 | } |
Okan Sahin |
0:047a7089311e | 1634 | |
Okan Sahin |
0:047a7089311e | 1635 | int MAX77659::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb) |
Okan Sahin |
0:047a7089311e | 1636 | { |
Okan Sahin |
0:047a7089311e | 1637 | int ret; |
Okan Sahin |
0:047a7089311e | 1638 | reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; |
Okan Sahin |
0:047a7089311e | 1639 | |
Okan Sahin |
0:047a7089311e | 1640 | ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b)); |
Okan Sahin |
0:047a7089311e | 1641 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1642 | |
Okan Sahin |
0:047a7089311e | 1643 | if (channel == 0) |
Okan Sahin |
0:047a7089311e | 1644 | *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb0; |
Okan Sahin |
0:047a7089311e | 1645 | else if (channel == 1) |
Okan Sahin |
0:047a7089311e | 1646 | *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb1; |
Okan Sahin |
0:047a7089311e | 1647 | else if (channel == 2) |
Okan Sahin |
0:047a7089311e | 1648 | *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb2; |
Okan Sahin |
0:047a7089311e | 1649 | else |
Okan Sahin |
0:047a7089311e | 1650 | return MAX77659_INVALID_DATA; |
Okan Sahin |
0:047a7089311e | 1651 | |
Okan Sahin |
0:047a7089311e | 1652 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1653 | } |
Okan Sahin |
0:047a7089311e | 1654 | |
Okan Sahin |
0:047a7089311e | 1655 | int MAX77659::set_tv_ldo_offset(decode_tv_ldo_offset_t offset) |
Okan Sahin |
0:047a7089311e | 1656 | { |
Okan Sahin |
0:047a7089311e | 1657 | reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1658 | |
Okan Sahin |
0:047a7089311e | 1659 | SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_offset, offset); |
Okan Sahin |
0:047a7089311e | 1660 | |
Okan Sahin |
0:047a7089311e | 1661 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1662 | } |
Okan Sahin |
0:047a7089311e | 1663 | |
Okan Sahin |
0:047a7089311e | 1664 | int MAX77659::get_tv_ldo_offset(decode_tv_ldo_offset_t *offset) |
Okan Sahin |
0:047a7089311e | 1665 | { |
Okan Sahin |
0:047a7089311e | 1666 | int ret; |
Okan Sahin |
0:047a7089311e | 1667 | reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1668 | |
Okan Sahin |
0:047a7089311e | 1669 | ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); |
Okan Sahin |
0:047a7089311e | 1670 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1671 | |
Okan Sahin |
0:047a7089311e | 1672 | *offset = (decode_tv_ldo_offset_t)reg_cnfg_ldo0_a.bits.tv_ldo_offset; |
Okan Sahin |
0:047a7089311e | 1673 | |
Okan Sahin |
0:047a7089311e | 1674 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1675 | } |
Okan Sahin |
0:047a7089311e | 1676 | |
Okan Sahin |
0:047a7089311e | 1677 | int MAX77659::set_tv_ldo_volt(float voltV) |
Okan Sahin |
0:047a7089311e | 1678 | { |
Okan Sahin |
0:047a7089311e | 1679 | int ret; |
Okan Sahin |
0:047a7089311e | 1680 | uint8_t value; |
Okan Sahin |
0:047a7089311e | 1681 | reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1682 | float voltmV = voltV * 1000; |
Okan Sahin |
0:047a7089311e | 1683 | |
Okan Sahin |
0:047a7089311e | 1684 | ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); |
Okan Sahin |
0:047a7089311e | 1685 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1686 | |
Okan Sahin |
0:047a7089311e | 1687 | if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) { //No Offset |
Okan Sahin |
0:047a7089311e | 1688 | if (voltmV < 500) voltmV = 500; |
Okan Sahin |
0:047a7089311e | 1689 | else if (voltmV > 3675) voltmV = 3675; |
Okan Sahin |
0:047a7089311e | 1690 | |
Okan Sahin |
0:047a7089311e | 1691 | value = (voltmV - 500) / 25; |
Okan Sahin |
0:047a7089311e | 1692 | } |
Okan Sahin |
0:047a7089311e | 1693 | else { //1.325V Offset |
Okan Sahin |
0:047a7089311e | 1694 | if (voltmV < 1825) voltmV = 1825; |
Okan Sahin |
0:047a7089311e | 1695 | else if (voltmV > 5000) voltmV = 5000; |
Okan Sahin |
0:047a7089311e | 1696 | |
Okan Sahin |
0:047a7089311e | 1697 | value = (voltmV - 1825) / 25; |
Okan Sahin |
0:047a7089311e | 1698 | } |
Okan Sahin |
0:047a7089311e | 1699 | |
Okan Sahin |
0:047a7089311e | 1700 | SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_volt, value); |
Okan Sahin |
0:047a7089311e | 1701 | |
Okan Sahin |
0:047a7089311e | 1702 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1703 | } |
Okan Sahin |
0:047a7089311e | 1704 | |
Okan Sahin |
0:047a7089311e | 1705 | int MAX77659::get_tv_ldo_volt(float *voltV) |
Okan Sahin |
0:047a7089311e | 1706 | { |
Okan Sahin |
0:047a7089311e | 1707 | int ret; |
Okan Sahin |
0:047a7089311e | 1708 | uint8_t bit_value; |
Okan Sahin |
0:047a7089311e | 1709 | reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; |
Okan Sahin |
0:047a7089311e | 1710 | |
Okan Sahin |
0:047a7089311e | 1711 | ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); |
Okan Sahin |
0:047a7089311e | 1712 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1713 | |
Okan Sahin |
0:047a7089311e | 1714 | bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo_volt; |
Okan Sahin |
0:047a7089311e | 1715 | if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) //No Offset |
Okan Sahin |
0:047a7089311e | 1716 | *voltV = (bit_value * 0.025f) + 0.5f; |
Okan Sahin |
0:047a7089311e | 1717 | else //1.325V Offset |
Okan Sahin |
0:047a7089311e | 1718 | *voltV = (bit_value * 0.025f) + 1.825f; |
Okan Sahin |
0:047a7089311e | 1719 | |
Okan Sahin |
0:047a7089311e | 1720 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1721 | } |
Okan Sahin |
0:047a7089311e | 1722 | |
Okan Sahin |
0:047a7089311e | 1723 | int MAX77659::set_en_ldo(decode_en_ldo_t en_ldo) |
Okan Sahin |
0:047a7089311e | 1724 | { |
Okan Sahin |
0:047a7089311e | 1725 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1726 | |
Okan Sahin |
0:047a7089311e | 1727 | SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo); |
Okan Sahin |
0:047a7089311e | 1728 | |
Okan Sahin |
0:047a7089311e | 1729 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1730 | } |
Okan Sahin |
0:047a7089311e | 1731 | |
Okan Sahin |
0:047a7089311e | 1732 | int MAX77659::get_en_ldo( decode_en_ldo_t *en_ldo) |
Okan Sahin |
0:047a7089311e | 1733 | { |
Okan Sahin |
0:047a7089311e | 1734 | int ret; |
Okan Sahin |
0:047a7089311e | 1735 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1736 | |
Okan Sahin |
0:047a7089311e | 1737 | ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); |
Okan Sahin |
0:047a7089311e | 1738 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1739 | |
Okan Sahin |
0:047a7089311e | 1740 | *en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo; |
Okan Sahin |
0:047a7089311e | 1741 | |
Okan Sahin |
0:047a7089311e | 1742 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1743 | } |
Okan Sahin |
0:047a7089311e | 1744 | |
Okan Sahin |
0:047a7089311e | 1745 | int MAX77659::set_ade_ldo(decode_ade_ldo_t ade_ldo) |
Okan Sahin |
0:047a7089311e | 1746 | { |
Okan Sahin |
0:047a7089311e | 1747 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1748 | |
Okan Sahin |
0:047a7089311e | 1749 | SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo); |
Okan Sahin |
0:047a7089311e | 1750 | |
Okan Sahin |
0:047a7089311e | 1751 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1752 | } |
Okan Sahin |
0:047a7089311e | 1753 | |
Okan Sahin |
0:047a7089311e | 1754 | int MAX77659::get_ade_ldo(decode_ade_ldo_t *ade_ldo) |
Okan Sahin |
0:047a7089311e | 1755 | { |
Okan Sahin |
0:047a7089311e | 1756 | int ret; |
Okan Sahin |
0:047a7089311e | 1757 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1758 | |
Okan Sahin |
0:047a7089311e | 1759 | ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); |
Okan Sahin |
0:047a7089311e | 1760 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1761 | |
Okan Sahin |
0:047a7089311e | 1762 | *ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo; |
Okan Sahin |
0:047a7089311e | 1763 | |
Okan Sahin |
0:047a7089311e | 1764 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1765 | } |
Okan Sahin |
0:047a7089311e | 1766 | |
Okan Sahin |
0:047a7089311e | 1767 | int MAX77659::set_ldo_md(decode_ldo_md_t mode) |
Okan Sahin |
0:047a7089311e | 1768 | { |
Okan Sahin |
0:047a7089311e | 1769 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1770 | |
Okan Sahin |
0:047a7089311e | 1771 | SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode); |
Okan Sahin |
0:047a7089311e | 1772 | |
Okan Sahin |
0:047a7089311e | 1773 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1774 | } |
Okan Sahin |
0:047a7089311e | 1775 | |
Okan Sahin |
0:047a7089311e | 1776 | int MAX77659::get_ldo_md(decode_ldo_md_t *mode) |
Okan Sahin |
0:047a7089311e | 1777 | { |
Okan Sahin |
0:047a7089311e | 1778 | int ret; |
Okan Sahin |
0:047a7089311e | 1779 | reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; |
Okan Sahin |
0:047a7089311e | 1780 | |
Okan Sahin |
0:047a7089311e | 1781 | ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); |
Okan Sahin |
0:047a7089311e | 1782 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1783 | |
Okan Sahin |
0:047a7089311e | 1784 | *mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md; |
Okan Sahin |
0:047a7089311e | 1785 | |
Okan Sahin |
0:047a7089311e | 1786 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1787 | } |
Okan Sahin |
0:047a7089311e | 1788 | |
Okan Sahin |
0:047a7089311e | 1789 | int MAX77659::irq_disable_all() |
Okan Sahin |
0:047a7089311e | 1790 | { |
Okan Sahin |
0:047a7089311e | 1791 | int ret; |
Okan Sahin |
0:047a7089311e | 1792 | uint8_t reg = 0; |
Okan Sahin |
0:047a7089311e | 1793 | uint8_t status = 0; |
Okan Sahin |
0:047a7089311e | 1794 | |
Okan Sahin |
0:047a7089311e | 1795 | //Disable Masks in INTM_GLBL1 |
Okan Sahin |
0:047a7089311e | 1796 | ret = write_register(INTM_GLBL1, ®); |
Okan Sahin |
0:047a7089311e | 1797 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1798 | |
Okan Sahin |
0:047a7089311e | 1799 | //Disable Masks in INTM_GLBL0 |
Okan Sahin |
0:047a7089311e | 1800 | ret = write_register(INTM_GLBL0, ®); |
Okan Sahin |
0:047a7089311e | 1801 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1802 | |
Okan Sahin |
0:047a7089311e | 1803 | //Disable Masks in INT_M_CHG |
Okan Sahin |
0:047a7089311e | 1804 | ret = write_register(INT_M_CHG, ®); |
Okan Sahin |
0:047a7089311e | 1805 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1806 | |
Okan Sahin |
0:047a7089311e | 1807 | // Clear Interrupt Flags in INT_GLBL1 |
Okan Sahin |
0:047a7089311e | 1808 | ret = read_register(INT_GLBL1, &status); |
Okan Sahin |
0:047a7089311e | 1809 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1810 | |
Okan Sahin |
0:047a7089311e | 1811 | // Clear Interrupt Flags in INT_GLBL0 |
Okan Sahin |
0:047a7089311e | 1812 | ret = read_register(INT_GLBL0, &status); |
Okan Sahin |
0:047a7089311e | 1813 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1814 | |
Okan Sahin |
0:047a7089311e | 1815 | // Clear Interrupt Flags in INT_CHG |
Okan Sahin |
0:047a7089311e | 1816 | ret = read_register(INT_CHG, &status); |
Okan Sahin |
0:047a7089311e | 1817 | if (ret != MAX77659_NO_ERROR) return ret; |
Okan Sahin |
0:047a7089311e | 1818 | |
Okan Sahin |
0:047a7089311e | 1819 | return MAX77659_NO_ERROR; |
Okan Sahin |
0:047a7089311e | 1820 | } |
Okan Sahin |
0:047a7089311e | 1821 | |
Okan Sahin |
0:047a7089311e | 1822 | void MAX77659::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb) |
Okan Sahin |
0:047a7089311e | 1823 | { |
Okan Sahin |
0:047a7089311e | 1824 | interrupt_handler_list[id].func = func; |
Okan Sahin |
0:047a7089311e | 1825 | interrupt_handler_list[id].cb = cb; |
Okan Sahin |
0:047a7089311e | 1826 | } |
Okan Sahin |
0:047a7089311e | 1827 | |
Okan Sahin |
0:047a7089311e | 1828 | void MAX77659::post_interrupt_work() |
Okan Sahin |
0:047a7089311e | 1829 | { |
Okan Sahin |
0:047a7089311e | 1830 | int ret; |
Okan Sahin |
0:047a7089311e | 1831 | uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0; |
Okan Sahin |
0:047a7089311e | 1832 | |
Okan Sahin |
0:047a7089311e | 1833 | |
Okan Sahin |
0:047a7089311e | 1834 | while (true) { |
Okan Sahin |
0:047a7089311e | 1835 | |
Okan Sahin |
0:047a7089311e | 1836 | ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID); |
Okan Sahin |
0:047a7089311e | 1837 | |
Okan Sahin |
0:047a7089311e | 1838 | // Check Interrupt Flags in INT_GLBL0 |
Okan Sahin |
0:047a7089311e | 1839 | ret = read_register(INT_GLBL0, ®); |
Okan Sahin |
0:047a7089311e | 1840 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1841 | |
Okan Sahin |
0:047a7089311e | 1842 | ret = read_register(INTM_GLBL0, &inten); |
Okan Sahin |
0:047a7089311e | 1843 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1844 | |
Okan Sahin |
0:047a7089311e | 1845 | not_inten = ~inten; // 0 means unmasked. |
Okan Sahin |
0:047a7089311e | 1846 | |
Okan Sahin |
0:047a7089311e | 1847 | for (int i = 0; i < INT_GLBL1_GPI1_F; i++) { |
Okan Sahin |
0:047a7089311e | 1848 | mask = (1 << i); |
Okan Sahin |
0:047a7089311e | 1849 | if ((reg & mask) && (not_inten & mask)) { |
Okan Sahin |
0:047a7089311e | 1850 | if (interrupt_handler_list[i].func != NULL) { |
Okan Sahin |
0:047a7089311e | 1851 | interrupt_handler_list[i] |
Okan Sahin |
0:047a7089311e | 1852 | .func(interrupt_handler_list[i].cb); |
Okan Sahin |
0:047a7089311e | 1853 | } |
Okan Sahin |
0:047a7089311e | 1854 | } |
Okan Sahin |
0:047a7089311e | 1855 | } |
Okan Sahin |
0:047a7089311e | 1856 | |
Okan Sahin |
0:047a7089311e | 1857 | // Check Interrupt Flags in INT_GLBL1 |
Okan Sahin |
0:047a7089311e | 1858 | ret = read_register(INT_GLBL1, ®); |
Okan Sahin |
0:047a7089311e | 1859 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1860 | |
Okan Sahin |
0:047a7089311e | 1861 | ret = read_register(INTM_GLBL1, &inten); |
Okan Sahin |
0:047a7089311e | 1862 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1863 | |
Okan Sahin |
0:047a7089311e | 1864 | not_inten = ~inten; // 0 means unmasked. |
Okan Sahin |
0:047a7089311e | 1865 | |
Okan Sahin |
0:047a7089311e | 1866 | for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_THM_I; i++) { |
Okan Sahin |
0:047a7089311e | 1867 | mask = (1 << (i - INT_GLBL1_GPI1_F)); |
Okan Sahin |
0:047a7089311e | 1868 | if ((reg & mask) && (not_inten & mask)) { |
Okan Sahin |
0:047a7089311e | 1869 | if (interrupt_handler_list[i].func != NULL) { |
Okan Sahin |
0:047a7089311e | 1870 | interrupt_handler_list[i] |
Okan Sahin |
0:047a7089311e | 1871 | .func(interrupt_handler_list[i].cb); |
Okan Sahin |
0:047a7089311e | 1872 | } |
Okan Sahin |
0:047a7089311e | 1873 | } |
Okan Sahin |
0:047a7089311e | 1874 | } |
Okan Sahin |
0:047a7089311e | 1875 | |
Okan Sahin |
0:047a7089311e | 1876 | // Check Interrupt Flags in INT_CHG |
Okan Sahin |
0:047a7089311e | 1877 | ret = read_register(INT_CHG, ®); |
Okan Sahin |
0:047a7089311e | 1878 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1879 | |
Okan Sahin |
0:047a7089311e | 1880 | ret = read_register(INT_M_CHG, &inten); |
Okan Sahin |
0:047a7089311e | 1881 | if (ret != MAX77659_NO_ERROR) return; |
Okan Sahin |
0:047a7089311e | 1882 | not_inten = ~inten; // 0 means unmasked. |
Okan Sahin |
0:047a7089311e | 1883 | |
Okan Sahin |
0:047a7089311e | 1884 | for (int i = INT_CHG_THM_I; i < INT_CHG_END; i++) { |
Okan Sahin |
0:047a7089311e | 1885 | mask = (1 << (i - INT_CHG_THM_I)); |
Okan Sahin |
0:047a7089311e | 1886 | if ((reg & mask) && (not_inten & mask)) { |
Okan Sahin |
0:047a7089311e | 1887 | if (interrupt_handler_list[i].func != NULL) { |
Okan Sahin |
0:047a7089311e | 1888 | interrupt_handler_list[i] |
Okan Sahin |
0:047a7089311e | 1889 | .func(interrupt_handler_list[i].cb); |
Okan Sahin |
0:047a7089311e | 1890 | } |
Okan Sahin |
0:047a7089311e | 1891 | } |
Okan Sahin |
0:047a7089311e | 1892 | } |
Okan Sahin |
0:047a7089311e | 1893 | } |
Okan Sahin |
0:047a7089311e | 1894 | } |
Okan Sahin |
0:047a7089311e | 1895 | |
Okan Sahin |
0:047a7089311e | 1896 | void MAX77659::interrupt_handler() |
Okan Sahin |
0:047a7089311e | 1897 | { |
Okan Sahin |
0:047a7089311e | 1898 | post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID); |
Okan Sahin |
0:047a7089311e | 1899 | } |