MAX77655.cpp

00001 /*******************************************************************************
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00010  *
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00031  */
00032 
00033 #include <Thread.h>
00034 #include "MAX77655.h"
00035 #include <math.h>
00036 
00037 #define POST_INTR_WORK_SIGNAL_ID            0x1
00038 #define TO_UINT8                            0xFF
00039 #define TO_UINT16                           0xFFFF
00040 
00041 MAX77655::MAX77655(I2C *i2c, PinName IRQPin):interrupt_handler_list{NULL}
00042 {
00043     if (i2c == NULL)
00044         return;
00045 
00046     i2c_handler = i2c;
00047 
00048     if (IRQPin != NC) {
00049             irq_disable_all();
00050             post_intr_work_thread = new Thread();
00051             post_intr_work_thread->start(Callback<void()>(this, &MAX77655::post_interrupt_work));
00052 
00053             this->irq_pin = new InterruptIn(IRQPin);
00054             this->irq_pin->fall(Callback<void()>(this, &MAX77655::interrupt_handler));
00055             this->irq_pin->enable_irq();
00056         } else {
00057             this->irq_pin = NULL;
00058         }
00059 }
00060 
00061 MAX77655::~MAX77655()
00062 {
00063     if (post_intr_work_thread)
00064             delete post_intr_work_thread;
00065 
00066         if (irq_pin)
00067             delete irq_pin;
00068 }
00069 
00070 int MAX77655::read_register(uint8_t reg, uint8_t *value)
00071 {
00072     int rtn_val;
00073 
00074         if (value == NULL)
00075             return MAX77655_VALUE_NULL;
00076 
00077         rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)&reg, 1, true);
00078         if (rtn_val != 0)
00079             return MAX77655_WRITE_DATA_FAILED;
00080 
00081         rtn_val = i2c_handler->read(MAX77655_I2C_ADDRESS, (char *) value, 1, false);
00082         if (rtn_val < 0)
00083             return MAX77655_READ_DATA_FAILED;
00084 
00085         return MAX77655_NO_ERROR;
00086 }
00087 
00088 int MAX77655::write_register(uint8_t reg, const uint8_t *value)
00089 {
00090         int rtn_val;
00091         unsigned char local_data[2];
00092 
00093         if (value == NULL)
00094             return MAX77655_VALUE_NULL;
00095 
00096         local_data[0] = reg;
00097 
00098         memcpy(&local_data[1], value, 1);
00099 
00100         rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
00101         if (rtn_val != MAX77655_NO_ERROR)
00102             return MAX77655_WRITE_DATA_FAILED;
00103 
00104         return MAX77655_NO_ERROR;
00105 }
00106 
00107 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value)                             \
00108             int ret_val;                                                                    \
00109             ret_val = read_register(address, (uint8_t *)&(reg_name));                       \
00110             if (ret_val) {                                                                  \
00111                 return ret_val;                                                             \
00112             }                                                                               \
00113             bit_field_name = value;                                                         \
00114             ret_val = write_register(address, (uint8_t *)&(reg_name));                      \
00115             if (ret_val) {                                                                  \
00116             return ret_val;                                                             \
00117             }
00118 
00119 int MAX77655::set_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t config)
00120 {
00121     int ret;
00122     reg_cnfg_glbl_a_t reg_cnfg_glbl_a;
00123     
00124     ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
00125     if (ret != MAX77655_NO_ERROR) return ret;
00126     
00127     switch (bit_field)
00128     {
00129     case CNFG_GLBL_A_DBEN_nEN:
00130         reg_cnfg_glbl_a.bits.dben_nen = config;
00131         break;
00132     case CNFG_GLBL_A_nEN_MODE:
00133         reg_cnfg_glbl_a.bits.nen_mode = config;
00134         break;
00135     case CNFG_GLBL_A_MRT:
00136         reg_cnfg_glbl_a.bits.mrt = config;
00137         break;
00138     case CNFG_GLBL_A_BIAS_LPM:
00139         reg_cnfg_glbl_a.bits.bias_lpm = config;
00140         break;
00141     case CNFG_GLBL_A_PU_DIS:
00142         reg_cnfg_glbl_a.bits.pu_dis = config;
00143         break;
00144     default:
00145         return MAX77655_INVALID_DATA;
00146         break;      
00147     }
00148     
00149     return write_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
00150 }
00151 
00152 int MAX77655::get_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t *config)
00153 {
00154         int ret;
00155     reg_cnfg_glbl_a_t reg_cnfg_glbl_a = {0};
00156     
00157     ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
00158     if (ret != MAX77655_NO_ERROR) return ret;
00159 
00160         switch (bit_field)
00161     {   
00162     case CNFG_GLBL_A_DBEN_nEN:
00163         *config = (uint8_t)reg_cnfg_glbl_a.bits.dben_nen;
00164         break;
00165     case CNFG_GLBL_A_nEN_MODE:
00166         *config = (uint8_t)reg_cnfg_glbl_a.bits.nen_mode;
00167         break;
00168     case CNFG_GLBL_A_MRT:
00169         *config = (uint8_t)reg_cnfg_glbl_a.bits.mrt;
00170         break;
00171     case CNFG_GLBL_A_BIAS_LPM:
00172         *config = (uint8_t)reg_cnfg_glbl_a.bits.bias_lpm;
00173         break;
00174     case CNFG_GLBL_A_PU_DIS:
00175         *config = (uint8_t)reg_cnfg_glbl_a.bits.pu_dis;
00176         break;
00177     default:
00178         return MAX77655_INVALID_DATA;
00179         break;      
00180     }
00181 
00182         return MAX77655_NO_ERROR;
00183 }
00184 
00185 int MAX77655::set_sft_ctrl(decode_sft_ctrl_t config)
00186 {   
00187     reg_cnfg_glbl_b_t reg_cnfg_glbl_b;
00188     
00189     SET_BIT_FIELD(CNFG_GLBL_B, reg_cnfg_glbl_b, reg_cnfg_glbl_b.bits.sft_ctrl, config);
00190     
00191     return MAX77655_NO_ERROR;
00192 }
00193 
00194 int MAX77655::get_sft_ctrl(decode_sft_ctrl_t *config)
00195 {
00196     int ret;
00197     reg_cnfg_glbl_b_t reg_cnfg_glbl_b = {0};
00198 
00199     ret = read_register(CNFG_GLBL_B, (uint8_t *)&(reg_cnfg_glbl_b));
00200     if (ret != MAX77655_NO_ERROR) return ret;
00201 
00202     *config = (decode_sft_ctrl_t)reg_cnfg_glbl_b.bits.sft_ctrl;
00203 
00204         return MAX77655_NO_ERROR;
00205 }
00206 
00207 int MAX77655::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
00208 {
00209     int ret;
00210     uint8_t reg_addr;
00211     reg_intm_glbl_t reg_intm_glbl;
00212     
00213     ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
00214     
00215     if (ret != MAX77655_NO_ERROR) return ret;
00216     
00217     switch (bit_field)
00218     {
00219     case INTM_GLBL_nEN_FM:
00220         reg_intm_glbl.bits.nen_fm = maskBit;
00221         break;
00222     case INTM_GLBL_nEN_RM:
00223         reg_intm_glbl.bits.nen_rm = maskBit;
00224         break;
00225     case INTM_GLBL_TJAL1_RM:
00226         reg_intm_glbl.bits.tjal1_rm = maskBit;
00227         break;
00228     case INTM_GLBL_TJAL2_RM:
00229         reg_intm_glbl.bits.tjal2_rm = maskBit;
00230         break;
00231     case INTM_GLBL_SBB0_FM:
00232         reg_intm_glbl.bits.sbb0_fm = maskBit;
00233         break;
00234     case INTM_GLBL_SBB1_FM:
00235         reg_intm_glbl.bits.sbb1_fm = maskBit;
00236         break;
00237     case INTM_GLBL_SBB2_FM:
00238         reg_intm_glbl.bits.sbb2_fm = maskBit;
00239         break;
00240     case INTM_GLBL_SBB3_FM:
00241         reg_intm_glbl.bits.sbb3_fm = maskBit;
00242         break;
00243     default:
00244         return MAX77655_INVALID_DATA;
00245         break;      
00246     }
00247     
00248     return write_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
00249 }
00250 
00251 int MAX77655::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
00252 {
00253         int ret;
00254     uint8_t reg_addr;
00255     reg_intm_glbl_t reg_intm_glbl = {0};
00256     
00257     ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
00258     
00259     if (ret != MAX77655_NO_ERROR) return ret;
00260 
00261     switch (bit_field)
00262     {   
00263     case INTM_GLBL_nEN_FM:
00264         *maskBit = (uint8_t)reg_intm_glbl.bits.nen_fm;
00265         break;
00266     case INTM_GLBL_nEN_RM:
00267         *maskBit = (uint8_t)reg_intm_glbl.bits.nen_rm;
00268         break;
00269     case INTM_GLBL_TJAL1_RM:
00270         *maskBit = (uint8_t)reg_intm_glbl.bits.tjal1_rm;
00271         break;
00272     case INTM_GLBL_TJAL2_RM:
00273         *maskBit = (uint8_t)reg_intm_glbl.bits.tjal2_rm;
00274         break;
00275     case INTM_GLBL_SBB0_FM:
00276         *maskBit = (uint8_t)reg_intm_glbl.bits.sbb0_fm;
00277         break;
00278     case INTM_GLBL_SBB1_FM:
00279         *maskBit = (uint8_t)reg_intm_glbl.bits.sbb1_fm;
00280         break;
00281     case INTM_GLBL_SBB2_FM:
00282         *maskBit = (uint8_t)reg_intm_glbl.bits.sbb2_fm;
00283         break;
00284     case INTM_GLBL_SBB3_FM:
00285         *maskBit = (uint8_t)reg_intm_glbl.bits.sbb3_fm;
00286         break;
00287     default:
00288         return MAX77655_INVALID_DATA;
00289         break;      
00290     }
00291 
00292         return MAX77655_NO_ERROR;
00293 }
00294 
00295 int MAX77655::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
00296 {
00297     int ret;
00298         reg_stat_glbl_t reg_stat_glbl = {0};
00299 
00300         ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00301         if (ret != MAX77655_NO_ERROR) return ret;
00302 
00303     switch (bit_field)
00304     {
00305     case STAT_GLBL_STAT_EN:
00306         *status = (uint8_t)reg_stat_glbl.bits.stat_en;
00307         break;
00308     case STAT_GLBL_TJAL1_S:
00309         *status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
00310         break;
00311     case STAT_GLBL_TJAL2_S:
00312         *status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
00313         break;
00314     case STAT_GLBL_SBB0_S:
00315         *status = (uint8_t)reg_stat_glbl.bits.sbb0_s;
00316         break;
00317     case STAT_GLBL_SBB1_S:
00318         *status = (uint8_t)reg_stat_glbl.bits.sbb1_s;
00319         break;
00320     case STAT_GLBL_SBB2_S:
00321         *status = (uint8_t)reg_stat_glbl.bits.sbb2_s;
00322         break;
00323     case STAT_GLBL_SBB3_S:
00324         *status = (uint8_t)reg_stat_glbl.bits.sbb3_s;
00325         break;
00326     default:
00327         ret = MAX77655_INVALID_DATA;
00328         break;      
00329     }
00330 
00331     return ret;
00332 }
00333 
00334 int MAX77655::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
00335 {
00336     int ret;
00337     reg_ercflag_t reg_ercflag = {0};
00338 
00339     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00340     if (ret != MAX77655_NO_ERROR) return ret;
00341     
00342     switch (bit_field)
00343     {
00344     case ERCFLAG_TOVLD:
00345         *flag = (uint8_t)reg_ercflag.bits.tovld;
00346         break;
00347     case ERCFLAG_OVLO:
00348         *flag = (uint8_t)reg_ercflag.bits.ovlo;
00349         break;
00350     case ERCFLAG_UVLO:
00351         *flag = (uint8_t)reg_ercflag.bits.uvlo;
00352         break;
00353     case ERCFLAG_MRST:
00354         *flag = (uint8_t)reg_ercflag.bits.mrst;
00355         break;
00356     case ERCFLAG_SFT_OFF_F:
00357         *flag = (uint8_t)reg_ercflag.bits.sft_off_f;
00358         break;
00359     case ERCFLAG_SFT_CRST_F:
00360         *flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
00361         break;
00362     default:
00363         ret = MAX77655_INVALID_DATA;
00364         break;      
00365     }
00366 
00367     return ret;
00368 }
00369 
00370 int MAX77655::get_cid(void) {
00371         char rbuf[1] = {0};
00372         int ret;
00373 
00374         ret = read_register(CID, (uint8_t *)&(rbuf));
00375     if (ret != MAX77655_NO_ERROR) return ret;
00376  
00377         return *rbuf;
00378 }
00379 
00380 int MAX77655::set_drv_sbb(decode_drv_sbb_t config)
00381 {   
00382     reg_config_sbb_top_t reg_config_sbb_top;
00383     
00384     SET_BIT_FIELD(CONFIG_SBB_TOP, reg_config_sbb_top, reg_config_sbb_top.bits.drv_sbb, config);
00385     
00386     return MAX77655_NO_ERROR;
00387 }
00388 
00389 int MAX77655::get_drv_sbb(decode_drv_sbb_t *config)
00390 {
00391         int ret;
00392         reg_config_sbb_top_t reg_config_sbb_top = {0};
00393 
00394     ret = read_register(CONFIG_SBB_TOP, (uint8_t *)&(reg_config_sbb_top));
00395     if (ret != MAX77655_NO_ERROR) return ret;
00396 
00397     *config = (decode_drv_sbb_t)reg_config_sbb_top.bits.drv_sbb;
00398 
00399         return MAX77655_NO_ERROR;
00400 }
00401 
00402 int MAX77655::set_tv_sbb(uint8_t channel, float voltV)
00403 {
00404     uint8_t value;
00405     reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a;
00406     reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a;
00407     reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a;
00408     reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a;
00409     float voltmV = voltV * 1000;
00410     
00411     if (voltmV < 500) voltmV = 500;
00412     else if (voltmV > 4000) voltmV = 4000;
00413 
00414     value = (voltmV - 500) / 25;
00415 
00416     if (channel == 0) {
00417         SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
00418     }       
00419     else if (channel == 1) {
00420         SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
00421     }
00422     else if (channel == 2) {
00423         SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
00424     }
00425     else if (channel == 3) {
00426         SET_BIT_FIELD(CNFG_SBB3_A, reg_cnfg_sbb3_a, reg_cnfg_sbb3_a.bits.tv_sbb3, value);
00427     }
00428     else {
00429         return MAX77655_INVALID_DATA;
00430     }
00431     
00432     return MAX77655_NO_ERROR;
00433 }
00434 
00435 int MAX77655::get_tv_sbb(uint8_t channel, float *voltV)
00436 {
00437     int ret;
00438     uint8_t bit_value;
00439     reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
00440     reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
00441     reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
00442     reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a = {0};
00443 
00444     if (channel == 0) { 
00445         ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
00446         if (ret != MAX77655_NO_ERROR) return ret;
00447         
00448         bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
00449     }
00450     else if (channel == 1) {
00451         ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
00452         if (ret != MAX77655_NO_ERROR) return ret;
00453     
00454         bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
00455     }
00456     else if (channel == 2) {
00457         ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
00458         if (ret != MAX77655_NO_ERROR) return ret;
00459     
00460         bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
00461     }
00462     else if (channel == 3) {
00463         ret = read_register(CNFG_SBB3_A, (uint8_t *)&(reg_cnfg_sbb3_a));
00464         if (ret != MAX77655_NO_ERROR) return ret;
00465     
00466         bit_value = (uint8_t)reg_cnfg_sbb3_a.bits.tv_sbb3;
00467     }
00468     else { 
00469         return MAX77655_INVALID_DATA;
00470     }
00471     
00472     if (bit_value > 141) bit_value = 141;
00473     *voltV = (bit_value * 0.025f) + 0.5f;
00474 
00475         return MAX77655_NO_ERROR;
00476 }
00477 
00478 int MAX77655::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
00479 {   
00480     reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
00481     reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
00482     reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
00483     reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
00484     
00485     if (channel == 0) {
00486         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
00487     }
00488     else if (channel == 1) {
00489         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
00490     }
00491     else if (channel == 2) {
00492         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
00493     }
00494     else if (channel == 3) {
00495         SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.ade_sbb3, ade_sbb);
00496     }
00497     else {
00498         return MAX77655_INVALID_DATA;
00499     }
00500     
00501     return MAX77655_NO_ERROR;
00502 }
00503 
00504 int MAX77655::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
00505 {
00506         int ret;
00507         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
00508     reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
00509     reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
00510     reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
00511 
00512     if (channel == 0) {
00513         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
00514         if (ret != MAX77655_NO_ERROR) return ret;
00515 
00516         *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
00517     }
00518     else if (channel == 1) {
00519         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
00520         if (ret != MAX77655_NO_ERROR) return ret;
00521 
00522         *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
00523     }
00524     else if (channel == 2) {
00525         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
00526         if (ret != MAX77655_NO_ERROR) return ret;
00527 
00528         *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
00529     }
00530     else if (channel == 3) {
00531         ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
00532         if (ret != MAX77655_NO_ERROR) return ret;
00533 
00534         *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb3_b.bits.ade_sbb3;
00535     }
00536     else {
00537         return MAX77655_INVALID_DATA;
00538     }
00539 
00540         return MAX77655_NO_ERROR;
00541 }
00542 
00543 int MAX77655::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
00544 {   
00545     reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
00546     reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
00547     reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
00548     reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
00549     
00550     if (channel == 0) {
00551         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
00552     }
00553     else if (channel == 1) {
00554         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
00555     }
00556     else if (channel == 2) {
00557         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
00558     }
00559     else if (channel == 3) {
00560         SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.en_sbb3, en_sbb);
00561     }
00562     else {
00563         return MAX77655_INVALID_DATA;
00564     }
00565     
00566     return MAX77655_NO_ERROR;
00567 }
00568 
00569 int MAX77655::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
00570 {
00571         int ret;
00572         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
00573     reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
00574     reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
00575     reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
00576 
00577     if (channel == 0) {
00578         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
00579         if (ret != MAX77655_NO_ERROR) return ret;
00580 
00581         *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
00582     }
00583     else if (channel == 1) {
00584         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
00585         if (ret != MAX77655_NO_ERROR) return ret;
00586 
00587         *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
00588     }
00589     else if (channel == 2) {
00590         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
00591         if (ret != MAX77655_NO_ERROR) return ret;
00592 
00593         *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
00594     }
00595     else if (channel == 3) {
00596         ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
00597         if (ret != MAX77655_NO_ERROR) return ret;
00598 
00599         *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb3_b.bits.en_sbb3;
00600     }
00601     else return MAX77655_INVALID_DATA;
00602 
00603         return MAX77655_NO_ERROR;
00604 }
00605 
00606 int MAX77655::irq_disable_all()
00607 {
00608         int ret;
00609         uint8_t reg = 0;
00610         uint8_t status = 0;
00611 
00612         //Disable Masks in INTM_GLBL
00613         ret = write_register(INTM_GLBL, &reg);
00614         if (ret != MAX77655_NO_ERROR) return ret;
00615 
00616         // Clear Interrupt Flags in INT_GLBL
00617         return read_register(INT_GLBL, &status);
00618 }
00619 
00620 void MAX77655::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
00621 {
00622         interrupt_handler_list[id].func = func;
00623         interrupt_handler_list[id].cb = cb;
00624 }
00625 
00626 void MAX77655::post_interrupt_work()
00627 {
00628         int ret;
00629         uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
00630 
00631         while (true) {
00632 
00633             ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
00634             // Check Interrupt Flags in INT_GLBL0
00635             ret = read_register(INT_GLBL, &reg);
00636             if (ret != MAX77655_NO_ERROR) return;
00637 
00638             ret = read_register(INTM_GLBL, &inten);
00639             if (ret != MAX77655_NO_ERROR) return;
00640 
00641             not_inten = ~inten; // 0 means unmasked.
00642 
00643             for (int i = 0; i <= INT_GLBL_SBB3_FM; i++) {
00644                     mask = (1 << i);
00645             /*
00646             ***************************************************
00647             This is special case.  when nEN is pulled high, the
00648             on/off controller initiates a power-down sequence and
00649             goes to shutdown mode.
00650             ***************************************************
00651             */
00652                     if (((reg & mask) && (not_inten & mask))
00653                 || ((reg & (1 << INT_GLBL_nEN_F)) && (i == INT_GLBL_nEN_F))
00654                 || ((reg & (1 << INT_GLBL_nEN_R)) && (i == INT_GLBL_nEN_R))) {
00655                     if (interrupt_handler_list[i].func != NULL) {
00656                         interrupt_handler_list[i]
00657                         .func(interrupt_handler_list[i].cb);
00658                     }
00659                 }
00660             }
00661         }
00662 }
00663 
00664 void MAX77655::interrupt_handler()
00665 {
00666         post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
00667 }
00668