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MAX77654
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MAX77654_regs.h
00001 /******************************************************************************* 00002 * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files(the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc.shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc.Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc.retains all 00030 * ownership rights. 00031 ******************************************************************************* 00032 */ 00033 00034 #ifndef MAX77654_REGS_H_ 00035 #define MAX77654_REGS_H_ 00036 00037 /** 00038 * @brief INT_GLBL0 Register 00039 * 00040 * Address : 0x00 00041 */ 00042 typedef union { 00043 unsigned char raw; 00044 struct { 00045 unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0. 00046 Note that "GPI" refers to the GPIO programmed to be an input. 00047 0 = No GPI falling edges have occurred since the last time this bit was read. 00048 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00049 unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1. 00050 Note that "GPI" refers to the GPIO programmed to be an input. 00051 0 = No GPI rising edges have occurred since the last time this bit was read. 00052 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00053 unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2. 00054 0 = No nEN falling edges have occurred since the last time this bit was read. 00055 1 = A nEN falling edge as occurred since the last time this bit was read. */ 00056 unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3. 00057 0 = No nEN rising edges have occurred since the last time this bit was read. 00058 1 = A nEN rising edge as occurred since the last time this bit was read. */ 00059 unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4. 00060 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. 00061 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */ 00062 unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5. 00063 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. 00064 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */ 00065 unsigned char d0d1_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 6. 00066 0 = The LDO has not detected dropout since the last time this bit was read. 00067 1 = The LDO has detected dropout since the last time this bit was read. */ 00068 unsigned char dod0_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 7. 00069 0 = The LDO has not detected dropout since the last time this bit was read. 00070 1 = The LDO has detected dropout since the last time this bit was read. */ 00071 } bits; 00072 } reg_int_glbl0_t; 00073 00074 /** 00075 * @brief INT_GLBL1 Register 00076 * 00077 * Address : 0x04 00078 */ 00079 typedef union { 00080 unsigned char raw; 00081 struct { 00082 unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0. 00083 Note that "GPI" refers to the GPIO programmed to be an input. 00084 0 = No GPI falling edges have occurred since the last time this bit was read. 00085 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00086 unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1. 00087 Note that "GPI" refers to the GPIO programmed to be an input. 00088 0 = No GPI rising edges have occurred since the last time this bit was read. 00089 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00090 unsigned char gpi2_f : 1; /**< GPI Falling Interrupt.Bit 2. 00091 0 = No GPI falling edges have occurred since the last time this bit was read. 00092 1 = A GPI falling edge as occurred since the last time this bit was read. */ 00093 unsigned char gpi2_r : 1; /**< GPI Rising Interrupt. Bit 3. 00094 Note that "GPI" refers to the GPIO programmed to be an input. 00095 0 = No GPI rising edges have occurred since the last time this bit was read. 00096 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00097 unsigned char sbb_to : 1; /**< SBB Timeout. Bit 4. 00098 0 = NO SBB timeout occurred since the last time this bit was read 00099 1 = SBB timeout occurred since the last time this bit was read */ 00100 unsigned char ldo0_f : 1; /**< LDO0 Fault Interrupt. Bit 5. 00101 0 = No fault has occurred on LDO0 since the last time this bit was read. 00102 1 = LDO0 has fallen out of regulation since the last time this bit was read. */ 00103 unsigned char ldo1_f : 1; /**< LDO1 Fault Interrupt. Bit 6. 00104 0 = No fault has occurred on LDO1 since the last time this bit was read. 00105 1 = LDO1 has fallen out of regulation since the last time this bit was read. */ 00106 unsigned char rsvd : 1; /**< Reserved. 00107 Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ 00108 } bits; 00109 } reg_int_glbl1_t; 00110 00111 /** 00112 * @brief ERCFLAG Register 00113 * 00114 * Address : 0x05 00115 */ 00116 typedef union { 00117 unsigned char raw; 00118 struct { 00119 unsigned char tovld : 1; /**< Thermal Overload. Bit 0. 00120 0 = Thermal overload has not occurred since the last read of this register. 00121 1 = Thermal overload has occurred since the list read of this register. 00122 This indicates that the junction temperature has exceeded 165ºC. */ 00123 unsigned char sysovlo : 1; /**< SYS Domain Overvoltage Lockout. Bit 1. 00124 0 = The SYS domain overvoltage lockout has not occurred since this last read of this register. 00125 1 = The SYS domain overvoltage lockout has occurred since the last read of this register. */ 00126 unsigned char sysuvlo : 1; /**< SYS Domain Undervoltage Lockout. Bit 2. 00127 0 = The SYS domain undervoltage lockout has not occurred since this last read of this register. 00128 1 = The SYS domain undervoltage lockout has occurred since the last read of this register. */ 00129 unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3. 00130 0 = A Manual Reset has not occurred since this last read of this register. 00131 1 = A Manual Reset has occurred since this last read of this register. */ 00132 unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4. 00133 0 = The SFT_OFF function has not occurred since the last read of this register. 00134 1 = The SFT_OFF function has occurred since the last read of this register. */ 00135 unsigned char sft_crst_f: 1; /**< Software Cold Reset Flag. Bit 5. 00136 0 = The software cold reset has not occurred since the last read of this register. 00137 1 = The software cold reset has occurred since the last read of this register. */ 00138 unsigned char wdt_off : 1; /**< Watchdog Timer OFF Flag. Bit 6. 00139 This bit sets when the watchdog timer expires and causes a power-off. 00140 0 = Watchdog timer has not caused a power-off since the last time this bit was read. 00141 1 = Watchdog timer has expired and caused a power-off since the last time this bit was read. */ 00142 unsigned char wdt_rst : 1; /**< Watchdog Timer Reset Flag. Bit 7. 00143 This bit sets when the watchdog timer expires and causes a power-reset. 00144 0 = Watchdog timer has not caused a power-reset since the last time this bit was read. 00145 1 = Watchdog timer has expired and caused a power-reset since the last time this bit was read.*/ 00146 } bits; 00147 } reg_ercflag_t; 00148 00149 /** 00150 * @brief STAT_GLBL Register 00151 * 00152 * Address : 0x06 00153 */ 00154 typedef union { 00155 unsigned char raw; 00156 struct { 00157 unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0. 00158 0 = unmasked gate drive is logic low 00159 1 = unmasked gate drive is logic high */ 00160 unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1. 00161 0 = nEN is not active (logic high) 00162 1 = nEN is active (logic low) */ 00163 unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2. 00164 0 = The junction temperature is less than TJAL1 00165 1 = The junction temperature is greater than TJAL1 */ 00166 unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3. 00167 0 = The junction temperature is less than TJAL2 00168 1 = The junction temperature is greater than TJAL2 */ 00169 unsigned char dod1_s : 1; /**< LDO1 Dropout Detector Rising Status. Bit 4. 00170 0 = LDO1 is not in dropout 00171 1 = LDO1 is in dropout */ 00172 unsigned char dod0_s : 1; /**< LDO0 Dropout Detector Rising Status. Bit 5. 00173 0 = LDO0 is not in dropout 00174 1 = LDO0 is in dropout */ 00175 unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6. 00176 0 = Main Bias is not ready. 00177 1 = Main Bias enabled and ready. */ 00178 unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7. 00179 0 = MAX77654 00180 1 = Reserved */ 00181 } bits; 00182 } reg_stat_glbl_t; 00183 00184 /** 00185 * @brief INTM_GLBL1 Register 00186 * 00187 * Address : 0x08 00188 */ 00189 typedef union { 00190 unsigned char raw; 00191 struct { 00192 unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00193 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00194 nIRQ goes high when all interrupt bits are cleared. 00195 1 = Masked. nIRQ does not go low due to GPI_F. */ 00196 unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00197 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00198 nIRQ goes high when all interrupt bits are cleared. 00199 1 = Masked. nIRQ does not go low due to GPI_R. */ 00200 unsigned char gpi2_fm : 1; /**< GPI Falling Interrupt Mask. Bit 2. 00201 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00202 nIRQ goes high when all interrupt bits are cleared. 00203 1 = Masked. nIRQ does not go low due to GPI_F. */ 00204 unsigned char gpi2_rm : 1; /**< GPI Rising Interrupt Mask. Bit 3. 00205 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00206 nIRQ goes high when all interrupt bits are cleared. 00207 1 = Masked. nIRQ does not go low due to GPI_R. */ 00208 unsigned char sbb_to_m : 1; /**< SBB Timeout Mask. Bit 4. 00209 0 = Unmasked. If SBB_TO goes from 0 to 1, then nIRQ goes low. 00210 nIRQ goes high when all interrupt bits are cleared. 00211 1 = Masked. nIRQ does not go low due to SBB_TO */ 00212 unsigned char ldo0_m : 1; /**< LDO0 Fault Interrupt. Bit 5. 00213 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. 00214 nIRQ goes high when all interrupt bits are cleared. 00215 1 = Masked. nIRQ does not go low due to LDO0_F. */ 00216 unsigned char ldo1_m : 1; /**< LDO1 Fault Interrupt Mask. Bit 6. 00217 0 = Unmasked. If LDO1_F goes from 0 to 1, then nIRQ goes low. 00218 nIRQ goes high when all interrupt bits are cleared. 00219 1 = Masked. nIRQ does not go low due to LDO1_F. */ 00220 unsigned char rsvd : 1; /**< Reserved. 00221 Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ 00222 } bits; 00223 } reg_intm_glbl1_t; 00224 00225 /** 00226 * @brief INTM_GLBL0 Register 00227 * 00228 * Address : 0x09 00229 */ 00230 typedef union { 00231 unsigned char raw; 00232 struct { 00233 unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00234 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00235 nIRQ goes high when all interrupt bits are cleared. 00236 1 = Masked. nIRQ does not go low due to GPI_F. */ 00237 unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00238 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00239 nIRQ goes high when all interrupt bits are cleared. 00240 1 = Masked. nIRQ does not go low due to GPI_R. */ 00241 unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2. 00242 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. 00243 nIRQ goes high when all interrupt bits are cleared. 00244 1 = Masked. nIRQ does not go low due to nEN_F. */ 00245 unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3. 00246 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. 00247 nIRQ goes high when all interrupt bits are cleared. 00248 1 = Masked. nIRQ does not go low due to nEN_R. */ 00249 unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4. 00250 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. 00251 nIRQ goes high when all interrupt bits are cleared. 00252 1 = Masked. nIRQ does not go low due to TJAL1_R. */ 00253 unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5. 00254 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. 00255 nIRQ goes high when all interrupt bits are cleared. 00256 1 = Masked. nIRQ does not go low due to TJAL2_R. */ 00257 unsigned char dod1_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 6. 00258 0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. 00259 nIRQ goes high when all interrupt bits are cleared. 00260 1 = Masked. nIRQ does not go low due to DOD1_R. */ 00261 unsigned char dod0_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 7. 00262 0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low. 00263 nIRQ goes high when all interrupt bits are cleared. 00264 1 = Masked. nIRQ does not go low due to DOD0_R. */ 00265 } bits; 00266 } reg_intm_glbl0_t; 00267 00268 /** 00269 * @brief CNFG_GLBL Register 00270 * 00271 * Address : 0x10 00272 */ 00273 typedef union { 00274 unsigned char raw; 00275 struct { 00276 unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0. 00277 0b00 = No Action 00278 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. 00279 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 00280 0b11 = Factory-Ship Mode Enter (FSM). */ 00281 unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2. 00282 0 = 500μs Debounce 00283 1 = 30ms Debounce */ 00284 unsigned char nen_mode : 1; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 3. 00285 0 = Push-Button Mode 00286 1 = Slide-Switch Mode */ 00287 unsigned char sbia_en : 1; /**< Main Bias Enable Software Request. Bit 4. 00288 0 = Main Bias not enabled by software. 00289 Note that the main bias may be on via the on/off controller. 00290 1 = Main Bias force enabled by software. */ 00291 unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5. 00292 0 = Main Bias requested to be in Normal-Power Mode by software. 00293 1 = Main Bias request to be in Low-Power Mode by software. */ 00294 unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6. 00295 0 = 8s 00296 1 = 16s */ 00297 unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7. 00298 0 = Strong internal nEN pullup (200kΩ) 00299 1 = Weak internal nEN pullup (10MΩ) */ 00300 } bits; 00301 } reg_cnfg_glbl_t; 00302 00303 /** 00304 * @brief CNFG_GPIO0 Register 00305 * 00306 * Address : 0x11 00307 */ 00308 typedef union { 00309 unsigned char raw; 00310 struct { 00311 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00312 0 = General purpose output (GPO) 00313 1 = General purpose input (GPI) */ 00314 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00315 0 = Input logic low 00316 1 = Input logic high */ 00317 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00318 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00319 0 = Open-Drain 00320 1 = Push-Pull */ 00321 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00322 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00323 0 = GPIO is output is logic low 00324 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00325 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00326 0 = no debounce 00327 1 = 30ms debounce */ 00328 unsigned char alt_gpio0 : 1; /**< Alternate Mode Enable for GPIO0. Bit 5. 00329 0 = Standard GPIO. 00330 1 = Flexible Power Sequencer Active-High Output for SBB2. */ 00331 unsigned char : 1; /**< Bit 6. */ 00332 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00333 Unutilized bit. Write to 0. Reads are don't care. */ 00334 } bits; 00335 } reg_cnfg_gpio0_t; 00336 00337 /** 00338 * @brief CNFG_GPIO1 Register 00339 * 00340 * Address : 0x12 00341 */ 00342 typedef union { 00343 unsigned char raw; 00344 struct { 00345 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00346 0 = General purpose output (GPO) 00347 1 = General purpose input (GPI) */ 00348 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00349 0 = Input logic low 00350 1 = Input logic high */ 00351 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00352 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00353 0 = Open-Drain 00354 1 = Push-Pull */ 00355 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00356 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00357 0 = GPIO is output is logic low 00358 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00359 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00360 0 = no debounce 00361 1 = 30ms debounce */ 00362 unsigned char alt_gpio1 : 1; /**< Alternate Mode Enable for GPIO1. Bit 5. 00363 0 = Standard GPIO. 00364 1 = SBB2 Enable. */ 00365 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00366 Unutilized bit. Write to 0. Reads are don't care. */ 00367 } bits; 00368 } reg_cnfg_gpio1_t; 00369 00370 /** 00371 * @brief CNFG_GPIO2 Register 00372 * 00373 * Address : 0x13 00374 */ 00375 typedef union { 00376 unsigned char raw; 00377 struct { 00378 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00379 0 = General purpose output (GPO) 00380 1 = General purpose input (GPI) */ 00381 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00382 0 = Input logic low 00383 1 = Input logic high */ 00384 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00385 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00386 0 = Open-Drain 00387 1 = Push-Pull */ 00388 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00389 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00390 0 = GPIO is output is logic low 00391 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00392 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00393 0 = no debounce 00394 1 = 30ms debounce */ 00395 unsigned char alt_gpio2 : 1; /**< Alternate Mode Enable for GPIO2. Bit 5. 00396 0 = Standard GPIO. 00397 1 = Bias LPM mode enable. */ 00398 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00399 Unutilized bit. Write to 0. Reads are don't care. */ 00400 } bits; 00401 } reg_cnfg_gpio2_t; 00402 00403 /** 00404 * @brief CID Register 00405 * 00406 * Address : 0x14 00407 */ 00408 typedef union { 00409 unsigned char raw; 00410 struct { 00411 unsigned char cid_3_0 : 4; /**< Bits 0 to 3 of the Chip Identification Code. Bit 3:0. 00412 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ 00413 unsigned char : 3; /**< Bit 6:4. */ 00414 unsigned char cid_7 : 1; /**< Bit 4 of the Chip Identification Code. Bit 7. 00415 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ 00416 } bits; 00417 } reg_cid_t; 00418 00419 /** 00420 * @brief CNFG_WDT Register 00421 * 00422 * Address : 0x17 00423 */ 00424 typedef union { 00425 unsigned char raw; 00426 struct { 00427 unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. 00428 0 = Watchdog timer can be enabled and disabled with WDT_EN. 00429 1 = Watchdog timer can not be disabled with WDT_EN. 00430 However, WDT_EN can still be used to enable the watchdog timer. */ 00431 unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1. 00432 0 = Watchdog timer is not enabled. 00433 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */ 00434 unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2. 00435 0 = Watchdog timer period is not reset. 00436 1 = Watchdog timer is reset back to tWD. */ 00437 unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3. 00438 0 = Watchdog timer expire causes power-off. 00439 1 = Watchdog timer expire causes power-reset. */ 00440 unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4. 00441 0b00 = 16 seconds 0b01 = 32 seconds 00442 0b10 = 64 seconds 0b11 = 128 seconds. */ 00443 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00444 Unutilized bit. Write to 0. Reads are don't care. */ 00445 } bits; 00446 } reg_cnfg_wdt_t; 00447 00448 /** 00449 * @brief INT_CHG Register 00450 * 00451 * Address : 0x01 00452 */ 00453 typedef union { 00454 unsigned char raw; 00455 struct { 00456 unsigned char thm_i : 1; /**< Thermistor related interrupt. Bit 0. 00457 0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read 00458 1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read */ 00459 unsigned char chg_i : 1; /**< Charger related interrupt. Bit 1. 00460 0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read 00461 1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read */ 00462 unsigned char chgin_i : 1; /**< CHGIN related interrupt. Bit 2. 00463 0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read 00464 1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read */ 00465 unsigned char tj_reg_i : 1; /**< Die junction temperature regulation interrupt. Bit 3. 00466 0 = The die temperature has not exceeded TJ-REG since the last time this bit was read 00467 1 = The die temperature has exceeded TJ-REG since the last time this bit was read */ 00468 unsigned char chgin_ctrl_i : 1; /**< CHGIN control-loop related interrupt. Bit 4. 00469 0 = Neither the VCHGIN_MIN_STAT nor the ICHGIN_LIM_STAT bits have changed since the last time this bit was read 00470 1 = The VCHGIN_MIN_STAT or ICHGIN_LIM_STAT bits have changed since the last time this bit was read */ 00471 unsigned char sys_ctrl_i : 1; /**< Minimum System Voltage Regulation-loop related interrupt. Bit 5. 00472 0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read 00473 1 = The minimum system voltage regulation loop has engaged since the last time this bit was read */ 00474 unsigned char sys_cnfg_i : 1; /**< System voltage configuration error interrupt. Bit 6. 00475 0 = The bit combination in CHG_CV has not been forced to change since the last time this bit was read 00476 1 = The bit combination in CHG_CV has been forced to change to ensure VSYS-REG = VFAST-CHG + 200mV 00477 since the last time this bit was read */ 00478 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00479 Unutilized bit. Write to 0. Reads are don't care. */ 00480 } bits; 00481 } reg_int_chg_t; 00482 00483 /** 00484 * @brief STAT_CHG_A 00485 * 00486 * Address : 0x02 00487 */ 00488 typedef union { 00489 unsigned char raw; 00490 struct 00491 { 00492 unsigned char thm_dtls : 3; /**< Battery Temperature Details. Bit 2:0. 00493 0b000 = Thermistor is disabled (THM_EN = 0) 00494 0b001 = Battery is cold as programmed by THM_COLD[1:0] If thermistor and charger are enabled while the battery is cold, a battery temperature fault will occur. 00495 0b010 = Battery is cool as programmed by THM_COOL[1:0] 00496 0b011 = Battery is warm as programmed by THM_WARM[1:0] 00497 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault will occur. 00498 0b101 = Battery is in the normal temperature region 00499 0b110 - 0b111 = reserved */ 00500 unsigned char tj_reg_stat : 1; /**< Maximum Junction Temperature Regulation Loop Status. Bit 3. 00501 0 = The maximum junction temperature regulation loop is not engaged 00502 1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG */ 00503 unsigned char vsys_min_stat : 1; /**< Minimum System Voltage Regulation Loop Status. Bit 4. 00504 0 = The minimum system voltage regulation loop is not enganged 00505 1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN */ 00506 unsigned char ichgin_lim_stat : 1; /**< Input Current Limit Loop Status. Bit 5. 00507 0 = The CHGIN current limit loop is not engaged 00508 1 = The CHGIN current limit loop has engaged to regulate ICHGIN ≤ ICHGIN-LIM */ 00509 unsigned char vchgin_min_stat : 1; /**< Minimum Input Voltage Regulation Loop Status. Bit 6. 00510 0 = The minimum CHGIN voltage regulation loop is not engaged 00511 1 = The minimum CHGIN voltage regulation loop has engaged to regulate VCHGIN ≥ VCHGIN-MIN */ 00512 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00513 Unutilized bit. Write to 0. Reads are don't care. */ 00514 } bits; 00515 } reg_stat_chg_a_t; 00516 00517 /** 00518 * @brief STAT_CHG_B 00519 * 00520 * Address : 0x03 00521 */ 00522 typedef union { 00523 unsigned char raw; 00524 struct 00525 { 00526 unsigned char time_sus : 1; /**< Time Suspend Indicator. Bit 0. 00527 0 = The charger's timers are either not active, or not suspended 00528 1 = The charger's active timer is suspended due to one of three reasons: 00529 charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode, 00530 the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. */ 00531 unsigned char chg : 1; /**< Quick Charger Status. Bit 1. 00532 0 = Charging is not happening 00533 1 = Charging is happening */ 00534 unsigned char chgin_dtls : 2; /**< CHGIN Status Detail. Bit 3:2. 00535 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO) 00536 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP) 00537 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce) 00538 0b11 = The CHGIN input is okay and debounced */ 00539 unsigned char chg_dtls : 4; /**< Charger Details. Bit 7:4. 00540 0b0000 = Off 00541 0b0001 = Prequalification mode 00542 0b0010 = Fast-charge constant-current (CC) mode 00543 0b0011 = JEITA modified fast-charge constant-current mode 00544 0b0100 = Fast-charge constant-voltage (CV) mode 00545 0b0101 = JEITA modified fast-charge constant-voltage mode 00546 0b0110 = Top-off mode 00547 0b0111 = JEITA modified top-off mode 00548 0b1000 = Done 00549 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states) 00550 0b1010 = Prequalification timer fault 00551 0b1011 = Fast-charge timer fault 00552 0b1100 = Battery temperature fault 00553 0b1101 - 0b1111 = reserved */ 00554 } bits; 00555 } reg_stat_chg_b_t; 00556 00557 /** 00558 * @brief INT_M_CHG Register 00559 * 00560 * Address : 0x07 00561 */ 00562 typedef union { 00563 unsigned char raw; 00564 struct { 00565 unsigned char thm_m : 1; /**< Setting this bit prevents the THM_I bit from causing hardware IRQs. Bit 0. 00566 0 = THM_I is not masked 00567 1 = THM_I is masked */ 00568 unsigned char chg_m : 1; /**< Setting this bit prevents the CHG_I bit from causing hardware IRQs. Bit 1. 00569 0 = CHG_I is not masked 00570 1 = CHG_I is masked */ 00571 unsigned char chgin_m : 1; /**< Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. Bit 2. 00572 0 = CHGIN_I is not masked 00573 1 = CHGIN_I is masked */ 00574 unsigned char tj_reg_m : 1; /**< Setting this bit prevents the TJREG_I bit from causing hardware IRQs. Bit 3. 00575 0 = TJREG_I is not masked 00576 1 = TJREG_I is masked */ 00577 unsigned char chgin_ctrl_m : 1; /**< Setting this bit prevents the CHGIN_CTRL_I bit from causing hardware IRQs. Bit 4. 00578 0 = CHGIN_CTRL_I is not masked 00579 1 = CHGIN_CTRL_I is masked */ 00580 unsigned char sys_ctrl_m : 1; /**< Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. Bit 5. 00581 0 = SYS_CTRL_I is not masked 00582 1 = SYS_CTRL_I is masked */ 00583 unsigned char sys_cnfg_m : 1; /**< Setting this bit prevents the SYS_CNFG_I bit from causing hardware IRQs. Bit 6. 00584 0 = SYS_CNFG_I is not masked 00585 1 = SYS_CNFG_I is masked 00586 since the last time this bit was read */ 00587 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00588 Unutilized bit. Write to 0. Reads are don't care. */ 00589 } bits; 00590 } reg_int_m_chg_t; 00591 00592 /** 00593 * @brief CNFG_CHG_A 00594 * 00595 * Address : 0x20 00596 */ 00597 typedef union { 00598 unsigned char raw; 00599 struct 00600 { 00601 unsigned char thm_cold : 2; /**< Sets the VCOLD JEITA Temperature Threshold. Bit 1:0. 00602 0b00 = VCOLD = 1.024V (-10ºC for β = 3380K) 00603 0b01 = VCOLD = 0.976V (-5ºC for β = 3380K) 00604 0b10 = VCOLD = 0.923V (0ºC for β = 3380K) 00605 0b11 = VCOLD = 0.867V (5ºC for β = 3380K) */ 00606 unsigned char thm_cool : 2; /**< Sets the VCOOL JEITA Temperature Threshold. Bit 3:2. 00607 0b00 = VCOOL = 0.923V (0ºC for β = 3380K) 00608 0b01 = VCOOL = 0.867V (5ºC for β = 3380K) 00609 0b10 = VCOOL = 0.807V (10ºC for β = 3380K) 00610 0b11 = VCOOL = 0.747V (15ºC for β = 3380K) */ 00611 unsigned char thm_warm : 2; /**< Sets the VWARM JEITA Temperature Threshold. Bit 5:4. 00612 0b00 = VWARM = 0.511V (35ºC for β = 3380K) 00613 0b01 = VWARM = 0.459V (40ºC for β = 3380K) 00614 0b10 = VWARM = 0.411V (45ºC for β = 3380K) 00615 0b11 = VWARM = 0.367V (50ºC for β = 3380K) */ 00616 unsigned char thm_hot : 2; /**< Sets the VHOT JEITA Temperature Threshold. Bit 7:6. 00617 0b00 = VHOT = 0.411V (45ºC for β = 3380K) 00618 0b01 = VHOT = 0.367V (50ºC for β = 3380K) 00619 0b10 = VHOT = 0.327V (55ºC for β = 3380K) 00620 0b11 = VHOT = 0.291V (60ºC for β = 3380K) */ 00621 } bits; 00622 } reg_cnfg_chg_a_t; 00623 00624 /** 00625 * @brief CNFG_CHG_B 00626 * 00627 * Address : 0x21 00628 */ 00629 typedef union { 00630 unsigned char raw; 00631 struct 00632 { 00633 unsigned char chg_en : 1; /**< Charger Enable. Bit 0. 00634 0 = the battery charger is disabled 00635 1 = the battery charger is enabled */ 00636 unsigned char i_pq : 1; /**< Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. Bit 1. 00637 0 = 10% 1 = 20% */ 00638 unsigned char ichgin_lim : 3; /**< CHGIN Input Current Limit (ICHGIN-LIM). Bit 4:2. 00639 0b000 = 95mA 0b001 = 190mA 00640 0b010 = 285mA 0b011 = 380mA 00641 0b100 = 475mA 0b101 0b111 = Reserved. */ 00642 unsigned char vchgin_min : 3; /**< Minimum CHGIN regulation voltage (VCHGIN-MIN). Bit 7:5. 00643 0b000 = 4.0V 0b001 = 4.1V 00644 0b010 = 4.2V 0b011 = 4.3V 00645 0b100 = 4.4V 0b101 = 4.5V 00646 0b110 = 4.6V 0b111 = 4.7V */ 00647 } bits; 00648 } reg_cnfg_chg_b_t; 00649 00650 /** 00651 * @brief CNFG_CHG_C 00652 * 00653 * Address : 0x22 00654 */ 00655 typedef union { 00656 unsigned char raw; 00657 struct 00658 { 00659 unsigned char t_topoff : 3; /**< Top-off timer value (tTO). Bit 2:0. 00660 0b000 = 0 minutes 0b001 = 5 minutes 00661 0b010 = 10 minutes 0b011 = 15 minutes 00662 0b100 = 20 minutes 0b101 = 25 minutes 00663 0b110 = 30 minutes 0b111 = 35 minutes */ 00664 unsigned char i_term : 2; /**< Charger Termination Current (ITERM). Bit 4:3. 00665 00 = 5% 01 = 7.5% 00666 10 = 10% 11 = 15% */ 00667 unsigned char chg_pq : 3; /**< Battery prequalification voltage threshold (VPQ). Bit 7:5. 00668 0b000 = 2.3V 0b001 = 2.4V 00669 0b010 = 2.5V 0b011 = 2.6V 00670 0b100 = 2.7V 0b101 = 2.8V 00671 0b110 = 2.9V 0b111 = 3.0V */ 00672 } bits; 00673 } reg_cnfg_chg_c_t; 00674 00675 /** 00676 * @brief CNFG_CHG_D 00677 * 00678 * Address : 0x23 00679 */ 00680 typedef union { 00681 unsigned char raw; 00682 struct 00683 { 00684 unsigned char vsys_reg : 5; /**< System voltage regulation (VSYS-REG). Bit 4:0. 00685 0x0 = 4.100V 0x1 = 4.125V 00686 0x2 = 4.150V ... 00687 0x1B = 4.775V 0x1C - 0x1F = 4.800V */ 00688 unsigned char tj_reg : 3; /**< Sets the die junction temperature regulation point, TJ-REG. Bit 7:5. 00689 0b000 = 60ºC 0b001 = 70ºC 00690 0b010 = 80ºC 0b011 = 90ºC 00691 0b100 - 0b111 = 100ºC */ 00692 } bits; 00693 } reg_cnfg_chg_d_t; 00694 00695 /** 00696 * @brief CNFG_CHG_E 00697 * 00698 * Address : 0x25 00699 */ 00700 typedef union { 00701 unsigned char raw; 00702 struct 00703 { 00704 unsigned char t_fast_chg : 2; /**< System voltage regulation (VSYS-REG). Bit 1:0. 00705 0b00 = timer disabled 0b01 = 3 hours 00706 0b10 = 5 hours 0b11 = 7 hours */ 00707 unsigned char chg_cc : 6; /**< Sets the fast-charge constant current value, IFAST-CHG. Bit 7:2. 00708 0x0 = 7.5mA 0x1 = 15.0mA 00709 0x2 = 22.5mA ... 00710 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ 00711 } bits; 00712 } reg_cnfg_chg_e_t; 00713 00714 /** 00715 * @brief CNFG_CHG_F 00716 * 00717 * Address : 0x25 00718 */ 00719 typedef union { 00720 unsigned char raw; 00721 struct 00722 { 00723 unsigned char : 1; /**< Bit 0*/ 00724 unsigned char thm_en : 1; /**< Thermistor enable bit. Bit 1. 00725 0 = Thermistor is disabled 00726 1 = Thermistor is enabled */ 00727 unsigned char chg_cc_jeita : 6; /**< Sets IFAST-CHG-JEITA for when the battery is either cool or warm as defined 00728 by the VCOOL and VWARM temperature thresholds. Bit 7:2. 00729 0x0 = 7.5mA 0x1 = 15.0mA 00730 0x2 = 22.5mA ... 00731 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ 00732 } bits; 00733 } reg_cnfg_chg_f_t; 00734 00735 /** 00736 * @brief CNFG_CHG_G 00737 * 00738 * Address : 0x26 00739 */ 00740 typedef union { 00741 unsigned char raw; 00742 struct 00743 { 00744 unsigned char rsvd : 1; /**< Reserved. Bit 0. 00745 Unutilized bit. Write to 0. Reads are don't care.*/ 00746 unsigned char usbs : 1; /**< Setting this bit places CHGIN in USB suspend mode. Bit 1. 00747 0 = CHGIN is not suspended and may draw current from an adapter source 00748 1 = CHGIN is suspended and may draw no current from an adapter source */ 00749 unsigned char chg_cv : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. 00750 0x0 = 3.600V 0x1 = 3.625V 00751 0x2 = 3.650V ... 00752 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ 00753 } bits; 00754 } reg_cnfg_chg_g_t; 00755 00756 /** 00757 * @brief CNFG_CHG_H 00758 * 00759 * Address : 0x27 00760 */ 00761 typedef union { 00762 unsigned char raw; 00763 struct 00764 { 00765 unsigned char rsvd : 2; /**< Reserved. Bit 1:0. 00766 Unutilized bit. Write to 0. Reads are don't care.*/ 00767 unsigned char chg_cv_jeita : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. 00768 0x0 = 3.600V 0x1 = 3.625V 00769 0x2 = 3.650V ... 00770 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ 00771 } bits; 00772 } reg_cnfg_chg_h_t; 00773 00774 /** 00775 * @brief CNFG_CHG_I 00776 * 00777 * Address : 0x28 00778 */ 00779 typedef union { 00780 unsigned char raw; 00781 struct 00782 { 00783 unsigned char mux_sel : 4; /**< Selects the analog channel to connect to AMUX. Bit 3:0. 00784 0b0000 = Multiplexer is disabled and AMUX is high-impedance. 00785 0b0001 = CHGIN voltage monitor. 00786 0b0010 = CHGIN current monitor. 00787 0b0011 = BATT voltage monitor. 00788 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1). 00789 0b0101 = BATT discharge current monitor normal measurement. 00790 0b0110 = BATT discharge current monitor nulling measurement. 00791 0b0111 = THM voltage monitor 0b1000 = TBIAS voltage monitor 00792 0b1001 = AGND voltage monitor (through 100Ω pull-down resistor) 00793 0b1010 - 0b1111 = SYS voltage monitor */ 00794 unsigned char imon_dischg_scale : 4; /**< Selects the battery discharge current full-scale current value. Bit 7:4. 00795 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA 00796 0x3 = 103.4mA 0x4 = 134.1mA 00797 0x5 = 164.1mA 0x6 = 193.7mA 00798 0x7 = 222.7mA 0x8 = 251.2mA 00799 0x9 = 279.3mA 0xA - 0xF = 300.0mA */ 00800 } bits; 00801 } reg_cnfg_chg_i_t; 00802 00803 /** 00804 * @brief CNFG_SBB0_A 00805 * 00806 * Address : 0x29 00807 */ 00808 typedef union { 00809 unsigned char raw; 00810 struct 00811 { 00812 unsigned char tv_sbb0 : 7; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 6:0. 00813 0x00 = 0.800V 0x01 = 0.850V 00814 0x02 = 0.900V 0x03 = 0.950V 00815 0x04 = 1.000V 0x05 = 1.050V 00816 0x06 = 1.100V ... 00817 0x5C = 5.400V 0x5D = 5.450V 00818 0x5E - 0x7F = 5.500V */ 00819 unsigned char : 1; /**< Bit 7. */ 00820 } bits; 00821 } reg_cnfg_sbb0_a_t; 00822 00823 /** 00824 * @brief CNFG_SBB0_B 00825 * 00826 * Address : 0x2A 00827 */ 00828 typedef union { 00829 unsigned char raw; 00830 struct 00831 { 00832 unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0, 00833 selecting either an FPS slot the channel powers-up and powers-down in 00834 or whether the channel is forced on or off. Bit 2:0. 00835 0b000 = FPS slot 0 0b001 = FPS slot 1 00836 0b010 = FPS slot 2 0b011 = FPS slot 3 00837 0b100 = Off irrespective of FPS 00838 0b101 = same as 0b100 0b110 = On irrespective of FPS 00839 0b111 = same as 0b110 */ 00840 unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3. 00841 0 = The active discharge function is disabled. 00842 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00843 1 = The active discharge function is enabled. 00844 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00845 unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 5:4 00846 0b00 = 1.000A 0b01 = 0.750A 00847 0b10 = 0.500A 0b11 = 0.333A*/ 00848 unsigned char op_mode : 1; /**< Operation mode of SBB0. Bit 6. 00849 0 = Buck-Boost Mode 00850 1 = Buck Mode*/ 00851 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00852 Unutilized bit. Write to 0. Reads are don't care.*/ 00853 } bits; 00854 } reg_cnfg_sbb0_b_t; 00855 00856 /** 00857 * @brief CNFG_SBB1_A 00858 * 00859 * Address : 0x2B 00860 */ 00861 typedef union { 00862 unsigned char raw; 00863 struct 00864 { 00865 unsigned char tv_sbb1 : 7; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 6:0. 00866 0x00 = 0.800V 0x01 = 0.850V 00867 0x02 = 0.900V 0x03 = 0.950V 00868 0x04 = 1.000V 0x05 = 1.050V 00869 0x06 = 1.100V ... 00870 0x5C = 5.400V 0x5D = 5.450V 00871 0x5E - 0x7F = 5.500V */ 00872 unsigned char : 1; /**< Bit 7. */ 00873 } bits; 00874 } reg_cnfg_sbb1_a_t; 00875 00876 /** 00877 * @brief CNFG_SBB1_B 00878 * 00879 * Address : 0x2C 00880 */ 00881 typedef union { 00882 unsigned char raw; 00883 struct 00884 { 00885 unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1, 00886 selecting either an FPS slot the channel powers-up and powers-down in 00887 or whether the channel is forced on or off. Bit 2:0. 00888 0b000 = FPS slot 0 0b001 = FPS slot 1 00889 0b010 = FPS slot 2 0b011 = FPS slot 3 00890 0b100 = Off irrespective of FPS 00891 0b101 = same as 0b100 0b110 = On irrespective of FPS 00892 0b111 = same as 0b110 */ 00893 unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3. 00894 0 = The active discharge function is disabled. 00895 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00896 1 = The active discharge function is enabled. 00897 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00898 unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 5:4. 00899 0b00 = 1.000A 0b01 = 0.750A 00900 0b10 = 0.500A 0b11 = 0.333A*/ 00901 unsigned char op_mode : 1; /**< Operation mode of SBB1. Bit 6. 00902 0 = Buck-Boost Mode 00903 1 = Buck Mode*/ 00904 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00905 Unutilized bit. Write to 0. Reads are don't care.*/ 00906 } bits; 00907 } reg_cnfg_sbb1_b_t; 00908 00909 /** 00910 * @brief CNFG_SBB2_A 00911 * 00912 * Address : 0x2D 00913 */ 00914 typedef union { 00915 unsigned char raw; 00916 struct 00917 { 00918 unsigned char tv_sbb2 : 7; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 6:0. 00919 0x00 = 0.800V 0x01 = 0.850V 00920 0x02 = 0.900V 0x03 = 0.950V 00921 0x04 = 1.000V 0x05 = 1.050V 00922 0x06 = 1.100V ... 00923 0x5C = 5.400V 0x5D = 5.450V 00924 0x5E - 0x7F = 5.500V */ 00925 unsigned char : 1; /**< Bit 7. */ 00926 } bits; 00927 } reg_cnfg_sbb2_a_t; 00928 00929 /** 00930 * @brief CNFG_SBB2_B 00931 * 00932 * Address : 0x2E 00933 */ 00934 typedef union { 00935 unsigned char raw; 00936 struct 00937 { 00938 unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2, 00939 selecting either an FPS slot the channel powers-up and powers-down in 00940 or whether the channel is forced on or off. Bit 2:0. 00941 0b000 = FPS slot 0 0b001 = FPS slot 1 00942 0b010 = FPS slot 2 0b011 = FPS slot 3 00943 0b100 = Off irrespective of FPS 00944 0b101 = same as 0b100 0b110 = On irrespective of FPS 00945 0b111 = same as 0b110 */ 00946 unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3. 00947 0 = The active discharge function is disabled. 00948 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00949 1 = The active discharge function is enabled. 00950 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00951 unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4. 00952 0b00 = 1.000A 0b01 = 0.750A 00953 0b10 = 0.500A 0b11 = 0.333A*/ 00954 unsigned char op_mode : 1; /**< Operation mode of SBB2. Bit 6. 00955 0 = Buck-Boost Mode 00956 1 = Buck Mode*/ 00957 unsigned char rsvd : 1; /**< Reserved. Bit 7. 00958 Unutilized bit. Write to 0. Reads are don't care.*/ 00959 } bits; 00960 } reg_cnfg_sbb2_b_t; 00961 00962 /** 00963 * @brief CNFG_SBB_TOP 00964 * 00965 * Address : 0x2F 00966 */ 00967 typedef union { 00968 unsigned char raw; 00969 struct 00970 { 00971 unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0. 00972 0b00 = fastest transition time 00973 0b01 = a little slower than 0b00 00974 0b10 = a little slower than 0b01 00975 0b11 = a little slower than 0b10 */ 00976 unsigned char : 5; /**< Bit 6:2. */ 00977 unsigned char ichgin_lim_def : 1; /**< Changes how CNFG_CHG_B.ICHGIN_LIM is interpreted. Bit 7. 00978 See CNFG_CHG_B.ICHGIN_LIM for more details.*/ 00979 } bits; 00980 } reg_cnfg_sbb_top_t; 00981 00982 /** 00983 * @brief CNFG_LDO0_A 00984 * 00985 * Address : 0x38 00986 */ 00987 typedef union { 00988 unsigned char raw; 00989 struct 00990 { 00991 unsigned char tv_ldo0 : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function 00992 that starts at 0.8V and ends at 3.975V, with 25mV increments. Bit 6:0. 00993 0x00 = 0.800V 0x01 = 0.825V 00994 0x02 = 0.850V 0x03 = 0.875V 00995 0x04 = 0.900V 0x05 = 0.925V 00996 0x06 = 0.950V ... 00997 0x7D = 3.925V 0x7E = 3.950V 00998 0x7F = 3.975V */ 00999 unsigned char rsvd : 1; /**< Reserved. Bit 7. 01000 Unutilized bit. Write to 0. Reads are don't care. */ 01001 } bits; 01002 } reg_cnfg_ldo0_a_t; 01003 01004 /** 01005 * @brief CNFG_LDO0_B 01006 * 01007 * Address : 0x39 01008 */ 01009 typedef union { 01010 unsigned char raw; 01011 struct 01012 { 01013 unsigned char en_ldo0 : 3; /**< Enable Control for LDO0, selecting either an FPS slot the channel powers-up and 01014 powers-down in or whether the channel is forced on or off. Bit 2:0. 01015 0b000 = FPS slot 0 0b001 = FPS slot 1 01016 0b010 = FPS slot 2 0b011 = FPS slot 3 01017 0b100 = Off irrespective of FPS 01018 0b101 = same as 0b100 01019 0b110 = On irrespective of FPS 01020 0b111 = same as 0b110 */ 01021 unsigned char ade_ldo0 : 1; /**< LDO0 Active-Discharge Enable. Bit 3. 01022 0 = The active discharge function is disabled. 01023 1 = The active discharge function is enabled. */ 01024 unsigned char ldo0_md : 1; /**< Operation mode of LDO0. Bit 4. 01025 0 = Low Dropout Linear Regulator (LDO) Mode 01026 1 = Load Switch (LSW) Mode */ 01027 unsigned char : 3; /**< Bit 7:5. */ 01028 } bits; 01029 } reg_cnfg_ldo0_b_t; 01030 01031 /** 01032 * @brief CNFG_LDO1_A 01033 * 01034 * Address : 0x3A 01035 */ 01036 typedef union { 01037 unsigned char raw; 01038 struct 01039 { 01040 unsigned char tv_ldo1 : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function 01041 that starts at 0.8V and ends at 3.975V, with 25mV increments. Bit 6:0. 01042 0x00 = 0.800V 0x01 = 0.825V 01043 0x02 = 0.850V 0x03 = 0.875V 01044 0x04 = 0.900V 0x05 = 0.925V 01045 0x06 = 0.950V ... 01046 0x7D = 3.925V 0x7E = 3.950V 01047 0x7F = 3.975V */ 01048 unsigned char rsvd : 1; /**< Reserved. Bit 7. 01049 Unutilized bit. Write to 0. Reads are don't care. */ 01050 } bits; 01051 } reg_cnfg_ldo1_a_t; 01052 01053 /** 01054 * @brief CNFG_LDO1_B 01055 * 01056 * Address : 0x3B 01057 */ 01058 typedef union { 01059 unsigned char raw; 01060 struct 01061 { 01062 unsigned char en_ldo1 : 3; /**< Enable Control for LDO1, selecting either an FPS slot the channel powers-up and 01063 powers-down in or whether the channel is forced on or off. Bit 2:0. 01064 0b000 = FPS slot 0 0b001 = FPS slot 1 01065 0b010 = FPS slot 2 0b011 = FPS slot 3 01066 0b100 = Off irrespective of FPS 01067 0b101 = same as 0b100 01068 0b110 = On irrespective of FPS 01069 0b111 = same as 0b110 */ 01070 unsigned char ade_ldo1 : 1; /**< LDO1 Active-Discharge Enable. Bit 3. 01071 0 = The active discharge function is disabled. 01072 1 = The active discharge function is enabled. */ 01073 unsigned char ldo1_md : 1; /**< Operation mode of LDO1. Bit 4. 01074 0 = Low Dropout Linear Regulator (LDO) Mode 01075 1 = Load Switch (LSW) Mode */ 01076 unsigned char : 3; /**< Bit 7:5.*/ 01077 } bits; 01078 } reg_cnfg_ldo1_b_t; 01079 01080 #endif /* MAX77654_REGS_H_ */
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