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00001 /*******************************************************************************
00002 * Copyright (C) 2022 Maxim Integrated Products, Inc., All rights Reserved.
00003 *
00004 * This software is protected by copyright laws of the United States and
00005 * of foreign countries. This material may also be protected by patent laws
00006 * and technology transfer regulations of the United States and of foreign
00007 * countries. This software is furnished under a license agreement and/or a
00008 * nondisclosure agreement and may only be used or reproduced in accordance
00009 * with the terms of those agreements. Dissemination of this information to
00010 * any party or parties not specified in the license agreement and/or
00011 * nondisclosure agreement is expressly prohibited.
00012 *
00013 * The above copyright notice and this permission notice shall be included
00014 * in all copies or substantial portions of the Software.
00015 *
00016 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00017 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00018 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00019 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00020 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00021 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00022 * OTHER DEALINGS IN THE SOFTWARE.
00023 *
00024 * Except as contained in this notice, the name of Maxim Integrated
00025 * Products, Inc. shall not be used except as stated in the Maxim Integrated
00026 * Products, Inc. Branding Policy.
00027 *
00028 * The mere transfer of this software does not imply any licenses
00029 * of trade secrets, proprietary technology, copyrights, patents,
00030 * trademarks, maskwork rights, or any other form of intellectual
00031 * property whatsoever. Maxim Integrated Products, Inc. retains all
00032 * ownership rights.
00033 *******************************************************************************
00034 */
00035 
00036 #include <Thread.h>
00037 #include "MAX77654.h"
00038 using namespace std;
00039 
00040 #define POST_INTR_WORK_SIGNAL_ID            0x1
00041 
00042 MAX77654::MAX77654(I2C *i2c, PinName IRQPin)
00043 {
00044     if (i2c == NULL)
00045         return;
00046 
00047     i2c_handler = i2c;
00048 
00049     interrupt_handler_list = new handler[INT_CHG_END]{};
00050     
00051     if (IRQPin != NC) {
00052         IRQDisableAll();
00053         post_intr_work_thread = new Thread();
00054         post_intr_work_thread->start(Callback<void()>(this, &MAX77654::PostInterruptWork));
00055 
00056         this->irq_pin = new InterruptIn(IRQPin);
00057         this->irq_pin->fall(Callback<void()>(this, &MAX77654::InterruptHandler));
00058         this->irq_pin->enable_irq();
00059     } else {
00060         this->irq_pin = NULL;
00061     }
00062 }
00063 
00064 MAX77654::~MAX77654()
00065 {
00066     if (post_intr_work_thread) {
00067         delete post_intr_work_thread;
00068     }
00069 
00070     if (irq_pin) {
00071         delete irq_pin;
00072     }
00073 
00074     if (interrupt_handler_list) {
00075         delete [] interrupt_handler_list;
00076     }
00077 }
00078 
00079 int MAX77654::read_register(uint8_t reg, uint8_t *value)
00080 {
00081     int rtn_val;
00082 
00083     if (value == NULL) {
00084         return MAX77654_VALUE_NULL;
00085     }
00086 
00087     rtn_val = i2c_handler->write(MAX77654_I2C_ADDRESS, (const char *)&reg, 1, true);
00088     if (rtn_val != 0) {
00089         return MAX77654_WRITE_DATA_FAILED;
00090     }
00091 
00092     rtn_val = i2c_handler->read(MAX77654_I2C_ADDRESS, (char *) value, 1, false);
00093     if (rtn_val < 0) {
00094         return MAX77654_READ_DATA_FAILED;
00095     }
00096 
00097     return MAX77654_NO_ERROR;
00098 }
00099 
00100 int MAX77654::write_register(uint8_t reg, const uint8_t *value)
00101 {
00102     int rtn_val;
00103     uint8_t local_data[2];
00104 
00105     if (value == NULL) {
00106         return MAX77654_VALUE_NULL;
00107     }
00108 
00109     local_data[0] = reg;
00110 
00111     memcpy(&local_data[1], value, 1);
00112 
00113     rtn_val = i2c_handler->write(MAX77654_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
00114     if (rtn_val != MAX77654_NO_ERROR) {
00115         return MAX77654_WRITE_DATA_FAILED;
00116     }
00117 
00118     return MAX77654_NO_ERROR;
00119 }
00120 
00121 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value)                         \
00122             int ret;                                                                    \
00123             ret = read_register(address, (uint8_t *)&(reg_name));                       \
00124             if (ret) {                                                                  \
00125                 return ret;                                                             \
00126             }                                                                           \
00127             bit_field_name = value;                                                     \
00128             ret = write_register(address, (uint8_t *)&(reg_name));                      \
00129             if (ret) {                                                                  \
00130                 return ret;                                                             \
00131             }
00132 
00133 int MAX77654::GetThermalOverload(ercflag_t *ercflag)
00134 {
00135     int ret;
00136     reg_ercflag_t reg_ercflag = {0};
00137 
00138     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00139     if (ret != MAX77654_NO_ERROR) {
00140         return ret;
00141     }
00142 
00143     *ercflag = (ercflag_t)reg_ercflag.bits.tovld;
00144 
00145     return MAX77654_NO_ERROR;
00146 }
00147 
00148 int MAX77654::GetSysOvervoltageLockout(ercflag_t *ercflag)
00149 {
00150     int ret;
00151     reg_ercflag_t reg_ercflag = {0};
00152 
00153     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00154     if (ret != MAX77654_NO_ERROR) {
00155         return ret;
00156     }
00157 
00158     *ercflag = (ercflag_t)reg_ercflag.bits.sysovlo;
00159 
00160     return MAX77654_NO_ERROR;
00161 }
00162 
00163 int MAX77654::GetSysUndervoltageLockout(ercflag_t *ercflag)
00164 {
00165     int ret;
00166     reg_ercflag_t reg_ercflag = {0};
00167 
00168     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00169     if (ret != MAX77654_NO_ERROR) {
00170         return ret;
00171     }
00172 
00173     *ercflag = (ercflag_t)reg_ercflag.bits.sysuvlo;
00174 
00175     return MAX77654_NO_ERROR;
00176 }
00177 
00178 int MAX77654::GetManualResetTimer(ercflag_t *ercflag)
00179 {
00180     int ret;
00181     reg_ercflag_t reg_ercflag = {0};
00182 
00183     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00184     if (ret != MAX77654_NO_ERROR) {
00185         return ret;
00186     }
00187 
00188     *ercflag = (ercflag_t)reg_ercflag.bits.mrst;
00189 
00190     return MAX77654_NO_ERROR;
00191 }
00192 
00193 int MAX77654::GetSoftwareOffFlag(ercflag_t *ercflag)
00194 {
00195     int ret;
00196     reg_ercflag_t reg_ercflag = {0};
00197 
00198     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00199     if (ret != MAX77654_NO_ERROR) {
00200         return ret;
00201     }
00202 
00203     *ercflag = (ercflag_t)reg_ercflag.bits.sft_off_f;
00204 
00205     return MAX77654_NO_ERROR;
00206 }
00207 
00208 int MAX77654::GetSoftwareColdResetFlag(ercflag_t *ercflag)
00209 {
00210     int ret;
00211     reg_ercflag_t reg_ercflag = {0};
00212 
00213     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00214     if (ret != MAX77654_NO_ERROR) {
00215         return ret;
00216     }
00217 
00218     *ercflag = (ercflag_t)reg_ercflag.bits.sft_crst_f;
00219 
00220     return MAX77654_NO_ERROR;
00221 }
00222 
00223 int MAX77654::GetWatchdogTimerOffFlag(ercflag_t *ercflag)
00224 {
00225     int ret;
00226     reg_ercflag_t reg_ercflag = {0};
00227 
00228     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00229     if (ret != MAX77654_NO_ERROR) {
00230         return ret;
00231     }
00232 
00233     *ercflag = (ercflag_t)reg_ercflag.bits.wdt_off;
00234 
00235     return MAX77654_NO_ERROR;
00236 }
00237 
00238 int MAX77654::GetWatchdogTimerResetFlag(ercflag_t *ercflag)
00239 {
00240     int ret;
00241     reg_ercflag_t reg_ercflag = {0};
00242 
00243     ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
00244     if (ret != MAX77654_NO_ERROR) {
00245         return ret;
00246     }
00247 
00248     *ercflag = (ercflag_t)reg_ercflag.bits.wdt_rst;
00249 
00250     return MAX77654_NO_ERROR;
00251 }
00252 
00253 int MAX77654::GetDeviceIdentification(didm_t *didm)
00254 {
00255     int ret;
00256     reg_stat_glbl_t reg_stat_glbl = {0};
00257 
00258     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00259     if (ret != MAX77654_NO_ERROR) {
00260         return ret;
00261     }
00262 
00263     *didm = (didm_t)reg_stat_glbl.bits.didm;
00264 
00265     return MAX77654_NO_ERROR;
00266 }
00267 
00268 int MAX77654::GetBOKInterruptStatus(bok_t* bok)
00269 {
00270     int ret;
00271     reg_stat_glbl_t reg_stat_glbl = {0};
00272 
00273     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00274     if (ret != MAX77654_NO_ERROR) {
00275         return ret;
00276     }
00277 
00278     *bok = (bok_t)reg_stat_glbl.bits.bok;
00279 
00280     return MAX77654_NO_ERROR;
00281 }
00282 
00283 int MAX77654::GetLDO0DropoutRisingStatus(dod0_s_t* dod0_s)
00284 {
00285     int ret;
00286     reg_stat_glbl_t reg_stat_glbl = {0};
00287 
00288     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00289     if (ret != MAX77654_NO_ERROR) {
00290         return ret;
00291     }
00292 
00293     *dod0_s = (dod0_s_t)reg_stat_glbl.bits.dod0_s;
00294 
00295     return MAX77654_NO_ERROR;
00296 }
00297 
00298 int MAX77654::GetLDO1DropoutRisingStatus(dod1_s_t* dod1_s)
00299 {
00300     int ret;
00301     reg_stat_glbl_t reg_stat_glbl = {0};
00302 
00303     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00304     if (ret != MAX77654_NO_ERROR) {
00305         return ret;
00306     }
00307 
00308     *dod1_s = (dod1_s_t)reg_stat_glbl.bits.dod1_s;
00309 
00310     return MAX77654_NO_ERROR;
00311 }
00312 
00313 int MAX77654::GetThermalAlarm2Status(tjal2_s_t* tjal2_s)
00314 {
00315     int ret;
00316     reg_stat_glbl_t reg_stat_glbl = {0};
00317 
00318     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00319     if (ret != MAX77654_NO_ERROR) {
00320         return ret;
00321     }
00322 
00323     *tjal2_s = (tjal2_s_t)reg_stat_glbl.bits.tjal2_s;
00324 
00325     return MAX77654_NO_ERROR;
00326 }
00327 
00328 int MAX77654::GetThermalAlarm1Status(tjal1_s_t* tjal1_s)
00329 {
00330     int ret;
00331     reg_stat_glbl_t reg_stat_glbl = {0};
00332 
00333     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00334     if (ret != MAX77654_NO_ERROR) {
00335         return ret;
00336     }
00337 
00338     *tjal1_s = (tjal1_s_t)reg_stat_glbl.bits.tjal1_s;
00339 
00340     return MAX77654_NO_ERROR;
00341 }
00342 
00343 int MAX77654::GetnENDebouncedStatus(stat_en_t* stat_en)
00344 {
00345     int ret;
00346     reg_stat_glbl_t reg_stat_glbl = {0};
00347 
00348     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00349     if (ret != MAX77654_NO_ERROR) {
00350         return ret;
00351     }
00352 
00353     *stat_en = (stat_en_t)reg_stat_glbl.bits.stat_en;
00354 
00355     return MAX77654_NO_ERROR;
00356 }
00357 
00358 int MAX77654::GetSoftwareVersionGateDrive(stat_irq_t* stat_irq)
00359 {
00360     int ret;
00361     reg_stat_glbl_t reg_stat_glbl = {0};
00362 
00363     ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
00364     if (ret != MAX77654_NO_ERROR) {
00365         return ret;
00366     }
00367 
00368     *stat_irq = (stat_irq_t)reg_stat_glbl.bits.stat_irq;
00369 
00370     return MAX77654_NO_ERROR;
00371 }
00372 
00373 int MAX77654::SetLDO1FaultInterruptMask(intm_t intm)
00374 {
00375     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00376 
00377     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.ldo1_m, intm);
00378 
00379     return MAX77654_NO_ERROR;
00380 }
00381 
00382 int MAX77654::GetLDO1FaultInterruptMask(intm_t* intm)
00383 {
00384     int ret;
00385     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00386 
00387     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00388     if (ret != MAX77654_NO_ERROR) {
00389         return ret;
00390     }
00391 
00392     *intm = (intm_t)reg_intm_glbl1.bits.ldo1_m;
00393 
00394     return MAX77654_NO_ERROR;
00395 }
00396 
00397 int MAX77654::SetLDO0FaultInterruptMask(intm_t intm)
00398 {
00399     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00400 
00401     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.ldo0_m, intm);
00402 
00403     return MAX77654_NO_ERROR;
00404 }
00405 
00406 int MAX77654::GetLDO0FaultInterruptMask(intm_t* intm)
00407 {
00408     int ret;
00409     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00410 
00411     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00412     if (ret != MAX77654_NO_ERROR) {
00413         return ret;
00414     }
00415 
00416     *intm = (intm_t)reg_intm_glbl1.bits.ldo0_m;
00417 
00418     return MAX77654_NO_ERROR;
00419 }
00420 
00421 int MAX77654::SetSBBTimeoutMask(intm_t intm)
00422 {
00423     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00424 
00425     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.sbb_to_m, intm);
00426 
00427     return MAX77654_NO_ERROR;
00428 }
00429 
00430 int MAX77654::GetSBBTimeoutMask(intm_t* intm)
00431 {
00432     int ret;
00433     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00434 
00435     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00436     if (ret != MAX77654_NO_ERROR) {
00437         return ret;
00438     }
00439 
00440     *intm = (intm_t)reg_intm_glbl1.bits.sbb_to_m;
00441 
00442     return MAX77654_NO_ERROR;
00443 }
00444 
00445 int MAX77654::SetGPI2RisingInterruptMask(intm_t intm)
00446 {
00447     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00448 
00449     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.gpi2_rm, intm);
00450 
00451     return MAX77654_NO_ERROR;
00452 }
00453 
00454 int MAX77654::GetGPI2RisingInterruptMask(intm_t* intm)
00455 {
00456     int ret;
00457     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00458 
00459     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00460     if (ret != MAX77654_NO_ERROR) {
00461         return ret;
00462     }
00463 
00464     *intm = (intm_t)reg_intm_glbl1.bits.gpi2_rm;
00465 
00466     return MAX77654_NO_ERROR;
00467 }
00468 
00469 int MAX77654::SetGPI2FallingInterruptMask(intm_t intm)
00470 {
00471     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00472 
00473     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.gpi2_fm, intm);
00474 
00475     return MAX77654_NO_ERROR;
00476 }
00477 
00478 int MAX77654::GetGPI2FallingInterruptMask(intm_t* intm)
00479 {
00480     int ret;
00481     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00482 
00483     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00484     if (ret != MAX77654_NO_ERROR) {
00485         return ret;
00486     }
00487 
00488     *intm = (intm_t)reg_intm_glbl1.bits.gpi2_fm;
00489 
00490     return MAX77654_NO_ERROR;
00491 }
00492 
00493 int MAX77654::SetGPI1RisingInterruptMask(intm_t intm)
00494 {
00495     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00496 
00497     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.gpi1_rm, intm);
00498 
00499     return MAX77654_NO_ERROR;
00500 }
00501 
00502 int MAX77654::GetGPI1RisingInterruptMask(intm_t* intm)
00503 {
00504     int ret;
00505     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00506 
00507     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00508     if (ret != MAX77654_NO_ERROR) {
00509         return ret;
00510     }
00511 
00512     *intm = (intm_t)reg_intm_glbl1.bits.gpi1_rm;
00513 
00514     return MAX77654_NO_ERROR;
00515 }
00516 
00517 int MAX77654::SetGPI1FallingInterruptMask(intm_t intm)
00518 {
00519     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00520 
00521     SET_BIT_FIELD(INTM_GLBL1, reg_intm_glbl1, reg_intm_glbl1.bits.gpi1_fm, intm);
00522 
00523     return MAX77654_NO_ERROR;
00524 }
00525 
00526 int MAX77654::GetGPI1FallingInterruptMask(intm_t* intm)
00527 {
00528     int ret;
00529     reg_intm_glbl1_t reg_intm_glbl1 = {0};
00530 
00531     ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
00532     if (ret != MAX77654_NO_ERROR) {
00533         return ret;
00534     }
00535 
00536     *intm = (intm_t)reg_intm_glbl1.bits.gpi1_fm;
00537 
00538     return MAX77654_NO_ERROR;
00539 }
00540 
00541 int MAX77654::SetDropout0RisingInterruptMask(intm_t intm)
00542 {
00543     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00544 
00545     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.dod0_rm, intm);
00546 
00547     return MAX77654_NO_ERROR;
00548 }
00549 
00550 int MAX77654::GetDropout0RisingInterruptMask(intm_t* intm)
00551 {
00552     int ret;
00553     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00554 
00555     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00556     if (ret != MAX77654_NO_ERROR) {
00557         return ret;
00558     }
00559 
00560     *intm = (intm_t)reg_intm_glbl0.bits.dod0_rm;
00561 
00562     return MAX77654_NO_ERROR;
00563 }
00564 
00565 int MAX77654::SetDropout1RisingInterruptMask(intm_t intm)
00566 {
00567     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00568 
00569     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.dod1_rm, intm);
00570 
00571     return MAX77654_NO_ERROR;
00572 }
00573 
00574 int MAX77654::GetDropout1RisingInterruptMask(intm_t* intm)
00575 {
00576     int ret;
00577     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00578 
00579     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00580     if (ret != MAX77654_NO_ERROR) {
00581         return ret;
00582     }
00583 
00584     *intm = (intm_t)reg_intm_glbl0.bits.dod1_rm;
00585 
00586     return MAX77654_NO_ERROR;
00587 }
00588 
00589 int MAX77654::SetThermalAlarm2RisingInterruptMask(intm_t intm)
00590 {
00591     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00592 
00593     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.tjal2_rm, intm);
00594 
00595     return MAX77654_NO_ERROR;
00596 }
00597 
00598 int MAX77654::GetThermalAlarm2RisingInterruptMask(intm_t* intm)
00599 {
00600     int ret;
00601     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00602 
00603     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00604     if (ret != MAX77654_NO_ERROR) {
00605         return ret;
00606     }
00607 
00608     *intm = (intm_t)reg_intm_glbl0.bits.tjal2_rm;
00609 
00610     return MAX77654_NO_ERROR;
00611 }
00612 
00613 int MAX77654::SetThermalAlarm1RisingInterruptMask(intm_t intm)
00614 {
00615     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00616 
00617     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.tjal1_rm, intm);
00618 
00619     return MAX77654_NO_ERROR;
00620 }
00621 
00622 int MAX77654::GetThermalAlarm1RisingInterruptMask(intm_t* intm)
00623 {
00624     int ret;
00625     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00626 
00627     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00628     if (ret != MAX77654_NO_ERROR) {
00629         return ret;
00630     }
00631 
00632     *intm = (intm_t)reg_intm_glbl0.bits.tjal1_rm;
00633 
00634     return MAX77654_NO_ERROR;
00635 }
00636 
00637 int MAX77654::SetnENRisingInterruptMask(intm_t intm)
00638 {
00639     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00640 
00641     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.nen_rm, intm);
00642 
00643     return MAX77654_NO_ERROR;
00644 }
00645 
00646 int MAX77654::GetnENRisingInterruptMask(intm_t* intm)
00647 {
00648     int ret;
00649     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00650 
00651     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00652     if (ret != MAX77654_NO_ERROR) {
00653         return ret;
00654     }
00655 
00656     *intm = (intm_t)reg_intm_glbl0.bits.nen_rm;
00657 
00658     return MAX77654_NO_ERROR;
00659 }
00660 
00661 int MAX77654::SetnENFallingInterruptMask(intm_t intm)
00662 {
00663     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00664 
00665     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.nen_fm, intm);
00666 
00667     return MAX77654_NO_ERROR;
00668 }
00669 
00670 int MAX77654::GetnENFallingInterruptMask(intm_t* intm)
00671 {
00672     int ret;
00673     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00674 
00675     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00676     if (ret != MAX77654_NO_ERROR) {
00677         return ret;
00678     }
00679 
00680     *intm = (intm_t)reg_intm_glbl0.bits.nen_fm;
00681 
00682     return MAX77654_NO_ERROR;
00683 }
00684 
00685 int MAX77654::SetGPI0RisingInterruptMask(intm_t intm)
00686 {
00687     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00688 
00689     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.gpi0_rm, intm);
00690 
00691     return MAX77654_NO_ERROR;
00692 }
00693 
00694 int MAX77654::GetGPI0RisingInterruptMask(intm_t* intm)
00695 {
00696     int ret;
00697     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00698 
00699     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00700     if (ret != MAX77654_NO_ERROR) {
00701         return ret;
00702     }
00703 
00704     *intm = (intm_t)reg_intm_glbl0.bits.gpi0_rm;
00705 
00706     return MAX77654_NO_ERROR;
00707 }
00708 
00709 int MAX77654::SetGPI0FallingInterruptMask(intm_t intm)
00710 {
00711     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00712 
00713     SET_BIT_FIELD(INTM_GLBL0, reg_intm_glbl0, reg_intm_glbl0.bits.gpi0_fm, intm);
00714 
00715     return MAX77654_NO_ERROR;
00716 }
00717 
00718 int MAX77654::GetGPI0FallingInterruptMask(intm_t* intm)
00719 {
00720     int ret;
00721     reg_intm_glbl0_t reg_intm_glbl0 = {0};
00722 
00723     ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
00724     if (ret != MAX77654_NO_ERROR) {
00725         return ret;
00726     }
00727 
00728     *intm = (intm_t)reg_intm_glbl0.bits.gpi0_fm;
00729 
00730     return MAX77654_NO_ERROR;
00731 }
00732 
00733 int MAX77654::SetnENInternalPullupResistor(pu_dis_t pu_dis)
00734 {
00735     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00736 
00737     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.pu_dis, pu_dis);
00738 
00739     return MAX77654_NO_ERROR;
00740 }
00741 
00742 int MAX77654::GetnENInternalPullupResistor(pu_dis_t* pu_dis)
00743 {
00744     int ret;
00745     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00746 
00747     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00748     if (ret != MAX77654_NO_ERROR) {
00749         return ret;
00750     }
00751 
00752     *pu_dis = (pu_dis_t)reg_cnfg_glbl.bits.pu_dis;
00753 
00754     return MAX77654_NO_ERROR;
00755 }
00756 
00757 int MAX77654::SetManualResetTime(t_mrst_t t_mrst)
00758 {
00759     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00760 
00761     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.t_mrst, t_mrst);
00762 
00763     return MAX77654_NO_ERROR;
00764 }
00765 
00766 int MAX77654::GetManualResetTime(t_mrst_t* t_mrst)
00767 {
00768     int ret;
00769     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00770 
00771     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00772     if (ret != MAX77654_NO_ERROR) {
00773         return ret;
00774     }
00775 
00776     *t_mrst = (t_mrst_t)reg_cnfg_glbl.bits.t_mrst;
00777 
00778     return MAX77654_NO_ERROR;
00779 }
00780 
00781 int MAX77654::SetMainBiasLowerPowerModeReq(sbia_lpm_t sbia_lpm)
00782 {
00783     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00784 
00785     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.sbia_lpm, sbia_lpm);
00786 
00787     return MAX77654_NO_ERROR;
00788 }
00789 
00790 int MAX77654::GetMainBiasLowerPowerModeReq(sbia_lpm_t* sbia_lpm)
00791 {
00792     int ret;
00793     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00794 
00795     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00796     if (ret != MAX77654_NO_ERROR) {
00797         return ret;
00798     }
00799 
00800     *sbia_lpm = (sbia_lpm_t)reg_cnfg_glbl.bits.sbia_lpm;
00801 
00802     return MAX77654_NO_ERROR;
00803 }
00804 
00805 int MAX77654::SetMainBiasEnableReq(sbia_en_t sbia_en)
00806 {
00807     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00808 
00809     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.sbia_en, sbia_en);
00810 
00811     return MAX77654_NO_ERROR;
00812 }
00813 
00814 int MAX77654::GetMainBiasEnableReq(sbia_en_t* sbia_en)
00815 {
00816     int ret;
00817     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00818 
00819     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00820     if (ret != MAX77654_NO_ERROR) {
00821         return ret;
00822     }
00823 
00824     *sbia_en = (sbia_en_t)reg_cnfg_glbl.bits.sbia_en;
00825 
00826     return MAX77654_NO_ERROR;
00827 }
00828 
00829 int MAX77654::SetnEnInputMode(nen_mode_t nen_mode)
00830 {
00831     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00832 
00833     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.nen_mode, nen_mode);
00834 
00835     return MAX77654_NO_ERROR;
00836 }
00837 
00838 int MAX77654::GetnEnInputMode(nen_mode_t* nen_mode)
00839 {
00840     int ret;
00841     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00842 
00843     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00844     if (ret != MAX77654_NO_ERROR) {
00845         return ret;
00846     }
00847 
00848     *nen_mode = (nen_mode_t)reg_cnfg_glbl.bits.nen_mode;
00849 
00850     return MAX77654_NO_ERROR;
00851 }
00852 
00853 int MAX77654::SetDebounceTimerEnable(dben_nen_t dben_nen)
00854 {
00855     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00856 
00857     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.dben_nen, dben_nen);
00858 
00859     return MAX77654_NO_ERROR;
00860 }
00861 
00862 int MAX77654::GetDebounceTimerEnable(dben_nen_t* dben_nen)
00863 {
00864     int ret;
00865     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00866 
00867     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00868     if (ret != MAX77654_NO_ERROR) {
00869         return ret;
00870     }
00871 
00872     *dben_nen = (dben_nen_t)reg_cnfg_glbl.bits.dben_nen;
00873 
00874     return MAX77654_NO_ERROR;
00875 }
00876 
00877 int MAX77654::SetSoftwareResetFunctions(sft_ctrl_t sft_ctrl)
00878 {
00879     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00880 
00881     SET_BIT_FIELD(CNFG_GLBL, reg_cnfg_glbl, reg_cnfg_glbl.bits.sft_ctrl, sft_ctrl);
00882 
00883     return MAX77654_NO_ERROR;
00884 }
00885 
00886 int MAX77654::GetSoftwareResetFunctions(sft_ctrl_t* sft_ctrl)
00887 {
00888     int ret;
00889     reg_cnfg_glbl_t reg_cnfg_glbl = {0};
00890 
00891     ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
00892     if (ret != MAX77654_NO_ERROR) {
00893         return ret;
00894     }
00895 
00896     *sft_ctrl = (sft_ctrl_t)reg_cnfg_glbl.bits.sft_ctrl;
00897 
00898     return MAX77654_NO_ERROR;
00899 }
00900 
00901 int MAX77654::SetAlternateModeEnable(uint8_t channel, alt_gpio_t alt_gpio)
00902 {
00903     if (channel == 0) {
00904         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
00905         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.alt_gpio0, alt_gpio);
00906     }
00907     else if (channel == 1) {
00908         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
00909         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.alt_gpio1, alt_gpio);
00910     }
00911     else if (channel == 2) {
00912         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
00913         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.alt_gpio2, alt_gpio);
00914     }
00915     else {
00916         return MAX77654_INVALID_CHANNEL_NUMBER;
00917     }
00918 
00919     return MAX77654_NO_ERROR;
00920 }
00921 
00922 int MAX77654::GetAlternateModeEnable(uint8_t channel, alt_gpio_t* alt_gpio)
00923 {
00924     int ret;
00925 
00926     if (channel == 0) {
00927         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
00928         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
00929         if (ret != MAX77654_NO_ERROR) {
00930             return ret;
00931         }
00932 
00933         *alt_gpio = (alt_gpio_t)reg_cnfg_gpio0.bits.alt_gpio0;
00934     }
00935     else if (channel == 1) {
00936         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
00937         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
00938         if (ret != MAX77654_NO_ERROR) {
00939             return ret;
00940         }
00941 
00942         *alt_gpio = (alt_gpio_t)reg_cnfg_gpio1.bits.alt_gpio1;
00943     }
00944     else if (channel == 2) {
00945         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
00946         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
00947         if (ret != MAX77654_NO_ERROR) {
00948             return ret;
00949         }
00950 
00951         *alt_gpio = (alt_gpio_t)reg_cnfg_gpio2.bits.alt_gpio2;
00952     }
00953     else {
00954         return MAX77654_INVALID_CHANNEL_NUMBER;
00955     }
00956 
00957     return MAX77654_NO_ERROR;
00958 }
00959 
00960 int MAX77654::SetGPIDebounceTimerEnable(uint8_t channel, dben_gpi_t dben_gpi)
00961 {
00962     if (channel == 0) {
00963         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
00964         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.dben_gpi, dben_gpi);
00965     }
00966     else if (channel == 1) {
00967         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
00968         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.dben_gpi, dben_gpi);
00969     }
00970     else if (channel == 2) {
00971         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
00972         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.dben_gpi, dben_gpi);
00973     }
00974     else {
00975         return MAX77654_INVALID_CHANNEL_NUMBER;
00976     }
00977 
00978     return MAX77654_NO_ERROR;
00979 }
00980 
00981 int MAX77654::GetGPIDebounceTimerEnable(uint8_t channel, dben_gpi_t* dben_gpi)
00982 {
00983     int ret;
00984 
00985     if (channel == 0) {
00986         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
00987         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
00988         if (ret != MAX77654_NO_ERROR) {
00989             return ret;
00990         }
00991 
00992         *dben_gpi = (dben_gpi_t)reg_cnfg_gpio0.bits.dben_gpi;
00993     }
00994     else if (channel == 1) {
00995         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
00996         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
00997         if (ret != MAX77654_NO_ERROR) {
00998             return ret;
00999         }
01000 
01001         *dben_gpi = (dben_gpi_t)reg_cnfg_gpio1.bits.dben_gpi;
01002     }
01003     else if (channel == 2) {
01004         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01005         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
01006         if (ret != MAX77654_NO_ERROR) {
01007             return ret;
01008         }
01009 
01010         *dben_gpi = (dben_gpi_t)reg_cnfg_gpio2.bits.dben_gpi;
01011     }
01012     else {
01013         return MAX77654_INVALID_CHANNEL_NUMBER;
01014     }
01015 
01016     return MAX77654_NO_ERROR;
01017 }
01018 
01019 int MAX77654::SetGPODataOutput(uint8_t channel, gpo_do_t gpo_do)
01020 {
01021 
01022     if (channel == 0) {
01023         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01024         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.gpo_do, gpo_do);
01025     }
01026     else if (channel == 1) {
01027         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01028         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.gpo_do, gpo_do);
01029     }
01030     else if (channel == 2) {
01031         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01032         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.gpo_do, gpo_do);
01033     }
01034     else {
01035         return MAX77654_INVALID_CHANNEL_NUMBER;
01036     }
01037 
01038     return MAX77654_NO_ERROR;
01039 }
01040 
01041 int MAX77654::GetGPODataOutput(uint8_t channel, gpo_do_t *gpo_do)
01042 {
01043     int ret;
01044 
01045     if (channel == 0) {
01046         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01047         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
01048         if (ret != MAX77654_NO_ERROR) {
01049             return ret;
01050         }
01051 
01052         *gpo_do = (gpo_do_t)reg_cnfg_gpio0.bits.gpo_do;
01053     }
01054     else if (channel == 1) {
01055         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01056         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
01057         if (ret != MAX77654_NO_ERROR) {
01058             return ret;
01059         }
01060 
01061         *gpo_do = (gpo_do_t)reg_cnfg_gpio1.bits.gpo_do;
01062     }
01063     else if (channel == 2) {
01064         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01065         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
01066         if (ret != MAX77654_NO_ERROR) {
01067             return ret;
01068         }
01069 
01070         *gpo_do = (gpo_do_t)reg_cnfg_gpio2.bits.gpo_do;
01071     }
01072     else {
01073         return MAX77654_INVALID_CHANNEL_NUMBER;
01074     }
01075 
01076     return MAX77654_NO_ERROR;
01077 }
01078 
01079 int MAX77654::SetGPODriveType(uint8_t channel, gpo_drv_t gpo_drv)
01080 {
01081     if (channel == 0) {
01082         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01083         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.gpo_drv, gpo_drv);
01084     }
01085     else if (channel == 1) {
01086         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01087         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.gpo_drv, gpo_drv);
01088     }
01089     else if (channel == 2) {
01090         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01091         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.gpo_drv, gpo_drv);
01092     }
01093     else {
01094         return MAX77654_INVALID_CHANNEL_NUMBER;
01095     }
01096 
01097     return MAX77654_NO_ERROR;
01098 }
01099 
01100 int MAX77654::GetGPODriveType(uint8_t channel, gpo_drv_t *gpo_drv)
01101 {
01102     int ret;
01103 
01104     if (channel == 0) {
01105         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01106         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
01107         if (ret != MAX77654_NO_ERROR) {
01108             return ret;
01109         }
01110 
01111         *gpo_drv = (gpo_drv_t)reg_cnfg_gpio0.bits.gpo_drv;
01112     }
01113     else if (channel == 1) {
01114         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01115         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
01116         if (ret != MAX77654_NO_ERROR) {
01117             return ret;
01118         }
01119 
01120         *gpo_drv = (gpo_drv_t)reg_cnfg_gpio1.bits.gpo_drv;
01121     }
01122     else if (channel == 2) {
01123         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01124         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
01125         if (ret != MAX77654_NO_ERROR) {
01126             return ret;
01127         }
01128 
01129         *gpo_drv = (gpo_drv_t)reg_cnfg_gpio2.bits.gpo_drv;
01130     }
01131     else {
01132         return MAX77654_INVALID_CHANNEL_NUMBER;
01133     }
01134 
01135     return MAX77654_NO_ERROR;
01136 }
01137 
01138 int MAX77654::SetGPIOInputValue(uint8_t channel, gpo_di_t gpo_di)
01139 {
01140     if (channel == 0) {
01141         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01142         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.gpo_di, gpo_di);
01143     }
01144     else if (channel == 1) {
01145         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01146         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.gpo_di, gpo_di);
01147     }
01148     else if (channel == 2) {
01149         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01150         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.gpo_di, gpo_di);
01151     }
01152     else {
01153         return MAX77654_INVALID_CHANNEL_NUMBER;
01154     }
01155 
01156     return MAX77654_NO_ERROR;
01157 }
01158 
01159 int MAX77654::GetGPIOInputValue(uint8_t channel, gpo_di_t *gpo_di)
01160 {
01161     int ret;
01162 
01163     if (channel == 0) {
01164         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01165         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
01166         if (ret != MAX77654_NO_ERROR) {
01167             return ret;
01168         }
01169 
01170         *gpo_di = (gpo_di_t)reg_cnfg_gpio0.bits.gpo_di;
01171     }
01172     else if (channel == 1) {
01173         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01174         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
01175         if (ret != MAX77654_NO_ERROR) {
01176             return ret;
01177         }
01178 
01179         *gpo_di = (gpo_di_t)reg_cnfg_gpio1.bits.gpo_di;
01180     }
01181     else if (channel == 2) {
01182         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01183         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
01184         if (ret != MAX77654_NO_ERROR) {
01185             return ret;
01186         }
01187 
01188         *gpo_di = (gpo_di_t)reg_cnfg_gpio2.bits.gpo_di;
01189     }
01190     else {
01191         return MAX77654_INVALID_CHANNEL_NUMBER;
01192     }
01193 
01194     return MAX77654_NO_ERROR;
01195 }
01196 
01197 int MAX77654::SetGPIODirection(uint8_t channel, gpo_dir_t gpo_dir)
01198 {
01199     if (channel == 0) {
01200         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01201         SET_BIT_FIELD(CNFG_GPIO0, reg_cnfg_gpio0, reg_cnfg_gpio0.bits.gpo_dir, gpo_dir);
01202     }
01203     else if (channel == 1) {
01204         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01205         SET_BIT_FIELD(CNFG_GPIO1, reg_cnfg_gpio1, reg_cnfg_gpio1.bits.gpo_dir, gpo_dir);
01206     }
01207     else if (channel == 2) {
01208         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01209         SET_BIT_FIELD(CNFG_GPIO2, reg_cnfg_gpio2, reg_cnfg_gpio2.bits.gpo_dir, gpo_dir);
01210     }
01211     else {
01212         return MAX77654_INVALID_CHANNEL_NUMBER;
01213     }
01214 
01215     return MAX77654_NO_ERROR;
01216 }
01217 
01218 int MAX77654::GetGPIODirection(uint8_t channel, gpo_dir_t *gpo_dir)
01219 {
01220     int ret;
01221     
01222     if (channel == 0) {
01223         reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
01224         ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
01225         if (ret != MAX77654_NO_ERROR) {
01226             return ret;
01227         }
01228 
01229         *gpo_dir = (gpo_dir_t)reg_cnfg_gpio0.bits.gpo_dir;
01230     }
01231     else if (channel == 1) {
01232         reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
01233         ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
01234         if (ret != MAX77654_NO_ERROR) {
01235             return ret;
01236         }
01237 
01238         *gpo_dir = (gpo_dir_t)reg_cnfg_gpio1.bits.gpo_dir;
01239     }
01240     else if (channel == 2) {
01241         reg_cnfg_gpio2_t reg_cnfg_gpio2 = {0};
01242         ret = read_register(CNFG_GPIO2, (uint8_t *)&(reg_cnfg_gpio2));
01243         if (ret != MAX77654_NO_ERROR) {
01244             return ret;
01245         }
01246 
01247         *gpo_dir = (gpo_dir_t)reg_cnfg_gpio2.bits.gpo_dir;
01248     }
01249     else {
01250         return MAX77654_INVALID_CHANNEL_NUMBER;
01251     }
01252 
01253     return MAX77654_NO_ERROR;
01254 }
01255 
01256 int MAX77654::GetCID(void) {
01257     char rbuf[1];
01258     int ret;
01259 
01260     ret = read_register(CID, (uint8_t *)&(rbuf));
01261         if (ret != MAX77654_NO_ERROR) {
01262             return ret;
01263         }
01264  
01265     return *rbuf;
01266 }
01267 
01268 int MAX77654::SetWatchdogTimerPeriod(wdt_per_t wdt_per)
01269 {
01270     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01271 
01272     SET_BIT_FIELD(CNFG_WDT, reg_cnfg_wdt, reg_cnfg_wdt.bits.wdt_per, wdt_per);
01273 
01274     return MAX77654_NO_ERROR;
01275 }
01276 
01277 int MAX77654::GetWatchdogTimerPeriod(wdt_per_t *wdt_per)
01278 {
01279     int ret;
01280     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01281 
01282     ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
01283     if (ret != MAX77654_NO_ERROR) {
01284         return ret;
01285     }
01286 
01287     *wdt_per = (wdt_per_t)reg_cnfg_wdt.bits.wdt_per;
01288 
01289     return MAX77654_NO_ERROR;
01290 }
01291 
01292 int MAX77654::SetWatchdogTimerExpiredAction(wdt_mode_t wdt_mode)
01293 {
01294     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01295 
01296     SET_BIT_FIELD(CNFG_WDT, reg_cnfg_wdt, reg_cnfg_wdt.bits.wdt_mode, wdt_mode);
01297 
01298     return MAX77654_NO_ERROR;
01299 }
01300 
01301 int MAX77654::GetWatchdogTimerExpiredAction(wdt_mode_t *wdt_mode)
01302 {
01303     int ret;
01304     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01305 
01306     ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
01307     if (ret != MAX77654_NO_ERROR) {
01308         return ret;
01309     }
01310 
01311     *wdt_mode = (wdt_mode_t)reg_cnfg_wdt.bits.wdt_mode;
01312 
01313     return MAX77654_NO_ERROR;
01314 }
01315 
01316 int MAX77654::SetWatchdogTimerClearControl(wdt_clr_t wdt_clr)
01317 {
01318     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01319 
01320     SET_BIT_FIELD(CNFG_WDT, reg_cnfg_wdt, reg_cnfg_wdt.bits.wdt_clr, wdt_clr);
01321 
01322     return MAX77654_NO_ERROR;
01323 }
01324 
01325 int MAX77654::GetWatchdogTimerClearControl(wdt_clr_t *wdt_clr)
01326 {
01327     int ret;
01328     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01329 
01330     ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
01331     if (ret != MAX77654_NO_ERROR) {
01332         return ret;
01333     }
01334 
01335     *wdt_clr = (wdt_clr_t)reg_cnfg_wdt.bits.wdt_clr;
01336 
01337     return MAX77654_NO_ERROR;
01338 }
01339 
01340 int MAX77654::SetWatchdogTimerEnable(wdt_en_t wdt_en)
01341 {
01342     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01343 
01344     SET_BIT_FIELD(CNFG_WDT, reg_cnfg_wdt, reg_cnfg_wdt.bits.wdt_en, wdt_en);
01345 
01346     return MAX77654_NO_ERROR;
01347 }
01348 
01349 int MAX77654::GetWatchdogTimerEnable(wdt_en_t *wdt_en)
01350 {
01351     int ret;
01352     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01353 
01354     ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
01355     if (ret != MAX77654_NO_ERROR) {
01356         return ret;
01357     }
01358 
01359     *wdt_en = (wdt_en_t)reg_cnfg_wdt.bits.wdt_en;
01360 
01361     return MAX77654_NO_ERROR;
01362 }
01363 
01364 int MAX77654::SetFactorySetSafetyBit(wdt_lock_t wdt_lock)
01365 {
01366     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01367 
01368     SET_BIT_FIELD(CNFG_WDT, reg_cnfg_wdt, reg_cnfg_wdt.bits.wdt_lock, wdt_lock);
01369 
01370     return MAX77654_NO_ERROR;
01371 }
01372 
01373 int MAX77654::GetFactorySetSafetyBit(wdt_lock_t *wdt_lock)
01374 {
01375     int ret;
01376     reg_cnfg_wdt_t reg_cnfg_wdt = {0};
01377 
01378     ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
01379     if (ret != MAX77654_NO_ERROR) {
01380         return ret;
01381     }
01382 
01383     *wdt_lock = (wdt_lock_t)reg_cnfg_wdt.bits.wdt_lock;
01384 
01385     return MAX77654_NO_ERROR;
01386 }
01387 
01388 int MAX77654::GetMinimumVCHGINVoltageLoopStatus(stat_t *stat)
01389 {
01390     int ret;
01391     reg_stat_chg_a_t reg_stat_chg_a = {0};
01392 
01393     ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
01394     if (ret != MAX77654_NO_ERROR) {
01395         return ret;
01396     }
01397 
01398     *stat = (stat_t)reg_stat_chg_a.bits.vchgin_min_stat;
01399 
01400     return MAX77654_NO_ERROR;
01401 }
01402 
01403 int MAX77654::GetCHGINCurrentLimitLoopStatus(stat_t *stat)
01404 {
01405     int ret;
01406     reg_stat_chg_a_t reg_stat_chg_a = {0};
01407 
01408     ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
01409     if (ret != MAX77654_NO_ERROR) {
01410         return ret;
01411     }
01412 
01413     *stat = (stat_t)reg_stat_chg_a.bits.ichgin_lim_stat;
01414 
01415     return MAX77654_NO_ERROR;
01416 }
01417 
01418 int MAX77654::GetMinimumSYSVoltageLoopStatus(stat_t *stat)
01419 {
01420     int ret;
01421     reg_stat_chg_a_t reg_stat_chg_a = {0};
01422 
01423     ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
01424     if (ret != MAX77654_NO_ERROR) {
01425         return ret;
01426     }
01427 
01428     *stat = (stat_t)reg_stat_chg_a.bits.vsys_min_stat;
01429 
01430     return MAX77654_NO_ERROR;
01431 }
01432 
01433 int MAX77654::GetMaximumJunctionTempLoopStatus(stat_t *stat)
01434 {
01435     int ret;
01436     reg_stat_chg_a_t reg_stat_chg_a = {0};
01437 
01438     ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
01439     if (ret != MAX77654_NO_ERROR) {
01440         return ret;
01441     }
01442 
01443     *stat = (stat_t)reg_stat_chg_a.bits.tj_reg_stat;
01444 
01445     return MAX77654_NO_ERROR;
01446 }
01447 
01448 int MAX77654::GetBatteryTemperatureDetails(thm_dtls_t *thm_dtls)
01449 {
01450     int ret;
01451     reg_stat_chg_a_t reg_stat_chg_a = {0};
01452 
01453     ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
01454     if (ret != MAX77654_NO_ERROR) {
01455         return ret;
01456     }
01457 
01458     *thm_dtls = (thm_dtls_t)reg_stat_chg_a.bits.thm_dtls;
01459 
01460     return MAX77654_NO_ERROR;
01461 }
01462 
01463 int MAX77654::GetChargerDetails(chg_dtls_t *chg_dtls)
01464 {
01465     int ret;
01466     reg_stat_chg_b_t reg_stat_chg_b = {0};
01467 
01468     ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
01469     if (ret != MAX77654_NO_ERROR) {
01470         return ret;
01471     }
01472 
01473     *chg_dtls = (chg_dtls_t)reg_stat_chg_b.bits.chg_dtls;
01474 
01475     return MAX77654_NO_ERROR;
01476 }
01477 
01478 int MAX77654::GetCHGINStatusDetails(chgin_dtls_t *chgin_dtls)
01479 {
01480     int ret;
01481     reg_stat_chg_b_t reg_stat_chg_b = {0};
01482 
01483     ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
01484     if (ret != MAX77654_NO_ERROR) {
01485         return ret;
01486     }
01487 
01488     *chgin_dtls = (chgin_dtls_t)reg_stat_chg_b.bits.chgin_dtls;
01489 
01490     return MAX77654_NO_ERROR;
01491 }
01492 
01493 int MAX77654::GetQuickChargerStatus(chg_t *chg)
01494 {
01495     int ret;
01496     reg_stat_chg_b_t reg_stat_chg_b = {0};
01497 
01498     ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
01499     if (ret != MAX77654_NO_ERROR) {
01500         return ret;
01501     }
01502 
01503     *chg = (chg_t)reg_stat_chg_b.bits.chg;
01504 
01505     return MAX77654_NO_ERROR;
01506 }
01507 
01508 int MAX77654::GetTimeSuspendedIndicator(time_sus_t *time_sus)
01509 {
01510     int ret;
01511     reg_stat_chg_b_t reg_stat_chg_b = {0};
01512 
01513     ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
01514     if (ret != MAX77654_NO_ERROR) {
01515         return ret;
01516     }
01517 
01518     *time_sus = (time_sus_t)reg_stat_chg_b.bits.time_sus;
01519 
01520     return MAX77654_NO_ERROR;
01521 }
01522 
01523 int MAX77654::SetSYSCONFIGMBit(intm_t intm)
01524 {
01525     reg_int_m_chg_t reg_int_m_chg = {0};
01526 
01527     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.sys_cnfg_m, intm);
01528 
01529     return MAX77654_NO_ERROR;
01530 }
01531 
01532 int MAX77654::GetSYSCONFIGMBit(intm_t *intm)
01533 {
01534     int ret;
01535     reg_int_m_chg_t reg_int_m_chg = {0};
01536 
01537     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01538     if (ret != MAX77654_NO_ERROR) {
01539         return ret;
01540     }
01541 
01542     *intm = (intm_t)reg_int_m_chg.bits.sys_cnfg_m;
01543 
01544     return MAX77654_NO_ERROR;
01545 }
01546 
01547 int MAX77654::SetSYSCTRLMBit(intm_t intm)
01548 {
01549     reg_int_m_chg_t reg_int_m_chg = {0};
01550 
01551     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.sys_ctrl_m, intm);
01552 
01553     return MAX77654_NO_ERROR;
01554 }
01555 
01556 int MAX77654::GetSYSCTRLMBit(intm_t *intm)
01557 {
01558     int ret;
01559     reg_int_m_chg_t reg_int_m_chg = {0};
01560 
01561     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01562     if (ret != MAX77654_NO_ERROR) {
01563         return ret;
01564     }
01565 
01566     *intm = (intm_t)reg_int_m_chg.bits.sys_ctrl_m;
01567 
01568     return MAX77654_NO_ERROR;
01569 }
01570 
01571 int MAX77654::SetCHGINCTRLMBit(intm_t intm)
01572 {
01573     reg_int_m_chg_t reg_int_m_chg = {0};
01574 
01575     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.chgin_ctrl_m, intm);
01576 
01577     return MAX77654_NO_ERROR;
01578 }
01579 
01580 int MAX77654::GetCHGINCTRLMBit(intm_t *intm)
01581 { 
01582     int ret;
01583     reg_int_m_chg_t reg_int_m_chg = {0};
01584 
01585     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01586     if (ret != MAX77654_NO_ERROR) {
01587         return ret;
01588     }
01589 
01590     *intm = (intm_t)reg_int_m_chg.bits.chgin_ctrl_m;
01591 
01592     return MAX77654_NO_ERROR;
01593 }
01594 
01595 int MAX77654::SetTJREGMBit(intm_t intm)
01596 {
01597     reg_int_m_chg_t reg_int_m_chg = {0};
01598 
01599     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.tj_reg_m, intm);
01600 
01601     return MAX77654_NO_ERROR;
01602 }
01603 
01604 int MAX77654::GetTJREGMBit(intm_t *intm)
01605 {
01606     int ret;
01607     reg_int_m_chg_t reg_int_m_chg = {0};
01608 
01609     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01610     if (ret != MAX77654_NO_ERROR) {
01611         return ret;
01612     }
01613 
01614     *intm = (intm_t)reg_int_m_chg.bits.tj_reg_m;
01615 
01616     return MAX77654_NO_ERROR;
01617 }
01618 
01619 int MAX77654::SetCHGINMBit(intm_t intm)
01620 {
01621     reg_int_m_chg_t reg_int_m_chg = {0};
01622 
01623     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.chgin_m, intm);
01624 
01625     return MAX77654_NO_ERROR;
01626 }
01627 
01628 int MAX77654::GetCHGINMBit(intm_t *intm)
01629 {
01630     int ret;
01631     reg_int_m_chg_t reg_int_m_chg = {0};
01632 
01633     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01634     if (ret != MAX77654_NO_ERROR) {
01635         return ret;
01636     }
01637 
01638     *intm = (intm_t)reg_int_m_chg.bits.chgin_m;
01639 
01640     return MAX77654_NO_ERROR;
01641 }
01642 
01643 int MAX77654::SetCHGMBit(intm_t intm)
01644 {
01645     reg_int_m_chg_t reg_int_m_chg = {0};
01646 
01647     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.chg_m, intm);
01648 
01649     return MAX77654_NO_ERROR;
01650 }
01651 
01652 int MAX77654::GetCHGMBit(intm_t *intm)
01653 {
01654     int ret;
01655     reg_int_m_chg_t reg_int_m_chg = {0};
01656 
01657     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01658     if (ret != MAX77654_NO_ERROR) {
01659         return ret;
01660     }
01661 
01662     *intm = (intm_t)reg_int_m_chg.bits.chg_m;
01663 
01664     return MAX77654_NO_ERROR;
01665 }
01666 
01667 int MAX77654::SetTHMMBit(intm_t intm)
01668 {
01669     reg_int_m_chg_t reg_int_m_chg = {0};
01670 
01671     SET_BIT_FIELD(INT_M_CHG, reg_int_m_chg, reg_int_m_chg.bits.thm_m, intm);
01672 
01673     return MAX77654_NO_ERROR;
01674 }
01675 
01676 int MAX77654::GetTHMMBit(intm_t *intm)
01677 {
01678     int ret;
01679     reg_int_m_chg_t reg_int_m_chg = {0};
01680 
01681     ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
01682     if (ret != MAX77654_NO_ERROR) {
01683         return ret;
01684     }
01685 
01686     *intm = (intm_t)reg_int_m_chg.bits.thm_m;
01687 
01688     return MAX77654_NO_ERROR;
01689 }
01690 
01691 int MAX77654::SetHOTJEITATemperature(thm_hot_t thm_hot)
01692 {
01693     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01694 
01695     SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_hot, thm_hot);
01696 
01697     return MAX77654_NO_ERROR;
01698 }
01699 
01700 int MAX77654::GetHOTJEITATemperature(thm_hot_t *thm_hot)
01701 {
01702     int ret;
01703     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01704 
01705     ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
01706     if (ret != MAX77654_NO_ERROR) {
01707         return ret;
01708     }
01709 
01710     *thm_hot = (thm_hot_t)reg_cnfg_chg_a.bits.thm_hot;
01711 
01712     return MAX77654_NO_ERROR;
01713 }
01714 
01715 int MAX77654::SetWARMJEITATemperature(thm_warm_t thm_warm)
01716 {
01717     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01718 
01719     SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_warm, thm_warm);
01720 
01721     return MAX77654_NO_ERROR;
01722 }
01723 
01724 int MAX77654::GetWARMJEITATemperature(thm_warm_t *thm_warm)
01725 {
01726     int ret;
01727     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01728 
01729     ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
01730     if (ret != MAX77654_NO_ERROR) {
01731         return ret;
01732     }
01733 
01734     *thm_warm = (thm_warm_t)reg_cnfg_chg_a.bits.thm_warm;
01735 
01736     return MAX77654_NO_ERROR;
01737 }
01738 
01739 int MAX77654::SetCOOLJEITATemperature(thm_cool_t thm_cool)
01740 {
01741     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01742 
01743     SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cool, thm_cool);
01744 
01745     return MAX77654_NO_ERROR;
01746 }
01747 
01748 int MAX77654::GetCOOLJEITATemperature(thm_cool_t *thm_cool)
01749 {
01750     int ret;
01751     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01752 
01753     ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
01754     if (ret != MAX77654_NO_ERROR) {
01755         return ret;
01756     }
01757 
01758     *thm_cool = (thm_cool_t)reg_cnfg_chg_a.bits.thm_cool;
01759 
01760     return MAX77654_NO_ERROR;
01761 }
01762 
01763 int MAX77654::SetCOLDJEITATemperature(thm_cold_t thm_cold)
01764 {
01765     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01766 
01767     SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cold, thm_cold);
01768 
01769     return MAX77654_NO_ERROR;
01770 }
01771 
01772 int MAX77654::GetCOLDJEITATemperature(thm_cold_t *thm_cold)
01773 {
01774     int ret;
01775     reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
01776 
01777     ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
01778     if (ret != MAX77654_NO_ERROR) {
01779         return ret;
01780     }
01781 
01782     *thm_cold = (thm_cold_t)reg_cnfg_chg_a.bits.thm_cold;
01783 
01784     return MAX77654_NO_ERROR;
01785 }
01786 
01787 int MAX77654::SetMinimumCHGINVoltage(vchgin_min_t vchgin_min)
01788 {
01789     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01790 
01791     SET_BIT_FIELD(CNFG_CHG_B, reg_cnfg_chg_b, reg_cnfg_chg_b.bits.vchgin_min, vchgin_min);
01792 
01793     return MAX77654_NO_ERROR;
01794 }
01795 
01796 int MAX77654::GetMinimumCHGINVoltage(vchgin_min_t *vchgin_min)
01797 {
01798     int ret;
01799     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01800 
01801     ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
01802     if (ret != MAX77654_NO_ERROR) {
01803         return ret;
01804     }
01805 
01806     *vchgin_min = (vchgin_min_t)reg_cnfg_chg_b.bits.vchgin_min;
01807 
01808     return MAX77654_NO_ERROR;
01809 }
01810 
01811 int MAX77654::SetCHGINInputCurrentLimit(ichgin_lim_t ichgin_lim)
01812 {
01813     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01814 
01815     SET_BIT_FIELD(CNFG_CHG_B, reg_cnfg_chg_b, reg_cnfg_chg_b.bits.ichgin_lim, ichgin_lim);
01816 
01817     return MAX77654_NO_ERROR;
01818 }
01819 
01820 int MAX77654::GetCHGINInputCurrentLimit(ichgin_lim_t *ichgin_lim)
01821 {
01822     int ret;
01823     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01824 
01825     ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
01826     if (ret != MAX77654_NO_ERROR) {
01827         return ret;
01828     }
01829 
01830     *ichgin_lim = (ichgin_lim_t)reg_cnfg_chg_b.bits.ichgin_lim;
01831 
01832     return MAX77654_NO_ERROR;
01833 }
01834 
01835 int MAX77654::SetPrequalificationChargeCurrent(i_pq_t i_pq)
01836 {
01837     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01838 
01839     SET_BIT_FIELD(CNFG_CHG_B, reg_cnfg_chg_b, reg_cnfg_chg_b.bits.i_pq, i_pq);
01840 
01841     return MAX77654_NO_ERROR;
01842 }
01843 
01844 int MAX77654::GetPrequalificationChargeCurrent(i_pq_t *i_pq)
01845 {
01846     int ret;
01847     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01848 
01849     ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
01850     if (ret != MAX77654_NO_ERROR) {
01851         return ret;
01852     }
01853 
01854     *i_pq = (i_pq_t)reg_cnfg_chg_b.bits.i_pq;
01855 
01856     return MAX77654_NO_ERROR;
01857 }
01858 
01859 int MAX77654::SetBatteryChargerEnable(chg_en_t chg_en)
01860 {
01861     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01862 
01863     SET_BIT_FIELD(CNFG_CHG_B, reg_cnfg_chg_b, reg_cnfg_chg_b.bits.chg_en, chg_en);
01864 
01865     return MAX77654_NO_ERROR;
01866 }
01867 
01868 int MAX77654::GetBatteryChargerEnable(chg_en_t *chg_en)
01869 {
01870     int ret;
01871     reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
01872 
01873     ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
01874     if (ret != MAX77654_NO_ERROR) {
01875         return ret;
01876     }
01877 
01878     *chg_en = (chg_en_t)reg_cnfg_chg_b.bits.chg_en;
01879 
01880     return MAX77654_NO_ERROR;
01881 }
01882 
01883 int MAX77654::SetBatteryPQVoltageThreshold(chg_pq_t chg_pq)
01884 {
01885     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01886 
01887     SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.chg_pq, chg_pq);
01888 
01889     return MAX77654_NO_ERROR;
01890 }
01891 
01892 int MAX77654::GetBatteryPQVoltageThreshold(chg_pq_t *chg_pq)
01893 {
01894     int ret;
01895     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01896 
01897     ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
01898     if (ret != MAX77654_NO_ERROR) {
01899         return ret;
01900     }
01901 
01902     *chg_pq = (chg_pq_t)reg_cnfg_chg_c.bits.chg_pq;
01903 
01904     return MAX77654_NO_ERROR;
01905 }
01906 
01907 int MAX77654::SetChargerTerminationCurrent(i_term_t i_term)
01908 {
01909     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01910 
01911     SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.i_term, i_term);
01912 
01913     return MAX77654_NO_ERROR;
01914 }
01915 
01916 int MAX77654::GetChargerTerminationCurrent(i_term_t *i_term)
01917 {
01918     int ret;
01919     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01920 
01921     ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
01922     if (ret != MAX77654_NO_ERROR) {
01923         return ret;
01924     }
01925 
01926     *i_term = (i_term_t)reg_cnfg_chg_c.bits.i_term;
01927 
01928     return MAX77654_NO_ERROR;
01929 }
01930 
01931 int MAX77654::SetTopOffTimerValue(t_topoff_t t_topoff)
01932 {
01933     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01934 
01935     SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.t_topoff, t_topoff);
01936 
01937     return MAX77654_NO_ERROR;
01938 }
01939 
01940 int MAX77654::GetTopOffTimerValue(t_topoff_t *t_topoff)
01941 {
01942     int ret;
01943     reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
01944 
01945     ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
01946     if (ret != MAX77654_NO_ERROR) {
01947         return ret;
01948     }
01949 
01950     *t_topoff = (t_topoff_t)reg_cnfg_chg_c.bits.t_topoff;
01951 
01952     return MAX77654_NO_ERROR;
01953 }
01954 
01955 int MAX77654::SetDieJunctionTemperature(tj_reg_t tj_reg)
01956 {
01957     reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
01958 
01959     SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.tj_reg, tj_reg);
01960 
01961     return MAX77654_NO_ERROR;
01962 }
01963 
01964 int MAX77654::GetDieJunctionTemperature(tj_reg_t *tj_reg)
01965 {
01966     int ret;
01967     reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
01968 
01969     ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d));
01970     if (ret != MAX77654_NO_ERROR) {
01971         return ret;
01972     }
01973 
01974     *tj_reg = (tj_reg_t)reg_cnfg_chg_d.bits.tj_reg;
01975 
01976     return MAX77654_NO_ERROR;
01977 }
01978 
01979 int MAX77654::SetSystemVoltageRegulation(vsys_reg_t vsys_reg)
01980 {
01981     reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
01982 
01983     SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_reg, vsys_reg);
01984 
01985     return MAX77654_NO_ERROR;
01986 }
01987 
01988 int MAX77654::GetSystemVoltageRegulation(vsys_reg_t *vsys_reg)
01989 {
01990     int ret;
01991     reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
01992 
01993     ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d));
01994     if (ret != MAX77654_NO_ERROR) {
01995         return ret;
01996     }
01997 
01998     *vsys_reg = (vsys_reg_t)reg_cnfg_chg_d.bits.vsys_reg;
01999 
02000     return MAX77654_NO_ERROR;
02001 }
02002 
02003 int MAX77654::SetFastChargeCCValue(chg_cc_t chg_cc)
02004 {
02005     reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
02006 
02007     SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.chg_cc, chg_cc);
02008 
02009     return MAX77654_NO_ERROR;
02010 }
02011 
02012 int MAX77654::GetFastChargeCCValue(chg_cc_t *chg_cc)
02013 {
02014     int ret;
02015     reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
02016 
02017     ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e));
02018     if (ret != MAX77654_NO_ERROR) {
02019         return ret;
02020     }
02021 
02022     *chg_cc = (chg_cc_t)reg_cnfg_chg_e.bits.chg_cc;
02023 
02024     return MAX77654_NO_ERROR;
02025 }
02026 
02027 int MAX77654::SetFastChargSafetyTimer(t_fast_chg_t t_fast_chg)
02028 {
02029     reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
02030 
02031     SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.t_fast_chg, t_fast_chg);
02032 
02033     return MAX77654_NO_ERROR;
02034 }
02035 
02036 int MAX77654::GetFastChargSafetyTimer(t_fast_chg_t *t_fast_chg)
02037 {
02038     int ret;
02039     reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
02040 
02041     ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e));
02042     if (ret != MAX77654_NO_ERROR) {
02043         return ret;
02044     }
02045 
02046     *t_fast_chg = (t_fast_chg_t)reg_cnfg_chg_e.bits.t_fast_chg;
02047 
02048     return MAX77654_NO_ERROR;
02049 }
02050 
02051 int MAX77654::SetFastChargeCCJEITA(chg_cc_t chg_cc_jeita)
02052 {
02053     reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
02054 
02055     SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.chg_cc_jeita, chg_cc_jeita);
02056 
02057     return MAX77654_NO_ERROR;
02058 }
02059 
02060 int MAX77654::GetFastChargeCCJEITA(chg_cc_t *chg_cc_jeita)
02061 {
02062     int ret;
02063     reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
02064 
02065     ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f));
02066     if (ret != MAX77654_NO_ERROR) {
02067         return ret;
02068     }
02069 
02070     *chg_cc_jeita = (chg_cc_t)reg_cnfg_chg_f.bits.chg_cc_jeita;
02071 
02072     return MAX77654_NO_ERROR;
02073 }
02074 
02075 int MAX77654::SetThermistorEnable(thm_en_t thm_en)
02076 {
02077     reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
02078 
02079     SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.thm_en, thm_en);
02080 
02081     return MAX77654_NO_ERROR;
02082 }
02083 
02084 int MAX77654::GetThermistorEnable(thm_en_t *thm_en)
02085 {
02086     int ret;
02087     reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
02088 
02089     ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f));
02090     if (ret != MAX77654_NO_ERROR) {
02091         return ret;
02092     }
02093 
02094     *thm_en = (thm_en_t)reg_cnfg_chg_f.bits.thm_en;
02095 
02096     return MAX77654_NO_ERROR;
02097 }
02098 
02099 int MAX77654::SetFastChargeBatteryRegVolt(chg_cv_t chg_cv)
02100 {
02101     reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
02102 
02103     SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.chg_cv, chg_cv);
02104 
02105     return MAX77654_NO_ERROR;
02106 }
02107 
02108 int MAX77654::GetFastChargeBatteryRegVolt(chg_cv_t *chg_cv)
02109 {
02110     int ret;
02111     reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
02112 
02113     ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g));
02114     if (ret != MAX77654_NO_ERROR) {
02115         return ret;
02116     }
02117 
02118     *chg_cv = (chg_cv_t)reg_cnfg_chg_g.bits.chg_cv;
02119 
02120     return MAX77654_NO_ERROR;
02121 }
02122 
02123 int MAX77654::SetCHGINUSBSuspendMode(usbs_t usbs)
02124 {
02125     reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
02126 
02127     SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.usbs, usbs);
02128 
02129     return MAX77654_NO_ERROR;
02130 }
02131 
02132 int MAX77654::GetCHGINUSBSuspendMode(usbs_t *usbs)
02133 {
02134     int ret;
02135     reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
02136 
02137     ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g));
02138     if (ret != MAX77654_NO_ERROR) {
02139         return ret;
02140     }
02141 
02142     *usbs = (usbs_t)reg_cnfg_chg_g.bits.usbs;
02143 
02144     return MAX77654_NO_ERROR;
02145 }
02146 
02147 int MAX77654::SetFastChargeVoltageJEITA(chg_cv_t chg_cv_jeita)
02148 {
02149     reg_cnfg_chg_h_t reg_cnfg_chg_h = {0};
02150 
02151     SET_BIT_FIELD(CNFG_CHG_H, reg_cnfg_chg_h, reg_cnfg_chg_h.bits.chg_cv_jeita, chg_cv_jeita);
02152 
02153     return MAX77654_NO_ERROR;
02154 }
02155 
02156 int MAX77654::GetFastChargeVoltageJEITA(chg_cv_t *chg_cv_jeita)
02157 {
02158     int ret;
02159     reg_cnfg_chg_h_t reg_cnfg_chg_h = {0};
02160 
02161     ret = read_register(CNFG_CHG_H, (uint8_t *)&(reg_cnfg_chg_h));
02162     if (ret != MAX77654_NO_ERROR) {
02163         return ret;
02164     }
02165 
02166     *chg_cv_jeita = (chg_cv_t)reg_cnfg_chg_h.bits.chg_cv_jeita;
02167 
02168     return MAX77654_NO_ERROR;
02169 }
02170 
02171 int MAX77654::SetDischargeCurrentFullScale(imon_dischg_scale_t imon_dischg_scale)
02172 {
02173     reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
02174 
02175     SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.imon_dischg_scale, imon_dischg_scale);
02176 
02177     return MAX77654_NO_ERROR;
02178 }
02179 
02180 int MAX77654::GetDischargeCurrentFullScale(imon_dischg_scale_t *imon_dischg_scale)
02181 {
02182     int ret;
02183     reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
02184 
02185     ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i));
02186     if (ret != MAX77654_NO_ERROR) {
02187         return ret;
02188     }
02189 
02190     *imon_dischg_scale = (imon_dischg_scale_t)reg_cnfg_chg_i.bits.imon_dischg_scale;
02191 
02192     return MAX77654_NO_ERROR;
02193 }
02194 
02195 int MAX77654::SetAMUX(mux_sel_t mux_sel)
02196 {
02197     reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
02198 
02199     SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.mux_sel, mux_sel);
02200 
02201     return MAX77654_NO_ERROR;
02202 }
02203 
02204 int MAX77654::GetAMUX(mux_sel_t *mux_sel)
02205 {
02206     int ret;
02207     reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
02208 
02209     ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i));
02210     if (ret != MAX77654_NO_ERROR) {
02211         return ret;
02212     }
02213 
02214     *mux_sel = (mux_sel_t)reg_cnfg_chg_i.bits.mux_sel;
02215 
02216     return MAX77654_NO_ERROR;
02217 }
02218 
02219 int MAX77654::SetSBBTargetOutVoltage(uint8_t channel, tv_sbb_t tv_sbb)
02220 {
02221     if (channel == 0) {
02222         reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
02223         SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, tv_sbb);
02224     }
02225     else if (channel == 1) {
02226         reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
02227         SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, tv_sbb);
02228     }
02229     else if (channel == 2) {
02230         reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
02231         SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, tv_sbb);
02232     }
02233     else {
02234         return MAX77654_INVALID_CHANNEL_NUMBER;
02235     }
02236 
02237     return MAX77654_NO_ERROR;
02238 }
02239 
02240 int MAX77654::GetSBBTargetOutVoltage(uint8_t channel, tv_sbb_t *tv_sbb)
02241 {
02242     int ret;
02243 
02244     if (channel == 0) {
02245         reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
02246         ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
02247         if (ret != MAX77654_NO_ERROR) {
02248         return ret;
02249         }
02250         *tv_sbb = (tv_sbb_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
02251     }
02252     else if (channel == 1) {
02253         reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
02254         ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
02255         if (ret != MAX77654_NO_ERROR) {
02256         return ret;
02257         }
02258         *tv_sbb = (tv_sbb_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
02259     }
02260     else if (channel == 2) {
02261         reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
02262         ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
02263         if (ret != MAX77654_NO_ERROR) {
02264         return ret;
02265         }
02266         *tv_sbb = (tv_sbb_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
02267     }
02268     else {
02269         return MAX77654_INVALID_CHANNEL_NUMBER;
02270     }
02271 
02272     return MAX77654_NO_ERROR;
02273 }
02274 
02275 int MAX77654::SetSIMOOperationMode(uint8_t channel, op_mode_t op_mode)
02276 {
02277     if (channel == 0) {
02278         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02279         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode, op_mode);
02280     }
02281     else if (channel == 1) {
02282         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02283         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode, op_mode);
02284     }
02285     else if (channel == 2) {
02286         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02287         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode, op_mode);
02288     }
02289     else {
02290         return MAX77654_INVALID_CHANNEL_NUMBER;
02291     }
02292 
02293     return MAX77654_NO_ERROR;
02294 }
02295 
02296 int MAX77654::GetSIMOOperationMode(uint8_t channel, op_mode_t *op_mode)
02297 {
02298     int ret;
02299 
02300     if (channel == 0) {
02301         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02302         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
02303         if (ret != MAX77654_NO_ERROR) {
02304         return ret;
02305     }
02306         *op_mode = (op_mode_t)reg_cnfg_sbb0_b.bits.op_mode;
02307     }
02308     else if (channel == 1) {
02309         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02310         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
02311         if (ret != MAX77654_NO_ERROR) {
02312         return ret;
02313         }
02314         *op_mode = (op_mode_t)reg_cnfg_sbb1_b.bits.op_mode;
02315     }
02316     else if (channel == 2) {
02317         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02318         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
02319         if (ret != MAX77654_NO_ERROR) {
02320         return ret;
02321         }
02322         *op_mode = (op_mode_t)reg_cnfg_sbb2_b.bits.op_mode;
02323     }
02324     else {
02325         return MAX77654_INVALID_CHANNEL_NUMBER;
02326     }
02327 
02328     return MAX77654_NO_ERROR;
02329 }
02330 
02331 int MAX77654::SetSBBPeakCurrentLimit(uint8_t channel, ip_sbb_t ip_sbb)
02332 {
02333     if (channel == 0) {
02334         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02335         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ip_sbb0, ip_sbb);
02336     }
02337     else if (channel == 1) {
02338         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02339         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ip_sbb1, ip_sbb);
02340     }
02341     else if (channel == 2) {
02342         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02343         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ip_sbb2, ip_sbb);
02344     }
02345     else {
02346         return MAX77654_INVALID_CHANNEL_NUMBER;
02347     }
02348 
02349     return MAX77654_NO_ERROR;
02350 }
02351 
02352 int MAX77654::GetSBBPeakCurrentLimit(uint8_t channel, ip_sbb_t *ip_sbb)
02353 {
02354     int ret;
02355 
02356     if (channel == 0) {
02357         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02358         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
02359         if (ret != MAX77654_NO_ERROR) {
02360         return ret;
02361     }
02362         *ip_sbb = (ip_sbb_t)reg_cnfg_sbb0_b.bits.ip_sbb0;
02363     }
02364     else if (channel == 1) {
02365         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02366         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
02367         if (ret != MAX77654_NO_ERROR) {
02368         return ret;
02369         }
02370         *ip_sbb = (ip_sbb_t)reg_cnfg_sbb1_b.bits.ip_sbb1;
02371     }
02372     else if (channel == 2) {
02373         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02374         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
02375         if (ret != MAX77654_NO_ERROR) {
02376         return ret;
02377         }
02378         *ip_sbb = (ip_sbb_t)reg_cnfg_sbb2_b.bits.ip_sbb2;
02379     }
02380     else {
02381         return MAX77654_INVALID_CHANNEL_NUMBER;
02382     }
02383 
02384     return MAX77654_NO_ERROR;
02385 }
02386 
02387 int MAX77654::SetSBBActiveDischargeEnable(uint8_t channel, ade_sbb_t ade_sbb)
02388 {
02389     if (channel == 0) {
02390         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02391         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
02392     }
02393     else if (channel == 1) {
02394         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02395         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
02396     }
02397     else if (channel == 2) {
02398         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02399         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
02400     }
02401     else {
02402         return MAX77654_INVALID_CHANNEL_NUMBER;
02403     }
02404 
02405     return MAX77654_NO_ERROR;
02406 }
02407 
02408 int MAX77654::GetSBBActiveDischargeEnable(uint8_t channel, ade_sbb_t *ade_sbb)
02409 {
02410     int ret;
02411     
02412     if (channel == 0) {
02413         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02414         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
02415         if (ret != MAX77654_NO_ERROR) {
02416         return ret;
02417         }
02418         *ade_sbb = (ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
02419     }
02420     else if (channel == 1) {
02421         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02422         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
02423         if (ret != MAX77654_NO_ERROR) {
02424         return ret;
02425         }
02426         *ade_sbb = (ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
02427     }
02428     else if (channel == 2) {
02429         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02430         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
02431         if (ret != MAX77654_NO_ERROR) {
02432         return ret;
02433         }
02434         *ade_sbb = (ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
02435     }
02436     else {
02437         return MAX77654_INVALID_CHANNEL_NUMBER;
02438     }
02439 
02440     return MAX77654_NO_ERROR;
02441 }
02442 
02443 int MAX77654::SetSBBEnableControl(uint8_t channel, en_sbb_t en_sbb)
02444 {
02445     if (channel == 0) {
02446         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02447         SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
02448     }
02449     else if (channel == 1) {
02450         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02451         SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
02452     }
02453     else if (channel == 2) {
02454         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02455         SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
02456     }
02457     else {
02458         return MAX77654_INVALID_CHANNEL_NUMBER;
02459     }
02460 
02461     return MAX77654_NO_ERROR;
02462 }
02463 
02464 int MAX77654::GetSBBEnableControl(uint8_t channel, en_sbb_t *en_sbb)
02465 {
02466     int ret;
02467 
02468     if (channel == 0) {
02469         reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
02470         ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
02471         if (ret != MAX77654_NO_ERROR) {
02472         return ret;
02473         }
02474         *en_sbb = (en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
02475     }
02476     else if (channel == 1) {
02477         reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
02478         ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
02479         if (ret != MAX77654_NO_ERROR) {
02480         return ret;
02481         }
02482         *en_sbb = (en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
02483     }
02484     else if (channel == 2) {
02485         reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
02486         ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
02487         if (ret != MAX77654_NO_ERROR) {
02488         return ret;
02489         }
02490         *en_sbb = (en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
02491     }
02492     else {
02493         return MAX77654_INVALID_CHANNEL_NUMBER;
02494     }
02495 
02496     return MAX77654_NO_ERROR;
02497 }
02498 
02499 int MAX77654::SetCHGINInputCurrentLimit(ichgin_lim_def_t ichgin_lim_def)
02500 {
02501     reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
02502 
02503     SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.ichgin_lim_def, ichgin_lim_def);
02504 
02505     return MAX77654_NO_ERROR;
02506 }
02507 
02508 int MAX77654::GetCHGINInputCurrentLimit(ichgin_lim_def_t *ichgin_lim_def)
02509 {
02510     int ret;
02511     reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
02512 
02513     ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
02514     if (ret != MAX77654_NO_ERROR) {
02515         return ret;
02516     }
02517 
02518     *ichgin_lim_def = (ichgin_lim_def_t)reg_cnfg_sbb_top.bits.ichgin_lim_def;
02519 
02520     return MAX77654_NO_ERROR;
02521 }
02522 
02523 int MAX77654::SetSBBDriveStrength(drv_sbb_t drv_sbb)
02524 {
02525     reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
02526 
02527     SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.drv_sbb, drv_sbb);
02528 
02529     return MAX77654_NO_ERROR;
02530 }
02531 
02532 int MAX77654::GetSBBDriveStrength(drv_sbb_t *drv_sbb)
02533 {
02534     int ret;
02535     reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
02536 
02537     ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
02538     if (ret != MAX77654_NO_ERROR) {
02539         return ret;
02540     }
02541 
02542     *drv_sbb = (drv_sbb_t)reg_cnfg_sbb_top.bits.drv_sbb;
02543 
02544     return MAX77654_NO_ERROR;
02545 }
02546 
02547 int MAX77654::SetLDOTargetOutVoltage(uint8_t channel, tv_ldo_t tv_ldo)
02548 {
02549     if (channel == 0) {
02550         reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
02551         SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo0, tv_ldo);
02552     }
02553     else if (channel == 1) {
02554         reg_cnfg_ldo1_a_t reg_cnfg_ldo1_a = {0};
02555         SET_BIT_FIELD(CNFG_LDO1_A, reg_cnfg_ldo1_a, reg_cnfg_ldo1_a.bits.tv_ldo1, tv_ldo);
02556     }
02557     else {
02558         return MAX77654_INVALID_CHANNEL_NUMBER;
02559     }
02560 
02561     return MAX77654_NO_ERROR;
02562 }
02563 
02564 int MAX77654::GetLDOTargetOutVoltage(uint8_t channel, tv_ldo_t *tv_ldo)
02565 {
02566     int ret;
02567 
02568     if (channel == 0) {
02569         reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
02570         ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
02571         if (ret != MAX77654_NO_ERROR) {
02572         return ret;
02573         }
02574         *tv_ldo = (tv_ldo_t)reg_cnfg_ldo0_a.bits.tv_ldo0;
02575     }
02576     else if (channel == 1) {
02577         reg_cnfg_ldo1_a_t reg_cnfg_ldo1_a = {0};
02578         ret = read_register(CNFG_LDO1_A, (uint8_t *)&(reg_cnfg_ldo1_a));
02579         if (ret != MAX77654_NO_ERROR) {
02580         return ret;
02581         }
02582         *tv_ldo = (tv_ldo_t)reg_cnfg_ldo1_a.bits.tv_ldo1;
02583     }
02584     else {
02585         return MAX77654_INVALID_CHANNEL_NUMBER;
02586     }
02587 
02588     return MAX77654_NO_ERROR;
02589 }
02590 
02591 int MAX77654::SetLDOMode(uint8_t channel, ldo_md_t ldo_md)
02592 {
02593     if (channel == 0) {
02594         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02595         SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo0_md, ldo_md);
02596     }
02597     else if (channel == 1) {
02598         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02599         SET_BIT_FIELD(CNFG_LDO1_B, reg_cnfg_ldo1_b, reg_cnfg_ldo1_b.bits.ldo1_md, ldo_md);
02600     }
02601     else {
02602         return MAX77654_INVALID_CHANNEL_NUMBER;
02603     }
02604 
02605     return MAX77654_NO_ERROR;
02606 }
02607 
02608 int MAX77654::GetLDOMode(uint8_t channel, ldo_md_t *ldo_md)
02609 {
02610     int ret;
02611 
02612     if (channel == 0) {
02613         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02614         ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
02615         if (ret != MAX77654_NO_ERROR) {
02616         return ret;
02617         }
02618         *ldo_md = (ldo_md_t)reg_cnfg_ldo0_b.bits.ldo0_md;
02619     }
02620     else if (channel == 1) {
02621         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02622         ret = read_register(CNFG_LDO1_B, (uint8_t *)&(reg_cnfg_ldo1_b));
02623         if (ret != MAX77654_NO_ERROR) {
02624         return ret;
02625         }
02626         *ldo_md = (ldo_md_t)reg_cnfg_ldo1_b.bits.ldo1_md;
02627     }
02628     else {
02629         return MAX77654_INVALID_CHANNEL_NUMBER;
02630     }
02631 
02632     return MAX77654_NO_ERROR;
02633 }
02634 
02635 int MAX77654::SetLDOActiveDischargeEnable(uint8_t channel, ade_ldo_t ade_ldo)
02636 {
02637     if (channel == 0) {
02638         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02639         SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo0, ade_ldo);
02640     }
02641     else if (channel == 1) {
02642         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02643         SET_BIT_FIELD(CNFG_LDO1_B, reg_cnfg_ldo1_b, reg_cnfg_ldo1_b.bits.ade_ldo1, ade_ldo);
02644     }
02645     else {
02646         return MAX77654_INVALID_CHANNEL_NUMBER;
02647     }
02648 
02649     return MAX77654_NO_ERROR;
02650 }
02651 
02652 int MAX77654::GetLDOActiveDischargeEnable(uint8_t channel, ade_ldo_t *ade_ldo)
02653 {
02654     int ret;
02655 
02656     if (channel == 0) {
02657         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02658         ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
02659         if (ret != MAX77654_NO_ERROR) {
02660         return ret;
02661         }
02662         *ade_ldo = (ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo0;
02663     }
02664     else if (channel == 1) {
02665         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02666         ret = read_register(CNFG_LDO1_B, (uint8_t *)&(reg_cnfg_ldo1_b));
02667         if (ret != MAX77654_NO_ERROR) {
02668         return ret;
02669         }
02670         *ade_ldo = (ade_ldo_t)reg_cnfg_ldo1_b.bits.ade_ldo1;
02671     }
02672     else {
02673         return MAX77654_INVALID_CHANNEL_NUMBER;
02674     }
02675 
02676     return MAX77654_NO_ERROR;
02677 }
02678 
02679 int MAX77654::SetLDOEnableControl(uint8_t channel, en_ldo_t en_ldo)
02680 {
02681     if (channel == 0) {
02682         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02683         SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo0, en_ldo);
02684     }
02685     else if (channel == 1) {
02686         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02687         SET_BIT_FIELD(CNFG_LDO1_B, reg_cnfg_ldo1_b, reg_cnfg_ldo1_b.bits.en_ldo1, en_ldo);
02688     }
02689     else {
02690         return MAX77654_INVALID_CHANNEL_NUMBER;
02691     }
02692 
02693     return MAX77654_NO_ERROR;
02694 }
02695 
02696 int MAX77654::GetLDOEnableControl(uint8_t channel, en_ldo_t *en_ldo)
02697 {
02698     int ret;
02699 
02700     if (channel == 0) {
02701         reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
02702         ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
02703         if (ret != MAX77654_NO_ERROR) {
02704         return ret;
02705         }
02706         *en_ldo = (en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo0;
02707     }
02708     else if (channel == 1) {
02709         reg_cnfg_ldo1_b_t reg_cnfg_ldo1_b = {0};
02710         ret = read_register(CNFG_LDO1_B, (uint8_t *)&(reg_cnfg_ldo1_b));
02711         if (ret != MAX77654_NO_ERROR) {
02712         return ret;
02713         }
02714         *en_ldo = (en_ldo_t)reg_cnfg_ldo1_b.bits.en_ldo1;
02715     }
02716     else {
02717         return MAX77654_INVALID_CHANNEL_NUMBER;
02718     }
02719 
02720     return MAX77654_NO_ERROR;
02721 }
02722 
02723 int MAX77654::IRQDisableAll()
02724 {
02725     int ret;
02726     uint8_t reg = 0;
02727     uint8_t status = 0;
02728 
02729     //Disable Masks in INTM_GLBL1
02730     ret = write_register(INTM_GLBL1, &reg);
02731     if (ret != MAX77654_NO_ERROR) {
02732         return ret;
02733     }
02734     //Disable Masks in INTM_GLBL0
02735     ret = write_register(INTM_GLBL0, &reg);
02736     if (ret != MAX77654_NO_ERROR) {
02737         return ret;
02738     }
02739     //Disable Masks in INT_M_CHG
02740     ret = write_register(INT_M_CHG, &reg);
02741     if (ret != MAX77654_NO_ERROR) {
02742         return ret;
02743     }
02744 
02745     // Clear Interrupt Flags in INT_GLBL1
02746     ret = read_register(INT_GLBL1, &status);
02747     if (ret != MAX77654_NO_ERROR) {
02748         return ret;
02749     }
02750     // Clear Interrupt Flags in INT_GLBL0
02751     ret = read_register(INT_GLBL0, &status);
02752     if (ret != MAX77654_NO_ERROR) {
02753         return ret;
02754     }
02755     // Clear Interrupt Flags in INT_CHG
02756     ret = read_register(INT_CHG, &status);
02757     if (ret != MAX77654_NO_ERROR) {
02758         return ret;
02759     }
02760 
02761     return 0;
02762 }
02763 
02764 void MAX77654::SetInterruptHandler(int_glbl_t id, interrupt_handler_function func, void *cb)
02765 {
02766     interrupt_handler_list[id].func = func;
02767     interrupt_handler_list[id].cb = cb;
02768 }
02769 
02770 void MAX77654::PostInterruptWork()
02771 {
02772     int ret;
02773     uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
02774 
02775 
02776     while (true) {
02777 
02778         ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
02779 
02780         // Check Interrupt Flags in INT_GLBL0
02781         ret = read_register(INT_GLBL0, &reg);
02782         if (ret != MAX77654_NO_ERROR) {
02783             return;
02784         }
02785 
02786         ret = read_register(INTM_GLBL0, &inten);
02787         if (ret != MAX77654_NO_ERROR) {
02788             return;
02789         }
02790 
02791         not_inten = ~inten; // 0 means unmasked.
02792 
02793         for (int i = 0; i < INT_GLBL1_GPI1_F; i++) {
02794             mask = (1 << i);
02795             if ((reg & mask) && (not_inten & mask)) {
02796                 if (interrupt_handler_list[i].func != NULL) {
02797                     interrupt_handler_list[i]
02798                     .func(interrupt_handler_list[i].cb);
02799                 }
02800             }
02801         }
02802 
02803         // Check Interrupt Flags in INT_GLBL1
02804         ret = read_register(INT_GLBL1, &reg);
02805         if (ret != MAX77654_NO_ERROR) {
02806             return;
02807         }
02808 
02809         ret = read_register(INTM_GLBL1, &inten);
02810         if (ret != MAX77654_NO_ERROR) {
02811             return;
02812         }
02813 
02814         not_inten = ~inten; // 0 means unmasked.
02815 
02816         for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_THM_I; i++) {
02817             mask = (1 << (i - INT_GLBL1_GPI1_F));
02818             if ((reg & mask) && (not_inten & mask)) {
02819                 if (interrupt_handler_list[i].func != NULL) {
02820                     interrupt_handler_list[i]
02821                     .func(interrupt_handler_list[i].cb);
02822                 }
02823             }
02824         }
02825 
02826         // Check Interrupt Flags in INT_CHG
02827         ret = read_register(INT_CHG, &reg);
02828         if (ret != MAX77654_NO_ERROR) {
02829             return;
02830         }
02831 
02832         ret = read_register(INT_M_CHG, &inten);
02833         if (ret != MAX77654_NO_ERROR) {
02834             return;
02835         }
02836 
02837         not_inten = ~inten; // 0 means unmasked.
02838 
02839         for (int i = INT_CHG_THM_I; i < INT_CHG_END; i++) {
02840             mask = (1 << (i - INT_CHG_THM_I));
02841             if ((reg & mask) && (not_inten & mask)) {
02842                 if (interrupt_handler_list[i].func != NULL) {
02843                     interrupt_handler_list[i]
02844                     .func(interrupt_handler_list[i].cb);
02845                 }
02846             }
02847         }
02848     }
02849 }
02850 void MAX77654::InterruptHandler()
02851 {
02852     post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
02853 }
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Created:	25 Mar 2022
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