Maxim Integrated
MAX77654 Ultra-Low Power PMIC Mbed Driver
MAX77654_regs.h@4:77203c01b399, 20 months ago (annotated)
- Committer:
- Okan Sahin
- Date:
- Fri Aug 26 14:57:06 2022 +0300
- Revision:
- 4:77203c01b399
- Parent:
- 0:788f63dcf0a0
fix interrupt_handler_list
use number of interrupts as a size of array.
initialize with NULL.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1 | /******************************************************************************* |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 2 | * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 3 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 5 | * copy of this software and associated documentation files(the "Software"), |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 6 | * to deal in the Software without restriction, including without limitation |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 9 | * Software is furnished to do so, subject to the following conditions: |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 10 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 11 | * The above copyright notice and this permission notice shall be included |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 12 | * in all copies or substantial portions of the Software. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 13 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 21 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 23 | * Products, Inc.shall not be used except as stated in the Maxim Integrated |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 24 | * Products, Inc.Branding Policy. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 25 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 26 | * The mere transfer of this software does not imply any licenses |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 29 | * property whatsoever. Maxim Integrated Products, Inc.retains all |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 30 | * ownership rights. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 31 | ******************************************************************************* |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 32 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 33 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 34 | #ifndef MAX77654_REGS_H_ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 35 | #define MAX77654_REGS_H_ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 36 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 37 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 38 | * @brief INT_GLBL0 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 39 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 40 | * Address : 0x00 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 41 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 42 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 43 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 44 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 45 | unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 46 | Note that "GPI" refers to the GPIO programmed to be an input. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 47 | 0 = No GPI falling edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 48 | 1 = A GPI falling edge has occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 49 | unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 50 | Note that "GPI" refers to the GPIO programmed to be an input. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 51 | 0 = No GPI rising edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 52 | 1 = A GPI rising edge has occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 53 | unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 54 | 0 = No nEN falling edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 55 | 1 = A nEN falling edge as occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 56 | unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 57 | 0 = No nEN rising edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 58 | 1 = A nEN rising edge as occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 59 | unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 60 | 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 61 | 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 62 | unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 63 | 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 64 | 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 65 | unsigned char d0d1_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 66 | 0 = The LDO has not detected dropout since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 67 | 1 = The LDO has detected dropout since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 68 | unsigned char dod0_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 69 | 0 = The LDO has not detected dropout since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 70 | 1 = The LDO has detected dropout since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 71 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 72 | } reg_int_glbl0_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 73 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 74 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 75 | * @brief INT_GLBL1 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 76 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 77 | * Address : 0x04 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 78 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 79 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 80 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 81 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 82 | unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 83 | Note that "GPI" refers to the GPIO programmed to be an input. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 84 | 0 = No GPI falling edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 85 | 1 = A GPI falling edge has occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 86 | unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 87 | Note that "GPI" refers to the GPIO programmed to be an input. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 88 | 0 = No GPI rising edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 89 | 1 = A GPI rising edge has occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 90 | unsigned char gpi2_f : 1; /**< GPI Falling Interrupt.Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 91 | 0 = No GPI falling edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 92 | 1 = A GPI falling edge as occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 93 | unsigned char gpi2_r : 1; /**< GPI Rising Interrupt. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 94 | Note that "GPI" refers to the GPIO programmed to be an input. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 95 | 0 = No GPI rising edges have occurred since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 96 | 1 = A GPI rising edge has occurred since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 97 | unsigned char sbb_to : 1; /**< SBB Timeout. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 98 | 0 = NO SBB timeout occurred since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 99 | 1 = SBB timeout occurred since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 100 | unsigned char ldo0_f : 1; /**< LDO0 Fault Interrupt. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 101 | 0 = No fault has occurred on LDO0 since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 102 | 1 = LDO0 has fallen out of regulation since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 103 | unsigned char ldo1_f : 1; /**< LDO1 Fault Interrupt. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 104 | 0 = No fault has occurred on LDO1 since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 105 | 1 = LDO1 has fallen out of regulation since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 106 | unsigned char rsvd : 1; /**< Reserved. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 107 | Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 108 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 109 | } reg_int_glbl1_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 110 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 111 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 112 | * @brief ERCFLAG Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 113 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 114 | * Address : 0x05 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 115 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 116 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 117 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 118 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 119 | unsigned char tovld : 1; /**< Thermal Overload. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 120 | 0 = Thermal overload has not occurred since the last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 121 | 1 = Thermal overload has occurred since the list read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 122 | This indicates that the junction temperature has exceeded 165ºC. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 123 | unsigned char sysovlo : 1; /**< SYS Domain Overvoltage Lockout. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 124 | 0 = The SYS domain overvoltage lockout has not occurred since this last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 125 | 1 = The SYS domain overvoltage lockout has occurred since the last read of this register. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 126 | unsigned char sysuvlo : 1; /**< SYS Domain Undervoltage Lockout. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 127 | 0 = The SYS domain undervoltage lockout has not occurred since this last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 128 | 1 = The SYS domain undervoltage lockout has occurred since the last read of this register. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 129 | unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 130 | 0 = A Manual Reset has not occurred since this last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 131 | 1 = A Manual Reset has occurred since this last read of this register. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 132 | unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 133 | 0 = The SFT_OFF function has not occurred since the last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 134 | 1 = The SFT_OFF function has occurred since the last read of this register. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 135 | unsigned char sft_crst_f: 1; /**< Software Cold Reset Flag. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 136 | 0 = The software cold reset has not occurred since the last read of this register. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 137 | 1 = The software cold reset has occurred since the last read of this register. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 138 | unsigned char wdt_off : 1; /**< Watchdog Timer OFF Flag. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 139 | This bit sets when the watchdog timer expires and causes a power-off. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 140 | 0 = Watchdog timer has not caused a power-off since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 141 | 1 = Watchdog timer has expired and caused a power-off since the last time this bit was read. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 142 | unsigned char wdt_rst : 1; /**< Watchdog Timer Reset Flag. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 143 | This bit sets when the watchdog timer expires and causes a power-reset. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 144 | 0 = Watchdog timer has not caused a power-reset since the last time this bit was read. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 145 | 1 = Watchdog timer has expired and caused a power-reset since the last time this bit was read.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 146 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 147 | } reg_ercflag_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 148 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 149 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 150 | * @brief STAT_GLBL Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 151 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 152 | * Address : 0x06 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 153 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 154 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 155 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 156 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 157 | unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 158 | 0 = unmasked gate drive is logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 159 | 1 = unmasked gate drive is logic high */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 160 | unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 161 | 0 = nEN is not active (logic high) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 162 | 1 = nEN is active (logic low) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 163 | unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 164 | 0 = The junction temperature is less than TJAL1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 165 | 1 = The junction temperature is greater than TJAL1 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 166 | unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 167 | 0 = The junction temperature is less than TJAL2 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 168 | 1 = The junction temperature is greater than TJAL2 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 169 | unsigned char dod1_s : 1; /**< LDO1 Dropout Detector Rising Status. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 170 | 0 = LDO1 is not in dropout |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 171 | 1 = LDO1 is in dropout */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 172 | unsigned char dod0_s : 1; /**< LDO0 Dropout Detector Rising Status. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 173 | 0 = LDO0 is not in dropout |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 174 | 1 = LDO0 is in dropout */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 175 | unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 176 | 0 = Main Bias is not ready. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 177 | 1 = Main Bias enabled and ready. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 178 | unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 179 | 0 = MAX77654 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 180 | 1 = Reserved */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 181 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 182 | } reg_stat_glbl_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 183 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 184 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 185 | * @brief INTM_GLBL1 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 186 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 187 | * Address : 0x08 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 188 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 189 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 190 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 191 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 192 | unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 193 | 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 194 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 195 | 1 = Masked. nIRQ does not go low due to GPI_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 196 | unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 197 | 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 198 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 199 | 1 = Masked. nIRQ does not go low due to GPI_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 200 | unsigned char gpi2_fm : 1; /**< GPI Falling Interrupt Mask. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 201 | 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 202 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 203 | 1 = Masked. nIRQ does not go low due to GPI_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 204 | unsigned char gpi2_rm : 1; /**< GPI Rising Interrupt Mask. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 205 | 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 206 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 207 | 1 = Masked. nIRQ does not go low due to GPI_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 208 | unsigned char sbb_to_m : 1; /**< SBB Timeout Mask. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 209 | 0 = Unmasked. If SBB_TO goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 210 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 211 | 1 = Masked. nIRQ does not go low due to SBB_TO */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 212 | unsigned char ldo0_m : 1; /**< LDO0 Fault Interrupt. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 213 | 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 214 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 215 | 1 = Masked. nIRQ does not go low due to LDO0_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 216 | unsigned char ldo1_m : 1; /**< LDO1 Fault Interrupt Mask. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 217 | 0 = Unmasked. If LDO1_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 218 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 219 | 1 = Masked. nIRQ does not go low due to LDO1_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 220 | unsigned char rsvd : 1; /**< Reserved. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 221 | Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 222 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 223 | } reg_intm_glbl1_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 224 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 225 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 226 | * @brief INTM_GLBL0 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 227 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 228 | * Address : 0x09 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 229 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 230 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 231 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 232 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 233 | unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 234 | 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 235 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 236 | 1 = Masked. nIRQ does not go low due to GPI_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 237 | unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 238 | 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 239 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 240 | 1 = Masked. nIRQ does not go low due to GPI_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 241 | unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 242 | 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 243 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 244 | 1 = Masked. nIRQ does not go low due to nEN_F. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 245 | unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 246 | 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 247 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 248 | 1 = Masked. nIRQ does not go low due to nEN_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 249 | unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 250 | 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 251 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 252 | 1 = Masked. nIRQ does not go low due to TJAL1_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 253 | unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 254 | 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 255 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 256 | 1 = Masked. nIRQ does not go low due to TJAL2_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 257 | unsigned char dod1_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 258 | 0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 259 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 260 | 1 = Masked. nIRQ does not go low due to DOD1_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 261 | unsigned char dod0_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 262 | 0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 263 | nIRQ goes high when all interrupt bits are cleared. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 264 | 1 = Masked. nIRQ does not go low due to DOD0_R. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 265 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 266 | } reg_intm_glbl0_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 267 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 268 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 269 | * @brief CNFG_GLBL Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 270 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 271 | * Address : 0x10 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 272 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 273 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 274 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 275 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 276 | unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 277 | 0b00 = No Action |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 278 | 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 279 | 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 280 | 0b11 = Factory-Ship Mode Enter (FSM). */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 281 | unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 282 | 0 = 500μs Debounce |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 283 | 1 = 30ms Debounce */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 284 | unsigned char nen_mode : 1; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 285 | 0 = Push-Button Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 286 | 1 = Slide-Switch Mode */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 287 | unsigned char sbia_en : 1; /**< Main Bias Enable Software Request. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 288 | 0 = Main Bias not enabled by software. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 289 | Note that the main bias may be on via the on/off controller. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 290 | 1 = Main Bias force enabled by software. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 291 | unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 292 | 0 = Main Bias requested to be in Normal-Power Mode by software. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 293 | 1 = Main Bias request to be in Low-Power Mode by software. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 294 | unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 295 | 0 = 8s |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 296 | 1 = 16s */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 297 | unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 298 | 0 = Strong internal nEN pullup (200kΩ) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 299 | 1 = Weak internal nEN pullup (10MΩ) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 300 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 301 | } reg_cnfg_glbl_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 302 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 303 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 304 | * @brief CNFG_GPIO0 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 305 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 306 | * Address : 0x11 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 307 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 308 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 309 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 310 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 311 | unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 312 | 0 = General purpose output (GPO) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 313 | 1 = General purpose input (GPI) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 314 | unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 315 | 0 = Input logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 316 | 1 = Input logic high */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 317 | unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 318 | This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 319 | 0 = Open-Drain |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 320 | 1 = Push-Pull */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 321 | unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 322 | This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 323 | 0 = GPIO is output is logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 324 | 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 325 | unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 326 | 0 = no debounce |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 327 | 1 = 30ms debounce */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 328 | unsigned char alt_gpio0 : 1; /**< Alternate Mode Enable for GPIO0. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 329 | 0 = Standard GPIO. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 330 | 1 = Flexible Power Sequencer Active-High Output for SBB2. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 331 | unsigned char : 1; /**< Bit 6. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 332 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 333 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 334 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 335 | } reg_cnfg_gpio0_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 336 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 337 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 338 | * @brief CNFG_GPIO1 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 339 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 340 | * Address : 0x12 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 341 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 342 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 343 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 344 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 345 | unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 346 | 0 = General purpose output (GPO) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 347 | 1 = General purpose input (GPI) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 348 | unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 349 | 0 = Input logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 350 | 1 = Input logic high */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 351 | unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 352 | This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 353 | 0 = Open-Drain |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 354 | 1 = Push-Pull */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 355 | unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 356 | This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 357 | 0 = GPIO is output is logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 358 | 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 359 | unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 360 | 0 = no debounce |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 361 | 1 = 30ms debounce */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 362 | unsigned char alt_gpio1 : 1; /**< Alternate Mode Enable for GPIO1. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 363 | 0 = Standard GPIO. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 364 | 1 = SBB2 Enable. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 365 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 366 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 367 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 368 | } reg_cnfg_gpio1_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 369 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 370 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 371 | * @brief CNFG_GPIO2 Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 372 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 373 | * Address : 0x13 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 374 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 375 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 376 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 377 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 378 | unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 379 | 0 = General purpose output (GPO) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 380 | 1 = General purpose input (GPI) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 381 | unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 382 | 0 = Input logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 383 | 1 = Input logic high */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 384 | unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 385 | This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 386 | 0 = Open-Drain |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 387 | 1 = Push-Pull */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 388 | unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 389 | This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 390 | 0 = GPIO is output is logic low |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 391 | 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 392 | unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 393 | 0 = no debounce |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 394 | 1 = 30ms debounce */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 395 | unsigned char alt_gpio2 : 1; /**< Alternate Mode Enable for GPIO2. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 396 | 0 = Standard GPIO. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 397 | 1 = Bias LPM mode enable. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 398 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 399 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 400 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 401 | } reg_cnfg_gpio2_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 402 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 403 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 404 | * @brief CID Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 405 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 406 | * Address : 0x14 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 407 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 408 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 409 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 410 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 411 | unsigned char cid_3_0 : 4; /**< Bits 0 to 3 of the Chip Identification Code. Bit 3:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 412 | The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 413 | unsigned char : 3; /**< Bit 6:4. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 414 | unsigned char cid_7 : 1; /**< Bit 4 of the Chip Identification Code. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 415 | The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 416 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 417 | } reg_cid_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 418 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 419 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 420 | * @brief CNFG_WDT Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 421 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 422 | * Address : 0x17 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 423 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 424 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 425 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 426 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 427 | unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 428 | 0 = Watchdog timer can be enabled and disabled with WDT_EN. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 429 | 1 = Watchdog timer can not be disabled with WDT_EN. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 430 | However, WDT_EN can still be used to enable the watchdog timer. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 431 | unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 432 | 0 = Watchdog timer is not enabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 433 | 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 434 | unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 435 | 0 = Watchdog timer period is not reset. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 436 | 1 = Watchdog timer is reset back to tWD. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 437 | unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 438 | 0 = Watchdog timer expire causes power-off. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 439 | 1 = Watchdog timer expire causes power-reset. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 440 | unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 441 | 0b00 = 16 seconds 0b01 = 32 seconds |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 442 | 0b10 = 64 seconds 0b11 = 128 seconds. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 443 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 444 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 445 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 446 | } reg_cnfg_wdt_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 447 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 448 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 449 | * @brief INT_CHG Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 450 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 451 | * Address : 0x01 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 452 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 453 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 454 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 455 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 456 | unsigned char thm_i : 1; /**< Thermistor related interrupt. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 457 | 0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 458 | 1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 459 | unsigned char chg_i : 1; /**< Charger related interrupt. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 460 | 0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 461 | 1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 462 | unsigned char chgin_i : 1; /**< CHGIN related interrupt. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 463 | 0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 464 | 1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 465 | unsigned char tj_reg_i : 1; /**< Die junction temperature regulation interrupt. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 466 | 0 = The die temperature has not exceeded TJ-REG since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 467 | 1 = The die temperature has exceeded TJ-REG since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 468 | unsigned char chgin_ctrl_i : 1; /**< CHGIN control-loop related interrupt. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 469 | 0 = Neither the VCHGIN_MIN_STAT nor the ICHGIN_LIM_STAT bits have changed since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 470 | 1 = The VCHGIN_MIN_STAT or ICHGIN_LIM_STAT bits have changed since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 471 | unsigned char sys_ctrl_i : 1; /**< Minimum System Voltage Regulation-loop related interrupt. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 472 | 0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 473 | 1 = The minimum system voltage regulation loop has engaged since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 474 | unsigned char sys_cnfg_i : 1; /**< System voltage configuration error interrupt. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 475 | 0 = The bit combination in CHG_CV has not been forced to change since the last time this bit was read |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 476 | 1 = The bit combination in CHG_CV has been forced to change to ensure VSYS-REG = VFAST-CHG + 200mV |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 477 | since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 478 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 479 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 480 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 481 | } reg_int_chg_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 482 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 483 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 484 | * @brief STAT_CHG_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 485 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 486 | * Address : 0x02 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 487 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 488 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 489 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 490 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 491 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 492 | unsigned char thm_dtls : 3; /**< Battery Temperature Details. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 493 | 0b000 = Thermistor is disabled (THM_EN = 0) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 494 | 0b001 = Battery is cold as programmed by THM_COLD[1:0] If thermistor and charger are enabled while the battery is cold, a battery temperature fault will occur. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 495 | 0b010 = Battery is cool as programmed by THM_COOL[1:0] |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 496 | 0b011 = Battery is warm as programmed by THM_WARM[1:0] |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 497 | 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault will occur. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 498 | 0b101 = Battery is in the normal temperature region |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 499 | 0b110 - 0b111 = reserved */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 500 | unsigned char tj_reg_stat : 1; /**< Maximum Junction Temperature Regulation Loop Status. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 501 | 0 = The maximum junction temperature regulation loop is not engaged |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 502 | 1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 503 | unsigned char vsys_min_stat : 1; /**< Minimum System Voltage Regulation Loop Status. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 504 | 0 = The minimum system voltage regulation loop is not enganged |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 505 | 1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 506 | unsigned char ichgin_lim_stat : 1; /**< Input Current Limit Loop Status. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 507 | 0 = The CHGIN current limit loop is not engaged |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 508 | 1 = The CHGIN current limit loop has engaged to regulate ICHGIN ≤ ICHGIN-LIM */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 509 | unsigned char vchgin_min_stat : 1; /**< Minimum Input Voltage Regulation Loop Status. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 510 | 0 = The minimum CHGIN voltage regulation loop is not engaged |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 511 | 1 = The minimum CHGIN voltage regulation loop has engaged to regulate VCHGIN ≥ VCHGIN-MIN */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 512 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 513 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 514 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 515 | } reg_stat_chg_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 516 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 517 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 518 | * @brief STAT_CHG_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 519 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 520 | * Address : 0x03 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 521 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 522 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 523 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 524 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 525 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 526 | unsigned char time_sus : 1; /**< Time Suspend Indicator. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 527 | 0 = The charger's timers are either not active, or not suspended |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 528 | 1 = The charger's active timer is suspended due to one of three reasons: |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 529 | charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 530 | the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 531 | unsigned char chg : 1; /**< Quick Charger Status. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 532 | 0 = Charging is not happening |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 533 | 1 = Charging is happening */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 534 | unsigned char chgin_dtls : 2; /**< CHGIN Status Detail. Bit 3:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 535 | 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 536 | 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 537 | 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 538 | 0b11 = The CHGIN input is okay and debounced */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 539 | unsigned char chg_dtls : 4; /**< Charger Details. Bit 7:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 540 | 0b0000 = Off |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 541 | 0b0001 = Prequalification mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 542 | 0b0010 = Fast-charge constant-current (CC) mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 543 | 0b0011 = JEITA modified fast-charge constant-current mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 544 | 0b0100 = Fast-charge constant-voltage (CV) mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 545 | 0b0101 = JEITA modified fast-charge constant-voltage mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 546 | 0b0110 = Top-off mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 547 | 0b0111 = JEITA modified top-off mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 548 | 0b1000 = Done |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 549 | 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 550 | 0b1010 = Prequalification timer fault |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 551 | 0b1011 = Fast-charge timer fault |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 552 | 0b1100 = Battery temperature fault |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 553 | 0b1101 - 0b1111 = reserved */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 554 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 555 | } reg_stat_chg_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 556 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 557 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 558 | * @brief INT_M_CHG Register |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 559 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 560 | * Address : 0x07 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 561 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 562 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 563 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 564 | struct { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 565 | unsigned char thm_m : 1; /**< Setting this bit prevents the THM_I bit from causing hardware IRQs. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 566 | 0 = THM_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 567 | 1 = THM_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 568 | unsigned char chg_m : 1; /**< Setting this bit prevents the CHG_I bit from causing hardware IRQs. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 569 | 0 = CHG_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 570 | 1 = CHG_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 571 | unsigned char chgin_m : 1; /**< Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. Bit 2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 572 | 0 = CHGIN_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 573 | 1 = CHGIN_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 574 | unsigned char tj_reg_m : 1; /**< Setting this bit prevents the TJREG_I bit from causing hardware IRQs. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 575 | 0 = TJREG_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 576 | 1 = TJREG_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 577 | unsigned char chgin_ctrl_m : 1; /**< Setting this bit prevents the CHGIN_CTRL_I bit from causing hardware IRQs. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 578 | 0 = CHGIN_CTRL_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 579 | 1 = CHGIN_CTRL_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 580 | unsigned char sys_ctrl_m : 1; /**< Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. Bit 5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 581 | 0 = SYS_CTRL_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 582 | 1 = SYS_CTRL_I is masked */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 583 | unsigned char sys_cnfg_m : 1; /**< Setting this bit prevents the SYS_CNFG_I bit from causing hardware IRQs. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 584 | 0 = SYS_CNFG_I is not masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 585 | 1 = SYS_CNFG_I is masked |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 586 | since the last time this bit was read */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 587 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 588 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 589 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 590 | } reg_int_m_chg_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 591 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 592 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 593 | * @brief CNFG_CHG_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 594 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 595 | * Address : 0x20 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 596 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 597 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 598 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 599 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 600 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 601 | unsigned char thm_cold : 2; /**< Sets the VCOLD JEITA Temperature Threshold. Bit 1:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 602 | 0b00 = VCOLD = 1.024V (-10ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 603 | 0b01 = VCOLD = 0.976V (-5ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 604 | 0b10 = VCOLD = 0.923V (0ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 605 | 0b11 = VCOLD = 0.867V (5ºC for β = 3380K) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 606 | unsigned char thm_cool : 2; /**< Sets the VCOOL JEITA Temperature Threshold. Bit 3:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 607 | 0b00 = VCOOL = 0.923V (0ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 608 | 0b01 = VCOOL = 0.867V (5ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 609 | 0b10 = VCOOL = 0.807V (10ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 610 | 0b11 = VCOOL = 0.747V (15ºC for β = 3380K) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 611 | unsigned char thm_warm : 2; /**< Sets the VWARM JEITA Temperature Threshold. Bit 5:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 612 | 0b00 = VWARM = 0.511V (35ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 613 | 0b01 = VWARM = 0.459V (40ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 614 | 0b10 = VWARM = 0.411V (45ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 615 | 0b11 = VWARM = 0.367V (50ºC for β = 3380K) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 616 | unsigned char thm_hot : 2; /**< Sets the VHOT JEITA Temperature Threshold. Bit 7:6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 617 | 0b00 = VHOT = 0.411V (45ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 618 | 0b01 = VHOT = 0.367V (50ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 619 | 0b10 = VHOT = 0.327V (55ºC for β = 3380K) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 620 | 0b11 = VHOT = 0.291V (60ºC for β = 3380K) */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 621 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 622 | } reg_cnfg_chg_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 623 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 624 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 625 | * @brief CNFG_CHG_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 626 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 627 | * Address : 0x21 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 628 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 629 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 630 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 631 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 632 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 633 | unsigned char chg_en : 1; /**< Charger Enable. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 634 | 0 = the battery charger is disabled |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 635 | 1 = the battery charger is enabled */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 636 | unsigned char i_pq : 1; /**< Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 637 | 0 = 10% 1 = 20% */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 638 | unsigned char ichgin_lim : 3; /**< CHGIN Input Current Limit (ICHGIN-LIM). Bit 4:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 639 | 0b000 = 95mA 0b001 = 190mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 640 | 0b010 = 285mA 0b011 = 380mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 641 | 0b100 = 475mA 0b101 0b111 = Reserved. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 642 | unsigned char vchgin_min : 3; /**< Minimum CHGIN regulation voltage (VCHGIN-MIN). Bit 7:5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 643 | 0b000 = 4.0V 0b001 = 4.1V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 644 | 0b010 = 4.2V 0b011 = 4.3V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 645 | 0b100 = 4.4V 0b101 = 4.5V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 646 | 0b110 = 4.6V 0b111 = 4.7V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 647 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 648 | } reg_cnfg_chg_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 649 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 650 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 651 | * @brief CNFG_CHG_C |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 652 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 653 | * Address : 0x22 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 654 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 655 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 656 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 657 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 658 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 659 | unsigned char t_topoff : 3; /**< Top-off timer value (tTO). Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 660 | 0b000 = 0 minutes 0b001 = 5 minutes |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 661 | 0b010 = 10 minutes 0b011 = 15 minutes |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 662 | 0b100 = 20 minutes 0b101 = 25 minutes |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 663 | 0b110 = 30 minutes 0b111 = 35 minutes */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 664 | unsigned char i_term : 2; /**< Charger Termination Current (ITERM). Bit 4:3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 665 | 00 = 5% 01 = 7.5% |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 666 | 10 = 10% 11 = 15% */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 667 | unsigned char chg_pq : 3; /**< Battery prequalification voltage threshold (VPQ). Bit 7:5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 668 | 0b000 = 2.3V 0b001 = 2.4V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 669 | 0b010 = 2.5V 0b011 = 2.6V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 670 | 0b100 = 2.7V 0b101 = 2.8V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 671 | 0b110 = 2.9V 0b111 = 3.0V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 672 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 673 | } reg_cnfg_chg_c_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 674 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 675 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 676 | * @brief CNFG_CHG_D |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 677 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 678 | * Address : 0x23 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 679 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 680 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 681 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 682 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 683 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 684 | unsigned char vsys_reg : 5; /**< System voltage regulation (VSYS-REG). Bit 4:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 685 | 0x0 = 4.100V 0x1 = 4.125V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 686 | 0x2 = 4.150V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 687 | 0x1B = 4.775V 0x1C - 0x1F = 4.800V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 688 | unsigned char tj_reg : 3; /**< Sets the die junction temperature regulation point, TJ-REG. Bit 7:5. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 689 | 0b000 = 60ºC 0b001 = 70ºC |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 690 | 0b010 = 80ºC 0b011 = 90ºC |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 691 | 0b100 - 0b111 = 100ºC */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 692 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 693 | } reg_cnfg_chg_d_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 694 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 695 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 696 | * @brief CNFG_CHG_E |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 697 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 698 | * Address : 0x25 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 699 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 700 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 701 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 702 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 703 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 704 | unsigned char t_fast_chg : 2; /**< System voltage regulation (VSYS-REG). Bit 1:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 705 | 0b00 = timer disabled 0b01 = 3 hours |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 706 | 0b10 = 5 hours 0b11 = 7 hours */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 707 | unsigned char chg_cc : 6; /**< Sets the fast-charge constant current value, IFAST-CHG. Bit 7:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 708 | 0x0 = 7.5mA 0x1 = 15.0mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 709 | 0x2 = 22.5mA ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 710 | 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 711 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 712 | } reg_cnfg_chg_e_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 713 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 714 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 715 | * @brief CNFG_CHG_F |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 716 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 717 | * Address : 0x25 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 718 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 719 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 720 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 721 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 722 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 723 | unsigned char : 1; /**< Bit 0*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 724 | unsigned char thm_en : 1; /**< Thermistor enable bit. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 725 | 0 = Thermistor is disabled |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 726 | 1 = Thermistor is enabled */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 727 | unsigned char chg_cc_jeita : 6; /**< Sets IFAST-CHG-JEITA for when the battery is either cool or warm as defined |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 728 | by the VCOOL and VWARM temperature thresholds. Bit 7:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 729 | 0x0 = 7.5mA 0x1 = 15.0mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 730 | 0x2 = 22.5mA ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 731 | 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 732 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 733 | } reg_cnfg_chg_f_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 734 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 735 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 736 | * @brief CNFG_CHG_G |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 737 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 738 | * Address : 0x26 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 739 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 740 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 741 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 742 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 743 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 744 | unsigned char rsvd : 1; /**< Reserved. Bit 0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 745 | Unutilized bit. Write to 0. Reads are don't care.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 746 | unsigned char usbs : 1; /**< Setting this bit places CHGIN in USB suspend mode. Bit 1. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 747 | 0 = CHGIN is not suspended and may draw current from an adapter source |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 748 | 1 = CHGIN is suspended and may draw no current from an adapter source */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 749 | unsigned char chg_cv : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 750 | 0x0 = 3.600V 0x1 = 3.625V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 751 | 0x2 = 3.650V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 752 | 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 753 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 754 | } reg_cnfg_chg_g_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 755 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 756 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 757 | * @brief CNFG_CHG_H |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 758 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 759 | * Address : 0x27 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 760 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 761 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 762 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 763 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 764 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 765 | unsigned char rsvd : 2; /**< Reserved. Bit 1:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 766 | Unutilized bit. Write to 0. Reads are don't care.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 767 | unsigned char chg_cv_jeita : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 768 | 0x0 = 3.600V 0x1 = 3.625V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 769 | 0x2 = 3.650V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 770 | 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 771 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 772 | } reg_cnfg_chg_h_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 773 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 774 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 775 | * @brief CNFG_CHG_I |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 776 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 777 | * Address : 0x28 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 778 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 779 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 780 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 781 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 782 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 783 | unsigned char mux_sel : 4; /**< Selects the analog channel to connect to AMUX. Bit 3:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 784 | 0b0000 = Multiplexer is disabled and AMUX is high-impedance. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 785 | 0b0001 = CHGIN voltage monitor. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 786 | 0b0010 = CHGIN current monitor. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 787 | 0b0011 = BATT voltage monitor. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 788 | 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1). |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 789 | 0b0101 = BATT discharge current monitor normal measurement. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 790 | 0b0110 = BATT discharge current monitor nulling measurement. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 791 | 0b0111 = THM voltage monitor 0b1000 = TBIAS voltage monitor |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 792 | 0b1001 = AGND voltage monitor (through 100Ω pull-down resistor) |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 793 | 0b1010 - 0b1111 = SYS voltage monitor */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 794 | unsigned char imon_dischg_scale : 4; /**< Selects the battery discharge current full-scale current value. Bit 7:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 795 | 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 796 | 0x3 = 103.4mA 0x4 = 134.1mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 797 | 0x5 = 164.1mA 0x6 = 193.7mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 798 | 0x7 = 222.7mA 0x8 = 251.2mA |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 799 | 0x9 = 279.3mA 0xA - 0xF = 300.0mA */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 800 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 801 | } reg_cnfg_chg_i_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 802 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 803 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 804 | * @brief CNFG_SBB0_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 805 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 806 | * Address : 0x29 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 807 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 808 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 809 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 810 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 811 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 812 | unsigned char tv_sbb0 : 7; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 6:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 813 | 0x00 = 0.800V 0x01 = 0.850V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 814 | 0x02 = 0.900V 0x03 = 0.950V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 815 | 0x04 = 1.000V 0x05 = 1.050V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 816 | 0x06 = 1.100V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 817 | 0x5C = 5.400V 0x5D = 5.450V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 818 | 0x5E - 0x7F = 5.500V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 819 | unsigned char : 1; /**< Bit 7. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 820 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 821 | } reg_cnfg_sbb0_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 822 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 823 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 824 | * @brief CNFG_SBB0_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 825 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 826 | * Address : 0x2A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 827 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 828 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 829 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 830 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 831 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 832 | unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 833 | selecting either an FPS slot the channel powers-up and powers-down in |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 834 | or whether the channel is forced on or off. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 835 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 836 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 837 | 0b100 = Off irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 838 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 839 | 0b111 = same as 0b110 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 840 | unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 841 | 0 = The active discharge function is disabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 842 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 843 | 1 = The active discharge function is enabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 844 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 845 | unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 5:4 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 846 | 0b00 = 1.000A 0b01 = 0.750A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 847 | 0b10 = 0.500A 0b11 = 0.333A*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 848 | unsigned char op_mode : 1; /**< Operation mode of SBB0. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 849 | 0 = Buck-Boost Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 850 | 1 = Buck Mode*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 851 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 852 | Unutilized bit. Write to 0. Reads are don't care.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 853 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 854 | } reg_cnfg_sbb0_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 855 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 856 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 857 | * @brief CNFG_SBB1_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 858 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 859 | * Address : 0x2B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 860 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 861 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 862 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 863 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 864 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 865 | unsigned char tv_sbb1 : 7; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 6:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 866 | 0x00 = 0.800V 0x01 = 0.850V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 867 | 0x02 = 0.900V 0x03 = 0.950V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 868 | 0x04 = 1.000V 0x05 = 1.050V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 869 | 0x06 = 1.100V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 870 | 0x5C = 5.400V 0x5D = 5.450V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 871 | 0x5E - 0x7F = 5.500V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 872 | unsigned char : 1; /**< Bit 7. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 873 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 874 | } reg_cnfg_sbb1_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 875 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 876 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 877 | * @brief CNFG_SBB1_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 878 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 879 | * Address : 0x2C |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 880 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 881 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 882 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 883 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 884 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 885 | unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 886 | selecting either an FPS slot the channel powers-up and powers-down in |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 887 | or whether the channel is forced on or off. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 888 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 889 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 890 | 0b100 = Off irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 891 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 892 | 0b111 = same as 0b110 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 893 | unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 894 | 0 = The active discharge function is disabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 895 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 896 | 1 = The active discharge function is enabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 897 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 898 | unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 5:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 899 | 0b00 = 1.000A 0b01 = 0.750A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 900 | 0b10 = 0.500A 0b11 = 0.333A*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 901 | unsigned char op_mode : 1; /**< Operation mode of SBB1. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 902 | 0 = Buck-Boost Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 903 | 1 = Buck Mode*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 904 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 905 | Unutilized bit. Write to 0. Reads are don't care.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 906 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 907 | } reg_cnfg_sbb1_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 908 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 909 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 910 | * @brief CNFG_SBB2_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 911 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 912 | * Address : 0x2D |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 913 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 914 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 915 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 916 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 917 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 918 | unsigned char tv_sbb2 : 7; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 6:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 919 | 0x00 = 0.800V 0x01 = 0.850V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 920 | 0x02 = 0.900V 0x03 = 0.950V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 921 | 0x04 = 1.000V 0x05 = 1.050V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 922 | 0x06 = 1.100V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 923 | 0x5C = 5.400V 0x5D = 5.450V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 924 | 0x5E - 0x7F = 5.500V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 925 | unsigned char : 1; /**< Bit 7. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 926 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 927 | } reg_cnfg_sbb2_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 928 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 929 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 930 | * @brief CNFG_SBB2_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 931 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 932 | * Address : 0x2E |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 933 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 934 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 935 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 936 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 937 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 938 | unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2, |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 939 | selecting either an FPS slot the channel powers-up and powers-down in |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 940 | or whether the channel is forced on or off. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 941 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 942 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 943 | 0b100 = Off irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 944 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 945 | 0b111 = same as 0b110 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 946 | unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 947 | 0 = The active discharge function is disabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 948 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 949 | 1 = The active discharge function is enabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 950 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 951 | unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 952 | 0b00 = 1.000A 0b01 = 0.750A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 953 | 0b10 = 0.500A 0b11 = 0.333A*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 954 | unsigned char op_mode : 1; /**< Operation mode of SBB2. Bit 6. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 955 | 0 = Buck-Boost Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 956 | 1 = Buck Mode*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 957 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 958 | Unutilized bit. Write to 0. Reads are don't care.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 959 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 960 | } reg_cnfg_sbb2_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 961 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 962 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 963 | * @brief CNFG_SBB_TOP |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 964 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 965 | * Address : 0x2F |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 966 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 967 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 968 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 969 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 970 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 971 | unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 972 | 0b00 = fastest transition time |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 973 | 0b01 = a little slower than 0b00 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 974 | 0b10 = a little slower than 0b01 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 975 | 0b11 = a little slower than 0b10 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 976 | unsigned char : 5; /**< Bit 6:2. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 977 | unsigned char ichgin_lim_def : 1; /**< Changes how CNFG_CHG_B.ICHGIN_LIM is interpreted. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 978 | See CNFG_CHG_B.ICHGIN_LIM for more details.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 979 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 980 | } reg_cnfg_sbb_top_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 981 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 982 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 983 | * @brief CNFG_LDO0_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 984 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 985 | * Address : 0x38 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 986 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 987 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 988 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 989 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 990 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 991 | unsigned char tv_ldo0 : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 992 | that starts at 0.8V and ends at 3.975V, with 25mV increments. Bit 6:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 993 | 0x00 = 0.800V 0x01 = 0.825V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 994 | 0x02 = 0.850V 0x03 = 0.875V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 995 | 0x04 = 0.900V 0x05 = 0.925V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 996 | 0x06 = 0.950V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 997 | 0x7D = 3.925V 0x7E = 3.950V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 998 | 0x7F = 3.975V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 999 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1000 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1001 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1002 | } reg_cnfg_ldo0_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1003 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1004 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1005 | * @brief CNFG_LDO0_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1006 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1007 | * Address : 0x39 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1008 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1009 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1010 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1011 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1012 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1013 | unsigned char en_ldo0 : 3; /**< Enable Control for LDO0, selecting either an FPS slot the channel powers-up and |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1014 | powers-down in or whether the channel is forced on or off. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1015 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1016 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1017 | 0b100 = Off irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1018 | 0b101 = same as 0b100 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1019 | 0b110 = On irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1020 | 0b111 = same as 0b110 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1021 | unsigned char ade_ldo0 : 1; /**< LDO0 Active-Discharge Enable. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1022 | 0 = The active discharge function is disabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1023 | 1 = The active discharge function is enabled. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1024 | unsigned char ldo0_md : 1; /**< Operation mode of LDO0. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1025 | 0 = Low Dropout Linear Regulator (LDO) Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1026 | 1 = Load Switch (LSW) Mode */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1027 | unsigned char : 3; /**< Bit 7:5. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1028 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1029 | } reg_cnfg_ldo0_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1030 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1031 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1032 | * @brief CNFG_LDO1_A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1033 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1034 | * Address : 0x3A |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1035 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1036 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1037 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1038 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1039 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1040 | unsigned char tv_ldo1 : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1041 | that starts at 0.8V and ends at 3.975V, with 25mV increments. Bit 6:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1042 | 0x00 = 0.800V 0x01 = 0.825V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1043 | 0x02 = 0.850V 0x03 = 0.875V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1044 | 0x04 = 0.900V 0x05 = 0.925V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1045 | 0x06 = 0.950V ... |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1046 | 0x7D = 3.925V 0x7E = 3.950V |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1047 | 0x7F = 3.975V */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1048 | unsigned char rsvd : 1; /**< Reserved. Bit 7. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1049 | Unutilized bit. Write to 0. Reads are don't care. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1050 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1051 | } reg_cnfg_ldo1_a_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1052 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1053 | /** |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1054 | * @brief CNFG_LDO1_B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1055 | * |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1056 | * Address : 0x3B |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1057 | */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1058 | typedef union { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1059 | unsigned char raw; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1060 | struct |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1061 | { |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1062 | unsigned char en_ldo1 : 3; /**< Enable Control for LDO1, selecting either an FPS slot the channel powers-up and |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1063 | powers-down in or whether the channel is forced on or off. Bit 2:0. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1064 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1065 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1066 | 0b100 = Off irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1067 | 0b101 = same as 0b100 |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1068 | 0b110 = On irrespective of FPS |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1069 | 0b111 = same as 0b110 */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1070 | unsigned char ade_ldo1 : 1; /**< LDO1 Active-Discharge Enable. Bit 3. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1071 | 0 = The active discharge function is disabled. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1072 | 1 = The active discharge function is enabled. */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1073 | unsigned char ldo1_md : 1; /**< Operation mode of LDO1. Bit 4. |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1074 | 0 = Low Dropout Linear Regulator (LDO) Mode |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1075 | 1 = Load Switch (LSW) Mode */ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1076 | unsigned char : 3; /**< Bit 7:5.*/ |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1077 | } bits; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1078 | } reg_cnfg_ldo1_b_t; |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1079 | |
| metin.ozkan@analog.com | 0:788f63dcf0a0 | 1080 | #endif /* MAX77654_REGS_H_ */ |