Maxim Integrated
MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver
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MAX77643_2.h
00001 /******************************************************************************* 00002 * Copyright(C) Analog Devices Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files(the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Analog Devices Inc. 00023 * shall not be used except as stated in the Analog Devices Inc. 00024 * Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Analog Devices Inc.retains all ownership rights. 00030 ******************************************************************************* 00031 */ 00032 00033 #ifndef _MAX77643_2_H_ 00034 #define _MAX77643_2_H_ 00035 00036 #include "mbed.h" 00037 #include "MAX77643_2_regs.h" 00038 00039 #define MAX77643_2_NO_ERROR 0 00040 #define MAX77643_2_VALUE_NULL -1 00041 #define MAX77643_2_WRITE_DATA_FAILED -2 00042 #define MAX77643_2_READ_DATA_FAILED -3 00043 #define MAX77643_2_INVALID_DATA -4 00044 00045 #define MAX77643_2_I2C_ADDRESS 0x90 00046 00047 /** 00048 * @brief MAX77643_2 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 00049 * 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications 00050 * 00051 * @details The MAX77643_2/MAX77643_2 provide power supply solutions for low-power applications where size and efficiency 00052 * are critical. The MAX77643_2's SIMO and LDO output voltages are individually programmable through resistors. 00053 * 00054 * @code 00055 * @endcode 00056 */ 00057 00058 class MAX77643_2 00059 { 00060 private: 00061 I2C *i2c_handler; 00062 InterruptIn *irq_pin; // interrupt pin 00063 00064 /** 00065 * @brief Register Addresses 00066 * @details Enumerated MAX77643_2 register addresses 00067 */ 00068 typedef enum { 00069 /*Global*/ 00070 INT_GLBL0 = 0x00, // Interrupt Status 0 00071 INT_GLBL1 = 0x01, // Interrupt Status 1 00072 ERCFLAG = 0x02, // Flags 00073 STAT_GLBL = 0x03, // Global Status 00074 INTM_GLBL0 = 0x04, // Interrupt Mask 0 00075 INTM_GLBL1 = 0x05, // Interrupt Mask 1 00076 CNFG_GLBL0 = 0x06, // Configuration Global 0 00077 CNFG_GLBL1 = 0x07, // Configuration Global 1 00078 CNFG_GPIO0 = 0x08, // GPIO0 Configuration 00079 CNFG_GPIO1 = 0x09, // GPIO1 Configuration 00080 CID = 0x10, // Chip Identification Code 00081 CNFG_WDT = 0x17, // Configuration WatchDog Timer 00082 /*SBB*/ 00083 CNFG_SBB_TOP = 0x28, // SIMO Buck-Boost Configuration 00084 CNFG_SBB0_A = 0x29, // SIMO Buck-Boost 0 Configuration A 00085 CNFG_SBB0_B = 0x2A, // SIMO Buck-Boost 0 Configuration B 00086 CNFG_SBB1_A = 0x2B, // SIMO Buck-Boost 1 Configuration A 00087 CNFG_SBB1_B = 0x2C, // SIMO Buck-Boost 1 Configuration B 00088 CNFG_SBB2_A = 0x2D, // SIMO Buck-Boost 2 Configuration A 00089 CNFG_SBB2_B = 0x2E, // SIMO Buck-Boost 2 Configuration B 00090 CNFG_DVS_SBB0_A = 0x2F, // SIMO Buck-Boost 0 DVS Configuration A 00091 /*LDO*/ 00092 CNFG_LDO0_A = 0x38, // LDO0 Output Voltage 00093 CNFG_LDO0_B = 0x39 // LDO0 Output Voltage Configuration 00094 } reg_t; 00095 00096 void interrupt_handler(); 00097 00098 void (MAX77643_2::*funcptr)(void); 00099 00100 void post_interrupt_work(); 00101 00102 Thread *post_intr_work_thread; 00103 00104 struct handler { 00105 void (*func)(void *); 00106 void *cb; 00107 }; 00108 00109 handler *interrupt_handler_list; 00110 00111 public: 00112 /** 00113 * @brief MAX77643_2 constructor. 00114 */ 00115 MAX77643_2(I2C *i2c, PinName IRQPin = NC); 00116 00117 /** 00118 * @brief MAX77643_2 destructor. 00119 */ 00120 ~MAX77643_2(); 00121 00122 /** 00123 * @brief Function pointer type to interrupt handler function 00124 */ 00125 typedef void (*interrupt_handler_function)(void *); 00126 00127 /** 00128 * @brief Read from a register. 00129 * 00130 * @param[in] reg Address of a register to be written. 00131 * @param[out] value Pointer to save result value. 00132 * 00133 * @returns 0 on success, negative error code on failure. 00134 */ 00135 int read_register(uint8_t reg, uint8_t *value); 00136 00137 /** 00138 * @brief Write to a register. 00139 * 00140 * @param[in] reg Address of a register to be written. 00141 * @param[out] value Pointer of value to be written to register. 00142 * 00143 * @returns 0 on success, negative error code on failure. 00144 */ 00145 int write_register(uint8_t reg, const uint8_t *value); 00146 00147 /** 00148 * @brief Register Configuration. 00149 * All Interrupt Flags combined from INT_GLBL0 (0x00) and INT_GLBL1(0x01) 00150 * 00151 * @details 00152 * - Register : INT_GLBL0 (0x00) and INT_GLBL1(0x01) 00153 * - Bit Fields : 00154 * - Default : 0x0 00155 * - Description : Enumerated interrupts. 00156 */ 00157 typedef enum { 00158 INT_GLBL0_GPI0_F, 00159 INT_GLBL0_GPI0_R, 00160 INT_GLBL0_NEN_F, 00161 INT_GLBL0_NEN_R, 00162 INT_GLBL0_TJAL1_R, 00163 INT_GLBL0_TJAL2_R, 00164 INT_GLBL0_DOD_R, 00165 INT_GLBL0_RSVD, 00166 INT_GLBL1_GPI1_F, 00167 INT_GLBL1_GPI1_R, 00168 INT_GLBL1_SBB0_F, 00169 INT_GLBL1_SBB1_F, 00170 INT_GLBL1_SBB2_F, 00171 INT_GLBL1_LDO_F, 00172 INT_GLBL1_RSVD, 00173 INT_CHG_END 00174 } reg_bit_int_glbl_t; 00175 00176 /** 00177 * @brief Register Configuration 00178 * 00179 * @details 00180 * - Register : ERCFLAG (0x02) 00181 * - Bit Fields : [7:0] 00182 * - Default : 0x0 00183 * - Description : Event Recorder Flags. 00184 */ 00185 typedef enum { 00186 ERCFLAG_TOVLD, 00187 ERCFLAG_INOVLO, 00188 ERCFLAG_INUVLO, 00189 ERCFLAG_MRST_F, 00190 ERCFLAG_SFT_OFF_F, 00191 ERCFLAG_SFT_CRST_F, 00192 ERCFLAG_WDT_EXP_F, 00193 ERCFLAG_SBB_FAULT_F 00194 }reg_bit_ercflag_t; 00195 00196 /** 00197 * @brief Get bit field of ERCFLAG (0x02) register. 00198 * 00199 * @param[in] bit_field ERCFLAG register bit field to be written. 00200 * @param[out] flag Pointer to save result of ercglag bit states. 00201 * For individual bit 00202 * 0x0: ERCFLAG has not occurred, 00203 * 0x1: ERCFLAG has occurred. 00204 * 00205 * @return 0 on success, error code on failure. 00206 */ 00207 int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag); 00208 00209 /** 00210 * @brief Register Configuration 00211 * 00212 * @details 00213 * - Register : STAT_GLBL (0x03) 00214 * - Bit Fields : [7:0] 00215 * - Default : 0x0 00216 * - Description : Global Status. 00217 */ 00218 typedef enum { 00219 STAT_GLBL_STAT_IRQ, 00220 STAT_GLBL_STAT_EN, 00221 STAT_GLBL_TJAL1_S, 00222 STAT_GLBL_TJAL2_S, 00223 STAT_GLBL_DOD_S, 00224 STAT_GLBL_RSVD, 00225 STAT_GLBL_BOK, 00226 STAT_GLBL_DIDM 00227 }reg_bit_stat_glbl_t; 00228 00229 /** 00230 * @brief Get bit field of STAT_GLBL (0x03) register. 00231 * 00232 * @param[in] bit_field STAT_GLBL register bit field to be written. 00233 * @param[out] status Pointer to save result of Status Global bit state. 00234 * 00235 * @return 0 on success, error code on failure. 00236 */ 00237 int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status); 00238 00239 /** 00240 * @brief Register Configuration 00241 * 00242 * @details 00243 * - Register : INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05) 00244 * - Bit Fields : [7:0] 00245 * - Default : 0x0 00246 * - Description : All interrupt mask bits. 00247 */ 00248 typedef enum { 00249 INTM_GLBL0_GPI0_FM, 00250 INTM_GLBL0_GPI0_RM, 00251 INTM_GLBL0_nEN_FM, 00252 INTM_GLBL0_nEN_RM, 00253 INTM_GLBL0_TJAL1_RM, 00254 INTM_GLBL0_TJAL2_RM, 00255 INTM_GLBL0_DOD_RM, 00256 INTM_GLBL0_RSVD, 00257 INTM_GLBL1_GPI1_FM, 00258 INTM_GLBL1_GPI1_RM, 00259 INTM_GLBL1_SBB0_FM, 00260 INTM_GLBL1_SBB1_FM, 00261 INTM_GLBL1_SBB2_FM, 00262 INTM_GLBL1_LDO_M, 00263 INTM_GLBL1_RSVD, 00264 INTM_NUM_OF_BIT 00265 }reg_bit_int_mask_t; 00266 00267 /** 00268 * @brief Set bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register. 00269 * 00270 * @param[in] bit_field Register bit field to be set. 00271 * @param[out] maskBit 0x0: Interrupt is unmasked, 00272 * 0x1: Interrupt is masked. 00273 * 00274 * @return 0 on success, error code on failure. 00275 */ 00276 int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit); 00277 00278 /** 00279 * @brief Get bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register. 00280 * 00281 * @param[in] bit_field Register bit field to be written. 00282 * @param[out] maskBit 0x0: Interrupt is unmasked, 00283 * 0x1: Interrupt is masked. 00284 * 00285 * @return 0 on success, error code on failure. 00286 */ 00287 int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit); 00288 00289 /** 00290 * @brief Register Configuration 00291 * 00292 * @details 00293 * - Register : CNFG_GLBL0 (0x06) 00294 * - Bit Fields : [7:0] 00295 * - Default : 0x0 00296 * - Description : Event Recorder Flags. 00297 */ 00298 typedef enum { 00299 CNFG_GLBL0_SFT_CTRL, 00300 CNFG_GLBL0_DBEN_nEN, 00301 CNFG_GLBL0_nEN_MODE, 00302 CNFG_GLBL0_SBIA_LPM, 00303 CNFG_GLBL0_T_MRST, 00304 CNFG_GLBL0_PU_DIS 00305 }reg_bit_cnfg_glbl0_t; 00306 00307 /** 00308 * @brief Set CNFG_GLBL0 (0x06) register. 00309 * 00310 * @param[in] bit_field Register bit field to be written. 00311 * @param[in] config Register bit field to be written. 00312 * 00313 * @return 0 on success, error code on failure. 00314 */ 00315 int set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config); 00316 00317 /** 00318 * @brief Get CNFG_GLBL0 (0x06) register. 00319 * 00320 * @param[in] bit_field Register bit field to be written. 00321 * @param[out] config Pointer of value to be read. 00322 * 00323 * @return 0 on success, error code on failure. 00324 */ 00325 int get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config); 00326 00327 /** 00328 * @brief Register Configuration 00329 * 00330 * @details 00331 * - Register : CNFG_GLBL1 (0x07) 00332 * - Bit Fields : [7:0] 00333 * - Default : 0x0 00334 * - Description : Event Recorder Flags. 00335 */ 00336 typedef enum { 00337 CNFG_GLBL1_AUTO_WKT, 00338 CNFG_GLBL1_SBB_F_SHUTDN, 00339 CNFG_GLBL1_RSVD 00340 }reg_bit_cnfg_glbl1_t; 00341 00342 /** 00343 * @brief Set CNFG_GLBL1 (0x07) register. 00344 * 00345 * @param[in] bit_field Register bit field to be written. 00346 * @param[in] config Register bit field to be written. 00347 * 00348 * @return 0 on success, error code on failure. 00349 */ 00350 int set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config); 00351 00352 /** 00353 * @brief Get CNFG_GLBL1 (0x07) register. 00354 * 00355 * @param[in] bit_field Register bit field to be written. 00356 * @param[out] config Pointer of value to be read. 00357 * 00358 * @return 0 on success, error code on failure. 00359 */ 00360 int get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config); 00361 00362 /** 00363 * @brief Register Configuration 00364 * 00365 * @details 00366 * - Register : CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09) 00367 * - Bit Fields : [7:0] 00368 * - Default : 0x0 00369 * - Description : Event Recorder Flags. 00370 */ 00371 typedef enum { 00372 CNFG_GPIO_DIR, 00373 CNFG_GPIO_DI, 00374 CNFG_GPIO_DRV, 00375 CNFG_GPIO_DO, 00376 CNFG_GPIO_DBEN_GPI, 00377 CNFG_GPIO_ALT_GPIO, 00378 CNFG_GPIO_RSVD 00379 }reg_bit_cnfg_gpio_t; 00380 00381 /** 00382 * @brief Set either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09). 00383 * 00384 * @param[in] bit_field Register bit field to be written. 00385 * @param[in] channel Channel number: 0 or 1 00386 * @param[in] config Register bit field to be written. 00387 * 00388 * @return 0 on success, error code on failure. 00389 */ 00390 int set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config); 00391 00392 /** 00393 * @brief Get either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09). 00394 * 00395 * @param[in] bit_field Register bit field to be written. 00396 * @param[in] channel Channel number: 0 or 1 00397 * @param[out] config Pointer of value to be read. 00398 * 00399 * @return 0 on success, error code on failure. 00400 */ 00401 int get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config); 00402 00403 /** 00404 * @brief Get bit field of CID (0x10) register. 00405 * 00406 * @param[in] config Register bit field to be written 00407 * 00408 * @return CID on success, error code on failure. 00409 */ 00410 int get_cid(void); 00411 00412 /** 00413 * @brief Register Configuration 00414 * 00415 * @details 00416 * - Register : CNFG_WDT (0x17) 00417 * - Bit Fields : [7:0] 00418 * - Default : 0x0 00419 * - Description : Watchdog Timer Configuration. 00420 */ 00421 typedef enum { 00422 CNFG_WDT_WDT_LOCK, 00423 CNFG_WDT_WDT_EN, 00424 CNFG_WDT_WDT_CLR, 00425 CNFG_WDT_WDT_MODE, 00426 CNFG_WDT_WDT_PER, 00427 CNFG_WDT_RSVD 00428 }reg_bit_cnfg_wdt_t; 00429 00430 /** 00431 * @brief Set CNFG_WDT (0x17) register. 00432 * 00433 * @param[in] bit_field Register bit field to be written. 00434 * @param[in] config Field value to be written. 00435 * 00436 * @return 0 on success, error code on failure. 00437 */ 00438 int set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config); 00439 00440 /** 00441 * @brief Get CNFG_WDT (0x17) register. 00442 * 00443 * @param[in] bit_field Register bit field to be written. 00444 * @param[out] config Pointer of value to be read. 00445 * 00446 * @return 0 on success, error code on failure. 00447 */ 00448 int get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config); 00449 00450 /*SBB*/ 00451 00452 /** 00453 * @brief Register Configuration 00454 * 00455 * @details 00456 * - Register : CNFG_SBB_TOP (0x28) 00457 * - Bit Fields : [7:0] 00458 * - Default : 0x0 00459 * - Description : Watchdog Timer Configuration. 00460 */ 00461 typedef enum { 00462 CNFG_SBB_TOP_DRV_SBB, 00463 CNFG_SBB_TOP_DIS_LPM 00464 }reg_bit_cnfg_sbb_top_t; 00465 00466 /** 00467 * @brief Set CNFG_SBB_TOP (0x28) register. 00468 * 00469 * @param[in] bit_field Register bit field to be written. 00470 * @param[in] config Configuration value to be written. 00471 * 00472 * @return 0 on success, error code on failure. 00473 */ 00474 int set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config); 00475 00476 /** 00477 * @brief Get CNFG_SBB_TOP (0x28) register. 00478 * 00479 * @param[in] bit_field Register bit field to be written. 00480 * @param[out] config Configuration value to be read. 00481 * 00482 * @return 0 on success, error code on failure. 00483 */ 00484 int get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config); 00485 00486 /** 00487 * @brief Set SIMO Buck-Boost Channel x Target Output Voltage. 00488 * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D) 00489 * 00490 * @param[in] channel Channel number: 0, 1 or 2. 00491 * @param[in] voltV SIMO buck-boost channel x target output voltage field to be written. 00492 * SBBx = 500mV + 25mV x TV_SBBx[7:0] 00493 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00494 * 0.650V, 0.675V, 0.700V, ... 00495 * 5.425V, 5.450V, 5.475V, 5.500V. 00496 * 00497 * @return 0 on success, error code on failure. 00498 */ 00499 int set_tv_sbb(uint8_t channel, float voltV); 00500 00501 /** 00502 * @brief Get SIMO Buck-Boost Channel x Target Output Voltage. 00503 * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D) 00504 * 00505 * @param[in] channel Channel number: 0, 1 or 2. 00506 * @param[out] voltV SIMO buck-boost channel x target output voltage field to be read. 00507 * SBBx = 500mV + 25mV x TV_SBBx[7:0] 00508 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00509 * 0.650V, 0.675V, 0.700V, ... 00510 * 5.425V, 5.450V, 5.475V, 5.500V. 00511 * 00512 * @return 0 on success, error code on failure. 00513 */ 00514 int get_tv_sbb(uint8_t channel, float *voltV); 00515 00516 /** 00517 * @brief Register Configuration 00518 * 00519 * @details 00520 * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) 00521 * - Bit Fields : [7:6] 00522 * - Default : 0x0 00523 * - Description : Operation mode of SBB0, 1 or 2. 00524 */ 00525 typedef enum { 00526 OP_MODE_AUTOMATIC, 00527 OP_MODE_BUCK_MODE, 00528 OP_MODE_BOOST_MODE, 00529 OP_MODE_BUCK_BOOST_MODE 00530 }decode_op_mode_t; 00531 00532 /** 00533 * @brief Set Operation mode of SBBx. 00534 * 00535 * @param[in] channel Channel number: 0, 1 or 2. 00536 * @param[in] mode Operation mode of SBBx bit to be written. 00537 * 00538 * @return 0 on success, error code on failure. 00539 */ 00540 int set_op_mode(uint8_t channel, decode_op_mode_t mode); 00541 00542 /** 00543 * @brief Get Operation mode of SBBx. 00544 * 00545 * @param[in] channel Channel number: 0, 1 or 2. 00546 * @param[out] mode Operation mode of SBBx bit to be read. 00547 * 00548 * @return 0 on success, error code on failure. 00549 */ 00550 int get_op_mode(uint8_t channel, decode_op_mode_t *mode); 00551 00552 /** 00553 * @brief Register Configuration 00554 * 00555 * @details 00556 * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) 00557 * - Bit Fields : [5:4] 00558 * - Default : 0x0 00559 * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit. 00560 */ 00561 typedef enum { 00562 IP_SBB_AMP_1_000A, 00563 IP_SBB_AMP_0_750A, 00564 IP_SBB_AMP_0_500A, 00565 IP_SBB_AMP_0_333A 00566 }decode_ip_sbb_t; 00567 00568 /** 00569 * @brief Set SIMO Buck-Boost Channel x Peak Current Limit. 00570 * 00571 * @param[in] channel Channel number: 0, 1 or 2. 00572 * @param[in] ip_sbb SIMO buck-boost channel 2 peak current limit field to be written. 00573 * 00574 * @return 0 on success, error code on failure. 00575 */ 00576 int set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb); 00577 00578 /** 00579 * @brief Get SIMO Buck-Boost Channel x Peak Current Limit. 00580 * 00581 * @param[in] channel Channel number: 0, 1 or 2. 00582 * @param[out] ip_sbb SIMO buck-boost channel 2 peak current limit field to be read. 00583 * 00584 * @return 0 on success, error code on failure. 00585 */ 00586 int get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb); 00587 00588 /** 00589 * @brief Register Configuration 00590 * 00591 * @details 00592 * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) 00593 * - Bit Fields : [3] 00594 * - Default : 0x0 00595 * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Active-Discharge Enable. 00596 */ 00597 typedef enum { 00598 ADE_SBB_DISABLED, 00599 ADE_SBB_ENABLED 00600 }decode_ade_sbb_t; 00601 00602 /** 00603 * @brief Set SIMO Buck-Boost Channel x Active-Discharge Enable. 00604 * 00605 * @param[in] channel Channel number: 0, 1 or 2. 00606 * @param[in] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be written. 00607 * 00608 * @return 0 on success, error code on failure. 00609 */ 00610 int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb); 00611 00612 /** 00613 * @brief Get SIMO Buck-Boost Channel x Active-Discharge Enable. 00614 * 00615 * @param[in] channel Channel number: 0, 1 or 2. 00616 * @param[out] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be read. 00617 * 00618 * @return 0 on success, error code on failure. 00619 */ 00620 int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb); 00621 00622 /** 00623 * @brief Register Configuration 00624 * 00625 * @details 00626 * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) 00627 * - Bit Fields : [2:0] 00628 * - Default : 0x0 00629 * - Description : Enable Control for SIMO Buck-Boost Channel 0, 1 or 2. 00630 */ 00631 typedef enum { 00632 EN_SBB_FPS_SLOT_0, 00633 EN_SBB_FPS_SLOT_1, 00634 EN_SBB_FPS_SLOT_2, 00635 EN_SBB_FPS_SLOT_3, 00636 EN_SBB_OFF, 00637 EN_SBB_SAME_AS_0X04, 00638 EN_SBB_ON, 00639 EN_SBB_SAME_AS_0X06 00640 }decode_en_sbb_t; 00641 00642 /** 00643 * @brief Set Enable Control for SIMO Buck-Boost Channel x. 00644 * 00645 * @param[in] channel Channel number: 0, 1 or 2. 00646 * @param[in] en_sbb Enable control for SIMO buck-boost channel x field to be written. 00647 * 00648 * @return 0 on success, error code on failure. 00649 */ 00650 int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb); 00651 00652 /** 00653 * @brief Get Enable Control for SIMO Buck-Boost Channel x. 00654 * 00655 * @param[in] channel Channel number: 0, 1 or 2. 00656 * @param[out] en_sbb Enable control for SIMO buck-boost channel x field to be read. 00657 * 00658 * @return 0 on success, error code on failure. 00659 */ 00660 int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb); 00661 00662 /** 00663 * @brief Set SIMO Buck-Boost Channel 0 Target Output Voltage. 00664 * Bit 7:0 of CNFG_DVS_SBB0_A (0x2F). 00665 * 00666 * @param[in] voltV SIMO buck-boost channel 0 target output voltage field to be written. 00667 * SBBx = 500mV + 25mV x TV_SBBx[7:0] 00668 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00669 * 0.650V, 0.675V, 0.700V, ... 00670 * 5.425V, 5.450V, 5.475V, 5.500V. 00671 * 00672 * @return 0 on success, error code on failure. 00673 */ 00674 int set_tv_sbb_dvs(float voltV); 00675 00676 /** 00677 * @brief Get SIMO Buck-Boost Channel 0 Target Output Voltage. 00678 * Bit 7:0 of CNFG_DVS_SBB0_A (0x2F). 00679 * 00680 * @param[out] voltV SIMO buck-boost channel 0 target output voltage field to be read. 00681 * SBBx = 500mV + 25mV x TV_SBBx[7:0] 00682 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00683 * 0.650V, 0.675V, 0.700V, ... 00684 * 5.425V, 5.450V, 5.475V, 5.500V. 00685 * 00686 * @return 0 on success, error code on failure. 00687 */ 00688 int get_tv_sbb_dvs(float *voltV); 00689 00690 /*LDO*/ 00691 00692 /** 00693 * @brief Set LDO Output Channel x Target Output Voltage. Bit 6:0. 00694 * CNFG_LDO0_A (0x38) 00695 * 00696 * @param[in] voltV LDO Output Channel x target output voltage field to be read. 00697 * LDOx = 500mV + 25mV x TV_LDOx[6:0] 00698 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00699 * 0.650V, 0.675V, 0.700V, ... 00700 * 3.650, 3.675. 00701 * 00702 * When TV_LDO[7] = 0, TV_LDO[6:0] sets the 00703 * LDO's output voltage range from 0.5V to 3.675V. 00704 * When TV_LDO[7] = 1, TV_LDO[6:0] sets the 00705 * LDO's output voltage from 1.825V to 5V. 00706 * 00707 * @return 0 on success, error code on failure. 00708 */ 00709 int set_tv_ldo(float voltV); 00710 00711 /** 00712 * @brief Get LDO Output Channel x Target Output Voltage. Bit 6:0. 00713 * CNFG_LDO0_A (0x38) 00714 * 00715 * @param[out] voltV LDO Output Channel x target output voltage field to be read. 00716 * LDOx = 500mV + 25mV x TV_LDOx[6:0] 00717 * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 00718 * 0.650V, 0.675V, 0.700V, ... 00719 * 3.650, 3.675. 00720 * 00721 * When TV_LDO[7] = 0, TV_LDO[6:0] sets the 00722 * LDO's output voltage range from 0.5V to 3.675V. 00723 * When TV_LDO[7] = 1, TV_LDO[6:0] sets the 00724 * LDO's output voltage from 1.825V to 5V. 00725 * 00726 * @return 0 on success, error code on failure. 00727 */ 00728 int get_tv_ldo(float *voltV); 00729 00730 /** 00731 * @brief Register Configuration 00732 * 00733 * @details 00734 * - Register : CNFG_LDO0_A (0x38) 00735 * - Bit Fields : [7] 00736 * - Default : 0x0 00737 * - Description : SIMO Buck-Boost Channel 0 Peak Current Limit. 00738 */ 00739 typedef enum { 00740 TV_OFS_LDO_NO_OFFSET, 00741 TV_OFS_LDO_NO_1_325V 00742 }decode_tv_ofs_ldo_t; 00743 00744 /** 00745 * @brief Set LDO Output Channel 0 Target Output Voltage. Bit 7. 00746 * CNFG_LDO0_A (0x38) 00747 * 00748 * @param[in] offset LDO Output Channel 0 target output voltage offset field to be read. 00749 * 0b0 = No Offset 00750 * 0b1 = 1.325V Offset 00751 * 00752 * @return 0 on success, error code on failure. 00753 */ 00754 int set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset); 00755 00756 /** 00757 * @brief Get LDO Output Channel 0 Target Output Voltage. Bit 7. 00758 * CNFG_LDO0_A (0x38) 00759 * 00760 * @param[out] offset LDO Output Channel 0 target output voltage offset field to be read. 00761 * 0b0 = No Offset 00762 * 0b1 = 1.325V Offset 00763 * 00764 * @return 0 on success, error code on failure. 00765 */ 00766 int get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset); 00767 00768 /** 00769 * @brief Register Configuration 00770 * 00771 * @details 00772 * - Register : CNFG_LDO0_B (0x39) 00773 * - Bit Fields : [2:0] 00774 * - Default : 0x0 00775 * - Description : Enable Control for LDO 0. 00776 */ 00777 typedef enum { 00778 EN_LDO_FPS_SLOT_0, 00779 EN_LDO_FPS_SLOT_1, 00780 EN_LDO_FPS_SLOT_2, 00781 EN_LDO_FPS_SLOT_3, 00782 EN_LDO_OFF, 00783 EN_LDO_SAME_AS_0X04, 00784 EN_LDO_ON, 00785 EN_LDO_SAME_AS_0X06 00786 }decode_en_ldo_t; 00787 00788 /** 00789 * @brief Set Enable Control for LDO Channel 0. 00790 * 00791 * @param[in] en_ldo Enable control for LDO channel 0 field to be written. 00792 * 00793 * @return 0 on success, error code on failure. 00794 */ 00795 int set_en_ldo(decode_en_ldo_t en_ldo); 00796 00797 /** 00798 * @brief Get Enable Control for LDO Channel 0. 00799 * 00800 * @param[out] en_ldo Enable control for LDO channel x field to be read. 00801 * 00802 * @return 0 on success, error code on failure. 00803 */ 00804 int get_en_ldo(decode_en_ldo_t *en_ldo); 00805 00806 /** 00807 * @brief Register Configuration 00808 * 00809 * @details 00810 * - Register : CNFG_LDO0_B (0x39) 00811 * - Bit Fields : [3] 00812 * - Default : 0x0 00813 * - Description : LDO Channel 0 Active-Discharge Enable. 00814 */ 00815 typedef enum { 00816 ADE_LDO_DISABLED, 00817 ADE_LDO_ENABLED 00818 }decode_ade_ldo_t; 00819 00820 /** 00821 * @brief Set LDO Channel 0 Active-Discharge Enable. 00822 * 00823 * @param[in] ade_ldo LDO channel 0 active-discharge enable bit to be written. 00824 * 00825 * @return 0 on success, error code on failure. 00826 */ 00827 int set_ade_ldo(decode_ade_ldo_t ade_ldo); 00828 00829 /** 00830 * @brief Get LDO Channel 0 Active-Discharge Enable. 00831 * 00832 * @param[out] ade_ldo LDO channel 0 active-discharge enable bit to be read. 00833 * 00834 * @return 0 on success, error code on failure. 00835 */ 00836 int get_ade_ldo(decode_ade_ldo_t *ade_ldo); 00837 00838 /** 00839 * @brief Register Configuration 00840 * 00841 * @details 00842 * - Register : CNFG_LDO0_B (0x39) 00843 * - Bit Fields : [4] 00844 * - Default : 0x0 00845 * - Description : Operation mode of LDO 0. 00846 */ 00847 typedef enum { 00848 LDO_MD_LDO_MODE, 00849 LDO_MD_LSW_MODE 00850 }decode_ldo_md_t; 00851 00852 /** 00853 * @brief Set Operation mode of LDO0. 00854 * 00855 * @param[in] mode Operation mode of LDO0 bit to be written. 00856 * 00857 * @return 0 on success, error code on failure. 00858 */ 00859 int set_ldo_md(decode_ldo_md_t mode); 00860 00861 /** 00862 * @brief Get Operation mode of LDO0. 00863 * 00864 * @param[out] mode Operation mode of LDO0 bit to be read. 00865 * 00866 * @return 0 on success, error code on failure. 00867 */ 00868 int get_ldo_md(decode_ldo_md_t *mode); 00869 00870 /** 00871 * @brief Disable all interrupts 00872 * 00873 * @return 0 on success, error code on failure 00874 */ 00875 int irq_disable_all(); 00876 00877 /** 00878 * @brief Set Interrupt Handler for a Specific Interrupt ID. 00879 * 00880 * @param[in] id reg_bit_reg_bit_int_glbl_t id, one of INTR_ID_*. 00881 * @param[in] func Interrupt handler function. 00882 * @param[in] cb Interrupt handler data. 00883 */ 00884 void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb); 00885 }; 00886 #endif
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