Maxim Integrated
MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver
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MAX77643_2.cpp
00001 /******************************************************************************* 00002 * Copyright(C) Analog Devices Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files(the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Analog Devices Inc. 00023 * shall not be used except as stated in the Analog Devices Inc. 00024 * Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Analog Devices Inc.retains all ownership rights. 00030 ******************************************************************************* 00031 */ 00032 00033 #include <Thread.h> 00034 #include "MAX77643_2.h" 00035 #include <math.h> 00036 00037 #define POST_INTR_WORK_SIGNAL_ID 0x1 00038 #define TO_UINT8 0xFF 00039 #define TO_UINT16 0xFFFF 00040 00041 MAX77643_2::MAX77643_2(I2C *i2c, PinName IRQPin) 00042 { 00043 if (i2c == NULL) 00044 return; 00045 00046 i2c_handler = i2c; 00047 interrupt_handler_list = new handler[INTM_NUM_OF_BIT] {}; 00048 00049 if (IRQPin != NC) { 00050 irq_disable_all(); 00051 post_intr_work_thread = new Thread(); 00052 post_intr_work_thread->start(Callback<void()>(this, &MAX77643_2::post_interrupt_work)); 00053 00054 this->irq_pin = new InterruptIn(IRQPin); 00055 this->irq_pin->fall(Callback<void()>(this, &MAX77643_2::interrupt_handler)); 00056 this->irq_pin->enable_irq(); 00057 } else { 00058 this->irq_pin = NULL; 00059 } 00060 } 00061 00062 MAX77643_2::~MAX77643_2() 00063 { 00064 if (post_intr_work_thread) 00065 delete post_intr_work_thread; 00066 00067 if (irq_pin) 00068 delete irq_pin; 00069 00070 if (interrupt_handler_list) 00071 delete [] interrupt_handler_list; 00072 } 00073 00074 int MAX77643_2::read_register(uint8_t reg, uint8_t *value) 00075 { 00076 int rtn_val; 00077 00078 if (value == NULL) 00079 return MAX77643_2_VALUE_NULL; 00080 00081 rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)®, 1, true); 00082 if (rtn_val != 0) 00083 return MAX77643_2_WRITE_DATA_FAILED; 00084 rtn_val = i2c_handler->read(MAX77643_2_I2C_ADDRESS, (char *) value, 1, false); 00085 if (rtn_val < 0) 00086 return MAX77643_2_READ_DATA_FAILED; 00087 00088 return MAX77643_2_NO_ERROR; 00089 } 00090 00091 int MAX77643_2::write_register(uint8_t reg, const uint8_t *value) 00092 { 00093 int rtn_val; 00094 unsigned char local_data[2]; 00095 00096 if (value == NULL) 00097 return MAX77643_2_VALUE_NULL; 00098 00099 local_data[0] = reg; 00100 00101 memcpy(&local_data[1], value, 1); 00102 00103 rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)local_data, sizeof(local_data)); 00104 if (rtn_val != MAX77643_2_NO_ERROR) 00105 return MAX77643_2_WRITE_DATA_FAILED; 00106 00107 return MAX77643_2_NO_ERROR; 00108 } 00109 00110 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \ 00111 int ret_val; \ 00112 ret_val = read_register(address, (uint8_t *)&(reg_name)); \ 00113 if (ret_val) { \ 00114 return ret_val; \ 00115 } \ 00116 bit_field_name = value; \ 00117 ret_val = write_register(address, (uint8_t *)&(reg_name)); \ 00118 if (ret_val) { \ 00119 return ret_val; \ 00120 } 00121 00122 int MAX77643_2::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag) 00123 { 00124 int ret; 00125 reg_ercflag_t reg_ercflag = {0}; 00126 00127 ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag)); 00128 if (ret != MAX77643_2_NO_ERROR) return ret; 00129 00130 switch (bit_field) 00131 { 00132 case ERCFLAG_TOVLD: 00133 *flag = (uint8_t)reg_ercflag.bits.tovld; 00134 break; 00135 case ERCFLAG_INOVLO: 00136 *flag = (uint8_t)reg_ercflag.bits.inovlo; 00137 break; 00138 case ERCFLAG_INUVLO: 00139 *flag = (uint8_t)reg_ercflag.bits.inuvlo; 00140 break; 00141 case ERCFLAG_MRST_F: 00142 *flag = (uint8_t)reg_ercflag.bits.mrst_f; 00143 break; 00144 case ERCFLAG_SFT_OFF_F: 00145 *flag = (uint8_t)reg_ercflag.bits.sft_off_f; 00146 break; 00147 case ERCFLAG_SFT_CRST_F: 00148 *flag = (uint8_t)reg_ercflag.bits.sft_crst_f; 00149 break; 00150 case ERCFLAG_WDT_EXP_F: 00151 *flag = (uint8_t)reg_ercflag.bits.wdt_exp_f; 00152 break; 00153 case ERCFLAG_SBB_FAULT_F: 00154 *flag = (uint8_t)reg_ercflag.bits.sbb_fault_f; 00155 break; 00156 default: 00157 ret = MAX77643_2_INVALID_DATA; 00158 break; 00159 } 00160 00161 return ret; 00162 } 00163 00164 int MAX77643_2::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status) 00165 { 00166 int ret; 00167 reg_stat_glbl_t reg_stat_glbl = {0}; 00168 00169 ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl)); 00170 if (ret != MAX77643_2_NO_ERROR) return ret; 00171 00172 switch (bit_field) 00173 { 00174 case STAT_GLBL_STAT_IRQ: 00175 *status = (uint8_t)reg_stat_glbl.bits.stat_irq; 00176 break; 00177 case STAT_GLBL_STAT_EN: 00178 *status = (uint8_t)reg_stat_glbl.bits.stat_en; 00179 break; 00180 case STAT_GLBL_TJAL1_S: 00181 *status = (uint8_t)reg_stat_glbl.bits.tjal1_s; 00182 break; 00183 case STAT_GLBL_TJAL2_S: 00184 *status = (uint8_t)reg_stat_glbl.bits.tjal2_s; 00185 break; 00186 case STAT_GLBL_DOD_S: 00187 *status = (uint8_t)reg_stat_glbl.bits.dod_s; 00188 break; 00189 case STAT_GLBL_BOK: 00190 *status = (uint8_t)reg_stat_glbl.bits.bok; 00191 break; 00192 case STAT_GLBL_DIDM: 00193 *status = (uint8_t)reg_stat_glbl.bits.didm; 00194 break; 00195 default: 00196 ret = MAX77643_2_INVALID_DATA; 00197 break; 00198 } 00199 00200 return ret; 00201 } 00202 00203 int MAX77643_2::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit) 00204 { 00205 int ret; 00206 uint8_t reg_addr = 0; 00207 reg_intm_glbl0_t reg_intm_glbl0 = {0}; 00208 reg_intm_glbl1_t reg_intm_glbl1 = {0}; 00209 00210 //INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05) 00211 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04; 00212 00213 if (reg_addr == INTM_GLBL0) 00214 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00215 else if (reg_addr == INTM_GLBL1) 00216 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00217 else 00218 return MAX77643_2_INVALID_DATA; 00219 00220 if (ret != MAX77643_2_NO_ERROR) return ret; 00221 00222 switch (bit_field) 00223 { 00224 case INTM_GLBL0_GPI0_FM: 00225 reg_intm_glbl0.bits.gpi0_fm = maskBit; 00226 break; 00227 case INTM_GLBL0_GPI0_RM: 00228 reg_intm_glbl0.bits.gpi0_rm = maskBit; 00229 break; 00230 case INTM_GLBL0_nEN_FM: 00231 reg_intm_glbl0.bits.nen_fm = maskBit; 00232 break; 00233 case INTM_GLBL0_nEN_RM: 00234 reg_intm_glbl0.bits.nen_rm = maskBit; 00235 break; 00236 case INTM_GLBL0_TJAL1_RM: 00237 reg_intm_glbl0.bits.tjal1_rm = maskBit; 00238 break; 00239 case INTM_GLBL0_TJAL2_RM: 00240 reg_intm_glbl0.bits.tjal2_rm = maskBit; 00241 break; 00242 case INTM_GLBL0_DOD_RM: 00243 reg_intm_glbl0.bits.dod_rm = maskBit; 00244 break; 00245 case INTM_GLBL1_GPI1_FM: 00246 reg_intm_glbl1.bits.gpi1_fm = maskBit; 00247 break; 00248 case INTM_GLBL1_GPI1_RM: 00249 reg_intm_glbl1.bits.gpi1_rm = maskBit; 00250 break; 00251 case INTM_GLBL1_SBB0_FM: 00252 reg_intm_glbl1.bits.sbb0_fm = maskBit; 00253 break; 00254 case INTM_GLBL1_SBB1_FM: 00255 reg_intm_glbl1.bits.sbb1_fm = maskBit; 00256 break; 00257 case INTM_GLBL1_SBB2_FM: 00258 reg_intm_glbl1.bits.sbb2_fm = maskBit; 00259 break; 00260 case INTM_GLBL1_LDO_M: 00261 reg_intm_glbl1.bits.ldo_m = maskBit; 00262 break; 00263 default: 00264 return MAX77643_2_INVALID_DATA; 00265 break; 00266 } 00267 00268 if (reg_addr == INTM_GLBL0) 00269 return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00270 else if (reg_addr == INTM_GLBL1) 00271 return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00272 else 00273 return MAX77643_2_INVALID_DATA; 00274 } 00275 00276 int MAX77643_2::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit) 00277 { 00278 int ret; 00279 uint8_t reg_addr = 0; 00280 reg_intm_glbl0_t reg_intm_glbl0 = {0}; 00281 reg_intm_glbl1_t reg_intm_glbl1 = {0}; 00282 00283 //INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05) 00284 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04; 00285 00286 if (reg_addr == INTM_GLBL0) 00287 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00288 else if (reg_addr == INTM_GLBL1) 00289 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00290 else 00291 return MAX77643_2_INVALID_DATA; 00292 00293 if (ret != MAX77643_2_NO_ERROR) return ret; 00294 00295 switch (bit_field) 00296 { 00297 case INTM_GLBL0_GPI0_FM: 00298 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm; 00299 break; 00300 case INTM_GLBL0_GPI0_RM: 00301 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm; 00302 break; 00303 case INTM_GLBL0_nEN_FM: 00304 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm; 00305 break; 00306 case INTM_GLBL0_nEN_RM: 00307 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm; 00308 break; 00309 case INTM_GLBL0_TJAL1_RM: 00310 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm; 00311 break; 00312 case INTM_GLBL0_TJAL2_RM: 00313 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm; 00314 break; 00315 case INTM_GLBL0_DOD_RM: 00316 *maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm; 00317 break; 00318 case INTM_GLBL1_GPI1_FM: 00319 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm; 00320 break; 00321 case INTM_GLBL1_GPI1_RM: 00322 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm; 00323 break; 00324 case INTM_GLBL1_SBB0_FM: 00325 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb0_fm; 00326 break; 00327 case INTM_GLBL1_SBB1_FM: 00328 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb1_fm; 00329 break; 00330 case INTM_GLBL1_SBB2_FM: 00331 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb2_fm; 00332 break; 00333 case INTM_GLBL1_LDO_M: 00334 *maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m; 00335 break; 00336 default: 00337 return MAX77643_2_INVALID_DATA; 00338 break; 00339 } 00340 00341 return MAX77643_2_NO_ERROR; 00342 } 00343 00344 int MAX77643_2::set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config) 00345 { 00346 int ret; 00347 reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0}; 00348 00349 ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0)); 00350 if (ret != MAX77643_2_NO_ERROR) return ret; 00351 00352 switch (bit_field) 00353 { 00354 case CNFG_GLBL0_SFT_CTRL: 00355 reg_cnfg_glbl0.bits.sft_ctrl = config; 00356 break; 00357 case CNFG_GLBL0_DBEN_nEN: 00358 reg_cnfg_glbl0.bits.dben_nen = config; 00359 break; 00360 case CNFG_GLBL0_nEN_MODE: 00361 reg_cnfg_glbl0.bits.nen_mode = config; 00362 break; 00363 case CNFG_GLBL0_SBIA_LPM: 00364 reg_cnfg_glbl0.bits.sbia_lpm = config; 00365 break; 00366 case CNFG_GLBL0_T_MRST: 00367 reg_cnfg_glbl0.bits.t_mrst = config; 00368 break; 00369 case CNFG_GLBL0_PU_DIS: 00370 reg_cnfg_glbl0.bits.pu_dis = config; 00371 break; 00372 default: 00373 return MAX77643_2_INVALID_DATA; 00374 break; 00375 } 00376 00377 return write_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0)); 00378 } 00379 00380 int MAX77643_2::get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config) 00381 { 00382 int ret; 00383 reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0}; 00384 00385 ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0)); 00386 if (ret != MAX77643_2_NO_ERROR) return ret; 00387 00388 switch (bit_field) 00389 { 00390 case CNFG_GLBL0_SFT_CTRL: 00391 *config = (uint8_t)reg_cnfg_glbl0.bits.sft_ctrl; 00392 break; 00393 case CNFG_GLBL0_DBEN_nEN: 00394 *config = (uint8_t)reg_cnfg_glbl0.bits.dben_nen; 00395 break; 00396 case CNFG_GLBL0_nEN_MODE: 00397 *config = (uint8_t)reg_cnfg_glbl0.bits.nen_mode; 00398 break; 00399 case CNFG_GLBL0_SBIA_LPM: 00400 *config = (uint8_t)reg_cnfg_glbl0.bits.sbia_lpm; 00401 break; 00402 case CNFG_GLBL0_T_MRST: 00403 *config = (uint8_t)reg_cnfg_glbl0.bits.t_mrst; 00404 break; 00405 case CNFG_GLBL0_PU_DIS: 00406 *config = (uint8_t)reg_cnfg_glbl0.bits.pu_dis; 00407 break; 00408 default: 00409 ret = MAX77643_2_INVALID_DATA; 00410 break; 00411 } 00412 00413 return ret; 00414 } 00415 00416 int MAX77643_2::set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config) 00417 { 00418 int ret; 00419 reg_cnfg_glbl1_t reg_cnfg_glbl1; 00420 00421 ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1)); 00422 if (ret != MAX77643_2_NO_ERROR) return ret; 00423 00424 switch (bit_field) 00425 { 00426 case CNFG_GLBL1_AUTO_WKT: 00427 reg_cnfg_glbl1.bits.auto_wkt = config; 00428 break; 00429 case CNFG_GLBL1_SBB_F_SHUTDN: 00430 reg_cnfg_glbl1.bits.sbb_f_shutdn = config; 00431 break; 00432 default: 00433 return MAX77643_2_INVALID_DATA; 00434 break; 00435 } 00436 00437 return write_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1)); 00438 } 00439 00440 int MAX77643_2::get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config) 00441 { 00442 int ret; 00443 reg_cnfg_glbl1_t reg_cnfg_glbl1 = {0}; 00444 00445 ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1)); 00446 if (ret != MAX77643_2_NO_ERROR) return ret; 00447 00448 switch (bit_field) 00449 { 00450 case CNFG_GLBL1_AUTO_WKT: 00451 *config = (uint8_t)reg_cnfg_glbl1.bits.auto_wkt; 00452 break; 00453 case CNFG_GLBL1_SBB_F_SHUTDN: 00454 *config = (uint8_t)reg_cnfg_glbl1.bits.sbb_f_shutdn; 00455 break; 00456 default: 00457 ret = MAX77643_2_INVALID_DATA; 00458 break; 00459 } 00460 00461 return ret; 00462 } 00463 00464 int MAX77643_2::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config) 00465 { 00466 int ret; 00467 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; 00468 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; 00469 00470 if (channel == 0) 00471 { 00472 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00473 if (ret != MAX77643_2_NO_ERROR) return ret; 00474 00475 switch (bit_field) 00476 { 00477 case CNFG_GPIO_DIR: 00478 reg_cnfg_gpio0.bits.gpo_dir = config; 00479 break; 00480 case CNFG_GPIO_DI: 00481 reg_cnfg_gpio0.bits.gpo_di = config; 00482 break; 00483 case CNFG_GPIO_DRV: 00484 reg_cnfg_gpio0.bits.gpo_drv = config; 00485 break; 00486 case CNFG_GPIO_DO: 00487 reg_cnfg_gpio0.bits.gpo_do = config; 00488 break; 00489 case CNFG_GPIO_DBEN_GPI: 00490 reg_cnfg_gpio0.bits.dben_gpi = config; 00491 break; 00492 case CNFG_GPIO_ALT_GPIO: 00493 reg_cnfg_gpio0.bits.alt_gpio = config; 00494 break; 00495 default: 00496 return MAX77643_2_INVALID_DATA; 00497 break; 00498 } 00499 00500 return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00501 } 00502 else if (channel == 1) 00503 { 00504 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00505 if (ret != MAX77643_2_NO_ERROR) return ret; 00506 00507 switch (bit_field) 00508 { 00509 case CNFG_GPIO_DIR: 00510 reg_cnfg_gpio1.bits.gpo_dir = config; 00511 break; 00512 case CNFG_GPIO_DI: 00513 reg_cnfg_gpio1.bits.gpo_di = config; 00514 break; 00515 case CNFG_GPIO_DRV: 00516 reg_cnfg_gpio1.bits.gpo_drv = config; 00517 break; 00518 case CNFG_GPIO_DO: 00519 reg_cnfg_gpio1.bits.gpo_do = config; 00520 break; 00521 case CNFG_GPIO_DBEN_GPI: 00522 reg_cnfg_gpio1.bits.dben_gpi = config; 00523 break; 00524 case CNFG_GPIO_ALT_GPIO: 00525 reg_cnfg_gpio1.bits.alt_gpio = config; 00526 break; 00527 default: 00528 return MAX77643_2_INVALID_DATA; 00529 break; 00530 } 00531 00532 return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00533 } 00534 else { 00535 return MAX77643_2_INVALID_DATA; 00536 } 00537 } 00538 00539 int MAX77643_2::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config) 00540 { 00541 int ret; 00542 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; 00543 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; 00544 00545 if (channel == 0) 00546 { 00547 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00548 if (ret != MAX77643_2_NO_ERROR) return ret; 00549 00550 switch (bit_field) 00551 { 00552 case CNFG_GPIO_DIR: 00553 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir; 00554 break; 00555 case CNFG_GPIO_DI: 00556 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di; 00557 break; 00558 case CNFG_GPIO_DRV: 00559 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv; 00560 break; 00561 case CNFG_GPIO_DO: 00562 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do; 00563 break; 00564 case CNFG_GPIO_DBEN_GPI: 00565 *config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi; 00566 break; 00567 case CNFG_GPIO_ALT_GPIO: 00568 *config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio; 00569 break; 00570 default: 00571 return MAX77643_2_INVALID_DATA; 00572 break; 00573 } 00574 } 00575 else if (channel == 1) 00576 { 00577 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00578 if (ret != MAX77643_2_NO_ERROR) return ret; 00579 00580 switch (bit_field) 00581 { 00582 case CNFG_GPIO_DIR: 00583 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir; 00584 break; 00585 case CNFG_GPIO_DI: 00586 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di; 00587 break; 00588 case CNFG_GPIO_DRV: 00589 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv; 00590 break; 00591 case CNFG_GPIO_DO: 00592 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do; 00593 break; 00594 case CNFG_GPIO_DBEN_GPI: 00595 *config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi; 00596 break; 00597 case CNFG_GPIO_ALT_GPIO: 00598 *config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio; 00599 break; 00600 default: 00601 return MAX77643_2_INVALID_DATA; 00602 break; 00603 } 00604 } 00605 else { 00606 return MAX77643_2_INVALID_DATA; 00607 } 00608 00609 return ret; 00610 } 00611 00612 int MAX77643_2::get_cid(void) { 00613 char rbuf[1] = {0}; 00614 int ret; 00615 00616 ret = read_register(CID, (uint8_t *)&(rbuf)); 00617 if (ret != MAX77643_2_NO_ERROR) return ret; 00618 00619 return *rbuf; 00620 } 00621 00622 int MAX77643_2::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config) 00623 { 00624 int ret; 00625 reg_cnfg_wdt_t reg_cnfg_wdt = {0}; 00626 00627 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00628 if (ret != MAX77643_2_NO_ERROR) return ret; 00629 00630 switch (bit_field) 00631 { 00632 case CNFG_WDT_WDT_LOCK: 00633 reg_cnfg_wdt.bits.wdt_lock = config; 00634 break; 00635 case CNFG_WDT_WDT_EN: 00636 reg_cnfg_wdt.bits.wdt_en = config; 00637 break; 00638 case CNFG_WDT_WDT_CLR: 00639 reg_cnfg_wdt.bits.wdt_clr = config; 00640 break; 00641 case CNFG_WDT_WDT_MODE: 00642 reg_cnfg_wdt.bits.wdt_mode = config; 00643 break; 00644 case CNFG_WDT_WDT_PER: 00645 reg_cnfg_wdt.bits.wdt_per = config; 00646 break; 00647 default: 00648 return MAX77643_2_INVALID_DATA; 00649 break; 00650 } 00651 00652 return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00653 } 00654 00655 int MAX77643_2::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config) 00656 { 00657 int ret; 00658 reg_cnfg_wdt_t reg_cnfg_wdt = {0}; 00659 00660 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00661 if (ret != MAX77643_2_NO_ERROR) return ret; 00662 00663 switch (bit_field) 00664 { 00665 case CNFG_WDT_WDT_LOCK: 00666 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock; 00667 break; 00668 case CNFG_WDT_WDT_EN: 00669 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_en; 00670 break; 00671 case CNFG_WDT_WDT_CLR: 00672 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr; 00673 break; 00674 case CNFG_WDT_WDT_MODE: 00675 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode; 00676 break; 00677 case CNFG_WDT_WDT_PER: 00678 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_per; 00679 break; 00680 default: 00681 return MAX77643_2_INVALID_DATA; 00682 break; 00683 } 00684 00685 return MAX77643_2_NO_ERROR; 00686 } 00687 00688 int MAX77643_2::set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config) 00689 { 00690 int ret; 00691 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 00692 00693 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); 00694 if (ret != MAX77643_2_NO_ERROR) return ret; 00695 00696 switch (bit_field) 00697 { 00698 case CNFG_SBB_TOP_DRV_SBB: 00699 reg_cnfg_sbb_top.bits.drv_sbb = config; 00700 break; 00701 case CNFG_SBB_TOP_DIS_LPM: 00702 reg_cnfg_sbb_top.bits.dis_lpm = config; 00703 break; 00704 default: 00705 return MAX77643_2_INVALID_DATA; 00706 break; 00707 } 00708 00709 return write_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); 00710 } 00711 00712 int MAX77643_2::get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config) 00713 { 00714 int ret; 00715 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 00716 00717 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); 00718 if (ret != MAX77643_2_NO_ERROR) return ret; 00719 00720 switch (bit_field) 00721 { 00722 case CNFG_SBB_TOP_DRV_SBB: 00723 *config = (uint8_t)reg_cnfg_sbb_top.bits.drv_sbb; 00724 break; 00725 case CNFG_SBB_TOP_DIS_LPM: 00726 *config = (uint8_t)reg_cnfg_sbb_top.bits.dis_lpm; 00727 break; 00728 default: 00729 return MAX77643_2_INVALID_DATA; 00730 break; 00731 } 00732 00733 return MAX77643_2_NO_ERROR; 00734 } 00735 00736 int MAX77643_2::set_tv_sbb(uint8_t channel, float voltV) 00737 { 00738 uint8_t value; 00739 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; 00740 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; 00741 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; 00742 float voltmV = voltV * 1000; 00743 00744 if (voltmV < 500) voltmV = 500; 00745 else if (voltmV > 5500) voltmV = 5500; 00746 00747 value = (voltmV - 500) / 25; 00748 00749 if (channel == 0) { 00750 SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value); 00751 } 00752 else if (channel == 1) { 00753 SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value); 00754 } 00755 else if (channel == 2) { 00756 SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value); 00757 } 00758 else { 00759 return MAX77643_2_INVALID_DATA; 00760 } 00761 00762 return MAX77643_2_NO_ERROR; 00763 } 00764 00765 int MAX77643_2::get_tv_sbb(uint8_t channel, float *voltV) 00766 { 00767 int ret; 00768 uint8_t bit_value; 00769 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; 00770 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; 00771 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; 00772 00773 if (channel == 0) { 00774 ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a)); 00775 if (ret != MAX77643_2_NO_ERROR) return ret; 00776 00777 bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0; 00778 } 00779 else if (channel == 1) { 00780 ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a)); 00781 if (ret != MAX77643_2_NO_ERROR) return ret; 00782 00783 bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1; 00784 } 00785 else if (channel == 2) { 00786 ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a)); 00787 if (ret != MAX77643_2_NO_ERROR) return ret; 00788 00789 bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2; 00790 } 00791 else return MAX77643_2_INVALID_DATA; 00792 00793 if (bit_value > 200) bit_value = 200; 00794 *voltV = (bit_value * 0.025f) + 0.5f; 00795 00796 return MAX77643_2_NO_ERROR; 00797 } 00798 00799 int MAX77643_2::set_op_mode(uint8_t channel, decode_op_mode_t mode) 00800 { 00801 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00802 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00803 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00804 00805 if (channel == 0) { 00806 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode0, mode); 00807 } 00808 else if (channel == 1) { 00809 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode1, mode); 00810 } 00811 else if (channel == 2) { 00812 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode2, mode); 00813 } 00814 else { 00815 return MAX77643_2_INVALID_DATA; 00816 } 00817 00818 return MAX77643_2_NO_ERROR; 00819 } 00820 00821 int MAX77643_2::get_op_mode(uint8_t channel, decode_op_mode_t *mode) 00822 { 00823 int ret; 00824 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00825 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00826 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00827 00828 if (channel == 0) { 00829 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 00830 if (ret != MAX77643_2_NO_ERROR) return ret; 00831 00832 *mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode0; 00833 } 00834 else if (channel == 1) { 00835 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 00836 if (ret != MAX77643_2_NO_ERROR) return ret; 00837 00838 *mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode1; 00839 } 00840 else if (channel == 2) { 00841 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 00842 if (ret != MAX77643_2_NO_ERROR) return ret; 00843 00844 *mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode2; 00845 } 00846 else { 00847 return MAX77643_2_INVALID_DATA; 00848 } 00849 00850 return MAX77643_2_NO_ERROR; 00851 } 00852 00853 int MAX77643_2::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb) 00854 { 00855 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00856 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00857 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00858 00859 if (channel == 0) { 00860 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ip_sbb0, ip_sbb); 00861 } 00862 else if (channel == 1) { 00863 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ip_sbb1, ip_sbb); 00864 } 00865 else if (channel == 2) { 00866 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ip_sbb2, ip_sbb); 00867 } 00868 else { 00869 return MAX77643_2_INVALID_DATA; 00870 } 00871 00872 return MAX77643_2_NO_ERROR; 00873 } 00874 00875 int MAX77643_2::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb) 00876 { 00877 int ret; 00878 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00879 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00880 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00881 00882 if (channel == 0) { 00883 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 00884 if (ret != MAX77643_2_NO_ERROR) return ret; 00885 00886 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb0_b.bits.ip_sbb0; 00887 } 00888 else if (channel == 1) { 00889 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 00890 if (ret != MAX77643_2_NO_ERROR) return ret; 00891 00892 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb1_b.bits.ip_sbb1; 00893 } 00894 else if (channel == 2) { 00895 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 00896 if (ret != MAX77643_2_NO_ERROR) return ret; 00897 00898 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb2_b.bits.ip_sbb2; 00899 } 00900 else { 00901 return MAX77643_2_INVALID_DATA; 00902 } 00903 00904 return MAX77643_2_NO_ERROR; 00905 } 00906 00907 int MAX77643_2::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb) 00908 { 00909 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00910 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00911 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00912 00913 if (channel == 0) { 00914 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb); 00915 } 00916 else if (channel == 1) { 00917 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb); 00918 } 00919 else if (channel == 2) { 00920 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb); 00921 } 00922 else { 00923 return MAX77643_2_INVALID_DATA; 00924 } 00925 00926 return MAX77643_2_NO_ERROR; 00927 } 00928 00929 int MAX77643_2::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb) 00930 { 00931 int ret; 00932 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00933 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00934 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00935 00936 if (channel == 0) { 00937 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 00938 if (ret != MAX77643_2_NO_ERROR) return ret; 00939 00940 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0; 00941 } 00942 else if (channel == 1) { 00943 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 00944 if (ret != MAX77643_2_NO_ERROR) return ret; 00945 00946 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1; 00947 } 00948 else if (channel == 2) { 00949 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 00950 if (ret != MAX77643_2_NO_ERROR) return ret; 00951 00952 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2; 00953 } 00954 else { 00955 return MAX77643_2_INVALID_DATA; 00956 } 00957 00958 return MAX77643_2_NO_ERROR; 00959 } 00960 00961 int MAX77643_2::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb) 00962 { 00963 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00964 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00965 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00966 00967 if (channel == 0) { 00968 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb); 00969 } 00970 else if (channel == 1) { 00971 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb); 00972 } 00973 else if (channel == 2) { 00974 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb); 00975 } 00976 else { 00977 return MAX77643_2_INVALID_DATA; 00978 } 00979 00980 return MAX77643_2_NO_ERROR; 00981 } 00982 00983 int MAX77643_2::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb) 00984 { 00985 int ret; 00986 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 00987 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 00988 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 00989 00990 if (channel == 0) { 00991 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 00992 if (ret != MAX77643_2_NO_ERROR) return ret; 00993 00994 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0; 00995 } 00996 else if (channel == 1) { 00997 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 00998 if (ret != MAX77643_2_NO_ERROR) return ret; 00999 01000 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1; 01001 } 01002 else if (channel == 2) { 01003 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 01004 if (ret != MAX77643_2_NO_ERROR) return ret; 01005 01006 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2; 01007 } 01008 else return MAX77643_2_INVALID_DATA; 01009 01010 return MAX77643_2_NO_ERROR; 01011 } 01012 01013 int MAX77643_2::set_tv_sbb_dvs(float voltV) 01014 { 01015 uint8_t value; 01016 reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0}; 01017 float voltmV = voltV * 1000; 01018 01019 if (voltmV < 500) voltmV = 500; 01020 else if (voltmV > 5500) voltmV = 5500; 01021 01022 value = (voltmV - 500) / 25; 01023 01024 SET_BIT_FIELD(CNFG_DVS_SBB0_A, reg_cnfg_dvs_sbb0_a, reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs, value); 01025 return MAX77643_2_NO_ERROR; 01026 } 01027 01028 int MAX77643_2::get_tv_sbb_dvs(float *voltV) 01029 { 01030 int ret; 01031 uint8_t bit_value; 01032 reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0}; 01033 01034 ret = read_register(CNFG_DVS_SBB0_A, (uint8_t *)&(reg_cnfg_dvs_sbb0_a)); 01035 if (ret != MAX77643_2_NO_ERROR) return ret; 01036 01037 bit_value = (uint8_t)reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs; 01038 01039 if (bit_value > 200) bit_value = 200; 01040 01041 *voltV = (bit_value * 0.025f) + 0.5f; 01042 return MAX77643_2_NO_ERROR; 01043 } 01044 01045 int MAX77643_2::set_tv_ldo(float voltV) 01046 { 01047 int ret; 01048 uint8_t value; 01049 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01050 float voltmV = voltV * 1000; 01051 const float offsetmV = 1325; 01052 const float incrementmV = 25; 01053 float lower_limit_voltmV = 500, upper_limit_voltmV = 3675; 01054 01055 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01056 if (ret != MAX77643_2_NO_ERROR) return ret; 01057 01058 if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 1) { // 1.325V Offset 01059 lower_limit_voltmV += offsetmV; 01060 upper_limit_voltmV += offsetmV; 01061 } 01062 01063 voltmV = (voltmV < lower_limit_voltmV) ? lower_limit_voltmV : upper_limit_voltmV; 01064 value = (voltmV - lower_limit_voltmV) / incrementmV; 01065 01066 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo0, value); 01067 01068 return MAX77643_2_NO_ERROR; 01069 } 01070 01071 int MAX77643_2::get_tv_ldo(float *voltV) 01072 { 01073 int ret; 01074 uint8_t bit_value; 01075 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01076 float lower_limitV = 0.5f; 01077 const float incrementV = 0.025f; 01078 const float offsetV = 1.325f; 01079 01080 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01081 if (ret != MAX77643_2_NO_ERROR) return ret; 01082 01083 bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo0; 01084 if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 0) //No Offset 01085 *voltV = (bit_value * incrementV) + lower_limitV; 01086 else //1.325V Offset 01087 *voltV = (bit_value * incrementV) + (lower_limitV + offsetV); 01088 01089 return MAX77643_2_NO_ERROR; 01090 } 01091 01092 int MAX77643_2::set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset) 01093 { 01094 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01095 01096 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ofs_ldo, offset); 01097 01098 return MAX77643_2_NO_ERROR; 01099 } 01100 01101 int MAX77643_2::get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset) 01102 { 01103 int ret; 01104 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01105 01106 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01107 if (ret != MAX77643_2_NO_ERROR) return ret; 01108 01109 *offset = (decode_tv_ofs_ldo_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo; 01110 01111 return MAX77643_2_NO_ERROR; 01112 } 01113 01114 int MAX77643_2::set_en_ldo(decode_en_ldo_t en_ldo) 01115 { 01116 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01117 01118 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo); 01119 01120 return MAX77643_2_NO_ERROR; 01121 } 01122 01123 int MAX77643_2::get_en_ldo(decode_en_ldo_t *en_ldo) 01124 { 01125 int ret; 01126 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01127 01128 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01129 if (ret != MAX77643_2_NO_ERROR) return ret; 01130 01131 *en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo; 01132 01133 return MAX77643_2_NO_ERROR; 01134 } 01135 01136 int MAX77643_2::set_ade_ldo(decode_ade_ldo_t ade_ldo) 01137 { 01138 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01139 01140 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo); 01141 01142 return MAX77643_2_NO_ERROR; 01143 } 01144 01145 int MAX77643_2::get_ade_ldo(decode_ade_ldo_t *ade_ldo) 01146 { 01147 int ret; 01148 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01149 01150 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01151 if (ret != MAX77643_2_NO_ERROR) return ret; 01152 01153 *ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo; 01154 01155 return MAX77643_2_NO_ERROR; 01156 } 01157 01158 int MAX77643_2::set_ldo_md(decode_ldo_md_t mode) 01159 { 01160 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01161 01162 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode); 01163 01164 return MAX77643_2_NO_ERROR; 01165 } 01166 01167 int MAX77643_2::get_ldo_md(decode_ldo_md_t *mode) 01168 { 01169 int ret; 01170 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01171 01172 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01173 if (ret != MAX77643_2_NO_ERROR) return ret; 01174 01175 *mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md; 01176 01177 return MAX77643_2_NO_ERROR; 01178 } 01179 01180 int MAX77643_2::irq_disable_all() 01181 { 01182 int ret; 01183 uint8_t reg = 0; 01184 uint8_t status = 0; 01185 01186 //Disable Masks in INTM_GLBL1 01187 ret = write_register(INTM_GLBL1, ®); 01188 if (ret != MAX77643_2_NO_ERROR) return ret; 01189 01190 //Disable Masks in INTM_GLBL0 01191 ret = write_register(INTM_GLBL0, ®); 01192 if (ret != MAX77643_2_NO_ERROR) return ret; 01193 01194 // Clear Interrupt Flags in INT_GLBL1 01195 ret = read_register(INT_GLBL1, &status); 01196 if (ret != MAX77643_2_NO_ERROR) return ret; 01197 01198 // Clear Interrupt Flags in INT_GLBL0 01199 ret = read_register(INT_GLBL0, &status); 01200 if (ret != MAX77643_2_NO_ERROR) return ret; 01201 01202 return MAX77643_2_NO_ERROR; 01203 } 01204 01205 void MAX77643_2::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb) 01206 { 01207 interrupt_handler_list[id].func = func; 01208 interrupt_handler_list[id].cb = cb; 01209 } 01210 01211 void MAX77643_2::post_interrupt_work() 01212 { 01213 int ret; 01214 uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0; 01215 01216 while (true) { 01217 01218 ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID); 01219 01220 // Check Interrupt Flags in INT_GLBL0 01221 ret = read_register(INT_GLBL0, ®); 01222 if (ret != MAX77643_2_NO_ERROR) return; 01223 01224 ret = read_register(INTM_GLBL0, &inten); 01225 if (ret != MAX77643_2_NO_ERROR) return; 01226 01227 not_inten = ~inten; // 0 means unmasked. 01228 01229 for (int i = 0; i < INT_GLBL1_GPI1_F; i++) { 01230 mask = (1 << i); 01231 if ((reg & mask) && (not_inten & mask)) { 01232 if (interrupt_handler_list[i].func != NULL) { 01233 interrupt_handler_list[i] 01234 .func(interrupt_handler_list[i].cb); 01235 } 01236 } 01237 } 01238 01239 // Check Interrupt Flags in INT_GLBL1 01240 ret = read_register(INT_GLBL1, ®); 01241 if (ret != MAX77643_2_NO_ERROR) return; 01242 01243 ret = read_register(INTM_GLBL1, &inten); 01244 if (ret != MAX77643_2_NO_ERROR) return; 01245 01246 not_inten = ~inten; // 0 means unmasked. 01247 01248 for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_END; i++) { 01249 mask = (1 << (i - INT_GLBL1_GPI1_F)); 01250 if ((reg & mask) && (not_inten & mask)) { 01251 if (interrupt_handler_list[i].func != NULL) { 01252 interrupt_handler_list[i] 01253 .func(interrupt_handler_list[i].cb); 01254 } 01255 } 01256 } 01257 } 01258 } 01259 01260 void MAX77643_2::interrupt_handler() 01261 { 01262 post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID); 01263 } 01264
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