MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver

Files at this revision

API Documentation at this revision

Comitter:
Okan Sahin
Date:
Fri Aug 26 14:20:53 2022 +0300
Commit message:
Initial Commit

Changed in this revision

MAX77643_2.cpp Show annotated file Show diff for this revision Revisions of this file
MAX77643_2.h Show annotated file Show diff for this revision Revisions of this file
MAX77643_2_regs.h Show annotated file Show diff for this revision Revisions of this file
diff -r 000000000000 -r 55f664e8c56c MAX77643_2.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77643_2.cpp	Fri Aug 26 14:20:53 2022 +0300
@@ -0,0 +1,1264 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#include <Thread.h>
+#include "MAX77643_2.h"
+#include <math.h>
+
+#define POST_INTR_WORK_SIGNAL_ID			0x1
+#define TO_UINT8							0xFF
+#define TO_UINT16							0xFFFF
+
+MAX77643_2::MAX77643_2(I2C *i2c, PinName IRQPin)
+{
+	if (i2c == NULL)
+		return;
+
+	i2c_handler = i2c;
+	interrupt_handler_list = new handler[INTM_NUM_OF_BIT] {};
+
+	if (IRQPin != NC) {
+		irq_disable_all();
+		post_intr_work_thread = new Thread();
+		post_intr_work_thread->start(Callback<void()>(this, &MAX77643_2::post_interrupt_work));
+
+		this->irq_pin = new InterruptIn(IRQPin);
+		this->irq_pin->fall(Callback<void()>(this, &MAX77643_2::interrupt_handler));
+		this->irq_pin->enable_irq();
+	} else {
+		this->irq_pin = NULL;
+	}
+}
+
+MAX77643_2::~MAX77643_2()
+{
+	if (post_intr_work_thread)
+		delete post_intr_work_thread;
+
+	if (irq_pin)
+		delete irq_pin;
+
+	if (interrupt_handler_list)
+		delete [] interrupt_handler_list;
+}
+
+int MAX77643_2::read_register(uint8_t reg, uint8_t *value)
+{
+	int rtn_val;
+
+	if (value == NULL)
+		return MAX77643_2_VALUE_NULL;
+
+	rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)&reg, 1, true);
+	if (rtn_val != 0)
+		return MAX77643_2_WRITE_DATA_FAILED;
+	rtn_val = i2c_handler->read(MAX77643_2_I2C_ADDRESS, (char *) value, 1, false);
+	if (rtn_val < 0)
+		return MAX77643_2_READ_DATA_FAILED;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::write_register(uint8_t reg, const uint8_t *value)
+{
+	int rtn_val;
+	unsigned char local_data[2];
+
+	if (value == NULL)
+		return MAX77643_2_VALUE_NULL;
+
+	local_data[0] = reg;
+
+	memcpy(&local_data[1], value, 1);
+
+	rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
+	if (rtn_val != MAX77643_2_NO_ERROR)
+		return MAX77643_2_WRITE_DATA_FAILED;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+#define SET_BIT_FIELD(address, reg_name, bit_field_name, value)                         	\
+	int ret_val;                                                                    \
+        ret_val = read_register(address, (uint8_t *)&(reg_name));                       \
+        if (ret_val) {                                                                  \
+        	return ret_val;                                                             \
+	}                                                                           	\
+	bit_field_name = value;                                                     	\
+	ret_val = write_register(address, (uint8_t *)&(reg_name));                      \
+	if (ret_val) {                                                                  \
+	return ret_val;                                                             \
+	}
+
+int MAX77643_2::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
+{
+	int ret;
+	reg_ercflag_t reg_ercflag = {0};
+
+	ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+	case ERCFLAG_TOVLD:
+		*flag = (uint8_t)reg_ercflag.bits.tovld;
+		break;
+	case ERCFLAG_INOVLO:
+		*flag = (uint8_t)reg_ercflag.bits.inovlo;
+		break;
+	case ERCFLAG_INUVLO:
+		*flag = (uint8_t)reg_ercflag.bits.inuvlo;
+		break;
+	case ERCFLAG_MRST_F:
+		*flag = (uint8_t)reg_ercflag.bits.mrst_f;
+		break;
+	case ERCFLAG_SFT_OFF_F:
+		*flag = (uint8_t)reg_ercflag.bits.sft_off_f;
+		break;
+	case ERCFLAG_SFT_CRST_F:
+		*flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
+		break;
+	case ERCFLAG_WDT_EXP_F:
+		*flag = (uint8_t)reg_ercflag.bits.wdt_exp_f;
+		break;
+	case ERCFLAG_SBB_FAULT_F:
+		*flag = (uint8_t)reg_ercflag.bits.sbb_fault_f;
+		break;
+	default:
+		ret = MAX77643_2_INVALID_DATA;
+		break;		
+	}
+
+	return ret;
+}
+
+int MAX77643_2::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
+{
+	int ret;
+	reg_stat_glbl_t reg_stat_glbl = {0};
+
+	ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{
+	case STAT_GLBL_STAT_IRQ:
+		*status = (uint8_t)reg_stat_glbl.bits.stat_irq;
+		break;
+	case STAT_GLBL_STAT_EN:
+		*status = (uint8_t)reg_stat_glbl.bits.stat_en;
+		break;
+	case STAT_GLBL_TJAL1_S:
+		*status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
+		break;
+	case STAT_GLBL_TJAL2_S:
+		*status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
+		break;
+	case STAT_GLBL_DOD_S:
+		*status = (uint8_t)reg_stat_glbl.bits.dod_s;
+		break;
+	case STAT_GLBL_BOK:
+		*status = (uint8_t)reg_stat_glbl.bits.bok;
+		break;
+	case STAT_GLBL_DIDM:
+		*status = (uint8_t)reg_stat_glbl.bits.didm;
+		break;
+	default:
+		ret = MAX77643_2_INVALID_DATA;
+		break;		
+	}
+
+	return ret;
+}
+
+int MAX77643_2::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
+{
+	int ret;
+	uint8_t reg_addr = 0;
+	reg_intm_glbl0_t reg_intm_glbl0 = {0};
+	reg_intm_glbl1_t reg_intm_glbl1 = {0};
+ 
+	//INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05)
+	reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04; 
+	
+	if (reg_addr == INTM_GLBL0)
+		ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+	else if (reg_addr == INTM_GLBL1)
+		ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+	else 
+		return MAX77643_2_INVALID_DATA;
+	
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+	case INTM_GLBL0_GPI0_FM:
+		reg_intm_glbl0.bits.gpi0_fm = maskBit;
+		break;
+	case INTM_GLBL0_GPI0_RM:
+		reg_intm_glbl0.bits.gpi0_rm = maskBit;
+		break;
+	case INTM_GLBL0_nEN_FM:
+		reg_intm_glbl0.bits.nen_fm = maskBit;
+		break;
+	case INTM_GLBL0_nEN_RM:
+		reg_intm_glbl0.bits.nen_rm = maskBit;
+		break;
+	case INTM_GLBL0_TJAL1_RM:
+		reg_intm_glbl0.bits.tjal1_rm = maskBit;
+		break;
+	case INTM_GLBL0_TJAL2_RM:
+		reg_intm_glbl0.bits.tjal2_rm = maskBit;
+		break;
+	case INTM_GLBL0_DOD_RM:
+		reg_intm_glbl0.bits.dod_rm = maskBit;
+		break;
+	case INTM_GLBL1_GPI1_FM:
+		reg_intm_glbl1.bits.gpi1_fm = maskBit;
+		break;
+	case INTM_GLBL1_GPI1_RM:
+		reg_intm_glbl1.bits.gpi1_rm = maskBit;
+		break;
+	case INTM_GLBL1_SBB0_FM:
+		reg_intm_glbl1.bits.sbb0_fm = maskBit;
+		break;
+	case INTM_GLBL1_SBB1_FM:
+		reg_intm_glbl1.bits.sbb1_fm = maskBit;
+		break;
+	case INTM_GLBL1_SBB2_FM:
+		reg_intm_glbl1.bits.sbb2_fm = maskBit;
+		break;
+	case INTM_GLBL1_LDO_M:
+		reg_intm_glbl1.bits.ldo_m = maskBit;
+		break;
+	default:
+		return MAX77643_2_INVALID_DATA;
+		break;		
+	}
+    
+	if (reg_addr == INTM_GLBL0)
+		return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+	else if (reg_addr == INTM_GLBL1)
+		return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+	else 
+		return MAX77643_2_INVALID_DATA;
+}
+
+int MAX77643_2::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
+{
+	int ret;
+	uint8_t reg_addr = 0;
+	reg_intm_glbl0_t reg_intm_glbl0 = {0};
+	reg_intm_glbl1_t reg_intm_glbl1 = {0};
+ 
+	//INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05)
+	reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04; 
+	
+	if (reg_addr == INTM_GLBL0)
+		ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+	else if (reg_addr == INTM_GLBL1)
+		ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+	else 
+		return MAX77643_2_INVALID_DATA;
+	
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{	
+	case INTM_GLBL0_GPI0_FM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm;
+		break;
+	case INTM_GLBL0_GPI0_RM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm;
+		break;
+	case INTM_GLBL0_nEN_FM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm;
+		break;
+	case INTM_GLBL0_nEN_RM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm;
+		break;
+	case INTM_GLBL0_TJAL1_RM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm;
+		break;
+	case INTM_GLBL0_TJAL2_RM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm;
+		break;
+	case INTM_GLBL0_DOD_RM:
+		*maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm;
+		break;	
+	case INTM_GLBL1_GPI1_FM:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm;
+		break;
+	case INTM_GLBL1_GPI1_RM:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm;
+		break;
+	case INTM_GLBL1_SBB0_FM:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.sbb0_fm;
+		break;
+	case INTM_GLBL1_SBB1_FM:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.sbb1_fm;
+		break;
+	case INTM_GLBL1_SBB2_FM:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.sbb2_fm;
+		break;
+	case INTM_GLBL1_LDO_M:
+		*maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m;
+		break;
+	default:
+		return MAX77643_2_INVALID_DATA;
+		break;		
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config)
+{	
+	int ret;
+	reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0};
+	
+	ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+	case CNFG_GLBL0_SFT_CTRL:
+		reg_cnfg_glbl0.bits.sft_ctrl = config;
+		break;
+	case CNFG_GLBL0_DBEN_nEN:
+		reg_cnfg_glbl0.bits.dben_nen = config;
+		break;
+	case CNFG_GLBL0_nEN_MODE:
+		reg_cnfg_glbl0.bits.nen_mode = config;
+		break;
+	case CNFG_GLBL0_SBIA_LPM:
+		reg_cnfg_glbl0.bits.sbia_lpm = config;
+		break;
+	case CNFG_GLBL0_T_MRST:
+		reg_cnfg_glbl0.bits.t_mrst = config;
+		break;
+	case CNFG_GLBL0_PU_DIS:
+		reg_cnfg_glbl0.bits.pu_dis = config;
+		break;
+	default:
+		return MAX77643_2_INVALID_DATA;
+		break;		
+	}
+                                  	
+	return write_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
+}
+
+int MAX77643_2::get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config)
+{
+	int ret;
+	reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0};
+
+	ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{
+	case CNFG_GLBL0_SFT_CTRL:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.sft_ctrl;
+		break;
+	case CNFG_GLBL0_DBEN_nEN:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.dben_nen;
+		break;
+	case CNFG_GLBL0_nEN_MODE:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.nen_mode;
+		break;
+	case CNFG_GLBL0_SBIA_LPM:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.sbia_lpm;
+		break;
+	case CNFG_GLBL0_T_MRST:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.t_mrst;
+		break;
+	case CNFG_GLBL0_PU_DIS:
+		*config = (uint8_t)reg_cnfg_glbl0.bits.pu_dis;
+		break;
+	default:
+		ret = MAX77643_2_INVALID_DATA;
+		break;		
+	}
+
+    return ret;
+}
+
+int MAX77643_2::set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config)
+{	
+	int ret;
+	reg_cnfg_glbl1_t reg_cnfg_glbl1;
+	
+	ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+	case CNFG_GLBL1_AUTO_WKT:
+		reg_cnfg_glbl1.bits.auto_wkt = config;
+		break;
+	case CNFG_GLBL1_SBB_F_SHUTDN:
+		reg_cnfg_glbl1.bits.sbb_f_shutdn = config;
+		break;
+	default:
+		return MAX77643_2_INVALID_DATA;
+		break;		
+	}
+                                  	
+	return write_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
+}
+
+int MAX77643_2::get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config)
+{
+	int ret;
+	reg_cnfg_glbl1_t reg_cnfg_glbl1 = {0};
+
+	ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{
+	case CNFG_GLBL1_AUTO_WKT:
+		*config = (uint8_t)reg_cnfg_glbl1.bits.auto_wkt;
+		break;
+	case CNFG_GLBL1_SBB_F_SHUTDN:
+		*config = (uint8_t)reg_cnfg_glbl1.bits.sbb_f_shutdn;
+		break;
+	default:
+		ret = MAX77643_2_INVALID_DATA;
+		break;		
+	}
+
+	return ret;
+}
+
+int MAX77643_2::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config)
+{
+	int ret;
+	reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
+	reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
+	
+	if (channel == 0)
+	{
+		ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+		
+		switch (bit_field)
+		{
+			case CNFG_GPIO_DIR:
+				reg_cnfg_gpio0.bits.gpo_dir = config;
+				break;
+			case CNFG_GPIO_DI:
+				reg_cnfg_gpio0.bits.gpo_di = config;
+				break;
+			case CNFG_GPIO_DRV:
+				reg_cnfg_gpio0.bits.gpo_drv = config;
+				break;
+			case CNFG_GPIO_DO:
+				reg_cnfg_gpio0.bits.gpo_do = config;
+				break;
+			case CNFG_GPIO_DBEN_GPI:
+				reg_cnfg_gpio0.bits.dben_gpi = config;
+				break;
+			case CNFG_GPIO_ALT_GPIO:
+				reg_cnfg_gpio0.bits.alt_gpio = config;
+				break;
+			default:
+				return MAX77643_2_INVALID_DATA;
+				break;		
+		}
+		
+		return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+	}
+	else if (channel == 1)
+	{
+		ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+		
+		switch (bit_field)
+		{
+			case CNFG_GPIO_DIR:
+				reg_cnfg_gpio1.bits.gpo_dir = config;
+				break;
+			case CNFG_GPIO_DI:
+				reg_cnfg_gpio1.bits.gpo_di = config;
+				break;
+			case CNFG_GPIO_DRV:
+				reg_cnfg_gpio1.bits.gpo_drv = config;
+				break;
+			case CNFG_GPIO_DO:
+				reg_cnfg_gpio1.bits.gpo_do = config;
+				break;
+			case CNFG_GPIO_DBEN_GPI:
+				reg_cnfg_gpio1.bits.dben_gpi = config;
+				break;
+			case CNFG_GPIO_ALT_GPIO:
+				reg_cnfg_gpio1.bits.alt_gpio = config;
+				break;
+			default:
+				return MAX77643_2_INVALID_DATA;
+				break;		
+		}
+		
+		return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+}
+
+int MAX77643_2::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config)
+{
+	int ret;
+	reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
+	reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
+	
+	if (channel == 0)
+	{
+		ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+		switch (bit_field)
+		{
+			case CNFG_GPIO_DIR:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir;
+				break;
+			case CNFG_GPIO_DI:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di;
+				break;
+			case CNFG_GPIO_DRV:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv;
+				break;
+			case CNFG_GPIO_DO:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do;
+				break;
+			case CNFG_GPIO_DBEN_GPI:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi;
+				break;
+			case CNFG_GPIO_ALT_GPIO:
+				*config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio;
+				break;
+			default:
+				return MAX77643_2_INVALID_DATA;
+				break;		
+		}
+	}
+	else if (channel == 1)
+	{
+		ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+		
+		switch (bit_field)
+		{
+			case CNFG_GPIO_DIR:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir;
+				break;
+			case CNFG_GPIO_DI:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di;
+				break;
+			case CNFG_GPIO_DRV:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv;
+				break;
+			case CNFG_GPIO_DO:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do;
+				break;
+			case CNFG_GPIO_DBEN_GPI:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi;
+				break;
+			case CNFG_GPIO_ALT_GPIO:
+				*config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio;
+				break;
+			default:
+				return MAX77643_2_INVALID_DATA;
+				break;		
+		}
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+
+	return ret;
+}
+
+int MAX77643_2::get_cid(void) {
+	char rbuf[1] = {0};
+	int ret;
+
+	ret = read_register(CID, (uint8_t *)&(rbuf));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+ 
+	return *rbuf;
+}
+
+int MAX77643_2::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config)
+{
+	int ret;
+	reg_cnfg_wdt_t reg_cnfg_wdt = {0};
+	
+	ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+		case CNFG_WDT_WDT_LOCK:
+			reg_cnfg_wdt.bits.wdt_lock = config;
+			break;
+		case CNFG_WDT_WDT_EN:
+			reg_cnfg_wdt.bits.wdt_en = config;
+			break;
+		case CNFG_WDT_WDT_CLR:
+			reg_cnfg_wdt.bits.wdt_clr = config;
+			break;
+		case CNFG_WDT_WDT_MODE:
+			reg_cnfg_wdt.bits.wdt_mode = config;
+			break;
+		case CNFG_WDT_WDT_PER:
+			reg_cnfg_wdt.bits.wdt_per = config;
+			break;
+		default:
+			return MAX77643_2_INVALID_DATA;
+			break;		
+	}
+
+	return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+}
+
+int MAX77643_2::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config)
+{
+	int ret;
+	reg_cnfg_wdt_t reg_cnfg_wdt = {0};
+
+	ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{
+		case CNFG_WDT_WDT_LOCK:
+			*config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock;
+			break;
+		case CNFG_WDT_WDT_EN:
+			*config = (uint8_t)reg_cnfg_wdt.bits.wdt_en;
+			break;
+		case CNFG_WDT_WDT_CLR:
+			*config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr;
+			break;
+		case CNFG_WDT_WDT_MODE:
+			*config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode;
+			break;
+		case CNFG_WDT_WDT_PER:
+			*config = (uint8_t)reg_cnfg_wdt.bits.wdt_per;
+			break;
+		default:
+			return MAX77643_2_INVALID_DATA;
+			break;		
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config)
+{
+	int ret;
+	reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+	
+	ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+	switch (bit_field)
+	{
+		case CNFG_SBB_TOP_DRV_SBB:
+			reg_cnfg_sbb_top.bits.drv_sbb = config;
+			break;
+		case CNFG_SBB_TOP_DIS_LPM:
+			reg_cnfg_sbb_top.bits.dis_lpm = config;
+			break;
+		default:
+			return MAX77643_2_INVALID_DATA;
+		break;
+	}
+
+	return write_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
+}
+
+int MAX77643_2::get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config)
+{
+	int ret;
+	reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+
+	ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	switch (bit_field)
+	{
+		case CNFG_SBB_TOP_DRV_SBB:
+			*config = (uint8_t)reg_cnfg_sbb_top.bits.drv_sbb;
+			break;
+		case CNFG_SBB_TOP_DIS_LPM:
+			*config = (uint8_t)reg_cnfg_sbb_top.bits.dis_lpm;
+			break;
+		default:
+			return MAX77643_2_INVALID_DATA;
+		break;
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_tv_sbb(uint8_t channel, float voltV)
+{
+	uint8_t value;
+	reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
+	reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
+	reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
+	float voltmV = voltV * 1000;
+	
+	if (voltmV < 500) voltmV = 500;
+	else if (voltmV > 5500) voltmV = 5500;
+
+	value = (voltmV - 500) / 25;
+
+	if (channel == 0) {
+		SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
+	}		
+	else if (channel == 1) {
+		SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
+	}
+	else if (channel == 2) {
+		SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_tv_sbb(uint8_t channel, float *voltV)
+{
+	int ret;
+	uint8_t bit_value;
+	reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
+	reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
+	reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
+
+	if (channel == 0) { 
+		ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+		
+		bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
+	}
+	else if (channel == 1) {
+		ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+		bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
+	}
+	else if (channel == 2) {
+		ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+	
+		bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
+	}
+	else return MAX77643_2_INVALID_DATA;
+	
+	if (bit_value > 200) bit_value = 200;
+	*voltV = (bit_value * 0.025f) + 0.5f;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_op_mode(uint8_t channel, decode_op_mode_t mode)
+{	
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+	
+	if (channel == 0) {
+		SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode0, mode);
+	}
+	else if (channel == 1) {
+		SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode1, mode);
+	}
+	else if (channel == 2) {
+		SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode2, mode);
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_op_mode(uint8_t channel, decode_op_mode_t *mode)
+{
+	int ret;
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+	if (channel == 0) {
+		ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode0;
+	}
+	else if (channel == 1) {
+		ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode1;
+	}
+	else if (channel == 2) {
+		ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode2;
+	}
+	else { 
+		return MAX77643_2_INVALID_DATA;
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb)
+{	
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+	
+	if (channel == 0) {
+		SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ip_sbb0, ip_sbb);
+	}
+	else if (channel == 1) {
+		SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ip_sbb1, ip_sbb);
+	}
+	else if (channel == 2) {
+		SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ip_sbb2, ip_sbb);
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb)
+{
+	int ret;
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+	if (channel == 0) {
+		ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb0_b.bits.ip_sbb0;
+	}
+	else if (channel == 1) {
+		ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb1_b.bits.ip_sbb1;
+	}
+	else if (channel == 2) {
+		ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb2_b.bits.ip_sbb2;
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
+{	
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+	
+	if (channel == 0) {
+		SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
+	}
+	else if (channel == 1) {
+		SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
+	}
+	else if (channel == 2) {
+		SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
+{
+	int ret;
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+	if (channel == 0) {
+		ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
+	}
+	else if (channel == 1) {
+		ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
+	}
+	else if (channel == 2) {
+		ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
+{	
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+	
+	if (channel == 0) {
+		SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
+	}
+	else if (channel == 1) {
+		SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
+	}
+	else if (channel == 2) {
+		SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
+	}
+	else {
+		return MAX77643_2_INVALID_DATA;
+	}
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
+{
+	int ret;
+	reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+	reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+	reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+	if (channel == 0) {
+		ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
+	}
+	else if (channel == 1) {
+		ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
+	}
+	else if (channel == 2) {
+		ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+		if (ret != MAX77643_2_NO_ERROR) return ret;
+
+		*en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
+	}
+	else return MAX77643_2_INVALID_DATA;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_tv_sbb_dvs(float voltV)
+{
+	uint8_t value;
+	reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0};
+	float voltmV = voltV * 1000;
+
+	if (voltmV < 500) voltmV = 500;
+	else if (voltmV > 5500) voltmV = 5500;	
+
+	value = (voltmV - 500) / 25;
+	
+	SET_BIT_FIELD(CNFG_DVS_SBB0_A, reg_cnfg_dvs_sbb0_a, reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs, value);
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_tv_sbb_dvs(float *voltV)
+{
+	int ret;
+	uint8_t bit_value;
+	reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0};
+
+	ret = read_register(CNFG_DVS_SBB0_A, (uint8_t *)&(reg_cnfg_dvs_sbb0_a));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	bit_value = (uint8_t)reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs;
+	
+	if (bit_value > 200) bit_value = 200;
+	
+	*voltV = (bit_value * 0.025f) + 0.5f;
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_tv_ldo(float voltV)
+{
+	int ret;
+	uint8_t value;
+	reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+	float voltmV = voltV * 1000;
+	const float offsetmV = 1325;
+	const float incrementmV = 25;
+	float lower_limit_voltmV = 500, upper_limit_voltmV = 3675;
+
+	ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 1) { // 1.325V Offset
+		lower_limit_voltmV += offsetmV;
+		upper_limit_voltmV += offsetmV;
+	}
+
+	voltmV	= (voltmV < lower_limit_voltmV) ? lower_limit_voltmV : upper_limit_voltmV;
+	value	= (voltmV - lower_limit_voltmV) / incrementmV;
+
+	SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo0, value);
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_tv_ldo(float *voltV)
+{
+	int ret;
+	uint8_t bit_value;
+	reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+	float lower_limitV		= 0.5f;
+	const float incrementV	= 0.025f;
+	const float offsetV		= 1.325f;
+
+	ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo0;
+	if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 0) //No Offset
+		*voltV = (bit_value * incrementV) + lower_limitV;
+	else //1.325V Offset 
+		*voltV = (bit_value * incrementV) + (lower_limitV + offsetV);
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset)
+{	
+	reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+	
+	SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ofs_ldo, offset);
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset)
+{
+	int ret;
+	reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+
+	ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	*offset = (decode_tv_ofs_ldo_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_en_ldo(decode_en_ldo_t en_ldo)
+{	
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+	
+	SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo);
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_en_ldo(decode_en_ldo_t *en_ldo)
+{
+	int ret;
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+	ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	*en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_ade_ldo(decode_ade_ldo_t ade_ldo)
+{	
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+	
+	SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo);
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_ade_ldo(decode_ade_ldo_t *ade_ldo)
+{
+	int ret;
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+	ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	*ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::set_ldo_md(decode_ldo_md_t mode)
+{	
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+	
+	SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode);
+	
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::get_ldo_md(decode_ldo_md_t *mode)
+{
+	int ret;
+	reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+	ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	*mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+int MAX77643_2::irq_disable_all()
+{
+	int ret;
+	uint8_t reg = 0;
+	uint8_t status = 0;
+
+	//Disable Masks in INTM_GLBL1
+	ret = write_register(INTM_GLBL1, &reg);
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	//Disable Masks in INTM_GLBL0
+	ret = write_register(INTM_GLBL0, &reg);
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	// Clear Interrupt Flags in INT_GLBL1
+	ret = read_register(INT_GLBL1, &status);
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	// Clear Interrupt Flags in INT_GLBL0
+	ret = read_register(INT_GLBL0, &status);
+	if (ret != MAX77643_2_NO_ERROR) return ret;
+
+	return MAX77643_2_NO_ERROR;
+}
+
+void MAX77643_2::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
+{
+	interrupt_handler_list[id].func = func;
+	interrupt_handler_list[id].cb = cb;
+}
+
+void MAX77643_2::post_interrupt_work()
+{
+	int ret;
+	uint8_t reg = 0,  inten = 0, not_inten = 0, mask = 0;
+
+	while (true) {
+
+		ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
+
+		// Check Interrupt Flags in INT_GLBL0
+		ret = read_register(INT_GLBL0, &reg);
+		if (ret != MAX77643_2_NO_ERROR) return;
+
+		ret = read_register(INTM_GLBL0, &inten);
+		if (ret != MAX77643_2_NO_ERROR) return;
+
+		not_inten = ~inten; // 0 means unmasked.
+
+		for (int i = 0; i < INT_GLBL1_GPI1_F; i++) {
+			mask = (1 << i);
+			if ((reg & mask) && (not_inten & mask)) {
+			if (interrupt_handler_list[i].func != NULL) {
+				interrupt_handler_list[i]
+				.func(interrupt_handler_list[i].cb);
+			}
+			}
+		}
+
+		// Check Interrupt Flags in INT_GLBL1
+		ret = read_register(INT_GLBL1, &reg);
+		if (ret != MAX77643_2_NO_ERROR) return;
+
+		ret = read_register(INTM_GLBL1, &inten);
+		if (ret != MAX77643_2_NO_ERROR) return;
+
+		not_inten = ~inten; // 0 means unmasked.
+
+		for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_END; i++) {
+			mask = (1 << (i - INT_GLBL1_GPI1_F));
+			if ((reg & mask) && (not_inten & mask)) {
+				if (interrupt_handler_list[i].func != NULL) {
+					interrupt_handler_list[i]
+					.func(interrupt_handler_list[i].cb);
+				}
+			}
+		}
+	}
+}
+
+void MAX77643_2::interrupt_handler()
+{
+	post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
+}
+
diff -r 000000000000 -r 55f664e8c56c MAX77643_2.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77643_2.h	Fri Aug 26 14:20:53 2022 +0300
@@ -0,0 +1,886 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX77643_2_H_
+#define _MAX77643_2_H_
+
+#include "mbed.h"
+#include "MAX77643_2_regs.h"
+
+#define MAX77643_2_NO_ERROR                    0
+#define MAX77643_2_VALUE_NULL                 -1
+#define MAX77643_2_WRITE_DATA_FAILED          -2
+#define MAX77643_2_READ_DATA_FAILED           -3
+#define MAX77643_2_INVALID_DATA               -4
+
+#define MAX77643_2_I2C_ADDRESS         		0x90
+
+/**
+ * @brief MAX77643_2 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor,
+ * 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications
+ *
+ * @details The MAX77643_2/MAX77643_2 provide power supply solutions for low-power applications where size and efficiency
+ * are critical. The MAX77643_2's SIMO and LDO output voltages are individually programmable through resistors.
+ *
+ * @code
+ * @endcode
+ */
+
+class MAX77643_2
+{
+private:
+	I2C *i2c_handler;
+	InterruptIn *irq_pin;	// interrupt pin
+
+	/**
+	 * @brief   	Register Addresses
+	 * @details 	Enumerated MAX77643_2 register addresses
+	 */
+	typedef enum {
+		/*Global*/
+		INT_GLBL0    	= 0x00,    // Interrupt Status 0
+		INT_GLBL1   	= 0x01,    // Interrupt Status 1
+		ERCFLAG      	= 0x02,    // Flags
+		STAT_GLBL    	= 0x03,    // Global Status
+		INTM_GLBL0   	= 0x04,    // Interrupt Mask 0
+		INTM_GLBL1   	= 0x05,    // Interrupt Mask 1
+		CNFG_GLBL0    	= 0x06,    // Configuration Global 0
+		CNFG_GLBL1    	= 0x07,    // Configuration Global 1
+		CNFG_GPIO0   	= 0x08,    // GPIO0 Configuration
+		CNFG_GPIO1   	= 0x09,    // GPIO1 Configuration
+		CID          	= 0x10,    // Chip Identification Code
+		CNFG_WDT     	= 0x17,    // Configuration WatchDog Timer
+		/*SBB*/
+		CNFG_SBB_TOP 	= 0x28,    // SIMO Buck-Boost Configuration
+		CNFG_SBB0_A  	= 0x29,    // SIMO Buck-Boost 0 Configuration A
+		CNFG_SBB0_B  	= 0x2A,    // SIMO Buck-Boost 0 Configuration B
+		CNFG_SBB1_A  	= 0x2B,    // SIMO Buck-Boost 1 Configuration A
+		CNFG_SBB1_B  	= 0x2C,    // SIMO Buck-Boost 1 Configuration B
+		CNFG_SBB2_A  	= 0x2D,    // SIMO Buck-Boost 2 Configuration A
+		CNFG_SBB2_B  	= 0x2E,    // SIMO Buck-Boost 2 Configuration B
+		CNFG_DVS_SBB0_A = 0x2F,    // SIMO Buck-Boost 0 DVS Configuration A
+		/*LDO*/
+		CNFG_LDO0_A		= 0x38,	   // LDO0 Output Voltage
+		CNFG_LDO0_B		= 0x39	   // LDO0 Output Voltage Configuration
+	} reg_t;
+
+	void interrupt_handler();
+
+	void (MAX77643_2::*funcptr)(void);
+
+	void post_interrupt_work();
+
+	Thread *post_intr_work_thread;
+
+	struct handler {
+		void (*func)(void *);
+		void *cb;
+	};
+
+	handler *interrupt_handler_list;
+
+public:
+	/**
+	 * @brief		MAX77643_2 constructor.
+	 */
+	MAX77643_2(I2C *i2c, PinName IRQPin = NC);
+
+	/**
+	 * @brief		MAX77643_2 destructor.
+	 */
+	~MAX77643_2();
+
+	/**
+	 * @brief		Function pointer type to interrupt handler function
+	 */
+	typedef void (*interrupt_handler_function)(void *);
+
+	/**
+	 * @brief 		Read from a register.
+	 *
+	 * @param[in] 	reg Address of a register to be written.
+	 * @param[out] 	value Pointer to save result value.
+	 *
+	 * @returns 	0 on success, negative error code on failure.
+	 */
+	int read_register(uint8_t reg, uint8_t *value);
+
+	/**
+	 * @brief 		Write to a register.
+	 *
+	 * @param[in] 	reg Address of a register to be written.
+	 * @param[out] 	value Pointer of value to be written to register.
+	 *
+	 * @returns 	0 on success, negative error code on failure.
+	 */
+	int write_register(uint8_t reg, const uint8_t *value);	
+
+	/**
+	 * @brief 		Register Configuration.
+	*		 		All Interrupt Flags combined from INT_GLBL0 (0x00) and INT_GLBL1(0x01)
+	*
+	* @details
+	*  - Register      : INT_GLBL0 (0x00) and INT_GLBL1(0x01)
+	*  - Bit Fields    :
+	*  - Default       : 0x0
+	*  - Description   : Enumerated interrupts.
+	*/
+	typedef enum {
+		INT_GLBL0_GPI0_F,
+		INT_GLBL0_GPI0_R,
+		INT_GLBL0_NEN_F,
+		INT_GLBL0_NEN_R,
+		INT_GLBL0_TJAL1_R,
+		INT_GLBL0_TJAL2_R,
+		INT_GLBL0_DOD_R,
+		INT_GLBL0_RSVD,
+		INT_GLBL1_GPI1_F,
+		INT_GLBL1_GPI1_R,
+		INT_GLBL1_SBB0_F,
+		INT_GLBL1_SBB1_F,
+		INT_GLBL1_SBB2_F,
+		INT_GLBL1_LDO_F,
+		INT_GLBL1_RSVD,
+		INT_CHG_END
+	} reg_bit_int_glbl_t;
+	
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : ERCFLAG (0x02)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Event Recorder Flags.
+	 */
+	typedef enum {
+		ERCFLAG_TOVLD,
+		ERCFLAG_INOVLO,
+		ERCFLAG_INUVLO,
+		ERCFLAG_MRST_F,
+		ERCFLAG_SFT_OFF_F,
+		ERCFLAG_SFT_CRST_F,
+		ERCFLAG_WDT_EXP_F,
+		ERCFLAG_SBB_FAULT_F
+	}reg_bit_ercflag_t;
+
+	/**
+	 * @brief		Get bit field of ERCFLAG (0x02) register.
+	 *
+	* @param[in]	bit_field 	ERCFLAG register bit field to be written.
+	* @param[out] 	flag 		Pointer to save result of ercglag bit states.	
+	*							For individual bit
+	*							0x0: ERCFLAG has not occurred,
+	*               			0x1: ERCFLAG has occurred.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : STAT_GLBL (0x03)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Global Status.
+	 */
+	typedef enum {
+		STAT_GLBL_STAT_IRQ,
+		STAT_GLBL_STAT_EN,
+		STAT_GLBL_TJAL1_S,
+		STAT_GLBL_TJAL2_S,
+		STAT_GLBL_DOD_S,
+		STAT_GLBL_RSVD,
+		STAT_GLBL_BOK,
+		STAT_GLBL_DIDM
+	}reg_bit_stat_glbl_t;
+	
+	/**
+	 * @brief		Get bit field of STAT_GLBL (0x03) register.
+	 *
+	* @param[in]	bit_field 	STAT_GLBL register bit field to be written.
+	* @param[out] 	status 		Pointer to save result of Status Global bit state.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : All interrupt mask bits.
+	 */
+	typedef enum {
+		INTM_GLBL0_GPI0_FM,
+		INTM_GLBL0_GPI0_RM,
+		INTM_GLBL0_nEN_FM,
+		INTM_GLBL0_nEN_RM,
+		INTM_GLBL0_TJAL1_RM,
+		INTM_GLBL0_TJAL2_RM,
+		INTM_GLBL0_DOD_RM,
+		INTM_GLBL0_RSVD,
+		INTM_GLBL1_GPI1_FM,
+		INTM_GLBL1_GPI1_RM,
+		INTM_GLBL1_SBB0_FM,
+		INTM_GLBL1_SBB1_FM,
+		INTM_GLBL1_SBB2_FM,
+		INTM_GLBL1_LDO_M,
+		INTM_GLBL1_RSVD,
+		INTM_NUM_OF_BIT
+	}reg_bit_int_mask_t;
+	
+	/**
+	 * @brief		Set bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register.
+	 *
+	* @param[in]	bit_field 	Register bit field to be set.
+	* @param[out] 	maskBit 	0x0: Interrupt is unmasked,
+	*                    		0x1: Interrupt is masked.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit);
+
+	/**
+	 * @brief		Get bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register.
+	 *
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[out] 	maskBit 	0x0: Interrupt is unmasked,
+	*                    		0x1: Interrupt is masked.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : CNFG_GLBL0 (0x06)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Event Recorder Flags.
+	 */
+	typedef enum {
+		CNFG_GLBL0_SFT_CTRL,
+		CNFG_GLBL0_DBEN_nEN,
+		CNFG_GLBL0_nEN_MODE,
+		CNFG_GLBL0_SBIA_LPM,
+		CNFG_GLBL0_T_MRST,
+		CNFG_GLBL0_PU_DIS
+	}reg_bit_cnfg_glbl0_t;	
+
+	/**
+  	* @brief		Set CNFG_GLBL0 (0x06) register.
+  	*
+	* @param[in]	bit_field 	Register bit field to be written.
+  	* @param[in]	config 		Register bit field to be written.
+  	*
+  	* @return		0 on success, error code on failure.
+  	*/
+	int set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config);
+
+	/**
+	* @brief		Get CNFG_GLBL0 (0x06) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[out]	config 		Pointer of value to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : CNFG_GLBL1 (0x07)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Event Recorder Flags.
+	 */
+	typedef enum {
+		CNFG_GLBL1_AUTO_WKT,
+		CNFG_GLBL1_SBB_F_SHUTDN,
+		CNFG_GLBL1_RSVD
+	}reg_bit_cnfg_glbl1_t;	
+
+	/**
+	* @brief		Set CNFG_GLBL1 (0x07) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[in]	config 		Register bit field to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config);
+
+	/**
+	* @brief		Get CNFG_GLBL1 (0x07) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[out]	config 		Pointer of value to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Event Recorder Flags.
+	 */
+	typedef enum {
+		CNFG_GPIO_DIR,
+		CNFG_GPIO_DI,
+		CNFG_GPIO_DRV,
+		CNFG_GPIO_DO,
+		CNFG_GPIO_DBEN_GPI,
+		CNFG_GPIO_ALT_GPIO,
+		CNFG_GPIO_RSVD
+	}reg_bit_cnfg_gpio_t;	
+
+	/**
+	* @brief		Set either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09).
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[in]	channel 	Channel number: 0 or 1
+	* @param[in]	config 		Register bit field to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config);
+
+	/**
+	* @brief		Get either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09).
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[in]	channel 	Channel number: 0 or 1
+	* @param[out]	config 		Pointer of value to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config);
+
+	/**
+	 * @brief		Get bit field of CID (0x10) register.
+	* 
+	* @param[in]	config 		Register bit field to be written
+	* 
+	* @return		CID on success, error code on failure.
+	*/
+	int get_cid(void);
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : CNFG_WDT (0x17)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Watchdog Timer Configuration.
+	 */
+	typedef enum {
+		CNFG_WDT_WDT_LOCK,
+		CNFG_WDT_WDT_EN,
+		CNFG_WDT_WDT_CLR,
+		CNFG_WDT_WDT_MODE,
+		CNFG_WDT_WDT_PER,
+		CNFG_WDT_RSVD
+	}reg_bit_cnfg_wdt_t;	
+	
+	/**
+	* @brief		Set CNFG_WDT (0x17) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[in]	config 		Field value to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config);
+
+	/**
+	* @brief		Get CNFG_WDT (0x17) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[out]	config 		Pointer of value to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config);
+
+	/*SBB*/
+
+	/**
+	 * @brief Register Configuration
+	 *
+	 * @details
+	 *  - Register      : CNFG_SBB_TOP (0x28)
+	 *  - Bit Fields    : [7:0]
+	 *  - Default       : 0x0
+	 *  - Description   : Watchdog Timer Configuration.
+	 */
+	typedef enum {
+		CNFG_SBB_TOP_DRV_SBB,
+		CNFG_SBB_TOP_DIS_LPM
+	}reg_bit_cnfg_sbb_top_t;	
+	
+	/**
+	* @brief		Set CNFG_SBB_TOP (0x28) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[in]	config 		Configuration value to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config);
+
+	/**
+	* @brief		Get CNFG_SBB_TOP (0x28) register.
+	*
+	* @param[in]	bit_field 	Register bit field to be written.
+	* @param[out]	config 		Configuration value to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config);
+
+	/**
+	* @brief		Set SIMO Buck-Boost Channel x Target Output Voltage.
+	*				CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D)
+	*
+	* @param[in]	channel 	Channel number: 0, 1 or 2.
+	* @param[in]	voltV 		SIMO buck-boost channel x target output voltage field to be written.
+	*							SBBx = 500mV + 25mV x TV_SBBx[7:0]
+	*							0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*							0.650V, 0.675V, 0.700V, ... 
+	*							5.425V, 5.450V, 5.475V, 5.500V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_tv_sbb(uint8_t channel, float voltV);
+
+	/**
+	* @brief		Get SIMO Buck-Boost Channel x Target Output Voltage.
+	*				CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D)
+	*
+	* @param[in]	channel 	Channel number: 0, 1 or 2.
+	* @param[out]	voltV 		SIMO buck-boost channel x target output voltage field to be read.
+	*							SBBx = 500mV + 25mV x TV_SBBx[7:0]
+	*							0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*							0.650V, 0.675V, 0.700V, ... 
+	*							5.425V, 5.450V, 5.475V, 5.500V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_tv_sbb(uint8_t channel, float *voltV);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+	*  - Bit Fields    : [7:6]
+	*  - Default       : 0x0
+	*  - Description   : Operation mode of SBB0, 1 or 2.
+	*/
+	typedef enum {
+		OP_MODE_AUTOMATIC,
+		OP_MODE_BUCK_MODE,
+		OP_MODE_BOOST_MODE,
+		OP_MODE_BUCK_BOOST_MODE
+	}decode_op_mode_t;
+
+	/**
+	* @brief		Set Operation mode of SBBx.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[in]	mode 	Operation mode of SBBx bit to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_op_mode(uint8_t channel, decode_op_mode_t mode);
+
+	/**
+	* @brief		Get Operation mode of SBBx.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[out]	mode 	Operation mode of SBBx bit to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_op_mode(uint8_t channel, decode_op_mode_t *mode);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+	*  - Bit Fields    : [5:4]
+	*  - Default       : 0x0
+	*  - Description   : SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit.
+	*/
+	typedef enum {
+		IP_SBB_AMP_1_000A,
+		IP_SBB_AMP_0_750A,
+		IP_SBB_AMP_0_500A,
+		IP_SBB_AMP_0_333A
+	}decode_ip_sbb_t;
+
+	/**
+	* @brief		Set SIMO Buck-Boost Channel x Peak Current Limit.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[in]	ip_sbb 	SIMO buck-boost channel 2 peak current limit field to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb);
+
+	/**
+	* @brief		Get SIMO Buck-Boost Channel x Peak Current Limit.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[out]	ip_sbb 	SIMO buck-boost channel 2 peak current limit field to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+	*  - Bit Fields    : [3]
+	*  - Default       : 0x0
+	*  - Description   : SIMO Buck-Boost Channel 0, 1 or 2 Active-Discharge Enable.
+	*/
+	typedef enum {
+		ADE_SBB_DISABLED,
+		ADE_SBB_ENABLED
+	}decode_ade_sbb_t;
+
+	/**
+	* @brief		Set SIMO Buck-Boost Channel x Active-Discharge Enable.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[in]	ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb);
+
+	/**
+	* @brief		Get SIMO Buck-Boost Channel x Active-Discharge Enable.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[out]	ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+	*  - Bit Fields    : [2:0]
+	*  - Default       : 0x0
+	*  - Description   : Enable Control for SIMO Buck-Boost Channel 0, 1 or 2.
+	*/
+	typedef enum {
+		EN_SBB_FPS_SLOT_0,
+		EN_SBB_FPS_SLOT_1,
+		EN_SBB_FPS_SLOT_2,
+		EN_SBB_FPS_SLOT_3,
+		EN_SBB_OFF,
+		EN_SBB_SAME_AS_0X04,
+		EN_SBB_ON,
+		EN_SBB_SAME_AS_0X06
+	}decode_en_sbb_t;
+
+	/**
+	* @brief		Set Enable Control for SIMO Buck-Boost Channel x.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[in]	en_sbb 	Enable control for SIMO buck-boost channel x field to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb);
+
+	/**
+	* @brief		Get Enable Control for SIMO Buck-Boost Channel x.
+	*
+	* @param[in]	channel Channel number: 0, 1 or 2.
+	* @param[out]	en_sbb 	Enable control for SIMO buck-boost channel x field to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb);
+
+	/**
+	* @brief		Set SIMO Buck-Boost Channel 0 Target Output Voltage.
+	*				Bit 7:0 of CNFG_DVS_SBB0_A (0x2F).
+	*
+	* @param[in]	voltV 	SIMO buck-boost channel 0 target output voltage field to be written.
+	*						SBBx = 500mV + 25mV x TV_SBBx[7:0]
+	*						0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*						0.650V, 0.675V, 0.700V, ... 
+	*						5.425V, 5.450V, 5.475V, 5.500V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_tv_sbb_dvs(float voltV);
+
+	/**
+	* @brief		Get SIMO Buck-Boost Channel 0 Target Output Voltage.
+	*				Bit 7:0 of CNFG_DVS_SBB0_A (0x2F).
+	*
+	* @param[out]	voltV 	SIMO buck-boost channel 0 target output voltage field to be read.
+	*						SBBx = 500mV + 25mV x TV_SBBx[7:0]
+	*						0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*						0.650V, 0.675V, 0.700V, ... 
+	*						5.425V, 5.450V, 5.475V, 5.500V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_tv_sbb_dvs(float *voltV);
+
+	/*LDO*/
+
+	/**
+	* @brief		Set LDO Output Channel x Target Output Voltage. Bit 6:0.
+	*				CNFG_LDO0_A (0x38)
+	*
+	* @param[in]	voltV 		LDO Output Channel x target output voltage field to be read.
+	*							LDOx = 500mV + 25mV x TV_LDOx[6:0]
+	*							0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*							0.650V, 0.675V, 0.700V, ... 
+	*							3.650, 3.675.
+	*
+	*							When TV_LDO[7] = 0, TV_LDO[6:0] sets the
+	*							LDO's output voltage range from 0.5V to 3.675V.
+	*							When TV_LDO[7] = 1, TV_LDO[6:0] sets the
+	*							LDO's output voltage from 1.825V to 5V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_tv_ldo(float voltV);
+
+	/**
+	* @brief		Get LDO Output Channel x Target Output Voltage. Bit 6:0.
+	*				CNFG_LDO0_A (0x38)
+	*
+	* @param[out]	voltV 		LDO Output Channel x target output voltage field to be read.
+	*							LDOx = 500mV + 25mV x TV_LDOx[6:0]
+	*							0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, 
+	*							0.650V, 0.675V, 0.700V, ... 
+	*							3.650, 3.675.
+	*
+	*							When TV_LDO[7] = 0, TV_LDO[6:0] sets the
+	*							LDO's output voltage range from 0.5V to 3.675V.
+	*							When TV_LDO[7] = 1, TV_LDO[6:0] sets the
+	*							LDO's output voltage from 1.825V to 5V.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_tv_ldo(float *voltV);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_LDO0_A (0x38)
+	*  - Bit Fields    : [7]
+	*  - Default       : 0x0
+	*  - Description   : SIMO Buck-Boost Channel 0 Peak Current Limit.
+	*/
+	typedef enum {
+		TV_OFS_LDO_NO_OFFSET,
+		TV_OFS_LDO_NO_1_325V
+	}decode_tv_ofs_ldo_t;
+	
+	/**
+	* @brief		Set LDO Output Channel 0 Target Output Voltage. Bit 7.
+	*				CNFG_LDO0_A (0x38)
+	*
+	* @param[in]	offset 		LDO Output Channel 0 target output voltage offset field to be read.
+	*							0b0 = No Offset
+	*							0b1 = 1.325V Offset
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset);
+
+	/**
+	* @brief		Get LDO Output Channel 0 Target Output Voltage. Bit 7.
+	*				CNFG_LDO0_A (0x38)
+	*
+	* @param[out]	offset 		LDO Output Channel 0 target output voltage offset field to be read.
+	*							0b0 = No Offset
+	*							0b1 = 1.325V Offset
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_LDO0_B (0x39) 
+	*  - Bit Fields    : [2:0]
+	*  - Default       : 0x0
+	*  - Description   : Enable Control for LDO 0.
+	*/
+	typedef enum {
+		EN_LDO_FPS_SLOT_0,
+		EN_LDO_FPS_SLOT_1,
+		EN_LDO_FPS_SLOT_2,
+		EN_LDO_FPS_SLOT_3,
+		EN_LDO_OFF,
+		EN_LDO_SAME_AS_0X04,
+		EN_LDO_ON,
+		EN_LDO_SAME_AS_0X06
+	}decode_en_ldo_t;
+
+	/**
+	* @brief		Set Enable Control for LDO Channel 0.
+	*
+	* @param[in]	en_ldo 	Enable control for LDO channel 0 field to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_en_ldo(decode_en_ldo_t en_ldo);
+
+	/**
+	* @brief		Get Enable Control for LDO Channel 0.
+	*
+	* @param[out]	en_ldo 	Enable control for LDO channel x field to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_en_ldo(decode_en_ldo_t *en_ldo);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_LDO0_B (0x39) 
+	*  - Bit Fields    : [3]
+	*  - Default       : 0x0
+	*  - Description   : LDO Channel 0 Active-Discharge Enable.
+	*/
+	typedef enum {
+		ADE_LDO_DISABLED,
+		ADE_LDO_ENABLED
+	}decode_ade_ldo_t;
+
+	/**
+	* @brief		Set LDO Channel 0 Active-Discharge Enable.
+	*
+	* @param[in]	ade_ldo LDO channel 0 active-discharge enable bit to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_ade_ldo(decode_ade_ldo_t ade_ldo);
+
+	/**
+	* @brief		Get LDO Channel 0 Active-Discharge Enable.
+	*
+	* @param[out]	ade_ldo LDO channel 0 active-discharge enable bit to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_ade_ldo(decode_ade_ldo_t *ade_ldo);
+
+	/**
+	* @brief Register Configuration
+	*
+	* @details
+	*  - Register      : CNFG_LDO0_B (0x39)
+	*  - Bit Fields    : [4]
+	*  - Default       : 0x0
+	*  - Description   : Operation mode of LDO 0.
+	*/
+	typedef enum {
+		LDO_MD_LDO_MODE,
+		LDO_MD_LSW_MODE
+	}decode_ldo_md_t;
+
+	/**
+	* @brief		Set Operation mode of LDO0.
+	*
+	* @param[in]	mode 	Operation mode of LDO0 bit to be written.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int set_ldo_md(decode_ldo_md_t mode);
+
+	/**
+	* @brief		Get Operation mode of LDO0.
+	*
+	* @param[out]	mode 	Operation mode of LDO0 bit to be read.
+	*
+	* @return		0 on success, error code on failure.
+	*/
+	int get_ldo_md(decode_ldo_md_t *mode);
+
+	/**
+	 * @brief	Disable all interrupts
+	 *
+	 * @return	0 on success, error code on failure
+	 */
+	int irq_disable_all();
+
+	/**
+	 * @brief		Set Interrupt Handler for a Specific Interrupt ID.
+	 *
+	 * @param[in]	id reg_bit_reg_bit_int_glbl_t 	id, one of INTR_ID_*.
+	 * @param[in]	func 					Interrupt handler function.
+	 * @param[in]	cb 						Interrupt handler data.
+	 */
+	void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb);
+};
+#endif
diff -r 000000000000 -r 55f664e8c56c MAX77643_2_regs.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77643_2_regs.h	Fri Aug 26 14:20:53 2022 +0300
@@ -0,0 +1,662 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MAX77643_2_REGS_H_
+#define MAX77643_2_REGS_H_
+
+/**
+ * @brief INT_GLBL0 Register
+ *
+ * Address : 0x00
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpi0_f    : 1;    /**< GPI Falling Interrupt. Bit 0.
+                                             Note that "GPI" refers to the GPIO programmed to be an input.
+                                             0 = No GPI falling edges have occurred since the last time this bit was read.
+                                             1 = A GPI falling edge has occurred since the last time this bit was read. */
+        unsigned char gpi0_r    : 1;    /**< GPI Rising Interrupt. Bit 1. 
+                                             Note that "GPI" refers to the GPIO programmed to be an input.
+                                             0 = No GPI rising edges have occurred since the last time this bit was read. 
+                                             1 = A GPI rising edge has occurred since the last time this bit was read. */
+        unsigned char nen_f     : 1;    /**< nEN Falling Interrupt.Bit 2.
+                                             0 = No nEN falling edges have occurred since the last time this bit was read.
+                                             1 = A nEN falling edge as occurred since the last time this bit was read. */
+        unsigned char nen_r     : 1;    /**< nEN Rising Interrupt. Bit 3.
+                                             0 = No nEN rising edges have occurred since the last time this bit was read.
+                                             1 = A nEN rising edge as occurred since the last time this bit was read. */
+        unsigned char tjal1_r   : 1;    /**< Thermal Alarm 1 Rising Interrupt. Bit 4.
+                                             0 = The junction temperature has not risen above TJAL1 since the last time this bit was read.
+                                             1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */
+        unsigned char tjal2_r   : 1;    /**< Thermal Alarm 2 Rising Interrupt. Bit 5.
+                                             0 = The junction temperature has not risen above TJAL2 since the last time this bit was read.
+                                             1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */
+        unsigned char dod_r     : 1;    /**< LDO Dropout Detector Rising Interrupt. Bit 6.
+                                             0 = The LDO has not detected dropout since the last time this bit was read.
+                                             1 = The LDO has detected dropout since the last time this bit was read.  */
+        unsigned char rsvd      : 1;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */
+    } bits;
+} reg_int_glbl0_t;
+
+/**
+ * @brief INT_GLBL1 Register
+ *
+ * Address : 0x01
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpi1_f    : 1;    /**< GPI Falling Interrupt. Bit 0.
+                                             Note that "GPI" refers to the GPIO programmed to be an input.
+                                             0 = No GPI falling edges have occurred since the last time this bit was read.
+                                             1 = A GPI falling edge has occurred since the last time this bit was read. */
+        unsigned char gpi1_r    : 1;    /**< GPI Rising Interrupt. Bit 1.
+                                             Note that "GPI" refers to the GPIO programmed to be an input.
+                                             0 = No GPI rising edges have occurred since the last time this bit was read. 
+                                             1 = A GPI rising edge has occurred since the last time this bit was read. */
+        unsigned char sbb0_f    : 1;    /**< SBB0 Fault Indicator. Bit 2.
+                                             0 = No fault has occurred on SBB0 since the last time this bit was read.
+                                             1 = SBB0 has fallen out of regulation since the last time this bit was read. */
+		unsigned char sbb1_f    : 1;    /**< SBB1 Fault Indicator. Bit 3.
+                                             0 = No fault has occurred on SBB1 since the last time this bit was read.
+                                             1 = SBB1 has fallen out of regulation since the last time this bit was read. */
+		unsigned char sbb2_f    : 1;    /**< SBB2 Fault Indicator. Bit 4.
+                                             0 = No fault has occurred on SBB2 since the last time this bit was read.
+                                             1 = SBB2 has fallen out of regulation since the last time this bit was read. */
+        unsigned char ldo_f     : 1;    /**< LDO0 Fault Interrupt. Bit 5.
+                                             0 = No fault has occurred on LDO0 since the last time this bit was read.
+                                             1 = LDO0 has fallen out of regulation since the last time this bit was read. */
+        unsigned char rsvd      : 2;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
+    } bits;
+} reg_int_glbl1_t;
+
+/**
+ * @brief ERCFLAG Register
+ *
+ * Address : 0x02
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char tovld         : 1;    /**< Thermal Overload. Bit 0.
+                                                0 = Thermal overload has not occurred since the last read of this register.
+                                                1 = Thermal overload has occurred since the list read of this register.
+                                                This indicates that the junction temperature has exceeded 165ºC. */
+        unsigned char inovlo        : 1;    /**< IN Domain Overvoltage Lockout. Bit 1.
+                                                0 = The IN domain overvoltage lockout has not occurred since the last read of this register.
+                                                1 = The IN domain overvoltage lockout has occurred since the last read of this register */
+        unsigned char inuvlo        : 1;    /**< IN Domain Undervoltage Lockout. Bit 2.
+                                                0 = The IN domain undervoltage lockout has not occurred since the last read of this register. 
+                                                1 = The IN domain undervoltage lockout has occurred since the last read of this register */
+        unsigned char mrst_f        : 1;    /**< Manual Reset Timer. Bit 3.
+                                                0 = A Manual Reset has not occurred since this last read of this register.
+                                                1 = A Manual Reset has occurred since this last read of this register. */
+        unsigned char sft_off_f     : 1;    /**< Software Off Flag. Bit 4.
+                                                0 = The SFT_OFF function has not occurred since the last read of this register.
+                                                1 = The SFT_OFF function has occurred since the last read of this register. */
+        unsigned char sft_crst_f    : 1;    /**< Software Cold Reset Flag. Bit 5.
+                                                0 = The software cold reset has not occurred since the last read of this register.
+                                                1 = The software cold reset has occurred since the last read of this register. */
+        unsigned char wdt_exp_f     : 1;    /**< Watchdog Timer OFF or RESET Flag. Bit 6.
+                                                This bit sets when the watchdog timer expires and causes a power-off or a reset; based on WDT_MODE bitfield setting. 
+                                                0 = Watchdog timer has not caused a power-off or reset since the last time this bit was read.
+                                                1 = Watchdog timer has expired and caused a power-off or reset since the last time this bit was read.  */
+        unsigned char sbb_fault_f   : 1;    /**< SBBx Fault and Shutdown Flag. Bit 7.
+                                                This bit sets when a SBBx fault and consequent SBBx shutdown occurs.  
+                                                0 = No SBB shutdown occurred since the last time this bit was read.  
+                                                1 = SBBx fault and SBB shutdown occurred since the last time this bit was read. */
+    } bits;
+} reg_ercflag_t;
+
+/**
+ * @brief STAT_GLBL Register
+ *
+ * Address : 0x03
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char stat_irq  : 1;    /**< Software Version of the nIRQ MOSFET gate drive. Bit 0.
+                                             0 = unmasked gate drive is logic low 
+                                             1 = unmasked gate drive is logic high */
+        unsigned char stat_en   : 1;    /**< Debounced Status for the nEN input. Bit 1.
+                                             0 = nEN is not active (logic high) 
+                                             1 = nEN is active (logic low) */
+        unsigned char tjal1_s   : 1;    /**< Thermal Alarm 1 Status. Bit 2.
+                                             0 = The junction temperature is less than TJAL1 
+                                             1 = The junction temperature is greater than TJAL1 */
+        unsigned char tjal2_s   : 1;    /**< Thermal Alarm 2 Status. Bit 3.
+                                             0 = The junction temperature is less than TJAL2 
+                                             1 = The junction temperature is greater than TJAL2 */
+        unsigned char dod_s     : 1;    /**< LDO1 Dropout Detector Rising Status. Bit 4.
+                                             0 = LDO1 is not in dropout 
+                                             1 = LDO1 is in dropout */
+        unsigned char rsvd      : 1;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 5. */
+        unsigned char bok       : 1;    /**< BOK Interrupt Status. Bit 6.
+                                             0 = Main Bias is not ready. 
+                                             1 = Main Bias enabled and ready.  */
+        unsigned char didm      : 1;    /**< Device Identification Bits for Metal Options. Bit 7.
+                                             0 = MAX77643_2 
+                                             1 = Reserved */
+    } bits;
+} reg_stat_glbl_t;
+
+/**
+ * @brief INTM_GLBL0 Register
+ *
+ * Address : 0x04
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpi0_fm   : 1;    /**< GPI Falling Interrupt Mask. Bit 0. 
+                                             0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to GPI_F. */
+        unsigned char gpi0_rm   : 1;    /**< GPI Rising Interrupt Mask. Bit 1. 
+                                             0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to GPI_R. */
+        unsigned char nen_fm    : 1;    /**< nEN Falling Interrupt Mask. Bit 2.
+                                             0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to nEN_F. */
+        unsigned char nen_rm    : 1;    /**< nEN Rising Interrupt Mask. Bit 3.
+                                             0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to nEN_R. */
+        unsigned char tjal1_rm  : 1;    /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4.
+                                             0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to TJAL1_R. */
+        unsigned char tjal2_rm  : 1;    /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5.
+                                             0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to TJAL2_R. */
+        unsigned char dod_rm    : 1;    /**< LDO Dropout Detector Rising Interrupt Mask. Bit 6.
+                                             0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to DOD1_R.  */
+        unsigned char rsvd      : 1;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */
+    } bits;
+} reg_intm_glbl0_t;
+
+/**
+ * @brief INTM_GLBL1 Register
+ *
+ * Address : 0x05
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpi1_fm   : 1;    /**< GPI Falling Interrupt Mask. Bit 0. 
+                                             0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to GPI_F. */
+        unsigned char gpi1_rm   : 1;    /**< GPI Rising Interrupt Mask. Bit 1. 
+                                             0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared. 
+                                             1 = Masked. nIRQ does not go low due to GPI_R. */
+        unsigned char sbb0_fm  : 1;    /**< SBB0 Fault Interrupt Mask. Bit 2.
+                                             0 = Unmasked. If SBB0_F goes from 0 to 1, then nIRQ goes low. 
+											 nIRQ goes high when all interrupt bits are cleared..
+                                             1 = Masked. nIRQ does not go low due to SBB0_F. */
+        unsigned char sbb1_fm  : 1;    /**< SBB1 Fault Interrupt Mask. Bit 3.
+                                             0 = Unmasked. If SBB1_F goes from 0 to 1, then nIRQ goes low. 
+											 nIRQ goes high when all interrupt bits are cleared..
+                                             1 = Masked. nIRQ does not go low due to SBB1_F. */
+        unsigned char sbb2_fm  : 1;    /**< SBB2 Fault Interrupt Mask. Bit 4.
+                                             0 = Unmasked. If SBB2_F goes from 0 to 1, then nIRQ goes low. 
+											 nIRQ goes high when all interrupt bits are cleared..
+                                             1 = Masked. nIRQ does not go low due to SBB2_F. */
+        unsigned char ldo_m     : 1;    /**< LDO0 Fault Interrupt. Bit 5.
+                                             0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. 
+                                             nIRQ goes high when all interrupt bits are cleared.
+                                             1 = Masked. nIRQ does not go low due to LDO0_F. */
+        unsigned char rsvd      : 2;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
+    } bits;
+} reg_intm_glbl1_t;
+
+/**
+ * @brief CNFG_GLBL0 Register
+ *
+ * Address : 0x06
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char sft_ctrl  : 2;    /**< Software Reset Functions. Bit 1:0. 
+                                             0b00 = No Action 
+                                             0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. 
+                                             0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 
+                                             0b11 = Auto Wake Up (SFT_AUTO). */
+        unsigned char dben_nen  : 1;    /**< Debounce Timer Enable for the nEN Pin. Bit 2.
+                                             0 = 500μs Debounce 
+                                             1 = 30ms Debounce */
+        unsigned char nen_mode  : 2;    /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 4:3.
+                                             0b00 = Push-button mode 
+											 0b01 = Slide-switch mode 
+											 0b10 = Logic mode 
+											 0b11 = Reserved */
+        unsigned char sbia_lpm  : 1;    /**< Main Bias Low-Power Mode Software Request. Bit 5.
+                                             0 = Main Bias requested to be in Normal-Power Mode by software. 
+                                             1 = Main Bias request to be in Low-Power Mode by software. */
+        unsigned char t_mrst    : 1;    /**< Sets the Manual Reset Time (tMRST). Bit 6.
+                                             0 = 8s 
+                                             1 = 4s  */
+        unsigned char pu_dis    : 1;    /**< nEN Internal Pullup Resistor. Bit 7.
+                                             0 = Strong internal nEN pullup (200kΩ) 
+                                             1 = Weak internal nEN pullup (10MΩ) */
+    } bits;
+} reg_cnfg_glbl0_t;
+
+/**
+ * @brief CNFG_GLBL1 Register
+ *
+ * Address : 0x07
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char auto_wkt      : 2;    /**< Auto Wake-Up Timer. Bit 1:0. 
+                                                0b00 = 100ms Auto Wake-up Time
+                                                0b01 = 200ms Auto Wake-up Time
+                                                0b10 = 500ms Auto Wake-up Time
+                                                0b11 = 1000ms Auto Wake-up Time */
+        unsigned char sbb_f_shutdn  : 1;    /**< SBB Shutdown from SBB Fault. Bit 2.
+                                                0 = 500μs Debounce 
+                                                1 = 30ms Debounce */
+        unsigned char rsvd          : 5;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care */
+   } bits;
+} reg_cnfg_glbl1_t;
+
+/**
+ * @brief CNFG_GPIO0 Register
+ *
+ * Address : 0x08
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpo_dir   : 1;    /**< GPIO Direction. Bit 0. 
+                                             0 = General purpose output (GPO) 
+                                             1 = General purpose input (GPI) */
+        unsigned char gpo_di    : 1;    /**< GPIO Digital Input Value. Bit 1.
+                                             0 = Input logic low 
+                                             1 = Input logic high */
+        unsigned char gpo_drv   : 1;    /**< General Purpose Output Driver Type. Bit 2.
+                                             This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 
+                                             0 = Open-Drain 
+                                             1 = Push-Pull */
+        unsigned char gpo_do    : 1;    /**< General Purpose Output Data Output. Bit 3.
+                                             This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 
+                                             0 = GPIO is output is logic low 
+                                             1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
+        unsigned char dben_gpi  : 1;    /**< General Purpose Input Debounce Timer Enable. Bit 4.
+                                             0 = no debounce 
+                                             1 = 30ms debounce */
+        unsigned char alt_gpio  : 1;    /**< Alternate Mode Enable for GPIO0. Bit 5.
+                                             0 = Standard GPIO. 
+                                             1 = Active-high input, Force USB Suspend (FUS). FUS is only active if the FUS_M bit is set to 0.  */
+        unsigned char rsvd      : 2;    /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */
+    } bits;
+} reg_cnfg_gpio0_t;
+
+/**
+ * @brief CNFG_GPIO1 Register
+ *
+ * Address : 0x09
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char gpo_dir   : 1;    /**< GPIO Direction. Bit 0. 
+                                             0 = General purpose output (GPO) 
+                                             1 = General purpose input (GPI) */
+        unsigned char gpo_di    : 1;    /**< GPIO Digital Input Value. Bit 1.
+                                             0 = Input logic low 
+                                             1 = Input logic high */
+        unsigned char gpo_drv   : 1;    /**< General Purpose Output Driver Type. Bit 2.
+                                             This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 
+                                             0 = Open-Drain 
+                                             1 = Push-Pull */
+        unsigned char gpo_do    : 1;    /**< General Purpose Output Data Output. Bit 3.
+                                             This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 
+                                             0 = GPIO is output is logic low 
+                                             1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
+        unsigned char dben_gpi  : 1;    /**< General Purpose Input Debounce Timer Enable. Bit 4.
+                                             0 = no debounce 
+                                             1 = 30ms debounce */
+        unsigned char alt_gpio  : 1;    /**< Alternate Mode Enable for GPIO1. Bit 5.
+                                             0 = Standard GPIO. 
+                                             1 = Active-high output of SBB2's Flexible Power Sequencer (FPS) slot. */
+        unsigned char rsvd      : 2;    /**< Reserved. Bit 7:6.
+                                             Unutilized bit. Write to 0. Reads are don't care. */
+    } bits;
+} reg_cnfg_gpio1_t;
+
+/**
+ * @brief CID Register
+ *
+ * Address : 0x10
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char cid   : 5;    /**< Chip Identification Code. Bit 4:0.
+                                    The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
+        unsigned char       : 3;    /**< Bit 7:5. */
+    } bits;
+} reg_cid_t;
+
+/**
+ * @brief CNFG_WDT Register
+ *
+ * Address : 0x17
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+        unsigned char wdt_lock  : 1;    /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. 
+                                             0 = Watchdog timer can be enabled and disabled with WDT_EN. 
+                                             1 = Watchdog timer can not be disabled with WDT_EN. 
+                                             However, WDT_EN can still be used to enable the watchdog timer. */
+        unsigned char wdt_en    : 1;    /**< Watchdog Timer Enable. Bit 1.
+                                             0 = Watchdog timer is not enabled. 
+                                             1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */
+        unsigned char wdt_clr   : 1;    /**< Watchdog Timer Clear Control. Bit 2.
+                                             0 = Watchdog timer period is not reset. 
+                                             1 = Watchdog timer is reset back to tWD. */
+        unsigned char wdt_mode  : 1;    /**< Watchdog Timer Expired Action. Bit 3.
+                                             0 = Watchdog timer expire causes power-off. 
+                                             1 = Watchdog timer expire causes power-reset. */
+        unsigned char wdt_per   : 2;    /**< Watchdog Timer Period. Bit 5:4.
+                                             0b00 = 16 seconds      0b01 = 32 seconds 
+                                             0b10 = 64 seconds      0b11 = 128 seconds. */
+        unsigned char rsvd      : 2;    /**< Reserved. Bit 7:6.
+                                             Unutilized bit. Write to 0. Reads are don't care. */
+    } bits;
+} reg_cnfg_wdt_t;
+
+/**
+ * @brief CNFG_SBB_TOP
+ * 
+ * Address : 0x28
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char drv_sbb   : 2;    /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0.
+                                            0b00 = Fastest transition time 
+											0b01 = A little slower than 0b00 
+											0b10 = A little slower than 0b01 
+											0b11 = A little slower than 0b10 */
+		unsigned char 		    : 5;    /**< Bit 6:2.*/
+        unsigned char dis_lpm   : 1;    /**< Disables the automatic Low Power Mode for Each SIMO Channel. Bit 7.
+											0b0 = Automatic Low Power Mode for each SIMO channel 
+											0b1 = Disable LPM feature for each SIMO channel */
+    } bits;
+} reg_cnfg_sbb_top_t;
+
+/**
+ * @brief CNFG_SBB0_A
+ * 
+ * Address : 0x29
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char tv_sbb0   : 8;    /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0.
+                                            0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 
+											0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 
+											0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 
+											... 
+											0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 
+											0xC8 to 0xFF = 5.500V */
+    } bits;
+} reg_cnfg_sbb0_a_t;
+
+/**
+ * @brief CNFG_SBB0_B
+ * 
+ * Address : 0x2A
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char en_sbb0       : 3;    /**< Enable Control for SIMO Buck-Boost Channel 0, 
+                                                selecting either an FPS slot the channel powers-up and powers-down in 
+                                                or whether the channel is forced on or off. Bit 2:0.
+                                                0b000 = FPS slot 0      0b001 = FPS slot 1 
+                                                0b010 = FPS slot 2      0b011 = FPS slot 3      
+                                                0b100 = Off irrespective of FPS 
+                                                0b101 = same as 0b100   0b110 = On irrespective of FPS 
+                                                0b111 = same as 0b110 */
+        unsigned char ade_sbb0      : 1;    /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3.
+                                                0 = The active discharge function is disabled. 
+                                                When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 
+                                                1 = The active discharge function is enabled. 
+                                                When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+        unsigned char ip_sbb0       : 2;    /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 5:4
+                                                0b00 = 1.000A       0b01 = 0.750A 
+                                                0b10 = 0.500A       0b11 = 0.333A*/
+        unsigned char op_mode0      : 2;    /**<  Operation mode of SBB0. Bit 6.
+                                                0b00 = Automatic 
+												0b01 = Buck mode 
+												0b10 = Boost mode 
+												0b11 = Buck-boost mode*/
+    } bits;
+} reg_cnfg_sbb0_b_t;
+
+/**
+ * @brief CNFG_SBB1_A
+ * 
+ * Address : 0x2B
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char tv_sbb1   : 8;    /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 7:0.
+                                            0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 
+											0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 
+											0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 
+											... 
+											0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 
+											0xC8 to 0xFF = 5.500V */
+    } bits;
+} reg_cnfg_sbb1_a_t;
+
+/**
+ * @brief CNFG_SBB1_B
+ * 
+ * Address : 0x3C
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char en_sbb1       : 3;    /**< Enable Control for SIMO Buck-Boost Channel 1, 
+                                                selecting either an FPS slot the channel powers-up and powers-down in 
+                                                or whether the channel is forced on or off. Bit 2:0.
+                                                0b000 = FPS slot 0      0b001 = FPS slot 1 
+                                                0b010 = FPS slot 2      0b011 = FPS slot 3      
+                                                0b100 = Off irrespective of FPS 
+                                                0b101 = same as 0b100   0b110 = On irrespective of FPS 
+                                                0b111 = same as 0b110 */
+        unsigned char ade_sbb1      : 1;    /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3.
+                                                0 = The active discharge function is disabled. 
+                                                When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 
+                                                1 = The active discharge function is enabled. 
+                                                When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+        unsigned char ip_sbb1       : 2;    /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 5:4.
+                                                0b00 = 1.000A       0b01 = 0.750A 
+                                                0b10 = 0.500A       0b11 = 0.333A*/
+        unsigned char op_mode1      : 2;    /**<  Operation mode of SBB1. Bit 7:6.
+                                                0b00 = Automatic 
+												0b01 = Buck mode 
+												0b10 = Boost mode 
+												0b11 = Buck-boost mode*/
+    } bits;
+} reg_cnfg_sbb1_b_t;
+
+/**
+ * @brief CNFG_SBB2_A
+ * 
+ * Address : 0x2D
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char tv_sbb2   : 8;    /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 7:0.
+                                            0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 
+											0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 
+											0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 
+											... 
+											0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 
+											0xC8 to 0xFF = 5.500V */
+    } bits;
+} reg_cnfg_sbb2_a_t;
+
+/**
+ * @brief CNFG_SBB2_B
+ * 
+ * Address : 0x2E
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char en_sbb2       : 3;    /**< Enable Control for SIMO Buck-Boost Channel 2, 
+                                                selecting either an FPS slot the channel powers-up and powers-down in 
+                                                or whether the channel is forced on or off. Bit 2:0.
+                                                0b000 = FPS slot 0      0b001 = FPS slot 1 
+                                                0b010 = FPS slot 2      0b011 = FPS slot 3      
+                                                0b100 = Off irrespective of FPS 
+                                                0b101 = same as 0b100   0b110 = On irrespective of FPS 
+                                                0b111 = same as 0b110 */
+        unsigned char ade_sbb2      : 1;    /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3.
+                                                0 = The active discharge function is disabled. 
+                                                When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 
+                                                1 = The active discharge function is enabled. 
+                                                When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+        unsigned char ip_sbb2       : 2;    /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4.
+                                                0b00 = 1.000A       0b01 = 0.750A 
+                                                0b10 = 0.500A       0b11 = 0.333A*/
+        unsigned char op_mode2      : 2;    /**< Operation mode of SBB2. Bit 7:6.
+                                                0b00 = Automatic 
+												0b01 = Buck mode 
+												0b10 = Boost mode 
+												0b11 = Buck-boost mode*/
+    } bits;
+} reg_cnfg_sbb2_b_t;
+
+/**
+ * @brief CNFG_DVS_SBB0_A
+ * 
+ * Address : 0x2F
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char tv_sbb0_dvs   : 8;    /**<  SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0.
+                                                0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 
+												0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 
+												0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 
+												... 
+												0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 
+												0xC8 to 0xFF = 5.500V */
+    } bits;
+} reg_cnfg_dvs_sbb0_a_t;
+
+/**
+ * @brief CNFG_LDO0_A
+ * 
+ * Address : 0x38
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char tv_ldo0      : 7;    /**<  LDO0 Target Output Voltage. Bit 6:0.
+                                                0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 
+												0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 
+												0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 
+												... 
+												0x7E = 3.650V
+												0x7F = 3.675V 
+												When TV_LDO[7] = 0, TV_LDO[6:0] sets the
+												LDO's output voltage range from 0.5V to 3.675V.
+												When TV_LDO[7] = 1, TV_LDO[6:0] sets the
+												LDO's output voltage from 1.825V to 5V. */
+		unsigned char tv_ofs_ldo   	: 1; 	/**< LDO0 Output Voltage. Bit7. 
+												This bit applies a 1.325V offset to the output voltage of the LDO0. 
+												0b0 = No Offset, 0b1 = 1.325V Offset
+												*/
+		
+    } bits;
+} reg_cnfg_ldo0_a_t;
+
+/**
+ * @brief CNFG_LDO0_B
+ * 
+ * Address : 0x39
+ */
+typedef union {
+    unsigned char raw;
+    struct 
+    {
+        unsigned char en_ldo        : 3;    /**< Enable Control for LDO0, 
+                                                selecting either an FPS slot the channel powers-up and 
+												powersdown in or whether the channel is forced on or off.  Bit 2:0.
+                                                0b000 = FPS slot 0      0b001 = FPS slot 1 
+                                                0b010 = FPS slot 2      0b011 = FPS slot 3      
+                                                0b100 = Off irrespective of FPS 
+                                                0b101 = same as 0b100   0b110 = On irrespective of FPS 
+                                                0b111 = same as 0b110 */
+        unsigned char ade_ldo       : 1;    /**< LDO0 Active-Discharge Enable. Bit 3.
+                                                0 = The active discharge function is disabled.                                            
+                                                1 = The active discharge function is enabled.*/
+        unsigned char ldo_md        : 1;    /**< Operation Mode of LDO0. Bit 4.
+                                                0b0 = Low dropout linear regulator (LDO) mode
+												0b1 = Load switch (LSW) mode*/
+        unsigned char rsvd    		: 3;    /**< Reserved. Unutilized bit. Write to 0. Reads are don't care.  */
+    } bits;
+} reg_cnfg_ldo0_b_t;
+
+#endif /* MAX77643_2_REGS_H_ */