Maxim Integrated / MAX5715

Maxim Integrated MAX5715 12-bit 4-channel voltage-output DAC

Dependents:   MAX5715BOB_Tester MAX5715BOB_12bit_4ch_SPI_DAC MAX5715BOB_Serial_Tester

MAX5715.cpp@4:500c80398f90, 2019-08-28 (annotated)

Committer:
whismanoid
Date:
Wed Aug 28 03:21:35 2019 -0700
Revision:
4:500c80398f90
Parent:
3:a3f0518094f4
Child:
5:7894decf9375
Rename REF argument 'ref' instead of 'value'

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 0:777851395940 1 // /*******************************************************************************
whismanoid 0:777851395940 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 0:777851395940 3 // *
whismanoid 0:777851395940 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 0:777851395940 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 0:777851395940 6 // * to deal in the Software without restriction, including without limitation
whismanoid 0:777851395940 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 0:777851395940 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 0:777851395940 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 0:777851395940 10 // *
whismanoid 0:777851395940 11 // * The above copyright notice and this permission notice shall be included
whismanoid 0:777851395940 12 // * in all copies or substantial portions of the Software.
whismanoid 0:777851395940 13 // *
whismanoid 0:777851395940 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 0:777851395940 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 0:777851395940 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 0:777851395940 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 0:777851395940 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 0:777851395940 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 0:777851395940 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 0:777851395940 21 // *
whismanoid 0:777851395940 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 0:777851395940 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 0:777851395940 24 // * Products, Inc. Branding Policy.
whismanoid 0:777851395940 25 // *
whismanoid 0:777851395940 26 // * The mere transfer of this software does not imply any licenses
whismanoid 0:777851395940 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 0:777851395940 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 0:777851395940 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 0:777851395940 30 // * ownership rights.
whismanoid 0:777851395940 31 // *******************************************************************************
whismanoid 0:777851395940 32 // */
whismanoid 0:777851395940 33 // *********************************************************************
whismanoid 0:777851395940 34 // @file MAX5715.cpp
whismanoid 0:777851395940 35 // *********************************************************************
whismanoid 0:777851395940 36 // Device Driver file
whismanoid 0:777851395940 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 0:777851395940 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 0:777851395940 39 // System Name = ExampleSystem
whismanoid 0:777851395940 40 // System Description = Device driver example
whismanoid 0:777851395940 41
whismanoid 0:777851395940 42 #include "MAX5715.h"
whismanoid 0:777851395940 43
whismanoid 0:777851395940 44 // Device Name = MAX5715
whismanoid 0:777851395940 45 // Device Description = Ultra-Small, 12-Bit, 4-Channel, Buffered Output Voltage DAC with Internal Reference and SPI Interface
whismanoid 0:777851395940 46 // Device Manufacturer = Maxim Integrated
whismanoid 0:777851395940 47 // Device PartNumber = MAX5715AAUD+
whismanoid 0:777851395940 48 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 0:777851395940 49 //
whismanoid 0:777851395940 50 // DAC NumChannels = 4
whismanoid 0:777851395940 51 // DAC ResolutionBits = 12
whismanoid 0:777851395940 52 //
whismanoid 0:777851395940 53 // SPI CS = ActiveLow
whismanoid 0:777851395940 54 // SPI FrameStart = CS
whismanoid 0:777851395940 55 // SPI CPOL = 1
whismanoid 0:777851395940 56 // SPI CPHA = 0
whismanoid 0:777851395940 57 // SPI MOSI and MISO Data are both stable on Falling edge of SCLK
whismanoid 0:777851395940 58 // SPI SCLK Idle High
whismanoid 0:777851395940 59 // SPI SCLKMaxMHz = 50
whismanoid 0:777851395940 60 // SPI SCLKMinMHz = 0
whismanoid 0:777851395940 61 //
whismanoid 0:777851395940 62 // InputPin Name = LDAC#
whismanoid 0:777851395940 63 // InputPin Description = Dedicated Active-Low Asynchronous Load DAC.
whismanoid 0:777851395940 64 // InputPin Function = Trigger
whismanoid 0:777851395940 65 //
whismanoid 0:777851395940 66 // InputPin Name = CLR#
whismanoid 0:777851395940 67 // InputPin Description = Active-Low Clear Input.
whismanoid 0:777851395940 68 // InputPin Function = Trigger
whismanoid 0:777851395940 69 //
whismanoid 0:777851395940 70 // InputPin Name = REF
whismanoid 0:777851395940 71 // InputPin Description = Reference Voltage Input/Output.
whismanoid 0:777851395940 72 // Software selectable to be external reference or internal 2.048V, 2.500V, or 4.096V reference.
whismanoid 0:777851395940 73 // Default is external reference mode.
whismanoid 0:777851395940 74 // InputPin Function = Reference
whismanoid 0:777851395940 75 //
whismanoid 0:777851395940 76 // OutputPin Name = OUTA
whismanoid 0:777851395940 77 // OutputPin Description = Buffered Channel A DAC Output
whismanoid 0:777851395940 78 // OutputPin Function = Analog
whismanoid 0:777851395940 79 //
whismanoid 0:777851395940 80 // OutputPin Name = OUTB
whismanoid 0:777851395940 81 // OutputPin Description = Buffered Channel B DAC Output
whismanoid 0:777851395940 82 // OutputPin Function = Analog
whismanoid 0:777851395940 83 //
whismanoid 0:777851395940 84 // OutputPin Name = OUTC
whismanoid 0:777851395940 85 // OutputPin Description = Buffered Channel C DAC Output
whismanoid 0:777851395940 86 // OutputPin Function = Analog
whismanoid 0:777851395940 87 //
whismanoid 0:777851395940 88 // OutputPin Name = OUTD
whismanoid 0:777851395940 89 // OutputPin Description = Buffered Channel D DAC Output
whismanoid 0:777851395940 90 // OutputPin Function = Analog
whismanoid 0:777851395940 91 //
whismanoid 0:777851395940 92 // OutputPin Name = RDY#
whismanoid 0:777851395940 93 // OutputPin Description = SPI RDY Output. In daisy-chained applications connect RDY to the CSB of the next device in the chain.
whismanoid 0:777851395940 94 // OutputPin Function = DaisyChain
whismanoid 0:777851395940 95 //
whismanoid 0:777851395940 96 // SupplyPin Name = VDD
whismanoid 0:777851395940 97 // SupplyPin Description = Supply Voltage Input. Bypass VDD with a 0.1uF capacitor to GND.
whismanoid 0:777851395940 98 // SupplyPin VinMax = 5.5
whismanoid 0:777851395940 99 // SupplyPin VinMin = 2.7 (unless configured DAC VRefInternal = 4.096V, then VinMin = 4.5V)
whismanoid 0:777851395940 100 // SupplyPin Function = Analog
whismanoid 0:777851395940 101 //
whismanoid 0:777851395940 102 // SupplyPin Name = VDDIO
whismanoid 0:777851395940 103 // SupplyPin Description = Digital Interface Power-Supply Input
whismanoid 0:777851395940 104 // SupplyPin VinMax = 5.5
whismanoid 0:777851395940 105 // SupplyPin VinMin = 1.8
whismanoid 0:777851395940 106 // SupplyPin Function = Digital
whismanoid 0:777851395940 107 //
whismanoid 0:777851395940 108
whismanoid 0:777851395940 109 // CODE GENERATOR: class constructor definition
whismanoid 0:777851395940 110 MAX5715::MAX5715(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 0:777851395940 111 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 0:777851395940 112 DigitalOut &LDACb_pin, // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 113 DigitalOut &CLRb_pin, // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 114 // AnalogOut &REF_pin, // Reference Input to MAX5715 device
whismanoid 0:777851395940 115 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 0:777851395940 116 // AnalogIn &OUTA_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 117 // AnalogIn &OUTB_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 118 // AnalogIn &OUTC_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 119 // AnalogIn &OUTD_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 120 // DigitalIn &RDYb_pin, // Digital DaisyChain Output from MAX5715 device
whismanoid 0:777851395940 121 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 0:777851395940 122 MAX5715_ic_t ic_variant)
whismanoid 0:777851395940 123 // CODE GENERATOR: class constructor initializer list
whismanoid 0:777851395940 124 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 0:777851395940 125 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 0:777851395940 126 m_LDACb_pin(LDACb_pin), // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 127 m_CLRb_pin(CLRb_pin), // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 128 // m_REF_pin(REF_pin), // Reference Input to MAX5715 device
whismanoid 0:777851395940 129 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 0:777851395940 130 // m_OUTA_pin(OUTA_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 131 // m_OUTB_pin(OUTB_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 132 // m_OUTC_pin(OUTC_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 133 // m_OUTD_pin(OUTD_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 134 // m_RDYb_pin(RDYb_pin), // Digital DaisyChain Output from MAX5715 device
whismanoid 0:777851395940 135 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 0:777851395940 136 m_ic_variant(ic_variant)
whismanoid 0:777851395940 137 {
whismanoid 0:777851395940 138 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 0:777851395940 139 //
whismanoid 0:777851395940 140 // SPI CS = ActiveLow
whismanoid 0:777851395940 141 // SPI FrameStart = CS
whismanoid 0:777851395940 142 m_SPI_cs_state = 1;
whismanoid 0:777851395940 143 m_cs_pin = m_SPI_cs_state;
whismanoid 0:777851395940 144
whismanoid 0:777851395940 145 // SPI CPOL = 1
whismanoid 0:777851395940 146 // SPI CPHA = 0
whismanoid 0:777851395940 147 // SPI MOSI and MISO Data are both stable on Falling edge of SCLK
whismanoid 0:777851395940 148 // SPI SCLK Idle High
whismanoid 0:777851395940 149 m_SPI_dataMode = 2; //SPI_MODE2; // CPOL=1,CPHA=0: Falling Edge stable; SCLK idle High
whismanoid 0:777851395940 150 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 0:777851395940 151
whismanoid 0:777851395940 152 // SPI SCLKMaxMHz = 50
whismanoid 0:777851395940 153 // SPI SCLKMinMHz = 0
whismanoid 0:777851395940 154 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 0:777851395940 155 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 0:777851395940 156 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 3:a3f0518094f4 157 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 0:777851395940 158 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 0:777851395940 159 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 0:777851395940 160 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 0:777851395940 161 m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX5715 limit is 50MHz
whismanoid 0:777851395940 162 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 0:777851395940 163
whismanoid 0:777851395940 164 // TODO1: CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 0:777851395940 165 //
whismanoid 0:777851395940 166 m_LDACb_pin = 1; // output logic high -- initial value in constructor
whismanoid 0:777851395940 167 m_CLRb_pin = 1; // output logic high -- initial value in constructor
whismanoid 0:777851395940 168 }
whismanoid 0:777851395940 169
whismanoid 0:777851395940 170 // CODE GENERATOR: class destructor definition
whismanoid 0:777851395940 171 MAX5715::~MAX5715()
whismanoid 0:777851395940 172 {
whismanoid 0:777851395940 173 // do nothing
whismanoid 0:777851395940 174 }
whismanoid 0:777851395940 175
whismanoid 0:777851395940 176 // CODE GENERATOR: spi_frequency setter definition
whismanoid 3:a3f0518094f4 177 /// set SPI SCLK frequency
whismanoid 0:777851395940 178 void MAX5715::spi_frequency(int spi_sclk_Hz)
whismanoid 0:777851395940 179 {
whismanoid 0:777851395940 180 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 0:777851395940 181 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 0:777851395940 182 }
whismanoid 0:777851395940 183
whismanoid 0:777851395940 184 // CODE GENERATOR: omit global g_MAX5715_device
whismanoid 0:777851395940 185 // CODE GENERATOR: extern function declarations
whismanoid 0:777851395940 186 // CODE GENERATOR: extern function requirement MAX5715::SPIoutputCS
whismanoid 0:777851395940 187 // Assert SPI Chip Select
whismanoid 0:777851395940 188 // SPI chip-select for MAX5715
whismanoid 0:777851395940 189 //
whismanoid 0:777851395940 190 void MAX5715::SPIoutputCS(int isLogicHigh)
whismanoid 0:777851395940 191 {
whismanoid 0:777851395940 192 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 0:777851395940 193 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 0:777851395940 194 m_SPI_cs_state = isLogicHigh;
whismanoid 0:777851395940 195 m_cs_pin = m_SPI_cs_state;
whismanoid 0:777851395940 196 }
whismanoid 0:777851395940 197
whismanoid 0:777851395940 198 // CODE GENERATOR: extern function requirement MAX5715::SPIwrite24bits
whismanoid 0:777851395940 199 // SPI write 24 bits
whismanoid 0:777851395940 200 // SPI interface to MAX5715 shift 24 bits mosiData into MAX5715 DIN
whismanoid 0:777851395940 201 //
whismanoid 0:777851395940 202 void MAX5715::SPIwrite24bits(int8_t mosiData8_FF0000, int16_t mosiData16_00FFFF)
whismanoid 0:777851395940 203 {
whismanoid 0:777851395940 204 // CODE GENERATOR: extern function definition for function SPIwrite24bits
whismanoid 0:777851395940 205 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite24bits(int8_t mosiData8_FF0000, int16_t mosiData16_00FFFF)
whismanoid 0:777851395940 206 size_t byteCount = 3;
whismanoid 0:777851395940 207 static char mosiData[3];
whismanoid 0:777851395940 208 static char misoData[3];
whismanoid 0:777851395940 209 mosiData[0] = mosiData8_FF0000;
whismanoid 0:777851395940 210 mosiData[1] = (char)((mosiData16_00FFFF >> 8) & 0xFF); // MSByte
whismanoid 0:777851395940 211 mosiData[2] = (char)((mosiData16_00FFFF >> 0) & 0xFF); // LSByte
whismanoid 0:777851395940 212 //
whismanoid 0:777851395940 213 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 0:777851395940 214 //~ noInterrupts();
whismanoid 0:777851395940 215 //
whismanoid 0:777851395940 216 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 0:777851395940 217 //
whismanoid 0:777851395940 218 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 0:777851395940 219 //~ SPI.transfer(mosiData8_FF0000);
whismanoid 0:777851395940 220 //~ SPI.transfer(mosiData16_00FF00);
whismanoid 0:777851395940 221 //~ SPI.transfer(mosiData16_0000FF);
whismanoid 0:777851395940 222 //
whismanoid 0:777851395940 223 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 0:777851395940 224 //
whismanoid 0:777851395940 225 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 0:777851395940 226 //~ interrupts();
whismanoid 0:777851395940 227 //
whismanoid 0:777851395940 228 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 0:777851395940 229 //cmdLine.serial().printf(" MOSI->"));
whismanoid 0:777851395940 230 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 231 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 0:777851395940 232 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 233 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 0:777851395940 234 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 235 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 0:777851395940 236 // hex dump mosiData[0..byteCount-1]
whismanoid 0:777851395940 237 #if HAS_MICROUSBSERIAL
whismanoid 0:777851395940 238 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 0:777851395940 239 if (byteCount > 7) {
whismanoid 0:777851395940 240 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 0:777851395940 241 }
whismanoid 0:777851395940 242 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 0:777851395940 243 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 0:777851395940 244 {
whismanoid 0:777851395940 245 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 0:777851395940 246 }
whismanoid 0:777851395940 247 // hex dump misoData[0..byteCount-1]
whismanoid 0:777851395940 248 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 0:777851395940 249 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 0:777851395940 250 {
whismanoid 0:777851395940 251 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 0:777851395940 252 }
whismanoid 0:777851395940 253 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 0:777851395940 254 #endif
whismanoid 0:777851395940 255 #if HAS_DAPLINK_SERIAL
whismanoid 0:777851395940 256 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 0:777851395940 257 if (byteCount > 7) {
whismanoid 0:777851395940 258 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 0:777851395940 259 }
whismanoid 0:777851395940 260 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 0:777851395940 261 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 0:777851395940 262 {
whismanoid 0:777851395940 263 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 0:777851395940 264 }
whismanoid 0:777851395940 265 // hex dump misoData[0..byteCount-1]
whismanoid 0:777851395940 266 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 0:777851395940 267 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 0:777851395940 268 {
whismanoid 0:777851395940 269 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 0:777851395940 270 }
whismanoid 0:777851395940 271 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 0:777851395940 272 #endif
whismanoid 0:777851395940 273 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 0:777851395940 274 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 0:777851395940 275 //
whismanoid 0:777851395940 276 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 0:777851395940 277 // return misoData16;
whismanoid 0:777851395940 278 }
whismanoid 0:777851395940 279
whismanoid 0:777851395940 280 // TODO1: CODE GENERATOR: extern function GPIOoutputLDACb alias LDACboutputValue
whismanoid 0:777851395940 281 // CODE GENERATOR: extern function requirement MAX5715::LDACboutputValue
whismanoid 0:777851395940 282 // Assert MAX5715 LDAC pin : High = inactive, Low = load DAC.
whismanoid 0:777851395940 283 //
whismanoid 0:777851395940 284 void MAX5715::LDACboutputValue(int isLogicHigh)
whismanoid 0:777851395940 285 {
whismanoid 0:777851395940 286 // CODE GENERATOR: extern function definition for function LDACboutputValue
whismanoid 0:777851395940 287 // TODO1: CODE GENERATOR: extern function definition for gpio interface function LDACboutputValue
whismanoid 0:777851395940 288 // TODO1: CODE GENERATOR: gpio pin LDACb assuming member function m_LDACb_pin
whismanoid 0:777851395940 289 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 0:777851395940 290 // m_LDACb_pin.output(); // only applicable to DigitalInOut
whismanoid 0:777851395940 291 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 0:777851395940 292 m_LDACb_pin = isLogicHigh;
whismanoid 0:777851395940 293 }
whismanoid 0:777851395940 294
whismanoid 0:777851395940 295 // TODO1: CODE GENERATOR: extern function GPIOoutputCLRb alias CLRboutputValue
whismanoid 0:777851395940 296 // CODE GENERATOR: extern function requirement MAX5715::CLRboutputValue
whismanoid 0:777851395940 297 // Assert MAX5715 CLR pin : High = inactive, Low = clear DAC.
whismanoid 0:777851395940 298 //
whismanoid 0:777851395940 299 void MAX5715::CLRboutputValue(int isLogicHigh)
whismanoid 0:777851395940 300 {
whismanoid 0:777851395940 301 // CODE GENERATOR: extern function definition for function CLRboutputValue
whismanoid 0:777851395940 302 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CLRboutputValue
whismanoid 0:777851395940 303 // TODO1: CODE GENERATOR: gpio pin CLRb assuming member function m_CLRb_pin
whismanoid 0:777851395940 304 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 0:777851395940 305 // m_CLRb_pin.output(); // only applicable to DigitalInOut
whismanoid 0:777851395940 306 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 0:777851395940 307 m_CLRb_pin = isLogicHigh;
whismanoid 0:777851395940 308 }
whismanoid 0:777851395940 309
whismanoid 0:777851395940 310 // CODE GENERATOR: class member function definitions
whismanoid 0:777851395940 311 //----------------------------------------
whismanoid 0:777851395940 312 // Initialize device
whismanoid 0:777851395940 313 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 314 uint8_t MAX5715::Init(void)
whismanoid 0:777851395940 315 {
whismanoid 0:777851395940 316
whismanoid 0:777851395940 317 //----------------------------------------
whismanoid 0:777851395940 318 // Initialize device
whismanoid 0:777851395940 319 //----------------------------------------
whismanoid 0:777851395940 320 // Perform Software Reset
whismanoid 0:777851395940 321 if (!SW_RESET()) {
whismanoid 0:777851395940 322 return 0; // failure
whismanoid 0:777851395940 323 }
whismanoid 0:777851395940 324 //----------------------------------------
whismanoid 0:777851395940 325 // Turn on the reference output pin
whismanoid 0:777851395940 326 REF(REF_AlwaysOn_2V500);
whismanoid 0:777851395940 327 //
whismanoid 0:777851395940 328 //~ Serial.println(F(" success"));
whismanoid 0:777851395940 329 //~ return;
whismanoid 0:777851395940 330 return 1; // success
whismanoid 0:777851395940 331 }
whismanoid 0:777851395940 332
whismanoid 0:777851395940 333 //----------------------------------------
whismanoid 0:777851395940 334 // Return the DAC register value corresponding to physical voltage.
whismanoid 0:777851395940 335 // Does not perform any offset or gain correction.
whismanoid 0:777851395940 336 //
whismanoid 0:777851395940 337 // @pre VRef = Voltage of REF input, in Volts
whismanoid 0:777851395940 338 // @param[in] voltage = physical voltage in Volts
whismanoid 0:777851395940 339 // @return raw 12-bit MAX5715 code (right justified).
whismanoid 0:777851395940 340 uint16_t MAX5715::DACCodeOfVoltage(double voltageV)
whismanoid 0:777851395940 341 {
whismanoid 0:777851395940 342
whismanoid 0:777851395940 343 //----------------------------------------
whismanoid 0:777851395940 344 // Linear map min and max endpoints
whismanoid 0:777851395940 345 const double MaxScaleVoltage = VRef; // voltage of maximum code 0x0fff
whismanoid 0:777851395940 346 const double MinScaleVoltage = 0.0; // voltage of minimum code 0x000
whismanoid 0:777851395940 347 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 0:777851395940 348 const uint16_t MaxCode = FULL_SCALE_CODE_12BIT;
whismanoid 0:777851395940 349 const uint16_t MinCode = 0x000;
whismanoid 0:777851395940 350 double codeFraction = (voltageV - MinScaleVoltage) / (MaxScaleVoltage - MinScaleVoltage);
whismanoid 0:777851395940 351 double dacRegValueIdeal = ((codeFraction * (double)(MaxCode - MinCode + 1)) + MinCode + 0.5);
whismanoid 0:777851395940 352 uint16_t dacRegValue = (uint16_t)dacRegValueIdeal;
whismanoid 0:777851395940 353 if (dacRegValueIdeal > MaxCode)
whismanoid 0:777851395940 354 {
whismanoid 0:777851395940 355 dacRegValue = MaxCode;
whismanoid 0:777851395940 356 } else if (dacRegValueIdeal < MinCode)
whismanoid 0:777851395940 357 {
whismanoid 0:777851395940 358 dacRegValue = MinCode;
whismanoid 0:777851395940 359 }
whismanoid 0:777851395940 360 return dacRegValue;
whismanoid 0:777851395940 361 }
whismanoid 0:777851395940 362
whismanoid 0:777851395940 363 //----------------------------------------
whismanoid 0:777851395940 364 // Return the physical voltage corresponding to DAC register.
whismanoid 0:777851395940 365 // Does not perform any offset or gain correction.
whismanoid 0:777851395940 366 //
whismanoid 0:777851395940 367 // @pre VRef = Voltage of REF input, in Volts
whismanoid 0:777851395940 368 // @param[in] value_u12: raw 12-bit MAX5715 code (right justified).
whismanoid 0:777851395940 369 // @return physical voltage corresponding to MAX5715 code.
whismanoid 0:777851395940 370 double MAX5715::VoltageOfCode(uint16_t value_u12)
whismanoid 0:777851395940 371 {
whismanoid 0:777851395940 372
whismanoid 0:777851395940 373 //----------------------------------------
whismanoid 0:777851395940 374 // Linear map min and max endpoints
whismanoid 0:777851395940 375 double MaxScaleVoltage = VRef; // voltage of maximum code 0x0fff
whismanoid 0:777851395940 376 double MinScaleVoltage = 0.0; // voltage of minimum code 0x000
whismanoid 0:777851395940 377 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 0:777851395940 378 const uint16_t MaxCode = FULL_SCALE_CODE_12BIT;
whismanoid 0:777851395940 379 const uint16_t MinCode = 0x000;
whismanoid 0:777851395940 380 double codeFraction = ((double)value_u12 - MinCode) / (MaxCode - MinCode + 1);
whismanoid 0:777851395940 381 return MinScaleVoltage + ((MaxScaleVoltage - MinScaleVoltage) * codeFraction);
whismanoid 0:777851395940 382 }
whismanoid 0:777851395940 383
whismanoid 0:777851395940 384 //----------------------------------------
whismanoid 0:777851395940 385 // CMD_1000_0000_dddd_dddd_dddd_0000_CODEall
whismanoid 0:777851395940 386 //
whismanoid 0:777851395940 387 // Writes data to all CODE registers
whismanoid 0:777851395940 388 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 389 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 390 void MAX5715::CODEall(uint16_t dacCodeLsbs)
whismanoid 0:777851395940 391 {
whismanoid 0:777851395940 392
whismanoid 0:777851395940 393 //----------------------------------------
whismanoid 0:777851395940 394 // Define command code
whismanoid 0:777851395940 395 uint8_t command_regAddress = CMD_1000_0000_dddd_dddd_dddd_0000_CODEall;
whismanoid 0:777851395940 396 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 397
whismanoid 0:777851395940 398 //----------------------------------------
whismanoid 0:777851395940 399 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 400 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 401 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 402 SPIoutputCS(0);
whismanoid 0:777851395940 403 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 404 SPIoutputCS(1);
whismanoid 0:777851395940 405
whismanoid 0:777851395940 406 //----------------------------------------
whismanoid 0:777851395940 407 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 408 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 409 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 410 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 411 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 412 }
whismanoid 0:777851395940 413 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 414 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 415 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 416 }
whismanoid 0:777851395940 417 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 418 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 419 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 420 }
whismanoid 0:777851395940 421 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 422 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 423 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 424 }
whismanoid 0:777851395940 425 }
whismanoid 0:777851395940 426
whismanoid 0:777851395940 427 //----------------------------------------
whismanoid 0:777851395940 428 // CMD_0000_nnnn_dddd_dddd_dddd_0000_CODEn
whismanoid 0:777851395940 429 //
whismanoid 0:777851395940 430 // Writes data to the selected CODE register(s)
whismanoid 0:777851395940 431 //
whismanoid 0:777851395940 432 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 433 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 434 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 435 void MAX5715::CODEn(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 436 {
whismanoid 0:777851395940 437
whismanoid 0:777851395940 438 //----------------------------------------
whismanoid 0:777851395940 439 // update channel selection from channel_0_3
whismanoid 0:777851395940 440 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 441 switch (channelNumber_0_3) {
whismanoid 0:777851395940 442 case 0:
whismanoid 0:777851395940 443 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 444 break;
whismanoid 0:777851395940 445 case 1:
whismanoid 0:777851395940 446 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 447 break;
whismanoid 0:777851395940 448 case 2:
whismanoid 0:777851395940 449 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 450 break;
whismanoid 0:777851395940 451 case 3:
whismanoid 0:777851395940 452 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 453 break;
whismanoid 0:777851395940 454 default:
whismanoid 0:777851395940 455 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 456 }
whismanoid 0:777851395940 457
whismanoid 0:777851395940 458 //----------------------------------------
whismanoid 0:777851395940 459 // Define command code
whismanoid 0:777851395940 460 uint8_t command_regAddress = CMD_0000_nnnn_dddd_dddd_dddd_0000_CODEn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 461 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 462
whismanoid 0:777851395940 463 //----------------------------------------
whismanoid 0:777851395940 464 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 465 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 466 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 467 SPIoutputCS(0);
whismanoid 0:777851395940 468 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 469 SPIoutputCS(1);
whismanoid 0:777851395940 470
whismanoid 0:777851395940 471 //----------------------------------------
whismanoid 0:777851395940 472 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 473 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 474 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 475 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 476 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 477 }
whismanoid 0:777851395940 478 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 479 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 480 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 481 }
whismanoid 0:777851395940 482 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 483 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 484 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 485 }
whismanoid 0:777851395940 486 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 487 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 488 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 489 }
whismanoid 0:777851395940 490 }
whismanoid 0:777851395940 491
whismanoid 0:777851395940 492 //----------------------------------------
whismanoid 0:777851395940 493 // CMD_1000_0010_dddd_dddd_dddd_0000_CODEallLOADall
whismanoid 0:777851395940 494 //
whismanoid 0:777851395940 495 // Simultaneously writes data to all CODE registers while updating all DAC registers
whismanoid 0:777851395940 496 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 497 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 498 void MAX5715::CODEallLOADall(uint16_t dacCodeLsbs)
whismanoid 0:777851395940 499 {
whismanoid 0:777851395940 500
whismanoid 0:777851395940 501 //----------------------------------------
whismanoid 0:777851395940 502 // Define command code
whismanoid 0:777851395940 503 uint8_t command_regAddress = CMD_1000_0010_dddd_dddd_dddd_0000_CODEallLOADall;
whismanoid 0:777851395940 504 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 505
whismanoid 0:777851395940 506 //----------------------------------------
whismanoid 0:777851395940 507 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 508 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 509 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 510 SPIoutputCS(0);
whismanoid 0:777851395940 511 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 512 SPIoutputCS(1);
whismanoid 0:777851395940 513
whismanoid 0:777851395940 514 //----------------------------------------
whismanoid 0:777851395940 515 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 516 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 517 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 518 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 519 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 520 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 521 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 522 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 523 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 524 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 525 }
whismanoid 0:777851395940 526
whismanoid 0:777851395940 527 //----------------------------------------
whismanoid 0:777851395940 528 // CMD_0010_nnnn_dddd_dddd_dddd_0000_CODEnLOADall
whismanoid 0:777851395940 529 //
whismanoid 0:777851395940 530 // Simultaneously writes data to the selected CODE register(s) while updating all DAC registers.
whismanoid 0:777851395940 531 //
whismanoid 0:777851395940 532 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 533 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 534 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 535 void MAX5715::CODEnLOADall(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 536 {
whismanoid 0:777851395940 537
whismanoid 0:777851395940 538 //----------------------------------------
whismanoid 0:777851395940 539 // update channel selection from channel_0_3
whismanoid 0:777851395940 540 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 541 switch (channelNumber_0_3) {
whismanoid 0:777851395940 542 case 0:
whismanoid 0:777851395940 543 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 544 break;
whismanoid 0:777851395940 545 case 1:
whismanoid 0:777851395940 546 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 547 break;
whismanoid 0:777851395940 548 case 2:
whismanoid 0:777851395940 549 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 550 break;
whismanoid 0:777851395940 551 case 3:
whismanoid 0:777851395940 552 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 553 break;
whismanoid 0:777851395940 554 default:
whismanoid 0:777851395940 555 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 556 }
whismanoid 0:777851395940 557
whismanoid 0:777851395940 558 //----------------------------------------
whismanoid 0:777851395940 559 // Define command code
whismanoid 0:777851395940 560 uint8_t command_regAddress = CMD_0010_nnnn_dddd_dddd_dddd_0000_CODEnLOADall | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 561 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 562
whismanoid 0:777851395940 563 //----------------------------------------
whismanoid 0:777851395940 564 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 565 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 566 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 567 SPIoutputCS(0);
whismanoid 0:777851395940 568 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 569 SPIoutputCS(1);
whismanoid 0:777851395940 570
whismanoid 0:777851395940 571 //----------------------------------------
whismanoid 0:777851395940 572 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 573 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 574 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 575 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 576 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 577 }
whismanoid 0:777851395940 578 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 579 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 580 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 581 }
whismanoid 0:777851395940 582 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 583 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 584 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 585 }
whismanoid 0:777851395940 586 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 587 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 588 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 589 }
whismanoid 0:777851395940 590 }
whismanoid 0:777851395940 591
whismanoid 0:777851395940 592 //----------------------------------------
whismanoid 0:777851395940 593 // CMD_0011_nnnn_dddd_dddd_dddd_0000_CODEnLOADn
whismanoid 0:777851395940 594 //
whismanoid 0:777851395940 595 // Simultaneously writes data to the selected CODE register(s) while updating selected DAC register(s)
whismanoid 0:777851395940 596 //
whismanoid 0:777851395940 597 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 598 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 599 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 600 void MAX5715::CODEnLOADn(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 601 {
whismanoid 0:777851395940 602
whismanoid 0:777851395940 603 //----------------------------------------
whismanoid 0:777851395940 604 // update channel selection from channel_0_3
whismanoid 0:777851395940 605 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 606 switch (channelNumber_0_3) {
whismanoid 0:777851395940 607 case 0:
whismanoid 0:777851395940 608 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 609 break;
whismanoid 0:777851395940 610 case 1:
whismanoid 0:777851395940 611 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 612 break;
whismanoid 0:777851395940 613 case 2:
whismanoid 0:777851395940 614 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 615 break;
whismanoid 0:777851395940 616 case 3:
whismanoid 0:777851395940 617 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 618 break;
whismanoid 0:777851395940 619 default:
whismanoid 0:777851395940 620 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 621 }
whismanoid 0:777851395940 622
whismanoid 0:777851395940 623 //----------------------------------------
whismanoid 0:777851395940 624 // Define command code
whismanoid 0:777851395940 625 uint8_t command_regAddress = CMD_0011_nnnn_dddd_dddd_dddd_0000_CODEnLOADn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 626 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 627
whismanoid 0:777851395940 628 //----------------------------------------
whismanoid 0:777851395940 629 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 630 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 631 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 632 SPIoutputCS(0);
whismanoid 0:777851395940 633 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 634 SPIoutputCS(1);
whismanoid 0:777851395940 635
whismanoid 0:777851395940 636 //----------------------------------------
whismanoid 0:777851395940 637 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 638 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 639 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 640 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 641 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 642 }
whismanoid 0:777851395940 643 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 644 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 645 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 646 }
whismanoid 0:777851395940 647 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 648 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 649 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 650 }
whismanoid 0:777851395940 651 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 652 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 653 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 654 }
whismanoid 0:777851395940 655 }
whismanoid 0:777851395940 656
whismanoid 0:777851395940 657 //----------------------------------------
whismanoid 0:777851395940 658 // CMD_0110_0000_0000_dcba_0000_0000_CONFIGn_LATCHED
whismanoid 0:777851395940 659 //
whismanoid 0:777851395940 660 // Sets the DAC Latch Mode of the selected DACs.
whismanoid 0:777851395940 661 // Only DACS with a 1 in the selection bit are updated by the command.
whismanoid 0:777851395940 662 // LD_EN = 0: DAC latch is operational (LOAD and LDAC controlled)
whismanoid 0:777851395940 663 //
whismanoid 0:777851395940 664 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 665 // bit 1000 = channel D
whismanoid 0:777851395940 666 // bit 0100 = channel C
whismanoid 0:777851395940 667 // bit 0010 = channel B
whismanoid 0:777851395940 668 // bit 0001 = channel A
whismanoid 0:777851395940 669 void MAX5715::CONFIGn_LATCHED(uint8_t channels_bitmask_DCBA)
whismanoid 0:777851395940 670 {
whismanoid 0:777851395940 671
whismanoid 0:777851395940 672 //----------------------------------------
whismanoid 0:777851395940 673 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 674 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 675 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 676 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 677 }
whismanoid 0:777851395940 678 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 679 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 680 }
whismanoid 0:777851395940 681 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 682 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 683 }
whismanoid 0:777851395940 684 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 685 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 686 }
whismanoid 0:777851395940 687 else {
whismanoid 0:777851395940 688 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 689 }
whismanoid 0:777851395940 690
whismanoid 0:777851395940 691 //----------------------------------------
whismanoid 0:777851395940 692 // Define command code
whismanoid 0:777851395940 693 uint8_t command_regAddress = CMD_0110_0000_0000_dcba_0000_0000_CONFIGn_LATCHED;
whismanoid 0:777851395940 694 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // align field 0000_dcba_0000_0000
whismanoid 0:777851395940 695
whismanoid 0:777851395940 696 //----------------------------------------
whismanoid 0:777851395940 697 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 698 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 699 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 700 SPIoutputCS(0);
whismanoid 0:777851395940 701 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 702 SPIoutputCS(1);
whismanoid 0:777851395940 703 }
whismanoid 0:777851395940 704
whismanoid 0:777851395940 705 //----------------------------------------
whismanoid 0:777851395940 706 // CMD_0110_0001_0000_dcba_0000_0000_CONFIGn_TRANSPARENT
whismanoid 0:777851395940 707 //
whismanoid 0:777851395940 708 // Sets the DAC Latch Mode of the selected DACs.
whismanoid 0:777851395940 709 // Only DACS with a 1 in the selection bit are updated by the command.
whismanoid 0:777851395940 710 // LD_EN = 1: DAC latch is transparent
whismanoid 0:777851395940 711 //
whismanoid 0:777851395940 712 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 713 // bit 1000 = channel D
whismanoid 0:777851395940 714 // bit 0100 = channel C
whismanoid 0:777851395940 715 // bit 0010 = channel B
whismanoid 0:777851395940 716 // bit 0001 = channel A
whismanoid 0:777851395940 717 void MAX5715::CONFIGn_TRANSPARENT(uint8_t channels_bitmask_DCBA)
whismanoid 0:777851395940 718 {
whismanoid 0:777851395940 719
whismanoid 0:777851395940 720 //----------------------------------------
whismanoid 0:777851395940 721 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 722 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 723 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 724 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 725 }
whismanoid 0:777851395940 726 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 727 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 728 }
whismanoid 0:777851395940 729 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 730 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 731 }
whismanoid 0:777851395940 732 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 733 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 734 }
whismanoid 0:777851395940 735 else {
whismanoid 0:777851395940 736 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 737 }
whismanoid 0:777851395940 738
whismanoid 0:777851395940 739 //----------------------------------------
whismanoid 0:777851395940 740 // Define command code
whismanoid 0:777851395940 741 uint8_t command_regAddress = CMD_0110_0001_0000_dcba_0000_0000_CONFIGn_TRANSPARENT;
whismanoid 0:777851395940 742 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // align field 0000_dcba_0000_0000
whismanoid 0:777851395940 743
whismanoid 0:777851395940 744 //----------------------------------------
whismanoid 0:777851395940 745 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 746 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 747 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 748 SPIoutputCS(0);
whismanoid 0:777851395940 749 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 750 SPIoutputCS(1);
whismanoid 0:777851395940 751 }
whismanoid 0:777851395940 752
whismanoid 0:777851395940 753 //----------------------------------------
whismanoid 0:777851395940 754 // CMD_0110_1000_0000_0000_0000_0000_CONFIGall_LATCHED
whismanoid 0:777851395940 755 //
whismanoid 0:777851395940 756 // Sets the DAC Latch Mode of all DACs.
whismanoid 0:777851395940 757 // LD_EN = 0: DAC latch is operational (LOAD and LDAC controlled)
whismanoid 0:777851395940 758 void MAX5715::CONFIGall_LATCHED(void)
whismanoid 0:777851395940 759 {
whismanoid 0:777851395940 760
whismanoid 0:777851395940 761 //----------------------------------------
whismanoid 0:777851395940 762 // Define command code
whismanoid 0:777851395940 763 uint8_t command_regAddress = CMD_0110_1000_0000_0000_0000_0000_CONFIGall_LATCHED;
whismanoid 0:777851395940 764 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 765
whismanoid 0:777851395940 766 //----------------------------------------
whismanoid 0:777851395940 767 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 768 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 769 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 770 SPIoutputCS(0);
whismanoid 0:777851395940 771 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 772 SPIoutputCS(1);
whismanoid 0:777851395940 773 }
whismanoid 0:777851395940 774
whismanoid 0:777851395940 775 //----------------------------------------
whismanoid 0:777851395940 776 // CMD_0110_1001_0000_0000_0000_0000_CONFIGall_TRANSPARENT
whismanoid 0:777851395940 777 //
whismanoid 0:777851395940 778 // Sets the DAC Latch Mode of all DACs.
whismanoid 0:777851395940 779 // LD_EN = 1: DAC latch is transparent
whismanoid 0:777851395940 780 void MAX5715::CONFIGall_TRANSPARENT(void)
whismanoid 0:777851395940 781 {
whismanoid 0:777851395940 782
whismanoid 0:777851395940 783 //----------------------------------------
whismanoid 0:777851395940 784 // Define command code
whismanoid 0:777851395940 785 uint8_t command_regAddress = CMD_0110_1001_0000_0000_0000_0000_CONFIGall_TRANSPARENT;
whismanoid 0:777851395940 786 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 787
whismanoid 0:777851395940 788 //----------------------------------------
whismanoid 0:777851395940 789 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 790 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 791 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 792 SPIoutputCS(0);
whismanoid 0:777851395940 793 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 794 SPIoutputCS(1);
whismanoid 0:777851395940 795 }
whismanoid 0:777851395940 796
whismanoid 0:777851395940 797 //----------------------------------------
whismanoid 0:777851395940 798 // CMD_1000_0001_0000_0000_0000_0000_LOADall
whismanoid 0:777851395940 799 //
whismanoid 0:777851395940 800 // Updates all DAC latches with current CODE register data
whismanoid 0:777851395940 801 void MAX5715::LOADall(void)
whismanoid 0:777851395940 802 {
whismanoid 0:777851395940 803
whismanoid 0:777851395940 804 //----------------------------------------
whismanoid 0:777851395940 805 // Define command code
whismanoid 0:777851395940 806 uint8_t command_regAddress = CMD_1000_0001_0000_0000_0000_0000_LOADall;
whismanoid 0:777851395940 807 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 808
whismanoid 0:777851395940 809 //----------------------------------------
whismanoid 0:777851395940 810 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 811 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 812 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 813 SPIoutputCS(0);
whismanoid 0:777851395940 814 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 815 SPIoutputCS(1);
whismanoid 0:777851395940 816 }
whismanoid 0:777851395940 817
whismanoid 0:777851395940 818 //----------------------------------------
whismanoid 0:777851395940 819 // CMD_0001_nnnn_0000_0000_0000_0000_LOADn
whismanoid 0:777851395940 820 //
whismanoid 0:777851395940 821 // Transfers data from the selected CODE register(s) to the selected DAC register(s).
whismanoid 0:777851395940 822 //
whismanoid 0:777851395940 823 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 824 void MAX5715::LOADn(uint8_t channel_0_3)
whismanoid 0:777851395940 825 {
whismanoid 0:777851395940 826
whismanoid 0:777851395940 827 //----------------------------------------
whismanoid 0:777851395940 828 // update channel selection from channel_0_3
whismanoid 0:777851395940 829 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 830 switch (channelNumber_0_3) {
whismanoid 0:777851395940 831 case 0:
whismanoid 0:777851395940 832 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 833 break;
whismanoid 0:777851395940 834 case 1:
whismanoid 0:777851395940 835 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 836 break;
whismanoid 0:777851395940 837 case 2:
whismanoid 0:777851395940 838 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 839 break;
whismanoid 0:777851395940 840 case 3:
whismanoid 0:777851395940 841 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 842 break;
whismanoid 0:777851395940 843 default:
whismanoid 0:777851395940 844 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 845 }
whismanoid 0:777851395940 846
whismanoid 0:777851395940 847 //----------------------------------------
whismanoid 0:777851395940 848 // Define command code
whismanoid 0:777851395940 849 uint8_t command_regAddress = CMD_0001_nnnn_0000_0000_0000_0000_LOADn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 850 uint16_t regValue = (0 << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 851
whismanoid 0:777851395940 852 //----------------------------------------
whismanoid 0:777851395940 853 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 854 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 855 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 856 SPIoutputCS(0);
whismanoid 0:777851395940 857 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 858 SPIoutputCS(1);
whismanoid 0:777851395940 859 }
whismanoid 0:777851395940 860
whismanoid 0:777851395940 861 //----------------------------------------
whismanoid 0:777851395940 862 // CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal
whismanoid 3:a3f0518094f4 863 // CMD_0100_0001_0000_dcba_0000_0000_POWERn_PD1k
whismanoid 3:a3f0518094f4 864 // CMD_0100_0010_0000_dcba_0000_0000_POWERn_PD100k
whismanoid 3:a3f0518094f4 865 // CMD_0100_0011_0000_dcba_0000_0000_POWERn_PDHiZ
whismanoid 0:777851395940 866 //
whismanoid 0:777851395940 867 // Sets the power mode of the selected DACs
whismanoid 0:777851395940 868 // (DACs selected with a 1 in the corresponding DACn bit are updated,
whismanoid 0:777851395940 869 // DACs with a 0 in the corresponding DACn bit are not impacted)
whismanoid 0:777851395940 870 //
whismanoid 0:777851395940 871 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 872 // bit 1000 = channel D
whismanoid 0:777851395940 873 // bit 0100 = channel C
whismanoid 0:777851395940 874 // bit 0010 = channel B
whismanoid 0:777851395940 875 // bit 0001 = channel A
whismanoid 0:777851395940 876 // @param[in] powerValue = power configuration for selected channel
whismanoid 0:777851395940 877 void MAX5715::POWER(uint8_t channels_bitmask_DCBA, MAX5715_POWER_enum_t powerValue)
whismanoid 0:777851395940 878 {
whismanoid 0:777851395940 879
whismanoid 0:777851395940 880 //----------------------------------------
whismanoid 0:777851395940 881 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 882 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 883 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 884 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 885 }
whismanoid 0:777851395940 886 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 887 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 888 }
whismanoid 0:777851395940 889 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 890 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 891 }
whismanoid 0:777851395940 892 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 893 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 894 }
whismanoid 0:777851395940 895 else {
whismanoid 0:777851395940 896 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 897 }
whismanoid 0:777851395940 898
whismanoid 0:777851395940 899 //----------------------------------------
whismanoid 0:777851395940 900 // select command_regAddress based on condition
whismanoid 0:777851395940 901 uint8_t command_regAddress = CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal; // diagnostic
whismanoid 0:777851395940 902 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // 0000_dcba_0000_0000
whismanoid 0:777851395940 903 // select command_regAddress from list of 4 values, based on condition
whismanoid 3:a3f0518094f4 904 if (powerValue == POWERn_Normal) {
whismanoid 3:a3f0518094f4 905 command_regAddress = CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal;
whismanoid 0:777851395940 906 }
whismanoid 0:777851395940 907 if (powerValue == POWERn_PD1k) {
whismanoid 0:777851395940 908 command_regAddress = CMD_0100_0001_0000_dcba_0000_0000_POWERn_PD1k;
whismanoid 0:777851395940 909 }
whismanoid 3:a3f0518094f4 910 if (powerValue == POWERn_PD100k) {
whismanoid 3:a3f0518094f4 911 command_regAddress = CMD_0100_0010_0000_dcba_0000_0000_POWERn_PD100k;
whismanoid 0:777851395940 912 }
whismanoid 0:777851395940 913 if (powerValue == POWERn_PDHiZ) {
whismanoid 0:777851395940 914 command_regAddress = CMD_0100_0011_0000_dcba_0000_0000_POWERn_PDHiZ;
whismanoid 0:777851395940 915 }
whismanoid 0:777851395940 916
whismanoid 0:777851395940 917 //----------------------------------------
whismanoid 0:777851395940 918 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 919 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 920 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 921 SPIoutputCS(0);
whismanoid 0:777851395940 922 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 923 SPIoutputCS(1);
whismanoid 0:777851395940 924 }
whismanoid 0:777851395940 925
whismanoid 0:777851395940 926 //----------------------------------------
whismanoid 0:777851395940 927 // CMD_0111_0000_0000_0000_0000_0000_REF_EXT
whismanoid 0:777851395940 928 // CMD_0111_0001_0000_0000_0000_0000_REF_2V500
whismanoid 0:777851395940 929 // CMD_0111_0010_0000_0000_0000_0000_REF_2V048
whismanoid 0:777851395940 930 // CMD_0111_0011_0000_0000_0000_0000_REF_4V096
whismanoid 0:777851395940 931 // CMD_0111_0100_0000_0000_0000_0000_REF_AlwaysOn_EXT
whismanoid 0:777851395940 932 // CMD_0111_0101_0000_0000_0000_0000_REF_AlwaysOn_2V500
whismanoid 0:777851395940 933 // CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048
whismanoid 0:777851395940 934 // CMD_0111_0111_0000_0000_0000_0000_REF_AlwaysOn_4V096
whismanoid 0:777851395940 935 //
whismanoid 0:777851395940 936 // Sets the reference operating mode.
whismanoid 0:777851395940 937 // REF Power (B18): 0 = Internal reference is only powered if at least one DAC is powered
whismanoid 0:777851395940 938 // 1 = Internal reference is always powered
whismanoid 4:500c80398f90 939 void MAX5715::REF(MAX5715_REF_enum_t ref)
whismanoid 0:777851395940 940 {
whismanoid 0:777851395940 941
whismanoid 0:777851395940 942 //----------------------------------------
whismanoid 0:777851395940 943 // select command_regAddress based on condition
whismanoid 0:777851395940 944 uint8_t command_regAddress = CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048; // diagnostic
whismanoid 0:777851395940 945 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 946 // select command_regAddress from list of 8 values, based on condition
whismanoid 4:500c80398f90 947 if (ref == REF_EXT) {
whismanoid 3:a3f0518094f4 948 command_regAddress = CMD_0111_0000_0000_0000_0000_0000_REF_EXT;
whismanoid 3:a3f0518094f4 949 }
whismanoid 4:500c80398f90 950 if (ref == REF_2V500) {
whismanoid 3:a3f0518094f4 951 command_regAddress = CMD_0111_0001_0000_0000_0000_0000_REF_2V500;
whismanoid 3:a3f0518094f4 952 VRef = 2.500;
whismanoid 3:a3f0518094f4 953 }
whismanoid 4:500c80398f90 954 if (ref == REF_2V048) {
whismanoid 3:a3f0518094f4 955 command_regAddress = CMD_0111_0010_0000_0000_0000_0000_REF_2V048;
whismanoid 3:a3f0518094f4 956 VRef = 2.048;
whismanoid 3:a3f0518094f4 957 }
whismanoid 4:500c80398f90 958 if (ref == REF_4V096) {
whismanoid 0:777851395940 959 command_regAddress = CMD_0111_0011_0000_0000_0000_0000_REF_4V096;
whismanoid 0:777851395940 960 VRef = 4.096;
whismanoid 0:777851395940 961 }
whismanoid 4:500c80398f90 962 if (ref == REF_AlwaysOn_EXT) {
whismanoid 0:777851395940 963 command_regAddress = CMD_0111_0100_0000_0000_0000_0000_REF_AlwaysOn_EXT;
whismanoid 0:777851395940 964 }
whismanoid 4:500c80398f90 965 if (ref == REF_AlwaysOn_2V500) {
whismanoid 3:a3f0518094f4 966 command_regAddress = CMD_0111_0101_0000_0000_0000_0000_REF_AlwaysOn_2V500;
whismanoid 0:777851395940 967 VRef = 2.500;
whismanoid 0:777851395940 968 }
whismanoid 4:500c80398f90 969 if (ref == REF_AlwaysOn_2V048) {
whismanoid 0:777851395940 970 command_regAddress = CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048;
whismanoid 0:777851395940 971 VRef = 2.048;
whismanoid 0:777851395940 972 }
whismanoid 4:500c80398f90 973 if (ref == REF_AlwaysOn_4V096) {
whismanoid 0:777851395940 974 command_regAddress = CMD_0111_0111_0000_0000_0000_0000_REF_AlwaysOn_4V096;
whismanoid 0:777851395940 975 VRef = 4.096;
whismanoid 0:777851395940 976 }
whismanoid 0:777851395940 977
whismanoid 0:777851395940 978 //----------------------------------------
whismanoid 0:777851395940 979 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 980 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 981 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 982 SPIoutputCS(0);
whismanoid 0:777851395940 983 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 984 SPIoutputCS(1);
whismanoid 0:777851395940 985
whismanoid 0:777851395940 986 //----------------------------------------
whismanoid 0:777851395940 987 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 988 Shadow_0111_0rrr_REF = regValue;
whismanoid 0:777851395940 989 }
whismanoid 0:777851395940 990
whismanoid 0:777851395940 991 //----------------------------------------
whismanoid 0:777851395940 992 // CMD_0101_0000_0000_0000_0000_0000_SW_CLEAR
whismanoid 0:777851395940 993 //
whismanoid 0:777851395940 994 // Software Clear
whismanoid 0:777851395940 995 // All CODE and DAC registers cleared to their default values.
whismanoid 0:777851395940 996 //
whismanoid 0:777851395940 997 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 998 uint8_t MAX5715::SW_CLEAR(void)
whismanoid 0:777851395940 999 {
whismanoid 0:777851395940 1000
whismanoid 0:777851395940 1001 //----------------------------------------
whismanoid 0:777851395940 1002 // Define command code
whismanoid 0:777851395940 1003 uint8_t command_regAddress = CMD_0101_0000_0000_0000_0000_0000_SW_CLEAR;
whismanoid 0:777851395940 1004 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 1005
whismanoid 0:777851395940 1006 //----------------------------------------
whismanoid 0:777851395940 1007 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 1008 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 1009 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 1010 SPIoutputCS(0);
whismanoid 0:777851395940 1011 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 1012 SPIoutputCS(1);
whismanoid 0:777851395940 1013
whismanoid 0:777851395940 1014 //----------------------------------------
whismanoid 0:777851395940 1015 // after successful SW_RESET, update shadow registers
whismanoid 0:777851395940 1016 // assume SPI write was successful
whismanoid 0:777851395940 1017 if (1)
whismanoid 0:777851395940 1018 {
whismanoid 0:777851395940 1019 // shadow of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1020 Shadow_0010_nnnn_CODE[0] = 0x0000;
whismanoid 0:777851395940 1021 Shadow_0010_nnnn_CODE[1] = 0x0000;
whismanoid 0:777851395940 1022 Shadow_0010_nnnn_CODE[2] = 0x0000;
whismanoid 0:777851395940 1023 Shadow_0010_nnnn_CODE[3] = 0x0000;
whismanoid 0:777851395940 1024 //
whismanoid 0:777851395940 1025 // shadow of write-only register POWER[channel_0_3] CMD_0100_00pp
whismanoid 0:777851395940 1026 //Shadow_0100_00pp_POWER[0] = POWERn_Normal;
whismanoid 0:777851395940 1027 //Shadow_0100_00pp_POWER[1] = POWERn_Normal;
whismanoid 0:777851395940 1028 //Shadow_0100_00pp_POWER[2] = POWERn_Normal;
whismanoid 0:777851395940 1029 //Shadow_0100_00pp_POWER[3] = POWERn_Normal;
whismanoid 0:777851395940 1030 //
whismanoid 0:777851395940 1031 // shadow of write-only register CONFIG[channel_0_3] CMD_0110_a00t
whismanoid 0:777851395940 1032 //Shadow_0110_a00t_CONFIG[0] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1033 //Shadow_0110_a00t_CONFIG[1] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1034 //Shadow_0110_a00t_CONFIG[2] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1035 //Shadow_0110_a00t_CONFIG[3] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1036 //
whismanoid 0:777851395940 1037 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 1038 //Shadow_0111_0rrr_REF = REF_EXT;
whismanoid 0:777851395940 1039 //
whismanoid 0:777851395940 1040 // shadow of CODE field of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1041 CODE[0] = 0x0000;
whismanoid 0:777851395940 1042 CODE[1] = 0x0000;
whismanoid 0:777851395940 1043 CODE[2] = 0x0000;
whismanoid 0:777851395940 1044 CODE[3] = 0x0000;
whismanoid 0:777851395940 1045 //
whismanoid 0:777851395940 1046 }
whismanoid 0:777851395940 1047
whismanoid 0:777851395940 1048 //----------------------------------------
whismanoid 0:777851395940 1049 // success
whismanoid 0:777851395940 1050 return 1;
whismanoid 0:777851395940 1051 }
whismanoid 0:777851395940 1052
whismanoid 0:777851395940 1053 //----------------------------------------
whismanoid 0:777851395940 1054 // CMD_0101_0001_0000_0000_0000_0000_SW_RESET
whismanoid 0:777851395940 1055 //
whismanoid 0:777851395940 1056 // Software Reset
whismanoid 0:777851395940 1057 // All CODE, DAC, and control registers returned to their default values,
whismanoid 0:777851395940 1058 // simulating a power cycle reset.
whismanoid 0:777851395940 1059 //
whismanoid 0:777851395940 1060 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 1061 uint8_t MAX5715::SW_RESET(void)
whismanoid 0:777851395940 1062 {
whismanoid 0:777851395940 1063
whismanoid 0:777851395940 1064 //----------------------------------------
whismanoid 0:777851395940 1065 // Define command code
whismanoid 0:777851395940 1066 uint8_t command_regAddress = CMD_0101_0001_0000_0000_0000_0000_SW_RESET;
whismanoid 0:777851395940 1067 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 1068
whismanoid 0:777851395940 1069 //----------------------------------------
whismanoid 0:777851395940 1070 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 1071 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 1072 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 1073 SPIoutputCS(0);
whismanoid 0:777851395940 1074 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 1075 SPIoutputCS(1);
whismanoid 0:777851395940 1076
whismanoid 0:777851395940 1077 //----------------------------------------
whismanoid 0:777851395940 1078 // after successful SW_RESET, update shadow registers
whismanoid 0:777851395940 1079 // assume SPI write was successful
whismanoid 0:777851395940 1080 if (1)
whismanoid 0:777851395940 1081 {
whismanoid 0:777851395940 1082 // shadow of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1083 Shadow_0010_nnnn_CODE[0] = 0x0000;
whismanoid 0:777851395940 1084 Shadow_0010_nnnn_CODE[1] = 0x0000;
whismanoid 0:777851395940 1085 Shadow_0010_nnnn_CODE[2] = 0x0000;
whismanoid 0:777851395940 1086 Shadow_0010_nnnn_CODE[3] = 0x0000;
whismanoid 0:777851395940 1087 //
whismanoid 0:777851395940 1088 // shadow of write-only register POWER[channel_0_3] CMD_0100_00pp
whismanoid 0:777851395940 1089 Shadow_0100_00pp_POWER[0] = POWERn_Normal;
whismanoid 0:777851395940 1090 Shadow_0100_00pp_POWER[1] = POWERn_Normal;
whismanoid 0:777851395940 1091 Shadow_0100_00pp_POWER[2] = POWERn_Normal;
whismanoid 0:777851395940 1092 Shadow_0100_00pp_POWER[3] = POWERn_Normal;
whismanoid 0:777851395940 1093 //
whismanoid 0:777851395940 1094 // shadow of write-only register CONFIG[channel_0_3] CMD_0110_a00t
whismanoid 0:777851395940 1095 Shadow_0110_a00t_CONFIG[0] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1096 Shadow_0110_a00t_CONFIG[1] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1097 Shadow_0110_a00t_CONFIG[2] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1098 Shadow_0110_a00t_CONFIG[3] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1099 //
whismanoid 0:777851395940 1100 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 1101 Shadow_0111_0rrr_REF = REF_EXT;
whismanoid 0:777851395940 1102 //
whismanoid 0:777851395940 1103 // shadow of CODE field of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1104 CODE[0] = 0x0000;
whismanoid 0:777851395940 1105 CODE[1] = 0x0000;
whismanoid 0:777851395940 1106 CODE[2] = 0x0000;
whismanoid 0:777851395940 1107 CODE[3] = 0x0000;
whismanoid 0:777851395940 1108 //
whismanoid 0:777851395940 1109 }
whismanoid 0:777851395940 1110
whismanoid 0:777851395940 1111 //----------------------------------------
whismanoid 0:777851395940 1112 // success
whismanoid 0:777851395940 1113 return 1;
whismanoid 0:777851395940 1114 }
whismanoid 0:777851395940 1115
whismanoid 0:777851395940 1116
whismanoid 0:777851395940 1117 // End of file