Maxim Integrated / MAX4147X

MAX4147X RF Receiver Mbed Driver

Fork of MAX4147X by Sinan Divarci

Max4147x.h@0:dc5ded118d7c, 2021-08-02 (annotated)

Committer:
Sinan Divarci
Date:
Mon Aug 02 16:34:28 2021 +0300
Revision:
0:dc5ded118d7c
initial commit

Who changed what in which revision?

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Sinan Divarci 0:dc5ded118d7c 1 /*******************************************************************************
Sinan Divarci 0:dc5ded118d7c 2 * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
Sinan Divarci 0:dc5ded118d7c 3 *
Sinan Divarci 0:dc5ded118d7c 4 * Permission is hereby granted, free of charge, to any person obtaining a
Sinan Divarci 0:dc5ded118d7c 5 * copy of this software and associated documentation files(the "Software"),
Sinan Divarci 0:dc5ded118d7c 6 * to deal in the Software without restriction, including without limitation
Sinan Divarci 0:dc5ded118d7c 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Sinan Divarci 0:dc5ded118d7c 8 * and/or sell copies of the Software, and to permit persons to whom the
Sinan Divarci 0:dc5ded118d7c 9 * Software is furnished to do so, subject to the following conditions:
Sinan Divarci 0:dc5ded118d7c 10 *
Sinan Divarci 0:dc5ded118d7c 11 * The above copyright notice and this permission notice shall be included
Sinan Divarci 0:dc5ded118d7c 12 * in all copies or substantial portions of the Software.
Sinan Divarci 0:dc5ded118d7c 13 *
Sinan Divarci 0:dc5ded118d7c 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Sinan Divarci 0:dc5ded118d7c 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Sinan Divarci 0:dc5ded118d7c 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Sinan Divarci 0:dc5ded118d7c 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Sinan Divarci 0:dc5ded118d7c 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Sinan Divarci 0:dc5ded118d7c 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Sinan Divarci 0:dc5ded118d7c 20 * OTHER DEALINGS IN THE SOFTWARE.
Sinan Divarci 0:dc5ded118d7c 21 *
Sinan Divarci 0:dc5ded118d7c 22 * Except as contained in this notice, the name of Maxim Integrated
Sinan Divarci 0:dc5ded118d7c 23 * Products, Inc.shall not be used except as stated in the Maxim Integrated
Sinan Divarci 0:dc5ded118d7c 24 * Products, Inc.Branding Policy.
Sinan Divarci 0:dc5ded118d7c 25 *
Sinan Divarci 0:dc5ded118d7c 26 * The mere transfer of this software does not imply any licenses
Sinan Divarci 0:dc5ded118d7c 27 * of trade secrets, proprietary technology, copyrights, patents,
Sinan Divarci 0:dc5ded118d7c 28 * trademarks, maskwork rights, or any other form of intellectual
Sinan Divarci 0:dc5ded118d7c 29 * property whatsoever. Maxim Integrated Products, Inc.retains all
Sinan Divarci 0:dc5ded118d7c 30 * ownership rights.
Sinan Divarci 0:dc5ded118d7c 31 *******************************************************************************
Sinan Divarci 0:dc5ded118d7c 32 */
Sinan Divarci 0:dc5ded118d7c 33
Sinan Divarci 0:dc5ded118d7c 34 #ifndef MAX4147X_MAX4147X_H_
Sinan Divarci 0:dc5ded118d7c 35 #define MAX4147X_MAX4147X_H_
Sinan Divarci 0:dc5ded118d7c 36
Sinan Divarci 0:dc5ded118d7c 37 #include "mbed.h"
Sinan Divarci 0:dc5ded118d7c 38 #include "rtos.h"
Sinan Divarci 0:dc5ded118d7c 39 #include "Max41470_regs.h"
Sinan Divarci 0:dc5ded118d7c 40 #include "Max41473_4_regs.h"
Sinan Divarci 0:dc5ded118d7c 41
Sinan Divarci 0:dc5ded118d7c 42 #define MAX4147X_SPI MXC_SPIM2
Sinan Divarci 0:dc5ded118d7c 43
Sinan Divarci 0:dc5ded118d7c 44 #define MAX4147X_PIN_POWER P4_0
Sinan Divarci 0:dc5ded118d7c 45 #define MAX4147X_PIN_RSSI P3_1
Sinan Divarci 0:dc5ded118d7c 46 #define MAX4147X_PIN_DATA P5_6
Sinan Divarci 0:dc5ded118d7c 47
Sinan Divarci 0:dc5ded118d7c 48 #define MAX4147X_I2C_SCL P3_5
Sinan Divarci 0:dc5ded118d7c 49 #define MAX4147X_I2C_SDA P3_4
Sinan Divarci 0:dc5ded118d7c 50
Sinan Divarci 0:dc5ded118d7c 51 #define MAX4147X_SPI_SCK P5_0
Sinan Divarci 0:dc5ded118d7c 52 #define MAX4147X_SPI_MOSI P5_1
Sinan Divarci 0:dc5ded118d7c 53 #define MAX4147X_SPI_MISO P5_2
Sinan Divarci 0:dc5ded118d7c 54 #define MAX4147X_SPI_SSEL P3_0
Sinan Divarci 0:dc5ded118d7c 55
Sinan Divarci 0:dc5ded118d7c 56 #define MAX4147X_I2C_ADDRESS 0xD6
Sinan Divarci 0:dc5ded118d7c 57
Sinan Divarci 0:dc5ded118d7c 58 #define Q_CONF_LEN 15
Sinan Divarci 0:dc5ded118d7c 59
Sinan Divarci 0:dc5ded118d7c 60 extern const uint8_t default_register_value_0[Q_CONF_LEN];
Sinan Divarci 0:dc5ded118d7c 61 extern const uint8_t default_register_value_1[Q_CONF_LEN];
Sinan Divarci 0:dc5ded118d7c 62
Sinan Divarci 0:dc5ded118d7c 63 template <class REG>
Sinan Divarci 0:dc5ded118d7c 64 class MAX4147X
Sinan Divarci 0:dc5ded118d7c 65 {
Sinan Divarci 0:dc5ded118d7c 66 private:
Sinan Divarci 0:dc5ded118d7c 67 REG *reg_map;
Sinan Divarci 0:dc5ded118d7c 68 I2C *i2c_handler;
Sinan Divarci 0:dc5ded118d7c 69 SPI *spi_handler;
Sinan Divarci 0:dc5ded118d7c 70 DigitalOut *ssel;
Sinan Divarci 0:dc5ded118d7c 71 DigitalOut *power_pin;
Sinan Divarci 0:dc5ded118d7c 72
Sinan Divarci 0:dc5ded118d7c 73 DigitalIn *data_read; // data sent pin
Sinan Divarci 0:dc5ded118d7c 74
Sinan Divarci 0:dc5ded118d7c 75 uint8_t preset_mode;
Sinan Divarci 0:dc5ded118d7c 76 float crystal_frequency ;
Sinan Divarci 0:dc5ded118d7c 77 float center_frequency;
Sinan Divarci 0:dc5ded118d7c 78 float baud_rate;
Sinan Divarci 0:dc5ded118d7c 79 float baud_rate_ratio;
Sinan Divarci 0:dc5ded118d7c 80
Sinan Divarci 0:dc5ded118d7c 81 typedef enum {
Sinan Divarci 0:dc5ded118d7c 82 DEMOD_ADDR = 0x00,
Sinan Divarci 0:dc5ded118d7c 83 AGC_ADDR = 0x01,
Sinan Divarci 0:dc5ded118d7c 84 IF_CHF_SEL_ADDR = 0x02,
Sinan Divarci 0:dc5ded118d7c 85 PDF_CFG_ADDR = 0x03,
Sinan Divarci 0:dc5ded118d7c 86 ATH_CFG1_ADDR = 0x04,
Sinan Divarci 0:dc5ded118d7c 87 ATH_CFG2_ADDR = 0x05,
Sinan Divarci 0:dc5ded118d7c 88 ATH_CFG3_ADDR = 0x06,
Sinan Divarci 0:dc5ded118d7c 89 AFC_CFG1_ADDR = 0x07,
Sinan Divarci 0:dc5ded118d7c 90 AFC_CFG2_ADDR = 0x08,
Sinan Divarci 0:dc5ded118d7c 91 LO_CTR_FREQ3_ADDR = 0x09,
Sinan Divarci 0:dc5ded118d7c 92 LO_CTR_FREQ2_ADDR = 0x0A,
Sinan Divarci 0:dc5ded118d7c 93 LO_CTR_FREQ1_ADDR = 0x0B,
Sinan Divarci 0:dc5ded118d7c 94 PREAMBLE_CFG1_ADDR = 0x0C,
Sinan Divarci 0:dc5ded118d7c 95 PREAMBLE_WORD1_ADDR = 0x0D,
Sinan Divarci 0:dc5ded118d7c 96 PREAMBLE_WORD2_ADDR = 0x0E,
Sinan Divarci 0:dc5ded118d7c 97 RSSI_ADDR = 0x10,
Sinan Divarci 0:dc5ded118d7c 98 FEI_ADDR = 0x11,
Sinan Divarci 0:dc5ded118d7c 99 PDF_OUT_ADDR = 0x12,
Sinan Divarci 0:dc5ded118d7c 100 ISR_ADDR = 0x13,
Sinan Divarci 0:dc5ded118d7c 101 CDR_CFG1_ADDR = 0x35,
Sinan Divarci 0:dc5ded118d7c 102 STATE_CTRL1_ADDR = 0x14,
Sinan Divarci 0:dc5ded118d7c 103 STATE_CTRL2_ADDR = 0x15,
Sinan Divarci 0:dc5ded118d7c 104 STATE_CTRL3_ADDR = 0x16,
Sinan Divarci 0:dc5ded118d7c 105 WUT1_ADDR = 0x17,
Sinan Divarci 0:dc5ded118d7c 106 WUT2_ADDR = 0x18,
Sinan Divarci 0:dc5ded118d7c 107 AFE_CTL1_ADDR = 0x19,
Sinan Divarci 0:dc5ded118d7c 108 IR_ADJUST_ADDR = 0x1A,
Sinan Divarci 0:dc5ded118d7c 109 PART_NUM_ADDR = 0x1E,
Sinan Divarci 0:dc5ded118d7c 110 REV_NUM_ADDR = 0x1F,
Sinan Divarci 0:dc5ded118d7c 111 STATUS_ADDR = 0x27
Sinan Divarci 0:dc5ded118d7c 112 }register_address_t;
Sinan Divarci 0:dc5ded118d7c 113
Sinan Divarci 0:dc5ded118d7c 114 /**
Sinan Divarci 0:dc5ded118d7c 115 * @brief Sets LO Center Frequency, lower byte of 24-bit word (Register: LO_CTR_FREQ1 ,0x0B)
Sinan Divarci 0:dc5ded118d7c 116 *
Sinan Divarci 0:dc5ded118d7c 117 * @param[in] lo_ctr_freq_lower
Sinan Divarci 0:dc5ded118d7c 118 *
Sinan Divarci 0:dc5ded118d7c 119 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 120 *
Sinan Divarci 0:dc5ded118d7c 121 * @description LO Center Frequency, lower byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 122 */
Sinan Divarci 0:dc5ded118d7c 123 int set_lo_ctr_freq_lower(uint8_t lo_ctr_freq_lower);
Sinan Divarci 0:dc5ded118d7c 124
Sinan Divarci 0:dc5ded118d7c 125 /**
Sinan Divarci 0:dc5ded118d7c 126 * @brief Sets LO Center Frequency, middle byte of 24-bit word (Register: LO_CTR_FREQ2 ,0x0A)
Sinan Divarci 0:dc5ded118d7c 127 *
Sinan Divarci 0:dc5ded118d7c 128 * @param[in] lo_ctr_freq_middle
Sinan Divarci 0:dc5ded118d7c 129 *
Sinan Divarci 0:dc5ded118d7c 130 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 131 *
Sinan Divarci 0:dc5ded118d7c 132 * @description LO Center Frequency, middle byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 133 */
Sinan Divarci 0:dc5ded118d7c 134 int set_lo_ctr_freq_middle(uint8_t lo_ctr_freq_middle);
Sinan Divarci 0:dc5ded118d7c 135
Sinan Divarci 0:dc5ded118d7c 136 /**
Sinan Divarci 0:dc5ded118d7c 137 * @brief Sets LO Center Frequency, upper byte of 24-bit word (Register: LO_CTR_FREQ3 ,0x09)
Sinan Divarci 0:dc5ded118d7c 138 *
Sinan Divarci 0:dc5ded118d7c 139 * @param[in] lo_ctr_freq_upper
Sinan Divarci 0:dc5ded118d7c 140 *
Sinan Divarci 0:dc5ded118d7c 141 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 142 *
Sinan Divarci 0:dc5ded118d7c 143 * @description LO Center Frequency, upper byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 144 */
Sinan Divarci 0:dc5ded118d7c 145 int set_lo_ctr_freq_upper(uint8_t lo_ctr_freq_upper);
Sinan Divarci 0:dc5ded118d7c 146
Sinan Divarci 0:dc5ded118d7c 147 /**
Sinan Divarci 0:dc5ded118d7c 148 * @brief Sets Preamble Bit Pattern Length before Manchester Coding (Register: PREAMBLE_CFG1 ,0x0C)
Sinan Divarci 0:dc5ded118d7c 149 *
Sinan Divarci 0:dc5ded118d7c 150 * @param[in] preamb_len
Sinan Divarci 0:dc5ded118d7c 151 *
Sinan Divarci 0:dc5ded118d7c 152 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 153 *
Sinan Divarci 0:dc5ded118d7c 154 * @description Preamble Bit Pattern Length before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 155 * Bit Pattern Length = Register Field Value +1
Sinan Divarci 0:dc5ded118d7c 156 */
Sinan Divarci 0:dc5ded118d7c 157 int set_preamb_len(uint8_t preamb_len);
Sinan Divarci 0:dc5ded118d7c 158
Sinan Divarci 0:dc5ded118d7c 159 /**
Sinan Divarci 0:dc5ded118d7c 160 * @brief Sets Lower Byte of the Preamble Bit Pattern before Manchester Coding (Register: PREAMBLE_WORD1 ,0x0D)
Sinan Divarci 0:dc5ded118d7c 161 *
Sinan Divarci 0:dc5ded118d7c 162 * @param[in] preamb_word_lower
Sinan Divarci 0:dc5ded118d7c 163 *
Sinan Divarci 0:dc5ded118d7c 164 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 165 *
Sinan Divarci 0:dc5ded118d7c 166 * @description Lower Byte of the Preamble Bit Pattern before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 167 */
Sinan Divarci 0:dc5ded118d7c 168 int set_preamb_word_lower(uint8_t preamb_word_lower);
Sinan Divarci 0:dc5ded118d7c 169
Sinan Divarci 0:dc5ded118d7c 170 /**
Sinan Divarci 0:dc5ded118d7c 171 * @brief Sets Upper Byte of the Preamble Bit Pattern before Manchester Coding (Register: PREAMBLE_WORD2 ,0x0E)
Sinan Divarci 0:dc5ded118d7c 172 *
Sinan Divarci 0:dc5ded118d7c 173 * @param[in] preamb_word_upper
Sinan Divarci 0:dc5ded118d7c 174 *
Sinan Divarci 0:dc5ded118d7c 175 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 176 *
Sinan Divarci 0:dc5ded118d7c 177 * @description Upper Byte of the Preamble Bit Pattern before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 178 */
Sinan Divarci 0:dc5ded118d7c 179 int set_preamb_word_upper(uint8_t preamb_word_upper);
Sinan Divarci 0:dc5ded118d7c 180
Sinan Divarci 0:dc5ded118d7c 181
Sinan Divarci 0:dc5ded118d7c 182 protected:
Sinan Divarci 0:dc5ded118d7c 183
Sinan Divarci 0:dc5ded118d7c 184 int io_read(uint8_t *data, uint32_t length);
Sinan Divarci 0:dc5ded118d7c 185
Sinan Divarci 0:dc5ded118d7c 186 public:
Sinan Divarci 0:dc5ded118d7c 187
Sinan Divarci 0:dc5ded118d7c 188 //Constructors
Sinan Divarci 0:dc5ded118d7c 189 MAX4147X(REG *reg, SPI *spi, DigitalOut *cs, DigitalOut *powerPin, DigitalIn *dataPin);
Sinan Divarci 0:dc5ded118d7c 190
Sinan Divarci 0:dc5ded118d7c 191 MAX4147X(REG *reg, SPI *spi, DigitalOut *powerPin, DigitalIn *dataPin);
Sinan Divarci 0:dc5ded118d7c 192
Sinan Divarci 0:dc5ded118d7c 193 MAX4147X(REG *reg, I2C *i2c, DigitalOut *powerPin, DigitalIn *dataPin);
Sinan Divarci 0:dc5ded118d7c 194
Sinan Divarci 0:dc5ded118d7c 195 typedef enum
Sinan Divarci 0:dc5ded118d7c 196 {
Sinan Divarci 0:dc5ded118d7c 197 Manchester = 0,
Sinan Divarci 0:dc5ded118d7c 198 NRZ = 1
Sinan Divarci 0:dc5ded118d7c 199 }encoding_t;
Sinan Divarci 0:dc5ded118d7c 200
Sinan Divarci 0:dc5ded118d7c 201 encoding_t encoding;
Sinan Divarci 0:dc5ded118d7c 202
Sinan Divarci 0:dc5ded118d7c 203 /**
Sinan Divarci 0:dc5ded118d7c 204 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 205 *
Sinan Divarci 0:dc5ded118d7c 206 * @details
Sinan Divarci 0:dc5ded118d7c 207 * - Register : DEMOD (0x00)
Sinan Divarci 0:dc5ded118d7c 208 * - Bit Fields : [7:6]
Sinan Divarci 0:dc5ded118d7c 209 * - Default : 0x1
Sinan Divarci 0:dc5ded118d7c 210 * - Description : RSSI Peak Detector Discharge Time
Sinan Divarci 0:dc5ded118d7c 211 */
Sinan Divarci 0:dc5ded118d7c 212 typedef enum {
Sinan Divarci 0:dc5ded118d7c 213 RSSI_DT_DEFAULT_VALUE_X0_5, /**< 0x0: 1/2 default value */
Sinan Divarci 0:dc5ded118d7c 214 RSSI_DT_DEFAULT_VALUE, /**< 0x1: default value */
Sinan Divarci 0:dc5ded118d7c 215 RSSI_DT_DEFAULT_VALUE_X2, /**< 0x2: 0x2: 2x default value */
Sinan Divarci 0:dc5ded118d7c 216 RSSI_DT_DEFAULT_VALUE_X4, /**< 0x3: 0x3: 4x default value */
Sinan Divarci 0:dc5ded118d7c 217 } rssi_dt_t;
Sinan Divarci 0:dc5ded118d7c 218
Sinan Divarci 0:dc5ded118d7c 219 /**
Sinan Divarci 0:dc5ded118d7c 220 * @brief Set RSSI Peak Detector Discharge Time
Sinan Divarci 0:dc5ded118d7c 221 *
Sinan Divarci 0:dc5ded118d7c 222 * @param[in] rssi_dt
Sinan Divarci 0:dc5ded118d7c 223 *
Sinan Divarci 0:dc5ded118d7c 224 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 225 */
Sinan Divarci 0:dc5ded118d7c 226 int set_rssi_dt(rssi_dt_t rssi_dt);
Sinan Divarci 0:dc5ded118d7c 227
Sinan Divarci 0:dc5ded118d7c 228 /**
Sinan Divarci 0:dc5ded118d7c 229 * @brief Get RSSI Peak Detector Discharge Time
Sinan Divarci 0:dc5ded118d7c 230 *
Sinan Divarci 0:dc5ded118d7c 231 * @param[in] rssi_dt
Sinan Divarci 0:dc5ded118d7c 232 *
Sinan Divarci 0:dc5ded118d7c 233 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 234 */
Sinan Divarci 0:dc5ded118d7c 235 int get_rssi_dt(rssi_dt_t *rssi_dt);
Sinan Divarci 0:dc5ded118d7c 236
Sinan Divarci 0:dc5ded118d7c 237 /**
Sinan Divarci 0:dc5ded118d7c 238 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 239 *
Sinan Divarci 0:dc5ded118d7c 240 * @details
Sinan Divarci 0:dc5ded118d7c 241 * - Register : DEMOD (0x00)
Sinan Divarci 0:dc5ded118d7c 242 * - Bit Fields : [5:3]
Sinan Divarci 0:dc5ded118d7c 243 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 244 * - Description : Demodulator Parameter #2 to be used only in FSK mode. Must be programmed according to
Sinan Divarci 0:dc5ded118d7c 245 * the table of FSK Demodulator Configuration.
Sinan Divarci 0:dc5ded118d7c 246 */
Sinan Divarci 0:dc5ded118d7c 247 typedef enum {
Sinan Divarci 0:dc5ded118d7c 248 DEMOD_FSK_CONF_0, /**< 0x0: FSK Demod Config Index = 0, 14 */
Sinan Divarci 0:dc5ded118d7c 249 DEMOD_FSK_CONF_1, /**< 0x1: FSK Demod Config Index = 1, 15 */
Sinan Divarci 0:dc5ded118d7c 250 DEMOD_FSK_CONF_2, /**< 0x2: FSK Demod Config Index = 2, 16 */
Sinan Divarci 0:dc5ded118d7c 251 DEMOD_FSK_CONF_3, /**< 0x3: FSK Demod Config Index = 3, 6, 17, 20 */
Sinan Divarci 0:dc5ded118d7c 252 DEMOD_FSK_CONF_4, /**< 0x4: FSK Demod Config Index = 4, 7, 9, 11, 18, 21, 23, 25 */
Sinan Divarci 0:dc5ded118d7c 253 DEMOD_FSK_CONF_5, /**< 0x5: FSK Demod Config Index = 5, 8, 10, 12, 19, 22, 24, 26 */
Sinan Divarci 0:dc5ded118d7c 254 DEMOD_FSK_CONF_6, /**< 0x6: FSK Demod Config Index = 13, 27 */
Sinan Divarci 0:dc5ded118d7c 255 DEMOD_FSK_CONF_7 /**< 0x7: Invalid value */
Sinan Divarci 0:dc5ded118d7c 256 } demod_fsk_t;
Sinan Divarci 0:dc5ded118d7c 257
Sinan Divarci 0:dc5ded118d7c 258 /**
Sinan Divarci 0:dc5ded118d7c 259 * @brief Set Demodulator Parameter #2
Sinan Divarci 0:dc5ded118d7c 260 *
Sinan Divarci 0:dc5ded118d7c 261 * @param[in] demod_fsk
Sinan Divarci 0:dc5ded118d7c 262 *
Sinan Divarci 0:dc5ded118d7c 263 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 264 */
Sinan Divarci 0:dc5ded118d7c 265 int set_demod_fsk(demod_fsk_t demod_fsk);
Sinan Divarci 0:dc5ded118d7c 266
Sinan Divarci 0:dc5ded118d7c 267 /**
Sinan Divarci 0:dc5ded118d7c 268 * @brief Get Demodulator Parameter #2
Sinan Divarci 0:dc5ded118d7c 269 *
Sinan Divarci 0:dc5ded118d7c 270 * @param[in] demod_fsk
Sinan Divarci 0:dc5ded118d7c 271 *
Sinan Divarci 0:dc5ded118d7c 272 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 273 */
Sinan Divarci 0:dc5ded118d7c 274 int get_demod_fsk(demod_fsk_t *demod_fsk);
Sinan Divarci 0:dc5ded118d7c 275
Sinan Divarci 0:dc5ded118d7c 276 /**
Sinan Divarci 0:dc5ded118d7c 277 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 278 *
Sinan Divarci 0:dc5ded118d7c 279 * @details
Sinan Divarci 0:dc5ded118d7c 280 * - Register : DEMOD (0x00)
Sinan Divarci 0:dc5ded118d7c 281 * - Bit Fields : [2:0]
Sinan Divarci 0:dc5ded118d7c 282 * - Default : 0x4
Sinan Divarci 0:dc5ded118d7c 283 * - Description : Demodulator Parameter #1.
Sinan Divarci 0:dc5ded118d7c 284 * Conditions / Recommended Value
Sinan Divarci 0:dc5ded118d7c 285 * ASK_FSK_SEL=1 / 4 - CHF_SEL
Sinan Divarci 0:dc5ded118d7c 286 * ASK_FSK_SEL=0, ATH_TYPE=0 / min(2+SRC_LG, 7)
Sinan Divarci 0:dc5ded118d7c 287 * ASK_FSK_SEL=0, ATH_TYPE=1 / min(3+SRC_LG,7)
Sinan Divarci 0:dc5ded118d7c 288 */
Sinan Divarci 0:dc5ded118d7c 289 typedef enum {
Sinan Divarci 0:dc5ded118d7c 290 DEMOD_TCTRL_CONF_0, /**< 0x0: 1/16 Default */
Sinan Divarci 0:dc5ded118d7c 291 DEMOD_TCTRL_CONF_1, /**< 0x1: 1/8 Default */
Sinan Divarci 0:dc5ded118d7c 292 DEMOD_TCTRL_CONF_2, /**< 0x2: 1/4 Default */
Sinan Divarci 0:dc5ded118d7c 293 DEMOD_TCTRL_CONF_3, /**< 0x3: 1/2 Default */
Sinan Divarci 0:dc5ded118d7c 294 DEMOD_TCTRL_CONF_4, /**< 0x4: Default value */
Sinan Divarci 0:dc5ded118d7c 295 DEMOD_TCTRL_CONF_5, /**< 0x5: 2x Default */
Sinan Divarci 0:dc5ded118d7c 296 DEMOD_TCTRL_CONF_6, /**< 0x6: 4x Default */
Sinan Divarci 0:dc5ded118d7c 297 DEMOD_TCTRL_CONF_7 /**< 0x7: 8x Default */
Sinan Divarci 0:dc5ded118d7c 298 } demod_tctrl_t;
Sinan Divarci 0:dc5ded118d7c 299
Sinan Divarci 0:dc5ded118d7c 300 /**
Sinan Divarci 0:dc5ded118d7c 301 * @brief Set Demodulator Parameter #1
Sinan Divarci 0:dc5ded118d7c 302 *
Sinan Divarci 0:dc5ded118d7c 303 * @param[in] demod_tctrl
Sinan Divarci 0:dc5ded118d7c 304 *
Sinan Divarci 0:dc5ded118d7c 305 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 306 */
Sinan Divarci 0:dc5ded118d7c 307 int set_demod_tctrl(demod_tctrl_t demod_tctrl);
Sinan Divarci 0:dc5ded118d7c 308
Sinan Divarci 0:dc5ded118d7c 309 /**
Sinan Divarci 0:dc5ded118d7c 310 * @brief Get Demodulator Parameter #1
Sinan Divarci 0:dc5ded118d7c 311 *
Sinan Divarci 0:dc5ded118d7c 312 * @param[in] demod_tctrl
Sinan Divarci 0:dc5ded118d7c 313 *
Sinan Divarci 0:dc5ded118d7c 314 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 315 */
Sinan Divarci 0:dc5ded118d7c 316 int get_demod_tctrl(demod_tctrl_t *demod_tctrl);
Sinan Divarci 0:dc5ded118d7c 317
Sinan Divarci 0:dc5ded118d7c 318 /**
Sinan Divarci 0:dc5ded118d7c 319 * @brief Sets AGC-Release Threshold Fine Tune (Register: AGC ,0x01)
Sinan Divarci 0:dc5ded118d7c 320 *
Sinan Divarci 0:dc5ded118d7c 321 * @param[in] agc_threl
Sinan Divarci 0:dc5ded118d7c 322 *
Sinan Divarci 0:dc5ded118d7c 323 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 324 *
Sinan Divarci 0:dc5ded118d7c 325 * @description AGC-Release Threshold Fine Tune. Recommended value is 0x9 when data rate is lower than 52kbps, or 0xF when data rate is higher than 52kbps.
Sinan Divarci 0:dc5ded118d7c 326 */
Sinan Divarci 0:dc5ded118d7c 327 int set_agc_threl(uint8_t agc_threl);
Sinan Divarci 0:dc5ded118d7c 328
Sinan Divarci 0:dc5ded118d7c 329 /**
Sinan Divarci 0:dc5ded118d7c 330 * @brief Gets AGC-Release Threshold Fine Tune (Register: AGC ,0x01)
Sinan Divarci 0:dc5ded118d7c 331 *
Sinan Divarci 0:dc5ded118d7c 332 * @param[in] agc_threl
Sinan Divarci 0:dc5ded118d7c 333 *
Sinan Divarci 0:dc5ded118d7c 334 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 335 *
Sinan Divarci 0:dc5ded118d7c 336 * @description AGC-Release Threshold Fine Tune. Recommended value is 0x9 when data rate is lower than 52kbps, or 0xF when data rate is higher than 52kbps.
Sinan Divarci 0:dc5ded118d7c 337 */
Sinan Divarci 0:dc5ded118d7c 338 int get_agc_threl(uint8_t *agc_threl);
Sinan Divarci 0:dc5ded118d7c 339
Sinan Divarci 0:dc5ded118d7c 340 /**
Sinan Divarci 0:dc5ded118d7c 341 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 342 *
Sinan Divarci 0:dc5ded118d7c 343 * @details
Sinan Divarci 0:dc5ded118d7c 344 * - Register : AGC (0x01)
Sinan Divarci 0:dc5ded118d7c 345 * - Bit Fields : [1:0]
Sinan Divarci 0:dc5ded118d7c 346 * - Default : 0x2
Sinan Divarci 0:dc5ded118d7c 347 * - Description : AGC Operation Mode
Sinan Divarci 0:dc5ded118d7c 348 */
Sinan Divarci 0:dc5ded118d7c 349 typedef enum {
Sinan Divarci 0:dc5ded118d7c 350 AGC_EN_BO_AGC_DISABLED_MAX_GAIN, /**< 0x0: AGC disabled, max gain */
Sinan Divarci 0:dc5ded118d7c 351 AGC_EN_BO_AGC_DISABLED_BO_ADC_BUF, /**< 0x1: AGC disabled, back off ADC buffer */
Sinan Divarci 0:dc5ded118d7c 352 AGC_EN_BO_AGC_ENABLED, /**< 0x2: AGC enabled */
Sinan Divarci 0:dc5ded118d7c 353 AGC_EN_BO_AGC_ENABLED_BO_ADC_BUF /**< 0x3: AGC enabled, back off ADC buffer */
Sinan Divarci 0:dc5ded118d7c 354 } agc_en_bo_t;
Sinan Divarci 0:dc5ded118d7c 355
Sinan Divarci 0:dc5ded118d7c 356 /**
Sinan Divarci 0:dc5ded118d7c 357 * @brief Set AGC Operation Mode
Sinan Divarci 0:dc5ded118d7c 358 *
Sinan Divarci 0:dc5ded118d7c 359 * @param[in] agc_op_mode
Sinan Divarci 0:dc5ded118d7c 360 *
Sinan Divarci 0:dc5ded118d7c 361 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 362 */
Sinan Divarci 0:dc5ded118d7c 363 int set_agc_en_bo(agc_en_bo_t agc_op_mode);
Sinan Divarci 0:dc5ded118d7c 364
Sinan Divarci 0:dc5ded118d7c 365 /**
Sinan Divarci 0:dc5ded118d7c 366 * @brief Get AGC Operation Mode
Sinan Divarci 0:dc5ded118d7c 367 *
Sinan Divarci 0:dc5ded118d7c 368 * @param[in] agc_op_mode
Sinan Divarci 0:dc5ded118d7c 369 *
Sinan Divarci 0:dc5ded118d7c 370 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 371 */
Sinan Divarci 0:dc5ded118d7c 372 int get_agc_en_bo(agc_en_bo_t *agc_op_mode);
Sinan Divarci 0:dc5ded118d7c 373
Sinan Divarci 0:dc5ded118d7c 374 /**
Sinan Divarci 0:dc5ded118d7c 375 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 376 *
Sinan Divarci 0:dc5ded118d7c 377 * @details
Sinan Divarci 0:dc5ded118d7c 378 * - Register : IF_CHF_SEL (0x02)
Sinan Divarci 0:dc5ded118d7c 379 * - Bit Fields : [4]
Sinan Divarci 0:dc5ded118d7c 380 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 381 * - Description : ASK/FSK Selection
Sinan Divarci 0:dc5ded118d7c 382 */
Sinan Divarci 0:dc5ded118d7c 383 typedef enum {
Sinan Divarci 0:dc5ded118d7c 384 ASK_FSK_SEL_ASK, /**< 0x0: ASK demodulation */
Sinan Divarci 0:dc5ded118d7c 385 ASK_FSK_SEL_FSK /**< 0x1: FSK demodulation */
Sinan Divarci 0:dc5ded118d7c 386 } ask_fsk_sel_t;
Sinan Divarci 0:dc5ded118d7c 387
Sinan Divarci 0:dc5ded118d7c 388 /**
Sinan Divarci 0:dc5ded118d7c 389 * @brief Sets Demodulation Mode to ASK or FSK
Sinan Divarci 0:dc5ded118d7c 390 *
Sinan Divarci 0:dc5ded118d7c 391 * @param[in] ask_fsk_sel
Sinan Divarci 0:dc5ded118d7c 392 *
Sinan Divarci 0:dc5ded118d7c 393 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 394 */
Sinan Divarci 0:dc5ded118d7c 395 int set_ask_fsk_sel(ask_fsk_sel_t ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 396
Sinan Divarci 0:dc5ded118d7c 397 /**
Sinan Divarci 0:dc5ded118d7c 398 * @brief Gets Demodulation Mode
Sinan Divarci 0:dc5ded118d7c 399 *
Sinan Divarci 0:dc5ded118d7c 400 * @param[in] ask_fsk_sel
Sinan Divarci 0:dc5ded118d7c 401 *
Sinan Divarci 0:dc5ded118d7c 402 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 403 */
Sinan Divarci 0:dc5ded118d7c 404 int get_ask_fsk_sel(ask_fsk_sel_t *ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 405
Sinan Divarci 0:dc5ded118d7c 406 /**
Sinan Divarci 0:dc5ded118d7c 407 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 408 *
Sinan Divarci 0:dc5ded118d7c 409 * @details
Sinan Divarci 0:dc5ded118d7c 410 * - Register : IF_CHF_SEL (0x02)
Sinan Divarci 0:dc5ded118d7c 411 * - Bit Fields : [3]
Sinan Divarci 0:dc5ded118d7c 412 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 413 * - Description : Intermediate Frequency Selection
Sinan Divarci 0:dc5ded118d7c 414 */
Sinan Divarci 0:dc5ded118d7c 415 typedef enum {
Sinan Divarci 0:dc5ded118d7c 416 IF_SEL_400_KHZ, /**< 0x0: 400kHz */
Sinan Divarci 0:dc5ded118d7c 417 IF_SEL_200_KHZ /**< 0x1: 200kHz */
Sinan Divarci 0:dc5ded118d7c 418 } if_sel_t;
Sinan Divarci 0:dc5ded118d7c 419
Sinan Divarci 0:dc5ded118d7c 420 /**
Sinan Divarci 0:dc5ded118d7c 421 * @brief Sets Intermediate Frequency
Sinan Divarci 0:dc5ded118d7c 422 *
Sinan Divarci 0:dc5ded118d7c 423 * @param[in] if_sel
Sinan Divarci 0:dc5ded118d7c 424 *
Sinan Divarci 0:dc5ded118d7c 425 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 426 */
Sinan Divarci 0:dc5ded118d7c 427 int set_if_sel(if_sel_t if_sel);
Sinan Divarci 0:dc5ded118d7c 428
Sinan Divarci 0:dc5ded118d7c 429 /**
Sinan Divarci 0:dc5ded118d7c 430 * @brief Gets Intermediate Frequency
Sinan Divarci 0:dc5ded118d7c 431 *
Sinan Divarci 0:dc5ded118d7c 432 * @param[in] if_sel
Sinan Divarci 0:dc5ded118d7c 433 *
Sinan Divarci 0:dc5ded118d7c 434 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 435 */
Sinan Divarci 0:dc5ded118d7c 436 int get_if_sel(if_sel_t *if_sel);
Sinan Divarci 0:dc5ded118d7c 437
Sinan Divarci 0:dc5ded118d7c 438 /**
Sinan Divarci 0:dc5ded118d7c 439 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 440 *
Sinan Divarci 0:dc5ded118d7c 441 * @details
Sinan Divarci 0:dc5ded118d7c 442 * - Register : IF_CHF_SEL (0x02)
Sinan Divarci 0:dc5ded118d7c 443 * - Bit Fields : [2:0]
Sinan Divarci 0:dc5ded118d7c 444 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 445 * - Description : Channel Filter Selection
Sinan Divarci 0:dc5ded118d7c 446 */
Sinan Divarci 0:dc5ded118d7c 447 typedef enum {
Sinan Divarci 0:dc5ded118d7c 448 CHF_SEL_RXBW_340_170_KHZ, /**< 0x0: RXBW = 340kHz or 170kHz */
Sinan Divarci 0:dc5ded118d7c 449 CHF_SEL_RXBW_120_60_KHZ, /**< 0x1: RXBW = 120kHz or 60kHz */
Sinan Divarci 0:dc5ded118d7c 450 CHF_SEL_RXBW_52_26_KHZ, /**< 0x2: RXBW = 52kHz or 26kHz */
Sinan Divarci 0:dc5ded118d7c 451 CHF_SEL_RXBW_24_12_KHZ, /**< 0x3: RXBW = 24kHz or 12kHz */
Sinan Divarci 0:dc5ded118d7c 452 CHF_SEL_RXBW_12_6_KHZ, /**< 0x4: RXBW = 12kHz or 6kHz */
Sinan Divarci 0:dc5ded118d7c 453 CHF_SEL_INV0, /**< 0x5: Invalid value */
Sinan Divarci 0:dc5ded118d7c 454 CHF_SEL_INV1, /**< 0x6: Invalid value */
Sinan Divarci 0:dc5ded118d7c 455 CHF_SEL_INV2 /**< 0x7: Invalid value */
Sinan Divarci 0:dc5ded118d7c 456 } chf_sel_t;
Sinan Divarci 0:dc5ded118d7c 457
Sinan Divarci 0:dc5ded118d7c 458 /**
Sinan Divarci 0:dc5ded118d7c 459 * @brief Sets Channel Filter
Sinan Divarci 0:dc5ded118d7c 460 *
Sinan Divarci 0:dc5ded118d7c 461 * @param[in] chf_sel
Sinan Divarci 0:dc5ded118d7c 462 *
Sinan Divarci 0:dc5ded118d7c 463 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 464 */
Sinan Divarci 0:dc5ded118d7c 465 int set_chf_sel(chf_sel_t chf_sel);
Sinan Divarci 0:dc5ded118d7c 466
Sinan Divarci 0:dc5ded118d7c 467 /**
Sinan Divarci 0:dc5ded118d7c 468 * @brief Gets Channel Filter Selection
Sinan Divarci 0:dc5ded118d7c 469 *
Sinan Divarci 0:dc5ded118d7c 470 * @param[in] chf_sel
Sinan Divarci 0:dc5ded118d7c 471 *
Sinan Divarci 0:dc5ded118d7c 472 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 473 */
Sinan Divarci 0:dc5ded118d7c 474 int get_chf_sel(chf_sel_t *chf_sel);
Sinan Divarci 0:dc5ded118d7c 475
Sinan Divarci 0:dc5ded118d7c 476 /**
Sinan Divarci 0:dc5ded118d7c 477 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 478 *
Sinan Divarci 0:dc5ded118d7c 479 * @details
Sinan Divarci 0:dc5ded118d7c 480 * - Register : PDF_CFG (0x03)
Sinan Divarci 0:dc5ded118d7c 481 * - Bit Fields : [7]
Sinan Divarci 0:dc5ded118d7c 482 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 483 * - Description : Output Buffer Selection. Low delay buffer can only be selected
Sinan Divarci 0:dc5ded118d7c 484 * when (SRC_LG >= 3) or (SRC_LG = 2 and SRC_SM is even).
Sinan Divarci 0:dc5ded118d7c 485 */
Sinan Divarci 0:dc5ded118d7c 486 typedef enum {
Sinan Divarci 0:dc5ded118d7c 487 LF_BUF_DEFAULT_SELECTION, /**< 0x0: Default selection */
Sinan Divarci 0:dc5ded118d7c 488 LF_BUF_LOW_DELAY_BUF /**< 0x1: Low delay buffer */
Sinan Divarci 0:dc5ded118d7c 489 } ld_buf_t;
Sinan Divarci 0:dc5ded118d7c 490
Sinan Divarci 0:dc5ded118d7c 491 /**
Sinan Divarci 0:dc5ded118d7c 492 * @brief Sets Output Buffer
Sinan Divarci 0:dc5ded118d7c 493 *
Sinan Divarci 0:dc5ded118d7c 494 * @param[in] ld_buf
Sinan Divarci 0:dc5ded118d7c 495 *
Sinan Divarci 0:dc5ded118d7c 496 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 497 */
Sinan Divarci 0:dc5ded118d7c 498 int set_ld_buf(ld_buf_t ld_buf);
Sinan Divarci 0:dc5ded118d7c 499
Sinan Divarci 0:dc5ded118d7c 500 /**
Sinan Divarci 0:dc5ded118d7c 501 * @brief Gets Output Buffer Selection
Sinan Divarci 0:dc5ded118d7c 502 *
Sinan Divarci 0:dc5ded118d7c 503 * @param[in] ld_buf
Sinan Divarci 0:dc5ded118d7c 504 *
Sinan Divarci 0:dc5ded118d7c 505 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 506 */
Sinan Divarci 0:dc5ded118d7c 507 int get_ld_buf(ld_buf_t *ld_buf);
Sinan Divarci 0:dc5ded118d7c 508
Sinan Divarci 0:dc5ded118d7c 509 /**
Sinan Divarci 0:dc5ded118d7c 510 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 511 *
Sinan Divarci 0:dc5ded118d7c 512 * @details
Sinan Divarci 0:dc5ded118d7c 513 * - Register : PDF_CFG (0x03)
Sinan Divarci 0:dc5ded118d7c 514 * - Bit Fields : [6]
Sinan Divarci 0:dc5ded118d7c 515 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 516 * - Description : Post Demodulation Filter Bandwidth Control
Sinan Divarci 0:dc5ded118d7c 517 */
Sinan Divarci 0:dc5ded118d7c 518 typedef enum {
Sinan Divarci 0:dc5ded118d7c 519 LF_BW_DEFAULT_BW, /**< 0x0: Default selection */
Sinan Divarci 0:dc5ded118d7c 520 LF_BW_DEFAULT_BW_X1_67 /**< 0x1: Low delay buffer */
Sinan Divarci 0:dc5ded118d7c 521 } ld_bw_t;
Sinan Divarci 0:dc5ded118d7c 522
Sinan Divarci 0:dc5ded118d7c 523 /**
Sinan Divarci 0:dc5ded118d7c 524 * @brief Sets Post Demodulation Filter Bandwidth
Sinan Divarci 0:dc5ded118d7c 525 *
Sinan Divarci 0:dc5ded118d7c 526 * @param[in] ld_bw
Sinan Divarci 0:dc5ded118d7c 527 *
Sinan Divarci 0:dc5ded118d7c 528 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 529 */
Sinan Divarci 0:dc5ded118d7c 530 int set_ld_bw(ld_bw_t ld_bw);
Sinan Divarci 0:dc5ded118d7c 531
Sinan Divarci 0:dc5ded118d7c 532 /**
Sinan Divarci 0:dc5ded118d7c 533 * @brief Gets Post Demodulation Filter Bandwidth
Sinan Divarci 0:dc5ded118d7c 534 *
Sinan Divarci 0:dc5ded118d7c 535 * @param[in] ld_bw
Sinan Divarci 0:dc5ded118d7c 536 *
Sinan Divarci 0:dc5ded118d7c 537 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 538 */
Sinan Divarci 0:dc5ded118d7c 539 int get_ld_bw(ld_bw_t *ld_bw);
Sinan Divarci 0:dc5ded118d7c 540
Sinan Divarci 0:dc5ded118d7c 541 /**
Sinan Divarci 0:dc5ded118d7c 542 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 543 *
Sinan Divarci 0:dc5ded118d7c 544 * @details
Sinan Divarci 0:dc5ded118d7c 545 * - Register : PDF_CFG (0x03)
Sinan Divarci 0:dc5ded118d7c 546 * - Bit Fields : [5:3]
Sinan Divarci 0:dc5ded118d7c 547 * - Default : 0x2
Sinan Divarci 0:dc5ded118d7c 548 * - Description : "Large" adjustment to the Sample Rate Converter used to
Sinan Divarci 0:dc5ded118d7c 549 * calculate the recommended data rate. See Configuration
Sinan Divarci 0:dc5ded118d7c 550 * Guidance Tables and Recommended Data Rate Equation
Sinan Divarci 0:dc5ded118d7c 551 */
Sinan Divarci 0:dc5ded118d7c 552 typedef enum {
Sinan Divarci 0:dc5ded118d7c 553 SRC_LG_CONF_0, /**< 0x0: 4x Default */
Sinan Divarci 0:dc5ded118d7c 554 SRC_LG_CONF_1, /**< 0x1: 2x Default */
Sinan Divarci 0:dc5ded118d7c 555 SRC_LG_CONF_2, /**< 0x2: Default rate */
Sinan Divarci 0:dc5ded118d7c 556 SRC_LG_CONF_3, /**< 0x3: 1/2 Default */
Sinan Divarci 0:dc5ded118d7c 557 SRC_LG_CONF_4, /**< 0x4: 1/4 Default */
Sinan Divarci 0:dc5ded118d7c 558 SRC_LG_CONF_5, /**< 0x5: 1/8 Default */
Sinan Divarci 0:dc5ded118d7c 559 SRC_LG_CONF_6, /**< 0x6: 1/16 Default */
Sinan Divarci 0:dc5ded118d7c 560 SRC_LG_CONF_7 /**< 0x7: 1/32 Default */
Sinan Divarci 0:dc5ded118d7c 561 } src_lg_t;
Sinan Divarci 0:dc5ded118d7c 562
Sinan Divarci 0:dc5ded118d7c 563 /**
Sinan Divarci 0:dc5ded118d7c 564 * @brief Sets "Large" adjustment to the Sample Rate Converter
Sinan Divarci 0:dc5ded118d7c 565 *
Sinan Divarci 0:dc5ded118d7c 566 * @param[in] src_lg
Sinan Divarci 0:dc5ded118d7c 567 *
Sinan Divarci 0:dc5ded118d7c 568 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 569 */
Sinan Divarci 0:dc5ded118d7c 570 int set_src_lg(src_lg_t src_lg);
Sinan Divarci 0:dc5ded118d7c 571
Sinan Divarci 0:dc5ded118d7c 572 /**
Sinan Divarci 0:dc5ded118d7c 573 * @brief Gets "Large" adjustment of the Sample Rate Converter
Sinan Divarci 0:dc5ded118d7c 574 *
Sinan Divarci 0:dc5ded118d7c 575 * @param[in] src_lg
Sinan Divarci 0:dc5ded118d7c 576 *
Sinan Divarci 0:dc5ded118d7c 577 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 578 */
Sinan Divarci 0:dc5ded118d7c 579 int get_src_lg(src_lg_t *src_lg);
Sinan Divarci 0:dc5ded118d7c 580
Sinan Divarci 0:dc5ded118d7c 581 /**
Sinan Divarci 0:dc5ded118d7c 582 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 583 *
Sinan Divarci 0:dc5ded118d7c 584 * @details
Sinan Divarci 0:dc5ded118d7c 585 * - Register : PDF_CFG (0x03)
Sinan Divarci 0:dc5ded118d7c 586 * - Bit Fields : [2:0]
Sinan Divarci 0:dc5ded118d7c 587 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 588 * - Description : "Small" adjustment to the Sample Rate Converter used to
Sinan Divarci 0:dc5ded118d7c 589 * calculate the recommended data rate. See Configuration
Sinan Divarci 0:dc5ded118d7c 590 * Guidance Tables and Recommended Data Rate Equation
Sinan Divarci 0:dc5ded118d7c 591 */
Sinan Divarci 0:dc5ded118d7c 592 typedef enum {
Sinan Divarci 0:dc5ded118d7c 593 SRC_SM_CONF_0, /**< 0x0: Default rate */
Sinan Divarci 0:dc5ded118d7c 594 SRC_SM_CONF_1, /**< 0x1: 8/9 Default */
Sinan Divarci 0:dc5ded118d7c 595 SRC_SM_CONF_2, /**< 0x2: 8/10 Default */
Sinan Divarci 0:dc5ded118d7c 596 SRC_SM_CONF_3, /**< 0x3: 8/11 Default */
Sinan Divarci 0:dc5ded118d7c 597 SRC_SM_CONF_4, /**< 0x4: 8/12 Default */
Sinan Divarci 0:dc5ded118d7c 598 SRC_SM_CONF_5, /**< 0x5: 8/13 Default */
Sinan Divarci 0:dc5ded118d7c 599 SRC_SM_CONF_6, /**< 0x6: 8/14 Default */
Sinan Divarci 0:dc5ded118d7c 600 SRC_SM_CONF_7 /**< 0x7: 8/15 Default */
Sinan Divarci 0:dc5ded118d7c 601 } src_sm_t;
Sinan Divarci 0:dc5ded118d7c 602
Sinan Divarci 0:dc5ded118d7c 603 /**
Sinan Divarci 0:dc5ded118d7c 604 * @brief Sets "Small" adjustment to the Sample Rate Converter
Sinan Divarci 0:dc5ded118d7c 605 *
Sinan Divarci 0:dc5ded118d7c 606 * @param[in] src_sm
Sinan Divarci 0:dc5ded118d7c 607 *
Sinan Divarci 0:dc5ded118d7c 608 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 609 */
Sinan Divarci 0:dc5ded118d7c 610 int set_src_sm(src_sm_t src_sm);
Sinan Divarci 0:dc5ded118d7c 611
Sinan Divarci 0:dc5ded118d7c 612 /**
Sinan Divarci 0:dc5ded118d7c 613 * @brief Gets "Small" adjustment of the Sample Rate Converter
Sinan Divarci 0:dc5ded118d7c 614 *
Sinan Divarci 0:dc5ded118d7c 615 * @param[in] src_sm
Sinan Divarci 0:dc5ded118d7c 616 *
Sinan Divarci 0:dc5ded118d7c 617 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 618 */
Sinan Divarci 0:dc5ded118d7c 619 int get_src_sm(src_sm_t *src_sm);
Sinan Divarci 0:dc5ded118d7c 620
Sinan Divarci 0:dc5ded118d7c 621 /**
Sinan Divarci 0:dc5ded118d7c 622 * @brief Sets Parameter #1 for ASK Threshold Generation (Register: ATH_CFG1 ,0x04)
Sinan Divarci 0:dc5ded118d7c 623 *
Sinan Divarci 0:dc5ded118d7c 624 * @param[in] ath_lb
Sinan Divarci 0:dc5ded118d7c 625 *
Sinan Divarci 0:dc5ded118d7c 626 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 627 *
Sinan Divarci 0:dc5ded118d7c 628 * @description Parameter #1 for ASK Threshold Generation: lower bound of threshold in 8-bit signed, two's complement format. Valid value from -128 to 0.
Sinan Divarci 0:dc5ded118d7c 629 */
Sinan Divarci 0:dc5ded118d7c 630 int set_ath_lb(uint8_t ath_lb);
Sinan Divarci 0:dc5ded118d7c 631
Sinan Divarci 0:dc5ded118d7c 632 /**
Sinan Divarci 0:dc5ded118d7c 633 * @brief Gets Parameter #1 of ASK Threshold Generation (Register: ATH_CFG1 ,0x04)
Sinan Divarci 0:dc5ded118d7c 634 *
Sinan Divarci 0:dc5ded118d7c 635 * @param[in] ath_lb
Sinan Divarci 0:dc5ded118d7c 636 *
Sinan Divarci 0:dc5ded118d7c 637 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 638 *
Sinan Divarci 0:dc5ded118d7c 639 * @description Parameter #1 for ASK Threshold Generation: lower bound of threshold in 8-bit signed, two's complement format. Valid value from -128 to 0.
Sinan Divarci 0:dc5ded118d7c 640 */
Sinan Divarci 0:dc5ded118d7c 641 int get_ath_lb(uint8_t *ath_lb);
Sinan Divarci 0:dc5ded118d7c 642
Sinan Divarci 0:dc5ded118d7c 643 /**
Sinan Divarci 0:dc5ded118d7c 644 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 645 *
Sinan Divarci 0:dc5ded118d7c 646 * @details
Sinan Divarci 0:dc5ded118d7c 647 * - Register : ATH_CFG2 (0x05)
Sinan Divarci 0:dc5ded118d7c 648 * - Bit Fields : [6:5]
Sinan Divarci 0:dc5ded118d7c 649 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 650 * - Description : Parameter #4 for ASK Threshold Generation: peak-hold time control
Sinan Divarci 0:dc5ded118d7c 651 * in the "adaptive Peak Detector" (aPD) method
Sinan Divarci 0:dc5ded118d7c 652 */
Sinan Divarci 0:dc5ded118d7c 653 typedef enum {
Sinan Divarci 0:dc5ded118d7c 654 ATH_DT_DEFAULT_DISCHARGE_TIME, /**< 0x0: Default discharge time, suggested for Manchester data, close to Rb */
Sinan Divarci 0:dc5ded118d7c 655 ATH_DT_DISCHARGE_TIME_X2, /**< 0x1: 2x Discharge time, suggested for Manchester data, lower than Rb */
Sinan Divarci 0:dc5ded118d7c 656 ATH_DT_DISCHARGE_TIME_X4, /**< 0x2: 4x Discharge time */
Sinan Divarci 0:dc5ded118d7c 657 ATH_DT_DISCHARGE_TIME_X8 /**< 0x3: 8x Discharge time, suggested for NRZ data */
Sinan Divarci 0:dc5ded118d7c 658 } ath_dt_t;
Sinan Divarci 0:dc5ded118d7c 659
Sinan Divarci 0:dc5ded118d7c 660 /**
Sinan Divarci 0:dc5ded118d7c 661 * @brief Sets Parameter #4 for ASK Threshold Generation
Sinan Divarci 0:dc5ded118d7c 662 *
Sinan Divarci 0:dc5ded118d7c 663 * @param[in] ath_dt
Sinan Divarci 0:dc5ded118d7c 664 *
Sinan Divarci 0:dc5ded118d7c 665 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 666 */
Sinan Divarci 0:dc5ded118d7c 667 int set_ath_dt(ath_dt_t ath_dt);
Sinan Divarci 0:dc5ded118d7c 668
Sinan Divarci 0:dc5ded118d7c 669 /**
Sinan Divarci 0:dc5ded118d7c 670 * @brief Gets Parameter #4 of ASK Threshold Generation
Sinan Divarci 0:dc5ded118d7c 671 *
Sinan Divarci 0:dc5ded118d7c 672 * @param[in] ath_dt
Sinan Divarci 0:dc5ded118d7c 673 *
Sinan Divarci 0:dc5ded118d7c 674 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 675 */
Sinan Divarci 0:dc5ded118d7c 676 int get_ath_dt(ath_dt_t *ath_dt);
Sinan Divarci 0:dc5ded118d7c 677
Sinan Divarci 0:dc5ded118d7c 678 /**
Sinan Divarci 0:dc5ded118d7c 679 * @brief Sets Parameter #2 for ASK Threshold Generation (Register: ATH_CFG2 ,0x05)
Sinan Divarci 0:dc5ded118d7c 680 *
Sinan Divarci 0:dc5ded118d7c 681 * @param[in] ath_tc
Sinan Divarci 0:dc5ded118d7c 682 *
Sinan Divarci 0:dc5ded118d7c 683 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 684 *
Sinan Divarci 0:dc5ded118d7c 685 * @description: Parameter #2 for ASK Threshold Generation: to be programmed according to SRC_LG
Sinan Divarci 0:dc5ded118d7c 686 */
Sinan Divarci 0:dc5ded118d7c 687 int set_ath_tc(uint8_t ath_tc);
Sinan Divarci 0:dc5ded118d7c 688
Sinan Divarci 0:dc5ded118d7c 689 /**
Sinan Divarci 0:dc5ded118d7c 690 * @brief Gets Parameter #2 of ASK Threshold Generation (Register: ATH_CFG2 ,0x05)
Sinan Divarci 0:dc5ded118d7c 691 *
Sinan Divarci 0:dc5ded118d7c 692 * @param[in] ath_tc
Sinan Divarci 0:dc5ded118d7c 693 *
Sinan Divarci 0:dc5ded118d7c 694 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 695 *
Sinan Divarci 0:dc5ded118d7c 696 * @description: Parameter #2 for ASK Threshold Generation: to be programmed according to SRC_LG
Sinan Divarci 0:dc5ded118d7c 697 */
Sinan Divarci 0:dc5ded118d7c 698 int get_ath_tc(uint8_t *ath_tc);
Sinan Divarci 0:dc5ded118d7c 699
Sinan Divarci 0:dc5ded118d7c 700 /**
Sinan Divarci 0:dc5ded118d7c 701 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 702 *
Sinan Divarci 0:dc5ded118d7c 703 * @details
Sinan Divarci 0:dc5ded118d7c 704 * - Register : ATH_CFG3 (0x06)
Sinan Divarci 0:dc5ded118d7c 705 * - Bit Fields : [6]
Sinan Divarci 0:dc5ded118d7c 706 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 707 * - Description : ASK Threshold Adjustment Method
Sinan Divarci 0:dc5ded118d7c 708 */
Sinan Divarci 0:dc5ded118d7c 709 typedef enum {
Sinan Divarci 0:dc5ded118d7c 710 ATH_TYPE_PRELPF_MANCHESTER, /**< 0x0: Precharged lowpass filter (preLPF) (Manchester) */
Sinan Divarci 0:dc5ded118d7c 711 ATH_TYPE_APD_NRZ /**< 0x1: Adaptive peak detector (aPD)(NRZ) */
Sinan Divarci 0:dc5ded118d7c 712 } ath_type_t;
Sinan Divarci 0:dc5ded118d7c 713
Sinan Divarci 0:dc5ded118d7c 714 /**
Sinan Divarci 0:dc5ded118d7c 715 * @brief Sets ASK Threshold Adjustment Method
Sinan Divarci 0:dc5ded118d7c 716 *
Sinan Divarci 0:dc5ded118d7c 717 * @param[in] ath_type
Sinan Divarci 0:dc5ded118d7c 718 *
Sinan Divarci 0:dc5ded118d7c 719 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 720 */
Sinan Divarci 0:dc5ded118d7c 721 int set_ath_type(ath_type_t ath_type);
Sinan Divarci 0:dc5ded118d7c 722
Sinan Divarci 0:dc5ded118d7c 723 /**
Sinan Divarci 0:dc5ded118d7c 724 * @brief Gets ASK Threshold Adjustment Method
Sinan Divarci 0:dc5ded118d7c 725 *
Sinan Divarci 0:dc5ded118d7c 726 * @param[in] ath_type
Sinan Divarci 0:dc5ded118d7c 727 *
Sinan Divarci 0:dc5ded118d7c 728 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 729 */
Sinan Divarci 0:dc5ded118d7c 730 int get_ath_type(ath_type_t *ath_type);
Sinan Divarci 0:dc5ded118d7c 731
Sinan Divarci 0:dc5ded118d7c 732 /**
Sinan Divarci 0:dc5ded118d7c 733 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 734 *
Sinan Divarci 0:dc5ded118d7c 735 * @details
Sinan Divarci 0:dc5ded118d7c 736 * - Register : ATH_CFG3 (0x06)
Sinan Divarci 0:dc5ded118d7c 737 * - Bit Fields : [5]
Sinan Divarci 0:dc5ded118d7c 738 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 739 * - Description : Parameter #5 for ASK Threshold Generation: bandwidth control for precharged LPF (preLPF)
Sinan Divarci 0:dc5ded118d7c 740 */
Sinan Divarci 0:dc5ded118d7c 741 typedef enum {
Sinan Divarci 0:dc5ded118d7c 742 ATH_BW_DEFAULT, /**< 0x0: Default bandwidth */
Sinan Divarci 0:dc5ded118d7c 743 ATH_BW_DEFAULT_X2 /**< 0x1: 2x default */
Sinan Divarci 0:dc5ded118d7c 744 } ath_bw_t;
Sinan Divarci 0:dc5ded118d7c 745
Sinan Divarci 0:dc5ded118d7c 746 /**
Sinan Divarci 0:dc5ded118d7c 747 * @brief Sets Parameter #5 for ASK Threshold Generation
Sinan Divarci 0:dc5ded118d7c 748 *
Sinan Divarci 0:dc5ded118d7c 749 * @param[in] ath_bw
Sinan Divarci 0:dc5ded118d7c 750 *
Sinan Divarci 0:dc5ded118d7c 751 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 752 */
Sinan Divarci 0:dc5ded118d7c 753 int set_ath_bw(ath_bw_t ath_bw);
Sinan Divarci 0:dc5ded118d7c 754
Sinan Divarci 0:dc5ded118d7c 755 /**
Sinan Divarci 0:dc5ded118d7c 756 * @brief Gets Parameter #5 of ASK Threshold Generation
Sinan Divarci 0:dc5ded118d7c 757 *
Sinan Divarci 0:dc5ded118d7c 758 * @param[in] ath_bw
Sinan Divarci 0:dc5ded118d7c 759 *
Sinan Divarci 0:dc5ded118d7c 760 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 761 */
Sinan Divarci 0:dc5ded118d7c 762 int get_ath_bw(ath_bw_t *ath_bw);
Sinan Divarci 0:dc5ded118d7c 763
Sinan Divarci 0:dc5ded118d7c 764 /**
Sinan Divarci 0:dc5ded118d7c 765 * @brief Sets Parameter #3 for ASK Threshold Generation (Register: ATH_CFG3 ,0x06)
Sinan Divarci 0:dc5ded118d7c 766 *
Sinan Divarci 0:dc5ded118d7c 767 * @param[in] ath_gc
Sinan Divarci 0:dc5ded118d7c 768 *
Sinan Divarci 0:dc5ded118d7c 769 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 770 *
Sinan Divarci 0:dc5ded118d7c 771 * @description Parameter #3 for ASK Threshold Generation: to be programmed according to IF_SEL and CHF_SEL
Sinan Divarci 0:dc5ded118d7c 772 */
Sinan Divarci 0:dc5ded118d7c 773 int set_ath_gc(uint8_t ath_gc);
Sinan Divarci 0:dc5ded118d7c 774
Sinan Divarci 0:dc5ded118d7c 775 /**
Sinan Divarci 0:dc5ded118d7c 776 * @brief Gets Parameter #3 of ASK Threshold Generation (Register: ATH_CFG3 ,0x06)
Sinan Divarci 0:dc5ded118d7c 777 *
Sinan Divarci 0:dc5ded118d7c 778 * @param[in] ath_gc
Sinan Divarci 0:dc5ded118d7c 779 *
Sinan Divarci 0:dc5ded118d7c 780 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 781 *
Sinan Divarci 0:dc5ded118d7c 782 * @description Parameter #3 for ASK Threshold Generation: to be programmed according to IF_SEL and CHF_SEL
Sinan Divarci 0:dc5ded118d7c 783 */
Sinan Divarci 0:dc5ded118d7c 784 int get_ath_gc(uint8_t *ath_gc);
Sinan Divarci 0:dc5ded118d7c 785
Sinan Divarci 0:dc5ded118d7c 786 /**
Sinan Divarci 0:dc5ded118d7c 787 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 788 *
Sinan Divarci 0:dc5ded118d7c 789 * @details
Sinan Divarci 0:dc5ded118d7c 790 * - Register : AFC_CFG1 (0x07)
Sinan Divarci 0:dc5ded118d7c 791 * - Bit Fields : [4:2]
Sinan Divarci 0:dc5ded118d7c 792 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 793 * - Description : AFC Frequency Offset Limit
Sinan Divarci 0:dc5ded118d7c 794 */
Sinan Divarci 0:dc5ded118d7c 795 typedef enum {
Sinan Divarci 0:dc5ded118d7c 796 AFC_MO_CONF_0, /**< 0x0: AFC disabled */
Sinan Divarci 0:dc5ded118d7c 797 AFC_MO_CONF_1, /**< 0x1: 1/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 798 AFC_MO_CONF_2, /**< 0x2: 2/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 799 AFC_MO_CONF_3, /**< 0x3: 3/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 800 AFC_MO_CONF_4, /**< 0x4: 4/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 801 AFC_MO_CONF_5, /**< 0x5: 5/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 802 AFC_MO_CONF_6, /**< 0x6: 6/7 Max offset */
Sinan Divarci 0:dc5ded118d7c 803 AFC_MO_CONF_7, /**< 0x7: Max offset */
Sinan Divarci 0:dc5ded118d7c 804 } afc_mo_t;
Sinan Divarci 0:dc5ded118d7c 805
Sinan Divarci 0:dc5ded118d7c 806 /**
Sinan Divarci 0:dc5ded118d7c 807 * @brief Sets AFC Frequency Offset Limit
Sinan Divarci 0:dc5ded118d7c 808 *
Sinan Divarci 0:dc5ded118d7c 809 * @param[in] afc_mo
Sinan Divarci 0:dc5ded118d7c 810 *
Sinan Divarci 0:dc5ded118d7c 811 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 812 */
Sinan Divarci 0:dc5ded118d7c 813 int set_afc_mo(afc_mo_t afc_mo);
Sinan Divarci 0:dc5ded118d7c 814
Sinan Divarci 0:dc5ded118d7c 815 /**
Sinan Divarci 0:dc5ded118d7c 816 * @brief Gets AFC Frequency Offset Limit
Sinan Divarci 0:dc5ded118d7c 817 *
Sinan Divarci 0:dc5ded118d7c 818 * @param[in] ath_bw
Sinan Divarci 0:dc5ded118d7c 819 *
Sinan Divarci 0:dc5ded118d7c 820 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 821 */
Sinan Divarci 0:dc5ded118d7c 822 int get_afc_mo(afc_mo_t *afc_mo);
Sinan Divarci 0:dc5ded118d7c 823
Sinan Divarci 0:dc5ded118d7c 824 /**
Sinan Divarci 0:dc5ded118d7c 825 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 826 *
Sinan Divarci 0:dc5ded118d7c 827 * @details
Sinan Divarci 0:dc5ded118d7c 828 * - Register : AFC_CFG1 (0x07)
Sinan Divarci 0:dc5ded118d7c 829 * - Bit Fields : [1:0]
Sinan Divarci 0:dc5ded118d7c 830 * - Default : 0x2
Sinan Divarci 0:dc5ded118d7c 831 * - Description : AFC Loop Gain Control
Sinan Divarci 0:dc5ded118d7c 832 */
Sinan Divarci 0:dc5ded118d7c 833 typedef enum {
Sinan Divarci 0:dc5ded118d7c 834 AFC_LG_CONF_DEFAULT_X0_25, /**< 0x0: 1/4 Default */
Sinan Divarci 0:dc5ded118d7c 835 AFC_LG_CONF_DEFAULT_X0_5, /**< 0x1: 1/2 Default */
Sinan Divarci 0:dc5ded118d7c 836 AFC_LG_CONF_DEFAULT, /**< 0x2: Default gain, FSK typical setting */
Sinan Divarci 0:dc5ded118d7c 837 AFC_LG_CONF_DEFAULT_X2 /**< 0x3: 2x Default, ASK typical setting */
Sinan Divarci 0:dc5ded118d7c 838 } afc_lg_t;
Sinan Divarci 0:dc5ded118d7c 839
Sinan Divarci 0:dc5ded118d7c 840 /**
Sinan Divarci 0:dc5ded118d7c 841 * @brief Sets AFC Loop Gain Control
Sinan Divarci 0:dc5ded118d7c 842 *
Sinan Divarci 0:dc5ded118d7c 843 * @param[in] afc_lg
Sinan Divarci 0:dc5ded118d7c 844 *
Sinan Divarci 0:dc5ded118d7c 845 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 846 */
Sinan Divarci 0:dc5ded118d7c 847 int set_afc_lg(afc_lg_t afc_lg);
Sinan Divarci 0:dc5ded118d7c 848
Sinan Divarci 0:dc5ded118d7c 849 /**
Sinan Divarci 0:dc5ded118d7c 850 * @brief Gets AFC Loop Gain Control
Sinan Divarci 0:dc5ded118d7c 851 *
Sinan Divarci 0:dc5ded118d7c 852 * @param[in] afc_lg
Sinan Divarci 0:dc5ded118d7c 853 *
Sinan Divarci 0:dc5ded118d7c 854 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 855 */
Sinan Divarci 0:dc5ded118d7c 856 int get_afc_lg(afc_lg_t *afc_lg);
Sinan Divarci 0:dc5ded118d7c 857
Sinan Divarci 0:dc5ded118d7c 858 /**
Sinan Divarci 0:dc5ded118d7c 859 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 860 *
Sinan Divarci 0:dc5ded118d7c 861 * @details
Sinan Divarci 0:dc5ded118d7c 862 * - Register : AFC_CFG2 (0x08)
Sinan Divarci 0:dc5ded118d7c 863 * - Bit Fields : [6]
Sinan Divarci 0:dc5ded118d7c 864 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 865 * - Description : Control bit to Freeze AFC after Preamble Detected. Not used in ASK mode.
Sinan Divarci 0:dc5ded118d7c 866 */
Sinan Divarci 0:dc5ded118d7c 867 typedef enum {
Sinan Divarci 0:dc5ded118d7c 868 PAD_FREEZE_AFC_NOT_FREEZE, /**< 0x0: Not to freeze AFC */
Sinan Divarci 0:dc5ded118d7c 869 PAD_FREEZE_AFC_FREEZE /**< 0x1: Freeze AFC (stop PLL frequency update) once preamble is detected */
Sinan Divarci 0:dc5ded118d7c 870 } pad_freeze_afc_t;
Sinan Divarci 0:dc5ded118d7c 871
Sinan Divarci 0:dc5ded118d7c 872 /**
Sinan Divarci 0:dc5ded118d7c 873 * @brief Sets Control bit to Freeze AFC after Preamble Detected
Sinan Divarci 0:dc5ded118d7c 874 *
Sinan Divarci 0:dc5ded118d7c 875 * @param[in] pad_freeze_afc
Sinan Divarci 0:dc5ded118d7c 876 *
Sinan Divarci 0:dc5ded118d7c 877 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 878 */
Sinan Divarci 0:dc5ded118d7c 879 int set_pad_freeze_afc(pad_freeze_afc_t pad_freeze_afc);
Sinan Divarci 0:dc5ded118d7c 880
Sinan Divarci 0:dc5ded118d7c 881 /**
Sinan Divarci 0:dc5ded118d7c 882 * @brief Gets Control bit of Freeze AFC after Preamble Detected
Sinan Divarci 0:dc5ded118d7c 883 *
Sinan Divarci 0:dc5ded118d7c 884 * @param[in] pad_freeze_afc
Sinan Divarci 0:dc5ded118d7c 885 *
Sinan Divarci 0:dc5ded118d7c 886 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 887 */
Sinan Divarci 0:dc5ded118d7c 888 int get_pad_freeze_afc(pad_freeze_afc_t *pad_freeze_afc);
Sinan Divarci 0:dc5ded118d7c 889
Sinan Divarci 0:dc5ded118d7c 890 /**
Sinan Divarci 0:dc5ded118d7c 891 * @brief Gets LO Center Frequency, upper byte of 24-bit word (Register: LO_CTR_FREQ3 ,0x09)
Sinan Divarci 0:dc5ded118d7c 892 *
Sinan Divarci 0:dc5ded118d7c 893 * @param[in] lo_ctr_freq_upper
Sinan Divarci 0:dc5ded118d7c 894 *
Sinan Divarci 0:dc5ded118d7c 895 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 896 *
Sinan Divarci 0:dc5ded118d7c 897 * @description LO Center Frequency, upper byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 898 */
Sinan Divarci 0:dc5ded118d7c 899 int get_lo_ctr_freq_upper(uint8_t *lo_ctr_freq_upper);
Sinan Divarci 0:dc5ded118d7c 900
Sinan Divarci 0:dc5ded118d7c 901 /**
Sinan Divarci 0:dc5ded118d7c 902 * @brief Gets LO Center Frequency, middle byte of 24-bit word (Register: LO_CTR_FREQ2 ,0x0A)
Sinan Divarci 0:dc5ded118d7c 903 *
Sinan Divarci 0:dc5ded118d7c 904 * @param[in] lo_ctr_freq_middle
Sinan Divarci 0:dc5ded118d7c 905 *
Sinan Divarci 0:dc5ded118d7c 906 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 907 *
Sinan Divarci 0:dc5ded118d7c 908 * @description LO Center Frequency, middle byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 909 */
Sinan Divarci 0:dc5ded118d7c 910 int get_lo_ctr_freq_middle(uint8_t *lo_ctr_freq_middle);
Sinan Divarci 0:dc5ded118d7c 911
Sinan Divarci 0:dc5ded118d7c 912 /**
Sinan Divarci 0:dc5ded118d7c 913 * @brief Gets LO Center Frequency, lower byte of 24-bit word (Register: LO_CTR_FREQ1 ,0x0B)
Sinan Divarci 0:dc5ded118d7c 914 *
Sinan Divarci 0:dc5ded118d7c 915 * @param[in] lo_ctr_freq_lower
Sinan Divarci 0:dc5ded118d7c 916 *
Sinan Divarci 0:dc5ded118d7c 917 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 918 *
Sinan Divarci 0:dc5ded118d7c 919 * @description LO Center Frequency, lower byte of 24-bit word
Sinan Divarci 0:dc5ded118d7c 920 */
Sinan Divarci 0:dc5ded118d7c 921 int get_lo_ctr_freq_lower(uint8_t *lo_ctr_freq_lower);
Sinan Divarci 0:dc5ded118d7c 922
Sinan Divarci 0:dc5ded118d7c 923 /**
Sinan Divarci 0:dc5ded118d7c 924 * @brief Gets Preamble Bit Pattern Length before Manchester Coding (Register: PREAMBLE_CFG1 ,0x0C)
Sinan Divarci 0:dc5ded118d7c 925 *
Sinan Divarci 0:dc5ded118d7c 926 * @param[in] preamb_len
Sinan Divarci 0:dc5ded118d7c 927 *
Sinan Divarci 0:dc5ded118d7c 928 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 929 *
Sinan Divarci 0:dc5ded118d7c 930 * @description Preamble Bit Pattern Length before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 931 * Bit Pattern Length = Register Field Value +1
Sinan Divarci 0:dc5ded118d7c 932 */
Sinan Divarci 0:dc5ded118d7c 933 int get_preamb_len(uint8_t *preamb_len);
Sinan Divarci 0:dc5ded118d7c 934
Sinan Divarci 0:dc5ded118d7c 935 /**
Sinan Divarci 0:dc5ded118d7c 936 * @brief Gets Lower Byte of the Preamble Bit Pattern before Manchester Coding (Register: PREAMBLE_WORD1 ,0x0D)
Sinan Divarci 0:dc5ded118d7c 937 *
Sinan Divarci 0:dc5ded118d7c 938 * @param[in] preamb_word_lower
Sinan Divarci 0:dc5ded118d7c 939 *
Sinan Divarci 0:dc5ded118d7c 940 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 941 *
Sinan Divarci 0:dc5ded118d7c 942 * @description Lower Byte of the Preamble Bit Pattern before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 943 */
Sinan Divarci 0:dc5ded118d7c 944 int get_preamb_word_lower(uint8_t *preamb_word_lower);
Sinan Divarci 0:dc5ded118d7c 945
Sinan Divarci 0:dc5ded118d7c 946 /**
Sinan Divarci 0:dc5ded118d7c 947 * @brief Gets Upper Byte of the Preamble Bit Pattern before Manchester Coding (Register: PREAMBLE_WORD2 ,0x0E)
Sinan Divarci 0:dc5ded118d7c 948 *
Sinan Divarci 0:dc5ded118d7c 949 * @param[in] preamb_word_upper
Sinan Divarci 0:dc5ded118d7c 950 *
Sinan Divarci 0:dc5ded118d7c 951 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 952 *
Sinan Divarci 0:dc5ded118d7c 953 * @description Upper Byte of the Preamble Bit Pattern before Manchester Coding
Sinan Divarci 0:dc5ded118d7c 954 */
Sinan Divarci 0:dc5ded118d7c 955 int get_preamb_word_upper(uint8_t *preamb_word_upper);
Sinan Divarci 0:dc5ded118d7c 956
Sinan Divarci 0:dc5ded118d7c 957 /**
Sinan Divarci 0:dc5ded118d7c 958 * @brief Gets Received Signal Strength Indicator (RSSI) (Register: RSSI ,0x10)
Sinan Divarci 0:dc5ded118d7c 959 *
Sinan Divarci 0:dc5ded118d7c 960 * @param[in] rssi
Sinan Divarci 0:dc5ded118d7c 961 *
Sinan Divarci 0:dc5ded118d7c 962 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 963 *
Sinan Divarci 0:dc5ded118d7c 964 * @description Received Signal Strength Indicator (RSSI)
Sinan Divarci 0:dc5ded118d7c 965 * 8-bit unsigned integer
Sinan Divarci 0:dc5ded118d7c 966 */
Sinan Divarci 0:dc5ded118d7c 967 int get_rssi(uint8_t *rssi);
Sinan Divarci 0:dc5ded118d7c 968
Sinan Divarci 0:dc5ded118d7c 969 /**
Sinan Divarci 0:dc5ded118d7c 970 * @brief Gets AFC Frequency Error Indicator (FEI) (Register: FEI ,0x11)
Sinan Divarci 0:dc5ded118d7c 971 *
Sinan Divarci 0:dc5ded118d7c 972 * @param[in] fei
Sinan Divarci 0:dc5ded118d7c 973 *
Sinan Divarci 0:dc5ded118d7c 974 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 975 *
Sinan Divarci 0:dc5ded118d7c 976 * @description AFC Frequency Error Indicator (FEI)
Sinan Divarci 0:dc5ded118d7c 977 * 8-bit signed integer in two's complement format
Sinan Divarci 0:dc5ded118d7c 978 */
Sinan Divarci 0:dc5ded118d7c 979 int get_fei(uint8_t *fei);
Sinan Divarci 0:dc5ded118d7c 980
Sinan Divarci 0:dc5ded118d7c 981 /**
Sinan Divarci 0:dc5ded118d7c 982 * @brief Gets Post Demodulation Filter (PDF) Read Out (Register: PDF_OUT, 0x12)
Sinan Divarci 0:dc5ded118d7c 983 *
Sinan Divarci 0:dc5ded118d7c 984 * @param[in] pdf_out
Sinan Divarci 0:dc5ded118d7c 985 *
Sinan Divarci 0:dc5ded118d7c 986 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 987 *
Sinan Divarci 0:dc5ded118d7c 988 * @description Post Demodulation Filter (PDF) Read Out
Sinan Divarci 0:dc5ded118d7c 989 * 8-bit signed integer in two's complement format
Sinan Divarci 0:dc5ded118d7c 990 */
Sinan Divarci 0:dc5ded118d7c 991 int get_pdf_out(uint8_t *pdf_out);
Sinan Divarci 0:dc5ded118d7c 992
Sinan Divarci 0:dc5ded118d7c 993 /**
Sinan Divarci 0:dc5ded118d7c 994 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 995 *
Sinan Divarci 0:dc5ded118d7c 996 * @details
Sinan Divarci 0:dc5ded118d7c 997 * - Register : ISR (0x13)
Sinan Divarci 0:dc5ded118d7c 998 * - Bit Fields : [0]
Sinan Divarci 0:dc5ded118d7c 999 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 1000 * - Description : Interrupt Status Register Bit 0: preamble detector in self-polling mode
Sinan Divarci 0:dc5ded118d7c 1001 */
Sinan Divarci 0:dc5ded118d7c 1002 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1003 PREAMB_DET_NO_INT_EVENT, /**< 0x0: No interrupt event */
Sinan Divarci 0:dc5ded118d7c 1004 PREAMB_DET_PREAMB_DETECTED /**< 0x1: Preamble detected in self-polling */
Sinan Divarci 0:dc5ded118d7c 1005 } preamb_det_t;
Sinan Divarci 0:dc5ded118d7c 1006
Sinan Divarci 0:dc5ded118d7c 1007 /**
Sinan Divarci 0:dc5ded118d7c 1008 * @brief Gets Post Demodulation Filter (PDF) Read Out
Sinan Divarci 0:dc5ded118d7c 1009 *
Sinan Divarci 0:dc5ded118d7c 1010 * @param[in] preamb_det
Sinan Divarci 0:dc5ded118d7c 1011 *
Sinan Divarci 0:dc5ded118d7c 1012 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1013 */
Sinan Divarci 0:dc5ded118d7c 1014 int get_preamb_det(preamb_det_t *preamb_det);
Sinan Divarci 0:dc5ded118d7c 1015
Sinan Divarci 0:dc5ded118d7c 1016 /**
Sinan Divarci 0:dc5ded118d7c 1017 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1018 *
Sinan Divarci 0:dc5ded118d7c 1019 * @details
Sinan Divarci 0:dc5ded118d7c 1020 * - Register : CDR_CFG1 (0x35)
Sinan Divarci 0:dc5ded118d7c 1021 * - Bit Fields : [1:0]
Sinan Divarci 0:dc5ded118d7c 1022 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 1023 * - Description :
Sinan Divarci 0:dc5ded118d7c 1024 */
Sinan Divarci 0:dc5ded118d7c 1025 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1026 CDR_MODE_CDR_DISABLED, /**< 0x0: CDR disabled */
Sinan Divarci 0:dc5ded118d7c 1027 CDR_MODE_CLKOUT_EN_DATAOUT_UNTIMED, /**< 0x1: Clock out enabled, DATAOUT untimed */
Sinan Divarci 0:dc5ded118d7c 1028 CDR_MODE_CLKOUT_DIS_DATAOUT_RETIMED, /**< 0x2: Clock out disabled, DATAOUT retimed */
Sinan Divarci 0:dc5ded118d7c 1029 CDR_MODE_CLKOUT_EN_DATAOUT_RETIMED /**< 0x3: Clock out enabled, DATAOUT retimed */
Sinan Divarci 0:dc5ded118d7c 1030 } cdr_mode_t;
Sinan Divarci 0:dc5ded118d7c 1031
Sinan Divarci 0:dc5ded118d7c 1032 /**
Sinan Divarci 0:dc5ded118d7c 1033 * @brief Sets CDR_MODE
Sinan Divarci 0:dc5ded118d7c 1034 *
Sinan Divarci 0:dc5ded118d7c 1035 * @param[in] cdr_mode
Sinan Divarci 0:dc5ded118d7c 1036 *
Sinan Divarci 0:dc5ded118d7c 1037 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1038 */
Sinan Divarci 0:dc5ded118d7c 1039 int set_cdr_mode(cdr_mode_t cdr_mode);
Sinan Divarci 0:dc5ded118d7c 1040
Sinan Divarci 0:dc5ded118d7c 1041 /**
Sinan Divarci 0:dc5ded118d7c 1042 * @brief Gets CDR_MODE
Sinan Divarci 0:dc5ded118d7c 1043 *
Sinan Divarci 0:dc5ded118d7c 1044 * @param[in] cdr_mode
Sinan Divarci 0:dc5ded118d7c 1045 *
Sinan Divarci 0:dc5ded118d7c 1046 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1047 */
Sinan Divarci 0:dc5ded118d7c 1048 int get_cdr_mode(cdr_mode_t *cdr_mode);
Sinan Divarci 0:dc5ded118d7c 1049
Sinan Divarci 0:dc5ded118d7c 1050 /**
Sinan Divarci 0:dc5ded118d7c 1051 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1052 *
Sinan Divarci 0:dc5ded118d7c 1053 * @details
Sinan Divarci 0:dc5ded118d7c 1054 * - Register : STATE_CTRL1 (0x14)
Sinan Divarci 0:dc5ded118d7c 1055 * - Bit Fields : [2]
Sinan Divarci 0:dc5ded118d7c 1056 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 1057 * - Description : XO Enable Bit
Sinan Divarci 0:dc5ded118d7c 1058 */
Sinan Divarci 0:dc5ded118d7c 1059 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1060 EN_XO_DIS_XO, /**< 0x0: Disable XO */
Sinan Divarci 0:dc5ded118d7c 1061 EN_XO_EN_XO /**< 0x1: Enable XO */
Sinan Divarci 0:dc5ded118d7c 1062 } en_xo_t;
Sinan Divarci 0:dc5ded118d7c 1063
Sinan Divarci 0:dc5ded118d7c 1064 /**
Sinan Divarci 0:dc5ded118d7c 1065 * @brief Sets XO Enable Bit
Sinan Divarci 0:dc5ded118d7c 1066 *
Sinan Divarci 0:dc5ded118d7c 1067 * @param[in] en_xo
Sinan Divarci 0:dc5ded118d7c 1068 *
Sinan Divarci 0:dc5ded118d7c 1069 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1070 */
Sinan Divarci 0:dc5ded118d7c 1071 int set_en_xo(en_xo_t en_xo);
Sinan Divarci 0:dc5ded118d7c 1072
Sinan Divarci 0:dc5ded118d7c 1073 /**
Sinan Divarci 0:dc5ded118d7c 1074 * @brief Gets XO Enable Bit
Sinan Divarci 0:dc5ded118d7c 1075 *
Sinan Divarci 0:dc5ded118d7c 1076 * @param[in] en_xo
Sinan Divarci 0:dc5ded118d7c 1077 *
Sinan Divarci 0:dc5ded118d7c 1078 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1079 */
Sinan Divarci 0:dc5ded118d7c 1080 int get_en_xo(en_xo_t *en_xo);
Sinan Divarci 0:dc5ded118d7c 1081
Sinan Divarci 0:dc5ded118d7c 1082 /**
Sinan Divarci 0:dc5ded118d7c 1083 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1084 *
Sinan Divarci 0:dc5ded118d7c 1085 * @details
Sinan Divarci 0:dc5ded118d7c 1086 * - Register : STATE_CTRL1 (0x14)
Sinan Divarci 0:dc5ded118d7c 1087 * - Bit Fields : [1]
Sinan Divarci 0:dc5ded118d7c 1088 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 1089 * - Description : Wake-Up Timer (WUT) Enable Bit
Sinan Divarci 0:dc5ded118d7c 1090 */
Sinan Divarci 0:dc5ded118d7c 1091 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1092 WUT_EN_DIS_WUT, /**< 0x0: Disable WUT */
Sinan Divarci 0:dc5ded118d7c 1093 WUT_EN_EN_WUT /**< 0x1: Enable WUT */
Sinan Divarci 0:dc5ded118d7c 1094 } wut_en_t;
Sinan Divarci 0:dc5ded118d7c 1095
Sinan Divarci 0:dc5ded118d7c 1096 /**
Sinan Divarci 0:dc5ded118d7c 1097 * @brief Sets Wake-Up Timer (WUT) Enable Bit
Sinan Divarci 0:dc5ded118d7c 1098 *
Sinan Divarci 0:dc5ded118d7c 1099 * @param[in] wut_en
Sinan Divarci 0:dc5ded118d7c 1100 *
Sinan Divarci 0:dc5ded118d7c 1101 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1102 */
Sinan Divarci 0:dc5ded118d7c 1103 int set_wut_en(wut_en_t wut_en);
Sinan Divarci 0:dc5ded118d7c 1104
Sinan Divarci 0:dc5ded118d7c 1105 /**
Sinan Divarci 0:dc5ded118d7c 1106 * @brief Gets Wake-Up Timer (WUT) Enable Bit
Sinan Divarci 0:dc5ded118d7c 1107 *
Sinan Divarci 0:dc5ded118d7c 1108 * @param[in] wut_en
Sinan Divarci 0:dc5ded118d7c 1109 *
Sinan Divarci 0:dc5ded118d7c 1110 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1111 */
Sinan Divarci 0:dc5ded118d7c 1112 int get_wut_en(wut_en_t *wut_en);
Sinan Divarci 0:dc5ded118d7c 1113
Sinan Divarci 0:dc5ded118d7c 1114 /**
Sinan Divarci 0:dc5ded118d7c 1115 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1116 *
Sinan Divarci 0:dc5ded118d7c 1117 * @details
Sinan Divarci 0:dc5ded118d7c 1118 * - Register : STATE_CTRL1 (0x14)
Sinan Divarci 0:dc5ded118d7c 1119 * - Bit Fields : [0]
Sinan Divarci 0:dc5ded118d7c 1120 * - Default : 0x0
Sinan Divarci 0:dc5ded118d7c 1121 * - Description : Slave Receiver Enable Bit
Sinan Divarci 0:dc5ded118d7c 1122 */
Sinan Divarci 0:dc5ded118d7c 1123 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1124 SLAVE_RX_EN_DIS_RECEIVER, /**< 0x0: Disable Receiver */
Sinan Divarci 0:dc5ded118d7c 1125 SLAVE_RX_EN_EN_RECEIVER /**< 0x1: Enable Receiver */
Sinan Divarci 0:dc5ded118d7c 1126 } slave_rx_en_t;
Sinan Divarci 0:dc5ded118d7c 1127
Sinan Divarci 0:dc5ded118d7c 1128 /**
Sinan Divarci 0:dc5ded118d7c 1129 * @brief Sets Slave Receiver Enable Bit
Sinan Divarci 0:dc5ded118d7c 1130 *
Sinan Divarci 0:dc5ded118d7c 1131 * @param[in] slave_rx_en
Sinan Divarci 0:dc5ded118d7c 1132 *
Sinan Divarci 0:dc5ded118d7c 1133 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1134 */
Sinan Divarci 0:dc5ded118d7c 1135 int set_slave_rx_en(slave_rx_en_t slave_rx_en);
Sinan Divarci 0:dc5ded118d7c 1136
Sinan Divarci 0:dc5ded118d7c 1137 /**
Sinan Divarci 0:dc5ded118d7c 1138 * @brief Gets Slave Receiver Enable Bit
Sinan Divarci 0:dc5ded118d7c 1139 *
Sinan Divarci 0:dc5ded118d7c 1140 * @param[in] slave_rx_en
Sinan Divarci 0:dc5ded118d7c 1141 *
Sinan Divarci 0:dc5ded118d7c 1142 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1143 */
Sinan Divarci 0:dc5ded118d7c 1144 int get_slave_rx_en(slave_rx_en_t *slave_rx_en);
Sinan Divarci 0:dc5ded118d7c 1145
Sinan Divarci 0:dc5ded118d7c 1146 /**
Sinan Divarci 0:dc5ded118d7c 1147 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1148 *
Sinan Divarci 0:dc5ded118d7c 1149 * @details
Sinan Divarci 0:dc5ded118d7c 1150 * - Register : STATE_CTRL2 (0x15)
Sinan Divarci 0:dc5ded118d7c 1151 * - Bit Fields : [1:0]
Sinan Divarci 0:dc5ded118d7c 1152 * - Default :
Sinan Divarci 0:dc5ded118d7c 1153 * - Description : Receiver State Machine Register
Sinan Divarci 0:dc5ded118d7c 1154 */
Sinan Divarci 0:dc5ded118d7c 1155 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1156 RX_STATE_STANDBY, /**< 0x0: Standby */
Sinan Divarci 0:dc5ded118d7c 1157 RX_STATE_SLAVE_RECEIVER, /**< 0x1: Slave receiver */
Sinan Divarci 0:dc5ded118d7c 1158 RX_STATE_W_IN_SELFPOLLING, /**< 0x2: Wait in self-polling */
Sinan Divarci 0:dc5ded118d7c 1159 RX_STATE_POLLING_RECEIVER /**< 0x3: Polling receiver */
Sinan Divarci 0:dc5ded118d7c 1160 } rx_state_t;
Sinan Divarci 0:dc5ded118d7c 1161
Sinan Divarci 0:dc5ded118d7c 1162 /**
Sinan Divarci 0:dc5ded118d7c 1163 * @brief Gets Receiver State Machine Register
Sinan Divarci 0:dc5ded118d7c 1164 *
Sinan Divarci 0:dc5ded118d7c 1165 * @param[in] rx_state
Sinan Divarci 0:dc5ded118d7c 1166 *
Sinan Divarci 0:dc5ded118d7c 1167 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1168 */
Sinan Divarci 0:dc5ded118d7c 1169 int get_rx_state(rx_state_t *rx_state);
Sinan Divarci 0:dc5ded118d7c 1170
Sinan Divarci 0:dc5ded118d7c 1171 /**
Sinan Divarci 0:dc5ded118d7c 1172 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1173 *
Sinan Divarci 0:dc5ded118d7c 1174 * @details
Sinan Divarci 0:dc5ded118d7c 1175 * - Register : STATE_CTRL3 (0x16)
Sinan Divarci 0:dc5ded118d7c 1176 * - Bit Fields : [1:0]
Sinan Divarci 0:dc5ded118d7c 1177 * - Default : 0x03
Sinan Divarci 0:dc5ded118d7c 1178 * - Description : Receiver Front-End Turn-On Time
Sinan Divarci 0:dc5ded118d7c 1179 */
Sinan Divarci 0:dc5ded118d7c 1180 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1181 RX_RESET_TIME_80US, /**< 0x0: 0.08ms */
Sinan Divarci 0:dc5ded118d7c 1182 RX_RESET_TIME_160US, /**< 0x1: 0.16ms */
Sinan Divarci 0:dc5ded118d7c 1183 RX_RESET_TIME_240US, /**< 0x2: 0.24ms */
Sinan Divarci 0:dc5ded118d7c 1184 RX_RESET_TIME_320US /**< 0x3: 0.32ms */
Sinan Divarci 0:dc5ded118d7c 1185 } rx_reset_time_t;
Sinan Divarci 0:dc5ded118d7c 1186
Sinan Divarci 0:dc5ded118d7c 1187 /**
Sinan Divarci 0:dc5ded118d7c 1188 * @brief Sets Receiver Front-End Turn-On Time
Sinan Divarci 0:dc5ded118d7c 1189 *
Sinan Divarci 0:dc5ded118d7c 1190 * @param[in] rx_reset_time
Sinan Divarci 0:dc5ded118d7c 1191 *
Sinan Divarci 0:dc5ded118d7c 1192 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1193 */
Sinan Divarci 0:dc5ded118d7c 1194 int set_rx_reset_time(rx_reset_time_t rx_reset_time);
Sinan Divarci 0:dc5ded118d7c 1195
Sinan Divarci 0:dc5ded118d7c 1196 /**
Sinan Divarci 0:dc5ded118d7c 1197 * @brief Gets Receiver Front-End Turn-On Time
Sinan Divarci 0:dc5ded118d7c 1198 *
Sinan Divarci 0:dc5ded118d7c 1199 * @param[in] rx_reset_time
Sinan Divarci 0:dc5ded118d7c 1200 *
Sinan Divarci 0:dc5ded118d7c 1201 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1202 */
Sinan Divarci 0:dc5ded118d7c 1203 int get_rx_reset_time(rx_reset_time_t *rx_reset_time);
Sinan Divarci 0:dc5ded118d7c 1204
Sinan Divarci 0:dc5ded118d7c 1205 /**
Sinan Divarci 0:dc5ded118d7c 1206 * @brief Sets Duration in POLLINGRX State (Register: WUT1, 0x17)
Sinan Divarci 0:dc5ded118d7c 1207 *
Sinan Divarci 0:dc5ded118d7c 1208 * @param[in] tdet
Sinan Divarci 0:dc5ded118d7c 1209 *
Sinan Divarci 0:dc5ded118d7c 1210 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1211 *
Sinan Divarci 0:dc5ded118d7c 1212 * @description Duration in POLLINGRX State: from 0.48ms to 20.88ms, in step size of 0.08ms
Sinan Divarci 0:dc5ded118d7c 1213 * Duration (ms) = 0.48 + 0.08 x (tdet)
Sinan Divarci 0:dc5ded118d7c 1214 */
Sinan Divarci 0:dc5ded118d7c 1215 int set_tdet(uint8_t tdet);
Sinan Divarci 0:dc5ded118d7c 1216
Sinan Divarci 0:dc5ded118d7c 1217 /**
Sinan Divarci 0:dc5ded118d7c 1218 * @brief Gets Duration in POLLINGRX State (Register: WUT1, 0x17)
Sinan Divarci 0:dc5ded118d7c 1219 *
Sinan Divarci 0:dc5ded118d7c 1220 * @param[in] tdet
Sinan Divarci 0:dc5ded118d7c 1221 *
Sinan Divarci 0:dc5ded118d7c 1222 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1223 *
Sinan Divarci 0:dc5ded118d7c 1224 * @description Duration in POLLINGRX State: from 0.48ms to 20.88ms, in step size of 0.08ms
Sinan Divarci 0:dc5ded118d7c 1225 * Duration (ms) = 0.48 + 0.08 x (tdet)
Sinan Divarci 0:dc5ded118d7c 1226 */
Sinan Divarci 0:dc5ded118d7c 1227 int get_tdet(uint8_t *tdet);
Sinan Divarci 0:dc5ded118d7c 1228
Sinan Divarci 0:dc5ded118d7c 1229 /**
Sinan Divarci 0:dc5ded118d7c 1230 * @brief Sets WUT Duty Cycle Control (Register: WUT2, 0x18)
Sinan Divarci 0:dc5ded118d7c 1231 *
Sinan Divarci 0:dc5ded118d7c 1232 * @param[in] tsby_tdet_ratio
Sinan Divarci 0:dc5ded118d7c 1233 *
Sinan Divarci 0:dc5ded118d7c 1234 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1235 *
Sinan Divarci 0:dc5ded118d7c 1236 * @description Duty Cycle = 1 / (2 + tsby_tdet_ratio)
Sinan Divarci 0:dc5ded118d7c 1237 */
Sinan Divarci 0:dc5ded118d7c 1238 int set_tsby_tdet_ratio(uint8_t tsby_tdet_ratio);
Sinan Divarci 0:dc5ded118d7c 1239
Sinan Divarci 0:dc5ded118d7c 1240 /**
Sinan Divarci 0:dc5ded118d7c 1241 * @brief Gets WUT Duty Cycle Control (WUT2, 0x18)
Sinan Divarci 0:dc5ded118d7c 1242 *
Sinan Divarci 0:dc5ded118d7c 1243 * @param[in] tsby_tdet_ratio
Sinan Divarci 0:dc5ded118d7c 1244 *
Sinan Divarci 0:dc5ded118d7c 1245 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1246 *
Sinan Divarci 0:dc5ded118d7c 1247 * @description Duty Cycle = 1 / (2 + tsby_tdet_ratio)
Sinan Divarci 0:dc5ded118d7c 1248 */
Sinan Divarci 0:dc5ded118d7c 1249 int get_tsby_tdet_ratio(uint8_t *tsby_tdet_ratio);
Sinan Divarci 0:dc5ded118d7c 1250
Sinan Divarci 0:dc5ded118d7c 1251 /**
Sinan Divarci 0:dc5ded118d7c 1252 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1253 *
Sinan Divarci 0:dc5ded118d7c 1254 * @details
Sinan Divarci 0:dc5ded118d7c 1255 * - Register : AFE_CTL1 (0x19)
Sinan Divarci 0:dc5ded118d7c 1256 * - Bit Fields : [7:6]
Sinan Divarci 0:dc5ded118d7c 1257 * - Default : 0x02
Sinan Divarci 0:dc5ded118d7c 1258 * - Description : Start Delay before Applying XO Clock to Digital
Sinan Divarci 0:dc5ded118d7c 1259 */
Sinan Divarci 0:dc5ded118d7c 1260 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1261 XOCLKDELAY_NO_DELAY, /**< 0x0: No delay */
Sinan Divarci 0:dc5ded118d7c 1262 XOCLKDELAY_16_CYCLE, /**< 0x1: 16 cycle delay */
Sinan Divarci 0:dc5ded118d7c 1263 XOCLKDELAY_32_CYCLE, /**< 0x2: 32 cycle delay */
Sinan Divarci 0:dc5ded118d7c 1264 XOCLKDELAY_64_CYCLE /**< 0x3: 64 cycle delay */
Sinan Divarci 0:dc5ded118d7c 1265 } xoclkdelay_t;
Sinan Divarci 0:dc5ded118d7c 1266
Sinan Divarci 0:dc5ded118d7c 1267 /**
Sinan Divarci 0:dc5ded118d7c 1268 * @brief Sets Start Delay before Applying XO Clock to Digital
Sinan Divarci 0:dc5ded118d7c 1269 *
Sinan Divarci 0:dc5ded118d7c 1270 * @param[in] xoclkdelay
Sinan Divarci 0:dc5ded118d7c 1271 *
Sinan Divarci 0:dc5ded118d7c 1272 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1273 */
Sinan Divarci 0:dc5ded118d7c 1274 int set_xoclkdelay(xoclkdelay_t xoclkdelay);
Sinan Divarci 0:dc5ded118d7c 1275
Sinan Divarci 0:dc5ded118d7c 1276 /**
Sinan Divarci 0:dc5ded118d7c 1277 * @brief Gets Start Delay before Applying XO Clock to Digital
Sinan Divarci 0:dc5ded118d7c 1278 *
Sinan Divarci 0:dc5ded118d7c 1279 * @param[in] xoclkdelay
Sinan Divarci 0:dc5ded118d7c 1280 *
Sinan Divarci 0:dc5ded118d7c 1281 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1282 */
Sinan Divarci 0:dc5ded118d7c 1283 int get_xoclkdelay(xoclkdelay_t *xoclkdelay);
Sinan Divarci 0:dc5ded118d7c 1284
Sinan Divarci 0:dc5ded118d7c 1285 /**
Sinan Divarci 0:dc5ded118d7c 1286 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1287 *
Sinan Divarci 0:dc5ded118d7c 1288 * @details
Sinan Divarci 0:dc5ded118d7c 1289 * - Register : AFE_CTL1 (0x19)
Sinan Divarci 0:dc5ded118d7c 1290 * - Bit Fields : [5:4]
Sinan Divarci 0:dc5ded118d7c 1291 * - Default : 0x01
Sinan Divarci 0:dc5ded118d7c 1292 * - Description : XO Clock Divider Ratio
Sinan Divarci 0:dc5ded118d7c 1293 */
Sinan Divarci 0:dc5ded118d7c 1294 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1295 XOCLKDIV_DIVIDE_BY_4, /**< 0x0: Divide by 4 */
Sinan Divarci 0:dc5ded118d7c 1296 XOCLKDIV_DIVIDE_BY_5, /**< 0x1: Divide by 5 */
Sinan Divarci 0:dc5ded118d7c 1297 XOCLKDIV_DIVIDE_BY_6, /**< 0x2: Divide by 6 */
Sinan Divarci 0:dc5ded118d7c 1298 XOCLKDIV_INVALID /**< 0x3: Invalid Value */
Sinan Divarci 0:dc5ded118d7c 1299 } xoclkdiv_t;
Sinan Divarci 0:dc5ded118d7c 1300
Sinan Divarci 0:dc5ded118d7c 1301 /**
Sinan Divarci 0:dc5ded118d7c 1302 * @brief Sets Start Delay before Applying XO Clock to Digital
Sinan Divarci 0:dc5ded118d7c 1303 *
Sinan Divarci 0:dc5ded118d7c 1304 * @param[in] xoclkdiv
Sinan Divarci 0:dc5ded118d7c 1305 *
Sinan Divarci 0:dc5ded118d7c 1306 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1307 */
Sinan Divarci 0:dc5ded118d7c 1308 int set_xoclkdiv(xoclkdiv_t xoclkdiv);
Sinan Divarci 0:dc5ded118d7c 1309
Sinan Divarci 0:dc5ded118d7c 1310 /**
Sinan Divarci 0:dc5ded118d7c 1311 * @brief Gets Start Delay before Applying XO Clock to Digital
Sinan Divarci 0:dc5ded118d7c 1312 *
Sinan Divarci 0:dc5ded118d7c 1313 * @param[in] xoclkdelay
Sinan Divarci 0:dc5ded118d7c 1314 *
Sinan Divarci 0:dc5ded118d7c 1315 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1316 */
Sinan Divarci 0:dc5ded118d7c 1317 int get_xoclkdiv(xoclkdiv_t *xoclkdiv);
Sinan Divarci 0:dc5ded118d7c 1318
Sinan Divarci 0:dc5ded118d7c 1319 /**
Sinan Divarci 0:dc5ded118d7c 1320 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1321 *
Sinan Divarci 0:dc5ded118d7c 1322 * @details
Sinan Divarci 0:dc5ded118d7c 1323 * - Register : AFE_CTL1 (0x19)
Sinan Divarci 0:dc5ded118d7c 1324 * - Bit Fields : [3]
Sinan Divarci 0:dc5ded118d7c 1325 * - Default : 0x00
Sinan Divarci 0:dc5ded118d7c 1326 * - Description : LO Injection Control
Sinan Divarci 0:dc5ded118d7c 1327 */
Sinan Divarci 0:dc5ded118d7c 1328 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1329 MIX_HS_LSBAR_TARGET_HT_LO_FREQ, /**< 0x0: Targeted RF frequency higher than LO frequency */
Sinan Divarci 0:dc5ded118d7c 1330 MIX_HS_LSBAR_TARGET_LT_LO_FREQ /**< 0x1: Targeted RF frequency lower than LO frequency */
Sinan Divarci 0:dc5ded118d7c 1331 } mix_hs_lsbar_t;
Sinan Divarci 0:dc5ded118d7c 1332
Sinan Divarci 0:dc5ded118d7c 1333 /**
Sinan Divarci 0:dc5ded118d7c 1334 * @brief Sets LO Injection Control
Sinan Divarci 0:dc5ded118d7c 1335 *
Sinan Divarci 0:dc5ded118d7c 1336 * @param[in] mix_hs_ls_bar
Sinan Divarci 0:dc5ded118d7c 1337 *
Sinan Divarci 0:dc5ded118d7c 1338 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1339 */
Sinan Divarci 0:dc5ded118d7c 1340 int set_mix_hs_lsbar(mix_hs_lsbar_t mix_hs_lsbar);
Sinan Divarci 0:dc5ded118d7c 1341
Sinan Divarci 0:dc5ded118d7c 1342 /**
Sinan Divarci 0:dc5ded118d7c 1343 * @brief Gets LO Injection Control
Sinan Divarci 0:dc5ded118d7c 1344 *
Sinan Divarci 0:dc5ded118d7c 1345 * @param[in] mix_hs_ls_bar
Sinan Divarci 0:dc5ded118d7c 1346 *
Sinan Divarci 0:dc5ded118d7c 1347 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1348 */
Sinan Divarci 0:dc5ded118d7c 1349 int get_mix_hs_lsbar(mix_hs_lsbar_t *mix_hs_lsbar);
Sinan Divarci 0:dc5ded118d7c 1350
Sinan Divarci 0:dc5ded118d7c 1351 /**
Sinan Divarci 0:dc5ded118d7c 1352 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1353 *
Sinan Divarci 0:dc5ded118d7c 1354 * @details
Sinan Divarci 0:dc5ded118d7c 1355 * - Register : AFE_CTL1 (0x19)
Sinan Divarci 0:dc5ded118d7c 1356 * - Bit Fields : [2:1]
Sinan Divarci 0:dc5ded118d7c 1357 * - Default : 0x01
Sinan Divarci 0:dc5ded118d7c 1358 * - Description : LO Divider Control
Sinan Divarci 0:dc5ded118d7c 1359 */
Sinan Divarci 0:dc5ded118d7c 1360 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1361 LODIV_PLL_DISABLED, /**< 0x0: PLL disabled */
Sinan Divarci 0:dc5ded118d7c 1362 LODIV_860MHZ_TO_960MHZ, /**< 0x1: 860MHz to 960MHz */
Sinan Divarci 0:dc5ded118d7c 1363 LODIV_425MHZ_TO_480MHZ, /**< 0x2: 425MHz to 480MHz */
Sinan Divarci 0:dc5ded118d7c 1364 LODIV_286MHZ_TO_320MHZ, /**< 0x3: 286MHz to 320MHz */
Sinan Divarci 0:dc5ded118d7c 1365 } lodiv_t;
Sinan Divarci 0:dc5ded118d7c 1366
Sinan Divarci 0:dc5ded118d7c 1367 /**
Sinan Divarci 0:dc5ded118d7c 1368 * @brief Sets LO Divider Control
Sinan Divarci 0:dc5ded118d7c 1369 *
Sinan Divarci 0:dc5ded118d7c 1370 * @param[in] lodiv
Sinan Divarci 0:dc5ded118d7c 1371 *
Sinan Divarci 0:dc5ded118d7c 1372 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1373 */
Sinan Divarci 0:dc5ded118d7c 1374 int set_lodiv(lodiv_t lodiv);
Sinan Divarci 0:dc5ded118d7c 1375
Sinan Divarci 0:dc5ded118d7c 1376 /**
Sinan Divarci 0:dc5ded118d7c 1377 * @brief Gets LO Divider Control
Sinan Divarci 0:dc5ded118d7c 1378 *
Sinan Divarci 0:dc5ded118d7c 1379 * @param[in] lodiv
Sinan Divarci 0:dc5ded118d7c 1380 *
Sinan Divarci 0:dc5ded118d7c 1381 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1382 */
Sinan Divarci 0:dc5ded118d7c 1383 int get_lodiv(lodiv_t *lodiv);
Sinan Divarci 0:dc5ded118d7c 1384
Sinan Divarci 0:dc5ded118d7c 1385 /**
Sinan Divarci 0:dc5ded118d7c 1386 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1387 *
Sinan Divarci 0:dc5ded118d7c 1388 * @details
Sinan Divarci 0:dc5ded118d7c 1389 * - Register : AFE_CTL1 (0x19)
Sinan Divarci 0:dc5ded118d7c 1390 * - Bit Fields : [0]
Sinan Divarci 0:dc5ded118d7c 1391 * - Default : 0x01
Sinan Divarci 0:dc5ded118d7c 1392 * - Description : PLL Mode Control: always program to 1
Sinan Divarci 0:dc5ded118d7c 1393 */
Sinan Divarci 0:dc5ded118d7c 1394 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1395 FRACMODE_INTEGER_N_PLL, /**< 0x0: Integer-N PLL */
Sinan Divarci 0:dc5ded118d7c 1396 FRACMODE_FRACTIONAL_N_PLL /**< 0x1: Fractional-N PLL */
Sinan Divarci 0:dc5ded118d7c 1397 } fracmode_t;
Sinan Divarci 0:dc5ded118d7c 1398
Sinan Divarci 0:dc5ded118d7c 1399 /**
Sinan Divarci 0:dc5ded118d7c 1400 * @brief Sets PLL Mode Control
Sinan Divarci 0:dc5ded118d7c 1401 *
Sinan Divarci 0:dc5ded118d7c 1402 * @param[in] fracmode
Sinan Divarci 0:dc5ded118d7c 1403 *
Sinan Divarci 0:dc5ded118d7c 1404 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1405 */
Sinan Divarci 0:dc5ded118d7c 1406 int set_fracmode(fracmode_t fracmode);
Sinan Divarci 0:dc5ded118d7c 1407
Sinan Divarci 0:dc5ded118d7c 1408 /**
Sinan Divarci 0:dc5ded118d7c 1409 * @brief Gets PLL Mode Control
Sinan Divarci 0:dc5ded118d7c 1410 *
Sinan Divarci 0:dc5ded118d7c 1411 * @param[in] fracmode
Sinan Divarci 0:dc5ded118d7c 1412 *
Sinan Divarci 0:dc5ded118d7c 1413 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1414 */
Sinan Divarci 0:dc5ded118d7c 1415 int get_fracmode(fracmode_t *fracmode);
Sinan Divarci 0:dc5ded118d7c 1416
Sinan Divarci 0:dc5ded118d7c 1417 /**
Sinan Divarci 0:dc5ded118d7c 1418 * @brief Sets Image Rejection Adjustment (Register: IR_ADJUST ,0x1A)
Sinan Divarci 0:dc5ded118d7c 1419 *
Sinan Divarci 0:dc5ded118d7c 1420 * @param[in] ir_adjust
Sinan Divarci 0:dc5ded118d7c 1421 *
Sinan Divarci 0:dc5ded118d7c 1422 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1423 *
Sinan Divarci 0:dc5ded118d7c 1424 * @description Image Rejection Adjustment. See the Image Rejection Calibration section for more information.
Sinan Divarci 0:dc5ded118d7c 1425 */
Sinan Divarci 0:dc5ded118d7c 1426 int set_ir_adjust(uint8_t ir_adjust);
Sinan Divarci 0:dc5ded118d7c 1427
Sinan Divarci 0:dc5ded118d7c 1428 /**
Sinan Divarci 0:dc5ded118d7c 1429 * @brief Gets Image Rejection Adjustment (Register: IR_ADJUST ,0x1A)
Sinan Divarci 0:dc5ded118d7c 1430 *
Sinan Divarci 0:dc5ded118d7c 1431 * @param[in] ir_adjust
Sinan Divarci 0:dc5ded118d7c 1432 *
Sinan Divarci 0:dc5ded118d7c 1433 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1434 *
Sinan Divarci 0:dc5ded118d7c 1435 * @description Image Rejection Adjustment. See the Image Rejection Calibration section for more information.
Sinan Divarci 0:dc5ded118d7c 1436 */
Sinan Divarci 0:dc5ded118d7c 1437 int get_ir_adjust(uint8_t *ir_adjust);
Sinan Divarci 0:dc5ded118d7c 1438
Sinan Divarci 0:dc5ded118d7c 1439 /**
Sinan Divarci 0:dc5ded118d7c 1440 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1441 *
Sinan Divarci 0:dc5ded118d7c 1442 * @details
Sinan Divarci 0:dc5ded118d7c 1443 * - Register : PART_NUM (0x1E)
Sinan Divarci 0:dc5ded118d7c 1444 * - Bit Fields : [7:0]
Sinan Divarci 0:dc5ded118d7c 1445 * - Default :
Sinan Divarci 0:dc5ded118d7c 1446 * - Description : Part Number Designator.
Sinan Divarci 0:dc5ded118d7c 1447 * Read of part number requires EN_XO = 1
Sinan Divarci 0:dc5ded118d7c 1448 */
Sinan Divarci 0:dc5ded118d7c 1449 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1450 PART_NUM_MAX41470 = 0x70, /**< 0x70 = MAX41470 */
Sinan Divarci 0:dc5ded118d7c 1451 PART_NUM_MAX41473 = 0x73, /**< 0x73 = MAX41473 */
Sinan Divarci 0:dc5ded118d7c 1452 PART_NUM_MAX41474 = 0x74 /**< 0x74 = MAX41474 */
Sinan Divarci 0:dc5ded118d7c 1453 } part_num_t;
Sinan Divarci 0:dc5ded118d7c 1454
Sinan Divarci 0:dc5ded118d7c 1455 /**
Sinan Divarci 0:dc5ded118d7c 1456 * @brief Gets Part Number Designator
Sinan Divarci 0:dc5ded118d7c 1457 *
Sinan Divarci 0:dc5ded118d7c 1458 * @param[in] part_num
Sinan Divarci 0:dc5ded118d7c 1459 *
Sinan Divarci 0:dc5ded118d7c 1460 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1461 */
Sinan Divarci 0:dc5ded118d7c 1462 int get_part_num(part_num_t *part_num);
Sinan Divarci 0:dc5ded118d7c 1463
Sinan Divarci 0:dc5ded118d7c 1464 /**
Sinan Divarci 0:dc5ded118d7c 1465 * @brief Gets Revision Number of Chip (Register: REV_NUM ,0x1F)
Sinan Divarci 0:dc5ded118d7c 1466 *
Sinan Divarci 0:dc5ded118d7c 1467 * @param[in] rev_num
Sinan Divarci 0:dc5ded118d7c 1468 *
Sinan Divarci 0:dc5ded118d7c 1469 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1470 *
Sinan Divarci 0:dc5ded118d7c 1471 * @description Revision Number of Chip
Sinan Divarci 0:dc5ded118d7c 1472 */
Sinan Divarci 0:dc5ded118d7c 1473 int get_rev_num(uint8_t *rev_num);
Sinan Divarci 0:dc5ded118d7c 1474
Sinan Divarci 0:dc5ded118d7c 1475 /**
Sinan Divarci 0:dc5ded118d7c 1476 * @brief Register Configuration
Sinan Divarci 0:dc5ded118d7c 1477 *
Sinan Divarci 0:dc5ded118d7c 1478 * @details
Sinan Divarci 0:dc5ded118d7c 1479 * - Register : STATUS (0x27)
Sinan Divarci 0:dc5ded118d7c 1480 * - Bit Fields : [0]
Sinan Divarci 0:dc5ded118d7c 1481 * - Default :
Sinan Divarci 0:dc5ded118d7c 1482 * - Description : PLL Lock Status
Sinan Divarci 0:dc5ded118d7c 1483 */
Sinan Divarci 0:dc5ded118d7c 1484 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1485 PLL_LOCK_NOT_LOCKED, /**< 0x0: PLL is not locked */
Sinan Divarci 0:dc5ded118d7c 1486 PLL_LOCK_LOCKED /**< 0x1: PLL is locked */
Sinan Divarci 0:dc5ded118d7c 1487 } pll_lock_t;
Sinan Divarci 0:dc5ded118d7c 1488
Sinan Divarci 0:dc5ded118d7c 1489 /**
Sinan Divarci 0:dc5ded118d7c 1490 * @brief Gets PLL Lock Status
Sinan Divarci 0:dc5ded118d7c 1491 *
Sinan Divarci 0:dc5ded118d7c 1492 * @param[in] pll_lock
Sinan Divarci 0:dc5ded118d7c 1493 *
Sinan Divarci 0:dc5ded118d7c 1494 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1495 */
Sinan Divarci 0:dc5ded118d7c 1496 int get_pll_lock(pll_lock_t *pll_lock);
Sinan Divarci 0:dc5ded118d7c 1497
Sinan Divarci 0:dc5ded118d7c 1498 /**
Sinan Divarci 0:dc5ded118d7c 1499 * @brief Set power on/off
Sinan Divarci 0:dc5ded118d7c 1500 *
Sinan Divarci 0:dc5ded118d7c 1501 * @param[in] power 0 : power ON, 1: power OFF
Sinan Divarci 0:dc5ded118d7c 1502 *
Sinan Divarci 0:dc5ded118d7c 1503 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1504 */
Sinan Divarci 0:dc5ded118d7c 1505 int set_power_on_off(uint8_t power);
Sinan Divarci 0:dc5ded118d7c 1506
Sinan Divarci 0:dc5ded118d7c 1507 /**
Sinan Divarci 0:dc5ded118d7c 1508 * @brief Operation state of the RF receiver
Sinan Divarci 0:dc5ded118d7c 1509 *
Sinan Divarci 0:dc5ded118d7c 1510 * @details
Sinan Divarci 0:dc5ded118d7c 1511 * - Default : 0x00
Sinan Divarci 0:dc5ded118d7c 1512 * - Description :
Sinan Divarci 0:dc5ded118d7c 1513 */
Sinan Divarci 0:dc5ded118d7c 1514 typedef enum {
Sinan Divarci 0:dc5ded118d7c 1515 INITIALIZED = 0,
Sinan Divarci 0:dc5ded118d7c 1516 UNINITIALIZED = 1,
Sinan Divarci 0:dc5ded118d7c 1517 UNKNOWN = 2,
Sinan Divarci 0:dc5ded118d7c 1518 } operation_mode_t;
Sinan Divarci 0:dc5ded118d7c 1519
Sinan Divarci 0:dc5ded118d7c 1520
Sinan Divarci 0:dc5ded118d7c 1521 // Indicates whether initialization is successful
Sinan Divarci 0:dc5ded118d7c 1522 operation_mode_t operation_mode;
Sinan Divarci 0:dc5ded118d7c 1523
Sinan Divarci 0:dc5ded118d7c 1524 /* PUBLIC FUNCTION DECLARATIONS */
Sinan Divarci 0:dc5ded118d7c 1525
Sinan Divarci 0:dc5ded118d7c 1526 /**
Sinan Divarci 0:dc5ded118d7c 1527 * @brief Read from a register. Since 3-wire spi is not supported by mbed, the read_register function must be implemented by the user.
Sinan Divarci 0:dc5ded118d7c 1528 *
Sinan Divarci 0:dc5ded118d7c 1529 * @param[in] reg Address of a register to be read.
Sinan Divarci 0:dc5ded118d7c 1530 * @param[out] value Pointer to save result value.
Sinan Divarci 0:dc5ded118d7c 1531 * @param[in] len Size of result to be read.
Sinan Divarci 0:dc5ded118d7c 1532 *
Sinan Divarci 0:dc5ded118d7c 1533 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1534 */
Sinan Divarci 0:dc5ded118d7c 1535 virtual int read_register(uint8_t reg, uint8_t *value, uint8_t len);
Sinan Divarci 0:dc5ded118d7c 1536
Sinan Divarci 0:dc5ded118d7c 1537 /**
Sinan Divarci 0:dc5ded118d7c 1538 * @brief Write to a register.
Sinan Divarci 0:dc5ded118d7c 1539 *
Sinan Divarci 0:dc5ded118d7c 1540 * @param[in] reg Address of a register to be written.
Sinan Divarci 0:dc5ded118d7c 1541 * @param[out] value Pointer of value to be written to register.
Sinan Divarci 0:dc5ded118d7c 1542 * @param[in] len Size of result to be written.
Sinan Divarci 0:dc5ded118d7c 1543 *
Sinan Divarci 0:dc5ded118d7c 1544 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1545 */
Sinan Divarci 0:dc5ded118d7c 1546 int write_register(uint8_t reg, const uint8_t *value, uint8_t len);
Sinan Divarci 0:dc5ded118d7c 1547
Sinan Divarci 0:dc5ded118d7c 1548 /**
Sinan Divarci 0:dc5ded118d7c 1549 * @brief Configures the crystal frequency of the chip (Fxtal)
Sinan Divarci 0:dc5ded118d7c 1550 *
Sinan Divarci 0:dc5ded118d7c 1551 * @param[in] freq crystal frequency values between 12.8 MHz and 19.2 MHz
Sinan Divarci 0:dc5ded118d7c 1552 *
Sinan Divarci 0:dc5ded118d7c 1553 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1554 */
Sinan Divarci 0:dc5ded118d7c 1555 int set_crystal_frequency(float freq);
Sinan Divarci 0:dc5ded118d7c 1556
Sinan Divarci 0:dc5ded118d7c 1557 /**
Sinan Divarci 0:dc5ded118d7c 1558 * @brief Get the crystal frequency of the chip (Fxtal)
Sinan Divarci 0:dc5ded118d7c 1559 *
Sinan Divarci 0:dc5ded118d7c 1560 * @returns crystal frequency values between 12.8 MHz and 19.2 MHz
Sinan Divarci 0:dc5ded118d7c 1561 */
Sinan Divarci 0:dc5ded118d7c 1562 float get_crystal_frequency();
Sinan Divarci 0:dc5ded118d7c 1563
Sinan Divarci 0:dc5ded118d7c 1564 /**
Sinan Divarci 0:dc5ded118d7c 1565 * @brief Adjust baud rate
Sinan Divarci 0:dc5ded118d7c 1566 *
Sinan Divarci 0:dc5ded118d7c 1567 * @param[in] baud_rate preferred baud rate
Sinan Divarci 0:dc5ded118d7c 1568 *
Sinan Divarci 0:dc5ded118d7c 1569 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1570 *
Sinan Divarci 0:dc5ded118d7c 1571 * @description It changes only the values of SRC_LG and SRC_SM
Sinan Divarci 0:dc5ded118d7c 1572 * Baud_rate for Manchester = (200/(2^(IF_SEL+CHF_SEL+SRC_LG)))/(4/(8+SRC_SM))
Sinan Divarci 0:dc5ded118d7c 1573 * Baud_rate for NRZ = (200/(2^(IF_SEL+CHF_SEL+SRC_LG)))/(8/(8+SRC_SM))
Sinan Divarci 0:dc5ded118d7c 1574 */
Sinan Divarci 0:dc5ded118d7c 1575 int adjust_baud_rate(float baud_rate);
Sinan Divarci 0:dc5ded118d7c 1576
Sinan Divarci 0:dc5ded118d7c 1577 /**
Sinan Divarci 0:dc5ded118d7c 1578 * @brief Gets baud rate
Sinan Divarci 0:dc5ded118d7c 1579 *
Sinan Divarci 0:dc5ded118d7c 1580 * @returns baud rate.
Sinan Divarci 0:dc5ded118d7c 1581 */
Sinan Divarci 0:dc5ded118d7c 1582 float get_baud_rate();
Sinan Divarci 0:dc5ded118d7c 1583
Sinan Divarci 0:dc5ded118d7c 1584 /**
Sinan Divarci 0:dc5ded118d7c 1585 * @brief Adjust center/carrier frequency of the chip
Sinan Divarci 0:dc5ded118d7c 1586 *
Sinan Divarci 0:dc5ded118d7c 1587 * @param[in] freq center/carrier frequency value between 250 MHz and 950 MHz
Sinan Divarci 0:dc5ded118d7c 1588 *
Sinan Divarci 0:dc5ded118d7c 1589 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1590 */
Sinan Divarci 0:dc5ded118d7c 1591 int set_center_frequency(float freq);
Sinan Divarci 0:dc5ded118d7c 1592
Sinan Divarci 0:dc5ded118d7c 1593 /**
Sinan Divarci 0:dc5ded118d7c 1594 * @brief Gets center/carrier frequency of the chip
Sinan Divarci 0:dc5ded118d7c 1595 *
Sinan Divarci 0:dc5ded118d7c 1596 * @returns center/carrier frequency value between 250 MHz and 950 MHz
Sinan Divarci 0:dc5ded118d7c 1597 */
Sinan Divarci 0:dc5ded118d7c 1598 float get_center_frequency();
Sinan Divarci 0:dc5ded118d7c 1599
Sinan Divarci 0:dc5ded118d7c 1600 /**
Sinan Divarci 0:dc5ded118d7c 1601 * @brief Initial programming steps after power on or soft reset.
Sinan Divarci 0:dc5ded118d7c 1602 *
Sinan Divarci 0:dc5ded118d7c 1603 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1604 */
Sinan Divarci 0:dc5ded118d7c 1605 int initial_programming(void);
Sinan Divarci 0:dc5ded118d7c 1606
Sinan Divarci 0:dc5ded118d7c 1607 /**
Sinan Divarci 0:dc5ded118d7c 1608 * @brief Configures the crystal divider to maintain the internal 3.2MHz time base.
Sinan Divarci 0:dc5ded118d7c 1609 *
Sinan Divarci 0:dc5ded118d7c 1610 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1611 *
Sinan Divarci 0:dc5ded118d7c 1612 * @description The available crystal frequencies are 12.8MHz, 16.0MHz (default), and 19.2MHz.
Sinan Divarci 0:dc5ded118d7c 1613 * Crystal Freq(MHz) / Divider Ratio / XOCLKDIV
Sinan Divarci 0:dc5ded118d7c 1614 * 12.8 / 4 / 0
Sinan Divarci 0:dc5ded118d7c 1615 * 16.0 / 5 / 1
Sinan Divarci 0:dc5ded118d7c 1616 * 19.2 / 6 / 2
Sinan Divarci 0:dc5ded118d7c 1617 */
Sinan Divarci 0:dc5ded118d7c 1618 int adjust_crystal_divider(void);
Sinan Divarci 0:dc5ded118d7c 1619
Sinan Divarci 0:dc5ded118d7c 1620 /**
Sinan Divarci 0:dc5ded118d7c 1621 * @brief Read data for selected Preset/I2C/SPI mode
Sinan Divarci 0:dc5ded118d7c 1622 *
Sinan Divarci 0:dc5ded118d7c 1623 * @param[in] data data pointer for data to be read
Sinan Divarci 0:dc5ded118d7c 1624 * @param[in] length legth of data to be read
Sinan Divarci 0:dc5ded118d7c 1625 *
Sinan Divarci 0:dc5ded118d7c 1626 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1627 */
Sinan Divarci 0:dc5ded118d7c 1628 int read_data(uint8_t *data, uint32_t length);
Sinan Divarci 0:dc5ded118d7c 1629
Sinan Divarci 0:dc5ded118d7c 1630 /**
Sinan Divarci 0:dc5ded118d7c 1631 * @brief Updates Parameter #1 for ASK Threshold Generation(ath_lb) according to parameters
Sinan Divarci 0:dc5ded118d7c 1632 * Intermediate Frequency, Channel Filter, Sample Rate Converter and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1633 *
Sinan Divarci 0:dc5ded118d7c 1634 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1635 */
Sinan Divarci 0:dc5ded118d7c 1636 int update_ath_lb(void);
Sinan Divarci 0:dc5ded118d7c 1637
Sinan Divarci 0:dc5ded118d7c 1638 /**
Sinan Divarci 0:dc5ded118d7c 1639 * @brief Updates Parameter #2 for ASK Threshold Generation(ath_tc) according to parameters
Sinan Divarci 0:dc5ded118d7c 1640 * "Large" adjustment for the Sample Rate Converter(src_lg) and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1641 *
Sinan Divarci 0:dc5ded118d7c 1642 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1643 */
Sinan Divarci 0:dc5ded118d7c 1644 int update_ath_tc(void);
Sinan Divarci 0:dc5ded118d7c 1645
Sinan Divarci 0:dc5ded118d7c 1646 /**
Sinan Divarci 0:dc5ded118d7c 1647 * @brief Updates Parameter #3 for ASK Threshold Generation(ath_gc) according to parameters
Sinan Divarci 0:dc5ded118d7c 1648 * Intermediate Frequency, Channel Filter and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1649 *
Sinan Divarci 0:dc5ded118d7c 1650 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1651 */
Sinan Divarci 0:dc5ded118d7c 1652 int update_ath_gc(void);
Sinan Divarci 0:dc5ded118d7c 1653
Sinan Divarci 0:dc5ded118d7c 1654 /**
Sinan Divarci 0:dc5ded118d7c 1655 * @brief Updates Parameter #4 for ASK Threshold Generation(ath_dt) according to parameters
Sinan Divarci 0:dc5ded118d7c 1656 * Baud Rate Ratio, Encoding and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1657 *
Sinan Divarci 0:dc5ded118d7c 1658 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1659 */
Sinan Divarci 0:dc5ded118d7c 1660 int update_ath_dt(void);
Sinan Divarci 0:dc5ded118d7c 1661
Sinan Divarci 0:dc5ded118d7c 1662 /**
Sinan Divarci 0:dc5ded118d7c 1663 * @brief Updates Parameter #5 for ASK Threshold Generation(ath_bw) according to parameters
Sinan Divarci 0:dc5ded118d7c 1664 * Baud Rate Ratio, Encoding and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1665 *
Sinan Divarci 0:dc5ded118d7c 1666 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1667 */
Sinan Divarci 0:dc5ded118d7c 1668 int update_ath_bw(void);
Sinan Divarci 0:dc5ded118d7c 1669
Sinan Divarci 0:dc5ded118d7c 1670 /**
Sinan Divarci 0:dc5ded118d7c 1671 * @brief Updates AFC Frequency Offset Limit(afc_mo)
Sinan Divarci 0:dc5ded118d7c 1672 *
Sinan Divarci 0:dc5ded118d7c 1673 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1674 */
Sinan Divarci 0:dc5ded118d7c 1675 int update_afc_mo(void);
Sinan Divarci 0:dc5ded118d7c 1676
Sinan Divarci 0:dc5ded118d7c 1677 /**
Sinan Divarci 0:dc5ded118d7c 1678 * @brief Updates AFC Loop Gain Control(afc_lg) according to ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1679 *
Sinan Divarci 0:dc5ded118d7c 1680 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1681 */
Sinan Divarci 0:dc5ded118d7c 1682 int update_afc_lg(void);
Sinan Divarci 0:dc5ded118d7c 1683
Sinan Divarci 0:dc5ded118d7c 1684 /**
Sinan Divarci 0:dc5ded118d7c 1685 * @brief Updates Demodulator Parameter #1(demod_tctrl) according to parameters
Sinan Divarci 0:dc5ded118d7c 1686 * "Large" adjustment for the Sample Rate Converter(src_lg), Channel Filter(chf_sel),
Sinan Divarci 0:dc5ded118d7c 1687 * ASK Threshold Adjustment Method(ath_type) and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1688 *
Sinan Divarci 0:dc5ded118d7c 1689 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1690 */
Sinan Divarci 0:dc5ded118d7c 1691 int update_demod_tctrl(void);
Sinan Divarci 0:dc5ded118d7c 1692
Sinan Divarci 0:dc5ded118d7c 1693 /**
Sinan Divarci 0:dc5ded118d7c 1694 * @brief Updates AGC-Release Threshold Fine Tune(agc_threl) according to Data Rate,
Sinan Divarci 0:dc5ded118d7c 1695 * Encoding and ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1696 *
Sinan Divarci 0:dc5ded118d7c 1697 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1698 */
Sinan Divarci 0:dc5ded118d7c 1699 int update_agc_threl(void);
Sinan Divarci 0:dc5ded118d7c 1700
Sinan Divarci 0:dc5ded118d7c 1701 /**
Sinan Divarci 0:dc5ded118d7c 1702 * @brief Updates ASK Threshold Adjustment Method(ath_type) according to Encoding and
Sinan Divarci 0:dc5ded118d7c 1703 * ASK/FSK Selection.
Sinan Divarci 0:dc5ded118d7c 1704 *
Sinan Divarci 0:dc5ded118d7c 1705 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1706 */
Sinan Divarci 0:dc5ded118d7c 1707 int update_ath_type(void);
Sinan Divarci 0:dc5ded118d7c 1708
Sinan Divarci 0:dc5ded118d7c 1709 /**
Sinan Divarci 0:dc5ded118d7c 1710 * @brief Adjust demodulation type
Sinan Divarci 0:dc5ded118d7c 1711 *
Sinan Divarci 0:dc5ded118d7c 1712 * @param[in] demodulation_type ASK(0x00) or FSK(0x01)
Sinan Divarci 0:dc5ded118d7c 1713 *
Sinan Divarci 0:dc5ded118d7c 1714 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1715 *
Sinan Divarci 0:dc5ded118d7c 1716 * @description Adjusts the Register settings of the Receiver according to the modulation type.
Sinan Divarci 0:dc5ded118d7c 1717 */
Sinan Divarci 0:dc5ded118d7c 1718 int adjust_demodulation(ask_fsk_sel_t demodulation_type);
Sinan Divarci 0:dc5ded118d7c 1719
Sinan Divarci 0:dc5ded118d7c 1720 /**
Sinan Divarci 0:dc5ded118d7c 1721 * @brief Adjust encoding type
Sinan Divarci 0:dc5ded118d7c 1722 *
Sinan Divarci 0:dc5ded118d7c 1723 * @param[in] encoding_type Manchester(0x00) or NRZ(0x01)
Sinan Divarci 0:dc5ded118d7c 1724 *
Sinan Divarci 0:dc5ded118d7c 1725 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1726 *
Sinan Divarci 0:dc5ded118d7c 1727 * @description Adjusts the register settings of the Receiver according to the encoding type.
Sinan Divarci 0:dc5ded118d7c 1728 */
Sinan Divarci 0:dc5ded118d7c 1729 int adjust_encoding_type(encoding_t encoding_type);
Sinan Divarci 0:dc5ded118d7c 1730
Sinan Divarci 0:dc5ded118d7c 1731 /**
Sinan Divarci 0:dc5ded118d7c 1732 * @brief Gets encoding type
Sinan Divarci 0:dc5ded118d7c 1733 *
Sinan Divarci 0:dc5ded118d7c 1734 * @returns encoding type
Sinan Divarci 0:dc5ded118d7c 1735 *
Sinan Divarci 0:dc5ded118d7c 1736 * @description
Sinan Divarci 0:dc5ded118d7c 1737 */
Sinan Divarci 0:dc5ded118d7c 1738 int get_encoding_type();
Sinan Divarci 0:dc5ded118d7c 1739
Sinan Divarci 0:dc5ded118d7c 1740 /**
Sinan Divarci 0:dc5ded118d7c 1741 * @brief Adjust receiver bandwidth(chf_sel). Used only in ASK mode.
Sinan Divarci 0:dc5ded118d7c 1742 *
Sinan Divarci 0:dc5ded118d7c 1743 * @param[in] receiver_bw Receiver bandwidth(kHz)
Sinan Divarci 0:dc5ded118d7c 1744 *
Sinan Divarci 0:dc5ded118d7c 1745 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1746 *
Sinan Divarci 0:dc5ded118d7c 1747 * @description Adjusts the register settings of the receiver according to the desired bandwidth.
Sinan Divarci 0:dc5ded118d7c 1748 */
Sinan Divarci 0:dc5ded118d7c 1749 int adjust_receiver_bandwidth(int receiver_bw);
Sinan Divarci 0:dc5ded118d7c 1750
Sinan Divarci 0:dc5ded118d7c 1751 /**
Sinan Divarci 0:dc5ded118d7c 1752 * @brief Adjust intermediate frequency selection(if_sel). Used only in ASK mode.
Sinan Divarci 0:dc5ded118d7c 1753 *
Sinan Divarci 0:dc5ded118d7c 1754 * @param[in] if_sel intermediate frequency. 400kHz(0x00) or 200kHz(0x01).
Sinan Divarci 0:dc5ded118d7c 1755 *
Sinan Divarci 0:dc5ded118d7c 1756 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1757 *
Sinan Divarci 0:dc5ded118d7c 1758 * @description Adjusts the register settings of the receiver according to the desired intermediate frequency.
Sinan Divarci 0:dc5ded118d7c 1759 */
Sinan Divarci 0:dc5ded118d7c 1760 int adjust_if_sel(if_sel_t if_sel);
Sinan Divarci 0:dc5ded118d7c 1761
Sinan Divarci 0:dc5ded118d7c 1762 /**
Sinan Divarci 0:dc5ded118d7c 1763 * @brief Adjust receiver bandwidth(chf_sel). Used only in FSK mode.
Sinan Divarci 0:dc5ded118d7c 1764 *
Sinan Divarci 0:dc5ded118d7c 1765 * @param[in] receiver_bw Receiver bandwidth(kHz).
Sinan Divarci 0:dc5ded118d7c 1766 * @param[in] deviation FSK deviation(kHz).
Sinan Divarci 0:dc5ded118d7c 1767 *
Sinan Divarci 0:dc5ded118d7c 1768 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1769 *
Sinan Divarci 0:dc5ded118d7c 1770 * @description Adjusts the register settings of the receiver according to the desired bandwidth and FSK deviation.
Sinan Divarci 0:dc5ded118d7c 1771 */
Sinan Divarci 0:dc5ded118d7c 1772 int adjust_receiver_bandwidth(int receiver_bw, float deviation);
Sinan Divarci 0:dc5ded118d7c 1773
Sinan Divarci 0:dc5ded118d7c 1774 /**
Sinan Divarci 0:dc5ded118d7c 1775 * @brief Adjust intermediate frequency selection(if_sel). Used only in FSK mode.
Sinan Divarci 0:dc5ded118d7c 1776 *
Sinan Divarci 0:dc5ded118d7c 1777 * @param[in] if_sel intermediate frequency. 400kHz(0x00) or 200kHz(0x01).
Sinan Divarci 0:dc5ded118d7c 1778 * @param[in] deviation FSK deviation(kHz).
Sinan Divarci 0:dc5ded118d7c 1779 *
Sinan Divarci 0:dc5ded118d7c 1780 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1781 *
Sinan Divarci 0:dc5ded118d7c 1782 * @description Adjusts the register settings of the receiver according to the desired intermediate frequency and FSK deviation.
Sinan Divarci 0:dc5ded118d7c 1783 */
Sinan Divarci 0:dc5ded118d7c 1784 int adjust_if_sel(if_sel_t if_sel, float deviation);
Sinan Divarci 0:dc5ded118d7c 1785
Sinan Divarci 0:dc5ded118d7c 1786 /**
Sinan Divarci 0:dc5ded118d7c 1787 * @brief Adjust Demodulator Parameter #2 according to desired FSK deviation.
Sinan Divarci 0:dc5ded118d7c 1788 *
Sinan Divarci 0:dc5ded118d7c 1789 * @param[in] deviation FSK deviation(kHz).
Sinan Divarci 0:dc5ded118d7c 1790 *
Sinan Divarci 0:dc5ded118d7c 1791 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1792 *
Sinan Divarci 0:dc5ded118d7c 1793 * @description Adjusts the register settings of the receiver according to the desired FSK deviation.
Sinan Divarci 0:dc5ded118d7c 1794 * There are a total of 28 options for configuring the FSK demodulator. Please refer to the Demodulator
Sinan Divarci 0:dc5ded118d7c 1795 * Configuration section in the datasheet
Sinan Divarci 0:dc5ded118d7c 1796 */
Sinan Divarci 0:dc5ded118d7c 1797 int adjust_fsk_deviation(float deviation);
Sinan Divarci 0:dc5ded118d7c 1798
Sinan Divarci 0:dc5ded118d7c 1799 /**
Sinan Divarci 0:dc5ded118d7c 1800 * @brief Adjust Receiver's preamble detector
Sinan Divarci 0:dc5ded118d7c 1801 *
Sinan Divarci 0:dc5ded118d7c 1802 * @param[in] preamble Preamble bit pattern.
Sinan Divarci 0:dc5ded118d7c 1803 * @param[in] preamb_len pattern length.
Sinan Divarci 0:dc5ded118d7c 1804 *
Sinan Divarci 0:dc5ded118d7c 1805 * @returns 0 on success, negative error code on failure.
Sinan Divarci 0:dc5ded118d7c 1806 *
Sinan Divarci 0:dc5ded118d7c 1807 * @description Adjusts the receiver's preamble detector to be used with the self-polling operation. The preamble must be Manchester encoded.
Sinan Divarci 0:dc5ded118d7c 1808 */
Sinan Divarci 0:dc5ded118d7c 1809 int adjust_preamble(int preamble, uint8_t preamb_len);
Sinan Divarci 0:dc5ded118d7c 1810 };
Sinan Divarci 0:dc5ded118d7c 1811
Sinan Divarci 0:dc5ded118d7c 1812 /** MAX41470 Device Class
Sinan Divarci 0:dc5ded118d7c 1813 *
Sinan Divarci 0:dc5ded118d7c 1814 * Hold configurations for the MAX41470
Sinan Divarci 0:dc5ded118d7c 1815 */
Sinan Divarci 0:dc5ded118d7c 1816 class MAX41470 : public MAX4147X <max41470_reg_map_t>
Sinan Divarci 0:dc5ded118d7c 1817 {
Sinan Divarci 0:dc5ded118d7c 1818 max41470_reg_map_t regmap;
Sinan Divarci 0:dc5ded118d7c 1819 public:
Sinan Divarci 0:dc5ded118d7c 1820 MAX41470(SPI *spi, DigitalOut *cs, DigitalOut *powerPin, DigitalIn *dataPin) : MAX4147X<max41470_reg_map_t>(&regmap, spi, cs, powerPin, dataPin) {}
Sinan Divarci 0:dc5ded118d7c 1821
Sinan Divarci 0:dc5ded118d7c 1822 MAX41470(SPI *spi, DigitalOut *powerPin, DigitalIn *dataPin) : MAX4147X<max41470_reg_map_t>(&regmap, spi, powerPin, dataPin) {}
Sinan Divarci 0:dc5ded118d7c 1823 };
Sinan Divarci 0:dc5ded118d7c 1824
Sinan Divarci 0:dc5ded118d7c 1825 /** MAX41473 Device Class
Sinan Divarci 0:dc5ded118d7c 1826 *
Sinan Divarci 0:dc5ded118d7c 1827 * Hold configurations for the MAX41473
Sinan Divarci 0:dc5ded118d7c 1828 */
Sinan Divarci 0:dc5ded118d7c 1829 class MAX41473 : public MAX4147X <max41473_4_reg_map_t>
Sinan Divarci 0:dc5ded118d7c 1830 {
Sinan Divarci 0:dc5ded118d7c 1831 max41473_4_reg_map_t regmap;
Sinan Divarci 0:dc5ded118d7c 1832 public:
Sinan Divarci 0:dc5ded118d7c 1833 MAX41473(I2C *i2c, DigitalOut *powerPin, DigitalIn *dataPin) : MAX4147X<max41473_4_reg_map_t>(&regmap, i2c, powerPin, dataPin) {}
Sinan Divarci 0:dc5ded118d7c 1834 };
Sinan Divarci 0:dc5ded118d7c 1835
Sinan Divarci 0:dc5ded118d7c 1836 /** MAX41474 Device Class
Sinan Divarci 0:dc5ded118d7c 1837 *
Sinan Divarci 0:dc5ded118d7c 1838 * Hold configurations for the MAX41474
Sinan Divarci 0:dc5ded118d7c 1839 */
Sinan Divarci 0:dc5ded118d7c 1840 class MAX41474 : public MAX41473
Sinan Divarci 0:dc5ded118d7c 1841 {
Sinan Divarci 0:dc5ded118d7c 1842 public:
Sinan Divarci 0:dc5ded118d7c 1843 MAX41474(I2C *i2c, DigitalOut *powerPin, DigitalIn *dataPin) : MAX41473(i2c, powerPin, dataPin) {}
Sinan Divarci 0:dc5ded118d7c 1844 };
Sinan Divarci 0:dc5ded118d7c 1845
Sinan Divarci 0:dc5ded118d7c 1846 #endif /* MAX4147X_MAX4147X_H_ */