Maxim Integrated / MAX4147X

MAX4147X RF Receiver Mbed Driver

Fork of MAX4147X by Sinan Divarci

Max4147x.cpp@0:dc5ded118d7c, 2021-08-02 (annotated)

Committer:
Sinan Divarci
Date:
Mon Aug 02 16:34:28 2021 +0300
Revision:
0:dc5ded118d7c
initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sinan Divarci 0:dc5ded118d7c 1 /*******************************************************************************
Sinan Divarci 0:dc5ded118d7c 2 * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
Sinan Divarci 0:dc5ded118d7c 3 *
Sinan Divarci 0:dc5ded118d7c 4 * Permission is hereby granted, free of charge, to any person obtaining a
Sinan Divarci 0:dc5ded118d7c 5 * copy of this software and associated documentation files(the "Software"),
Sinan Divarci 0:dc5ded118d7c 6 * to deal in the Software without restriction, including without limitation
Sinan Divarci 0:dc5ded118d7c 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Sinan Divarci 0:dc5ded118d7c 8 * and/or sell copies of the Software, and to permit persons to whom the
Sinan Divarci 0:dc5ded118d7c 9 * Software is furnished to do so, subject to the following conditions:
Sinan Divarci 0:dc5ded118d7c 10 *
Sinan Divarci 0:dc5ded118d7c 11 * The above copyright notice and this permission notice shall be included
Sinan Divarci 0:dc5ded118d7c 12 * in all copies or substantial portions of the Software.
Sinan Divarci 0:dc5ded118d7c 13 *
Sinan Divarci 0:dc5ded118d7c 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Sinan Divarci 0:dc5ded118d7c 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Sinan Divarci 0:dc5ded118d7c 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Sinan Divarci 0:dc5ded118d7c 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Sinan Divarci 0:dc5ded118d7c 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Sinan Divarci 0:dc5ded118d7c 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Sinan Divarci 0:dc5ded118d7c 20 * OTHER DEALINGS IN THE SOFTWARE.
Sinan Divarci 0:dc5ded118d7c 21 *
Sinan Divarci 0:dc5ded118d7c 22 * Except as contained in this notice, the name of Maxim Integrated
Sinan Divarci 0:dc5ded118d7c 23 * Products, Inc.shall not be used except as stated in the Maxim Integrated
Sinan Divarci 0:dc5ded118d7c 24 * Products, Inc.Branding Policy.
Sinan Divarci 0:dc5ded118d7c 25 *
Sinan Divarci 0:dc5ded118d7c 26 * The mere transfer of this software does not imply any licenses
Sinan Divarci 0:dc5ded118d7c 27 * of trade secrets, proprietary technology, copyrights, patents,
Sinan Divarci 0:dc5ded118d7c 28 * trademarks, maskwork rights, or any other form of intellectual
Sinan Divarci 0:dc5ded118d7c 29 * property whatsoever. Maxim Integrated Products, Inc.retains all
Sinan Divarci 0:dc5ded118d7c 30 * ownership rights.
Sinan Divarci 0:dc5ded118d7c 31 *******************************************************************************
Sinan Divarci 0:dc5ded118d7c 32 */
Sinan Divarci 0:dc5ded118d7c 33
Sinan Divarci 0:dc5ded118d7c 34 #include "Max4147x.h"
Sinan Divarci 0:dc5ded118d7c 35 #include <iostream>
Sinan Divarci 0:dc5ded118d7c 36
Sinan Divarci 0:dc5ded118d7c 37 using namespace std;
Sinan Divarci 0:dc5ded118d7c 38
Sinan Divarci 0:dc5ded118d7c 39 const uint8_t default_register_value_0[Q_CONF_LEN] = {0x46,0x26,0x08,0x24,0xA7,0x09,0x0A,0x1F,0x00,0x13,0xAC,0xCD,0x0F,0x00,0x00};
Sinan Divarci 0:dc5ded118d7c 40 const uint8_t default_register_value_1[Q_CONF_LEN] = {0x44,0x26,0x18,0x24,0x00,0x00,0x00,0x1E,0x00,0x13,0xAC,0xCD,0x0F,0x00,0x00};
Sinan Divarci 0:dc5ded118d7c 41
Sinan Divarci 0:dc5ded118d7c 42 float bit_rate_min_max[10][2] = {{0.25, 103}, {0.125, 51.5}, {0.0625, 25.75}, {0.03125, 12.875}, {0.015625, 6.4375},
Sinan Divarci 0:dc5ded118d7c 43 {0.125, 51.5}, {0.0625, 25.75}, {0.3125, 12.875}, {0.015625, 6.4375}, {0.0078125, 3.21875}};
Sinan Divarci 0:dc5ded118d7c 44
Sinan Divarci 0:dc5ded118d7c 45 const int mu1_conf[10] = {-81, -93, -102, -110, -118, -90, -102, -110, -118, -125};
Sinan Divarci 0:dc5ded118d7c 46 const char ath_tc_conf[8] = {0x14, 0x12, 0x10, 0x0D, 0x09, 0x07, 0x05, 0x04};
Sinan Divarci 0:dc5ded118d7c 47 const char ath_gc_conf[10] = {0x0B, 0x09, 0x08, 0x07, 0x06, 0x0A, 0x07, 0x06, 0x05, 0x04};
Sinan Divarci 0:dc5ded118d7c 48
Sinan Divarci 0:dc5ded118d7c 49 const char nominal_fsk_conf[14] = {80, 57, 44, 40, 29, 22, 20, 14, 11, 10, 7, 5, 3, 2};
Sinan Divarci 0:dc5ded118d7c 50 const char chf_sel_demod_fsk_conf[14][2] = {{0, 0}, {0, 1}, {0, 2}, {1, 3}, {1, 4}, {1, 5}, {2, 3},
Sinan Divarci 0:dc5ded118d7c 51 {2, 4}, {2, 5}, {3, 4}, {3, 5}, {4, 4}, {4, 5}, {4, 6}};
Sinan Divarci 0:dc5ded118d7c 52
Sinan Divarci 0:dc5ded118d7c 53 template <class REG>
Sinan Divarci 0:dc5ded118d7c 54 MAX4147X<REG>::MAX4147X(REG *reg, SPI *spi, DigitalOut *cs, DigitalOut *powerPin, DigitalIn *dataPin)
Sinan Divarci 0:dc5ded118d7c 55 {
Sinan Divarci 0:dc5ded118d7c 56 operation_mode = UNINITIALIZED;
Sinan Divarci 0:dc5ded118d7c 57
Sinan Divarci 0:dc5ded118d7c 58 if (reg == NULL || spi == NULL || cs == NULL || powerPin == NULL || dataPin == NULL)
Sinan Divarci 0:dc5ded118d7c 59 return;
Sinan Divarci 0:dc5ded118d7c 60
Sinan Divarci 0:dc5ded118d7c 61 reg_map = reg;
Sinan Divarci 0:dc5ded118d7c 62 spi_handler = spi;
Sinan Divarci 0:dc5ded118d7c 63 ssel = cs;
Sinan Divarci 0:dc5ded118d7c 64 power_pin = powerPin;
Sinan Divarci 0:dc5ded118d7c 65 data_read = dataPin;
Sinan Divarci 0:dc5ded118d7c 66 i2c_handler = NULL;
Sinan Divarci 0:dc5ded118d7c 67 preset_mode = 0;
Sinan Divarci 0:dc5ded118d7c 68
Sinan Divarci 0:dc5ded118d7c 69 encoding = Manchester;
Sinan Divarci 0:dc5ded118d7c 70 crystal_frequency = 16.0f;
Sinan Divarci 0:dc5ded118d7c 71 center_frequency = 315.0f;
Sinan Divarci 0:dc5ded118d7c 72 baud_rate = 2.0f;
Sinan Divarci 0:dc5ded118d7c 73 baud_rate_ratio = 1.0f;
Sinan Divarci 0:dc5ded118d7c 74
Sinan Divarci 0:dc5ded118d7c 75 if (initial_programming() < 0)
Sinan Divarci 0:dc5ded118d7c 76 return;
Sinan Divarci 0:dc5ded118d7c 77 operation_mode = INITIALIZED;
Sinan Divarci 0:dc5ded118d7c 78 }
Sinan Divarci 0:dc5ded118d7c 79
Sinan Divarci 0:dc5ded118d7c 80 template <class REG>
Sinan Divarci 0:dc5ded118d7c 81 MAX4147X<REG>::MAX4147X(REG *reg, SPI *spi, DigitalOut *powerPin, DigitalIn *dataPin)
Sinan Divarci 0:dc5ded118d7c 82 {
Sinan Divarci 0:dc5ded118d7c 83 operation_mode = UNINITIALIZED;
Sinan Divarci 0:dc5ded118d7c 84
Sinan Divarci 0:dc5ded118d7c 85 if (reg == NULL || spi == NULL || powerPin == NULL || dataPin == NULL)
Sinan Divarci 0:dc5ded118d7c 86 return;
Sinan Divarci 0:dc5ded118d7c 87
Sinan Divarci 0:dc5ded118d7c 88 reg_map = reg;
Sinan Divarci 0:dc5ded118d7c 89 spi_handler = spi;
Sinan Divarci 0:dc5ded118d7c 90 ssel = NULL;
Sinan Divarci 0:dc5ded118d7c 91 power_pin = powerPin;
Sinan Divarci 0:dc5ded118d7c 92 data_read = dataPin;
Sinan Divarci 0:dc5ded118d7c 93 i2c_handler = NULL;
Sinan Divarci 0:dc5ded118d7c 94 preset_mode = 0;
Sinan Divarci 0:dc5ded118d7c 95
Sinan Divarci 0:dc5ded118d7c 96 encoding = Manchester;
Sinan Divarci 0:dc5ded118d7c 97 crystal_frequency = 16.0f;
Sinan Divarci 0:dc5ded118d7c 98 center_frequency = 315.0f;
Sinan Divarci 0:dc5ded118d7c 99 baud_rate = 2.0f;
Sinan Divarci 0:dc5ded118d7c 100 baud_rate_ratio = 1.0f;
Sinan Divarci 0:dc5ded118d7c 101
Sinan Divarci 0:dc5ded118d7c 102 if (initial_programming() < 0)
Sinan Divarci 0:dc5ded118d7c 103 return;
Sinan Divarci 0:dc5ded118d7c 104
Sinan Divarci 0:dc5ded118d7c 105 operation_mode = INITIALIZED;
Sinan Divarci 0:dc5ded118d7c 106 }
Sinan Divarci 0:dc5ded118d7c 107
Sinan Divarci 0:dc5ded118d7c 108 template <class REG>
Sinan Divarci 0:dc5ded118d7c 109 MAX4147X<REG>::MAX4147X(REG *reg, I2C *i2c, DigitalOut *powerPin, DigitalIn *dataPin)
Sinan Divarci 0:dc5ded118d7c 110 {
Sinan Divarci 0:dc5ded118d7c 111 operation_mode = UNINITIALIZED;
Sinan Divarci 0:dc5ded118d7c 112
Sinan Divarci 0:dc5ded118d7c 113 if (reg == NULL || i2c == NULL || powerPin == NULL || dataPin == NULL)
Sinan Divarci 0:dc5ded118d7c 114 return;
Sinan Divarci 0:dc5ded118d7c 115
Sinan Divarci 0:dc5ded118d7c 116 reg_map = reg;
Sinan Divarci 0:dc5ded118d7c 117 spi_handler = NULL;
Sinan Divarci 0:dc5ded118d7c 118 ssel = NULL;
Sinan Divarci 0:dc5ded118d7c 119 power_pin = powerPin;
Sinan Divarci 0:dc5ded118d7c 120 data_read = dataPin;
Sinan Divarci 0:dc5ded118d7c 121 i2c_handler = i2c;
Sinan Divarci 0:dc5ded118d7c 122 preset_mode = 0;
Sinan Divarci 0:dc5ded118d7c 123
Sinan Divarci 0:dc5ded118d7c 124 encoding = Manchester;
Sinan Divarci 0:dc5ded118d7c 125 crystal_frequency = 16.0f;
Sinan Divarci 0:dc5ded118d7c 126 center_frequency = 315.0f;
Sinan Divarci 0:dc5ded118d7c 127 baud_rate = 2.0f;
Sinan Divarci 0:dc5ded118d7c 128 baud_rate_ratio = 1.0f;
Sinan Divarci 0:dc5ded118d7c 129
Sinan Divarci 0:dc5ded118d7c 130 if (initial_programming() < 0)
Sinan Divarci 0:dc5ded118d7c 131 return;
Sinan Divarci 0:dc5ded118d7c 132
Sinan Divarci 0:dc5ded118d7c 133 operation_mode = INITIALIZED;
Sinan Divarci 0:dc5ded118d7c 134 }
Sinan Divarci 0:dc5ded118d7c 135
Sinan Divarci 0:dc5ded118d7c 136 template <>
Sinan Divarci 0:dc5ded118d7c 137 int MAX4147X<max41470_reg_map_t>::read_register(uint8_t reg, uint8_t *value, uint8_t len)
Sinan Divarci 0:dc5ded118d7c 138 {
Sinan Divarci 0:dc5ded118d7c 139
Sinan Divarci 0:dc5ded118d7c 140 int rtn_val = 0;
Sinan Divarci 0:dc5ded118d7c 141 uint8_t readed_byte_cnt = 0;
Sinan Divarci 0:dc5ded118d7c 142 //Since 3-wire spi is not supported by mbed, the read_register function must be implemented by the user.
Sinan Divarci 0:dc5ded118d7c 143 //Here you can find an implemented read_register function for the max32630fthr.
Sinan Divarci 0:dc5ded118d7c 144 #if defined(TARGET_MAX32630FTHR)
Sinan Divarci 0:dc5ded118d7c 145 if (value == NULL) {
Sinan Divarci 0:dc5ded118d7c 146 return -1;
Sinan Divarci 0:dc5ded118d7c 147 }
Sinan Divarci 0:dc5ded118d7c 148
Sinan Divarci 0:dc5ded118d7c 149 if (this->reg_map == NULL) {
Sinan Divarci 0:dc5ded118d7c 150 return -1;
Sinan Divarci 0:dc5ded118d7c 151 }
Sinan Divarci 0:dc5ded118d7c 152
Sinan Divarci 0:dc5ded118d7c 153 spi_handler->format(8,0);
Sinan Divarci 0:dc5ded118d7c 154 spi_handler->frequency(400000);
Sinan Divarci 0:dc5ded118d7c 155
Sinan Divarci 0:dc5ded118d7c 156 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 157 *ssel = 0;
Sinan Divarci 0:dc5ded118d7c 158 }
Sinan Divarci 0:dc5ded118d7c 159 spi_handler->write((uint8_t)0x80 | reg); // Set R/W bit 1 for reading
Sinan Divarci 0:dc5ded118d7c 160 spi_handler->write(0x00); // dummy write command for waiting data read
Sinan Divarci 0:dc5ded118d7c 161
Sinan Divarci 0:dc5ded118d7c 162 MAX4147X_SPI->mstr_cfg |= MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE;
Sinan Divarci 0:dc5ded118d7c 163
Sinan Divarci 0:dc5ded118d7c 164 // Disable SPI for General Control Configuration
Sinan Divarci 0:dc5ded118d7c 165 MAX4147X_SPI->gen_ctrl = 0;
Sinan Divarci 0:dc5ded118d7c 166 MAX4147X_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (1 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header
Sinan Divarci 0:dc5ded118d7c 167
Sinan Divarci 0:dc5ded118d7c 168 MAX4147X_SPI->simple_headers &= 0x0000FFFF;
Sinan Divarci 0:dc5ded118d7c 169 MAX4147X_SPI->simple_headers |= 0x2016<<16;
Sinan Divarci 0:dc5ded118d7c 170 MAX4147X_SPI->gen_ctrl |=MXC_F_SPIM_GEN_CTRL_START_RX_ONLY;
Sinan Divarci 0:dc5ded118d7c 171
Sinan Divarci 0:dc5ded118d7c 172 // Enable the SPI
Sinan Divarci 0:dc5ded118d7c 173 MAX4147X_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN;
Sinan Divarci 0:dc5ded118d7c 174
Sinan Divarci 0:dc5ded118d7c 175 volatile mxc_spim_fifo_regs_t *fifo;
Sinan Divarci 0:dc5ded118d7c 176
Sinan Divarci 0:dc5ded118d7c 177 fifo = MXC_SPIM_GET_SPIM_FIFO(MXC_SPIM_GET_IDX(MAX4147X_SPI));
Sinan Divarci 0:dc5ded118d7c 178
Sinan Divarci 0:dc5ded118d7c 179 int avail = ((MAX4147X_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
Sinan Divarci 0:dc5ded118d7c 180
Sinan Divarci 0:dc5ded118d7c 181 Timer *t = NULL;
Sinan Divarci 0:dc5ded118d7c 182 t = new Timer();
Sinan Divarci 0:dc5ded118d7c 183
Sinan Divarci 0:dc5ded118d7c 184 while(readed_byte_cnt < len)
Sinan Divarci 0:dc5ded118d7c 185 {
Sinan Divarci 0:dc5ded118d7c 186 t->start();
Sinan Divarci 0:dc5ded118d7c 187
Sinan Divarci 0:dc5ded118d7c 188 while (avail < 1) {
Sinan Divarci 0:dc5ded118d7c 189 if (t->read_ms() > 1000) {
Sinan Divarci 0:dc5ded118d7c 190 rtn_val = -1;
Sinan Divarci 0:dc5ded118d7c 191 break;
Sinan Divarci 0:dc5ded118d7c 192 } else {
Sinan Divarci 0:dc5ded118d7c 193 avail = ((MAX4147X_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
Sinan Divarci 0:dc5ded118d7c 194 }
Sinan Divarci 0:dc5ded118d7c 195 }
Sinan Divarci 0:dc5ded118d7c 196
Sinan Divarci 0:dc5ded118d7c 197 t->stop();
Sinan Divarci 0:dc5ded118d7c 198
Sinan Divarci 0:dc5ded118d7c 199 for (int i = 0; i < avail; i++) {
Sinan Divarci 0:dc5ded118d7c 200 *(value++) = fifo->rslts_8[i];
Sinan Divarci 0:dc5ded118d7c 201 readed_byte_cnt++;
Sinan Divarci 0:dc5ded118d7c 202 }
Sinan Divarci 0:dc5ded118d7c 203
Sinan Divarci 0:dc5ded118d7c 204 while (MAX4147X_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) {
Sinan Divarci 0:dc5ded118d7c 205 fifo->rslts_8[0];
Sinan Divarci 0:dc5ded118d7c 206 }
Sinan Divarci 0:dc5ded118d7c 207 }
Sinan Divarci 0:dc5ded118d7c 208
Sinan Divarci 0:dc5ded118d7c 209 MAX4147X_SPI->gen_ctrl = 0;
Sinan Divarci 0:dc5ded118d7c 210 MAX4147X_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (0 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header
Sinan Divarci 0:dc5ded118d7c 211
Sinan Divarci 0:dc5ded118d7c 212 MAX4147X_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN;
Sinan Divarci 0:dc5ded118d7c 213
Sinan Divarci 0:dc5ded118d7c 214 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 215 *ssel = 1;
Sinan Divarci 0:dc5ded118d7c 216 }
Sinan Divarci 0:dc5ded118d7c 217
Sinan Divarci 0:dc5ded118d7c 218 t->~Timer();
Sinan Divarci 0:dc5ded118d7c 219 delete t;
Sinan Divarci 0:dc5ded118d7c 220 #else
Sinan Divarci 0:dc5ded118d7c 221 if (value == NULL) {
Sinan Divarci 0:dc5ded118d7c 222 return -1;
Sinan Divarci 0:dc5ded118d7c 223 }
Sinan Divarci 0:dc5ded118d7c 224
Sinan Divarci 0:dc5ded118d7c 225 if (this->reg_map == NULL) {
Sinan Divarci 0:dc5ded118d7c 226 return -2;
Sinan Divarci 0:dc5ded118d7c 227 }
Sinan Divarci 0:dc5ded118d7c 228
Sinan Divarci 0:dc5ded118d7c 229 spi_handler->format(8,0);
Sinan Divarci 0:dc5ded118d7c 230 spi_handler->frequency(400000);
Sinan Divarci 0:dc5ded118d7c 231
Sinan Divarci 0:dc5ded118d7c 232 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 233 *ssel = 0;
Sinan Divarci 0:dc5ded118d7c 234 }
Sinan Divarci 0:dc5ded118d7c 235 spi_handler->write((uint8_t)0x80 | reg);
Sinan Divarci 0:dc5ded118d7c 236
Sinan Divarci 0:dc5ded118d7c 237 spi_handler->write(0x00); // dummy write command for waiting data read
Sinan Divarci 0:dc5ded118d7c 238
Sinan Divarci 0:dc5ded118d7c 239 for (uint8_t i = 0; i < len; i++) {
Sinan Divarci 0:dc5ded118d7c 240 *(value++) = spi_handler->write(0x00); // read back data bytes
Sinan Divarci 0:dc5ded118d7c 241 }
Sinan Divarci 0:dc5ded118d7c 242 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 243 *ssel = 1;
Sinan Divarci 0:dc5ded118d7c 244 }
Sinan Divarci 0:dc5ded118d7c 245 #endif
Sinan Divarci 0:dc5ded118d7c 246 return rtn_val;
Sinan Divarci 0:dc5ded118d7c 247 }
Sinan Divarci 0:dc5ded118d7c 248
Sinan Divarci 0:dc5ded118d7c 249 template <class REG>
Sinan Divarci 0:dc5ded118d7c 250 int MAX4147X<REG>::read_register(uint8_t reg, uint8_t *value, uint8_t len)
Sinan Divarci 0:dc5ded118d7c 251 {
Sinan Divarci 0:dc5ded118d7c 252 int rtn_val;
Sinan Divarci 0:dc5ded118d7c 253
Sinan Divarci 0:dc5ded118d7c 254 if (value == NULL) {
Sinan Divarci 0:dc5ded118d7c 255 return -1;
Sinan Divarci 0:dc5ded118d7c 256 }
Sinan Divarci 0:dc5ded118d7c 257
Sinan Divarci 0:dc5ded118d7c 258 if (this->reg_map == NULL) {
Sinan Divarci 0:dc5ded118d7c 259 return -2;
Sinan Divarci 0:dc5ded118d7c 260 }
Sinan Divarci 0:dc5ded118d7c 261
Sinan Divarci 0:dc5ded118d7c 262 rtn_val = i2c_handler->write(MAX4147X_I2C_ADDRESS, (const char *)&reg, 1, true);
Sinan Divarci 0:dc5ded118d7c 263 if (rtn_val != 0) {
Sinan Divarci 0:dc5ded118d7c 264 return -3;
Sinan Divarci 0:dc5ded118d7c 265 }
Sinan Divarci 0:dc5ded118d7c 266
Sinan Divarci 0:dc5ded118d7c 267 rtn_val = i2c_handler->read(MAX4147X_I2C_ADDRESS, (char *) value, len, false);
Sinan Divarci 0:dc5ded118d7c 268 if (rtn_val < 0) {
Sinan Divarci 0:dc5ded118d7c 269 return -4;
Sinan Divarci 0:dc5ded118d7c 270 }
Sinan Divarci 0:dc5ded118d7c 271
Sinan Divarci 0:dc5ded118d7c 272 return 0;
Sinan Divarci 0:dc5ded118d7c 273 }
Sinan Divarci 0:dc5ded118d7c 274
Sinan Divarci 0:dc5ded118d7c 275 template <>
Sinan Divarci 0:dc5ded118d7c 276 int MAX4147X<max41470_reg_map_t>::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
Sinan Divarci 0:dc5ded118d7c 277 {
Sinan Divarci 0:dc5ded118d7c 278 int rtn_val = -1;
Sinan Divarci 0:dc5ded118d7c 279 uint8_t local_data[1 + len];
Sinan Divarci 0:dc5ded118d7c 280
Sinan Divarci 0:dc5ded118d7c 281 if (value == NULL) {
Sinan Divarci 0:dc5ded118d7c 282 return -1;
Sinan Divarci 0:dc5ded118d7c 283 }
Sinan Divarci 0:dc5ded118d7c 284
Sinan Divarci 0:dc5ded118d7c 285 memcpy(&local_data[0], value, len);
Sinan Divarci 0:dc5ded118d7c 286
Sinan Divarci 0:dc5ded118d7c 287 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 288 *ssel = 0;
Sinan Divarci 0:dc5ded118d7c 289 }
Sinan Divarci 0:dc5ded118d7c 290
Sinan Divarci 0:dc5ded118d7c 291 rtn_val = spi_handler->write(0x7F & reg); // write mode and adress send
Sinan Divarci 0:dc5ded118d7c 292 for (int i = 0; i < len; i++) {
Sinan Divarci 0:dc5ded118d7c 293 rtn_val = spi_handler->write(local_data[i]); // write adress
Sinan Divarci 0:dc5ded118d7c 294 }
Sinan Divarci 0:dc5ded118d7c 295
Sinan Divarci 0:dc5ded118d7c 296 if (ssel != NULL) {
Sinan Divarci 0:dc5ded118d7c 297 *ssel = 1;
Sinan Divarci 0:dc5ded118d7c 298 }
Sinan Divarci 0:dc5ded118d7c 299
Sinan Divarci 0:dc5ded118d7c 300 if (rtn_val != 0) {
Sinan Divarci 0:dc5ded118d7c 301 return rtn_val;
Sinan Divarci 0:dc5ded118d7c 302 }
Sinan Divarci 0:dc5ded118d7c 303
Sinan Divarci 0:dc5ded118d7c 304 return 0;
Sinan Divarci 0:dc5ded118d7c 305 }
Sinan Divarci 0:dc5ded118d7c 306
Sinan Divarci 0:dc5ded118d7c 307 template <class REG>
Sinan Divarci 0:dc5ded118d7c 308 int MAX4147X<REG>::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
Sinan Divarci 0:dc5ded118d7c 309 {
Sinan Divarci 0:dc5ded118d7c 310 int rtn_val;
Sinan Divarci 0:dc5ded118d7c 311 uint8_t local_data[1 + len];
Sinan Divarci 0:dc5ded118d7c 312
Sinan Divarci 0:dc5ded118d7c 313 if (value == NULL) {
Sinan Divarci 0:dc5ded118d7c 314 return -1;
Sinan Divarci 0:dc5ded118d7c 315 }
Sinan Divarci 0:dc5ded118d7c 316
Sinan Divarci 0:dc5ded118d7c 317 local_data[0] = reg;
Sinan Divarci 0:dc5ded118d7c 318
Sinan Divarci 0:dc5ded118d7c 319 memcpy(&local_data[1], value, len);
Sinan Divarci 0:dc5ded118d7c 320
Sinan Divarci 0:dc5ded118d7c 321 rtn_val = i2c_handler->write(MAX4147X_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
Sinan Divarci 0:dc5ded118d7c 322 if (rtn_val != 0) {
Sinan Divarci 0:dc5ded118d7c 323 return -1;
Sinan Divarci 0:dc5ded118d7c 324 }
Sinan Divarci 0:dc5ded118d7c 325
Sinan Divarci 0:dc5ded118d7c 326 return 0;
Sinan Divarci 0:dc5ded118d7c 327 }
Sinan Divarci 0:dc5ded118d7c 328
Sinan Divarci 0:dc5ded118d7c 329 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
Sinan Divarci 0:dc5ded118d7c 330 int ret; \
Sinan Divarci 0:dc5ded118d7c 331 ret = read_register(address, (uint8_t *)&(reg_name), 1); \
Sinan Divarci 0:dc5ded118d7c 332 if (ret) { \
Sinan Divarci 0:dc5ded118d7c 333 return ret; \
Sinan Divarci 0:dc5ded118d7c 334 } \
Sinan Divarci 0:dc5ded118d7c 335 bit_field_name = value; \
Sinan Divarci 0:dc5ded118d7c 336 ret = write_register(address, (uint8_t *)&(reg_name), 1); \
Sinan Divarci 0:dc5ded118d7c 337 if (ret) { \
Sinan Divarci 0:dc5ded118d7c 338 return ret; \
Sinan Divarci 0:dc5ded118d7c 339 }
Sinan Divarci 0:dc5ded118d7c 340
Sinan Divarci 0:dc5ded118d7c 341 template <class REG>
Sinan Divarci 0:dc5ded118d7c 342 int MAX4147X<REG>::set_rssi_dt(rssi_dt_t rssi_dt)
Sinan Divarci 0:dc5ded118d7c 343 {
Sinan Divarci 0:dc5ded118d7c 344 SET_BIT_FIELD(DEMOD_ADDR, this->reg_map->reg_demod, this->reg_map->reg_demod.bits.rssi_dt, rssi_dt);
Sinan Divarci 0:dc5ded118d7c 345
Sinan Divarci 0:dc5ded118d7c 346 return 0;
Sinan Divarci 0:dc5ded118d7c 347 }
Sinan Divarci 0:dc5ded118d7c 348
Sinan Divarci 0:dc5ded118d7c 349 template <class REG>
Sinan Divarci 0:dc5ded118d7c 350 int MAX4147X<REG>::get_rssi_dt(rssi_dt_t* rssi_dt)
Sinan Divarci 0:dc5ded118d7c 351 {
Sinan Divarci 0:dc5ded118d7c 352 int ret;
Sinan Divarci 0:dc5ded118d7c 353
Sinan Divarci 0:dc5ded118d7c 354 ret = read_register(DEMOD_ADDR, (uint8_t *) & (this->reg_map->reg_demod), 1);
Sinan Divarci 0:dc5ded118d7c 355 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 356 return ret;
Sinan Divarci 0:dc5ded118d7c 357 }
Sinan Divarci 0:dc5ded118d7c 358
Sinan Divarci 0:dc5ded118d7c 359 *rssi_dt = (rssi_dt_t)this->reg_map->reg_demod.bits.rssi_dt;
Sinan Divarci 0:dc5ded118d7c 360
Sinan Divarci 0:dc5ded118d7c 361 return 0;
Sinan Divarci 0:dc5ded118d7c 362 }
Sinan Divarci 0:dc5ded118d7c 363
Sinan Divarci 0:dc5ded118d7c 364 template <class REG>
Sinan Divarci 0:dc5ded118d7c 365 int MAX4147X<REG>::set_demod_fsk(demod_fsk_t demod_fsk)
Sinan Divarci 0:dc5ded118d7c 366 {
Sinan Divarci 0:dc5ded118d7c 367 SET_BIT_FIELD(DEMOD_ADDR, this->reg_map->reg_demod, this->reg_map->reg_demod.bits.demod_fsk, demod_fsk);
Sinan Divarci 0:dc5ded118d7c 368
Sinan Divarci 0:dc5ded118d7c 369 return 0;
Sinan Divarci 0:dc5ded118d7c 370 }
Sinan Divarci 0:dc5ded118d7c 371
Sinan Divarci 0:dc5ded118d7c 372 template <class REG>
Sinan Divarci 0:dc5ded118d7c 373 int MAX4147X<REG>::get_demod_fsk(demod_fsk_t* demod_fsk)
Sinan Divarci 0:dc5ded118d7c 374 {
Sinan Divarci 0:dc5ded118d7c 375 int ret;
Sinan Divarci 0:dc5ded118d7c 376
Sinan Divarci 0:dc5ded118d7c 377 ret = read_register(DEMOD_ADDR, (uint8_t *) & (this->reg_map->reg_demod), 1);
Sinan Divarci 0:dc5ded118d7c 378 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 379 return ret;
Sinan Divarci 0:dc5ded118d7c 380 }
Sinan Divarci 0:dc5ded118d7c 381
Sinan Divarci 0:dc5ded118d7c 382 *demod_fsk = (demod_fsk_t)this->reg_map->reg_demod.bits.demod_fsk;
Sinan Divarci 0:dc5ded118d7c 383
Sinan Divarci 0:dc5ded118d7c 384 return 0;
Sinan Divarci 0:dc5ded118d7c 385 }
Sinan Divarci 0:dc5ded118d7c 386
Sinan Divarci 0:dc5ded118d7c 387 template <class REG>
Sinan Divarci 0:dc5ded118d7c 388 int MAX4147X<REG>::set_demod_tctrl(demod_tctrl_t demod_tctrl)
Sinan Divarci 0:dc5ded118d7c 389 {
Sinan Divarci 0:dc5ded118d7c 390 SET_BIT_FIELD(DEMOD_ADDR, this->reg_map->reg_demod, this->reg_map->reg_demod.bits.demod_tctrl, demod_tctrl);
Sinan Divarci 0:dc5ded118d7c 391
Sinan Divarci 0:dc5ded118d7c 392 return 0;
Sinan Divarci 0:dc5ded118d7c 393 }
Sinan Divarci 0:dc5ded118d7c 394
Sinan Divarci 0:dc5ded118d7c 395 template <class REG>
Sinan Divarci 0:dc5ded118d7c 396 int MAX4147X<REG>::get_demod_tctrl(demod_tctrl_t* demod_tctrl)
Sinan Divarci 0:dc5ded118d7c 397 {
Sinan Divarci 0:dc5ded118d7c 398 int ret;
Sinan Divarci 0:dc5ded118d7c 399
Sinan Divarci 0:dc5ded118d7c 400 ret = read_register(DEMOD_ADDR, (uint8_t *) & (this->reg_map->reg_demod), 1);
Sinan Divarci 0:dc5ded118d7c 401 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 402 return ret;
Sinan Divarci 0:dc5ded118d7c 403 }
Sinan Divarci 0:dc5ded118d7c 404
Sinan Divarci 0:dc5ded118d7c 405 *demod_tctrl = (demod_tctrl_t)this->reg_map->reg_demod.bits.demod_tctrl;
Sinan Divarci 0:dc5ded118d7c 406
Sinan Divarci 0:dc5ded118d7c 407 return 0;
Sinan Divarci 0:dc5ded118d7c 408 }
Sinan Divarci 0:dc5ded118d7c 409
Sinan Divarci 0:dc5ded118d7c 410 template <class REG>
Sinan Divarci 0:dc5ded118d7c 411 int MAX4147X<REG>::set_agc_threl(uint8_t agc_threl)
Sinan Divarci 0:dc5ded118d7c 412 {
Sinan Divarci 0:dc5ded118d7c 413 SET_BIT_FIELD(AGC_ADDR, this->reg_map->reg_agc, this->reg_map->reg_agc.bits.agc_threl, agc_threl);
Sinan Divarci 0:dc5ded118d7c 414
Sinan Divarci 0:dc5ded118d7c 415 return 0;
Sinan Divarci 0:dc5ded118d7c 416 }
Sinan Divarci 0:dc5ded118d7c 417
Sinan Divarci 0:dc5ded118d7c 418 template <class REG>
Sinan Divarci 0:dc5ded118d7c 419 int MAX4147X<REG>::get_agc_threl(uint8_t* agc_threl)
Sinan Divarci 0:dc5ded118d7c 420 {
Sinan Divarci 0:dc5ded118d7c 421 int ret;
Sinan Divarci 0:dc5ded118d7c 422
Sinan Divarci 0:dc5ded118d7c 423 ret = read_register(AGC_ADDR, (uint8_t *) & (this->reg_map->reg_agc), 1);
Sinan Divarci 0:dc5ded118d7c 424 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 425 return ret;
Sinan Divarci 0:dc5ded118d7c 426 }
Sinan Divarci 0:dc5ded118d7c 427
Sinan Divarci 0:dc5ded118d7c 428 *agc_threl = (uint8_t)this->reg_map->reg_agc.bits.agc_threl;
Sinan Divarci 0:dc5ded118d7c 429
Sinan Divarci 0:dc5ded118d7c 430 return 0;
Sinan Divarci 0:dc5ded118d7c 431 }
Sinan Divarci 0:dc5ded118d7c 432
Sinan Divarci 0:dc5ded118d7c 433 template <class REG>
Sinan Divarci 0:dc5ded118d7c 434 int MAX4147X<REG>::set_agc_en_bo(agc_en_bo_t agc_op_mode)
Sinan Divarci 0:dc5ded118d7c 435 {
Sinan Divarci 0:dc5ded118d7c 436 SET_BIT_FIELD(AGC_ADDR, this->reg_map->reg_agc, this->reg_map->reg_agc.bits.agc_en_bo, agc_op_mode);
Sinan Divarci 0:dc5ded118d7c 437
Sinan Divarci 0:dc5ded118d7c 438 return 0;
Sinan Divarci 0:dc5ded118d7c 439 }
Sinan Divarci 0:dc5ded118d7c 440
Sinan Divarci 0:dc5ded118d7c 441 template <class REG>
Sinan Divarci 0:dc5ded118d7c 442 int MAX4147X<REG>::get_agc_en_bo(agc_en_bo_t* agc_op_mode)
Sinan Divarci 0:dc5ded118d7c 443 {
Sinan Divarci 0:dc5ded118d7c 444 int ret;
Sinan Divarci 0:dc5ded118d7c 445
Sinan Divarci 0:dc5ded118d7c 446 ret = read_register(AGC_ADDR, (uint8_t *) & (this->reg_map->reg_agc), 1);
Sinan Divarci 0:dc5ded118d7c 447 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 448 return ret;
Sinan Divarci 0:dc5ded118d7c 449 }
Sinan Divarci 0:dc5ded118d7c 450
Sinan Divarci 0:dc5ded118d7c 451 *agc_op_mode = (agc_en_bo_t)this->reg_map->reg_agc.bits.agc_en_bo;
Sinan Divarci 0:dc5ded118d7c 452
Sinan Divarci 0:dc5ded118d7c 453 return 0;
Sinan Divarci 0:dc5ded118d7c 454 }
Sinan Divarci 0:dc5ded118d7c 455
Sinan Divarci 0:dc5ded118d7c 456 template <class REG>
Sinan Divarci 0:dc5ded118d7c 457 int MAX4147X<REG>::set_ask_fsk_sel(ask_fsk_sel_t ask_fsk_sel)
Sinan Divarci 0:dc5ded118d7c 458 {
Sinan Divarci 0:dc5ded118d7c 459 SET_BIT_FIELD(IF_CHF_SEL_ADDR, this->reg_map->reg_if_chf_sel, this->reg_map->reg_if_chf_sel.bits.ask_fsk_sel, ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 460
Sinan Divarci 0:dc5ded118d7c 461 return 0;
Sinan Divarci 0:dc5ded118d7c 462 }
Sinan Divarci 0:dc5ded118d7c 463
Sinan Divarci 0:dc5ded118d7c 464 template <class REG>
Sinan Divarci 0:dc5ded118d7c 465 int MAX4147X<REG>::get_ask_fsk_sel(ask_fsk_sel_t* ask_fsk_sel)
Sinan Divarci 0:dc5ded118d7c 466 {
Sinan Divarci 0:dc5ded118d7c 467 int ret;
Sinan Divarci 0:dc5ded118d7c 468
Sinan Divarci 0:dc5ded118d7c 469 ret = read_register(IF_CHF_SEL_ADDR, (uint8_t *) & (this->reg_map->reg_if_chf_sel), 1);
Sinan Divarci 0:dc5ded118d7c 470 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 471 return ret;
Sinan Divarci 0:dc5ded118d7c 472 }
Sinan Divarci 0:dc5ded118d7c 473
Sinan Divarci 0:dc5ded118d7c 474 *ask_fsk_sel = (ask_fsk_sel_t)this->reg_map->reg_if_chf_sel.bits.ask_fsk_sel;
Sinan Divarci 0:dc5ded118d7c 475
Sinan Divarci 0:dc5ded118d7c 476 return 0;
Sinan Divarci 0:dc5ded118d7c 477 }
Sinan Divarci 0:dc5ded118d7c 478
Sinan Divarci 0:dc5ded118d7c 479 template <class REG>
Sinan Divarci 0:dc5ded118d7c 480 int MAX4147X<REG>::set_if_sel(if_sel_t if_sel)
Sinan Divarci 0:dc5ded118d7c 481 {
Sinan Divarci 0:dc5ded118d7c 482 SET_BIT_FIELD(IF_CHF_SEL_ADDR, this->reg_map->reg_if_chf_sel, this->reg_map->reg_if_chf_sel.bits.if_sel, if_sel);
Sinan Divarci 0:dc5ded118d7c 483
Sinan Divarci 0:dc5ded118d7c 484 return 0;
Sinan Divarci 0:dc5ded118d7c 485 }
Sinan Divarci 0:dc5ded118d7c 486
Sinan Divarci 0:dc5ded118d7c 487 template <class REG>
Sinan Divarci 0:dc5ded118d7c 488 int MAX4147X<REG>::get_if_sel(if_sel_t* if_sel)
Sinan Divarci 0:dc5ded118d7c 489 {
Sinan Divarci 0:dc5ded118d7c 490 int ret;
Sinan Divarci 0:dc5ded118d7c 491
Sinan Divarci 0:dc5ded118d7c 492 ret = read_register(IF_CHF_SEL_ADDR, (uint8_t *) & (this->reg_map->reg_if_chf_sel), 1);
Sinan Divarci 0:dc5ded118d7c 493 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 494 return ret;
Sinan Divarci 0:dc5ded118d7c 495 }
Sinan Divarci 0:dc5ded118d7c 496
Sinan Divarci 0:dc5ded118d7c 497 *if_sel = (if_sel_t)this->reg_map->reg_if_chf_sel.bits.if_sel;
Sinan Divarci 0:dc5ded118d7c 498
Sinan Divarci 0:dc5ded118d7c 499 return 0;
Sinan Divarci 0:dc5ded118d7c 500 }
Sinan Divarci 0:dc5ded118d7c 501
Sinan Divarci 0:dc5ded118d7c 502 template <class REG>
Sinan Divarci 0:dc5ded118d7c 503 int MAX4147X<REG>::set_chf_sel(chf_sel_t chf_sel)
Sinan Divarci 0:dc5ded118d7c 504 {
Sinan Divarci 0:dc5ded118d7c 505 SET_BIT_FIELD(IF_CHF_SEL_ADDR, this->reg_map->reg_if_chf_sel, this->reg_map->reg_if_chf_sel.bits.chf_sel, chf_sel);
Sinan Divarci 0:dc5ded118d7c 506
Sinan Divarci 0:dc5ded118d7c 507 return 0;
Sinan Divarci 0:dc5ded118d7c 508 }
Sinan Divarci 0:dc5ded118d7c 509
Sinan Divarci 0:dc5ded118d7c 510 template <class REG>
Sinan Divarci 0:dc5ded118d7c 511 int MAX4147X<REG>::get_chf_sel(chf_sel_t* chf_sel)
Sinan Divarci 0:dc5ded118d7c 512 {
Sinan Divarci 0:dc5ded118d7c 513 int ret;
Sinan Divarci 0:dc5ded118d7c 514
Sinan Divarci 0:dc5ded118d7c 515 ret = read_register(IF_CHF_SEL_ADDR, (uint8_t *) & (this->reg_map->reg_if_chf_sel), 1);
Sinan Divarci 0:dc5ded118d7c 516 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 517 return ret;
Sinan Divarci 0:dc5ded118d7c 518 }
Sinan Divarci 0:dc5ded118d7c 519
Sinan Divarci 0:dc5ded118d7c 520 *chf_sel = (chf_sel_t)this->reg_map->reg_if_chf_sel.bits.chf_sel;
Sinan Divarci 0:dc5ded118d7c 521
Sinan Divarci 0:dc5ded118d7c 522 return 0;
Sinan Divarci 0:dc5ded118d7c 523 }
Sinan Divarci 0:dc5ded118d7c 524
Sinan Divarci 0:dc5ded118d7c 525 template <class REG>
Sinan Divarci 0:dc5ded118d7c 526 int MAX4147X<REG>::set_ld_buf(ld_buf_t ld_buf)
Sinan Divarci 0:dc5ded118d7c 527 {
Sinan Divarci 0:dc5ded118d7c 528 SET_BIT_FIELD(PDF_CFG_ADDR, this->reg_map->reg_pdf_cfg, this->reg_map->reg_pdf_cfg.bits.ld_buf, ld_buf);
Sinan Divarci 0:dc5ded118d7c 529
Sinan Divarci 0:dc5ded118d7c 530 return 0;
Sinan Divarci 0:dc5ded118d7c 531 }
Sinan Divarci 0:dc5ded118d7c 532
Sinan Divarci 0:dc5ded118d7c 533 template <class REG>
Sinan Divarci 0:dc5ded118d7c 534 int MAX4147X<REG>::get_ld_buf(ld_buf_t* ld_buf)
Sinan Divarci 0:dc5ded118d7c 535 {
Sinan Divarci 0:dc5ded118d7c 536 int ret;
Sinan Divarci 0:dc5ded118d7c 537
Sinan Divarci 0:dc5ded118d7c 538 ret = read_register(PDF_CFG_ADDR, (uint8_t *) & (this->reg_map->reg_pdf_cfg), 1);
Sinan Divarci 0:dc5ded118d7c 539 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 540 return ret;
Sinan Divarci 0:dc5ded118d7c 541 }
Sinan Divarci 0:dc5ded118d7c 542
Sinan Divarci 0:dc5ded118d7c 543 *ld_buf = (ld_buf_t)this->reg_map->reg_pdf_cfg.bits.ld_buf;
Sinan Divarci 0:dc5ded118d7c 544
Sinan Divarci 0:dc5ded118d7c 545 return 0;
Sinan Divarci 0:dc5ded118d7c 546 }
Sinan Divarci 0:dc5ded118d7c 547
Sinan Divarci 0:dc5ded118d7c 548 template <class REG>
Sinan Divarci 0:dc5ded118d7c 549 int MAX4147X<REG>::set_ld_bw(ld_bw_t ld_bw)
Sinan Divarci 0:dc5ded118d7c 550 {
Sinan Divarci 0:dc5ded118d7c 551 SET_BIT_FIELD(PDF_CFG_ADDR, this->reg_map->reg_pdf_cfg, this->reg_map->reg_pdf_cfg.bits.ld_bw, ld_bw);
Sinan Divarci 0:dc5ded118d7c 552
Sinan Divarci 0:dc5ded118d7c 553 return 0;
Sinan Divarci 0:dc5ded118d7c 554 }
Sinan Divarci 0:dc5ded118d7c 555
Sinan Divarci 0:dc5ded118d7c 556 template <class REG>
Sinan Divarci 0:dc5ded118d7c 557 int MAX4147X<REG>::get_ld_bw(ld_bw_t* ld_bw)
Sinan Divarci 0:dc5ded118d7c 558 {
Sinan Divarci 0:dc5ded118d7c 559 int ret;
Sinan Divarci 0:dc5ded118d7c 560
Sinan Divarci 0:dc5ded118d7c 561 ret = read_register(PDF_CFG_ADDR, (uint8_t *) & (this->reg_map->reg_pdf_cfg), 1);
Sinan Divarci 0:dc5ded118d7c 562 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 563 return ret;
Sinan Divarci 0:dc5ded118d7c 564 }
Sinan Divarci 0:dc5ded118d7c 565
Sinan Divarci 0:dc5ded118d7c 566 *ld_bw = (ld_bw_t)this->reg_map->reg_pdf_cfg.bits.ld_bw;
Sinan Divarci 0:dc5ded118d7c 567
Sinan Divarci 0:dc5ded118d7c 568 return 0;
Sinan Divarci 0:dc5ded118d7c 569 }
Sinan Divarci 0:dc5ded118d7c 570
Sinan Divarci 0:dc5ded118d7c 571 template <class REG>
Sinan Divarci 0:dc5ded118d7c 572 int MAX4147X<REG>::set_src_lg(src_lg_t src_lg)
Sinan Divarci 0:dc5ded118d7c 573 {
Sinan Divarci 0:dc5ded118d7c 574 SET_BIT_FIELD(PDF_CFG_ADDR, this->reg_map->reg_pdf_cfg, this->reg_map->reg_pdf_cfg.bits.src_lg, src_lg);
Sinan Divarci 0:dc5ded118d7c 575
Sinan Divarci 0:dc5ded118d7c 576 return 0;
Sinan Divarci 0:dc5ded118d7c 577 }
Sinan Divarci 0:dc5ded118d7c 578
Sinan Divarci 0:dc5ded118d7c 579 template <class REG>
Sinan Divarci 0:dc5ded118d7c 580 int MAX4147X<REG>::get_src_lg(src_lg_t* src_lg)
Sinan Divarci 0:dc5ded118d7c 581 {
Sinan Divarci 0:dc5ded118d7c 582 int ret;
Sinan Divarci 0:dc5ded118d7c 583
Sinan Divarci 0:dc5ded118d7c 584 ret = read_register(PDF_CFG_ADDR, (uint8_t *) & (this->reg_map->reg_pdf_cfg), 1);
Sinan Divarci 0:dc5ded118d7c 585 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 586 return ret;
Sinan Divarci 0:dc5ded118d7c 587 }
Sinan Divarci 0:dc5ded118d7c 588
Sinan Divarci 0:dc5ded118d7c 589 *src_lg = (src_lg_t)this->reg_map->reg_pdf_cfg.bits.src_lg;
Sinan Divarci 0:dc5ded118d7c 590
Sinan Divarci 0:dc5ded118d7c 591 return 0;
Sinan Divarci 0:dc5ded118d7c 592 }
Sinan Divarci 0:dc5ded118d7c 593
Sinan Divarci 0:dc5ded118d7c 594 template <class REG>
Sinan Divarci 0:dc5ded118d7c 595 int MAX4147X<REG>::set_src_sm(src_sm_t src_sm)
Sinan Divarci 0:dc5ded118d7c 596 {
Sinan Divarci 0:dc5ded118d7c 597 SET_BIT_FIELD(PDF_CFG_ADDR, this->reg_map->reg_pdf_cfg, this->reg_map->reg_pdf_cfg.bits.src_sm, src_sm);
Sinan Divarci 0:dc5ded118d7c 598
Sinan Divarci 0:dc5ded118d7c 599 return 0;
Sinan Divarci 0:dc5ded118d7c 600 }
Sinan Divarci 0:dc5ded118d7c 601
Sinan Divarci 0:dc5ded118d7c 602 template <class REG>
Sinan Divarci 0:dc5ded118d7c 603 int MAX4147X<REG>::get_src_sm(src_sm_t* src_sm)
Sinan Divarci 0:dc5ded118d7c 604 {
Sinan Divarci 0:dc5ded118d7c 605 int ret;
Sinan Divarci 0:dc5ded118d7c 606
Sinan Divarci 0:dc5ded118d7c 607 ret = read_register(PDF_CFG_ADDR, (uint8_t *) & (this->reg_map->reg_pdf_cfg), 1);
Sinan Divarci 0:dc5ded118d7c 608 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 609 return ret;
Sinan Divarci 0:dc5ded118d7c 610 }
Sinan Divarci 0:dc5ded118d7c 611
Sinan Divarci 0:dc5ded118d7c 612 *src_sm = (src_sm_t)this->reg_map->reg_pdf_cfg.bits.src_sm;
Sinan Divarci 0:dc5ded118d7c 613
Sinan Divarci 0:dc5ded118d7c 614 return 0;
Sinan Divarci 0:dc5ded118d7c 615 }
Sinan Divarci 0:dc5ded118d7c 616
Sinan Divarci 0:dc5ded118d7c 617 template <class REG>
Sinan Divarci 0:dc5ded118d7c 618 int MAX4147X<REG>::set_ath_lb(uint8_t ath_lb)
Sinan Divarci 0:dc5ded118d7c 619 {
Sinan Divarci 0:dc5ded118d7c 620 SET_BIT_FIELD(ATH_CFG1_ADDR, this->reg_map->reg_ath_cfg1, this->reg_map->reg_ath_cfg1.bits.ath_lb, ath_lb);
Sinan Divarci 0:dc5ded118d7c 621
Sinan Divarci 0:dc5ded118d7c 622 return 0;
Sinan Divarci 0:dc5ded118d7c 623 }
Sinan Divarci 0:dc5ded118d7c 624
Sinan Divarci 0:dc5ded118d7c 625 template <class REG>
Sinan Divarci 0:dc5ded118d7c 626 int MAX4147X<REG>::get_ath_lb(uint8_t* ath_lb)
Sinan Divarci 0:dc5ded118d7c 627 {
Sinan Divarci 0:dc5ded118d7c 628 int ret;
Sinan Divarci 0:dc5ded118d7c 629
Sinan Divarci 0:dc5ded118d7c 630 ret = read_register(ATH_CFG1_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg1), 1);
Sinan Divarci 0:dc5ded118d7c 631 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 632 return ret;
Sinan Divarci 0:dc5ded118d7c 633 }
Sinan Divarci 0:dc5ded118d7c 634
Sinan Divarci 0:dc5ded118d7c 635 *ath_lb = (uint8_t)this->reg_map->reg_ath_cfg1.bits.ath_lb;
Sinan Divarci 0:dc5ded118d7c 636
Sinan Divarci 0:dc5ded118d7c 637 return 0;
Sinan Divarci 0:dc5ded118d7c 638 }
Sinan Divarci 0:dc5ded118d7c 639
Sinan Divarci 0:dc5ded118d7c 640 template <class REG>
Sinan Divarci 0:dc5ded118d7c 641 int MAX4147X<REG>::set_ath_dt(ath_dt_t ath_dt)
Sinan Divarci 0:dc5ded118d7c 642 {
Sinan Divarci 0:dc5ded118d7c 643 SET_BIT_FIELD(ATH_CFG2_ADDR, this->reg_map->reg_ath_cfg2, this->reg_map->reg_ath_cfg2.bits.ath_dt, ath_dt);
Sinan Divarci 0:dc5ded118d7c 644
Sinan Divarci 0:dc5ded118d7c 645 return 0;
Sinan Divarci 0:dc5ded118d7c 646 }
Sinan Divarci 0:dc5ded118d7c 647
Sinan Divarci 0:dc5ded118d7c 648 template <class REG>
Sinan Divarci 0:dc5ded118d7c 649 int MAX4147X<REG>::get_ath_dt(ath_dt_t* ath_dt)
Sinan Divarci 0:dc5ded118d7c 650 {
Sinan Divarci 0:dc5ded118d7c 651 int ret;
Sinan Divarci 0:dc5ded118d7c 652
Sinan Divarci 0:dc5ded118d7c 653 ret = read_register(ATH_CFG2_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg2), 1);
Sinan Divarci 0:dc5ded118d7c 654 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 655 return ret;
Sinan Divarci 0:dc5ded118d7c 656 }
Sinan Divarci 0:dc5ded118d7c 657
Sinan Divarci 0:dc5ded118d7c 658 *ath_dt = (ath_dt_t)this->reg_map->reg_ath_cfg2.bits.ath_dt;
Sinan Divarci 0:dc5ded118d7c 659
Sinan Divarci 0:dc5ded118d7c 660 return 0;
Sinan Divarci 0:dc5ded118d7c 661 }
Sinan Divarci 0:dc5ded118d7c 662
Sinan Divarci 0:dc5ded118d7c 663 template <class REG>
Sinan Divarci 0:dc5ded118d7c 664 int MAX4147X<REG>::set_ath_tc(uint8_t ath_tc)
Sinan Divarci 0:dc5ded118d7c 665 {
Sinan Divarci 0:dc5ded118d7c 666 SET_BIT_FIELD(ATH_CFG2_ADDR, this->reg_map->reg_ath_cfg2, this->reg_map->reg_ath_cfg2.bits.ath_tc, ath_tc);
Sinan Divarci 0:dc5ded118d7c 667
Sinan Divarci 0:dc5ded118d7c 668 return 0;
Sinan Divarci 0:dc5ded118d7c 669 }
Sinan Divarci 0:dc5ded118d7c 670
Sinan Divarci 0:dc5ded118d7c 671 template <class REG>
Sinan Divarci 0:dc5ded118d7c 672 int MAX4147X<REG>::get_ath_tc(uint8_t* ath_tc)
Sinan Divarci 0:dc5ded118d7c 673 {
Sinan Divarci 0:dc5ded118d7c 674 int ret;
Sinan Divarci 0:dc5ded118d7c 675
Sinan Divarci 0:dc5ded118d7c 676 ret = read_register(ATH_CFG2_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg2), 1);
Sinan Divarci 0:dc5ded118d7c 677 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 678 return ret;
Sinan Divarci 0:dc5ded118d7c 679 }
Sinan Divarci 0:dc5ded118d7c 680
Sinan Divarci 0:dc5ded118d7c 681 *ath_tc = (uint8_t)this->reg_map->reg_ath_cfg2.bits.ath_tc;
Sinan Divarci 0:dc5ded118d7c 682
Sinan Divarci 0:dc5ded118d7c 683 return 0;
Sinan Divarci 0:dc5ded118d7c 684 }
Sinan Divarci 0:dc5ded118d7c 685
Sinan Divarci 0:dc5ded118d7c 686 template <class REG>
Sinan Divarci 0:dc5ded118d7c 687 int MAX4147X<REG>::set_ath_type(ath_type_t ath_type)
Sinan Divarci 0:dc5ded118d7c 688 {
Sinan Divarci 0:dc5ded118d7c 689 SET_BIT_FIELD(ATH_CFG3_ADDR, this->reg_map->reg_ath_cfg3, this->reg_map->reg_ath_cfg3.bits.ath_type, ath_type);
Sinan Divarci 0:dc5ded118d7c 690
Sinan Divarci 0:dc5ded118d7c 691 return 0;
Sinan Divarci 0:dc5ded118d7c 692 }
Sinan Divarci 0:dc5ded118d7c 693
Sinan Divarci 0:dc5ded118d7c 694 template <class REG>
Sinan Divarci 0:dc5ded118d7c 695 int MAX4147X<REG>::get_ath_type(ath_type_t* ath_type)
Sinan Divarci 0:dc5ded118d7c 696 {
Sinan Divarci 0:dc5ded118d7c 697 int ret;
Sinan Divarci 0:dc5ded118d7c 698
Sinan Divarci 0:dc5ded118d7c 699 ret = read_register(ATH_CFG3_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg3), 1);
Sinan Divarci 0:dc5ded118d7c 700 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 701 return ret;
Sinan Divarci 0:dc5ded118d7c 702 }
Sinan Divarci 0:dc5ded118d7c 703
Sinan Divarci 0:dc5ded118d7c 704 *ath_type = (ath_type_t)this->reg_map->reg_ath_cfg3.bits.ath_type;
Sinan Divarci 0:dc5ded118d7c 705
Sinan Divarci 0:dc5ded118d7c 706 return 0;
Sinan Divarci 0:dc5ded118d7c 707 }
Sinan Divarci 0:dc5ded118d7c 708
Sinan Divarci 0:dc5ded118d7c 709 template <class REG>
Sinan Divarci 0:dc5ded118d7c 710 int MAX4147X<REG>::set_ath_bw(ath_bw_t ath_bw)
Sinan Divarci 0:dc5ded118d7c 711 {
Sinan Divarci 0:dc5ded118d7c 712 SET_BIT_FIELD(ATH_CFG3_ADDR, this->reg_map->reg_ath_cfg3, this->reg_map->reg_ath_cfg3.bits.ath_bw, ath_bw);
Sinan Divarci 0:dc5ded118d7c 713
Sinan Divarci 0:dc5ded118d7c 714 return 0;
Sinan Divarci 0:dc5ded118d7c 715 }
Sinan Divarci 0:dc5ded118d7c 716
Sinan Divarci 0:dc5ded118d7c 717 template <class REG>
Sinan Divarci 0:dc5ded118d7c 718 int MAX4147X<REG>::get_ath_bw(ath_bw_t* ath_bw)
Sinan Divarci 0:dc5ded118d7c 719 {
Sinan Divarci 0:dc5ded118d7c 720 int ret;
Sinan Divarci 0:dc5ded118d7c 721
Sinan Divarci 0:dc5ded118d7c 722 ret = read_register(ATH_CFG3_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg3), 1);
Sinan Divarci 0:dc5ded118d7c 723 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 724 return ret;
Sinan Divarci 0:dc5ded118d7c 725 }
Sinan Divarci 0:dc5ded118d7c 726
Sinan Divarci 0:dc5ded118d7c 727 *ath_bw = (ath_bw_t)this->reg_map->reg_ath_cfg3.bits.ath_bw;
Sinan Divarci 0:dc5ded118d7c 728
Sinan Divarci 0:dc5ded118d7c 729 return 0;
Sinan Divarci 0:dc5ded118d7c 730 }
Sinan Divarci 0:dc5ded118d7c 731
Sinan Divarci 0:dc5ded118d7c 732 template <class REG>
Sinan Divarci 0:dc5ded118d7c 733 int MAX4147X<REG>::set_ath_gc(uint8_t ath_gc)
Sinan Divarci 0:dc5ded118d7c 734 {
Sinan Divarci 0:dc5ded118d7c 735 SET_BIT_FIELD(ATH_CFG3_ADDR, this->reg_map->reg_ath_cfg3, this->reg_map->reg_ath_cfg3.bits.ath_gc, ath_gc);
Sinan Divarci 0:dc5ded118d7c 736
Sinan Divarci 0:dc5ded118d7c 737 return 0;
Sinan Divarci 0:dc5ded118d7c 738 }
Sinan Divarci 0:dc5ded118d7c 739
Sinan Divarci 0:dc5ded118d7c 740 template <class REG>
Sinan Divarci 0:dc5ded118d7c 741 int MAX4147X<REG>::get_ath_gc(uint8_t* ath_gc)
Sinan Divarci 0:dc5ded118d7c 742 {
Sinan Divarci 0:dc5ded118d7c 743 int ret;
Sinan Divarci 0:dc5ded118d7c 744
Sinan Divarci 0:dc5ded118d7c 745 ret = read_register(ATH_CFG3_ADDR, (uint8_t *) & (this->reg_map->reg_ath_cfg3), 1);
Sinan Divarci 0:dc5ded118d7c 746 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 747 return ret;
Sinan Divarci 0:dc5ded118d7c 748 }
Sinan Divarci 0:dc5ded118d7c 749
Sinan Divarci 0:dc5ded118d7c 750 *ath_gc = (uint8_t)this->reg_map->reg_ath_cfg3.bits.ath_gc;
Sinan Divarci 0:dc5ded118d7c 751
Sinan Divarci 0:dc5ded118d7c 752 return 0;
Sinan Divarci 0:dc5ded118d7c 753 }
Sinan Divarci 0:dc5ded118d7c 754
Sinan Divarci 0:dc5ded118d7c 755 template <class REG>
Sinan Divarci 0:dc5ded118d7c 756 int MAX4147X<REG>::set_afc_mo(afc_mo_t afc_mo)
Sinan Divarci 0:dc5ded118d7c 757 {
Sinan Divarci 0:dc5ded118d7c 758 SET_BIT_FIELD(AFC_CFG1_ADDR, this->reg_map->reg_afc_cfg1, this->reg_map->reg_afc_cfg1.bits.afc_mo, afc_mo);
Sinan Divarci 0:dc5ded118d7c 759
Sinan Divarci 0:dc5ded118d7c 760 return 0;
Sinan Divarci 0:dc5ded118d7c 761 }
Sinan Divarci 0:dc5ded118d7c 762
Sinan Divarci 0:dc5ded118d7c 763 template <class REG>
Sinan Divarci 0:dc5ded118d7c 764 int MAX4147X<REG>::get_afc_mo(afc_mo_t* afc_mo)
Sinan Divarci 0:dc5ded118d7c 765 {
Sinan Divarci 0:dc5ded118d7c 766 int ret;
Sinan Divarci 0:dc5ded118d7c 767
Sinan Divarci 0:dc5ded118d7c 768 ret = read_register(AFC_CFG1_ADDR, (uint8_t *) & (this->reg_map->reg_afc_cfg1), 1);
Sinan Divarci 0:dc5ded118d7c 769 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 770 return ret;
Sinan Divarci 0:dc5ded118d7c 771 }
Sinan Divarci 0:dc5ded118d7c 772
Sinan Divarci 0:dc5ded118d7c 773 *afc_mo = (afc_mo_t)this->reg_map->reg_afc_cfg1.bits.afc_mo;
Sinan Divarci 0:dc5ded118d7c 774
Sinan Divarci 0:dc5ded118d7c 775 return 0;
Sinan Divarci 0:dc5ded118d7c 776 }
Sinan Divarci 0:dc5ded118d7c 777
Sinan Divarci 0:dc5ded118d7c 778 template <class REG>
Sinan Divarci 0:dc5ded118d7c 779 int MAX4147X<REG>::set_afc_lg(afc_lg_t afc_lg)
Sinan Divarci 0:dc5ded118d7c 780 {
Sinan Divarci 0:dc5ded118d7c 781 SET_BIT_FIELD(AFC_CFG1_ADDR, this->reg_map->reg_afc_cfg1, this->reg_map->reg_afc_cfg1.bits.afc_lg, afc_lg);
Sinan Divarci 0:dc5ded118d7c 782
Sinan Divarci 0:dc5ded118d7c 783 return 0;
Sinan Divarci 0:dc5ded118d7c 784 }
Sinan Divarci 0:dc5ded118d7c 785
Sinan Divarci 0:dc5ded118d7c 786 template <class REG>
Sinan Divarci 0:dc5ded118d7c 787 int MAX4147X<REG>::get_afc_lg(afc_lg_t* afc_lg)
Sinan Divarci 0:dc5ded118d7c 788 {
Sinan Divarci 0:dc5ded118d7c 789 int ret;
Sinan Divarci 0:dc5ded118d7c 790
Sinan Divarci 0:dc5ded118d7c 791 ret = read_register(AFC_CFG1_ADDR, (uint8_t *) & (this->reg_map->reg_afc_cfg1), 1);
Sinan Divarci 0:dc5ded118d7c 792 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 793 return ret;
Sinan Divarci 0:dc5ded118d7c 794 }
Sinan Divarci 0:dc5ded118d7c 795
Sinan Divarci 0:dc5ded118d7c 796 *afc_lg = (afc_lg_t)this->reg_map->reg_afc_cfg1.bits.afc_lg;
Sinan Divarci 0:dc5ded118d7c 797
Sinan Divarci 0:dc5ded118d7c 798 return 0;
Sinan Divarci 0:dc5ded118d7c 799 }
Sinan Divarci 0:dc5ded118d7c 800
Sinan Divarci 0:dc5ded118d7c 801 template <class REG>
Sinan Divarci 0:dc5ded118d7c 802 int MAX4147X<REG>::set_pad_freeze_afc(pad_freeze_afc_t pad_freeze_afc)
Sinan Divarci 0:dc5ded118d7c 803 {
Sinan Divarci 0:dc5ded118d7c 804 SET_BIT_FIELD(AFC_CFG2_ADDR, this->reg_map->reg_afc_cfg2, this->reg_map->reg_afc_cfg2.bits.pad_freeze_afc, pad_freeze_afc);
Sinan Divarci 0:dc5ded118d7c 805
Sinan Divarci 0:dc5ded118d7c 806 return 0;
Sinan Divarci 0:dc5ded118d7c 807 }
Sinan Divarci 0:dc5ded118d7c 808
Sinan Divarci 0:dc5ded118d7c 809 template <class REG>
Sinan Divarci 0:dc5ded118d7c 810 int MAX4147X<REG>::get_pad_freeze_afc(pad_freeze_afc_t* pad_freeze_afc)
Sinan Divarci 0:dc5ded118d7c 811 {
Sinan Divarci 0:dc5ded118d7c 812 int ret;
Sinan Divarci 0:dc5ded118d7c 813
Sinan Divarci 0:dc5ded118d7c 814 ret = read_register(AFC_CFG2_ADDR, (uint8_t *) & (this->reg_map->reg_afc_cfg2), 1);
Sinan Divarci 0:dc5ded118d7c 815 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 816 return ret;
Sinan Divarci 0:dc5ded118d7c 817 }
Sinan Divarci 0:dc5ded118d7c 818
Sinan Divarci 0:dc5ded118d7c 819 *pad_freeze_afc = (pad_freeze_afc_t)this->reg_map->reg_afc_cfg2.bits.pad_freeze_afc;
Sinan Divarci 0:dc5ded118d7c 820
Sinan Divarci 0:dc5ded118d7c 821 return 0;
Sinan Divarci 0:dc5ded118d7c 822 }
Sinan Divarci 0:dc5ded118d7c 823
Sinan Divarci 0:dc5ded118d7c 824 template <class REG>
Sinan Divarci 0:dc5ded118d7c 825 int MAX4147X<REG>::set_lo_ctr_freq_upper(uint8_t lo_ctr_freq_upper)
Sinan Divarci 0:dc5ded118d7c 826 {
Sinan Divarci 0:dc5ded118d7c 827 SET_BIT_FIELD(LO_CTR_FREQ3_ADDR, this->reg_map->reg_lo_ctr_freq3, this->reg_map->reg_lo_ctr_freq3.bits.lo_ctr_freq_23_to_16, lo_ctr_freq_upper);
Sinan Divarci 0:dc5ded118d7c 828
Sinan Divarci 0:dc5ded118d7c 829 return 0;
Sinan Divarci 0:dc5ded118d7c 830 }
Sinan Divarci 0:dc5ded118d7c 831
Sinan Divarci 0:dc5ded118d7c 832 template <class REG>
Sinan Divarci 0:dc5ded118d7c 833 int MAX4147X<REG>::get_lo_ctr_freq_upper(uint8_t* lo_ctr_freq_upper)
Sinan Divarci 0:dc5ded118d7c 834 {
Sinan Divarci 0:dc5ded118d7c 835 int ret;
Sinan Divarci 0:dc5ded118d7c 836
Sinan Divarci 0:dc5ded118d7c 837 ret = read_register(LO_CTR_FREQ3_ADDR, (uint8_t *) & (this->reg_map->reg_lo_ctr_freq3), 1);
Sinan Divarci 0:dc5ded118d7c 838 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 839 return ret;
Sinan Divarci 0:dc5ded118d7c 840 }
Sinan Divarci 0:dc5ded118d7c 841
Sinan Divarci 0:dc5ded118d7c 842 *lo_ctr_freq_upper = (uint8_t)this->reg_map->reg_lo_ctr_freq3.bits.lo_ctr_freq_23_to_16;
Sinan Divarci 0:dc5ded118d7c 843
Sinan Divarci 0:dc5ded118d7c 844 return 0;
Sinan Divarci 0:dc5ded118d7c 845 }
Sinan Divarci 0:dc5ded118d7c 846
Sinan Divarci 0:dc5ded118d7c 847 template <class REG>
Sinan Divarci 0:dc5ded118d7c 848 int MAX4147X<REG>::set_lo_ctr_freq_middle(uint8_t lo_ctr_freq_middle)
Sinan Divarci 0:dc5ded118d7c 849 {
Sinan Divarci 0:dc5ded118d7c 850 SET_BIT_FIELD(LO_CTR_FREQ2_ADDR, this->reg_map->reg_lo_ctr_freq2, this->reg_map->reg_lo_ctr_freq2.bits.lo_ctr_freq_15_to_8, lo_ctr_freq_middle);
Sinan Divarci 0:dc5ded118d7c 851
Sinan Divarci 0:dc5ded118d7c 852 return 0;
Sinan Divarci 0:dc5ded118d7c 853 }
Sinan Divarci 0:dc5ded118d7c 854
Sinan Divarci 0:dc5ded118d7c 855 template <class REG>
Sinan Divarci 0:dc5ded118d7c 856 int MAX4147X<REG>::get_lo_ctr_freq_middle(uint8_t* lo_ctr_freq_middle)
Sinan Divarci 0:dc5ded118d7c 857 {
Sinan Divarci 0:dc5ded118d7c 858 int ret;
Sinan Divarci 0:dc5ded118d7c 859
Sinan Divarci 0:dc5ded118d7c 860 ret = read_register(LO_CTR_FREQ2_ADDR, (uint8_t *) & (this->reg_map->reg_lo_ctr_freq2), 1);
Sinan Divarci 0:dc5ded118d7c 861 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 862 return ret;
Sinan Divarci 0:dc5ded118d7c 863 }
Sinan Divarci 0:dc5ded118d7c 864
Sinan Divarci 0:dc5ded118d7c 865 *lo_ctr_freq_middle = (uint8_t)this->reg_map->reg_lo_ctr_freq2.bits.lo_ctr_freq_15_to_8;
Sinan Divarci 0:dc5ded118d7c 866
Sinan Divarci 0:dc5ded118d7c 867 return 0;
Sinan Divarci 0:dc5ded118d7c 868 }
Sinan Divarci 0:dc5ded118d7c 869
Sinan Divarci 0:dc5ded118d7c 870 template <class REG>
Sinan Divarci 0:dc5ded118d7c 871 int MAX4147X<REG>::set_lo_ctr_freq_lower(uint8_t lo_ctr_freq_lower)
Sinan Divarci 0:dc5ded118d7c 872 {
Sinan Divarci 0:dc5ded118d7c 873 SET_BIT_FIELD(LO_CTR_FREQ1_ADDR, this->reg_map->reg_lo_ctr_freq1, this->reg_map->reg_lo_ctr_freq1.bits.lo_ctr_freq_7_to_0, lo_ctr_freq_lower);
Sinan Divarci 0:dc5ded118d7c 874
Sinan Divarci 0:dc5ded118d7c 875 return 0;
Sinan Divarci 0:dc5ded118d7c 876 }
Sinan Divarci 0:dc5ded118d7c 877
Sinan Divarci 0:dc5ded118d7c 878 template <class REG>
Sinan Divarci 0:dc5ded118d7c 879 int MAX4147X<REG>::get_lo_ctr_freq_lower(uint8_t* lo_ctr_freq_lower)
Sinan Divarci 0:dc5ded118d7c 880 {
Sinan Divarci 0:dc5ded118d7c 881 int ret;
Sinan Divarci 0:dc5ded118d7c 882
Sinan Divarci 0:dc5ded118d7c 883 ret = read_register(LO_CTR_FREQ1_ADDR, (uint8_t *) & (this->reg_map->reg_lo_ctr_freq1), 1);
Sinan Divarci 0:dc5ded118d7c 884 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 885 return ret;
Sinan Divarci 0:dc5ded118d7c 886 }
Sinan Divarci 0:dc5ded118d7c 887
Sinan Divarci 0:dc5ded118d7c 888 *lo_ctr_freq_lower = (uint8_t)this->reg_map->reg_lo_ctr_freq1.bits.lo_ctr_freq_7_to_0;
Sinan Divarci 0:dc5ded118d7c 889
Sinan Divarci 0:dc5ded118d7c 890 return 0;
Sinan Divarci 0:dc5ded118d7c 891 }
Sinan Divarci 0:dc5ded118d7c 892
Sinan Divarci 0:dc5ded118d7c 893 template <class REG>
Sinan Divarci 0:dc5ded118d7c 894 int MAX4147X<REG>::set_preamb_len(uint8_t preamb_len)
Sinan Divarci 0:dc5ded118d7c 895 {
Sinan Divarci 0:dc5ded118d7c 896 SET_BIT_FIELD(PREAMBLE_CFG1_ADDR, this->reg_map->reg_preamble_cfg1, this->reg_map->reg_preamble_cfg1.bits.preamb_len, preamb_len);
Sinan Divarci 0:dc5ded118d7c 897
Sinan Divarci 0:dc5ded118d7c 898 return 0;
Sinan Divarci 0:dc5ded118d7c 899 }
Sinan Divarci 0:dc5ded118d7c 900
Sinan Divarci 0:dc5ded118d7c 901 template <class REG>
Sinan Divarci 0:dc5ded118d7c 902 int MAX4147X<REG>::get_preamb_len(uint8_t* preamb_len)
Sinan Divarci 0:dc5ded118d7c 903 {
Sinan Divarci 0:dc5ded118d7c 904 int ret;
Sinan Divarci 0:dc5ded118d7c 905
Sinan Divarci 0:dc5ded118d7c 906 ret = read_register(PREAMBLE_CFG1_ADDR, (uint8_t *) & (this->reg_map->reg_preamble_cfg1), 1);
Sinan Divarci 0:dc5ded118d7c 907 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 908 return ret;
Sinan Divarci 0:dc5ded118d7c 909 }
Sinan Divarci 0:dc5ded118d7c 910
Sinan Divarci 0:dc5ded118d7c 911 *preamb_len = (uint8_t)this->reg_map->reg_preamble_cfg1.bits.preamb_len;
Sinan Divarci 0:dc5ded118d7c 912
Sinan Divarci 0:dc5ded118d7c 913 return 0;
Sinan Divarci 0:dc5ded118d7c 914 }
Sinan Divarci 0:dc5ded118d7c 915
Sinan Divarci 0:dc5ded118d7c 916 template <class REG>
Sinan Divarci 0:dc5ded118d7c 917 int MAX4147X<REG>::set_preamb_word_lower(uint8_t preamb_word_lower)
Sinan Divarci 0:dc5ded118d7c 918 {
Sinan Divarci 0:dc5ded118d7c 919 SET_BIT_FIELD(PREAMBLE_WORD1_ADDR, this->reg_map->reg_preamble_word1, this->reg_map->reg_preamble_word1.bits.preamb_word_7_to_0, preamb_word_lower);
Sinan Divarci 0:dc5ded118d7c 920
Sinan Divarci 0:dc5ded118d7c 921 return 0;
Sinan Divarci 0:dc5ded118d7c 922 }
Sinan Divarci 0:dc5ded118d7c 923
Sinan Divarci 0:dc5ded118d7c 924 template <class REG>
Sinan Divarci 0:dc5ded118d7c 925 int MAX4147X<REG>::get_preamb_word_lower(uint8_t* preamb_word_lower)
Sinan Divarci 0:dc5ded118d7c 926 {
Sinan Divarci 0:dc5ded118d7c 927 int ret;
Sinan Divarci 0:dc5ded118d7c 928
Sinan Divarci 0:dc5ded118d7c 929 ret = read_register(PREAMBLE_WORD1_ADDR, (uint8_t *) & (this->reg_map->reg_preamble_word1), 1);
Sinan Divarci 0:dc5ded118d7c 930 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 931 return ret;
Sinan Divarci 0:dc5ded118d7c 932 }
Sinan Divarci 0:dc5ded118d7c 933
Sinan Divarci 0:dc5ded118d7c 934 *preamb_word_lower = (uint8_t)this->reg_map->reg_preamble_word1.bits.preamb_word_7_to_0;
Sinan Divarci 0:dc5ded118d7c 935
Sinan Divarci 0:dc5ded118d7c 936 return 0;
Sinan Divarci 0:dc5ded118d7c 937 }
Sinan Divarci 0:dc5ded118d7c 938
Sinan Divarci 0:dc5ded118d7c 939 template <class REG>
Sinan Divarci 0:dc5ded118d7c 940 int MAX4147X<REG>::set_preamb_word_upper(uint8_t preamb_word_upper)
Sinan Divarci 0:dc5ded118d7c 941 {
Sinan Divarci 0:dc5ded118d7c 942 SET_BIT_FIELD(PREAMBLE_WORD2_ADDR, this->reg_map->reg_preamble_word2, this->reg_map->reg_preamble_word2.bits.preamb_word_15_to_8, preamb_word_upper);
Sinan Divarci 0:dc5ded118d7c 943
Sinan Divarci 0:dc5ded118d7c 944 return 0;
Sinan Divarci 0:dc5ded118d7c 945 }
Sinan Divarci 0:dc5ded118d7c 946
Sinan Divarci 0:dc5ded118d7c 947 template <class REG>
Sinan Divarci 0:dc5ded118d7c 948 int MAX4147X<REG>::get_preamb_word_upper(uint8_t* preamb_word_upper)
Sinan Divarci 0:dc5ded118d7c 949 {
Sinan Divarci 0:dc5ded118d7c 950 int ret;
Sinan Divarci 0:dc5ded118d7c 951
Sinan Divarci 0:dc5ded118d7c 952 ret = read_register(PREAMBLE_WORD2_ADDR, (uint8_t *) & (this->reg_map->reg_preamble_word2), 1);
Sinan Divarci 0:dc5ded118d7c 953 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 954 return ret;
Sinan Divarci 0:dc5ded118d7c 955 }
Sinan Divarci 0:dc5ded118d7c 956
Sinan Divarci 0:dc5ded118d7c 957 *preamb_word_upper = (uint8_t)this->reg_map->reg_preamble_word2.bits.preamb_word_15_to_8;
Sinan Divarci 0:dc5ded118d7c 958
Sinan Divarci 0:dc5ded118d7c 959 return 0;
Sinan Divarci 0:dc5ded118d7c 960 }
Sinan Divarci 0:dc5ded118d7c 961
Sinan Divarci 0:dc5ded118d7c 962 template <class REG>
Sinan Divarci 0:dc5ded118d7c 963 int MAX4147X<REG>::get_rssi(uint8_t* rssi)
Sinan Divarci 0:dc5ded118d7c 964 {
Sinan Divarci 0:dc5ded118d7c 965 int ret;
Sinan Divarci 0:dc5ded118d7c 966
Sinan Divarci 0:dc5ded118d7c 967 ret = read_register(RSSI_ADDR, (uint8_t *) & (this->reg_map->reg_rssi), 1);
Sinan Divarci 0:dc5ded118d7c 968 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 969 return ret;
Sinan Divarci 0:dc5ded118d7c 970 }
Sinan Divarci 0:dc5ded118d7c 971
Sinan Divarci 0:dc5ded118d7c 972 *rssi = (uint8_t)this->reg_map->reg_rssi.bits.rssi;
Sinan Divarci 0:dc5ded118d7c 973
Sinan Divarci 0:dc5ded118d7c 974 return 0;
Sinan Divarci 0:dc5ded118d7c 975 }
Sinan Divarci 0:dc5ded118d7c 976
Sinan Divarci 0:dc5ded118d7c 977 template <class REG>
Sinan Divarci 0:dc5ded118d7c 978 int MAX4147X<REG>::get_fei(uint8_t* fei)
Sinan Divarci 0:dc5ded118d7c 979 {
Sinan Divarci 0:dc5ded118d7c 980 int ret;
Sinan Divarci 0:dc5ded118d7c 981
Sinan Divarci 0:dc5ded118d7c 982 ret = read_register(FEI_ADDR, (uint8_t *) & (this->reg_map->reg_fei), 1);
Sinan Divarci 0:dc5ded118d7c 983 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 984 return ret;
Sinan Divarci 0:dc5ded118d7c 985 }
Sinan Divarci 0:dc5ded118d7c 986
Sinan Divarci 0:dc5ded118d7c 987 *fei = (uint8_t)this->reg_map->reg_fei.bits.fei;
Sinan Divarci 0:dc5ded118d7c 988
Sinan Divarci 0:dc5ded118d7c 989 return 0;
Sinan Divarci 0:dc5ded118d7c 990 }
Sinan Divarci 0:dc5ded118d7c 991
Sinan Divarci 0:dc5ded118d7c 992 template <class REG>
Sinan Divarci 0:dc5ded118d7c 993 int MAX4147X<REG>::get_pdf_out(uint8_t* pdf_out)
Sinan Divarci 0:dc5ded118d7c 994 {
Sinan Divarci 0:dc5ded118d7c 995 int ret;
Sinan Divarci 0:dc5ded118d7c 996
Sinan Divarci 0:dc5ded118d7c 997 ret = read_register(PDF_OUT_ADDR, (uint8_t *) & (this->reg_map->reg_pdf_out), 1);
Sinan Divarci 0:dc5ded118d7c 998 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 999 return ret;
Sinan Divarci 0:dc5ded118d7c 1000 }
Sinan Divarci 0:dc5ded118d7c 1001
Sinan Divarci 0:dc5ded118d7c 1002 *pdf_out = (uint8_t)this->reg_map->reg_pdf_out.bits.pdf_out;
Sinan Divarci 0:dc5ded118d7c 1003
Sinan Divarci 0:dc5ded118d7c 1004 return 0;
Sinan Divarci 0:dc5ded118d7c 1005 }
Sinan Divarci 0:dc5ded118d7c 1006
Sinan Divarci 0:dc5ded118d7c 1007 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1008 int MAX4147X<REG>::get_preamb_det(preamb_det_t *preamb_det)
Sinan Divarci 0:dc5ded118d7c 1009 {
Sinan Divarci 0:dc5ded118d7c 1010 int ret;
Sinan Divarci 0:dc5ded118d7c 1011
Sinan Divarci 0:dc5ded118d7c 1012 ret = read_register(ISR_ADDR, (uint8_t *) & (this->reg_map->reg_isr), 1);
Sinan Divarci 0:dc5ded118d7c 1013 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1014 return ret;
Sinan Divarci 0:dc5ded118d7c 1015 }
Sinan Divarci 0:dc5ded118d7c 1016
Sinan Divarci 0:dc5ded118d7c 1017 *preamb_det = (preamb_det_t)this->reg_map->reg_isr.bits.preamb_det;
Sinan Divarci 0:dc5ded118d7c 1018
Sinan Divarci 0:dc5ded118d7c 1019 return 0;
Sinan Divarci 0:dc5ded118d7c 1020 }
Sinan Divarci 0:dc5ded118d7c 1021
Sinan Divarci 0:dc5ded118d7c 1022 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1023 int MAX4147X<REG>::set_cdr_mode(cdr_mode_t cdr_mode)
Sinan Divarci 0:dc5ded118d7c 1024 {
Sinan Divarci 0:dc5ded118d7c 1025 SET_BIT_FIELD(CDR_CFG1_ADDR, this->reg_map->reg_cdr_cfg1, this->reg_map->reg_cdr_cfg1.bits.cdr_mode, cdr_mode);
Sinan Divarci 0:dc5ded118d7c 1026
Sinan Divarci 0:dc5ded118d7c 1027 return 0;
Sinan Divarci 0:dc5ded118d7c 1028 }
Sinan Divarci 0:dc5ded118d7c 1029
Sinan Divarci 0:dc5ded118d7c 1030 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1031 int MAX4147X<REG>::get_cdr_mode(cdr_mode_t* cdr_mode)
Sinan Divarci 0:dc5ded118d7c 1032 {
Sinan Divarci 0:dc5ded118d7c 1033 int ret;
Sinan Divarci 0:dc5ded118d7c 1034
Sinan Divarci 0:dc5ded118d7c 1035 ret = read_register(CDR_CFG1_ADDR, (uint8_t *) & (this->reg_map->reg_cdr_cfg1), 1);
Sinan Divarci 0:dc5ded118d7c 1036 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1037 return ret;
Sinan Divarci 0:dc5ded118d7c 1038 }
Sinan Divarci 0:dc5ded118d7c 1039
Sinan Divarci 0:dc5ded118d7c 1040 *cdr_mode = (cdr_mode_t)this->reg_map->reg_cdr_cfg1.bits.cdr_mode;
Sinan Divarci 0:dc5ded118d7c 1041
Sinan Divarci 0:dc5ded118d7c 1042 return 0;
Sinan Divarci 0:dc5ded118d7c 1043 }
Sinan Divarci 0:dc5ded118d7c 1044
Sinan Divarci 0:dc5ded118d7c 1045 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1046 int MAX4147X<REG>::set_en_xo(en_xo_t en_xo)
Sinan Divarci 0:dc5ded118d7c 1047 {
Sinan Divarci 0:dc5ded118d7c 1048 SET_BIT_FIELD(STATE_CTRL1_ADDR, this->reg_map->reg_state_ctrl1, this->reg_map->reg_state_ctrl1.bits.en_xo, en_xo);
Sinan Divarci 0:dc5ded118d7c 1049
Sinan Divarci 0:dc5ded118d7c 1050 return 0;
Sinan Divarci 0:dc5ded118d7c 1051 }
Sinan Divarci 0:dc5ded118d7c 1052
Sinan Divarci 0:dc5ded118d7c 1053 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1054 int MAX4147X<REG>::get_en_xo(en_xo_t* en_xo)
Sinan Divarci 0:dc5ded118d7c 1055 {
Sinan Divarci 0:dc5ded118d7c 1056 int ret;
Sinan Divarci 0:dc5ded118d7c 1057
Sinan Divarci 0:dc5ded118d7c 1058 ret = read_register(STATE_CTRL1_ADDR, (uint8_t *) & (this->reg_map->reg_state_ctrl1), 1);
Sinan Divarci 0:dc5ded118d7c 1059 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1060 return ret;
Sinan Divarci 0:dc5ded118d7c 1061 }
Sinan Divarci 0:dc5ded118d7c 1062
Sinan Divarci 0:dc5ded118d7c 1063 *en_xo = (en_xo_t)this->reg_map->reg_state_ctrl1.bits.en_xo;
Sinan Divarci 0:dc5ded118d7c 1064
Sinan Divarci 0:dc5ded118d7c 1065 return 0;
Sinan Divarci 0:dc5ded118d7c 1066 }
Sinan Divarci 0:dc5ded118d7c 1067
Sinan Divarci 0:dc5ded118d7c 1068 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1069 int MAX4147X<REG>::set_wut_en(wut_en_t wut_en)
Sinan Divarci 0:dc5ded118d7c 1070 {
Sinan Divarci 0:dc5ded118d7c 1071 SET_BIT_FIELD(STATE_CTRL1_ADDR, this->reg_map->reg_state_ctrl1, this->reg_map->reg_state_ctrl1.bits.wut_en, wut_en);
Sinan Divarci 0:dc5ded118d7c 1072
Sinan Divarci 0:dc5ded118d7c 1073 return 0;
Sinan Divarci 0:dc5ded118d7c 1074 }
Sinan Divarci 0:dc5ded118d7c 1075
Sinan Divarci 0:dc5ded118d7c 1076 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1077 int MAX4147X<REG>::get_wut_en(wut_en_t* wut_en)
Sinan Divarci 0:dc5ded118d7c 1078 {
Sinan Divarci 0:dc5ded118d7c 1079 int ret;
Sinan Divarci 0:dc5ded118d7c 1080
Sinan Divarci 0:dc5ded118d7c 1081 ret = read_register(STATE_CTRL1_ADDR, (uint8_t *) & (this->reg_map->reg_state_ctrl1), 1);
Sinan Divarci 0:dc5ded118d7c 1082 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1083 return ret;
Sinan Divarci 0:dc5ded118d7c 1084 }
Sinan Divarci 0:dc5ded118d7c 1085
Sinan Divarci 0:dc5ded118d7c 1086 *wut_en = (wut_en_t)this->reg_map->reg_state_ctrl1.bits.wut_en;
Sinan Divarci 0:dc5ded118d7c 1087
Sinan Divarci 0:dc5ded118d7c 1088 return 0;
Sinan Divarci 0:dc5ded118d7c 1089 }
Sinan Divarci 0:dc5ded118d7c 1090
Sinan Divarci 0:dc5ded118d7c 1091 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1092 int MAX4147X<REG>::set_slave_rx_en(slave_rx_en_t slave_rx_en)
Sinan Divarci 0:dc5ded118d7c 1093 {
Sinan Divarci 0:dc5ded118d7c 1094 SET_BIT_FIELD(STATE_CTRL1_ADDR, this->reg_map->reg_state_ctrl1, this->reg_map->reg_state_ctrl1.bits.slave_rx_en, slave_rx_en);
Sinan Divarci 0:dc5ded118d7c 1095
Sinan Divarci 0:dc5ded118d7c 1096 return 0;
Sinan Divarci 0:dc5ded118d7c 1097 }
Sinan Divarci 0:dc5ded118d7c 1098
Sinan Divarci 0:dc5ded118d7c 1099 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1100 int MAX4147X<REG>::get_slave_rx_en(slave_rx_en_t* slave_rx_en)
Sinan Divarci 0:dc5ded118d7c 1101 {
Sinan Divarci 0:dc5ded118d7c 1102 int ret;
Sinan Divarci 0:dc5ded118d7c 1103
Sinan Divarci 0:dc5ded118d7c 1104 ret = read_register(STATE_CTRL1_ADDR, (uint8_t *) & (this->reg_map->reg_state_ctrl1), 1);
Sinan Divarci 0:dc5ded118d7c 1105 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1106 return ret;
Sinan Divarci 0:dc5ded118d7c 1107 }
Sinan Divarci 0:dc5ded118d7c 1108
Sinan Divarci 0:dc5ded118d7c 1109 *slave_rx_en = (slave_rx_en_t)this->reg_map->reg_state_ctrl1.bits.slave_rx_en;
Sinan Divarci 0:dc5ded118d7c 1110
Sinan Divarci 0:dc5ded118d7c 1111 return 0;
Sinan Divarci 0:dc5ded118d7c 1112 }
Sinan Divarci 0:dc5ded118d7c 1113
Sinan Divarci 0:dc5ded118d7c 1114 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1115 int MAX4147X<REG>::get_rx_state(rx_state_t* rx_state)
Sinan Divarci 0:dc5ded118d7c 1116 {
Sinan Divarci 0:dc5ded118d7c 1117 int ret;
Sinan Divarci 0:dc5ded118d7c 1118
Sinan Divarci 0:dc5ded118d7c 1119 ret = read_register(STATE_CTRL2_ADDR, (uint8_t *) & (this->reg_map->reg_state_ctrl2), 1);
Sinan Divarci 0:dc5ded118d7c 1120 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1121 return ret;
Sinan Divarci 0:dc5ded118d7c 1122 }
Sinan Divarci 0:dc5ded118d7c 1123
Sinan Divarci 0:dc5ded118d7c 1124 *rx_state = (rx_state_t)this->reg_map->reg_state_ctrl2.bits.rx_state;
Sinan Divarci 0:dc5ded118d7c 1125
Sinan Divarci 0:dc5ded118d7c 1126 return 0;
Sinan Divarci 0:dc5ded118d7c 1127 }
Sinan Divarci 0:dc5ded118d7c 1128
Sinan Divarci 0:dc5ded118d7c 1129 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1130 int MAX4147X<REG>::set_rx_reset_time(rx_reset_time_t rx_reset_time)
Sinan Divarci 0:dc5ded118d7c 1131 {
Sinan Divarci 0:dc5ded118d7c 1132 SET_BIT_FIELD(STATE_CTRL3_ADDR, this->reg_map->reg_state_ctrl3, this->reg_map->reg_state_ctrl3.bits.rx_reset_time, rx_reset_time);
Sinan Divarci 0:dc5ded118d7c 1133
Sinan Divarci 0:dc5ded118d7c 1134 return 0;
Sinan Divarci 0:dc5ded118d7c 1135 }
Sinan Divarci 0:dc5ded118d7c 1136
Sinan Divarci 0:dc5ded118d7c 1137 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1138 int MAX4147X<REG>::get_rx_reset_time(rx_reset_time_t* rx_reset_time)
Sinan Divarci 0:dc5ded118d7c 1139 {
Sinan Divarci 0:dc5ded118d7c 1140 int ret;
Sinan Divarci 0:dc5ded118d7c 1141
Sinan Divarci 0:dc5ded118d7c 1142 ret = read_register(STATE_CTRL3_ADDR, (uint8_t *) & (this->reg_map->reg_state_ctrl3), 1);
Sinan Divarci 0:dc5ded118d7c 1143 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1144 return ret;
Sinan Divarci 0:dc5ded118d7c 1145 }
Sinan Divarci 0:dc5ded118d7c 1146
Sinan Divarci 0:dc5ded118d7c 1147 *rx_reset_time = (rx_reset_time_t)this->reg_map->reg_state_ctrl3.bits.rx_reset_time;
Sinan Divarci 0:dc5ded118d7c 1148
Sinan Divarci 0:dc5ded118d7c 1149 return 0;
Sinan Divarci 0:dc5ded118d7c 1150 }
Sinan Divarci 0:dc5ded118d7c 1151
Sinan Divarci 0:dc5ded118d7c 1152 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1153 int MAX4147X<REG>::set_tdet(uint8_t tdet)
Sinan Divarci 0:dc5ded118d7c 1154 {
Sinan Divarci 0:dc5ded118d7c 1155 SET_BIT_FIELD(WUT1_ADDR, this->reg_map->reg_wut1, this->reg_map->reg_wut1.bits.tdet, tdet);
Sinan Divarci 0:dc5ded118d7c 1156
Sinan Divarci 0:dc5ded118d7c 1157 return 0;
Sinan Divarci 0:dc5ded118d7c 1158 }
Sinan Divarci 0:dc5ded118d7c 1159
Sinan Divarci 0:dc5ded118d7c 1160 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1161 int MAX4147X<REG>::get_tdet(uint8_t* tdet)
Sinan Divarci 0:dc5ded118d7c 1162 {
Sinan Divarci 0:dc5ded118d7c 1163 int ret;
Sinan Divarci 0:dc5ded118d7c 1164
Sinan Divarci 0:dc5ded118d7c 1165 ret = read_register(WUT1_ADDR, (uint8_t *) & (this->reg_map->reg_wut1), 1);
Sinan Divarci 0:dc5ded118d7c 1166 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1167 return ret;
Sinan Divarci 0:dc5ded118d7c 1168 }
Sinan Divarci 0:dc5ded118d7c 1169
Sinan Divarci 0:dc5ded118d7c 1170 *tdet = (uint8_t)this->reg_map->reg_wut1.bits.tdet;
Sinan Divarci 0:dc5ded118d7c 1171
Sinan Divarci 0:dc5ded118d7c 1172 return 0;
Sinan Divarci 0:dc5ded118d7c 1173 }
Sinan Divarci 0:dc5ded118d7c 1174
Sinan Divarci 0:dc5ded118d7c 1175 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1176 int MAX4147X<REG>::set_tsby_tdet_ratio(uint8_t tsby_tdet_ratio)
Sinan Divarci 0:dc5ded118d7c 1177 {
Sinan Divarci 0:dc5ded118d7c 1178 SET_BIT_FIELD(WUT2_ADDR, this->reg_map->reg_wut2, this->reg_map->reg_wut2.bits.tsby_tdet_ratio, tsby_tdet_ratio);
Sinan Divarci 0:dc5ded118d7c 1179
Sinan Divarci 0:dc5ded118d7c 1180 return 0;
Sinan Divarci 0:dc5ded118d7c 1181 }
Sinan Divarci 0:dc5ded118d7c 1182
Sinan Divarci 0:dc5ded118d7c 1183 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1184 int MAX4147X<REG>::get_tsby_tdet_ratio(uint8_t* tsby_tdet_ratio)
Sinan Divarci 0:dc5ded118d7c 1185 {
Sinan Divarci 0:dc5ded118d7c 1186 int ret;
Sinan Divarci 0:dc5ded118d7c 1187
Sinan Divarci 0:dc5ded118d7c 1188 ret = read_register(WUT2_ADDR, (uint8_t *) & (this->reg_map->reg_wut2), 1);
Sinan Divarci 0:dc5ded118d7c 1189 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1190 return ret;
Sinan Divarci 0:dc5ded118d7c 1191 }
Sinan Divarci 0:dc5ded118d7c 1192
Sinan Divarci 0:dc5ded118d7c 1193 *tsby_tdet_ratio = (uint8_t)this->reg_map->reg_wut2.bits.tsby_tdet_ratio;
Sinan Divarci 0:dc5ded118d7c 1194
Sinan Divarci 0:dc5ded118d7c 1195 return 0;
Sinan Divarci 0:dc5ded118d7c 1196 }
Sinan Divarci 0:dc5ded118d7c 1197
Sinan Divarci 0:dc5ded118d7c 1198 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1199 int MAX4147X<REG>::set_xoclkdelay(xoclkdelay_t xoclkdelay)
Sinan Divarci 0:dc5ded118d7c 1200 {
Sinan Divarci 0:dc5ded118d7c 1201 SET_BIT_FIELD(AFE_CTL1_ADDR, this->reg_map->reg_afe_ctl1, this->reg_map->reg_afe_ctl1.bits.xoclkdelay, xoclkdelay);
Sinan Divarci 0:dc5ded118d7c 1202
Sinan Divarci 0:dc5ded118d7c 1203 return 0;
Sinan Divarci 0:dc5ded118d7c 1204 }
Sinan Divarci 0:dc5ded118d7c 1205
Sinan Divarci 0:dc5ded118d7c 1206 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1207 int MAX4147X<REG>::get_xoclkdelay(xoclkdelay_t* xoclkdelay)
Sinan Divarci 0:dc5ded118d7c 1208 {
Sinan Divarci 0:dc5ded118d7c 1209 int ret;
Sinan Divarci 0:dc5ded118d7c 1210
Sinan Divarci 0:dc5ded118d7c 1211 ret = read_register(AFE_CTL1_ADDR, (uint8_t *) & (this->reg_map->reg_afe_ctl1), 1);
Sinan Divarci 0:dc5ded118d7c 1212 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1213 return ret;
Sinan Divarci 0:dc5ded118d7c 1214 }
Sinan Divarci 0:dc5ded118d7c 1215
Sinan Divarci 0:dc5ded118d7c 1216 *xoclkdelay = (xoclkdelay_t)this->reg_map->reg_afe_ctl1.bits.xoclkdelay;
Sinan Divarci 0:dc5ded118d7c 1217
Sinan Divarci 0:dc5ded118d7c 1218 return 0;
Sinan Divarci 0:dc5ded118d7c 1219 }
Sinan Divarci 0:dc5ded118d7c 1220
Sinan Divarci 0:dc5ded118d7c 1221 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1222 int MAX4147X<REG>::set_xoclkdiv(xoclkdiv_t xoclkdiv)
Sinan Divarci 0:dc5ded118d7c 1223 {
Sinan Divarci 0:dc5ded118d7c 1224 SET_BIT_FIELD(AFE_CTL1_ADDR, this->reg_map->reg_afe_ctl1, this->reg_map->reg_afe_ctl1.bits.xoclkdiv, xoclkdiv);
Sinan Divarci 0:dc5ded118d7c 1225
Sinan Divarci 0:dc5ded118d7c 1226 return 0;
Sinan Divarci 0:dc5ded118d7c 1227 }
Sinan Divarci 0:dc5ded118d7c 1228
Sinan Divarci 0:dc5ded118d7c 1229 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1230 int MAX4147X<REG>::get_xoclkdiv(xoclkdiv_t* xoclkdiv)
Sinan Divarci 0:dc5ded118d7c 1231 {
Sinan Divarci 0:dc5ded118d7c 1232 int ret;
Sinan Divarci 0:dc5ded118d7c 1233
Sinan Divarci 0:dc5ded118d7c 1234 ret = read_register(AFE_CTL1_ADDR, (uint8_t *) & (this->reg_map->reg_afe_ctl1), 1);
Sinan Divarci 0:dc5ded118d7c 1235 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1236 return ret;
Sinan Divarci 0:dc5ded118d7c 1237 }
Sinan Divarci 0:dc5ded118d7c 1238
Sinan Divarci 0:dc5ded118d7c 1239 *xoclkdiv = (xoclkdiv_t)this->reg_map->reg_afe_ctl1.bits.xoclkdiv;
Sinan Divarci 0:dc5ded118d7c 1240
Sinan Divarci 0:dc5ded118d7c 1241 return 0;
Sinan Divarci 0:dc5ded118d7c 1242 }
Sinan Divarci 0:dc5ded118d7c 1243
Sinan Divarci 0:dc5ded118d7c 1244 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1245 int MAX4147X<REG>::set_mix_hs_lsbar(mix_hs_lsbar_t mix_hs_lsbar)
Sinan Divarci 0:dc5ded118d7c 1246 {
Sinan Divarci 0:dc5ded118d7c 1247 SET_BIT_FIELD(AFE_CTL1_ADDR, this->reg_map->reg_afe_ctl1, this->reg_map->reg_afe_ctl1.bits.mix_hs_lsbar, mix_hs_lsbar);
Sinan Divarci 0:dc5ded118d7c 1248
Sinan Divarci 0:dc5ded118d7c 1249 return 0;
Sinan Divarci 0:dc5ded118d7c 1250 }
Sinan Divarci 0:dc5ded118d7c 1251
Sinan Divarci 0:dc5ded118d7c 1252 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1253 int MAX4147X<REG>::get_mix_hs_lsbar(mix_hs_lsbar_t* mix_hs_lsbar)
Sinan Divarci 0:dc5ded118d7c 1254 {
Sinan Divarci 0:dc5ded118d7c 1255 int ret;
Sinan Divarci 0:dc5ded118d7c 1256
Sinan Divarci 0:dc5ded118d7c 1257 ret = read_register(AFE_CTL1_ADDR, (uint8_t *) & (this->reg_map->reg_afe_ctl1), 1);
Sinan Divarci 0:dc5ded118d7c 1258 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1259 return ret;
Sinan Divarci 0:dc5ded118d7c 1260 }
Sinan Divarci 0:dc5ded118d7c 1261
Sinan Divarci 0:dc5ded118d7c 1262 *mix_hs_lsbar = (mix_hs_lsbar_t)this->reg_map->reg_afe_ctl1.bits.mix_hs_lsbar;
Sinan Divarci 0:dc5ded118d7c 1263
Sinan Divarci 0:dc5ded118d7c 1264 return 0;
Sinan Divarci 0:dc5ded118d7c 1265 }
Sinan Divarci 0:dc5ded118d7c 1266
Sinan Divarci 0:dc5ded118d7c 1267 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1268 int MAX4147X<REG>::set_lodiv(lodiv_t lodiv)
Sinan Divarci 0:dc5ded118d7c 1269 {
Sinan Divarci 0:dc5ded118d7c 1270 SET_BIT_FIELD(AFE_CTL1_ADDR, this->reg_map->reg_afe_ctl1, this->reg_map->reg_afe_ctl1.bits.lodiv, lodiv);
Sinan Divarci 0:dc5ded118d7c 1271
Sinan Divarci 0:dc5ded118d7c 1272 return 0;
Sinan Divarci 0:dc5ded118d7c 1273 }
Sinan Divarci 0:dc5ded118d7c 1274
Sinan Divarci 0:dc5ded118d7c 1275 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1276 int MAX4147X<REG>::get_lodiv(lodiv_t* lodiv)
Sinan Divarci 0:dc5ded118d7c 1277 {
Sinan Divarci 0:dc5ded118d7c 1278 int ret;
Sinan Divarci 0:dc5ded118d7c 1279
Sinan Divarci 0:dc5ded118d7c 1280 ret = read_register(AFE_CTL1_ADDR, (uint8_t *) & (this->reg_map->reg_afe_ctl1), 1);
Sinan Divarci 0:dc5ded118d7c 1281 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1282 return ret;
Sinan Divarci 0:dc5ded118d7c 1283 }
Sinan Divarci 0:dc5ded118d7c 1284
Sinan Divarci 0:dc5ded118d7c 1285 *lodiv = (lodiv_t)this->reg_map->reg_afe_ctl1.bits.lodiv;
Sinan Divarci 0:dc5ded118d7c 1286
Sinan Divarci 0:dc5ded118d7c 1287 return 0;
Sinan Divarci 0:dc5ded118d7c 1288 }
Sinan Divarci 0:dc5ded118d7c 1289
Sinan Divarci 0:dc5ded118d7c 1290 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1291 int MAX4147X<REG>::set_fracmode(fracmode_t fracmode)
Sinan Divarci 0:dc5ded118d7c 1292 {
Sinan Divarci 0:dc5ded118d7c 1293 SET_BIT_FIELD(AFE_CTL1_ADDR, this->reg_map->reg_afe_ctl1, this->reg_map->reg_afe_ctl1.bits.fracmode, fracmode);
Sinan Divarci 0:dc5ded118d7c 1294
Sinan Divarci 0:dc5ded118d7c 1295 return 0;
Sinan Divarci 0:dc5ded118d7c 1296 }
Sinan Divarci 0:dc5ded118d7c 1297
Sinan Divarci 0:dc5ded118d7c 1298 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1299 int MAX4147X<REG>::get_fracmode(fracmode_t* fracmode)
Sinan Divarci 0:dc5ded118d7c 1300 {
Sinan Divarci 0:dc5ded118d7c 1301 int ret;
Sinan Divarci 0:dc5ded118d7c 1302
Sinan Divarci 0:dc5ded118d7c 1303 ret = read_register(AFE_CTL1_ADDR, (uint8_t *) & (this->reg_map->reg_afe_ctl1), 1);
Sinan Divarci 0:dc5ded118d7c 1304 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1305 return ret;
Sinan Divarci 0:dc5ded118d7c 1306 }
Sinan Divarci 0:dc5ded118d7c 1307
Sinan Divarci 0:dc5ded118d7c 1308 *fracmode = (fracmode_t)this->reg_map->reg_afe_ctl1.bits.fracmode;
Sinan Divarci 0:dc5ded118d7c 1309
Sinan Divarci 0:dc5ded118d7c 1310 return 0;
Sinan Divarci 0:dc5ded118d7c 1311 }
Sinan Divarci 0:dc5ded118d7c 1312
Sinan Divarci 0:dc5ded118d7c 1313 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1314 int MAX4147X<REG>::set_ir_adjust(uint8_t ir_adjust)
Sinan Divarci 0:dc5ded118d7c 1315 {
Sinan Divarci 0:dc5ded118d7c 1316 SET_BIT_FIELD(IR_ADJUST_ADDR, this->reg_map->reg_ir_adjust, this->reg_map->reg_ir_adjust.bits.ir_adjust, ir_adjust);
Sinan Divarci 0:dc5ded118d7c 1317
Sinan Divarci 0:dc5ded118d7c 1318 return 0;
Sinan Divarci 0:dc5ded118d7c 1319 }
Sinan Divarci 0:dc5ded118d7c 1320
Sinan Divarci 0:dc5ded118d7c 1321 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1322 int MAX4147X<REG>::get_ir_adjust(uint8_t* ir_adjust)
Sinan Divarci 0:dc5ded118d7c 1323 {
Sinan Divarci 0:dc5ded118d7c 1324 int ret;
Sinan Divarci 0:dc5ded118d7c 1325
Sinan Divarci 0:dc5ded118d7c 1326 ret = read_register(IR_ADJUST_ADDR, (uint8_t *) & (this->reg_map->reg_ir_adjust), 1);
Sinan Divarci 0:dc5ded118d7c 1327 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1328 return ret;
Sinan Divarci 0:dc5ded118d7c 1329 }
Sinan Divarci 0:dc5ded118d7c 1330
Sinan Divarci 0:dc5ded118d7c 1331 *ir_adjust = (uint8_t)this->reg_map->reg_ir_adjust.bits.ir_adjust;
Sinan Divarci 0:dc5ded118d7c 1332
Sinan Divarci 0:dc5ded118d7c 1333 return 0;
Sinan Divarci 0:dc5ded118d7c 1334 }
Sinan Divarci 0:dc5ded118d7c 1335
Sinan Divarci 0:dc5ded118d7c 1336 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1337 int MAX4147X<REG>::get_part_num(part_num_t* part_num)
Sinan Divarci 0:dc5ded118d7c 1338 {
Sinan Divarci 0:dc5ded118d7c 1339 int ret;
Sinan Divarci 0:dc5ded118d7c 1340
Sinan Divarci 0:dc5ded118d7c 1341 ret = read_register(PART_NUM_ADDR, (uint8_t *) & (this->reg_map->reg_part_num), 1);
Sinan Divarci 0:dc5ded118d7c 1342 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1343 return ret;
Sinan Divarci 0:dc5ded118d7c 1344 }
Sinan Divarci 0:dc5ded118d7c 1345
Sinan Divarci 0:dc5ded118d7c 1346 *part_num = (part_num_t)this->reg_map->reg_part_num.bits.part_num;
Sinan Divarci 0:dc5ded118d7c 1347
Sinan Divarci 0:dc5ded118d7c 1348 return 0;
Sinan Divarci 0:dc5ded118d7c 1349 }
Sinan Divarci 0:dc5ded118d7c 1350
Sinan Divarci 0:dc5ded118d7c 1351 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1352 int MAX4147X<REG>::get_rev_num(uint8_t* rev_num)
Sinan Divarci 0:dc5ded118d7c 1353 {
Sinan Divarci 0:dc5ded118d7c 1354 int ret;
Sinan Divarci 0:dc5ded118d7c 1355
Sinan Divarci 0:dc5ded118d7c 1356 ret = read_register(REV_NUM_ADDR, (uint8_t *) & (this->reg_map->reg_rev_num), 1);
Sinan Divarci 0:dc5ded118d7c 1357 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1358 return ret;
Sinan Divarci 0:dc5ded118d7c 1359 }
Sinan Divarci 0:dc5ded118d7c 1360
Sinan Divarci 0:dc5ded118d7c 1361 *rev_num = (uint8_t)this->reg_map->reg_rev_num.bits.rev_num;
Sinan Divarci 0:dc5ded118d7c 1362
Sinan Divarci 0:dc5ded118d7c 1363 return 0;
Sinan Divarci 0:dc5ded118d7c 1364 }
Sinan Divarci 0:dc5ded118d7c 1365
Sinan Divarci 0:dc5ded118d7c 1366 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1367 int MAX4147X<REG>::get_pll_lock(pll_lock_t* pll_lock)
Sinan Divarci 0:dc5ded118d7c 1368 {
Sinan Divarci 0:dc5ded118d7c 1369 int ret;
Sinan Divarci 0:dc5ded118d7c 1370
Sinan Divarci 0:dc5ded118d7c 1371 ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->reg_status), 1);
Sinan Divarci 0:dc5ded118d7c 1372 if (ret < 0) {
Sinan Divarci 0:dc5ded118d7c 1373 return ret;
Sinan Divarci 0:dc5ded118d7c 1374 }
Sinan Divarci 0:dc5ded118d7c 1375
Sinan Divarci 0:dc5ded118d7c 1376 *pll_lock = (pll_lock_t)this->reg_map->reg_status.bits.pll_lock;
Sinan Divarci 0:dc5ded118d7c 1377
Sinan Divarci 0:dc5ded118d7c 1378 return 0;
Sinan Divarci 0:dc5ded118d7c 1379 }
Sinan Divarci 0:dc5ded118d7c 1380
Sinan Divarci 0:dc5ded118d7c 1381 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1382 int MAX4147X<REG>::set_crystal_frequency(float freq)
Sinan Divarci 0:dc5ded118d7c 1383 {
Sinan Divarci 0:dc5ded118d7c 1384
Sinan Divarci 0:dc5ded118d7c 1385 if( ((int)freq == 12))
Sinan Divarci 0:dc5ded118d7c 1386 this->crystal_frequency = 12.8;
Sinan Divarci 0:dc5ded118d7c 1387 else if((int)freq == 16)
Sinan Divarci 0:dc5ded118d7c 1388 this->crystal_frequency = 16.0;
Sinan Divarci 0:dc5ded118d7c 1389 else if((int)freq == 19)
Sinan Divarci 0:dc5ded118d7c 1390 this->crystal_frequency = 19.2;
Sinan Divarci 0:dc5ded118d7c 1391 else
Sinan Divarci 0:dc5ded118d7c 1392 return -1;
Sinan Divarci 0:dc5ded118d7c 1393
Sinan Divarci 0:dc5ded118d7c 1394 if(this->adjust_crystal_divider() < 0)
Sinan Divarci 0:dc5ded118d7c 1395 return -2;
Sinan Divarci 0:dc5ded118d7c 1396 if(this->set_center_frequency(this->center_frequency) < 0)
Sinan Divarci 0:dc5ded118d7c 1397 return -3;
Sinan Divarci 0:dc5ded118d7c 1398
Sinan Divarci 0:dc5ded118d7c 1399 return 0;
Sinan Divarci 0:dc5ded118d7c 1400 }
Sinan Divarci 0:dc5ded118d7c 1401
Sinan Divarci 0:dc5ded118d7c 1402 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1403 float MAX4147X<REG>::get_crystal_frequency()
Sinan Divarci 0:dc5ded118d7c 1404 {
Sinan Divarci 0:dc5ded118d7c 1405 return this->crystal_frequency;
Sinan Divarci 0:dc5ded118d7c 1406 }
Sinan Divarci 0:dc5ded118d7c 1407
Sinan Divarci 0:dc5ded118d7c 1408 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1409 int MAX4147X<REG>::adjust_baud_rate(float baud_rate)
Sinan Divarci 0:dc5ded118d7c 1410 {
Sinan Divarci 0:dc5ded118d7c 1411 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 1412 uint8_t rate_index, src_lg_conf_idx, src_sm_conf_idx;
Sinan Divarci 0:dc5ded118d7c 1413 float nearestValue = 400, minDiff = 400;
Sinan Divarci 0:dc5ded118d7c 1414 float bit_rate_min, bit_rate_max, bit_rate, pre_rate, conf_rate, recommended_bit_rate, dif0, dif1;
Sinan Divarci 0:dc5ded118d7c 1415
Sinan Divarci 0:dc5ded118d7c 1416 if_sel_t *if_sel = (if_sel_t *)malloc(sizeof(if_sel_t));
Sinan Divarci 0:dc5ded118d7c 1417 if(if_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 1418 return -99;
Sinan Divarci 0:dc5ded118d7c 1419
Sinan Divarci 0:dc5ded118d7c 1420 chf_sel_t *chf_sel = (chf_sel_t *)malloc(sizeof(chf_sel_t));
Sinan Divarci 0:dc5ded118d7c 1421 if(chf_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 1422 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 1423 return -98;
Sinan Divarci 0:dc5ded118d7c 1424 }
Sinan Divarci 0:dc5ded118d7c 1425
Sinan Divarci 0:dc5ded118d7c 1426 src_lg_t *src_lg = (src_lg_t *)malloc(sizeof(src_lg_t));
Sinan Divarci 0:dc5ded118d7c 1427 if(src_lg == NULL){
Sinan Divarci 0:dc5ded118d7c 1428 free(if_sel); free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 1429 return -97;
Sinan Divarci 0:dc5ded118d7c 1430 }
Sinan Divarci 0:dc5ded118d7c 1431
Sinan Divarci 0:dc5ded118d7c 1432 src_sm_t *src_sm = (src_sm_t *)malloc(sizeof(src_sm_t));
Sinan Divarci 0:dc5ded118d7c 1433 if(src_sm == NULL){
Sinan Divarci 0:dc5ded118d7c 1434 free(if_sel); free(chf_sel); free(src_lg);
Sinan Divarci 0:dc5ded118d7c 1435 return -96;
Sinan Divarci 0:dc5ded118d7c 1436 }
Sinan Divarci 0:dc5ded118d7c 1437
Sinan Divarci 0:dc5ded118d7c 1438 if(encoding == Manchester){
Sinan Divarci 0:dc5ded118d7c 1439 bit_rate = baud_rate * 2;
Sinan Divarci 0:dc5ded118d7c 1440 recommended_bit_rate = this->baud_rate * 2;
Sinan Divarci 0:dc5ded118d7c 1441 }else{
Sinan Divarci 0:dc5ded118d7c 1442 bit_rate = baud_rate;
Sinan Divarci 0:dc5ded118d7c 1443 recommended_bit_rate = this->baud_rate;
Sinan Divarci 0:dc5ded118d7c 1444 }
Sinan Divarci 0:dc5ded118d7c 1445
Sinan Divarci 0:dc5ded118d7c 1446 if (bit_rate > 200.0 || bit_rate < 0){
Sinan Divarci 0:dc5ded118d7c 1447 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 1448 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1449 }
Sinan Divarci 0:dc5ded118d7c 1450
Sinan Divarci 0:dc5ded118d7c 1451 if(this->get_if_sel(if_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1452 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 1453 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1454 }
Sinan Divarci 0:dc5ded118d7c 1455 if(this->get_chf_sel(chf_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1456 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 1457 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1458 }
Sinan Divarci 0:dc5ded118d7c 1459 if(this->get_src_lg(src_lg) < 0){
Sinan Divarci 0:dc5ded118d7c 1460 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 1461 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1462 }
Sinan Divarci 0:dc5ded118d7c 1463 if(this->get_src_sm(src_sm) < 0){
Sinan Divarci 0:dc5ded118d7c 1464 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 1465 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1466 }
Sinan Divarci 0:dc5ded118d7c 1467
Sinan Divarci 0:dc5ded118d7c 1468 rate_index = (*if_sel) * 5 + (*chf_sel);
Sinan Divarci 0:dc5ded118d7c 1469
Sinan Divarci 0:dc5ded118d7c 1470 bit_rate_min = bit_rate_min_max[rate_index][0];
Sinan Divarci 0:dc5ded118d7c 1471 bit_rate_max = bit_rate_min_max[rate_index][1];
Sinan Divarci 0:dc5ded118d7c 1472
Sinan Divarci 0:dc5ded118d7c 1473 if(bit_rate < bit_rate_min || bit_rate > bit_rate_max){
Sinan Divarci 0:dc5ded118d7c 1474 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 1475 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1476 }
Sinan Divarci 0:dc5ded118d7c 1477
Sinan Divarci 0:dc5ded118d7c 1478 pre_rate = 1600.0 / (pow(2, (*if_sel + *chf_sel)));
Sinan Divarci 0:dc5ded118d7c 1479
Sinan Divarci 0:dc5ded118d7c 1480 for (src_sm_conf_idx = 0; src_sm_conf_idx < 8; src_sm_conf_idx++)
Sinan Divarci 0:dc5ded118d7c 1481 {
Sinan Divarci 0:dc5ded118d7c 1482 for (src_lg_conf_idx = 0; src_lg_conf_idx < 8; src_lg_conf_idx++)
Sinan Divarci 0:dc5ded118d7c 1483 {
Sinan Divarci 0:dc5ded118d7c 1484 conf_rate = (pre_rate / ((8 + src_sm_conf_idx) * pow(2, src_lg_conf_idx)));
Sinan Divarci 0:dc5ded118d7c 1485 dif0 = fabs(bit_rate - conf_rate);
Sinan Divarci 0:dc5ded118d7c 1486 dif1 = fabs(bit_rate - floor(conf_rate));
Sinan Divarci 0:dc5ded118d7c 1487
Sinan Divarci 0:dc5ded118d7c 1488 if (dif1 <= nearestValue && dif0 < minDiff && (0.6 * conf_rate) < bit_rate && bit_rate < (1.03 * conf_rate))
Sinan Divarci 0:dc5ded118d7c 1489 {
Sinan Divarci 0:dc5ded118d7c 1490 nearestValue = dif1;
Sinan Divarci 0:dc5ded118d7c 1491 minDiff = dif0;
Sinan Divarci 0:dc5ded118d7c 1492 *src_sm = (src_sm_t)src_sm_conf_idx;
Sinan Divarci 0:dc5ded118d7c 1493 *src_lg = (src_lg_t)src_lg_conf_idx;
Sinan Divarci 0:dc5ded118d7c 1494
Sinan Divarci 0:dc5ded118d7c 1495 this->baud_rate_ratio = bit_rate / conf_rate;
Sinan Divarci 0:dc5ded118d7c 1496 recommended_bit_rate = conf_rate;
Sinan Divarci 0:dc5ded118d7c 1497 }
Sinan Divarci 0:dc5ded118d7c 1498 }
Sinan Divarci 0:dc5ded118d7c 1499 }
Sinan Divarci 0:dc5ded118d7c 1500
Sinan Divarci 0:dc5ded118d7c 1501 this->set_src_lg(*src_lg);
Sinan Divarci 0:dc5ded118d7c 1502 this->set_src_sm(*src_sm);
Sinan Divarci 0:dc5ded118d7c 1503
Sinan Divarci 0:dc5ded118d7c 1504 if(encoding == Manchester)
Sinan Divarci 0:dc5ded118d7c 1505 this->baud_rate = recommended_bit_rate/2;
Sinan Divarci 0:dc5ded118d7c 1506 else
Sinan Divarci 0:dc5ded118d7c 1507 this->baud_rate = recommended_bit_rate;
Sinan Divarci 0:dc5ded118d7c 1508
Sinan Divarci 0:dc5ded118d7c 1509 if(this->update_ath_tc() < 0){
Sinan Divarci 0:dc5ded118d7c 1510 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 1511 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1512 }
Sinan Divarci 0:dc5ded118d7c 1513 if(this->update_ath_dt() < 0){
Sinan Divarci 0:dc5ded118d7c 1514 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 1515 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1516 }
Sinan Divarci 0:dc5ded118d7c 1517 if(this->update_ath_bw() < 0){
Sinan Divarci 0:dc5ded118d7c 1518 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 1519 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1520 }
Sinan Divarci 0:dc5ded118d7c 1521 if(this->update_agc_threl() < 0){
Sinan Divarci 0:dc5ded118d7c 1522 return_val = -10;
Sinan Divarci 0:dc5ded118d7c 1523 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1524 }
Sinan Divarci 0:dc5ded118d7c 1525 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 1526 return_val = -11;
Sinan Divarci 0:dc5ded118d7c 1527 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1528 }
Sinan Divarci 0:dc5ded118d7c 1529 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 1530 return_val = -12;
Sinan Divarci 0:dc5ded118d7c 1531 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1532 }
Sinan Divarci 0:dc5ded118d7c 1533
Sinan Divarci 0:dc5ded118d7c 1534 free_and_return:
Sinan Divarci 0:dc5ded118d7c 1535 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 1536 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 1537 free(src_lg);
Sinan Divarci 0:dc5ded118d7c 1538 free(src_sm);
Sinan Divarci 0:dc5ded118d7c 1539 return return_val;
Sinan Divarci 0:dc5ded118d7c 1540 }
Sinan Divarci 0:dc5ded118d7c 1541
Sinan Divarci 0:dc5ded118d7c 1542 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1543 float MAX4147X<REG>::get_baud_rate()
Sinan Divarci 0:dc5ded118d7c 1544 {
Sinan Divarci 0:dc5ded118d7c 1545 return this->baud_rate;
Sinan Divarci 0:dc5ded118d7c 1546 }
Sinan Divarci 0:dc5ded118d7c 1547
Sinan Divarci 0:dc5ded118d7c 1548 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1549 int MAX4147X<REG>::set_center_frequency(float freq)
Sinan Divarci 0:dc5ded118d7c 1550 {
Sinan Divarci 0:dc5ded118d7c 1551 int return_val = 0, lo_ctr_freq_reg_val;
Sinan Divarci 0:dc5ded118d7c 1552 float f_if, crystal_frequency;
Sinan Divarci 0:dc5ded118d7c 1553
Sinan Divarci 0:dc5ded118d7c 1554 mix_hs_lsbar_t *mix_hs_lsbar = (mix_hs_lsbar_t *)malloc(sizeof(mix_hs_lsbar_t));
Sinan Divarci 0:dc5ded118d7c 1555 if(mix_hs_lsbar == NULL)
Sinan Divarci 0:dc5ded118d7c 1556 return -99;
Sinan Divarci 0:dc5ded118d7c 1557
Sinan Divarci 0:dc5ded118d7c 1558 if_sel_t *if_sel = (if_sel_t *)malloc(sizeof(if_sel_t));
Sinan Divarci 0:dc5ded118d7c 1559 if(if_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 1560 free(mix_hs_lsbar);
Sinan Divarci 0:dc5ded118d7c 1561 return -98;
Sinan Divarci 0:dc5ded118d7c 1562 }
Sinan Divarci 0:dc5ded118d7c 1563
Sinan Divarci 0:dc5ded118d7c 1564 if(freq < 290 || freq > 960){
Sinan Divarci 0:dc5ded118d7c 1565 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 1566 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1567 }
Sinan Divarci 0:dc5ded118d7c 1568
Sinan Divarci 0:dc5ded118d7c 1569 if(freq >= 286.0 && freq<= 320.0)
Sinan Divarci 0:dc5ded118d7c 1570 this->set_lodiv(LODIV_286MHZ_TO_320MHZ);
Sinan Divarci 0:dc5ded118d7c 1571 else if(freq >= 425.0 && freq<= 480.0)
Sinan Divarci 0:dc5ded118d7c 1572 this->set_lodiv(LODIV_425MHZ_TO_480MHZ);
Sinan Divarci 0:dc5ded118d7c 1573 else if(freq >= 860.0 && freq<= 960.0)
Sinan Divarci 0:dc5ded118d7c 1574 this->set_lodiv(LODIV_860MHZ_TO_960MHZ);
Sinan Divarci 0:dc5ded118d7c 1575 else{
Sinan Divarci 0:dc5ded118d7c 1576 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 1577 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1578 }
Sinan Divarci 0:dc5ded118d7c 1579
Sinan Divarci 0:dc5ded118d7c 1580 if(this->get_mix_hs_lsbar(mix_hs_lsbar) < 0){
Sinan Divarci 0:dc5ded118d7c 1581 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 1582 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1583 }
Sinan Divarci 0:dc5ded118d7c 1584
Sinan Divarci 0:dc5ded118d7c 1585 if(this->get_if_sel(if_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1586 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 1587 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1588 }
Sinan Divarci 0:dc5ded118d7c 1589
Sinan Divarci 0:dc5ded118d7c 1590 crystal_frequency = this->get_crystal_frequency();
Sinan Divarci 0:dc5ded118d7c 1591
Sinan Divarci 0:dc5ded118d7c 1592 if(*if_sel == (IF_SEL_400_KHZ))
Sinan Divarci 0:dc5ded118d7c 1593 f_if = 0.4; //400kHz
Sinan Divarci 0:dc5ded118d7c 1594 else
Sinan Divarci 0:dc5ded118d7c 1595 f_if = 0.2; //200kHz
Sinan Divarci 0:dc5ded118d7c 1596
Sinan Divarci 0:dc5ded118d7c 1597 if(*mix_hs_lsbar == (MIX_HS_LSBAR_TARGET_HT_LO_FREQ))
Sinan Divarci 0:dc5ded118d7c 1598 lo_ctr_freq_reg_val = uint32_t( (65536*(freq - f_if)) / crystal_frequency);
Sinan Divarci 0:dc5ded118d7c 1599 else
Sinan Divarci 0:dc5ded118d7c 1600 lo_ctr_freq_reg_val = uint32_t( (65536*(freq + f_if)) / crystal_frequency);
Sinan Divarci 0:dc5ded118d7c 1601
Sinan Divarci 0:dc5ded118d7c 1602 this->set_lo_ctr_freq_upper(uint8_t(lo_ctr_freq_reg_val>>16));
Sinan Divarci 0:dc5ded118d7c 1603 this->set_lo_ctr_freq_middle(uint8_t(lo_ctr_freq_reg_val>>8));
Sinan Divarci 0:dc5ded118d7c 1604 this->set_lo_ctr_freq_lower(uint8_t(lo_ctr_freq_reg_val));
Sinan Divarci 0:dc5ded118d7c 1605
Sinan Divarci 0:dc5ded118d7c 1606 this->center_frequency = freq;
Sinan Divarci 0:dc5ded118d7c 1607
Sinan Divarci 0:dc5ded118d7c 1608 free_and_return:
Sinan Divarci 0:dc5ded118d7c 1609 free(mix_hs_lsbar);
Sinan Divarci 0:dc5ded118d7c 1610 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 1611 return return_val;
Sinan Divarci 0:dc5ded118d7c 1612 }
Sinan Divarci 0:dc5ded118d7c 1613
Sinan Divarci 0:dc5ded118d7c 1614 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1615 float MAX4147X<REG>::get_center_frequency()
Sinan Divarci 0:dc5ded118d7c 1616 {
Sinan Divarci 0:dc5ded118d7c 1617 return this->center_frequency;
Sinan Divarci 0:dc5ded118d7c 1618 }
Sinan Divarci 0:dc5ded118d7c 1619
Sinan Divarci 0:dc5ded118d7c 1620 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1621 int MAX4147X<REG>::set_power_on_off(uint8_t power) {
Sinan Divarci 0:dc5ded118d7c 1622 if (power > 0) { // Shut down the device
Sinan Divarci 0:dc5ded118d7c 1623
Sinan Divarci 0:dc5ded118d7c 1624 *this->power_pin = power;
Sinan Divarci 0:dc5ded118d7c 1625
Sinan Divarci 0:dc5ded118d7c 1626 } else { // Turn on the device
Sinan Divarci 0:dc5ded118d7c 1627
Sinan Divarci 0:dc5ded118d7c 1628 *this->power_pin = 0;
Sinan Divarci 0:dc5ded118d7c 1629 wait_us(1500);
Sinan Divarci 0:dc5ded118d7c 1630 *this->power_pin = 1;
Sinan Divarci 0:dc5ded118d7c 1631 wait_us(1500);
Sinan Divarci 0:dc5ded118d7c 1632 *this->power_pin = 0;
Sinan Divarci 0:dc5ded118d7c 1633 }
Sinan Divarci 0:dc5ded118d7c 1634
Sinan Divarci 0:dc5ded118d7c 1635 return 0;
Sinan Divarci 0:dc5ded118d7c 1636 }
Sinan Divarci 0:dc5ded118d7c 1637
Sinan Divarci 0:dc5ded118d7c 1638 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1639 int MAX4147X<REG>::initial_programming(void)
Sinan Divarci 0:dc5ded118d7c 1640 {
Sinan Divarci 0:dc5ded118d7c 1641 uint8_t address;
Sinan Divarci 0:dc5ded118d7c 1642
Sinan Divarci 0:dc5ded118d7c 1643 this->set_power_on_off(0);
Sinan Divarci 0:dc5ded118d7c 1644
Sinan Divarci 0:dc5ded118d7c 1645 this->set_en_xo(EN_XO_EN_XO);
Sinan Divarci 0:dc5ded118d7c 1646 wait_us(500);
Sinan Divarci 0:dc5ded118d7c 1647
Sinan Divarci 0:dc5ded118d7c 1648 if(this->write_register(0, default_register_value_0, (Q_CONF_LEN-1)) < 0)
Sinan Divarci 0:dc5ded118d7c 1649 return -1;
Sinan Divarci 0:dc5ded118d7c 1650 if(this->write_register(0x19, &default_register_value_0[Q_CONF_LEN-1], 1) <0 )
Sinan Divarci 0:dc5ded118d7c 1651 return -2;
Sinan Divarci 0:dc5ded118d7c 1652
Sinan Divarci 0:dc5ded118d7c 1653 wait_us(500);
Sinan Divarci 0:dc5ded118d7c 1654
Sinan Divarci 0:dc5ded118d7c 1655 address = 0x05;
Sinan Divarci 0:dc5ded118d7c 1656 if(this->write_register(0x14, &address, 1) < 0) //This will turn on the receiver and place the device into the SlaveRX state.
Sinan Divarci 0:dc5ded118d7c 1657 return -3;
Sinan Divarci 0:dc5ded118d7c 1658
Sinan Divarci 0:dc5ded118d7c 1659 return 0;
Sinan Divarci 0:dc5ded118d7c 1660 }
Sinan Divarci 0:dc5ded118d7c 1661
Sinan Divarci 0:dc5ded118d7c 1662 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1663 int MAX4147X<REG>::adjust_crystal_divider(void)
Sinan Divarci 0:dc5ded118d7c 1664 {
Sinan Divarci 0:dc5ded118d7c 1665 if( (int)this->crystal_frequency == 12)
Sinan Divarci 0:dc5ded118d7c 1666 return set_xoclkdiv(XOCLKDIV_DIVIDE_BY_4);
Sinan Divarci 0:dc5ded118d7c 1667 else if((int)this->crystal_frequency == 16)
Sinan Divarci 0:dc5ded118d7c 1668 return set_xoclkdiv(XOCLKDIV_DIVIDE_BY_5);
Sinan Divarci 0:dc5ded118d7c 1669 else if((int)this->crystal_frequency == 19)
Sinan Divarci 0:dc5ded118d7c 1670 return set_xoclkdiv(XOCLKDIV_DIVIDE_BY_6);
Sinan Divarci 0:dc5ded118d7c 1671 else
Sinan Divarci 0:dc5ded118d7c 1672 return -1;
Sinan Divarci 0:dc5ded118d7c 1673 }
Sinan Divarci 0:dc5ded118d7c 1674
Sinan Divarci 0:dc5ded118d7c 1675 template <>
Sinan Divarci 0:dc5ded118d7c 1676 int MAX4147X<max41470_reg_map_t>::read_data(uint8_t *data, uint32_t length)
Sinan Divarci 0:dc5ded118d7c 1677 {
Sinan Divarci 0:dc5ded118d7c 1678 preamb_det_t *preamb_det = (preamb_det_t *)malloc(sizeof(preamb_det_t));
Sinan Divarci 0:dc5ded118d7c 1679
Sinan Divarci 0:dc5ded118d7c 1680 if(preamb_det == NULL){
Sinan Divarci 0:dc5ded118d7c 1681 return -99;
Sinan Divarci 0:dc5ded118d7c 1682 }
Sinan Divarci 0:dc5ded118d7c 1683
Sinan Divarci 0:dc5ded118d7c 1684 if (this->preset_mode == 0) {
Sinan Divarci 0:dc5ded118d7c 1685 if(this->get_preamb_det(preamb_det) < 0){ //ISR Register is Read. PREAMB_DET bit and WUT_EN bit automatically cleared. MAX41470 placed into the Standby State.
Sinan Divarci 0:dc5ded118d7c 1686 free(preamb_det);
Sinan Divarci 0:dc5ded118d7c 1687 return -1;
Sinan Divarci 0:dc5ded118d7c 1688 }
Sinan Divarci 0:dc5ded118d7c 1689
Sinan Divarci 0:dc5ded118d7c 1690 if(*preamb_det != PREAMB_DET_PREAMB_DETECTED){ //Interrupt Status Register is not Set!
Sinan Divarci 0:dc5ded118d7c 1691 free(preamb_det);
Sinan Divarci 0:dc5ded118d7c 1692 return -2;
Sinan Divarci 0:dc5ded118d7c 1693 }
Sinan Divarci 0:dc5ded118d7c 1694
Sinan Divarci 0:dc5ded118d7c 1695 this->set_slave_rx_en(SLAVE_RX_EN_EN_RECEIVER); //MAX41470 moved from Standby to the SlaveRX state. DATA pin will be stream
Sinan Divarci 0:dc5ded118d7c 1696 }
Sinan Divarci 0:dc5ded118d7c 1697
Sinan Divarci 0:dc5ded118d7c 1698 free(preamb_det);
Sinan Divarci 0:dc5ded118d7c 1699 return this->io_read(data, length);
Sinan Divarci 0:dc5ded118d7c 1700 }
Sinan Divarci 0:dc5ded118d7c 1701
Sinan Divarci 0:dc5ded118d7c 1702 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1703 int MAX4147X<REG>::read_data(uint8_t *data, uint32_t length)
Sinan Divarci 0:dc5ded118d7c 1704 {
Sinan Divarci 0:dc5ded118d7c 1705 if (this->preset_mode == 0) {
Sinan Divarci 0:dc5ded118d7c 1706 if (length > 32767) {
Sinan Divarci 0:dc5ded118d7c 1707 return -100;
Sinan Divarci 0:dc5ded118d7c 1708 }
Sinan Divarci 0:dc5ded118d7c 1709
Sinan Divarci 0:dc5ded118d7c 1710
Sinan Divarci 0:dc5ded118d7c 1711 } else {
Sinan Divarci 0:dc5ded118d7c 1712 this->io_read(data, length);
Sinan Divarci 0:dc5ded118d7c 1713 }
Sinan Divarci 0:dc5ded118d7c 1714
Sinan Divarci 0:dc5ded118d7c 1715 return 0;
Sinan Divarci 0:dc5ded118d7c 1716 }
Sinan Divarci 0:dc5ded118d7c 1717
Sinan Divarci 0:dc5ded118d7c 1718
Sinan Divarci 0:dc5ded118d7c 1719 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1720 int MAX4147X<REG>::io_read(uint8_t *data, uint32_t length)
Sinan Divarci 0:dc5ded118d7c 1721 {
Sinan Divarci 0:dc5ded118d7c 1722 uint32_t byte_idx, bit_idx, bit_val, bit_cnt = 0;
Sinan Divarci 0:dc5ded118d7c 1723 uint32_t signal_period_us, read_period_us, time;
Sinan Divarci 0:dc5ded118d7c 1724 float baud_rate;
Sinan Divarci 0:dc5ded118d7c 1725 Timer *t = NULL;
Sinan Divarci 0:dc5ded118d7c 1726
Sinan Divarci 0:dc5ded118d7c 1727 t = new Timer();
Sinan Divarci 0:dc5ded118d7c 1728 t->start();
Sinan Divarci 0:dc5ded118d7c 1729
Sinan Divarci 0:dc5ded118d7c 1730 baud_rate = this->get_baud_rate();
Sinan Divarci 0:dc5ded118d7c 1731 signal_period_us = 1000000 / baud_rate;
Sinan Divarci 0:dc5ded118d7c 1732 read_period_us = signal_period_us/2;
Sinan Divarci 0:dc5ded118d7c 1733
Sinan Divarci 0:dc5ded118d7c 1734 core_util_critical_section_enter();
Sinan Divarci 0:dc5ded118d7c 1735 t->reset();
Sinan Divarci 0:dc5ded118d7c 1736 for(byte_idx=0; byte_idx<length; byte_idx++)
Sinan Divarci 0:dc5ded118d7c 1737 {
Sinan Divarci 0:dc5ded118d7c 1738 data[byte_idx] = 0;
Sinan Divarci 0:dc5ded118d7c 1739 for(bit_idx=0; bit_idx<8; bit_idx++)
Sinan Divarci 0:dc5ded118d7c 1740 {
Sinan Divarci 0:dc5ded118d7c 1741 while(1)
Sinan Divarci 0:dc5ded118d7c 1742 {
Sinan Divarci 0:dc5ded118d7c 1743 time = t->read_us();
Sinan Divarci 0:dc5ded118d7c 1744 if(byte_idx == 0 && bit_idx == 0)
Sinan Divarci 0:dc5ded118d7c 1745 {
Sinan Divarci 0:dc5ded118d7c 1746 if(time >= read_period_us/2)
Sinan Divarci 0:dc5ded118d7c 1747 {
Sinan Divarci 0:dc5ded118d7c 1748 bit_val = uint8_t(data_read->read());
Sinan Divarci 0:dc5ded118d7c 1749 data[byte_idx] |= bit_val<<bit_idx;
Sinan Divarci 0:dc5ded118d7c 1750 bit_cnt++;
Sinan Divarci 0:dc5ded118d7c 1751 t->reset();
Sinan Divarci 0:dc5ded118d7c 1752 break;
Sinan Divarci 0:dc5ded118d7c 1753 }
Sinan Divarci 0:dc5ded118d7c 1754 continue;
Sinan Divarci 0:dc5ded118d7c 1755 }
Sinan Divarci 0:dc5ded118d7c 1756
Sinan Divarci 0:dc5ded118d7c 1757 if(time >= (read_period_us * bit_cnt))
Sinan Divarci 0:dc5ded118d7c 1758 {
Sinan Divarci 0:dc5ded118d7c 1759 bit_val = uint8_t(data_read->read());
Sinan Divarci 0:dc5ded118d7c 1760 data[byte_idx] |= bit_val<<bit_idx;
Sinan Divarci 0:dc5ded118d7c 1761 bit_cnt++;
Sinan Divarci 0:dc5ded118d7c 1762 break;
Sinan Divarci 0:dc5ded118d7c 1763 }
Sinan Divarci 0:dc5ded118d7c 1764 }
Sinan Divarci 0:dc5ded118d7c 1765 }
Sinan Divarci 0:dc5ded118d7c 1766 }
Sinan Divarci 0:dc5ded118d7c 1767 core_util_critical_section_exit();
Sinan Divarci 0:dc5ded118d7c 1768
Sinan Divarci 0:dc5ded118d7c 1769 t->~Timer();
Sinan Divarci 0:dc5ded118d7c 1770 delete t;
Sinan Divarci 0:dc5ded118d7c 1771 return 0;
Sinan Divarci 0:dc5ded118d7c 1772 }
Sinan Divarci 0:dc5ded118d7c 1773
Sinan Divarci 0:dc5ded118d7c 1774 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1775 int MAX4147X<REG>::adjust_encoding_type(encoding_t encoding_type)
Sinan Divarci 0:dc5ded118d7c 1776 {
Sinan Divarci 0:dc5ded118d7c 1777 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 1778
Sinan Divarci 0:dc5ded118d7c 1779 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 1780 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 1781 return -99;
Sinan Divarci 0:dc5ded118d7c 1782 }
Sinan Divarci 0:dc5ded118d7c 1783
Sinan Divarci 0:dc5ded118d7c 1784 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 1785 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 1786 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1787 }
Sinan Divarci 0:dc5ded118d7c 1788
Sinan Divarci 0:dc5ded118d7c 1789 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 1790 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 1791 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1792 }
Sinan Divarci 0:dc5ded118d7c 1793
Sinan Divarci 0:dc5ded118d7c 1794 encoding = encoding_type;
Sinan Divarci 0:dc5ded118d7c 1795
Sinan Divarci 0:dc5ded118d7c 1796 if(this->update_ath_type() < 0){
Sinan Divarci 0:dc5ded118d7c 1797 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 1798 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1799 }
Sinan Divarci 0:dc5ded118d7c 1800 if(this->update_ath_bw() < 0){
Sinan Divarci 0:dc5ded118d7c 1801 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 1802 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1803 }
Sinan Divarci 0:dc5ded118d7c 1804 if(this->update_ath_dt() < 0){
Sinan Divarci 0:dc5ded118d7c 1805 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 1806 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1807 }
Sinan Divarci 0:dc5ded118d7c 1808 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 1809 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 1810 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1811 }
Sinan Divarci 0:dc5ded118d7c 1812
Sinan Divarci 0:dc5ded118d7c 1813 free_and_return:
Sinan Divarci 0:dc5ded118d7c 1814 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 1815 return return_val;
Sinan Divarci 0:dc5ded118d7c 1816 }
Sinan Divarci 0:dc5ded118d7c 1817
Sinan Divarci 0:dc5ded118d7c 1818 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1819 int MAX4147X<REG>::get_encoding_type()
Sinan Divarci 0:dc5ded118d7c 1820 {
Sinan Divarci 0:dc5ded118d7c 1821 return int(encoding);
Sinan Divarci 0:dc5ded118d7c 1822 }
Sinan Divarci 0:dc5ded118d7c 1823
Sinan Divarci 0:dc5ded118d7c 1824 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1825 int MAX4147X<REG>::adjust_demodulation(ask_fsk_sel_t demodulation_type)
Sinan Divarci 0:dc5ded118d7c 1826 {
Sinan Divarci 0:dc5ded118d7c 1827 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 1828 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 1829
Sinan Divarci 0:dc5ded118d7c 1830 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 1831 return -99;
Sinan Divarci 0:dc5ded118d7c 1832 }
Sinan Divarci 0:dc5ded118d7c 1833
Sinan Divarci 0:dc5ded118d7c 1834 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 1835 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 1836 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1837 }
Sinan Divarci 0:dc5ded118d7c 1838
Sinan Divarci 0:dc5ded118d7c 1839 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 1840 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 1841 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1842 }
Sinan Divarci 0:dc5ded118d7c 1843
Sinan Divarci 0:dc5ded118d7c 1844 this->set_ask_fsk_sel(demodulation_type);
Sinan Divarci 0:dc5ded118d7c 1845
Sinan Divarci 0:dc5ded118d7c 1846 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 1847 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 1848 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1849 }
Sinan Divarci 0:dc5ded118d7c 1850 if(this->update_afc_lg() < 0){
Sinan Divarci 0:dc5ded118d7c 1851 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 1852 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1853 }
Sinan Divarci 0:dc5ded118d7c 1854 if(this->update_agc_threl() < 0){
Sinan Divarci 0:dc5ded118d7c 1855 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 1856 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1857 }
Sinan Divarci 0:dc5ded118d7c 1858
Sinan Divarci 0:dc5ded118d7c 1859 /*Update ASK Bit Fields*/
Sinan Divarci 0:dc5ded118d7c 1860 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 1861 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 1862 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1863 }
Sinan Divarci 0:dc5ded118d7c 1864 if(this->update_afc_mo() < 0){
Sinan Divarci 0:dc5ded118d7c 1865 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 1866 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1867 }
Sinan Divarci 0:dc5ded118d7c 1868 if(this->update_ath_gc() < 0){
Sinan Divarci 0:dc5ded118d7c 1869 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 1870 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1871 }
Sinan Divarci 0:dc5ded118d7c 1872 if(this->update_ath_dt() < 0){
Sinan Divarci 0:dc5ded118d7c 1873 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 1874 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1875 }
Sinan Divarci 0:dc5ded118d7c 1876 if(this->update_ath_bw() < 0){
Sinan Divarci 0:dc5ded118d7c 1877 return_val = -10;
Sinan Divarci 0:dc5ded118d7c 1878 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1879 }
Sinan Divarci 0:dc5ded118d7c 1880 if(this->update_ath_type() < 0){
Sinan Divarci 0:dc5ded118d7c 1881 return_val = -11;
Sinan Divarci 0:dc5ded118d7c 1882 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1883 }
Sinan Divarci 0:dc5ded118d7c 1884 /*End of Update ASK Bit Fields*/
Sinan Divarci 0:dc5ded118d7c 1885
Sinan Divarci 0:dc5ded118d7c 1886 free_and_return:
Sinan Divarci 0:dc5ded118d7c 1887 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 1888 return return_val;
Sinan Divarci 0:dc5ded118d7c 1889 }
Sinan Divarci 0:dc5ded118d7c 1890
Sinan Divarci 0:dc5ded118d7c 1891 template <class REG>
Sinan Divarci 0:dc5ded118d7c 1892 int MAX4147X<REG>::update_ath_lb(void)
Sinan Divarci 0:dc5ded118d7c 1893 {
Sinan Divarci 0:dc5ded118d7c 1894 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 1895 float src_ratio = 0;
Sinan Divarci 0:dc5ded118d7c 1896 uint8_t src_r0 = 0, src_r1= 0, foo = 0;
Sinan Divarci 0:dc5ded118d7c 1897 uint32_t mu_1= 0, mu_2 = 0;
Sinan Divarci 0:dc5ded118d7c 1898 char data = 0;
Sinan Divarci 0:dc5ded118d7c 1899
Sinan Divarci 0:dc5ded118d7c 1900 chf_sel_t *chf_sel = (chf_sel_t *)malloc(sizeof(chf_sel_t));
Sinan Divarci 0:dc5ded118d7c 1901 if(chf_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 1902 return -99;
Sinan Divarci 0:dc5ded118d7c 1903
Sinan Divarci 0:dc5ded118d7c 1904 if_sel_t *if_sel = (if_sel_t *)malloc(sizeof(if_sel_t));
Sinan Divarci 0:dc5ded118d7c 1905 if(if_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 1906 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 1907 return -98;
Sinan Divarci 0:dc5ded118d7c 1908 }
Sinan Divarci 0:dc5ded118d7c 1909
Sinan Divarci 0:dc5ded118d7c 1910 src_lg_t *src_lg = (src_lg_t *)malloc(sizeof(src_lg_t));
Sinan Divarci 0:dc5ded118d7c 1911 if(src_lg == NULL){
Sinan Divarci 0:dc5ded118d7c 1912 free(chf_sel); free(if_sel);
Sinan Divarci 0:dc5ded118d7c 1913 return -97;
Sinan Divarci 0:dc5ded118d7c 1914 }
Sinan Divarci 0:dc5ded118d7c 1915
Sinan Divarci 0:dc5ded118d7c 1916 src_sm_t *src_sm = (src_sm_t *)malloc(sizeof(src_sm_t));
Sinan Divarci 0:dc5ded118d7c 1917 if(src_sm == NULL){
Sinan Divarci 0:dc5ded118d7c 1918 free(chf_sel); free(if_sel); free(src_lg);
Sinan Divarci 0:dc5ded118d7c 1919 return -96;
Sinan Divarci 0:dc5ded118d7c 1920 }
Sinan Divarci 0:dc5ded118d7c 1921
Sinan Divarci 0:dc5ded118d7c 1922 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 1923 if(ask_fsk_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 1924 free(chf_sel); free(if_sel); free(src_lg); free(src_sm);
Sinan Divarci 0:dc5ded118d7c 1925 return -95;
Sinan Divarci 0:dc5ded118d7c 1926 }
Sinan Divarci 0:dc5ded118d7c 1927
Sinan Divarci 0:dc5ded118d7c 1928 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 1929 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 1930 free(chf_sel); free(if_sel); free(src_lg); free(src_sm); free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 1931 return -94;
Sinan Divarci 0:dc5ded118d7c 1932 }
Sinan Divarci 0:dc5ded118d7c 1933
Sinan Divarci 0:dc5ded118d7c 1934 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 1935 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 1936 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1937 }
Sinan Divarci 0:dc5ded118d7c 1938
Sinan Divarci 0:dc5ded118d7c 1939 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 1940 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 1941 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1942 }
Sinan Divarci 0:dc5ded118d7c 1943
Sinan Divarci 0:dc5ded118d7c 1944 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1945 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 1946 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1947 }
Sinan Divarci 0:dc5ded118d7c 1948
Sinan Divarci 0:dc5ded118d7c 1949 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 1950 if(this->set_ath_lb(0) < 0)
Sinan Divarci 0:dc5ded118d7c 1951 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 1952 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1953 }
Sinan Divarci 0:dc5ded118d7c 1954
Sinan Divarci 0:dc5ded118d7c 1955 if(this->get_if_sel(if_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1956 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 1957 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1958 }
Sinan Divarci 0:dc5ded118d7c 1959 if(this->get_chf_sel(chf_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 1960 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 1961 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1962 }
Sinan Divarci 0:dc5ded118d7c 1963 if(this->get_src_sm(src_sm) < 0){
Sinan Divarci 0:dc5ded118d7c 1964 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 1965 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1966 }
Sinan Divarci 0:dc5ded118d7c 1967 if(this->get_src_lg(src_lg) < 0){
Sinan Divarci 0:dc5ded118d7c 1968 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 1969 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 1970 }
Sinan Divarci 0:dc5ded118d7c 1971
Sinan Divarci 0:dc5ded118d7c 1972 src_ratio = *src_lg + log2(*src_sm + 8) - 3;
Sinan Divarci 0:dc5ded118d7c 1973
Sinan Divarci 0:dc5ded118d7c 1974 if(src_ratio < 1.0){
Sinan Divarci 0:dc5ded118d7c 1975 src_r0 = 29; src_r1 = 21;
Sinan Divarci 0:dc5ded118d7c 1976 }
Sinan Divarci 0:dc5ded118d7c 1977 else if (src_ratio < 2){
Sinan Divarci 0:dc5ded118d7c 1978 src_r0 = 21; src_r1 = 15;
Sinan Divarci 0:dc5ded118d7c 1979 }
Sinan Divarci 0:dc5ded118d7c 1980 else if (src_ratio < 3){
Sinan Divarci 0:dc5ded118d7c 1981 src_r0 = 15; src_r1 = 11;
Sinan Divarci 0:dc5ded118d7c 1982 }
Sinan Divarci 0:dc5ded118d7c 1983 else if (src_ratio < 4){
Sinan Divarci 0:dc5ded118d7c 1984 src_r0 = 11; src_r1 = 8;
Sinan Divarci 0:dc5ded118d7c 1985 }
Sinan Divarci 0:dc5ded118d7c 1986 else if (src_ratio < 5){
Sinan Divarci 0:dc5ded118d7c 1987 src_r0 = 8; src_r1 = 6;
Sinan Divarci 0:dc5ded118d7c 1988 }
Sinan Divarci 0:dc5ded118d7c 1989 else if (src_ratio < 6){
Sinan Divarci 0:dc5ded118d7c 1990 src_r0 = 6; src_r1 = 4;
Sinan Divarci 0:dc5ded118d7c 1991 }
Sinan Divarci 0:dc5ded118d7c 1992 else if (src_ratio < 7){
Sinan Divarci 0:dc5ded118d7c 1993 src_r0 = 4; src_r1 = 3;
Sinan Divarci 0:dc5ded118d7c 1994 }
Sinan Divarci 0:dc5ded118d7c 1995 else if (src_ratio < 8){
Sinan Divarci 0:dc5ded118d7c 1996 src_r0 = 3; src_r1 = 2;
Sinan Divarci 0:dc5ded118d7c 1997 }
Sinan Divarci 0:dc5ded118d7c 1998 else {
Sinan Divarci 0:dc5ded118d7c 1999 src_r0 = 2; src_r1 = 2;
Sinan Divarci 0:dc5ded118d7c 2000 }
Sinan Divarci 0:dc5ded118d7c 2001
Sinan Divarci 0:dc5ded118d7c 2002 mu_1 = mu1_conf[(*if_sel) * 5 + *chf_sel];
Sinan Divarci 0:dc5ded118d7c 2003 mu_2 = (int)round(src_r0 - ((src_r0 - src_r1) * (src_ratio - floor(src_ratio))));
Sinan Divarci 0:dc5ded118d7c 2004
Sinan Divarci 0:dc5ded118d7c 2005 data = (char)(mu_1 + mu_2 - 6);
Sinan Divarci 0:dc5ded118d7c 2006 foo = (uint8_t)(data + 256);
Sinan Divarci 0:dc5ded118d7c 2007
Sinan Divarci 0:dc5ded118d7c 2008 if(this->set_ath_lb(foo) < 0)
Sinan Divarci 0:dc5ded118d7c 2009 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 2010
Sinan Divarci 0:dc5ded118d7c 2011
Sinan Divarci 0:dc5ded118d7c 2012 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2013 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2014 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2015 free(src_lg);
Sinan Divarci 0:dc5ded118d7c 2016 free(src_sm);
Sinan Divarci 0:dc5ded118d7c 2017 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2018 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2019 return return_val;
Sinan Divarci 0:dc5ded118d7c 2020 }
Sinan Divarci 0:dc5ded118d7c 2021
Sinan Divarci 0:dc5ded118d7c 2022 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2023 int MAX4147X<REG>::update_ath_type(void)
Sinan Divarci 0:dc5ded118d7c 2024 {
Sinan Divarci 0:dc5ded118d7c 2025 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2026
Sinan Divarci 0:dc5ded118d7c 2027 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2028 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2029 return -99;
Sinan Divarci 0:dc5ded118d7c 2030
Sinan Divarci 0:dc5ded118d7c 2031 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2032 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2033 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2034 return -98;
Sinan Divarci 0:dc5ded118d7c 2035 }
Sinan Divarci 0:dc5ded118d7c 2036
Sinan Divarci 0:dc5ded118d7c 2037 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2038 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2039 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2040 }
Sinan Divarci 0:dc5ded118d7c 2041
Sinan Divarci 0:dc5ded118d7c 2042 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2043 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2044 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2045 }
Sinan Divarci 0:dc5ded118d7c 2046
Sinan Divarci 0:dc5ded118d7c 2047 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2048 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2049 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2050 }
Sinan Divarci 0:dc5ded118d7c 2051
Sinan Divarci 0:dc5ded118d7c 2052 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2053 if(this->set_ath_type(ATH_TYPE_PRELPF_MANCHESTER) < 0){
Sinan Divarci 0:dc5ded118d7c 2054 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2055 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2056 }
Sinan Divarci 0:dc5ded118d7c 2057 }
Sinan Divarci 0:dc5ded118d7c 2058 else{
Sinan Divarci 0:dc5ded118d7c 2059 if(encoding == Manchester){
Sinan Divarci 0:dc5ded118d7c 2060 if(this->set_ath_type(ATH_TYPE_PRELPF_MANCHESTER) < 0){
Sinan Divarci 0:dc5ded118d7c 2061 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2062 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2063 }
Sinan Divarci 0:dc5ded118d7c 2064 }else{
Sinan Divarci 0:dc5ded118d7c 2065 if(this->set_ath_type(ATH_TYPE_APD_NRZ) < 0){
Sinan Divarci 0:dc5ded118d7c 2066 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2067 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2068 }
Sinan Divarci 0:dc5ded118d7c 2069 }
Sinan Divarci 0:dc5ded118d7c 2070 }
Sinan Divarci 0:dc5ded118d7c 2071
Sinan Divarci 0:dc5ded118d7c 2072 if(this->update_demod_tctrl() < 0)
Sinan Divarci 0:dc5ded118d7c 2073 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2074
Sinan Divarci 0:dc5ded118d7c 2075 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2076 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2077 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2078 return return_val;
Sinan Divarci 0:dc5ded118d7c 2079 }
Sinan Divarci 0:dc5ded118d7c 2080
Sinan Divarci 0:dc5ded118d7c 2081 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2082 int MAX4147X<REG>::update_ath_bw(void)
Sinan Divarci 0:dc5ded118d7c 2083 {
Sinan Divarci 0:dc5ded118d7c 2084 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2085
Sinan Divarci 0:dc5ded118d7c 2086 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2087 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2088 return -99;
Sinan Divarci 0:dc5ded118d7c 2089
Sinan Divarci 0:dc5ded118d7c 2090 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2091 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2092 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2093 return -98;
Sinan Divarci 0:dc5ded118d7c 2094 }
Sinan Divarci 0:dc5ded118d7c 2095
Sinan Divarci 0:dc5ded118d7c 2096 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2097 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2098 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2099 }
Sinan Divarci 0:dc5ded118d7c 2100
Sinan Divarci 0:dc5ded118d7c 2101 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2102 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2103 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2104 }
Sinan Divarci 0:dc5ded118d7c 2105
Sinan Divarci 0:dc5ded118d7c 2106 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2107 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2108 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2109 }
Sinan Divarci 0:dc5ded118d7c 2110
Sinan Divarci 0:dc5ded118d7c 2111 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2112 if(this->set_ath_bw(ATH_BW_DEFAULT) < 0)
Sinan Divarci 0:dc5ded118d7c 2113 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2114 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2115 }
Sinan Divarci 0:dc5ded118d7c 2116
Sinan Divarci 0:dc5ded118d7c 2117 if(encoding == Manchester){
Sinan Divarci 0:dc5ded118d7c 2118 if(baud_rate_ratio < 0.6){
Sinan Divarci 0:dc5ded118d7c 2119 if(this->set_ath_bw(ATH_BW_DEFAULT_X2) < 0)
Sinan Divarci 0:dc5ded118d7c 2120 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2121 }else{
Sinan Divarci 0:dc5ded118d7c 2122 if(this->set_ath_bw(ATH_BW_DEFAULT) < 0)
Sinan Divarci 0:dc5ded118d7c 2123 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2124 }
Sinan Divarci 0:dc5ded118d7c 2125 }else{
Sinan Divarci 0:dc5ded118d7c 2126 if(this->set_ath_bw(ATH_BW_DEFAULT) < 0)
Sinan Divarci 0:dc5ded118d7c 2127 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2128 }
Sinan Divarci 0:dc5ded118d7c 2129
Sinan Divarci 0:dc5ded118d7c 2130 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2131 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2132 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2133 return return_val;
Sinan Divarci 0:dc5ded118d7c 2134 }
Sinan Divarci 0:dc5ded118d7c 2135
Sinan Divarci 0:dc5ded118d7c 2136 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2137 int MAX4147X<REG>::update_ath_dt(void)
Sinan Divarci 0:dc5ded118d7c 2138 {
Sinan Divarci 0:dc5ded118d7c 2139 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2140
Sinan Divarci 0:dc5ded118d7c 2141 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2142 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2143 return -99;
Sinan Divarci 0:dc5ded118d7c 2144
Sinan Divarci 0:dc5ded118d7c 2145 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2146 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2147 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2148 return -98;
Sinan Divarci 0:dc5ded118d7c 2149 }
Sinan Divarci 0:dc5ded118d7c 2150
Sinan Divarci 0:dc5ded118d7c 2151 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2152 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2153 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2154 }
Sinan Divarci 0:dc5ded118d7c 2155
Sinan Divarci 0:dc5ded118d7c 2156 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2157 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2158 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2159 }
Sinan Divarci 0:dc5ded118d7c 2160
Sinan Divarci 0:dc5ded118d7c 2161 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2162 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2163 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2164 }
Sinan Divarci 0:dc5ded118d7c 2165
Sinan Divarci 0:dc5ded118d7c 2166 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2167 if(this->set_ath_dt(ATH_DT_DEFAULT_DISCHARGE_TIME) < 0)
Sinan Divarci 0:dc5ded118d7c 2168 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2169 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2170 }
Sinan Divarci 0:dc5ded118d7c 2171
Sinan Divarci 0:dc5ded118d7c 2172 if(encoding == Manchester){
Sinan Divarci 0:dc5ded118d7c 2173 if(baud_rate_ratio < 0.6){
Sinan Divarci 0:dc5ded118d7c 2174 if(this->set_ath_dt(ATH_DT_DISCHARGE_TIME_X2) < 0)
Sinan Divarci 0:dc5ded118d7c 2175 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2176 }else{
Sinan Divarci 0:dc5ded118d7c 2177 if(this->set_ath_dt(ATH_DT_DEFAULT_DISCHARGE_TIME) < 0)
Sinan Divarci 0:dc5ded118d7c 2178 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2179 }
Sinan Divarci 0:dc5ded118d7c 2180 }else{
Sinan Divarci 0:dc5ded118d7c 2181 if(this->set_ath_dt(ATH_DT_DISCHARGE_TIME_X8) < 0)
Sinan Divarci 0:dc5ded118d7c 2182 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2183 }
Sinan Divarci 0:dc5ded118d7c 2184
Sinan Divarci 0:dc5ded118d7c 2185 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2186 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2187 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2188 return return_val;
Sinan Divarci 0:dc5ded118d7c 2189 }
Sinan Divarci 0:dc5ded118d7c 2190
Sinan Divarci 0:dc5ded118d7c 2191 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2192 int MAX4147X<REG>::update_ath_tc(void)
Sinan Divarci 0:dc5ded118d7c 2193 {
Sinan Divarci 0:dc5ded118d7c 2194 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2195
Sinan Divarci 0:dc5ded118d7c 2196 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2197 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2198 return -99;
Sinan Divarci 0:dc5ded118d7c 2199
Sinan Divarci 0:dc5ded118d7c 2200 src_lg_t *src_lg = (src_lg_t *)malloc(sizeof(src_lg_t));
Sinan Divarci 0:dc5ded118d7c 2201 if(src_lg == NULL){
Sinan Divarci 0:dc5ded118d7c 2202 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2203 return -98;
Sinan Divarci 0:dc5ded118d7c 2204 }
Sinan Divarci 0:dc5ded118d7c 2205
Sinan Divarci 0:dc5ded118d7c 2206 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2207 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2208 free(ask_fsk_sel); free(src_lg);
Sinan Divarci 0:dc5ded118d7c 2209 return -97;
Sinan Divarci 0:dc5ded118d7c 2210 }
Sinan Divarci 0:dc5ded118d7c 2211
Sinan Divarci 0:dc5ded118d7c 2212 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2213 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2214 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2215 }
Sinan Divarci 0:dc5ded118d7c 2216
Sinan Divarci 0:dc5ded118d7c 2217 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2218 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2219 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2220 }
Sinan Divarci 0:dc5ded118d7c 2221
Sinan Divarci 0:dc5ded118d7c 2222 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2223 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2224 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2225 }
Sinan Divarci 0:dc5ded118d7c 2226
Sinan Divarci 0:dc5ded118d7c 2227 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2228 if(this->set_ath_tc(0) < 0)
Sinan Divarci 0:dc5ded118d7c 2229 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2230 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2231 }
Sinan Divarci 0:dc5ded118d7c 2232
Sinan Divarci 0:dc5ded118d7c 2233 if(this->get_src_lg(src_lg) < 0){
Sinan Divarci 0:dc5ded118d7c 2234 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2235 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2236 }
Sinan Divarci 0:dc5ded118d7c 2237
Sinan Divarci 0:dc5ded118d7c 2238 if(*src_lg > 7){
Sinan Divarci 0:dc5ded118d7c 2239 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2240 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2241 }
Sinan Divarci 0:dc5ded118d7c 2242
Sinan Divarci 0:dc5ded118d7c 2243 if(this->set_ath_tc(ath_tc_conf[*src_lg]) < 0){
Sinan Divarci 0:dc5ded118d7c 2244 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2245 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2246 }
Sinan Divarci 0:dc5ded118d7c 2247
Sinan Divarci 0:dc5ded118d7c 2248 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2249 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2250 free(src_lg);
Sinan Divarci 0:dc5ded118d7c 2251 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2252 return return_val;
Sinan Divarci 0:dc5ded118d7c 2253 }
Sinan Divarci 0:dc5ded118d7c 2254
Sinan Divarci 0:dc5ded118d7c 2255 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2256 int MAX4147X<REG>::update_ath_gc(void)
Sinan Divarci 0:dc5ded118d7c 2257 {
Sinan Divarci 0:dc5ded118d7c 2258 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2259
Sinan Divarci 0:dc5ded118d7c 2260 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2261 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2262 return -99;
Sinan Divarci 0:dc5ded118d7c 2263
Sinan Divarci 0:dc5ded118d7c 2264 chf_sel_t *chf_sel = (chf_sel_t *)malloc(sizeof(chf_sel_t));
Sinan Divarci 0:dc5ded118d7c 2265 if(chf_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 2266 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2267 return -98;
Sinan Divarci 0:dc5ded118d7c 2268 }
Sinan Divarci 0:dc5ded118d7c 2269
Sinan Divarci 0:dc5ded118d7c 2270 if_sel_t *if_sel = (if_sel_t *)malloc(sizeof(if_sel_t));
Sinan Divarci 0:dc5ded118d7c 2271 if(if_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 2272 free(ask_fsk_sel); free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2273 return -97;
Sinan Divarci 0:dc5ded118d7c 2274 }
Sinan Divarci 0:dc5ded118d7c 2275
Sinan Divarci 0:dc5ded118d7c 2276 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2277 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2278 free(ask_fsk_sel); free(chf_sel); free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2279 return -96;
Sinan Divarci 0:dc5ded118d7c 2280 }
Sinan Divarci 0:dc5ded118d7c 2281
Sinan Divarci 0:dc5ded118d7c 2282 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2283 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2284 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2285 }
Sinan Divarci 0:dc5ded118d7c 2286
Sinan Divarci 0:dc5ded118d7c 2287 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2288 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2289 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2290 }
Sinan Divarci 0:dc5ded118d7c 2291
Sinan Divarci 0:dc5ded118d7c 2292 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2293 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2294 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2295 }
Sinan Divarci 0:dc5ded118d7c 2296
Sinan Divarci 0:dc5ded118d7c 2297 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2298 if(this->set_ath_gc(0) < 0)
Sinan Divarci 0:dc5ded118d7c 2299 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2300 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2301 }
Sinan Divarci 0:dc5ded118d7c 2302
Sinan Divarci 0:dc5ded118d7c 2303 if(this->get_if_sel(if_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2304 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2305 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2306 }
Sinan Divarci 0:dc5ded118d7c 2307
Sinan Divarci 0:dc5ded118d7c 2308 if(this->get_chf_sel(chf_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2309 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2310 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2311 }
Sinan Divarci 0:dc5ded118d7c 2312
Sinan Divarci 0:dc5ded118d7c 2313 if(this->set_ath_gc(ath_gc_conf[(*if_sel) * 5 + *chf_sel]) < 0){
Sinan Divarci 0:dc5ded118d7c 2314 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2315 goto free_and_return;
Sinan Divarci 0:dc5ded118d7c 2316 }
Sinan Divarci 0:dc5ded118d7c 2317
Sinan Divarci 0:dc5ded118d7c 2318 free_and_return:
Sinan Divarci 0:dc5ded118d7c 2319 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2320 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2321 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2322 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2323 return return_val;
Sinan Divarci 0:dc5ded118d7c 2324 }
Sinan Divarci 0:dc5ded118d7c 2325
Sinan Divarci 0:dc5ded118d7c 2326 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2327 int MAX4147X<REG>::update_afc_mo(void)
Sinan Divarci 0:dc5ded118d7c 2328 {
Sinan Divarci 0:dc5ded118d7c 2329 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2330
Sinan Divarci 0:dc5ded118d7c 2331 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2332 return -99;
Sinan Divarci 0:dc5ded118d7c 2333 }
Sinan Divarci 0:dc5ded118d7c 2334
Sinan Divarci 0:dc5ded118d7c 2335 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2336 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2337 return -1;
Sinan Divarci 0:dc5ded118d7c 2338 }
Sinan Divarci 0:dc5ded118d7c 2339
Sinan Divarci 0:dc5ded118d7c 2340 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2341 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2342 return -2;
Sinan Divarci 0:dc5ded118d7c 2343 }
Sinan Divarci 0:dc5ded118d7c 2344
Sinan Divarci 0:dc5ded118d7c 2345 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2346
Sinan Divarci 0:dc5ded118d7c 2347 return (this->set_afc_mo(AFC_MO_CONF_7) < 0) ? -3 : 0;
Sinan Divarci 0:dc5ded118d7c 2348 }
Sinan Divarci 0:dc5ded118d7c 2349
Sinan Divarci 0:dc5ded118d7c 2350 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2351 int MAX4147X<REG>::update_afc_lg(void)
Sinan Divarci 0:dc5ded118d7c 2352 {
Sinan Divarci 0:dc5ded118d7c 2353 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2354
Sinan Divarci 0:dc5ded118d7c 2355 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2356 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2357 return -99;
Sinan Divarci 0:dc5ded118d7c 2358
Sinan Divarci 0:dc5ded118d7c 2359 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2360 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2361 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2362 return -98;
Sinan Divarci 0:dc5ded118d7c 2363 }
Sinan Divarci 0:dc5ded118d7c 2364
Sinan Divarci 0:dc5ded118d7c 2365 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2366 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2367 goto error;
Sinan Divarci 0:dc5ded118d7c 2368 }
Sinan Divarci 0:dc5ded118d7c 2369
Sinan Divarci 0:dc5ded118d7c 2370 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2371 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2372 goto error;
Sinan Divarci 0:dc5ded118d7c 2373 }
Sinan Divarci 0:dc5ded118d7c 2374
Sinan Divarci 0:dc5ded118d7c 2375 if(this->get_ask_fsk_sel(ask_fsk_sel)){
Sinan Divarci 0:dc5ded118d7c 2376 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2377 goto error;
Sinan Divarci 0:dc5ded118d7c 2378 }
Sinan Divarci 0:dc5ded118d7c 2379
Sinan Divarci 0:dc5ded118d7c 2380 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2381 if(this->set_afc_lg(AFC_LG_CONF_DEFAULT) < 0){
Sinan Divarci 0:dc5ded118d7c 2382 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2383 goto error;
Sinan Divarci 0:dc5ded118d7c 2384 }
Sinan Divarci 0:dc5ded118d7c 2385 }else{
Sinan Divarci 0:dc5ded118d7c 2386 if(this->set_afc_lg(AFC_LG_CONF_DEFAULT_X2) < 0){
Sinan Divarci 0:dc5ded118d7c 2387 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2388 goto error;
Sinan Divarci 0:dc5ded118d7c 2389 }
Sinan Divarci 0:dc5ded118d7c 2390 }
Sinan Divarci 0:dc5ded118d7c 2391
Sinan Divarci 0:dc5ded118d7c 2392 error:
Sinan Divarci 0:dc5ded118d7c 2393 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2394 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2395 return return_val;
Sinan Divarci 0:dc5ded118d7c 2396 }
Sinan Divarci 0:dc5ded118d7c 2397
Sinan Divarci 0:dc5ded118d7c 2398 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2399 int MAX4147X<REG>::update_agc_threl(void)
Sinan Divarci 0:dc5ded118d7c 2400 {
Sinan Divarci 0:dc5ded118d7c 2401 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2402 float bit_rate;
Sinan Divarci 0:dc5ded118d7c 2403
Sinan Divarci 0:dc5ded118d7c 2404 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2405 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2406 return -99;
Sinan Divarci 0:dc5ded118d7c 2407
Sinan Divarci 0:dc5ded118d7c 2408 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2409 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2410 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2411 return -98;
Sinan Divarci 0:dc5ded118d7c 2412 }
Sinan Divarci 0:dc5ded118d7c 2413
Sinan Divarci 0:dc5ded118d7c 2414 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2415 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2416 goto error;
Sinan Divarci 0:dc5ded118d7c 2417 }
Sinan Divarci 0:dc5ded118d7c 2418
Sinan Divarci 0:dc5ded118d7c 2419 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2420 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2421 goto error;
Sinan Divarci 0:dc5ded118d7c 2422 }
Sinan Divarci 0:dc5ded118d7c 2423
Sinan Divarci 0:dc5ded118d7c 2424 if(encoding == Manchester)
Sinan Divarci 0:dc5ded118d7c 2425 bit_rate = this->baud_rate * 2;
Sinan Divarci 0:dc5ded118d7c 2426 else
Sinan Divarci 0:dc5ded118d7c 2427 bit_rate = this->baud_rate;
Sinan Divarci 0:dc5ded118d7c 2428
Sinan Divarci 0:dc5ded118d7c 2429 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2430 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2431 goto error;
Sinan Divarci 0:dc5ded118d7c 2432 }
Sinan Divarci 0:dc5ded118d7c 2433
Sinan Divarci 0:dc5ded118d7c 2434 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2435 if(bit_rate > 51.5){
Sinan Divarci 0:dc5ded118d7c 2436 if(this->set_agc_threl(0x0F) < 0){
Sinan Divarci 0:dc5ded118d7c 2437 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2438 goto error;
Sinan Divarci 0:dc5ded118d7c 2439 }
Sinan Divarci 0:dc5ded118d7c 2440 }else{
Sinan Divarci 0:dc5ded118d7c 2441 if(this->set_agc_threl(0x09) < 0){
Sinan Divarci 0:dc5ded118d7c 2442 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2443 goto error;
Sinan Divarci 0:dc5ded118d7c 2444 }
Sinan Divarci 0:dc5ded118d7c 2445 }
Sinan Divarci 0:dc5ded118d7c 2446 }
Sinan Divarci 0:dc5ded118d7c 2447 else{
Sinan Divarci 0:dc5ded118d7c 2448 if(bit_rate > 26){
Sinan Divarci 0:dc5ded118d7c 2449 if(this->set_agc_threl(0x0F) < 0){
Sinan Divarci 0:dc5ded118d7c 2450 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2451 goto error;
Sinan Divarci 0:dc5ded118d7c 2452 }
Sinan Divarci 0:dc5ded118d7c 2453 }else{
Sinan Divarci 0:dc5ded118d7c 2454 if(this->set_agc_threl(0x09) < 0){
Sinan Divarci 0:dc5ded118d7c 2455 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2456 goto error;
Sinan Divarci 0:dc5ded118d7c 2457 }
Sinan Divarci 0:dc5ded118d7c 2458 }
Sinan Divarci 0:dc5ded118d7c 2459 }
Sinan Divarci 0:dc5ded118d7c 2460
Sinan Divarci 0:dc5ded118d7c 2461 error:
Sinan Divarci 0:dc5ded118d7c 2462 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2463 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2464 return return_val;
Sinan Divarci 0:dc5ded118d7c 2465 }
Sinan Divarci 0:dc5ded118d7c 2466
Sinan Divarci 0:dc5ded118d7c 2467 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2468 int MAX4147X<REG>::update_demod_tctrl(void)
Sinan Divarci 0:dc5ded118d7c 2469 {
Sinan Divarci 0:dc5ded118d7c 2470 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2471
Sinan Divarci 0:dc5ded118d7c 2472 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2473 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2474 return -99;
Sinan Divarci 0:dc5ded118d7c 2475
Sinan Divarci 0:dc5ded118d7c 2476 src_lg_t *src_lg = (src_lg_t *)malloc(sizeof(src_lg_t));
Sinan Divarci 0:dc5ded118d7c 2477 if(src_lg == NULL){
Sinan Divarci 0:dc5ded118d7c 2478 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2479 return -98;
Sinan Divarci 0:dc5ded118d7c 2480 }
Sinan Divarci 0:dc5ded118d7c 2481
Sinan Divarci 0:dc5ded118d7c 2482 chf_sel_t *chf_sel = (chf_sel_t *)malloc(sizeof(chf_sel_t));
Sinan Divarci 0:dc5ded118d7c 2483 if(chf_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 2484 free(ask_fsk_sel); free(src_lg);
Sinan Divarci 0:dc5ded118d7c 2485 return -97;
Sinan Divarci 0:dc5ded118d7c 2486 }
Sinan Divarci 0:dc5ded118d7c 2487
Sinan Divarci 0:dc5ded118d7c 2488 ath_type_t *ath_type = (ath_type_t *)malloc(sizeof(ath_type_t));
Sinan Divarci 0:dc5ded118d7c 2489 if(ath_type == NULL){
Sinan Divarci 0:dc5ded118d7c 2490 free(ask_fsk_sel); free(src_lg); free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2491 return -96;
Sinan Divarci 0:dc5ded118d7c 2492 }
Sinan Divarci 0:dc5ded118d7c 2493
Sinan Divarci 0:dc5ded118d7c 2494 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2495 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2496 free(ask_fsk_sel); free(src_lg); free(chf_sel); free(ath_type);
Sinan Divarci 0:dc5ded118d7c 2497 return -95;
Sinan Divarci 0:dc5ded118d7c 2498 }
Sinan Divarci 0:dc5ded118d7c 2499
Sinan Divarci 0:dc5ded118d7c 2500 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2501 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2502 goto error;
Sinan Divarci 0:dc5ded118d7c 2503 }
Sinan Divarci 0:dc5ded118d7c 2504
Sinan Divarci 0:dc5ded118d7c 2505 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2506 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2507 goto error;
Sinan Divarci 0:dc5ded118d7c 2508 }
Sinan Divarci 0:dc5ded118d7c 2509
Sinan Divarci 0:dc5ded118d7c 2510 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2511 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2512 goto error;
Sinan Divarci 0:dc5ded118d7c 2513 }
Sinan Divarci 0:dc5ded118d7c 2514
Sinan Divarci 0:dc5ded118d7c 2515 if(*ask_fsk_sel == ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2516 if(this->get_chf_sel(chf_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2517 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2518 goto error;
Sinan Divarci 0:dc5ded118d7c 2519 }
Sinan Divarci 0:dc5ded118d7c 2520 set_demod_tctrl(demod_tctrl_t(4 - *chf_sel));
Sinan Divarci 0:dc5ded118d7c 2521 }
Sinan Divarci 0:dc5ded118d7c 2522 else{
Sinan Divarci 0:dc5ded118d7c 2523 if(this->get_ath_type(ath_type) < 0){
Sinan Divarci 0:dc5ded118d7c 2524 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2525 goto error;
Sinan Divarci 0:dc5ded118d7c 2526 }
Sinan Divarci 0:dc5ded118d7c 2527 if(this->get_src_lg(src_lg) < 0){
Sinan Divarci 0:dc5ded118d7c 2528 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2529 goto error;
Sinan Divarci 0:dc5ded118d7c 2530 }
Sinan Divarci 0:dc5ded118d7c 2531 if(*ath_type == ATH_TYPE_PRELPF_MANCHESTER){
Sinan Divarci 0:dc5ded118d7c 2532 if(2 + *src_lg < 7)
Sinan Divarci 0:dc5ded118d7c 2533 set_demod_tctrl(demod_tctrl_t(2 + *src_lg));
Sinan Divarci 0:dc5ded118d7c 2534 else
Sinan Divarci 0:dc5ded118d7c 2535 set_demod_tctrl(demod_tctrl_t(7));
Sinan Divarci 0:dc5ded118d7c 2536 }
Sinan Divarci 0:dc5ded118d7c 2537 else{
Sinan Divarci 0:dc5ded118d7c 2538 if(3 + *src_lg < 7)
Sinan Divarci 0:dc5ded118d7c 2539 set_demod_tctrl(demod_tctrl_t(3 + *src_lg));
Sinan Divarci 0:dc5ded118d7c 2540 else
Sinan Divarci 0:dc5ded118d7c 2541 set_demod_tctrl(demod_tctrl_t(7));
Sinan Divarci 0:dc5ded118d7c 2542 }
Sinan Divarci 0:dc5ded118d7c 2543 }
Sinan Divarci 0:dc5ded118d7c 2544
Sinan Divarci 0:dc5ded118d7c 2545 error:
Sinan Divarci 0:dc5ded118d7c 2546 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2547 free(src_lg);
Sinan Divarci 0:dc5ded118d7c 2548 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2549 free(ath_type);
Sinan Divarci 0:dc5ded118d7c 2550 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2551 return return_val;
Sinan Divarci 0:dc5ded118d7c 2552 }
Sinan Divarci 0:dc5ded118d7c 2553
Sinan Divarci 0:dc5ded118d7c 2554 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2555 int MAX4147X<REG>::adjust_receiver_bandwidth(int receiver_bw)
Sinan Divarci 0:dc5ded118d7c 2556 {
Sinan Divarci 0:dc5ded118d7c 2557 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2558
Sinan Divarci 0:dc5ded118d7c 2559 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2560 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2561 return -99;
Sinan Divarci 0:dc5ded118d7c 2562
Sinan Divarci 0:dc5ded118d7c 2563 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2564 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2565 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2566 return -98;
Sinan Divarci 0:dc5ded118d7c 2567 }
Sinan Divarci 0:dc5ded118d7c 2568
Sinan Divarci 0:dc5ded118d7c 2569 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2570 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2571 goto error;
Sinan Divarci 0:dc5ded118d7c 2572 }
Sinan Divarci 0:dc5ded118d7c 2573
Sinan Divarci 0:dc5ded118d7c 2574 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2575 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2576 goto error;
Sinan Divarci 0:dc5ded118d7c 2577 }
Sinan Divarci 0:dc5ded118d7c 2578
Sinan Divarci 0:dc5ded118d7c 2579 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2580 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2581 goto error;
Sinan Divarci 0:dc5ded118d7c 2582 }
Sinan Divarci 0:dc5ded118d7c 2583
Sinan Divarci 0:dc5ded118d7c 2584 if(*ask_fsk_sel != ASK_FSK_SEL_ASK){
Sinan Divarci 0:dc5ded118d7c 2585 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2586 goto error;
Sinan Divarci 0:dc5ded118d7c 2587 }
Sinan Divarci 0:dc5ded118d7c 2588
Sinan Divarci 0:dc5ded118d7c 2589 if(receiver_bw == 340 || receiver_bw == 170)
Sinan Divarci 0:dc5ded118d7c 2590 set_chf_sel(CHF_SEL_RXBW_340_170_KHZ);
Sinan Divarci 0:dc5ded118d7c 2591 else if(receiver_bw == 120 || receiver_bw == 60)
Sinan Divarci 0:dc5ded118d7c 2592 set_chf_sel(CHF_SEL_RXBW_120_60_KHZ);
Sinan Divarci 0:dc5ded118d7c 2593 else if(receiver_bw == 52 || receiver_bw == 26)
Sinan Divarci 0:dc5ded118d7c 2594 set_chf_sel(CHF_SEL_RXBW_52_26_KHZ);
Sinan Divarci 0:dc5ded118d7c 2595 else if(receiver_bw == 24 || receiver_bw == 12)
Sinan Divarci 0:dc5ded118d7c 2596 set_chf_sel(CHF_SEL_RXBW_24_12_KHZ);
Sinan Divarci 0:dc5ded118d7c 2597 else if(receiver_bw == 12 || receiver_bw == 6)
Sinan Divarci 0:dc5ded118d7c 2598 set_chf_sel(CHF_SEL_RXBW_12_6_KHZ);
Sinan Divarci 0:dc5ded118d7c 2599 else{
Sinan Divarci 0:dc5ded118d7c 2600 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2601 goto error;
Sinan Divarci 0:dc5ded118d7c 2602 }
Sinan Divarci 0:dc5ded118d7c 2603
Sinan Divarci 0:dc5ded118d7c 2604 if(this->adjust_baud_rate(this->baud_rate) < 0){
Sinan Divarci 0:dc5ded118d7c 2605 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2606 goto error;
Sinan Divarci 0:dc5ded118d7c 2607 }
Sinan Divarci 0:dc5ded118d7c 2608 if(this->update_ath_gc() < 0){
Sinan Divarci 0:dc5ded118d7c 2609 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2610 goto error;
Sinan Divarci 0:dc5ded118d7c 2611 }
Sinan Divarci 0:dc5ded118d7c 2612 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 2613 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 2614 goto error;
Sinan Divarci 0:dc5ded118d7c 2615 }
Sinan Divarci 0:dc5ded118d7c 2616 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 2617 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 2618 goto error;
Sinan Divarci 0:dc5ded118d7c 2619 }
Sinan Divarci 0:dc5ded118d7c 2620
Sinan Divarci 0:dc5ded118d7c 2621 error:
Sinan Divarci 0:dc5ded118d7c 2622 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2623 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2624 return return_val;
Sinan Divarci 0:dc5ded118d7c 2625 }
Sinan Divarci 0:dc5ded118d7c 2626
Sinan Divarci 0:dc5ded118d7c 2627 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2628 int MAX4147X<REG>::adjust_receiver_bandwidth(int receiver_bw, float deviation)
Sinan Divarci 0:dc5ded118d7c 2629 {
Sinan Divarci 0:dc5ded118d7c 2630 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2631
Sinan Divarci 0:dc5ded118d7c 2632 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2633 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2634 return -99;
Sinan Divarci 0:dc5ded118d7c 2635
Sinan Divarci 0:dc5ded118d7c 2636 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2637 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2638 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2639 return -98;
Sinan Divarci 0:dc5ded118d7c 2640 }
Sinan Divarci 0:dc5ded118d7c 2641
Sinan Divarci 0:dc5ded118d7c 2642 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2643 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2644 goto error;
Sinan Divarci 0:dc5ded118d7c 2645 }
Sinan Divarci 0:dc5ded118d7c 2646
Sinan Divarci 0:dc5ded118d7c 2647 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2648 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2649 goto error;
Sinan Divarci 0:dc5ded118d7c 2650 }
Sinan Divarci 0:dc5ded118d7c 2651
Sinan Divarci 0:dc5ded118d7c 2652 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2653 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2654 goto error;
Sinan Divarci 0:dc5ded118d7c 2655 }
Sinan Divarci 0:dc5ded118d7c 2656
Sinan Divarci 0:dc5ded118d7c 2657 if(*ask_fsk_sel != ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2658 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2659 goto error;
Sinan Divarci 0:dc5ded118d7c 2660 }
Sinan Divarci 0:dc5ded118d7c 2661
Sinan Divarci 0:dc5ded118d7c 2662 if(receiver_bw == 340 || receiver_bw == 170)
Sinan Divarci 0:dc5ded118d7c 2663 set_chf_sel(CHF_SEL_RXBW_340_170_KHZ);
Sinan Divarci 0:dc5ded118d7c 2664 else if(receiver_bw == 120 || receiver_bw == 60)
Sinan Divarci 0:dc5ded118d7c 2665 set_chf_sel(CHF_SEL_RXBW_120_60_KHZ);
Sinan Divarci 0:dc5ded118d7c 2666 else if(receiver_bw == 52 || receiver_bw == 26)
Sinan Divarci 0:dc5ded118d7c 2667 set_chf_sel(CHF_SEL_RXBW_52_26_KHZ);
Sinan Divarci 0:dc5ded118d7c 2668 else if(receiver_bw == 24 || receiver_bw == 12)
Sinan Divarci 0:dc5ded118d7c 2669 set_chf_sel(CHF_SEL_RXBW_24_12_KHZ);
Sinan Divarci 0:dc5ded118d7c 2670 else if(receiver_bw == 12 || receiver_bw == 6)
Sinan Divarci 0:dc5ded118d7c 2671 set_chf_sel(CHF_SEL_RXBW_12_6_KHZ);
Sinan Divarci 0:dc5ded118d7c 2672 else{
Sinan Divarci 0:dc5ded118d7c 2673 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2674 goto error;
Sinan Divarci 0:dc5ded118d7c 2675 }
Sinan Divarci 0:dc5ded118d7c 2676
Sinan Divarci 0:dc5ded118d7c 2677 if(this->adjust_baud_rate(this->baud_rate) < 0){
Sinan Divarci 0:dc5ded118d7c 2678 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2679 goto error;
Sinan Divarci 0:dc5ded118d7c 2680 }
Sinan Divarci 0:dc5ded118d7c 2681 if(this->update_ath_gc() < 0){
Sinan Divarci 0:dc5ded118d7c 2682 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2683 goto error;
Sinan Divarci 0:dc5ded118d7c 2684 }
Sinan Divarci 0:dc5ded118d7c 2685 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 2686 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 2687 goto error;
Sinan Divarci 0:dc5ded118d7c 2688 }
Sinan Divarci 0:dc5ded118d7c 2689 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 2690 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 2691 goto error;
Sinan Divarci 0:dc5ded118d7c 2692 }
Sinan Divarci 0:dc5ded118d7c 2693 if(this->adjust_fsk_deviation(deviation) < 0){
Sinan Divarci 0:dc5ded118d7c 2694 return_val = -10;
Sinan Divarci 0:dc5ded118d7c 2695 goto error;
Sinan Divarci 0:dc5ded118d7c 2696 }
Sinan Divarci 0:dc5ded118d7c 2697
Sinan Divarci 0:dc5ded118d7c 2698 error:
Sinan Divarci 0:dc5ded118d7c 2699 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2700 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2701 return return_val;
Sinan Divarci 0:dc5ded118d7c 2702 }
Sinan Divarci 0:dc5ded118d7c 2703
Sinan Divarci 0:dc5ded118d7c 2704 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2705 int MAX4147X<REG>::adjust_if_sel(if_sel_t if_sel)
Sinan Divarci 0:dc5ded118d7c 2706 {
Sinan Divarci 0:dc5ded118d7c 2707 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2708
Sinan Divarci 0:dc5ded118d7c 2709 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2710 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2711 return -99;
Sinan Divarci 0:dc5ded118d7c 2712
Sinan Divarci 0:dc5ded118d7c 2713 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2714 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2715 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2716 return -98;
Sinan Divarci 0:dc5ded118d7c 2717 }
Sinan Divarci 0:dc5ded118d7c 2718
Sinan Divarci 0:dc5ded118d7c 2719 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2720 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2721 goto error;
Sinan Divarci 0:dc5ded118d7c 2722 }
Sinan Divarci 0:dc5ded118d7c 2723
Sinan Divarci 0:dc5ded118d7c 2724 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2725 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2726 goto error;
Sinan Divarci 0:dc5ded118d7c 2727 }
Sinan Divarci 0:dc5ded118d7c 2728
Sinan Divarci 0:dc5ded118d7c 2729 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2730 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2731 goto error;
Sinan Divarci 0:dc5ded118d7c 2732 }
Sinan Divarci 0:dc5ded118d7c 2733
Sinan Divarci 0:dc5ded118d7c 2734 if(*ask_fsk_sel != ASK_FSK_SEL_ASK){
Sinan Divarci 0:dc5ded118d7c 2735 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2736 goto error;
Sinan Divarci 0:dc5ded118d7c 2737 }
Sinan Divarci 0:dc5ded118d7c 2738
Sinan Divarci 0:dc5ded118d7c 2739 this->set_if_sel(if_sel);
Sinan Divarci 0:dc5ded118d7c 2740
Sinan Divarci 0:dc5ded118d7c 2741 if(this->adjust_baud_rate(this->baud_rate) < 0){
Sinan Divarci 0:dc5ded118d7c 2742 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2743 goto error;
Sinan Divarci 0:dc5ded118d7c 2744 }
Sinan Divarci 0:dc5ded118d7c 2745 if(this->update_ath_gc() < 0){
Sinan Divarci 0:dc5ded118d7c 2746 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2747 goto error;
Sinan Divarci 0:dc5ded118d7c 2748 }
Sinan Divarci 0:dc5ded118d7c 2749 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 2750 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2751 goto error;
Sinan Divarci 0:dc5ded118d7c 2752 }
Sinan Divarci 0:dc5ded118d7c 2753 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 2754 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 2755 goto error;
Sinan Divarci 0:dc5ded118d7c 2756 }
Sinan Divarci 0:dc5ded118d7c 2757 if(this->set_center_frequency(this->center_frequency) < 0){
Sinan Divarci 0:dc5ded118d7c 2758 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 2759 goto error;
Sinan Divarci 0:dc5ded118d7c 2760 }
Sinan Divarci 0:dc5ded118d7c 2761
Sinan Divarci 0:dc5ded118d7c 2762 error:
Sinan Divarci 0:dc5ded118d7c 2763 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2764 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2765 return return_val;
Sinan Divarci 0:dc5ded118d7c 2766 }
Sinan Divarci 0:dc5ded118d7c 2767
Sinan Divarci 0:dc5ded118d7c 2768 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2769 int MAX4147X<REG>::adjust_if_sel(if_sel_t if_sel, float deviation)
Sinan Divarci 0:dc5ded118d7c 2770 {
Sinan Divarci 0:dc5ded118d7c 2771 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2772
Sinan Divarci 0:dc5ded118d7c 2773 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2774 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2775 return -99;
Sinan Divarci 0:dc5ded118d7c 2776
Sinan Divarci 0:dc5ded118d7c 2777 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2778 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2779 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2780 return -98;
Sinan Divarci 0:dc5ded118d7c 2781 }
Sinan Divarci 0:dc5ded118d7c 2782
Sinan Divarci 0:dc5ded118d7c 2783 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2784 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2785 goto error;
Sinan Divarci 0:dc5ded118d7c 2786 }
Sinan Divarci 0:dc5ded118d7c 2787
Sinan Divarci 0:dc5ded118d7c 2788 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2789 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2790 goto error;
Sinan Divarci 0:dc5ded118d7c 2791 }
Sinan Divarci 0:dc5ded118d7c 2792
Sinan Divarci 0:dc5ded118d7c 2793 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2794 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2795 goto error;
Sinan Divarci 0:dc5ded118d7c 2796 }
Sinan Divarci 0:dc5ded118d7c 2797
Sinan Divarci 0:dc5ded118d7c 2798 if(*ask_fsk_sel != ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2799 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2800 goto error;
Sinan Divarci 0:dc5ded118d7c 2801 }
Sinan Divarci 0:dc5ded118d7c 2802
Sinan Divarci 0:dc5ded118d7c 2803 this->set_if_sel(if_sel);
Sinan Divarci 0:dc5ded118d7c 2804
Sinan Divarci 0:dc5ded118d7c 2805 if(this->adjust_baud_rate(this->baud_rate) < 0){
Sinan Divarci 0:dc5ded118d7c 2806 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2807 goto error;
Sinan Divarci 0:dc5ded118d7c 2808 }
Sinan Divarci 0:dc5ded118d7c 2809 if(this->update_ath_gc() < 0){
Sinan Divarci 0:dc5ded118d7c 2810 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2811 goto error;
Sinan Divarci 0:dc5ded118d7c 2812 }
Sinan Divarci 0:dc5ded118d7c 2813 if(this->update_demod_tctrl() < 0){
Sinan Divarci 0:dc5ded118d7c 2814 return_val = -7;
Sinan Divarci 0:dc5ded118d7c 2815 goto error;
Sinan Divarci 0:dc5ded118d7c 2816 }
Sinan Divarci 0:dc5ded118d7c 2817 if(this->update_ath_lb() < 0){
Sinan Divarci 0:dc5ded118d7c 2818 return_val = -8;
Sinan Divarci 0:dc5ded118d7c 2819 goto error;
Sinan Divarci 0:dc5ded118d7c 2820 }
Sinan Divarci 0:dc5ded118d7c 2821 if(this->set_center_frequency(this->center_frequency) < 0){
Sinan Divarci 0:dc5ded118d7c 2822 return_val = -9;
Sinan Divarci 0:dc5ded118d7c 2823 goto error;
Sinan Divarci 0:dc5ded118d7c 2824 }
Sinan Divarci 0:dc5ded118d7c 2825 if(this->adjust_fsk_deviation(deviation) < 0){
Sinan Divarci 0:dc5ded118d7c 2826 return_val = -10;
Sinan Divarci 0:dc5ded118d7c 2827 goto error;
Sinan Divarci 0:dc5ded118d7c 2828 }
Sinan Divarci 0:dc5ded118d7c 2829
Sinan Divarci 0:dc5ded118d7c 2830 error:
Sinan Divarci 0:dc5ded118d7c 2831 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2832 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2833 return return_val;
Sinan Divarci 0:dc5ded118d7c 2834 }
Sinan Divarci 0:dc5ded118d7c 2835
Sinan Divarci 0:dc5ded118d7c 2836 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2837 int MAX4147X<REG>::adjust_fsk_deviation(float deviation)
Sinan Divarci 0:dc5ded118d7c 2838 {
Sinan Divarci 0:dc5ded118d7c 2839 int return_val = 0;
Sinan Divarci 0:dc5ded118d7c 2840 uint8_t fsk_dev_conf_idx, conf_chf_sel, conf_demod_fsk;
Sinan Divarci 0:dc5ded118d7c 2841 float conf_nominal_fsk_df;
Sinan Divarci 0:dc5ded118d7c 2842
Sinan Divarci 0:dc5ded118d7c 2843 ask_fsk_sel_t *ask_fsk_sel = (ask_fsk_sel_t *)malloc(sizeof(ask_fsk_sel_t));
Sinan Divarci 0:dc5ded118d7c 2844 if(ask_fsk_sel == NULL)
Sinan Divarci 0:dc5ded118d7c 2845 return -99;
Sinan Divarci 0:dc5ded118d7c 2846
Sinan Divarci 0:dc5ded118d7c 2847 chf_sel_t *chf_sel = (chf_sel_t *)malloc(sizeof(chf_sel_t));
Sinan Divarci 0:dc5ded118d7c 2848 if(chf_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 2849 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2850 return -98;
Sinan Divarci 0:dc5ded118d7c 2851 }
Sinan Divarci 0:dc5ded118d7c 2852
Sinan Divarci 0:dc5ded118d7c 2853 if_sel_t *if_sel = (if_sel_t *)malloc(sizeof(if_sel_t));
Sinan Divarci 0:dc5ded118d7c 2854 if(if_sel == NULL){
Sinan Divarci 0:dc5ded118d7c 2855 free(ask_fsk_sel); free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2856 return -97;
Sinan Divarci 0:dc5ded118d7c 2857 }
Sinan Divarci 0:dc5ded118d7c 2858
Sinan Divarci 0:dc5ded118d7c 2859 rx_state_t *rx_state = (rx_state_t *)malloc(sizeof(rx_state_t));
Sinan Divarci 0:dc5ded118d7c 2860 if(rx_state == NULL){
Sinan Divarci 0:dc5ded118d7c 2861 free(ask_fsk_sel); free(chf_sel); free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2862 return -96;
Sinan Divarci 0:dc5ded118d7c 2863 }
Sinan Divarci 0:dc5ded118d7c 2864
Sinan Divarci 0:dc5ded118d7c 2865 if(this->get_rx_state(rx_state) < 0){
Sinan Divarci 0:dc5ded118d7c 2866 return_val = -1;
Sinan Divarci 0:dc5ded118d7c 2867 goto error;
Sinan Divarci 0:dc5ded118d7c 2868 }
Sinan Divarci 0:dc5ded118d7c 2869
Sinan Divarci 0:dc5ded118d7c 2870 if(*rx_state != RX_STATE_STANDBY){
Sinan Divarci 0:dc5ded118d7c 2871 return_val = -2;
Sinan Divarci 0:dc5ded118d7c 2872 goto error;
Sinan Divarci 0:dc5ded118d7c 2873 }
Sinan Divarci 0:dc5ded118d7c 2874
Sinan Divarci 0:dc5ded118d7c 2875 if(this->get_ask_fsk_sel(ask_fsk_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2876 return_val = -3;
Sinan Divarci 0:dc5ded118d7c 2877 goto error;
Sinan Divarci 0:dc5ded118d7c 2878 }
Sinan Divarci 0:dc5ded118d7c 2879
Sinan Divarci 0:dc5ded118d7c 2880 if(*ask_fsk_sel != ASK_FSK_SEL_FSK){
Sinan Divarci 0:dc5ded118d7c 2881 return_val = -4;
Sinan Divarci 0:dc5ded118d7c 2882 goto error;
Sinan Divarci 0:dc5ded118d7c 2883 }
Sinan Divarci 0:dc5ded118d7c 2884
Sinan Divarci 0:dc5ded118d7c 2885 if (this->get_if_sel(if_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2886 return_val = -5;
Sinan Divarci 0:dc5ded118d7c 2887 goto error;
Sinan Divarci 0:dc5ded118d7c 2888 }
Sinan Divarci 0:dc5ded118d7c 2889 if(this->get_chf_sel(chf_sel) < 0){
Sinan Divarci 0:dc5ded118d7c 2890 return_val = -6;
Sinan Divarci 0:dc5ded118d7c 2891 goto error;
Sinan Divarci 0:dc5ded118d7c 2892 }
Sinan Divarci 0:dc5ded118d7c 2893
Sinan Divarci 0:dc5ded118d7c 2894 for(fsk_dev_conf_idx = 0; fsk_dev_conf_idx < 14; fsk_dev_conf_idx++)
Sinan Divarci 0:dc5ded118d7c 2895 {
Sinan Divarci 0:dc5ded118d7c 2896 conf_nominal_fsk_df = nominal_fsk_conf[fsk_dev_conf_idx];
Sinan Divarci 0:dc5ded118d7c 2897 conf_nominal_fsk_df = (conf_nominal_fsk_df*10)/(*if_sel + 1);
Sinan Divarci 0:dc5ded118d7c 2898
Sinan Divarci 0:dc5ded118d7c 2899 if(int(conf_nominal_fsk_df) == int(deviation*10))
Sinan Divarci 0:dc5ded118d7c 2900 {
Sinan Divarci 0:dc5ded118d7c 2901 conf_chf_sel = chf_sel_demod_fsk_conf[fsk_dev_conf_idx][0];
Sinan Divarci 0:dc5ded118d7c 2902 conf_demod_fsk = chf_sel_demod_fsk_conf[fsk_dev_conf_idx][1];
Sinan Divarci 0:dc5ded118d7c 2903 if(conf_chf_sel == *chf_sel)
Sinan Divarci 0:dc5ded118d7c 2904 {
Sinan Divarci 0:dc5ded118d7c 2905 set_demod_fsk(demod_fsk_t(conf_demod_fsk));
Sinan Divarci 0:dc5ded118d7c 2906 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2907 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2908 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2909 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2910 return conf_demod_fsk;
Sinan Divarci 0:dc5ded118d7c 2911 }
Sinan Divarci 0:dc5ded118d7c 2912 }
Sinan Divarci 0:dc5ded118d7c 2913 }
Sinan Divarci 0:dc5ded118d7c 2914
Sinan Divarci 0:dc5ded118d7c 2915 error:
Sinan Divarci 0:dc5ded118d7c 2916 free(ask_fsk_sel);
Sinan Divarci 0:dc5ded118d7c 2917 free(chf_sel);
Sinan Divarci 0:dc5ded118d7c 2918 free(if_sel);
Sinan Divarci 0:dc5ded118d7c 2919 free(rx_state);
Sinan Divarci 0:dc5ded118d7c 2920 return return_val;
Sinan Divarci 0:dc5ded118d7c 2921 }
Sinan Divarci 0:dc5ded118d7c 2922
Sinan Divarci 0:dc5ded118d7c 2923 template <class REG>
Sinan Divarci 0:dc5ded118d7c 2924 int MAX4147X<REG>::adjust_preamble(int preamble, uint8_t preamb_len)
Sinan Divarci 0:dc5ded118d7c 2925 {
Sinan Divarci 0:dc5ded118d7c 2926 uint8_t preamb_w1, preamb_w2;
Sinan Divarci 0:dc5ded118d7c 2927 if(preamble < 0 || preamble > 65535)
Sinan Divarci 0:dc5ded118d7c 2928 return -1;
Sinan Divarci 0:dc5ded118d7c 2929
Sinan Divarci 0:dc5ded118d7c 2930 if(preamb_len < 1 || preamb_len > 16)
Sinan Divarci 0:dc5ded118d7c 2931 return -2;
Sinan Divarci 0:dc5ded118d7c 2932
Sinan Divarci 0:dc5ded118d7c 2933 if(this->set_preamb_len(preamb_len-1) < 0)
Sinan Divarci 0:dc5ded118d7c 2934 return -3;
Sinan Divarci 0:dc5ded118d7c 2935
Sinan Divarci 0:dc5ded118d7c 2936 preamb_w1 = (preamble & 0xFF);
Sinan Divarci 0:dc5ded118d7c 2937 preamb_w2 = ((preamble >> 8) & 0xFF);
Sinan Divarci 0:dc5ded118d7c 2938
Sinan Divarci 0:dc5ded118d7c 2939 if(this->set_preamb_word_lower(preamb_w1) < 0)
Sinan Divarci 0:dc5ded118d7c 2940 return -4;
Sinan Divarci 0:dc5ded118d7c 2941
Sinan Divarci 0:dc5ded118d7c 2942 if(this->set_preamb_word_upper(preamb_w2) < 0)
Sinan Divarci 0:dc5ded118d7c 2943 return -5;
Sinan Divarci 0:dc5ded118d7c 2944
Sinan Divarci 0:dc5ded118d7c 2945 return 0;
Sinan Divarci 0:dc5ded118d7c 2946 }
Sinan Divarci 0:dc5ded118d7c 2947
Sinan Divarci 0:dc5ded118d7c 2948 template class MAX4147X<max41470_reg_map_t>;
Sinan Divarci 0:dc5ded118d7c 2949 template class MAX4147X<max41473_4_reg_map_t>;