MAX4147X RF Receiver Mbed Driver
Fork of MAX4147X by
Max41470_regs.h@0:dc5ded118d7c, 2021-08-02 (annotated)
- Committer:
- Sinan Divarci
- Date:
- Mon Aug 02 16:34:28 2021 +0300
- Revision:
- 0:dc5ded118d7c
initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Sinan Divarci |
0:dc5ded118d7c | 1 | /******************************************************************************* |
Sinan Divarci |
0:dc5ded118d7c | 2 | * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. |
Sinan Divarci |
0:dc5ded118d7c | 3 | * |
Sinan Divarci |
0:dc5ded118d7c | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Sinan Divarci |
0:dc5ded118d7c | 5 | * copy of this software and associated documentation files(the "Software"), |
Sinan Divarci |
0:dc5ded118d7c | 6 | * to deal in the Software without restriction, including without limitation |
Sinan Divarci |
0:dc5ded118d7c | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Sinan Divarci |
0:dc5ded118d7c | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Sinan Divarci |
0:dc5ded118d7c | 9 | * Software is furnished to do so, subject to the following conditions: |
Sinan Divarci |
0:dc5ded118d7c | 10 | * |
Sinan Divarci |
0:dc5ded118d7c | 11 | * The above copyright notice and this permission notice shall be included |
Sinan Divarci |
0:dc5ded118d7c | 12 | * in all copies or substantial portions of the Software. |
Sinan Divarci |
0:dc5ded118d7c | 13 | * |
Sinan Divarci |
0:dc5ded118d7c | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Sinan Divarci |
0:dc5ded118d7c | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Sinan Divarci |
0:dc5ded118d7c | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Sinan Divarci |
0:dc5ded118d7c | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Sinan Divarci |
0:dc5ded118d7c | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Sinan Divarci |
0:dc5ded118d7c | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Sinan Divarci |
0:dc5ded118d7c | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Sinan Divarci |
0:dc5ded118d7c | 21 | * |
Sinan Divarci |
0:dc5ded118d7c | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Sinan Divarci |
0:dc5ded118d7c | 23 | * Products, Inc.shall not be used except as stated in the Maxim Integrated |
Sinan Divarci |
0:dc5ded118d7c | 24 | * Products, Inc.Branding Policy. |
Sinan Divarci |
0:dc5ded118d7c | 25 | * |
Sinan Divarci |
0:dc5ded118d7c | 26 | * The mere transfer of this software does not imply any licenses |
Sinan Divarci |
0:dc5ded118d7c | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Sinan Divarci |
0:dc5ded118d7c | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Sinan Divarci |
0:dc5ded118d7c | 29 | * property whatsoever. Maxim Integrated Products, Inc.retains all |
Sinan Divarci |
0:dc5ded118d7c | 30 | * ownership rights. |
Sinan Divarci |
0:dc5ded118d7c | 31 | ******************************************************************************* |
Sinan Divarci |
0:dc5ded118d7c | 32 | */ |
Sinan Divarci |
0:dc5ded118d7c | 33 | |
Sinan Divarci |
0:dc5ded118d7c | 34 | #ifndef MAX41470_REGS_H_ |
Sinan Divarci |
0:dc5ded118d7c | 35 | #define MAX41470_REGS_H_ |
Sinan Divarci |
0:dc5ded118d7c | 36 | |
Sinan Divarci |
0:dc5ded118d7c | 37 | /** |
Sinan Divarci |
0:dc5ded118d7c | 38 | * @brief DEMOD Register |
Sinan Divarci |
0:dc5ded118d7c | 39 | * |
Sinan Divarci |
0:dc5ded118d7c | 40 | * Address : 0x00 |
Sinan Divarci |
0:dc5ded118d7c | 41 | */ |
Sinan Divarci |
0:dc5ded118d7c | 42 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 43 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 44 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 45 | unsigned char demod_tctrl : 3; /**< Demodulator Parameter#1 |
Sinan Divarci |
0:dc5ded118d7c | 46 | Conditions / Recommended Value |
Sinan Divarci |
0:dc5ded118d7c | 47 | ASK_FSK_SEL=1 / 4 - CHF_SEL |
Sinan Divarci |
0:dc5ded118d7c | 48 | ASK_FSK_SEL=0, ATH_TYPE=0 / min(2+SRC_LG, 7) |
Sinan Divarci |
0:dc5ded118d7c | 49 | ASK_FSK_SEL=0, ATH_TYPE=1 / min(3+SRC_LG,7) */ |
Sinan Divarci |
0:dc5ded118d7c | 50 | unsigned char demod_fsk : 3; /**< Demodulator Parameter#2 to be used only in FSK mode. Must be programmed |
Sinan Divarci |
0:dc5ded118d7c | 51 | according to the table of FSK Demodulator Configuration. */ |
Sinan Divarci |
0:dc5ded118d7c | 52 | unsigned char rssi_dt : 2; /**< RSSI Peak Peak Detector Discharge Time |
Sinan Divarci |
0:dc5ded118d7c | 53 | 0x0: 1/2 default value 0x2: 2x default value |
Sinan Divarci |
0:dc5ded118d7c | 54 | 0x1: default value 0x3: 4x default value */ |
Sinan Divarci |
0:dc5ded118d7c | 55 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 56 | } max41470_reg_demod_t; |
Sinan Divarci |
0:dc5ded118d7c | 57 | |
Sinan Divarci |
0:dc5ded118d7c | 58 | /** |
Sinan Divarci |
0:dc5ded118d7c | 59 | * @brief AGC Register |
Sinan Divarci |
0:dc5ded118d7c | 60 | * |
Sinan Divarci |
0:dc5ded118d7c | 61 | * Address : 0x01 |
Sinan Divarci |
0:dc5ded118d7c | 62 | */ |
Sinan Divarci |
0:dc5ded118d7c | 63 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 64 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 65 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 66 | unsigned char agc_en_bo : 2; /**< AGC Operation Mode |
Sinan Divarci |
0:dc5ded118d7c | 67 | 0x0: AGC disabled, max gain 0x2: AGC enabled |
Sinan Divarci |
0:dc5ded118d7c | 68 | 0x1: AGC disabled, back off ADC buffer 0x3: AGC enabled, back off ADC buffer */ |
Sinan Divarci |
0:dc5ded118d7c | 69 | unsigned char agc_threl : 4; /**< AGC-Release Threshold Fine Tune. Recommended value is 0x9 when data |
Sinan Divarci |
0:dc5ded118d7c | 70 | rate is lower than 52kbps, or 0xF when data rate is higher than 52kbps. */ |
Sinan Divarci |
0:dc5ded118d7c | 71 | unsigned char : 2; |
Sinan Divarci |
0:dc5ded118d7c | 72 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 73 | } max41470_reg_agc_t; |
Sinan Divarci |
0:dc5ded118d7c | 74 | |
Sinan Divarci |
0:dc5ded118d7c | 75 | /** |
Sinan Divarci |
0:dc5ded118d7c | 76 | * @brief IF_CGF_SEL Register |
Sinan Divarci |
0:dc5ded118d7c | 77 | * |
Sinan Divarci |
0:dc5ded118d7c | 78 | * Address : 0x02 |
Sinan Divarci |
0:dc5ded118d7c | 79 | */ |
Sinan Divarci |
0:dc5ded118d7c | 80 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 81 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 82 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 83 | unsigned char chf_sel : 3; /**< Channel Filter Selection |
Sinan Divarci |
0:dc5ded118d7c | 84 | 0x0: RXBW = 340kHz or 170kHz 0x4: RXBW = 12kHz or 6kHz |
Sinan Divarci |
0:dc5ded118d7c | 85 | 0x1: RXBW = 120kHz or 60kHz 0x5: Invalid value |
Sinan Divarci |
0:dc5ded118d7c | 86 | 0x2: RXBW = 52kHz or 26kHz 0x6: Invalid value |
Sinan Divarci |
0:dc5ded118d7c | 87 | 0x3: RXBW = 24kHz or 12kHz 0x7: Invalid value */ |
Sinan Divarci |
0:dc5ded118d7c | 88 | unsigned char if_sel : 1; /**< Intermediate Frequency Selection |
Sinan Divarci |
0:dc5ded118d7c | 89 | 0x0: 400KHz 0x1: 200KHz */ |
Sinan Divarci |
0:dc5ded118d7c | 90 | unsigned char ask_fsk_sel : 1; /**< ASK/FSK Selection |
Sinan Divarci |
0:dc5ded118d7c | 91 | 0x0: ASK Demodulation 0x1: FSK Demodulation */ |
Sinan Divarci |
0:dc5ded118d7c | 92 | unsigned char : 3; |
Sinan Divarci |
0:dc5ded118d7c | 93 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 94 | } max41470_reg_if_chf_sel_t; |
Sinan Divarci |
0:dc5ded118d7c | 95 | |
Sinan Divarci |
0:dc5ded118d7c | 96 | /** |
Sinan Divarci |
0:dc5ded118d7c | 97 | * @brief PDF_CFG Post Demodulation Filter Register |
Sinan Divarci |
0:dc5ded118d7c | 98 | * |
Sinan Divarci |
0:dc5ded118d7c | 99 | * Address : 0x03 |
Sinan Divarci |
0:dc5ded118d7c | 100 | */ |
Sinan Divarci |
0:dc5ded118d7c | 101 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 102 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 103 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 104 | unsigned char src_sm : 3; /**< "Small" adjustment to the Sample Rate Converter used to calculate the |
Sinan Divarci |
0:dc5ded118d7c | 105 | recommended data rate. |
Sinan Divarci |
0:dc5ded118d7c | 106 | See Configuration Guidance Tables and Recommended Data Rate Equation. |
Sinan Divarci |
0:dc5ded118d7c | 107 | 0x0: Default rate 0x4: 8/12 Default |
Sinan Divarci |
0:dc5ded118d7c | 108 | 0x1: 8/9 Default 0x5: 8/13 Default |
Sinan Divarci |
0:dc5ded118d7c | 109 | 0x2: 8/10 Default 0x6: 8/14 Default |
Sinan Divarci |
0:dc5ded118d7c | 110 | 0x3: 8/11 Default 0x7: 8/15 Default */ |
Sinan Divarci |
0:dc5ded118d7c | 111 | unsigned char src_lg : 3; /**< "Large" adjustment to the Sample Rate Converter used to calculate the |
Sinan Divarci |
0:dc5ded118d7c | 112 | recommended data rate. |
Sinan Divarci |
0:dc5ded118d7c | 113 | See Configuration Guidance Tables and Recommended Data Rate Equation. |
Sinan Divarci |
0:dc5ded118d7c | 114 | 0x0: 4x Default 0x4: 1/4 Default |
Sinan Divarci |
0:dc5ded118d7c | 115 | 0x1: 2x Default 0x5: 1/8 Default |
Sinan Divarci |
0:dc5ded118d7c | 116 | 0x2: Default rate 0x6: 1/16 Default |
Sinan Divarci |
0:dc5ded118d7c | 117 | 0x3: 1/2 Default 0x7: 1/32 Default*/ |
Sinan Divarci |
0:dc5ded118d7c | 118 | unsigned char ld_bw : 1; /**< Post Demodulation Filter Bandwidth Control |
Sinan Divarci |
0:dc5ded118d7c | 119 | 0x0: Default BW |
Sinan Divarci |
0:dc5ded118d7c | 120 | 0x1: 1.67x Default BW */ |
Sinan Divarci |
0:dc5ded118d7c | 121 | unsigned char ld_buf : 1; /**< Output Buffer Selection. Low delay buffer can only be selected when |
Sinan Divarci |
0:dc5ded118d7c | 122 | (SRC_LG >= 3) or (SRC_LG = 2 and SRC_SM is even). |
Sinan Divarci |
0:dc5ded118d7c | 123 | 0x0: Default Selection |
Sinan Divarci |
0:dc5ded118d7c | 124 | 0x1: Low Delay Buffer */ |
Sinan Divarci |
0:dc5ded118d7c | 125 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 126 | } max41470_reg_pdf_cfg_t; |
Sinan Divarci |
0:dc5ded118d7c | 127 | |
Sinan Divarci |
0:dc5ded118d7c | 128 | /** |
Sinan Divarci |
0:dc5ded118d7c | 129 | * @brief ATH_CFG1 ASK Threshold Configuration 1 Register |
Sinan Divarci |
0:dc5ded118d7c | 130 | * |
Sinan Divarci |
0:dc5ded118d7c | 131 | * Address : 0x04 |
Sinan Divarci |
0:dc5ded118d7c | 132 | */ |
Sinan Divarci |
0:dc5ded118d7c | 133 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 134 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 135 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 136 | unsigned char ath_lb : 8; /**< Parameter#1 for ASK Threshold Generation: lower bound of threshold |
Sinan Divarci |
0:dc5ded118d7c | 137 | in 8bit signed, two's complement format. Valid value from -128 to 0 */ |
Sinan Divarci |
0:dc5ded118d7c | 138 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 139 | } max41470_reg_ath_cfg1_t; |
Sinan Divarci |
0:dc5ded118d7c | 140 | |
Sinan Divarci |
0:dc5ded118d7c | 141 | /** |
Sinan Divarci |
0:dc5ded118d7c | 142 | * @brief ATH_CFG2 ASK Threshold Configuration 2 Register |
Sinan Divarci |
0:dc5ded118d7c | 143 | * |
Sinan Divarci |
0:dc5ded118d7c | 144 | * Address : 0x05 |
Sinan Divarci |
0:dc5ded118d7c | 145 | */ |
Sinan Divarci |
0:dc5ded118d7c | 146 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 147 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 148 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 149 | unsigned char ath_tc : 5, /**< Parameter#2 for ASK Threshold Generation: to be programmed |
Sinan Divarci |
0:dc5ded118d7c | 150 | according to SRC_LG */ |
Sinan Divarci |
0:dc5ded118d7c | 151 | ath_dt : 2, /**< Parameter#4 for ASK Threshold Generation: peak-hold time control in the |
Sinan Divarci |
0:dc5ded118d7c | 152 | "adaptive Peak Detector" (aPD) method |
Sinan Divarci |
0:dc5ded118d7c | 153 | 0x0: Default discharge time, suggested for Manchester data, close to Rb |
Sinan Divarci |
0:dc5ded118d7c | 154 | 0x1: 2x Discharge time, suggested for Manchester data, lower than Rb |
Sinan Divarci |
0:dc5ded118d7c | 155 | 0x2: 4x Discharge time |
Sinan Divarci |
0:dc5ded118d7c | 156 | 0x3: 8x Discharge time, suggested for NRZ data */ |
Sinan Divarci |
0:dc5ded118d7c | 157 | dummy : 1; |
Sinan Divarci |
0:dc5ded118d7c | 158 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 159 | } max41470_reg_ath_cfg2_t; |
Sinan Divarci |
0:dc5ded118d7c | 160 | |
Sinan Divarci |
0:dc5ded118d7c | 161 | /** |
Sinan Divarci |
0:dc5ded118d7c | 162 | * @brief ATH_CFG3 ASK Threshold Configuration 3 Register |
Sinan Divarci |
0:dc5ded118d7c | 163 | * |
Sinan Divarci |
0:dc5ded118d7c | 164 | * Address : 0x06 |
Sinan Divarci |
0:dc5ded118d7c | 165 | */ |
Sinan Divarci |
0:dc5ded118d7c | 166 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 167 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 168 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 169 | unsigned char ath_gc : 5; /**< Parameter#3 for ASK Threshold Generation: to be programmed |
Sinan Divarci |
0:dc5ded118d7c | 170 | according to IF_SEL and CHF_SEL */ |
Sinan Divarci |
0:dc5ded118d7c | 171 | unsigned char ath_bw : 1; /**< Parameter#5 for ASK Threshold Generation: bandwidth control |
Sinan Divarci |
0:dc5ded118d7c | 172 | for precharged LPF(preLPF) |
Sinan Divarci |
0:dc5ded118d7c | 173 | 0x0: Default bandwidth 0x1: 2x default */ |
Sinan Divarci |
0:dc5ded118d7c | 174 | unsigned char ath_type : 1; /**< ASK Threshold Adjustment Method |
Sinan Divarci |
0:dc5ded118d7c | 175 | 0x0: Precharged Low Pass Filter (preLPF)(Manchester) |
Sinan Divarci |
0:dc5ded118d7c | 176 | 0x1: Adaptive Peak Detector (aPD)(NRZ) */ |
Sinan Divarci |
0:dc5ded118d7c | 177 | unsigned char : 1; |
Sinan Divarci |
0:dc5ded118d7c | 178 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 179 | } max41470_reg_ath_cfg3_t; |
Sinan Divarci |
0:dc5ded118d7c | 180 | |
Sinan Divarci |
0:dc5ded118d7c | 181 | /** |
Sinan Divarci |
0:dc5ded118d7c | 182 | * @brief AFC_CFG1 Register |
Sinan Divarci |
0:dc5ded118d7c | 183 | * |
Sinan Divarci |
0:dc5ded118d7c | 184 | * Address : 0x07 |
Sinan Divarci |
0:dc5ded118d7c | 185 | */ |
Sinan Divarci |
0:dc5ded118d7c | 186 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 187 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 188 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 189 | unsigned char afc_lg : 2; /**< AFC Loop Gain Control |
Sinan Divarci |
0:dc5ded118d7c | 190 | 0x0: 1/4 Default 0x2: Default gain, FSK typical setting |
Sinan Divarci |
0:dc5ded118d7c | 191 | 0x1: 1/2 Default 0x3: 2x Default, ASK typical setting */ |
Sinan Divarci |
0:dc5ded118d7c | 192 | unsigned char afc_mo : 3; /**< AFC Frequency Offset Limit |
Sinan Divarci |
0:dc5ded118d7c | 193 | 0x0: AFC disabled 0x4: 4/7 Max offset |
Sinan Divarci |
0:dc5ded118d7c | 194 | 0x1: 1/7 Max offset 0x5: 5/7 Max offset |
Sinan Divarci |
0:dc5ded118d7c | 195 | 0x2: 2/7 Max offset 0x6: 6/7 Max offset |
Sinan Divarci |
0:dc5ded118d7c | 196 | 0x3: 3/7 Max offset 0x7: Max offset */ |
Sinan Divarci |
0:dc5ded118d7c | 197 | unsigned char : 3; |
Sinan Divarci |
0:dc5ded118d7c | 198 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 199 | } max41470_reg_afc_cfg1_t; |
Sinan Divarci |
0:dc5ded118d7c | 200 | |
Sinan Divarci |
0:dc5ded118d7c | 201 | /** |
Sinan Divarci |
0:dc5ded118d7c | 202 | * @brief AFC_CFG2 Register |
Sinan Divarci |
0:dc5ded118d7c | 203 | * |
Sinan Divarci |
0:dc5ded118d7c | 204 | * Address : 0x08 |
Sinan Divarci |
0:dc5ded118d7c | 205 | */ |
Sinan Divarci |
0:dc5ded118d7c | 206 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 207 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 208 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 209 | unsigned char reserved : 6; /**< Reserved. Set to 0 */ |
Sinan Divarci |
0:dc5ded118d7c | 210 | unsigned char pad_freeze_afc : 1; /**< Control bit to Freeze AFC after Preamble Detected. |
Sinan Divarci |
0:dc5ded118d7c | 211 | Not used in ASK mode. |
Sinan Divarci |
0:dc5ded118d7c | 212 | 0x0: Not to freeze AFC |
Sinan Divarci |
0:dc5ded118d7c | 213 | 0x1: Freeze AFC (stop PLL frequency update) once preamble is detected*/ |
Sinan Divarci |
0:dc5ded118d7c | 214 | unsigned char : 1; |
Sinan Divarci |
0:dc5ded118d7c | 215 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 216 | } max41470_reg_afc_cfg2_t; |
Sinan Divarci |
0:dc5ded118d7c | 217 | |
Sinan Divarci |
0:dc5ded118d7c | 218 | /** |
Sinan Divarci |
0:dc5ded118d7c | 219 | * @brief LO_CTR_FREQ3 Register |
Sinan Divarci |
0:dc5ded118d7c | 220 | * |
Sinan Divarci |
0:dc5ded118d7c | 221 | * Address : 0x09 |
Sinan Divarci |
0:dc5ded118d7c | 222 | */ |
Sinan Divarci |
0:dc5ded118d7c | 223 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 224 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 225 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 226 | unsigned char lo_ctr_freq_23_to_16 : 8; /**< LO Center Frequency, Upper Byte of 24-bit Word */ |
Sinan Divarci |
0:dc5ded118d7c | 227 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 228 | } max41470_reg_lo_ctr_freq3_t; |
Sinan Divarci |
0:dc5ded118d7c | 229 | |
Sinan Divarci |
0:dc5ded118d7c | 230 | /** |
Sinan Divarci |
0:dc5ded118d7c | 231 | * @brief LO_CTR_FREQ2 Register |
Sinan Divarci |
0:dc5ded118d7c | 232 | * |
Sinan Divarci |
0:dc5ded118d7c | 233 | * Address : 0x0A |
Sinan Divarci |
0:dc5ded118d7c | 234 | */ |
Sinan Divarci |
0:dc5ded118d7c | 235 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 236 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 237 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 238 | unsigned char lo_ctr_freq_15_to_8 : 8; /**< LO Center Frequency, Middle Byte of 24-bit Word */ |
Sinan Divarci |
0:dc5ded118d7c | 239 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 240 | } max41470_reg_lo_ctr_freq2_t; |
Sinan Divarci |
0:dc5ded118d7c | 241 | |
Sinan Divarci |
0:dc5ded118d7c | 242 | /** |
Sinan Divarci |
0:dc5ded118d7c | 243 | * @brief LO_CTR_FREQ1 Register |
Sinan Divarci |
0:dc5ded118d7c | 244 | * |
Sinan Divarci |
0:dc5ded118d7c | 245 | * Address : 0x0B |
Sinan Divarci |
0:dc5ded118d7c | 246 | */ |
Sinan Divarci |
0:dc5ded118d7c | 247 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 248 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 249 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 250 | unsigned char lo_ctr_freq_7_to_0 : 8; /**< LO Center Frequency, Lower Byte of 24-bit Word */ |
Sinan Divarci |
0:dc5ded118d7c | 251 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 252 | } max41470_reg_lo_ctr_freq1_t; |
Sinan Divarci |
0:dc5ded118d7c | 253 | |
Sinan Divarci |
0:dc5ded118d7c | 254 | /** |
Sinan Divarci |
0:dc5ded118d7c | 255 | * @brief PREAMBLE_CFG1 Register |
Sinan Divarci |
0:dc5ded118d7c | 256 | * |
Sinan Divarci |
0:dc5ded118d7c | 257 | * Address : 0x0C |
Sinan Divarci |
0:dc5ded118d7c | 258 | */ |
Sinan Divarci |
0:dc5ded118d7c | 259 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 260 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 261 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 262 | unsigned char preamb_len : 4; /**< Preamble Bit Pattern Length before Manchester Coding |
Sinan Divarci |
0:dc5ded118d7c | 263 | Bit Pattern Length = Register Field Value +1 */ |
Sinan Divarci |
0:dc5ded118d7c | 264 | unsigned char : 4; |
Sinan Divarci |
0:dc5ded118d7c | 265 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 266 | } max41470_reg_preamble_cfg1_t; |
Sinan Divarci |
0:dc5ded118d7c | 267 | |
Sinan Divarci |
0:dc5ded118d7c | 268 | /** |
Sinan Divarci |
0:dc5ded118d7c | 269 | * @brief PREAMBLE_WORD1 Register |
Sinan Divarci |
0:dc5ded118d7c | 270 | * |
Sinan Divarci |
0:dc5ded118d7c | 271 | * Address : 0x0D |
Sinan Divarci |
0:dc5ded118d7c | 272 | */ |
Sinan Divarci |
0:dc5ded118d7c | 273 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 274 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 275 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 276 | unsigned char preamb_word_7_to_0 : 8; /**< Lower Byte of the Preamble Bit Pattern before Manchester Coding */ |
Sinan Divarci |
0:dc5ded118d7c | 277 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 278 | } max41470_reg_preamble_word1_t; |
Sinan Divarci |
0:dc5ded118d7c | 279 | |
Sinan Divarci |
0:dc5ded118d7c | 280 | /** |
Sinan Divarci |
0:dc5ded118d7c | 281 | * @brief PREAMBLE_WORD2 Register |
Sinan Divarci |
0:dc5ded118d7c | 282 | * |
Sinan Divarci |
0:dc5ded118d7c | 283 | * Address : 0x0E |
Sinan Divarci |
0:dc5ded118d7c | 284 | */ |
Sinan Divarci |
0:dc5ded118d7c | 285 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 286 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 287 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 288 | unsigned char preamb_word_15_to_8 : 8; /**< Upper Byte of the Preamble Bit Pattern before Manchester Coding */ |
Sinan Divarci |
0:dc5ded118d7c | 289 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 290 | } max41470_reg_preamble_word2_t; |
Sinan Divarci |
0:dc5ded118d7c | 291 | |
Sinan Divarci |
0:dc5ded118d7c | 292 | /** |
Sinan Divarci |
0:dc5ded118d7c | 293 | * @brief RSSI Register |
Sinan Divarci |
0:dc5ded118d7c | 294 | * |
Sinan Divarci |
0:dc5ded118d7c | 295 | * Address : 0x10 |
Sinan Divarci |
0:dc5ded118d7c | 296 | */ |
Sinan Divarci |
0:dc5ded118d7c | 297 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 298 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 299 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 300 | unsigned char rssi : 8; /**< Received Signal Strength Indicator (RSSI) |
Sinan Divarci |
0:dc5ded118d7c | 301 | 8-bit unsigned integer */ |
Sinan Divarci |
0:dc5ded118d7c | 302 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 303 | } max41470_reg_rssi_t; |
Sinan Divarci |
0:dc5ded118d7c | 304 | |
Sinan Divarci |
0:dc5ded118d7c | 305 | /** |
Sinan Divarci |
0:dc5ded118d7c | 306 | * @brief FEI Register |
Sinan Divarci |
0:dc5ded118d7c | 307 | * |
Sinan Divarci |
0:dc5ded118d7c | 308 | * Address : 0x11 |
Sinan Divarci |
0:dc5ded118d7c | 309 | */ |
Sinan Divarci |
0:dc5ded118d7c | 310 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 311 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 312 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 313 | unsigned char fei : 8; /**< AFC Frequency Error Indicator (FEI) |
Sinan Divarci |
0:dc5ded118d7c | 314 | 8-bit signed integer in two's complement format */ |
Sinan Divarci |
0:dc5ded118d7c | 315 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 316 | } max41470_reg_fei_t; |
Sinan Divarci |
0:dc5ded118d7c | 317 | |
Sinan Divarci |
0:dc5ded118d7c | 318 | /** |
Sinan Divarci |
0:dc5ded118d7c | 319 | * @brief PDF_OUT Register |
Sinan Divarci |
0:dc5ded118d7c | 320 | * |
Sinan Divarci |
0:dc5ded118d7c | 321 | * Address : 0x12 |
Sinan Divarci |
0:dc5ded118d7c | 322 | */ |
Sinan Divarci |
0:dc5ded118d7c | 323 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 324 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 325 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 326 | unsigned char pdf_out : 8; /**< Post Demodulation Filter (PDF) Read Out |
Sinan Divarci |
0:dc5ded118d7c | 327 | 8-bit signed integer in two's complement format */ |
Sinan Divarci |
0:dc5ded118d7c | 328 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 329 | } max41470_reg_pdf_out_t; |
Sinan Divarci |
0:dc5ded118d7c | 330 | |
Sinan Divarci |
0:dc5ded118d7c | 331 | /** |
Sinan Divarci |
0:dc5ded118d7c | 332 | * @brief ISR Register |
Sinan Divarci |
0:dc5ded118d7c | 333 | * |
Sinan Divarci |
0:dc5ded118d7c | 334 | * Address : 0x13 |
Sinan Divarci |
0:dc5ded118d7c | 335 | */ |
Sinan Divarci |
0:dc5ded118d7c | 336 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 337 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 338 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 339 | unsigned char preamb_det : 1; /**< Interreupt Status Register Bit0: preamble detector in self-polling mode |
Sinan Divarci |
0:dc5ded118d7c | 340 | 0x0: No interrupt event 0x1: Preamble detected in self-polling*/ |
Sinan Divarci |
0:dc5ded118d7c | 341 | unsigned char : 7; |
Sinan Divarci |
0:dc5ded118d7c | 342 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 343 | } max41470_reg_isr_t; |
Sinan Divarci |
0:dc5ded118d7c | 344 | |
Sinan Divarci |
0:dc5ded118d7c | 345 | /** |
Sinan Divarci |
0:dc5ded118d7c | 346 | * @brief CDR_CFG1 Register |
Sinan Divarci |
0:dc5ded118d7c | 347 | * |
Sinan Divarci |
0:dc5ded118d7c | 348 | * Address : 0x35 |
Sinan Divarci |
0:dc5ded118d7c | 349 | */ |
Sinan Divarci |
0:dc5ded118d7c | 350 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 351 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 352 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 353 | unsigned char cdr_mode : 2; /**< Clock Data Recovery configuration register |
Sinan Divarci |
0:dc5ded118d7c | 354 | 0x0: CDR disabled 0x2: Clock out disabled, DATAOUT retimed |
Sinan Divarci |
0:dc5ded118d7c | 355 | 0x1: Clock out enabled, DATAOUT untimed 0x3: Clock out enabled, DATAOUT retimed */ |
Sinan Divarci |
0:dc5ded118d7c | 356 | unsigned char : 6; |
Sinan Divarci |
0:dc5ded118d7c | 357 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 358 | } max41470_reg_cdr_cfg1_t; |
Sinan Divarci |
0:dc5ded118d7c | 359 | |
Sinan Divarci |
0:dc5ded118d7c | 360 | /** |
Sinan Divarci |
0:dc5ded118d7c | 361 | * @brief STATE_CTRL1 Register |
Sinan Divarci |
0:dc5ded118d7c | 362 | * |
Sinan Divarci |
0:dc5ded118d7c | 363 | * Address : 0x14 |
Sinan Divarci |
0:dc5ded118d7c | 364 | */ |
Sinan Divarci |
0:dc5ded118d7c | 365 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 366 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 367 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 368 | unsigned char slave_rx_en : 1; /**< Slave Receiver Enable bit |
Sinan Divarci |
0:dc5ded118d7c | 369 | 0x0 Disable Receiver 0x1 Enable Receiver */ |
Sinan Divarci |
0:dc5ded118d7c | 370 | unsigned char wut_en : 1; /**< Wake Up Timer (WUT) Enable bit |
Sinan Divarci |
0:dc5ded118d7c | 371 | 0x0: Disable WUT 0x1: Enable WUT */ |
Sinan Divarci |
0:dc5ded118d7c | 372 | unsigned char en_xo : 1; /**< XO Enable Bit |
Sinan Divarci |
0:dc5ded118d7c | 373 | 0x0: Disable XO 0x1: Enebale XO */ |
Sinan Divarci |
0:dc5ded118d7c | 374 | unsigned char : 5; |
Sinan Divarci |
0:dc5ded118d7c | 375 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 376 | } max41470_reg_state_ctrl1_t; |
Sinan Divarci |
0:dc5ded118d7c | 377 | |
Sinan Divarci |
0:dc5ded118d7c | 378 | /** |
Sinan Divarci |
0:dc5ded118d7c | 379 | * @brief STATE_CTRL2 Register |
Sinan Divarci |
0:dc5ded118d7c | 380 | * |
Sinan Divarci |
0:dc5ded118d7c | 381 | * Address : 0x15 |
Sinan Divarci |
0:dc5ded118d7c | 382 | */ |
Sinan Divarci |
0:dc5ded118d7c | 383 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 384 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 385 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 386 | unsigned char rx_state : 2; /**< Receiver State Machine Register |
Sinan Divarci |
0:dc5ded118d7c | 387 | 0x0: Standby 0x2: Wait in Self-Polling |
Sinan Divarci |
0:dc5ded118d7c | 388 | 0x1: Slave Receiver 0x3: Polling Receiver */ |
Sinan Divarci |
0:dc5ded118d7c | 389 | unsigned char : 6; |
Sinan Divarci |
0:dc5ded118d7c | 390 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 391 | } max41470_reg_state_ctrl2_t; |
Sinan Divarci |
0:dc5ded118d7c | 392 | |
Sinan Divarci |
0:dc5ded118d7c | 393 | /** |
Sinan Divarci |
0:dc5ded118d7c | 394 | * @brief STATE_CTRL3 Register |
Sinan Divarci |
0:dc5ded118d7c | 395 | * |
Sinan Divarci |
0:dc5ded118d7c | 396 | * Address : 0x16 |
Sinan Divarci |
0:dc5ded118d7c | 397 | */ |
Sinan Divarci |
0:dc5ded118d7c | 398 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 399 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 400 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 401 | unsigned char rx_reset_time : 2; /**< Receiver Front-End Turn-On Time |
Sinan Divarci |
0:dc5ded118d7c | 402 | 0x0: 0.08 ms 0x2: 0.24 ms |
Sinan Divarci |
0:dc5ded118d7c | 403 | 0x1: 0.16 ms 0x3: 0.32 ms */ |
Sinan Divarci |
0:dc5ded118d7c | 404 | unsigned char : 6; |
Sinan Divarci |
0:dc5ded118d7c | 405 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 406 | } max41470_reg_state_ctrl3_t; |
Sinan Divarci |
0:dc5ded118d7c | 407 | |
Sinan Divarci |
0:dc5ded118d7c | 408 | /** |
Sinan Divarci |
0:dc5ded118d7c | 409 | * @brief WUT1 Register |
Sinan Divarci |
0:dc5ded118d7c | 410 | * |
Sinan Divarci |
0:dc5ded118d7c | 411 | * Address : 0x17 |
Sinan Divarci |
0:dc5ded118d7c | 412 | */ |
Sinan Divarci |
0:dc5ded118d7c | 413 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 414 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 415 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 416 | unsigned char tdet : 8; /**< Duration in POLLINGRX State: from 0.48ms to 20.88ms, in step size of 0.08ms |
Sinan Divarci |
0:dc5ded118d7c | 417 | Duration (ms) = 0.48 + 0.08 x (Register Field Value) */ |
Sinan Divarci |
0:dc5ded118d7c | 418 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 419 | } max41470_reg_wut1_t; |
Sinan Divarci |
0:dc5ded118d7c | 420 | |
Sinan Divarci |
0:dc5ded118d7c | 421 | /** |
Sinan Divarci |
0:dc5ded118d7c | 422 | * @brief WUT2 Register |
Sinan Divarci |
0:dc5ded118d7c | 423 | * |
Sinan Divarci |
0:dc5ded118d7c | 424 | * Address : 0x18 |
Sinan Divarci |
0:dc5ded118d7c | 425 | */ |
Sinan Divarci |
0:dc5ded118d7c | 426 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 427 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 428 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 429 | unsigned char tsby_tdet_ratio : 7; /**< WUT Duty Cycle Control |
Sinan Divarci |
0:dc5ded118d7c | 430 | Duty Cycle = 1 / (2 + Register Field Value) */ |
Sinan Divarci |
0:dc5ded118d7c | 431 | unsigned char : 1; |
Sinan Divarci |
0:dc5ded118d7c | 432 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 433 | } max41470_reg_wut2_t; |
Sinan Divarci |
0:dc5ded118d7c | 434 | |
Sinan Divarci |
0:dc5ded118d7c | 435 | /** |
Sinan Divarci |
0:dc5ded118d7c | 436 | * @brief AFE_CTL1 Register |
Sinan Divarci |
0:dc5ded118d7c | 437 | * |
Sinan Divarci |
0:dc5ded118d7c | 438 | * Address : 0x19 |
Sinan Divarci |
0:dc5ded118d7c | 439 | */ |
Sinan Divarci |
0:dc5ded118d7c | 440 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 441 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 442 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 443 | unsigned char fracmode : 1; /**< PLL Mode Control: always program to 1 |
Sinan Divarci |
0:dc5ded118d7c | 444 | 0x0: Integer-N PLL 0x1: Fractional-N PLL */ |
Sinan Divarci |
0:dc5ded118d7c | 445 | unsigned char lodiv : 2; /**< LO Divider Control |
Sinan Divarci |
0:dc5ded118d7c | 446 | 0x0: Disabled 0x2: 425MHz to 480MHz |
Sinan Divarci |
0:dc5ded118d7c | 447 | 0x1: 860MHz to 960MHz 0x3: 286MHz to 320MHz */ |
Sinan Divarci |
0:dc5ded118d7c | 448 | unsigned char mix_hs_lsbar : 1; /**< LO Injection Control. |
Sinan Divarci |
0:dc5ded118d7c | 449 | 0x0: Targeted RF frequency higher than LO frequency |
Sinan Divarci |
0:dc5ded118d7c | 450 | 0x1: Targeted RF frequency lower than LO frequency */ |
Sinan Divarci |
0:dc5ded118d7c | 451 | unsigned char xoclkdiv : 2; /**< XO Clock Divider Ratio |
Sinan Divarci |
0:dc5ded118d7c | 452 | 0x0: divide by 4 0x2: divide by 6 |
Sinan Divarci |
0:dc5ded118d7c | 453 | 0x1: divide by 5 0x3: invalid value */ |
Sinan Divarci |
0:dc5ded118d7c | 454 | unsigned char xoclkdelay : 2; /**< Start Delay before Applying XO Clock to Digital |
Sinan Divarci |
0:dc5ded118d7c | 455 | 0x0: No delay. 0x2: 32 cycle delay |
Sinan Divarci |
0:dc5ded118d7c | 456 | 0x1: 16 cycle delay 0x3: 64 cycle delay */ |
Sinan Divarci |
0:dc5ded118d7c | 457 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 458 | } max41470_reg_afe_ctl1_t; |
Sinan Divarci |
0:dc5ded118d7c | 459 | |
Sinan Divarci |
0:dc5ded118d7c | 460 | /** |
Sinan Divarci |
0:dc5ded118d7c | 461 | * @brief IR_ADJUST Register |
Sinan Divarci |
0:dc5ded118d7c | 462 | * |
Sinan Divarci |
0:dc5ded118d7c | 463 | * Address : 0x1A |
Sinan Divarci |
0:dc5ded118d7c | 464 | */ |
Sinan Divarci |
0:dc5ded118d7c | 465 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 466 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 467 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 468 | unsigned char ir_adjust : 5 /**< Image Rejection Adjustment. See the Image Rejection Calibration section |
Sinan Divarci |
0:dc5ded118d7c | 469 | for more information*/; |
Sinan Divarci |
0:dc5ded118d7c | 470 | unsigned char : 3; |
Sinan Divarci |
0:dc5ded118d7c | 471 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 472 | } max41470_reg_ir_adjust_t; |
Sinan Divarci |
0:dc5ded118d7c | 473 | |
Sinan Divarci |
0:dc5ded118d7c | 474 | /** |
Sinan Divarci |
0:dc5ded118d7c | 475 | * @brief PART_NUM Register |
Sinan Divarci |
0:dc5ded118d7c | 476 | * |
Sinan Divarci |
0:dc5ded118d7c | 477 | * Address : 0x1E |
Sinan Divarci |
0:dc5ded118d7c | 478 | */ |
Sinan Divarci |
0:dc5ded118d7c | 479 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 480 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 481 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 482 | unsigned char part_num : 8; /**< Part Number Designator. Read of part number requires EN_XO = 1 |
Sinan Divarci |
0:dc5ded118d7c | 483 | 0x70 = MAX41470 |
Sinan Divarci |
0:dc5ded118d7c | 484 | 0x73 = MAX41473 |
Sinan Divarci |
0:dc5ded118d7c | 485 | 0x74 = MAX41474 */ |
Sinan Divarci |
0:dc5ded118d7c | 486 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 487 | } max41470_reg_part_num_t; |
Sinan Divarci |
0:dc5ded118d7c | 488 | |
Sinan Divarci |
0:dc5ded118d7c | 489 | /** |
Sinan Divarci |
0:dc5ded118d7c | 490 | * @brief REV_NUM Register |
Sinan Divarci |
0:dc5ded118d7c | 491 | * |
Sinan Divarci |
0:dc5ded118d7c | 492 | * Address : 0x1F |
Sinan Divarci |
0:dc5ded118d7c | 493 | */ |
Sinan Divarci |
0:dc5ded118d7c | 494 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 495 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 496 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 497 | unsigned char rev_num : 3; /**< Revision Number of chip */ |
Sinan Divarci |
0:dc5ded118d7c | 498 | unsigned char : 5; |
Sinan Divarci |
0:dc5ded118d7c | 499 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 500 | } max41470_reg_rev_num_t; |
Sinan Divarci |
0:dc5ded118d7c | 501 | |
Sinan Divarci |
0:dc5ded118d7c | 502 | /** |
Sinan Divarci |
0:dc5ded118d7c | 503 | * @brief STATUS Register |
Sinan Divarci |
0:dc5ded118d7c | 504 | * |
Sinan Divarci |
0:dc5ded118d7c | 505 | * Address : 0x27 |
Sinan Divarci |
0:dc5ded118d7c | 506 | */ |
Sinan Divarci |
0:dc5ded118d7c | 507 | typedef union { |
Sinan Divarci |
0:dc5ded118d7c | 508 | unsigned char raw; |
Sinan Divarci |
0:dc5ded118d7c | 509 | struct { |
Sinan Divarci |
0:dc5ded118d7c | 510 | unsigned char pll_lock : 1; /**< PLL Lock Status |
Sinan Divarci |
0:dc5ded118d7c | 511 | 0x0: PLL is not locked 0x1: PLL is locked */ |
Sinan Divarci |
0:dc5ded118d7c | 512 | unsigned char reserved : 1; /**< Reserved */ |
Sinan Divarci |
0:dc5ded118d7c | 513 | unsigned char : 6; |
Sinan Divarci |
0:dc5ded118d7c | 514 | } bits; |
Sinan Divarci |
0:dc5ded118d7c | 515 | } max41470_reg_status_t; |
Sinan Divarci |
0:dc5ded118d7c | 516 | |
Sinan Divarci |
0:dc5ded118d7c | 517 | /** |
Sinan Divarci |
0:dc5ded118d7c | 518 | * @brief Register Set |
Sinan Divarci |
0:dc5ded118d7c | 519 | * |
Sinan Divarci |
0:dc5ded118d7c | 520 | * |
Sinan Divarci |
0:dc5ded118d7c | 521 | */ |
Sinan Divarci |
0:dc5ded118d7c | 522 | typedef struct { |
Sinan Divarci |
0:dc5ded118d7c | 523 | max41470_reg_demod_t reg_demod; |
Sinan Divarci |
0:dc5ded118d7c | 524 | max41470_reg_agc_t reg_agc; |
Sinan Divarci |
0:dc5ded118d7c | 525 | max41470_reg_if_chf_sel_t reg_if_chf_sel; |
Sinan Divarci |
0:dc5ded118d7c | 526 | max41470_reg_pdf_cfg_t reg_pdf_cfg; |
Sinan Divarci |
0:dc5ded118d7c | 527 | max41470_reg_ath_cfg1_t reg_ath_cfg1; |
Sinan Divarci |
0:dc5ded118d7c | 528 | max41470_reg_ath_cfg2_t reg_ath_cfg2; |
Sinan Divarci |
0:dc5ded118d7c | 529 | max41470_reg_ath_cfg3_t reg_ath_cfg3; |
Sinan Divarci |
0:dc5ded118d7c | 530 | max41470_reg_afc_cfg1_t reg_afc_cfg1; |
Sinan Divarci |
0:dc5ded118d7c | 531 | max41470_reg_afc_cfg2_t reg_afc_cfg2; |
Sinan Divarci |
0:dc5ded118d7c | 532 | max41470_reg_lo_ctr_freq3_t reg_lo_ctr_freq3; |
Sinan Divarci |
0:dc5ded118d7c | 533 | max41470_reg_lo_ctr_freq2_t reg_lo_ctr_freq2; |
Sinan Divarci |
0:dc5ded118d7c | 534 | max41470_reg_lo_ctr_freq1_t reg_lo_ctr_freq1; |
Sinan Divarci |
0:dc5ded118d7c | 535 | max41470_reg_preamble_cfg1_t reg_preamble_cfg1; |
Sinan Divarci |
0:dc5ded118d7c | 536 | max41470_reg_preamble_word1_t reg_preamble_word1; |
Sinan Divarci |
0:dc5ded118d7c | 537 | max41470_reg_preamble_word2_t reg_preamble_word2; |
Sinan Divarci |
0:dc5ded118d7c | 538 | max41470_reg_rssi_t reg_rssi; |
Sinan Divarci |
0:dc5ded118d7c | 539 | max41470_reg_fei_t reg_fei; |
Sinan Divarci |
0:dc5ded118d7c | 540 | max41470_reg_pdf_out_t reg_pdf_out; |
Sinan Divarci |
0:dc5ded118d7c | 541 | max41470_reg_isr_t reg_isr; |
Sinan Divarci |
0:dc5ded118d7c | 542 | max41470_reg_cdr_cfg1_t reg_cdr_cfg1; |
Sinan Divarci |
0:dc5ded118d7c | 543 | max41470_reg_state_ctrl1_t reg_state_ctrl1; |
Sinan Divarci |
0:dc5ded118d7c | 544 | max41470_reg_state_ctrl2_t reg_state_ctrl2; |
Sinan Divarci |
0:dc5ded118d7c | 545 | max41470_reg_state_ctrl3_t reg_state_ctrl3; |
Sinan Divarci |
0:dc5ded118d7c | 546 | max41470_reg_wut1_t reg_wut1; |
Sinan Divarci |
0:dc5ded118d7c | 547 | max41470_reg_wut2_t reg_wut2; |
Sinan Divarci |
0:dc5ded118d7c | 548 | max41470_reg_afe_ctl1_t reg_afe_ctl1; |
Sinan Divarci |
0:dc5ded118d7c | 549 | max41470_reg_ir_adjust_t reg_ir_adjust; |
Sinan Divarci |
0:dc5ded118d7c | 550 | max41470_reg_part_num_t reg_part_num; |
Sinan Divarci |
0:dc5ded118d7c | 551 | max41470_reg_rev_num_t reg_rev_num; |
Sinan Divarci |
0:dc5ded118d7c | 552 | max41470_reg_status_t reg_status; |
Sinan Divarci |
0:dc5ded118d7c | 553 | } max41470_reg_map_t; |
Sinan Divarci |
0:dc5ded118d7c | 554 | |
Sinan Divarci |
0:dc5ded118d7c | 555 | #endif /* MAX41470_REGS_H_ */ |