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MAX30003
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Dependents: MAX_IOT_KIT MAX30003WING_Demo_QRS_RK_Thread MAX30003WING_monitorhealth_beta_test1_ChannelID_5172021 MAX30003WING_monitorhealth_beta_test1_2ChannelID_5192021_copy ... more
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MAX30003.h
00001 /******************************************************************************* 00002 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 ******************************************************************************* 00032 */ 00033 00034 00035 #ifndef _MAX30003_H_ 00036 #define _MAX30003_H_ 00037 00038 00039 #include "mbed.h" 00040 00041 00042 /** 00043 * @brief Library for MAX30003\n 00044 * The MAX30003 is a complete, biopotential, analog frontend solution for 00045 * wearable applications. It offers high performance for clinical and fitness 00046 * applications, with ultra-low power for long battery life. The MAX30003 is a 00047 * single biopotential channel providing ECG waveforms and heart rate detection. 00048 * 00049 * @code 00050 * #include "mbed.h" 00051 * #include "max32630fthr.h" 00052 * #include "MAX30003.h" 00053 * 00054 * MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3); 00055 * 00056 * int main(void) 00057 * { 00058 * DigitalOut rLed(LED1, 1); 00059 * DigitalOut gLed(LED2, 1); 00060 * 00061 * Serial pc(USBTX, USBRX); 00062 * pc.baud(115200); 00063 * 00064 * SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); 00065 * MAX30003 ecgAfe(spiBus, P5_3); 00066 * 00067 * while(1) 00068 * { 00069 * gLed = !gLed; 00070 * wait(0.1); 00071 * } 00072 * } 00073 * @endcode 00074 */ 00075 class MAX30003 00076 { 00077 public: 00078 00079 ///MAX30003 Registers 00080 enum Registers_e 00081 { 00082 NO_OP = 0x00, 00083 STATUS = 0x01, 00084 EN_INT = 0x02, 00085 EN_INT2 = 0x03, 00086 MNGR_INT = 0x04, 00087 MNGR_DYN = 0x05, 00088 SW_RST = 0x08, 00089 SYNCH = 0x09, 00090 FIFO_RST = 0x0A, 00091 INFO = 0x0F, 00092 CNFG_GEN = 0x10, 00093 CNFG_ALL = 0x12, 00094 CNFG_EMUX = 0x14, 00095 CNFG_ECG = 0x15, 00096 CNFG_RTOR1 = 0x1D, 00097 CNFG_RTOR2 = 0x1E, 00098 ECG_FIFO_BURST = 0x20, 00099 ECG_FIFO = 0x21, 00100 RTOR = 0x25, 00101 NO_OP2 = 0x7F 00102 }; 00103 00104 ///Status register bits 00105 union Status_u 00106 { 00107 ///Access all bits 00108 uint32_t all; 00109 00110 ///Access individual bits 00111 struct BitField_s 00112 { 00113 uint32_t loff_nl : 1; 00114 uint32_t loff_nh : 1; 00115 uint32_t loff_pl : 1; 00116 uint32_t loff_ph : 1; 00117 uint32_t reserved1 : 4; 00118 uint32_t pllint : 1; 00119 uint32_t samp : 1; 00120 uint32_t rrint : 1; 00121 uint32_t lonint : 1; 00122 uint32_t reserved2 : 8; 00123 uint32_t dcloffint : 1; 00124 uint32_t fstint : 1; 00125 uint32_t eovf : 1; 00126 uint32_t eint : 1; 00127 uint32_t reserved3 : 8; 00128 }bits; 00129 }; 00130 00131 ///Enable Interrupt registers bits 00132 union EnableInterrupts_u 00133 { 00134 ///Access all bits 00135 uint32_t all; 00136 00137 ///Access individual bits 00138 struct BitField_s 00139 { 00140 uint32_t intb_type : 2; 00141 uint32_t reserved1 : 6; 00142 uint32_t en_pllint : 1; 00143 uint32_t en_samp : 1; 00144 uint32_t en_rrint : 1; 00145 uint32_t en_loint : 1; 00146 uint32_t reserved2 : 8; 00147 uint32_t en_dcloffint : 1; 00148 uint32_t en_fstint : 1; 00149 uint32_t en_eovf : 1; 00150 uint32_t en_eint : 1; 00151 uint32_t reserved3 : 8; 00152 }bits; 00153 }; 00154 00155 ///Manage Interrupt register bits 00156 union ManageInterrupts_u 00157 { 00158 ///Access all bits 00159 uint32_t all; 00160 00161 ///Access individual bits 00162 struct BitField_s 00163 { 00164 uint32_t samp_it : 4; 00165 uint32_t clr_samp : 1; 00166 uint32_t reserved1 : 1; 00167 uint32_t clr_rrint : 2; 00168 uint32_t clr_fast : 1; 00169 uint32_t reserved2 : 12; 00170 uint32_t efit : 5; 00171 uint32_t reserved3 : 8; 00172 }bits; 00173 }; 00174 00175 ///Manage Dynamic Modes register bits 00176 union ManageDynamicModes_u 00177 { 00178 ///Access all bits 00179 uint32_t all; 00180 00181 ///Access individual bits 00182 struct BitField_s 00183 { 00184 uint32_t reserved1 : 16; 00185 uint32_t fast_th : 6; 00186 uint32_t fast : 2; 00187 uint32_t reserved2 : 8; 00188 }bits; 00189 }; 00190 00191 ///General Configuration bits 00192 union GeneralConfiguration_u 00193 { 00194 ///Access all bits 00195 uint32_t all; 00196 00197 ///Access individual bits 00198 struct BitField_s 00199 { 00200 uint32_t rbiasn : 1; 00201 uint32_t rbiasp : 1; 00202 uint32_t rbiasv : 2; 00203 uint32_t en_rbias : 2; 00204 uint32_t vth : 2; 00205 uint32_t imag : 3; 00206 uint32_t ipol : 1; 00207 uint32_t en_dcloff : 2; 00208 uint32_t reserved1 : 5; 00209 uint32_t en_ecg : 1; 00210 uint32_t fmstr : 2; 00211 uint32_t en_ulp_lon : 2; 00212 uint32_t reserved2 : 8; 00213 }bits; 00214 }; 00215 00216 ///Cal Configuration bits 00217 union CalConfiguration_u 00218 { 00219 ///Access all bits 00220 uint32_t all; 00221 00222 ///Access individual bits 00223 struct BitField_s 00224 { 00225 uint32_t thigh : 11; 00226 uint32_t fifty : 1; 00227 uint32_t fcal : 3; 00228 uint32_t reserved1 : 5; 00229 uint32_t vmag : 1; 00230 uint32_t vmode : 1; 00231 uint32_t en_vcal : 1; 00232 uint32_t reserved2 : 9; 00233 00234 }bits; 00235 }; 00236 00237 ///Mux Configuration bits 00238 union MuxConfiguration_u 00239 { 00240 ///Access all bits 00241 uint32_t all; 00242 00243 ///Access individual bits 00244 struct BitField_s 00245 { 00246 uint32_t reserved1 : 16; 00247 uint32_t caln_sel : 2; 00248 uint32_t calp_sel : 2; 00249 uint32_t openn : 1; 00250 uint32_t openp : 1; 00251 uint32_t reserved2 : 1; 00252 uint32_t pol : 1; 00253 uint32_t reserved3 : 8; 00254 }bits; 00255 }; 00256 00257 ///ECG Configuration bits 00258 union ECGConfiguration_u 00259 { 00260 ///Access all bits 00261 uint32_t all; 00262 00263 ///Access individual bits 00264 struct BitField_s 00265 { 00266 uint32_t reserved1 : 12; 00267 uint32_t dlpf : 2; 00268 uint32_t dhpf : 1; 00269 uint32_t reserved2 : 1; 00270 uint32_t gain : 2; 00271 uint32_t reserved3 : 4; 00272 uint32_t rate : 2; 00273 uint32_t reserved4 : 8; 00274 }bits; 00275 }; 00276 00277 ///RtoR1 Configuration bits 00278 union RtoR1Configuration_u 00279 { 00280 ///Access all bits 00281 uint32_t all; 00282 00283 ///Access individual bits 00284 struct BitField_s 00285 { 00286 uint32_t reserved1 : 8; 00287 uint32_t ptsf : 4; 00288 uint32_t pavg : 2; 00289 uint32_t reserved2 : 1; 00290 uint32_t en_rtor : 1; 00291 uint32_t rgain : 4; 00292 uint32_t wndw : 4; 00293 uint32_t reserved3 : 8; 00294 }bits; 00295 }; 00296 00297 ///RtoR2 Configuration bits 00298 union RtoR2Configuration_u 00299 { 00300 ///Access all bits 00301 uint32_t all; 00302 00303 ///Access individual bits 00304 struct BitField_s 00305 { 00306 uint32_t reserved1 : 8; 00307 uint32_t rhsf : 3; 00308 uint32_t reserved2 : 1; 00309 uint32_t ravg : 2; 00310 uint32_t reserved3 : 2; 00311 uint32_t hoff : 6; 00312 uint32_t reserved4 : 10; 00313 }bits; 00314 }; 00315 00316 ///@brief MAX30003 Constructor 00317 ///@param spiBus - Reference to spi interface 00318 ///@param cs - Pin used for chip select 00319 MAX30003(SPI &spiBus, PinName cs); 00320 00321 ///@brief MAX30003 Destructor 00322 ~MAX30003(); 00323 00324 ///@brief Read given register.\n 00325 /// 00326 ///On Entry: 00327 ///@param[in] reg - Register to read 00328 /// 00329 ///On Exit: 00330 /// 00331 ///@returns Read data 00332 uint32_t readRegister(const Registers_e reg); 00333 00334 ///@brief Write given register.\n 00335 /// 00336 ///On Entry: 00337 ///@param[in] reg - Register to write 00338 ///@param[in] data - Data to write 00339 /// 00340 ///@returns None 00341 void writeRegister(const Registers_e reg, const uint32_t data); 00342 00343 private: 00344 00345 SPI &m_spiBus; 00346 DigitalOut m_cs; 00347 }; 00348 00349 #endif /* _MAX30003_H_ */ 00350
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