Maxim Integrated / MAX30003

Library for MAX30003

Dependents:   MAX_IOT_KIT MAX_IOT_KIT MAX30003WING_Demo_QRS_RK_Thread MAX30003WING_monitorhealth_beta_test1_ChannelID_5172021 ... more

MAX30003.h@0:5d58c707f629, 2017-05-12 (annotated)

Committer:
j3
Date:
Fri May 12 00:10:42 2017 +0000
Revision:
0:5d58c707f629
Child:
1:313e09ea1738
init commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:5d58c707f629 1 /*******************************************************************************
j3 0:5d58c707f629 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:5d58c707f629 3 *
j3 0:5d58c707f629 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:5d58c707f629 5 * copy of this software and associated documentation files (the "Software"),
j3 0:5d58c707f629 6 * to deal in the Software without restriction, including without limitation
j3 0:5d58c707f629 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:5d58c707f629 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:5d58c707f629 9 * Software is furnished to do so, subject to the following conditions:
j3 0:5d58c707f629 10 *
j3 0:5d58c707f629 11 * The above copyright notice and this permission notice shall be included
j3 0:5d58c707f629 12 * in all copies or substantial portions of the Software.
j3 0:5d58c707f629 13 *
j3 0:5d58c707f629 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:5d58c707f629 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:5d58c707f629 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:5d58c707f629 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:5d58c707f629 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:5d58c707f629 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:5d58c707f629 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:5d58c707f629 21 *
j3 0:5d58c707f629 22 * Except as contained in this notice, the name of Maxim Integrated
j3 0:5d58c707f629 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:5d58c707f629 24 * Products, Inc. Branding Policy.
j3 0:5d58c707f629 25 *
j3 0:5d58c707f629 26 * The mere transfer of this software does not imply any licenses
j3 0:5d58c707f629 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:5d58c707f629 28 * trademarks, maskwork rights, or any other form of intellectual
j3 0:5d58c707f629 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:5d58c707f629 30 * ownership rights.
j3 0:5d58c707f629 31 *******************************************************************************
j3 0:5d58c707f629 32 */
j3 0:5d58c707f629 33
j3 0:5d58c707f629 34
j3 0:5d58c707f629 35 #ifndef _MAX30003_H_
j3 0:5d58c707f629 36 #define _MAX30003_H_
j3 0:5d58c707f629 37
j3 0:5d58c707f629 38
j3 0:5d58c707f629 39 #include "mbed.h"
j3 0:5d58c707f629 40
j3 0:5d58c707f629 41
j3 0:5d58c707f629 42 /**
j3 0:5d58c707f629 43 * @brief Library for MAX30003\n
j3 0:5d58c707f629 44 * The MAX30003 is a complete, biopotential, analog frontend solution for
j3 0:5d58c707f629 45 * wearable applications. It offers high performance for clinical and fitness
j3 0:5d58c707f629 46 * applications, with ultra-low power for long battery life. The MAX30003 is a
j3 0:5d58c707f629 47 * single biopotential channel providing ECG waveforms and heart rate detection.
j3 0:5d58c707f629 48 *
j3 0:5d58c707f629 49 * @code
j3 0:5d58c707f629 50 * #include "mbed.h"
j3 0:5d58c707f629 51 * #include "max32630fthr.h"
j3 0:5d58c707f629 52 * #include "MAX30003.h"
j3 0:5d58c707f629 53 *
j3 0:5d58c707f629 54 * MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
j3 0:5d58c707f629 55 *
j3 0:5d58c707f629 56 * int main(void)
j3 0:5d58c707f629 57 * {
j3 0:5d58c707f629 58 * DigitalOut rLed(LED1, 1);
j3 0:5d58c707f629 59 * DigitalOut gLed(LED2, 1);
j3 0:5d58c707f629 60 *
j3 0:5d58c707f629 61 * Serial pc(USBTX, USBRX);
j3 0:5d58c707f629 62 * pc.baud(115200);
j3 0:5d58c707f629 63 *
j3 0:5d58c707f629 64 * SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK);
j3 0:5d58c707f629 65 * MAX30003 ecgAfe(spiBus, P5_3);
j3 0:5d58c707f629 66 *
j3 0:5d58c707f629 67 * while(1)
j3 0:5d58c707f629 68 * {
j3 0:5d58c707f629 69 * gLed = !gLed;
j3 0:5d58c707f629 70 * wait(0.1);
j3 0:5d58c707f629 71 * }
j3 0:5d58c707f629 72 * }
j3 0:5d58c707f629 73 * @endcode
j3 0:5d58c707f629 74 */
j3 0:5d58c707f629 75 class MAX30003
j3 0:5d58c707f629 76 {
j3 0:5d58c707f629 77 public:
j3 0:5d58c707f629 78
j3 0:5d58c707f629 79 ///MAX30003 Registers
j3 0:5d58c707f629 80 enum Registers_e
j3 0:5d58c707f629 81 {
j3 0:5d58c707f629 82 NO_OP = 0x00,
j3 0:5d58c707f629 83 STATUS = 0x01,
j3 0:5d58c707f629 84 EN_INT = 0x02,
j3 0:5d58c707f629 85 EN_INT2 = 0x03,
j3 0:5d58c707f629 86 MNGR_INT = 0x04,
j3 0:5d58c707f629 87 MNGR_DYN = 0x05,
j3 0:5d58c707f629 88 SW_RST = 0x08,
j3 0:5d58c707f629 89 SYNCH = 0x09,
j3 0:5d58c707f629 90 FIFO_RST = 0x0A,
j3 0:5d58c707f629 91 INFO = 0x0F,
j3 0:5d58c707f629 92 CNFG_GEN = 0x10,
j3 0:5d58c707f629 93 CNFG_ALL = 0x12,
j3 0:5d58c707f629 94 CNFG_EMUX = 0x14,
j3 0:5d58c707f629 95 CNFG_ECG = 0x15,
j3 0:5d58c707f629 96 CNFG_RTOR1 = 0x1D,
j3 0:5d58c707f629 97 CNFG_RTOR2 = 0x1E,
j3 0:5d58c707f629 98 ECG_FIFO_BURST = 0x20,
j3 0:5d58c707f629 99 ECG_FIFO = 0x21,
j3 0:5d58c707f629 100 RTOR = 0x25,
j3 0:5d58c707f629 101 NO_OP2 = 0x7F
j3 0:5d58c707f629 102 };
j3 0:5d58c707f629 103
j3 0:5d58c707f629 104 ///Status register bits
j3 0:5d58c707f629 105 union Status_u
j3 0:5d58c707f629 106 {
j3 0:5d58c707f629 107 ///Access all bits
j3 0:5d58c707f629 108 uint32_t all;
j3 0:5d58c707f629 109
j3 0:5d58c707f629 110 ///Access individual bits
j3 0:5d58c707f629 111 struct BitField_s
j3 0:5d58c707f629 112 {
j3 0:5d58c707f629 113 uint32_t loff_nl : 1;
j3 0:5d58c707f629 114 uint32_t loff_nh : 1;
j3 0:5d58c707f629 115 uint32_t loff_pl : 1;
j3 0:5d58c707f629 116 uint32_t loff_ph : 1;
j3 0:5d58c707f629 117 uint32_t reserved1 : 4;
j3 0:5d58c707f629 118 uint32_t pllint : 1;
j3 0:5d58c707f629 119 uint32_t samp : 1;
j3 0:5d58c707f629 120 uint32_t rrint : 1;
j3 0:5d58c707f629 121 uint32_t lonint : 1;
j3 0:5d58c707f629 122 uint32_t reserved2 : 8;
j3 0:5d58c707f629 123 uint32_t dcloffint : 1;
j3 0:5d58c707f629 124 uint32_t fstint : 1;
j3 0:5d58c707f629 125 uint32_t eovf : 1;
j3 0:5d58c707f629 126 uint32_t eint : 1;
j3 0:5d58c707f629 127 uint32_t reserved3 : 8;
j3 0:5d58c707f629 128 }bits;
j3 0:5d58c707f629 129 };
j3 0:5d58c707f629 130
j3 0:5d58c707f629 131 ///Enable Interrupt registers bits
j3 0:5d58c707f629 132 union EnableInterrupts_u
j3 0:5d58c707f629 133 {
j3 0:5d58c707f629 134 ///Access all bits
j3 0:5d58c707f629 135 uint32_t all;
j3 0:5d58c707f629 136
j3 0:5d58c707f629 137 ///Access individual bits
j3 0:5d58c707f629 138 struct BitField_s
j3 0:5d58c707f629 139 {
j3 0:5d58c707f629 140 uint32_t intb_type : 2;
j3 0:5d58c707f629 141 uint32_t reserved1 : 6;
j3 0:5d58c707f629 142 uint32_t en_pllint : 1;
j3 0:5d58c707f629 143 uint32_t en_samp : 1;
j3 0:5d58c707f629 144 uint32_t en_rrint : 1;
j3 0:5d58c707f629 145 uint32_t en_loint : 1;
j3 0:5d58c707f629 146 uint32_t reserved2 : 8;
j3 0:5d58c707f629 147 uint32_t en_dcloffint : 1;
j3 0:5d58c707f629 148 uint32_t en_fstint : 1;
j3 0:5d58c707f629 149 uint32_t en_eovf : 1;
j3 0:5d58c707f629 150 uint32_t en_eint : 1;
j3 0:5d58c707f629 151 uint32_t reserved3 : 8;
j3 0:5d58c707f629 152 }bits;
j3 0:5d58c707f629 153 };
j3 0:5d58c707f629 154
j3 0:5d58c707f629 155 ///Manage Interrupt register bits
j3 0:5d58c707f629 156 union ManageInterrupts_u
j3 0:5d58c707f629 157 {
j3 0:5d58c707f629 158 ///Access all bits
j3 0:5d58c707f629 159 uint32_t all;
j3 0:5d58c707f629 160
j3 0:5d58c707f629 161 ///Access individual bits
j3 0:5d58c707f629 162 struct BitField_s
j3 0:5d58c707f629 163 {
j3 0:5d58c707f629 164 uint32_t samp_it : 4;
j3 0:5d58c707f629 165 uint32_t clr_samp : 1;
j3 0:5d58c707f629 166 uint32_t reserved1 : 1;
j3 0:5d58c707f629 167 uint32_t clr_rrint : 2;
j3 0:5d58c707f629 168 uint32_t clr_fast : 1;
j3 0:5d58c707f629 169 uint32_t reserved2 : 12;
j3 0:5d58c707f629 170 uint32_t efit : 5;
j3 0:5d58c707f629 171 uint32_t reserved3 : 8;
j3 0:5d58c707f629 172 }bits;
j3 0:5d58c707f629 173 };
j3 0:5d58c707f629 174
j3 0:5d58c707f629 175 ///Manage Dynamic Modes register bits
j3 0:5d58c707f629 176 union ManageDynamicModes_u
j3 0:5d58c707f629 177 {
j3 0:5d58c707f629 178 ///Access all bits
j3 0:5d58c707f629 179 uint32_t all;
j3 0:5d58c707f629 180
j3 0:5d58c707f629 181 ///Access individual bits
j3 0:5d58c707f629 182 struct BitField_s
j3 0:5d58c707f629 183 {
j3 0:5d58c707f629 184 uint32_t reserved1 : 16;
j3 0:5d58c707f629 185 uint32_t fast_th : 6;
j3 0:5d58c707f629 186 uint32_t fast : 2;
j3 0:5d58c707f629 187 uint32_t reserved2 : 8;
j3 0:5d58c707f629 188 }bits;
j3 0:5d58c707f629 189 };
j3 0:5d58c707f629 190
j3 0:5d58c707f629 191 ///General Configuration bits
j3 0:5d58c707f629 192 union GeneralConfiguration_u
j3 0:5d58c707f629 193 {
j3 0:5d58c707f629 194 ///Access all bits
j3 0:5d58c707f629 195 uint32_t all;
j3 0:5d58c707f629 196
j3 0:5d58c707f629 197 ///Access individual bits
j3 0:5d58c707f629 198 struct BitField_s
j3 0:5d58c707f629 199 {
j3 0:5d58c707f629 200 uint32_t rbiasn : 1;
j3 0:5d58c707f629 201 uint32_t rbiasp : 1;
j3 0:5d58c707f629 202 uint32_t rbiasv : 2;
j3 0:5d58c707f629 203 uint32_t en_rbias : 2;
j3 0:5d58c707f629 204 uint32_t vth : 2;
j3 0:5d58c707f629 205 uint32_t imag : 3;
j3 0:5d58c707f629 206 uint32_t ipol : 1;
j3 0:5d58c707f629 207 uint32_t en_dcloff : 2;
j3 0:5d58c707f629 208 uint32_t reserved1 : 5;
j3 0:5d58c707f629 209 uint32_t en_ecg : 1;
j3 0:5d58c707f629 210 uint32_t fmstr : 2;
j3 0:5d58c707f629 211 uint32_t en_ulp_lon : 2;
j3 0:5d58c707f629 212 uint32_t reserved2 : 8;
j3 0:5d58c707f629 213 }bits;
j3 0:5d58c707f629 214 };
j3 0:5d58c707f629 215
j3 0:5d58c707f629 216 ///Cal Configuration bits
j3 0:5d58c707f629 217 union CalConfiguration_u
j3 0:5d58c707f629 218 {
j3 0:5d58c707f629 219 ///Access all bits
j3 0:5d58c707f629 220 uint32_t all;
j3 0:5d58c707f629 221
j3 0:5d58c707f629 222 ///Access individual bits
j3 0:5d58c707f629 223 struct BitField_s
j3 0:5d58c707f629 224 {
j3 0:5d58c707f629 225 uint32_t thigh : 11;
j3 0:5d58c707f629 226 uint32_t fifty : 1;
j3 0:5d58c707f629 227 uint32_t fcal : 3;
j3 0:5d58c707f629 228 uint32_t reserved1 : 5;
j3 0:5d58c707f629 229 uint32_t vmag : 1;
j3 0:5d58c707f629 230 uint32_t vmode : 1;
j3 0:5d58c707f629 231 uint32_t en_vcal : 1;
j3 0:5d58c707f629 232 uint32_t reserved2 : 9;
j3 0:5d58c707f629 233
j3 0:5d58c707f629 234 }bits;
j3 0:5d58c707f629 235 };
j3 0:5d58c707f629 236
j3 0:5d58c707f629 237 ///Mux Configuration bits
j3 0:5d58c707f629 238 union MuxConfiguration_u
j3 0:5d58c707f629 239 {
j3 0:5d58c707f629 240 ///Access all bits
j3 0:5d58c707f629 241 uint32_t all;
j3 0:5d58c707f629 242
j3 0:5d58c707f629 243 ///Access individual bits
j3 0:5d58c707f629 244 struct BitField_s
j3 0:5d58c707f629 245 {
j3 0:5d58c707f629 246 uint32_t reserved1 : 16;
j3 0:5d58c707f629 247 uint32_t caln_sel : 2;
j3 0:5d58c707f629 248 uint32_t calp_sel : 2;
j3 0:5d58c707f629 249 uint32_t openn : 1;
j3 0:5d58c707f629 250 uint32_t openp : 1;
j3 0:5d58c707f629 251 uint32_t reserved2 : 1;
j3 0:5d58c707f629 252 uint32_t pol : 1;
j3 0:5d58c707f629 253 uint32_t reserved3 : 8;
j3 0:5d58c707f629 254 }bits;
j3 0:5d58c707f629 255 };
j3 0:5d58c707f629 256
j3 0:5d58c707f629 257 ///ECG Configuration bits
j3 0:5d58c707f629 258 union ECGConfiguration_u
j3 0:5d58c707f629 259 {
j3 0:5d58c707f629 260 ///Access all bits
j3 0:5d58c707f629 261 uint32_t all;
j3 0:5d58c707f629 262
j3 0:5d58c707f629 263 ///Access individual bits
j3 0:5d58c707f629 264 struct BitField_s
j3 0:5d58c707f629 265 {
j3 0:5d58c707f629 266 uint32_t reserved1 : 12;
j3 0:5d58c707f629 267 uint32_t dlpf : 2;
j3 0:5d58c707f629 268 uint32_t dhpf : 1;
j3 0:5d58c707f629 269 uint32_t reserved2 : 1;
j3 0:5d58c707f629 270 uint32_t gain : 2;
j3 0:5d58c707f629 271 uint32_t reserved3 : 4;
j3 0:5d58c707f629 272 uint32_t rate : 2;
j3 0:5d58c707f629 273 uint32_t reserved4 : 8;
j3 0:5d58c707f629 274 }bits;
j3 0:5d58c707f629 275 };
j3 0:5d58c707f629 276
j3 0:5d58c707f629 277 ///RtoR1 Configuration bits
j3 0:5d58c707f629 278 union RtoR1Configuration_u
j3 0:5d58c707f629 279 {
j3 0:5d58c707f629 280 ///Access all bits
j3 0:5d58c707f629 281 uint32_t all;
j3 0:5d58c707f629 282
j3 0:5d58c707f629 283 ///Access individual bits
j3 0:5d58c707f629 284 struct BitField_s
j3 0:5d58c707f629 285 {
j3 0:5d58c707f629 286 uint32_t reserved1 : 8;
j3 0:5d58c707f629 287 uint32_t ptsf : 4;
j3 0:5d58c707f629 288 uint32_t pavg : 2;
j3 0:5d58c707f629 289 uint32_t reserved2 : 1;
j3 0:5d58c707f629 290 uint32_t en_rtor : 1;
j3 0:5d58c707f629 291 uint32_t rgain : 4;
j3 0:5d58c707f629 292 uint32_t wndw : 4;
j3 0:5d58c707f629 293 uint32_t reserved3 : 8;
j3 0:5d58c707f629 294 }bits;
j3 0:5d58c707f629 295 };
j3 0:5d58c707f629 296
j3 0:5d58c707f629 297 ///RtoR2 Configuration bits
j3 0:5d58c707f629 298 union RtoR2Configuration_u
j3 0:5d58c707f629 299 {
j3 0:5d58c707f629 300 ///Access all bits
j3 0:5d58c707f629 301 uint32_t all;
j3 0:5d58c707f629 302
j3 0:5d58c707f629 303 ///Access individual bits
j3 0:5d58c707f629 304 struct BitField_s
j3 0:5d58c707f629 305 {
j3 0:5d58c707f629 306 uint32_t reserved1 : 8;
j3 0:5d58c707f629 307 uint32_t rhsf : 3;
j3 0:5d58c707f629 308 uint32_t reserved2 : 1;
j3 0:5d58c707f629 309 uint32_t ravg : 2;
j3 0:5d58c707f629 310 uint32_t reserved3 : 2;
j3 0:5d58c707f629 311 uint32_t hoff : 6;
j3 0:5d58c707f629 312 uint32_t reserved4 : 10;
j3 0:5d58c707f629 313 }bits;
j3 0:5d58c707f629 314 };
j3 0:5d58c707f629 315
j3 0:5d58c707f629 316 ///@brief MAX30003 Constructor
j3 0:5d58c707f629 317 ///@param spiBus - Reference to spi interface
j3 0:5d58c707f629 318 ///@param cs - Pin used for chip select
j3 0:5d58c707f629 319 MAX30003(SPI &spiBus, PinName cs);
j3 0:5d58c707f629 320
j3 0:5d58c707f629 321 ///@brief MAX30003 Destructor
j3 0:5d58c707f629 322 ~MAX30003();
j3 0:5d58c707f629 323
j3 0:5d58c707f629 324 ///@brief Read given register.\n
j3 0:5d58c707f629 325 ///
j3 0:5d58c707f629 326 ///On Entry:
j3 0:5d58c707f629 327 ///@param[in] reg - Register to read
j3 0:5d58c707f629 328 ///
j3 0:5d58c707f629 329 ///On Exit:
j3 0:5d58c707f629 330 ///
j3 0:5d58c707f629 331 ///@returns Read data
j3 0:5d58c707f629 332 uint32_t readRegister(const Registers_e reg);
j3 0:5d58c707f629 333
j3 0:5d58c707f629 334 ///@brief Write given register.\n
j3 0:5d58c707f629 335 ///
j3 0:5d58c707f629 336 ///On Entry:
j3 0:5d58c707f629 337 ///@param[in] reg - Register to write
j3 0:5d58c707f629 338 ///@param[in] data - Data to write
j3 0:5d58c707f629 339 ///
j3 0:5d58c707f629 340 ///@returns None
j3 0:5d58c707f629 341 void writeRegister(const Registers_e reg, const uint32_t data);
j3 0:5d58c707f629 342
j3 0:5d58c707f629 343 private:
j3 0:5d58c707f629 344
j3 0:5d58c707f629 345 SPI &m_spiBus;
j3 0:5d58c707f629 346 DigitalOut m_cs;
j3 0:5d58c707f629 347 };
j3 0:5d58c707f629 348
j3 0:5d58c707f629 349 #endif /* _MAX30003_H_ */
j3 0:5d58c707f629 350
j3 0:5d58c707f629 351 ///@brief fx documentation template.\n
j3 0:5d58c707f629 352 ///
j3 0:5d58c707f629 353 ///On Entry:
j3 0:5d58c707f629 354 ///@param[in] none
j3 0:5d58c707f629 355 ///
j3 0:5d58c707f629 356 ///On Exit:
j3 0:5d58c707f629 357 ///@param[out] none
j3 0:5d58c707f629 358 ///
j3 0:5d58c707f629 359 ///@returns none
j3 0:5d58c707f629 360