Maxim Integrated
Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.
Dependencies: MaximTinyTester MAX11410 CmdLine USBDevice
Diff: MAX11410.cpp
- Revision:
- 35:8aa5dffe523d
- Parent:
- 25:a2afb91c605a
--- a/MAX11410.cpp Sun Sep 22 18:23:10 2019 -0700
+++ b/MAX11410.cpp Mon Nov 11 23:30:04 2019 +0000
@@ -1,4 +1,4 @@
-// /*******************************************************************************
+// /*******************************************************************************
// * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
// *
// * Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,10 +43,15 @@
// Device Name = MAX11410
// Device Description = 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC
+// Device DeviceBriefDescription = 24-bit 1.9ksps Delta-Sigma ADC
// Device Manufacturer = Maxim Integrated
// Device PartNumber = MAX11410ATI+
// Device RegValue_Width = DataWidth16bit_HL
//
+// ADC MaxOutputDataRate = 1.9ksps
+// ADC NumChannels = 10
+// ADC ResolutionBits = 24
+//
// SPI CS = ActiveLow
// SPI FrameStart = CS
// SPI CPOL = 0
@@ -81,7 +86,7 @@
// SPI CPHA = 0
// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
// SPI SCLK Idle Low
- m_SPI_dataMode = 0; //SPI_MODE0 // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
+ m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
// SPI SCLKMaxMHz = 8
@@ -89,6 +94,7 @@
//#define SPI_SCLK_Hz 48000000 // 48MHz
//#define SPI_SCLK_Hz 24000000 // 24MHz
//#define SPI_SCLK_Hz 12000000 // 12MHz
+ //#define SPI_SCLK_Hz 6000000 // 6MHz
//#define SPI_SCLK_Hz 4000000 // 4MHz
//#define SPI_SCLK_Hz 2000000 // 2MHz
//#define SPI_SCLK_Hz 1000000 // 1MHz
@@ -153,6 +159,11 @@
//
// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
//~ interrupts();
+ // Optional Diagnostic function to print SPI transactions
+ if (onSPIprint)
+ {
+ onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
+ }
//
// VERIFY: SPIwrite24bits print diagnostic information
//cmdLine.serial().printf(" MOSI->"));
@@ -236,6 +247,11 @@
//
// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
//~ interrupts();
+ // Optional Diagnostic function to print SPI transactions
+ if (onSPIprint)
+ {
+ onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
+ }
//
// VERIFY: SPIwrite24bits print diagnostic information
//cmdLine.serial().printf(" MOSI->"));
@@ -322,6 +338,11 @@
//
// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
//~ interrupts();
+ // Optional Diagnostic function to print SPI transactions
+ if (onSPIprint)
+ {
+ onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
+ }
//
// VERIFY: SPIwrite24bits print diagnostic information
//cmdLine.serial().printf(" MOSI->"));
@@ -379,6 +400,7 @@
// CODE GENERATOR: class member function definitions
//----------------------------------------
+// Menu item '!'
// Initialize device
// @return 1 on success; 0 on failure
uint8_t MAX11410::Init(void)
@@ -407,38 +429,92 @@
// Linear map min and max endpoints
double MaxScaleVoltage = VRef; // voltage of maximum code 0xffffff
double MinScaleVoltage = 0.0; // voltage of minimum code 0x000
- const uint16_t FULL_SCALE_CODE_24BIT = 0xffffff;
- const uint16_t MaxCode = FULL_SCALE_CODE_24BIT;
- const uint16_t MinCode = 0x000;
+ const uint32_t FULL_SCALE_CODE_24BIT = 0xffffff;
+ const uint32_t MaxCode = FULL_SCALE_CODE_24BIT;
+ const uint32_t MinCode = 0x000;
double codeFraction = ((double)value_u24 - MinCode) / (MaxCode - MinCode + 1);
return MinScaleVoltage + ((MaxScaleVoltage - MinScaleVoltage) * codeFraction);
}
//----------------------------------------
-// Write an 8-bit MAX11410 register
+// Write a MAX11410 register.
+//
+// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0 indicating a write operation.
+//
+// MAX11410 register length can be determined by function RegSize.
//
-// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
+// For 8-bit register size:
+//
+// SPI 16-bit transfer
+//
+// SPI MOSI = 0aaa_aaaa_dddd_dddd
+//
+// SPI MISO = xxxx_xxxx_xxxx_xxxx
//
-// SPI 16-bit transfer
+// For 16-bit register size:
+//
+// SPI 24-bit or 32-bit transfer
+//
+// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
+//
+// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
//
-// SPI MOSI = 0aaa_aaaa_dddd_dddd
+// For 24-bit register size:
+//
+// SPI 32-bit transfer
//
-// SPI MISO = xxxx_xxxx_xxxx_xxxx
+// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
+//
+// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
//
// @return 1 on success; 0 on failure
-uint8_t MAX11410::Write_8bit(MAX11410_CMD_enum_t regAddress, uint8_t regData)
+uint8_t MAX11410::RegWrite(MAX11410_CMD_enum_t regAddress, uint32_t regData)
{
//----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Write_8bit..."
-
- //----------------------------------------
- // SPI write 16-bit mosiData16 and read misoData16
- int16_t mosiData16 = ((int16_t)regAddress << 8) | ((int16_t)regData);
- SPIoutputCS(0);
- SPIwrite16bits(mosiData16);
- SPIoutputCS(1);
+ // switch based on register address szie RegSize(regAddress)
+ regAddress = (MAX11410_CMD_enum_t)((regAddress &~ CMD_1aaa_aaaa_REGISTER_READ) & 0xFF);
+ switch(RegSize(regAddress))
+ {
+ case 8: // 8-bit register size
+ #warning "Not Verified Yet: MAX11410::RegWrite 8-bit SPIwrite16bits"
+ {
+ // SPI 16-bit transfer
+ // SPI MOSI = 0aaa_aaaa_dddd_dddd
+ // SPI MISO = xxxx_xxxx_xxxx_xxxx
+ int16_t mosiData16 = ((int16_t)regAddress << 8) | ((int16_t)regData & 0xFF);
+ SPIoutputCS(0);
+ SPIwrite16bits(mosiData16);
+ SPIoutputCS(1);
+ }
+ break;
+ case 16: // 16-bit register size
+ #warning "Not Verified Yet: MAX11410::RegWrite 16-bit SPIreadWrite32bits"
+ {
+ // SPI 24-bit or 32-bit transfer
+ // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
+ // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
+ // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_0000_0000
+ // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
+ int32_t mosiData32 = ((int32_t)regAddress << 24) | (((int32_t)regData & 0xFFFF) << 8);
+ SPIoutputCS(0);
+ SPIreadWrite32bits(mosiData32);
+ SPIoutputCS(1);
+ }
+ break;
+ case 24: // 24-bit register size
+ #warning "Not Verified Yet: MAX11410::RegWrite 24-bit SPIreadWrite32bits"
+ {
+ // SPI 32-bit transfer
+ // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
+ // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
+ int32_t mosiData32 = ((int32_t)regAddress << 24) | ((int32_t)regData & 0x00FFFFFF);
+ SPIoutputCS(0);
+ SPIreadWrite32bits(mosiData32);
+ SPIoutputCS(1);
+ }
+ break;
+ }
//----------------------------------------
// success
@@ -448,60 +524,86 @@
//----------------------------------------
// Read an 8-bit MAX11410 register
//
-// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
+// CMD_1aaa_aaaa_REGISTER_READ bit is set 1 indicating a read operation.
+//
+// MAX11410 register length can be determined by function RegSize.
+//
+// For 8-bit register size:
//
-// SPI 16-bit transfer
+// SPI 16-bit transfer
+//
+// SPI MOSI = 1aaa_aaaa_0000_0000
+//
+// SPI MISO = xxxx_xxxx_dddd_dddd
+//
+// For 16-bit register size:
//
-// SPI MOSI = 1aaa_aaaa_0000_0000
+// SPI 24-bit or 32-bit transfer
+//
+// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
+//
+// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
//
-// SPI MISO = xxxx_xxxx_dddd_dddd
+// For 24-bit register size:
+//
+// SPI 32-bit transfer
+//
+// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
+//
+// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
+//
//
// @return 1 on success; 0 on failure
-uint8_t MAX11410::Read_8bit(MAX11410_CMD_enum_t regAddress, uint8_t* ptrRegData)
+uint8_t MAX11410::RegRead(MAX11410_CMD_enum_t regAddress, uint32_t* ptrRegData)
{
//----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Read_8bit..."
-
- //----------------------------------------
- // SPI write 16-bit mosiData16 and read misoData16
- int16_t mosiData16 = ((CMD_1aaa_aaaa_REGISTER_READ | (int16_t)regAddress) << 8) | ((int16_t)0);
- SPIoutputCS(0);
- int16_t misoData16 = SPIreadWrite16bits(mosiData16);
- SPIoutputCS(1);
- (*ptrRegData) = (misoData16 & 0x00FF);
-
- //----------------------------------------
- // success
- return 1;
-}
-
-//----------------------------------------
-// Write a 16-bit MAX11410 register
-//
-// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
-//
-// SPI 24-bit transfer
-//
-// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
-//
-// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
-//
-// @return 1 on success; 0 on failure
-uint8_t MAX11410::Write_16bit(MAX11410_CMD_enum_t regAddress, uint16_t regData)
-{
-
- //----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Write_16bit..."
-
- //----------------------------------------
- // SPI write 32-bit (24-bit) mosiData32 and read misoData32
- int32_t mosiData32 = ((int32_t)regAddress << 8) | ((int32_t)regData);
- SPIoutputCS(0);
- int32_t misoData32 = SPIreadWrite32bits(mosiData32);
- SPIoutputCS(1);
+ // switch based on register address szie RegSize(regAddress)
+ regAddress = (MAX11410_CMD_enum_t)((regAddress &~ CMD_1aaa_aaaa_REGISTER_READ) & 0xFF);
+ switch(RegSize(regAddress))
+ {
+ case 8: // 8-bit register size
+ #warning "Not Verified Yet: MAX11410::RegRead 8-bit SPIreadWrite16bits"
+ {
+ // SPI 16-bit transfer
+ // SPI MOSI = 1aaa_aaaa_0000_0000
+ // SPI MISO = xxxx_xxxx_dddd_dddd
+ int16_t mosiData16 = ((CMD_1aaa_aaaa_REGISTER_READ | (int16_t)regAddress) << 8) | ((int16_t)0);
+ SPIoutputCS(0);
+ int16_t misoData16 = SPIreadWrite16bits(mosiData16);
+ SPIoutputCS(1);
+ (*ptrRegData) = (misoData16 & 0x00FF);
+ }
+ break;
+ case 16: // 16-bit register size
+ #warning "Not Verified Yet: MAX11410::RegRead 16-bit SPIreadWrite32bits"
+ {
+ // SPI 24-bit or 32-bit transfer
+ // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
+ // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
+ // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
+ // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_xxxx_xxxx
+ int32_t mosiData32 = ((CMD_1aaa_aaaa_REGISTER_READ | (int32_t)regAddress) << 24);
+ SPIoutputCS(0);
+ int32_t misoData32 = SPIreadWrite32bits(mosiData32);
+ SPIoutputCS(1);
+ (*ptrRegData) = ((misoData32 >> 8) & 0x00FFFF);
+ }
+ break;
+ case 24: // 24-bit register size
+ #warning "Not Verified Yet: MAX11410::RegRead 24-bit SPIreadWrite32bits"
+ {
+ // SPI 32-bit transfer
+ // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
+ // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
+ int32_t mosiData32 = ((CMD_1aaa_aaaa_REGISTER_READ | (int32_t)regAddress) << 24);
+ SPIoutputCS(0);
+ int32_t misoData32 = SPIreadWrite32bits(mosiData32);
+ SPIoutputCS(1);
+ (*ptrRegData) = (misoData32 & 0x00FFFFFF);
+ }
+ break;
+ }
//----------------------------------------
// success
@@ -509,98 +611,264 @@
}
//----------------------------------------
-// Read a 16-bit MAX11410 register
-//
-// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
-//
-// SPI 24-bit transfer
+// Return the size of a MAX11410 register
//
-// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
-//
-// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
-//
-// @return 1 on success; 0 on failure
-uint8_t MAX11410::Read_16bit(MAX11410_CMD_enum_t regAddress, uint16_t* ptrRegData)
+// @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
+uint8_t MAX11410::RegSize(MAX11410_CMD_enum_t regAddress)
{
//----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Read_16bit..."
-
- //----------------------------------------
- // SPI write 32-bit (24-bit) mosiData32 and read misoData32
- int32_t mosiData32 = ((CMD_1aaa_aaaa_REGISTER_READ | (int32_t)regAddress) << 16);
- SPIoutputCS(0);
- int32_t misoData32 = SPIreadWrite32bits(mosiData32);
- SPIoutputCS(1);
- (*ptrRegData) = (misoData32 & 0x00FFFF);
-
- //----------------------------------------
- // success
- return 1;
+ // switch based on register address value regAddress
+ regAddress = (MAX11410_CMD_enum_t)((regAddress &~ CMD_1aaa_aaaa_REGISTER_READ) & 0xFF);
+ switch(regAddress)
+ {
+ default:
+ return 0; // undefined register size
+ case CMD_r000_0000_xxxx_xxdd_PD:
+ case CMD_r000_0001_xddd_xxdd_CONV_START:
+ case CMD_r000_0010_xddd_dddd_SEQ_START:
+ case CMD_r000_0011_xxxx_xddd_CAL_START:
+ case CMD_r000_0100_dddd_xddd_GP0_CTRL:
+ case CMD_r000_0101_dddd_xddd_GP1_CTRL:
+ case CMD_r000_0110_xddd_xxdd_GP_CONV:
+ case CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR:
+ case CMD_r000_1000_x0dd_dddd_FILTER:
+ case CMD_r000_1001_dddd_dddd_CTRL:
+ case CMD_r000_1010_dddd_dddd_SOURCE:
+ case CMD_r000_1011_dddd_dddd_MUX_CTRL0:
+ case CMD_r000_1100_dddd_dddd_MUX_CTRL1:
+ case CMD_r000_1101_dddd_dddd_MUX_CTRL2:
+ case CMD_r000_1110_xxdd_xddd_PGA:
+ case CMD_r000_1111_dddd_dddd_WAIT_EXT:
+ case CMD_r001_0000_xxxx_xxxx_WAIT_START:
+ return 8; // 8-bit register size
+ case CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID:
+ case CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL:
+ case CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A:
+ case CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B:
+ case CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A:
+ case CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B:
+ case CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF:
+ case CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1:
+ case CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2:
+ case CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4:
+ case CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8:
+ case CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16:
+ case CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32:
+ case CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64:
+ case CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128:
+ case CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0:
+ case CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1:
+ case CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2:
+ case CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3:
+ case CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4:
+ case CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5:
+ case CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6:
+ case CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7:
+ case CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0:
+ case CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1:
+ case CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2:
+ case CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3:
+ case CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4:
+ case CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5:
+ case CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6:
+ case CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7:
+ case CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0:
+ case CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1:
+ case CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2:
+ case CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3:
+ case CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4:
+ case CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5:
+ case CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6:
+ case CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7:
+ case CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS:
+ case CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE:
+ return 24; // 24-bit register size
+ case CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0:
+ case CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1:
+ case CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2:
+ case CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3:
+ case CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4:
+ case CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5:
+ case CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6:
+ case CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7:
+ case CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8:
+ case CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9:
+ case CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10:
+ case CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11:
+ case CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12:
+ case CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13:
+ case CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14:
+ case CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15:
+ case CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16:
+ case CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17:
+ case CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18:
+ case CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19:
+ case CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20:
+ case CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21:
+ case CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22:
+ case CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23:
+ case CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24:
+ case CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25:
+ case CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26:
+ case CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27:
+ case CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28:
+ case CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29:
+ case CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30:
+ case CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31:
+ case CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32:
+ case CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33:
+ case CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34:
+ case CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35:
+ case CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36:
+ case CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37:
+ case CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38:
+ case CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39:
+ case CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40:
+ case CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41:
+ case CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42:
+ case CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43:
+ case CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44:
+ case CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45:
+ case CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46:
+ case CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47:
+ case CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48:
+ case CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49:
+ case CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50:
+ case CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51:
+ case CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52:
+ case CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR:
+ return 16; // 16-bit register size
+ }
}
//----------------------------------------
-// Write a 24-bit MAX11410 register
-//
-// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
-//
-// SPI 32-bit transfer
+// Return the name of a MAX11410 register
//
-// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
-//
-// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
-//
-// @return 1 on success; 0 on failure
-uint8_t MAX11410::Write_24bit(MAX11410_CMD_enum_t regAddress, uint32_t regData)
+// @return null-terminated constant C string containing register name or empty string
+const char* MAX11410::RegName(MAX11410_CMD_enum_t regAddress)
{
//----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Write_24bit..."
-
- //----------------------------------------
- // SPI write 32-bit mosiData32 and read misoData32
- int32_t mosiData32 = ((int32_t)regAddress << 24) | ((int32_t)regData & 0x00FFFFFF);
- SPIoutputCS(0);
- SPIreadWrite32bits(mosiData32);
- SPIoutputCS(1);
-
- //----------------------------------------
- // success
- return 1;
-}
-
-//----------------------------------------
-// Read a 24-bit MAX11410 register
-//
-// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
-//
-// SPI 32-bit transfer
-//
-// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
-//
-// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
-//
-// @return 1 on success; 0 on failure
-uint8_t MAX11410::Read_24bit(MAX11410_CMD_enum_t regAddress, uint32_t* ptrRegData)
-{
-
- //----------------------------------------
- // warning -- WIP work in progress
- #warning "Not Implemented Yet: MAX11410::Read_24bit..."
-
- //----------------------------------------
- // SPI write 32-bit mosiData32 and read misoData32
- int32_t mosiData32 = ((CMD_1aaa_aaaa_REGISTER_READ | (int32_t)regAddress) << 24);
- SPIoutputCS(0);
- int32_t misoData32 = SPIreadWrite32bits(mosiData32);
- SPIoutputCS(1);
- (*ptrRegData) = (misoData32 & 0x00FFFFFF);
-
- //----------------------------------------
- // success
- return 1;
+ // switch based on register address value regAddress
+ regAddress = (MAX11410_CMD_enum_t)((regAddress &~ CMD_1aaa_aaaa_REGISTER_READ) & 0xFF);
+ switch(regAddress)
+ {
+ default:
+ return ""; // undefined register
+ case CMD_r000_0000_xxxx_xxdd_PD: return "PD";
+ case CMD_r000_0001_xddd_xxdd_CONV_START: return "CONV_START";
+ case CMD_r000_0010_xddd_dddd_SEQ_START: return "SEQ_START";
+ case CMD_r000_0011_xxxx_xddd_CAL_START: return "CAL_START";
+ case CMD_r000_0100_dddd_xddd_GP0_CTRL: return "GP0_CTRL";
+ case CMD_r000_0101_dddd_xddd_GP1_CTRL: return "GP1_CTRL";
+ case CMD_r000_0110_xddd_xxdd_GP_CONV: return "GP_CONV";
+ case CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR: return "GP_SEQ_ADDR";
+ case CMD_r000_1000_x0dd_dddd_FILTER: return "FILTER";
+ case CMD_r000_1001_dddd_dddd_CTRL: return "CTRL";
+ case CMD_r000_1010_dddd_dddd_SOURCE: return "SOURCE";
+ case CMD_r000_1011_dddd_dddd_MUX_CTRL0: return "MUX_CTRL0";
+ case CMD_r000_1100_dddd_dddd_MUX_CTRL1: return "MUX_CTRL1";
+ case CMD_r000_1101_dddd_dddd_MUX_CTRL2: return "MUX_CTRL2";
+ case CMD_r000_1110_xxdd_xddd_PGA: return "PGA";
+ case CMD_r000_1111_dddd_dddd_WAIT_EXT: return "WAIT_EXT";
+ case CMD_r001_0000_xxxx_xxxx_WAIT_START: return "WAIT_START";
+ case CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID: return "PART_ID";
+ case CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL: return "SYSC_SEL";
+ case CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A: return "SYS_OFF_A";
+ case CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B: return "SYS_OFF_B";
+ case CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A: return "SYS_GAIN_A";
+ case CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B: return "SYS_GAIN_B";
+ case CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF: return "SELF_OFF";
+ case CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1: return "SELF_GAIN_1";
+ case CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2: return "SELF_GAIN_2";
+ case CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4: return "SELF_GAIN_4";
+ case CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8: return "SELF_GAIN_8";
+ case CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16: return "SELF_GAIN_16";
+ case CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32: return "SELF_GAIN_32";
+ case CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64: return "SELF_GAIN_64";
+ case CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128: return "SELF_GAIN_128";
+ case CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0: return "LTHRESH0";
+ case CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1: return "LTHRESH1";
+ case CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2: return "LTHRESH2";
+ case CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3: return "LTHRESH3";
+ case CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4: return "LTHRESH4";
+ case CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5: return "LTHRESH5";
+ case CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6: return "LTHRESH6";
+ case CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7: return "LTHRESH7";
+ case CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0: return "UTHRESH0";
+ case CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1: return "UTHRESH1";
+ case CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2: return "UTHRESH2";
+ case CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3: return "UTHRESH3";
+ case CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4: return "UTHRESH4";
+ case CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5: return "UTHRESH5";
+ case CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6: return "UTHRESH6";
+ case CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7: return "UTHRESH7";
+ case CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0: return "DATA0";
+ case CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1: return "DATA1";
+ case CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2: return "DATA2";
+ case CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3: return "DATA3";
+ case CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4: return "DATA4";
+ case CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5: return "DATA5";
+ case CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6: return "DATA6";
+ case CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7: return "DATA7";
+ case CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS: return "STATUS";
+ case CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE: return "STATUS_IE";
+ case CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0: return "UC_0";
+ case CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1: return "UC_1";
+ case CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2: return "UC_2";
+ case CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3: return "UC_3";
+ case CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4: return "UC_4";
+ case CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5: return "UC_5";
+ case CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6: return "UC_6";
+ case CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7: return "UC_7";
+ case CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8: return "UC_8";
+ case CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9: return "UC_9";
+ case CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10: return "UC_10";
+ case CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11: return "UC_11";
+ case CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12: return "UC_12";
+ case CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13: return "UC_13";
+ case CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14: return "UC_14";
+ case CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15: return "UC_15";
+ case CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16: return "UC_16";
+ case CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17: return "UC_17";
+ case CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18: return "UC_18";
+ case CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19: return "UC_19";
+ case CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20: return "UC_20";
+ case CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21: return "UC_21";
+ case CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22: return "UC_22";
+ case CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23: return "UC_23";
+ case CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24: return "UC_24";
+ case CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25: return "UC_25";
+ case CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26: return "UC_26";
+ case CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27: return "UC_27";
+ case CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28: return "UC_28";
+ case CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29: return "UC_29";
+ case CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30: return "UC_30";
+ case CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31: return "UC_31";
+ case CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32: return "UC_32";
+ case CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33: return "UC_33";
+ case CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34: return "UC_34";
+ case CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35: return "UC_35";
+ case CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36: return "UC_36";
+ case CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37: return "UC_37";
+ case CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38: return "UC_38";
+ case CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39: return "UC_39";
+ case CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40: return "UC_40";
+ case CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41: return "UC_41";
+ case CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42: return "UC_42";
+ case CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43: return "UC_43";
+ case CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44: return "UC_44";
+ case CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45: return "UC_45";
+ case CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46: return "UC_46";
+ case CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47: return "UC_47";
+ case CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48: return "UC_48";
+ case CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49: return "UC_49";
+ case CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50: return "UC_50";
+ case CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51: return "UC_51";
+ case CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52: return "UC_52";
+ case CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR: return "UCADDR";
+ }
}
//----------------------------------------
@@ -632,39 +900,66 @@
//----------------------------------------
// write8 0x00 PD = 0x03 (Reset Registers; enter Standby mode)
- Write_8bit(CMD_r000_0000_xxxx_xxdd_PD, PD_11_Reset);
+ RegWrite(CMD_r000_0000_xxxx_xxdd_PD, PD_11_Reset);
//----------------------------------------
// write8 0x00 PD = 0x00 (NOP)
- Write_8bit(CMD_r000_0000_xxxx_xxdd_PD, PD_00_Normal);
+ RegWrite(CMD_r000_0000_xxxx_xxdd_PD, PD_00_Normal);
//----------------------------------------
// write8 0x08 FILTER = 0x34 to select RATE_0100, LINEF_11_SINC4 60SPS (given CONV_TYPE_01_Continuous)
- Write_8bit(CMD_r000_1000_x0dd_dddd_FILTER, 0x34);
+ RegWrite(CMD_r000_1000_x0dd_dddd_FILTER, 0x34);
//----------------------------------------
// write8 0x0B MUX_CTRL0 = 0x0A to select AINP=AIN0 and AINN=GND
- Write_8bit(CMD_r000_1011_dddd_dddd_MUX_CTRL0, 0x0A);
+ RegWrite(CMD_r000_1011_dddd_dddd_MUX_CTRL0, 0x0A);
//----------------------------------------
// write8 0x09 CTRL = 0x02 to select reference REF2P/REF2N; or CTRL = 0x1A to select reference REF2P/REF2N with reference input buffers enabled; Data Format = Bipolar 2's Complement
- Write_8bit(CMD_r000_1001_dddd_dddd_CTRL, 0x02);
+ RegWrite(CMD_r000_1001_dddd_dddd_CTRL, 0x02);
//----------------------------------------
// write8 0x0E PGA = 0x00 to select input path = Buffers, digital gain = 1V/V
- Write_8bit(CMD_r000_1110_xxdd_xddd_PGA, 0x00);
+ RegWrite(CMD_r000_1110_xxdd_xddd_PGA, 0x00);
//----------------------------------------
// write8 0x01 CONV_START = 0x01 to set Conversion Mode = Continuous
- Write_8bit(CMD_r000_0001_xddd_xxdd_CONV_START, 0x01);
+ RegWrite(CMD_r000_0001_xddd_xxdd_CONV_START, 0x01);
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+
+ //----------------------------------------
+ // success
+ return 1;
+}
+
+//----------------------------------------
+// Measure ADC channels in sequence from AIN0 to channelNumber_0_9.
+// @param[in] channel_hi = channel high side
+// @param[in] channel_lo = channel low side
+// @post AINcode[index]: measurement
+//
+// @return 1 on success; 0 on failure
+uint8_t MAX11410::_TODO_MAX11410_Read_All_Voltages_(MAX11410_AINP_SEL_enum_t channel_hi, MAX11410_AINN_SEL_enum_t channel_lo)
+{
+
+ //----------------------------------------
+ // warning -- WIP work in progress
+ #warning "Not Tested Yet: MAX11410::_TODO_MAX11410_Read_All_Voltages_..."
+
+ //----------------------------------------
+ // read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+
+ //----------------------------------------
+ // read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success
@@ -690,11 +985,11 @@
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success
@@ -720,11 +1015,11 @@
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success
@@ -751,11 +1046,11 @@
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success
@@ -782,11 +1077,11 @@
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success
@@ -814,11 +1109,11 @@
//----------------------------------------
// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
- Read_24bit(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
+ RegRead(CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS, &status);
//----------------------------------------
// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
- Read_24bit(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
+ RegRead(CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0, &data0);
//----------------------------------------
// success